VeriLadder-QwenCoder-7B

Qwen/Qwen2.5-Coder-7B-Instruct fine-tuned to write Verilog from a natural-language specification. It is trained on the refined specifications of VeriLadder, whose every specification is verified by a formal equivalence check to determine its circuit.

Files

• Top level: the merged model (bf16), ready for transformers or vLLM.
• lora/: the LoRA adapter alone (rank 16, alpha 32, all attention and MLP projections), to apply on top of Qwen/Qwen2.5-Coder-7B-Instruct.

Usage

from transformers import AutoModelForCausalLM, AutoTokenizer

name = "anonymous-review-0000/VeriLadder-QwenCoder-7B"
tok = AutoTokenizer.from_pretrained(name)
model = AutoModelForCausalLM.from_pretrained(name, dtype="bfloat16", device_map="auto")

spec = "A 4-bit counter with a synchronous active-high reset."
messages = [
    {"role": "system", "content": "You are a Verilog RTL designer that only writes code using correct Verilog syntax."},
    {"role": "user", "content": spec + "\n\nWrite the Verilog code for this design."},
]
ids = tok.apply_chat_template(messages, add_generation_prompt=True, return_tensors="pt").to(model.device)
out = model.generate(ids, max_new_tokens=3072, do_sample=True, temperature=0.2, top_p=0.95)
print(tok.decode(out[0, ids.shape[1]:], skip_special_tokens=True))

With the adapter instead of the merged weights:

from peft import PeftModel
base = AutoModelForCausalLM.from_pretrained("Qwen/Qwen2.5-Coder-7B-Instruct", dtype="bfloat16", device_map="auto")
model = PeftModel.from_pretrained(base, "anonymous-review-0000/VeriLadder-QwenCoder-7B", subfolder="lora")

Results

Functional pass@1 / pass@5 (%), five samples per problem.

Model	VerilogEval v2	RTLLM v2	VeriLadder-Bench
Qwen2.5-Coder-7B-Instruct	31.7 / 47.3	35.0 / 50.0	61.7 / 79.5
VeriLadder-QwenCoder-7B	50.0 / 61.5	45.2 / 54.0	83.1 / 92.3

Training

Supervised fine-tuning with LoRA (rank 16, alpha 32, three epochs) on VeriLadder.