anonymous-review-0000/VeriLadder-QwenCoder-7B
Text Generation • 8B • Updated
Datasets:
id int64 0 26.3k | accepted bool 2
classes | refined_specification stringlengths 183 5.12k | n_rounds int64 1 3 | accepted_round float64 0 2 ⌀ | rebuilt_from_original_instruction bool 2
classes | rebuilt_from_instruction_plus_interface bool 2
classes | verified_rebuild_code stringlengths 85 6.49k ⌀ |
|---|---|---|---|---|---|---|---|
3,081 | false | Overview: top_module is a combinational system combining a one-bit full adder, selection of a four-bit slice from a 1024-bit input, and conditional output logic.
Interface: input unsigned in[1023:0]; input unsigned sel[7:0]; input unsigned a, b, cin; output unsigned cout, sum; output unsigned out[3:0].
Behavior: At all... | 2 | null | false | false | null |
9,705 | true | Overview: Implement a combinational 32-bit adder that adds A and B.
Interface: Module ripple_carry_adder. A and B are unsigned 32-bit inputs. C is an unsigned 32-bit output.
Behavior: For every input pair, C is the low 32 bits of the unsigned sum of A and B; any carry out of bit 31 is discarded.
| 1 | 0 | true | true | module ripple_carry_adder (
input wire [31:0] A,
input wire [31:0] B,
output wire [31:0] C
);
wire [32:0] carry;
assign carry[0] = 1'b0;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : gen_fa
wire s_i;
assign s_i = A[i] ^ B[i] ^ carry[i];
... |
6,980 | true | Overview: add_sub is a combinational arithmetic circuit. It adds two 5-bit unsigned operands formed by concatenating the complement of C[0] with A and with B; it does not select subtraction when C[0] is high.
Interface: A and B are unsigned 4-bit inputs; C is an unsigned 4-bit input. O is an unsigned 4-bit output, and ... | 1 | 0 | false | false | module add_sub (
input wire [3:0] A,
input wire [3:0] B,
input wire [3:0] C,
output wire [3:0] O,
output wire CO,
output wire OV
);
wire [4:0] x = {~C[0], A};
wire [4:0] y = {~C[0], B};
wire [4:0] sum = x + y;
assign O = sum[3:0];
assign CO = sum[4];
... |
15,458 | true | Overview: top_module accepts two 32-bit binary inputs and has a 32-bit output. It includes the stated bitwise AND and byte-reordering behavior, but does not produce a uniquely defined result because the output is multiply driven and one driver is self-referential.
Interface: top_module has input a, unsigned 32 bits; in... | 1 | 0 | false | true | // Note: this follows the specification literally. The output net has two
// continuous drivers, and the second reads the output itself, which forms a
// combinational loop. The result is not a well-defined function. Conflicting
// bits resolve to X in simulation, and synthesis tools will typically reject
// or warn ab... |
2,995 | true | Overview: The alu module is a combinational block. It produces an XOR result X and a 32-bit truncated sum Y using A and either B or its bitwise complement, as selected by BI. It does not implement operation selection among the originally listed ALU functions.
Interface: A and B are signed 32-bit inputs; CI and BI are 1... | 1 | 0 | false | true | module alu #(
parameter WIDTH = 32
) (
input wire signed [WIDTH-1:0] A,
input wire signed [WIDTH-1:0] B,
input wire CI,
input wire BI,
output wire signed [WIDTH-1:0] X,
output wire signed [WIDTH-1:0] Y,
output wire CO
);
w... |
17,294 | true | Overview: top_module combines two 8-bit registered values and outputs their bitwise OR. The first value loads data or rotates; the second synchronously resets or rotates.
Interface: top_module has input clk (1-bit, unsigned), input reset (1-bit, unsigned), input load (1-bit, unsigned), input data_in_1 (8-bit, unsigned)... | 1 | 0 | false | false | module top_module (
input clk,
input reset,
input load,
input [7:0] data_in_1,
input [7:0] data_in_2,
output [7:0] functional_output
);
reg [7:0] shift_reg_1;
reg [7:0] shift_reg_2;
always @(posedge clk) begin
if (l... |
25,460 | true | Overview: top_module is combinational logic with 3-bit inputs a and b and two 1-bit select inputs. It provides logical-OR and input-inversion behavior, but out_always is undriven and out_or_bitwise has multiple drivers, so those outputs do not have fully specified single-driver behavior.
Interface: Inputs: a, unsigned ... | 1 | 0 | false | true | module top_module (
input wire [2:0] a,
input wire [2:0] b,
input wire sel_b1,
input wire sel_b2,
output wire out_always,
output wire [2:0] out_or_bitwise,
output wire out_or_logical,
output wire [5:0] out_not
);
// Undriven output per specification (high... |
11,470 | true | Overview: Combinational arithmetic/logic operation selection on A and B. The behavior sheet also describes an apparent conditional addition using in[0] and in[1]; however, because out is assigned in two combinational procedural blocks and one reads and rewrites out, the resulting output is not uniquely defined by ordin... | 1 | 0 | false | false | // Single-driver, purely combinational implementation.
// The behavior sheet's multiple-driver/feedback conflict on 'out' is resolved
// by computing out in one always block with no self-reference:
// - ctrl=011 uses A+B+in[0]+in[1] (zero-extended, truncated to 8 bits).
// - ctrl=110/111 with B==0 drives 0 (the spe... |
2,153 | true | Overview: A 4-bit binary counter with parallel load.
Interface: Module binary_counter has input clock (1-bit, unsigned), input load (1-bit, unsigned), input data_in (4-bit, unsigned), and output count (4-bit, unsigned, registered).
Behavior: On each rising edge of clock, if load is high, count takes the value of data_i... | 1 | 0 | true | true | module binary_counter (
input wire clock,
input wire load,
input wire [3:0] data_in,
output reg [3:0] count
);
always @(posedge clock) begin
if (load)
count <= data_in;
else
count <= count + 4'd1;
end
endmodule
|
17,444 | true | Overview: four_bit_adder is a combinational 4-bit adder with carry-in and carry-out.
Interface: a and b are unsigned 4-bit inputs; cin is a 1-bit input. sum is an unsigned 4-bit output; cout is a 1-bit output.
Behavior: The design evaluates a + b + c combinationally, where c[0] is cin and c[3:1] are undriven and theref... | 1 | 0 | true | true | module four_bit_adder (
input wire [3:0] a,
input wire [3:0] b,
input wire cin,
output wire [3:0] sum,
output wire cout
);
wire [4:0] result;
assign result = {1'b0, a} + {1'b0, b} + {4'b0, cin};
assign sum = result[3:0];
assign cout = result[4];
endmodule
|
16,120 | true | Overview: `vga_controller` generates horizontal and vertical counters and registered VGA sync and blank outputs from the input pixel clock. The counter cycles are 1056 horizontal counts per line and 628 lines per frame.
Interface: `vclock` is a 1-bit input. `hcount` is an unsigned 11-bit output; `vcount` is an unsigned... | 1 | 0 | false | false | module vga_controller (
input wire vclock,
output reg [10:0] hcount,
output reg [9:0] vcount,
output reg vsync,
output reg hsync,
output reg blank
);
// Assumed definition: the spec does not define hblank. This uses the
// horizontal active-blank inter... |
8,498 | true | Overview: The bcd_counter_pipeline module has a 16-bit unsigned register q that increments by one on each rising clock edge when reset is low. Despite the original BCD-counter intent, the specified behavior is binary counting modulo 65536, not four-digit BCD counting.
Interface: clk: 1-bit input, unsigned. reset: 1-bit... | 1 | 0 | false | false | module bcd_counter_pipeline (
input wire clk,
input wire reset,
output reg [2:0] ena,
output reg [15:0] q
);
always @(posedge clk) begin
if (reset) begin
q <= 16'd0;
ena <= 3'd0;
end else begin
q <= q + 16'd1;
en... |
16,213 | true | Overview: `predictor_2bit` is a branch-prediction module with registered counter-related state and a combinational prediction output. Its behavior is the state-dependent behavior specified below; it does not implement the increment/decrement behavior described in the original request.
Interface: `clock`: input, unsigne... | 1 | 0 | false | false | module predictor_2bit (
input wire clock,
input wire reset,
input wire enable,
input wire taken_i,
output reg prediction_o
);
reg [1:0] counter;
reg [1:0] next_counter;
reg [1:0] next_state;
// Registered state update
always @(posedge clock) begin
if (reset) begin
... |
22,916 | true | Overview: Span4Mux_v is a combinational 4-to-1 multiplexer that selects one bit from I.
Interface: I is an unsigned 4-bit input; S is an unsigned 2-bit input; O is an unsigned 1-bit output.
Behavior: O equals I[0] when S is 2'b00, I[1] when S is 2'b01, I[2] when S is 2'b10, and I[3] when S is 2'b11. If no listed equali... | 1 | 0 | false | true | module Span4Mux_v (
input wire [3:0] I,
input wire [1:0] S,
output reg O
);
always @(*) begin
case (S)
2'b00: O = I[0];
2'b01: O = I[1];
2'b10: O = I[2];
2'b11: O = I[3];
default: O = 1'bx;
endcase
end
end... |
25,048 | true | Overview: mux4to1 is a combinational 4:1 multiplexer.
Interface: input data[3:0] (4 bits, unsigned); input sel[1:0] (2 bits, unsigned); output out (1 bit, unsigned). No parameters or external modules.
Behavior: With no latency, out equals data[0] when sel is 00, data[1] when sel is 01, data[2] when sel is 10, and data[... | 1 | 0 | false | true | module mux4to1 (
input wire [3:0] data,
input wire [1:0] sel,
output wire out
);
assign out = data[sel];
endmodule
|
25,303 | true | Overview: The axi4_lite_memory module provides a read-data interface. It always indicates address readiness, asserts read-data valid when axi_arvalid and axi_rready are both high, and captures a selected memory word under that same condition.
Interface: Inputs: clk (1-bit unsigned), rst (1-bit unsigned), axi_araddr (32... | 1 | 0 | false | false | module axi4_lite_memory (
input wire clk,
input wire rst,
input wire [31:0] axi_araddr,
input wire axi_arvalid,
input wire axi_rready,
output wire axi_arready,
output reg [31:0] axi_rdata,
output wire axi_rvalid
);
// 1024-word memory,... |
12,192 | true | Overview: RegisterAnd stores a 4-bit input value when enabled, synchronously clears it when disabled, and provides the AND of the stored bits.
Interface: EN is a 1-bit input; D is a 4-bit unsigned input; CLK is a 1-bit input; Q_AND is a 1-bit unsigned output. Module name: RegisterAnd.
Behavior: On each rising edge of C... | 1 | 0 | false | true | module RegisterAnd (
input wire EN,
input wire [3:0] D,
input wire CLK,
output wire Q_AND
);
reg [3:0] stored;
always @(posedge CLK) begin
if (!EN)
stored <= 4'b0000;
else
stored <= D;
end
assign Q_AND = &stored;
endmodule
|
5,284 | true | Overview: max32 compares the current 32-bit input with a stored value and updates that value only when the input is greater under an unsigned comparison. The output continuously reflects the stored value; this is not a signed maximum over a specified input set.
Interface: Module max32. in1 is a 32-bit input. out1 is a ... | 1 | 0 | true | true | module max32 (
input wire [31:0] in1,
output wire [31:0] out1
);
reg [31:0] max_val;
// Input-change-sensitive latch: updates only when in1 > max_val (unsigned).
// No reset; max_val is undefined until the first qualifying input change.
always @(in1) begin
if (in1 > max_val)
... |
19,188 | true | Overview: adder_4bit registers the low four bits of the sum of A, B, and Cin.\nInterface: Module adder_4bit. Inputs: A, unsigned 4-bit; B, unsigned 4-bit; Cin, unsigned 1-bit; Clk, unsigned 1-bit. Outputs: S, unsigned 4-bit; Cout, unsigned 1-bit.\nBehavior: On each rising edge of Clk, S takes the low four bits of A + B... | 1 | 0 | true | true | module adder_4bit (
input wire [3:0] A,
input wire [3:0] B,
input wire Cin,
input wire Clk,
output reg [3:0] S,
output wire Cout
);
// Full 5-bit sum so the carry bit is explicitly defined.
// The spec leaves Cout undefined; driving it with the true
// carry-o... |
6,154 | true | Overview: The sky130_fd_sc_lp__a32o module outputs the OR of a three-input AND and a two-input AND.
Interface: output X (1-bit, unsigned); inputs A1, A2, A3, B1, and B2 (each 1-bit, unsigned).
Behavior: X is 1 when all of A1, A2, and A3 are 1, or when both B1 and B2 are 1. In all other input cases, X is 0. The output i... | 1 | 0 | true | true | module sky130_fd_sc_lp__a32o (
output X,
input A1,
input A2,
input A3,
input B1,
input B2
);
assign X = (A1 & A2 & A3) | (B1 & B2);
endmodule
|
1,647 | true | Overview: four_to_one_mux is a combinational 4-to-1 multiplexer.
Interface: Parameter WIDTH defaults to 4 and sets the width of in0, in1, in2, in3, and out. Inputs: in0, in1, in2, and in3 are unsigned WIDTH-bit data inputs; sel is an unsigned 2-bit input. Output: out is an unsigned WIDTH-bit output.
Behavior: out equal... | 1 | 0 | true | true | module four_to_one_mux #(
parameter WIDTH = 4
) (
input wire [WIDTH-1:0] in0,
input wire [WIDTH-1:0] in1,
input wire [WIDTH-1:0] in2,
input wire [WIDTH-1:0] in3,
input wire [1:0] sel,
output reg [WIDTH-1:0] out
);
always @(*) begin
case (sel)
2'b00: out... |
13,761 | true | Overview: `binary_adder` is combinational logic. Its observed port behavior does not implement a well-defined 2-bit binary addition result: S1 has a defined Boolean value, while S2 has multiple drivers and combinational feedback.
Interface: Inputs: A1_N, A2_N, B1, and B2, each unsigned 1 bit. Outputs: S1 and S2, each u... | 1 | 0 | false | false | module binary_adder (
input wire A1_N,
input wire A2_N,
input wire B1,
input wire B2,
output wire S1,
output wire S2
);
// Internal XOR of the A1_N/B1 pair
wire x1 = A1_N ^ B1;
// S1 is always the XOR of A1_N and B1
assign S1 = x1;
// S2 has two drivers, as specified:
... |
5,588 | true | Overview: MUX4 is combinational logic. When E is high, Y is the bitwise OR of A, B, C, and D. When E is low, Y is formed from four conditional terms.
Interface: A, B, C, D, S0, S1, and E are unsigned 1-bit inputs. Y is an unsigned 1-bit output.
Behavior: For E=1, Y equals A OR B OR C OR D. For E=0, Y1 is A when S1S0=10... | 1 | 0 | true | true | module MUX4 (
input wire A,
input wire B,
input wire C,
input wire D,
input wire S0,
input wire S1,
input wire E,
output wire Y
);
// Conditional terms for E = 0; X when the select does not match.
wire Y1 = ({S1, S0} == 2'b10) ? A : 1'bx;
wire Y2 = ({S1, S0} == 2'b00)... |
16,685 | true | Overview: ring_counter is a 4-bit ring counter. On each rising edge of clk, it synchronously resets to zero when reset is high; otherwise, it rotates its bits left by one position.
Interface: clk and reset are 1-bit inputs. bit_0, bit_1, bit_2, and bit_3 are unsigned 4-bit outputs. There are no parameters.
Behavior: Af... | 1 | 0 | false | true | module ring_counter (
input wire clk,
input wire reset,
output wire [3:0] bit_0,
output wire [3:0] bit_1,
output wire [3:0] bit_2,
output wire [3:0] bit_3
);
reg [3:0] counter;
always @(posedge clk) begin
if (reset)
counter <= 4'b0000;
else
... |
19,294 | true | Overview: Combine an 8-bit register, an input-change-triggered edge detector, and a bitwise AND. The register captures d; the detector produces a rising-transition mask from in; the final output is the bitwise AND of q and anyedge.
Interface: Module top_module. Inputs: clk (1-bit unsigned), reset (1-bit unsigned), d (8... | 1 | 0 | false | false | module top_module (
input clk,
input reset,
input [7:0] d,
input [7:0] in,
output reg [7:0] q,
output reg [7:0] anyedge,
output [7:0] final_output
);
reg [7:0] prev_in;
// Synchronous register with active-high reset to 8'h34 (priority over d)
always @(posedg... |
796 | true | Overview: The curr_source_sink module combinationally routes the positive difference between i_in and i_set to either the source output or the sink output when enabled. Both outputs are zero when disabled.
Interface: enable is a 1-bit input. i_set and i_in are unsigned 32-bit inputs. i_out and i_sunk are unsigned 32-bi... | 1 | 0 | false | true | module curr_source_sink (
input wire enable,
input wire [31:0] i_set,
input wire [31:0] i_in,
output wire [31:0] i_out,
output wire [31:0] i_sunk
);
wire in_lt_set = (i_in < i_set);
wire [31:0] diff_sunk = i_set - i_in;
wire [31:0] diff_out = i_in - i_set;
assign ... |
834 | true | Overview: fifo_buffer provides registered read data and occupancy status for a FIFO-like buffer. Its behavior is as specified below; it does not implement an eight-entry FIFO ordering because its pointers address only two entries.
Interface: clk: input, 1-bit unsigned. fifo_wdata: input, 8-bit unsigned. fifo_wr: input,... | 1 | 0 | false | false | module fifo_buffer (
input wire clk,
input wire [7:0] fifo_wdata,
input wire fifo_wr,
output wire fifo_FF,
output reg [7:0] r_dat,
output wire wfifo_empty,
output reg [5:0] wfifo_used
);
// Storage: declared with eight entries, but pointers only address 0 an... |
14,525 | true | Overview: bit_counter combinationally counts the 1 bits in a 64-bit input.
Interface: Module bit_counter has an unsigned 64-bit input in_word and an unsigned 6-bit output bits.
Behavior: When all bits of in_word are known 0 or 1, bits is the number of 1 bits in in_word, from 0 through 64 inclusive. If any in_word bit i... | 1 | 0 | true | false | // Combinational population count of a 64-bit word.
// Note: the spec allows results up to 64, but a 6-bit output can only
// represent 0..63. The all-ones case (64) wraps to 0 in bits[5:0].
// An X/Z bit in in_word propagates X into the sum, as the spec permits.
module bit_counter (
input wire [63:0] in_word,
... |
2,734 | true | Overview: adder combinationally outputs the 32-bit sum of A and B.
Interface: A and B are unsigned 32-bit inputs. sum is an unsigned 32-bit output. Parameter INITVAL has default value 0 and does not affect any output.
Behavior: For every pair of input values, sum is their unsigned sum modulo 2^32 (the low 32 bits of th... | 1 | 0 | false | true | module adder #(
parameter INITVAL = 0
) (
input wire [31:0] A,
input wire [31:0] B,
output wire [31:0] sum
);
assign sum = A + B;
endmodule
|
12,653 | true | Overview: top_module combines an 8-bit shift register with an 8-bit one-hot value decoded from vec. The output is the shift-register value for select=000; for all other select values it is the bitwise OR of the shift-register value and the decoded value.
Interface: clk: 1-bit unsigned input; reset: 1-bit unsigned input... | 1 | 0 | false | false | module top_module (
input wire clk,
input wire reset,
input wire [7:0] d,
input wire [2:0] select,
input wire [2:0] vec,
output wire [7:0] q
);
reg [7:0] shift_reg;
wire [7:0] output_vec;
// Synchronous-reset shift register.
// The spec's {shift_reg[0], d[7:0]... |
5,323 | true | Overview: fifo1 is a one-word FIFO. It accepts a push when empty and a pull when full. Its data output continuously reflects the stored word.
Interface: Inputs: clk_i (1-bit), rst_i (1-bit), data_i (32-bit unsigned), push_i (1-bit), pull_i (1-bit). Outputs: data_o (32-bit unsigned), full_o (1-bit), empty_o (1-bit). Par... | 1 | 0 | false | false | module fifo1 #(
parameter g_width = 32
) (
input clk_i,
input rst_i,
input [g_width-1:0] data_i,
input push_i,
input pull_i,
output [g_width-1:0] data_o,
output reg full_o,
output reg ... |
20,145 | true | Overview: motor_speed_measurement provides a memory-mapped register interface and count-related logic driven by the frequent input and PWM clock. The state does not advance during normal operation after reset, so the completion state is not reached through the described normal transitions.
Interface: Inputs: rsi_MRST_r... | 1 | 0 | false | false | module motor_speed_measurement (
input wire rsi_MRST_reset,
input wire csi_MCLK_clk,
input wire [31:0] avs_ctrl_writedata,
input wire [3:0] avs_ctrl_byteenable,
input wire [2:0] avs_ctrl_address,
input wire avs_ctrl_write,
input wire avs_ctrl_read,
in... |
7,233 | false | Overview: top_module maintains a 4-bit counter in counter mode and captures the XOR-reduction parity of DATA_IN in parity mode. Each output is high-impedance outside its respective mode.
Interface: input DATA_IN[3:0] (4-bit unsigned); input LOAD (1-bit); input CLK (1-bit); input RESET (1-bit); input select (1-bit); out... | 3 | null | false | false | null |
19,663 | false | Overview: Implement top_module with the clocked behavior described below.
Interface: Inputs: r[2:0] (unsigned), L (1 bit), clk (1 bit). Output: q[2:0] (unsigned).
Behavior: On each rising edge of clk when L is high, the two internal state bits load r[0] and r[1], respectively. On that same edge, q loads the values of t... | 3 | null | false | false | null |
6,035 | false | Overview: POR generates a registered reset output from the vdd rising-edge behavior described below.
Interface: Module POR has input vdd, 1-bit unsigned, and output rst, 1-bit unsigned. Parameter t defaults to 100 and is the counter-comparison threshold.
Behavior: On each rising edge of vdd, if the prior sampled vdd va... | 3 | null | false | false | null |
4,163 | false | Overview: top_module stores an 8-bit input and a 4-bit counter on rising clock edges, then combinationally selects a value and adds it to the stored input.
Interface: clk: input, 1-bit; reset: input, 1-bit; d: input, 8-bit unsigned; select: input, 2-bit unsigned; q: output, 12-bit unsigned.
Behavior: On each rising edg... | 3 | null | false | false | null |
19,591 | false | Overview: shift_decoder contains an asynchronously reset 4-bit shift-left register and combinational decoder/selection logic. The selected decoder bit is presented as an 8-bit output.
Interface: module shift_decoder; input clk (1-bit unsigned), input reset (1-bit unsigned), input parallel_load (1-bit unsigned), input s... | 3 | null | false | false | null |
16,076 | false | Overview: top_module combines two input bytes into a 16-bit unsigned value, adds a registered counter value, and presents the result at out.
Interface: clk: input, 1 bit, unsigned; reset: input, 1 bit, unsigned; in_hi: input, 8 bits, unsigned; in_lo: input, 8 bits, unsigned; out: output, 16 bits, unsigned.
Behavior: Th... | 3 | null | false | false | null |
9,902 | false | Overview: A 1-bit-wide FIFO datapath with registered read output and registered empty/full flags, using 5-bit read and write pointers. The storage has 32 address positions. The interface parameters are `abits` (default 5) and `dbits` (default 1); the verified ports are 1 bit wide.
Interface: Module `fifo`. Inputs: `res... | 3 | null | false | false | null |
8,247 | true | Overview: Module t is a registered 41-bit output whose portions update independently on clock enables, with asynchronous active-high reset.
Interface: Inputs: clk_sys (1-bit unsigned), _0_t (1-bit unsigned), taa (1-bit unsigned), tab (1-bit unsigned), trb (1-bit unsigned), clockta (1-bit unsigned), clocktb (1-bit unsig... | 1 | 0 | false | false | module t (
input wire clk_sys,
input wire _0_t,
input wire taa,
input wire tab,
input wire trb,
input wire clockta,
input wire clocktb,
input wire clocktc,
input wire t_1_d,
input wire [0:39] k,
... |
6,266 | false | Overview: BinaryAdder combinationally computes the 5-bit output C from unsigned inputs A[3:0], B[3:0], and Cin[0].
Interface: Module BinaryAdder. Inputs: unsigned A[3:0], B[3:0], and Cin[0]. Output: unsigned C[4:0].
Behavior: For every input combination, C is determined by the following equations, evaluated as simultan... | 3 | null | false | false | null |
2,622 | true | Overview: A combinational 4-to-1 multiplexer selects one of A, B, C, or D.
Interface: Module mux_4to1. Inputs: A, B, C, D, S0, and S1, each unsigned 1-bit. Output: Y, unsigned 1-bit.
Behavior: Y equals C when S1=0 and S0=0; A when S1=0 and S0=1; B when S1=1 and S0=0; and D when S1=1 and S0=1. These four cases cover all... | 1 | 0 | false | false | module mux_4to1 (
input wire A,
input wire B,
input wire C,
input wire D,
input wire S0,
input wire S1,
output wire Y
);
assign Y = S1 ? (S0 ? D : B) : (S0 ? A : C);
endmodule
|
3,465 | true | Overview: FIFO_image_filter is a shift-register buffer for image-column data. It accepts new data on enabled rising clock edges and provides an addressed buffer entry at q.
Interface: Parameters are ADDR_WIDTH=2, DATA_WIDTH=12, and DEPTH=3. Inputs: clk (1-bit), data (12-bit unsigned), ce (1-bit), and a (2-bit unsigned)... | 1 | 0 | false | true | module FIFO_image_filter #(
parameter ADDR_WIDTH = 2,
parameter DATA_WIDTH = 12,
parameter DEPTH = 3
) (
input wire clk,
input wire [DATA_WIDTH-1:0] data,
input wire ce,
input wire [ADDR_WIDTH-1:0] a,
output reg [DATA_WIDTH-1:0] q
);
reg [DATA_... |
25,081 | true | Overview: A simple arithmetic circuit that subtracts d_in from a temporary value and registers the result.
Interface: Module arithmetic_circuit. Inputs: clock (1-bit), c_in (1-bit), d_in (1-bit). Output: out1 (1-bit, unsigned). No parameters.
Behavior: On each rising edge of clock, out1 captures the low bit of the valu... | 1 | 0 | false | false | module arithmetic_circuit (
input wire clock,
input wire c_in,
input wire d_in,
output reg out1
);
reg temp;
always @(posedge clock) begin
out1 <= temp ^ d_in;
temp <= c_in ^ d_in;
end
endmodule
|
9,875 | true | Overview: The eight_bit_adder computes an 8-bit bitwise sum from a and b using a carry chain initialized by cin, and exposes the final carry-chain bit as cout. Carry propagation after bit 0 is undefined because the full-adder carry logic has conflicting and undriven signals.
Interface: Module eight_bit_adder. Unsigned ... | 1 | 0 | false | true | module full_adder (
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
module eight_bit_adder #(
parameter WIDTH = 8
) (
input wire [WIDTH-1:0] a,
input wire [W... |
10,750 | true | Overview: The five_to_one module combinationally produces X from A1, A2, A3, B1, and B2. X is high for either specified input condition and low otherwise.
Interface: Module five_to_one. Single-bit inputs: A1, A2, A3, B1, B2, VPB, VPWR, VGND, and VNB. Single-bit output: X. All ports are unsigned.
Behavior: X is 1 when A... | 1 | 0 | false | false | module five_to_one (
input wire A1,
input wire A2,
input wire A3,
input wire B1,
input wire B2,
input wire VPB,
input wire VPWR,
input wire VGND,
input wire VNB,
output wire X
);
wire a_all_one = A1 & A2 & A3;
wire a_any_zero = ~(A1 & A2 & A3);
wire b_low ... |
21,830 | true | Overview: MemoryArbiter is a combinational block whose single-bit access output is asserted only for one exact request pattern; it does not provide per-request grants or priority arbitration.
Interface: Module MemoryArbiter. Input req: unsigned 4-bit vector. Output access: unsigned 1-bit signal. No other ports.
Behavio... | 1 | 0 | false | false | module MemoryArbiter (
input wire [3:0] req,
output wire access
);
assign access = (req == 4'b0001);
endmodule
|
1,777 | true | Overview: memory_arbiter is a combinational memory-arbitration block. Its implemented behavior does not guarantee exclusive grants or fair round-robin arbitration.
Interface: Module memory_arbiter. Parameter n defaults to 4 and denotes the request/grant vector width. Input: req, 4-bit unsigned. Output: gnt, 4-bit unsig... | 1 | 0 | false | true | module memory_arbiter #(
parameter n = 4
) (
input [3:0] req,
output [3:0] gnt
);
// Latch-held state: no reset, no defined initial value.
reg [3:0] grant_queue;
reg [3:0] round_robin_counter;
// Combinational grant output: bitwise AND of req and grant_queue.
assign gnt = req & grant_... |
13,122 | true | Overview: `accumulator` produces the population count of its input: the number of input bits that are 1.
Interface: Parameter `n` defaults to 4 and determines the input width and number of bits summed. The module has an unsigned `in` input of width 4 and an unsigned `out` output of width 5. No other ports are present.
... | 1 | 0 | false | true | module accumulator #(
parameter n = 4
) (
input [n-1:0] in,
output reg [n:0] out
);
integer i;
always @(*) begin
out = {(n+1){1'b0}};
for (i = 0; i < n; i = i + 1) begin
out = out + {{n{1'b0}}, in[i]};
end
end
endmodule
|
642 | true | Overview: delay_module delays each 32-bit input sample A by 10 rising edges of clk.
Interface: input clk (1 bit), input rst (1 bit), input A (32-bit unsigned), output X (32-bit unsigned).
Behavior: On each rising edge of clk when rst is low, X updates to the A value sampled 10 rising edges earlier. X holds its current ... | 1 | 0 | false | true | module delay_module (
input wire clk,
input wire rst,
input wire [31:0] A,
output reg [31:0] X
);
// 9 pipeline stages plus the registered output X form a 10-stage delay.
reg [31:0] sr [0:8];
integer i;
always @(posedge clk) begin
if (rst) begin
fo... |
2,128 | true | Overview: Module mux is a combinational 4-to-1 multiplexer with an enable input.
Interface: Inputs: in0, in1, in2, and in3 are unsigned 8-bit data inputs; sel is an unsigned 2-bit select input; en is a 1-bit enable input. Output: out is an unsigned 8-bit output.
Behavior: When en is 1, out equals in0 for sel=2'b00, in1... | 1 | 0 | true | true | module mux (
input wire [7:0] in0,
input wire [7:0] in1,
input wire [7:0] in2,
input wire [7:0] in3,
input wire [1:0] sel,
input wire en,
output reg [7:0] out
);
always @(*) begin
if (en) begin
case (sel)
2'b00: out = in0;
... |
10,121 | true | Overview: The data_inverter module registers data_in on each rising edge of clk and registers its bitwise complement on each falling edge.
Interface: clk is a 1-bit input. data_in is an unsigned 8-bit input. data_out is an unsigned 8-bit output. data_out_inv is an unsigned 8-bit output. No parameters are defined.
Behav... | 1 | 0 | true | true | module data_inverter (
input wire clk,
input wire [7:0] data_in,
output reg [7:0] data_out,
output reg [7:0] data_out_inv
);
always @(posedge clk) begin
data_out <= data_in;
end
always @(negedge clk) begin
data_out_inv <= ~data_in;
end
endmodule
|
18,272 | true | Overview: CDR is a reference-clock-driven data sampler and edge-responsive clock toggle with a registered data output.
Interface: Module CDR. Inputs: data_in, 1-bit unsigned; clk_ref, 1-bit unsigned. Outputs: clk_out, 1-bit unsigned; data_out, 1-bit unsigned.
Behavior: On each rising edge of clk_ref, the design samples... | 1 | 0 | false | false | module CDR (
input wire data_in,
input wire clk_ref,
output reg clk_out,
output reg data_out
);
// Registered delayed copy of data_in, sampled on clk_ref
reg data_in_delayed;
// Two-bit edge-detection state
reg [1:0] edge_state;
// Combinational difference, reduced modulo 4 by... |
10,993 | true | Overview: Combinational module and_or_gate. Its output is the logical AND of a and b; c does not affect the output.
Interface: and_or_gate has 1-bit unsigned inputs a, b, and c, and a 1-bit unsigned output y.
Behavior: y is 1 exactly when a=1 and b=1. For every other combination of a and b, y is 0. This behavior is ide... | 1 | 0 | false | false | module and_or_gate (
input wire a,
input wire b,
input wire c,
output wire y
);
assign y = a & b;
endmodule
|
22,718 | true | Overview: matrix_multiplier samples start and updates internal count, indices, and an indexed c element on rising clock edges. It does not implement a complete 4x4 matrix multiplication. The result output exposes only c[3][3].
Interface: clk: input, 1-bit unsigned; rst: input, 1-bit unsigned; start: input, 1-bit unsign... | 1 | 0 | false | false | module matrix_multiplier (
input wire clk,
input wire rst,
input wire start,
input wire [15:0] matrix_a,
input wire [15:0] matrix_b,
output wire [15:0] result,
output reg done
);
reg [3:0] count;
reg [3:0] i;
reg [3:0] j;
reg [15:0] c... |
22,053 | true | Overview: A combinational 4-to-1 multiplexer named mux4to1 selects one bit from in according to sel.
Interface: input [3:0] in; input [1:0] sel; output out, 1 bit and unsigned. No parameters.
Behavior: out equals in[0] when sel is 2'b00, in[1] when sel is 2'b01, in[2] when sel is 2'b10, and in[3] when sel is 2'b11. The... | 1 | 0 | true | true | module mux4to1 (
input [3:0] in,
input [1:0] sel,
output out
);
assign out = in[sel];
endmodule
|
13,003 | true | Overview: four_bit_adder is a combinational 4-bit adder. It adds A, B, and C_in as unsigned binary values. The original description's claim of selectable two's-complement signed operation is not supported by the interface or the verified behavior.
Interface: A and B are unsigned 4-bit inputs; C_in is an unsigned 1-bit ... | 1 | 0 | true | true | module four_bit_adder (
input wire [3:0] A,
input wire [3:0] B,
input wire C_in,
output wire [3:0] S,
output wire C_out
);
wire [4:0] sum;
assign sum = {1'b0, A} + {1'b0, B} + {4'b0, C_in};
assign S = sum[3:0];
assign C_out = sum[4];
endmodule
|
12,795 | true | Overview: axis_histogram sequentially drives a BRAM interface to zero-fill its address range and then processes accepted AXI-stream data by selecting an address and producing incremented BRAM write data. It does not contain an internal BRAM.
Interface: axis_histogram has input aclk (1-bit unsigned), input aresetn (1-bi... | 1 | 0 | false | false | module axis_histogram #(
parameter AXIS_TDATA_WIDTH = 16,
parameter BRAM_ADDR_WIDTH = 14,
parameter BRAM_DATA_WIDTH = 32
)(
input wire aclk,
input wire aresetn,
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDT... |
28 | true | Overview: Combinational signed multiply-add module.
Interface: Module hls_contrast_streibs_DSP48_6. Inputs: in0, 8 bits; in1, 23 bits; in2, 32 bits. Output: dout, 32 bits, unsigned.
Behavior: At all times, interpret in0, in1, and in2 as signed two's-complement values. Sign-extend in0 to 18 bits, in1 to 25 bits, and in2... | 1 | 0 | false | false | module hls_contrast_streibs_DSP48_6 (
input wire [7:0] in0,
input wire [22:0] in1,
input wire [31:0] in2,
output wire [31:0] dout
);
// Sign-extended operands
wire signed [17:0] a = {{10{in0[7]}}, in0};
wire signed [24:0] b = {{2{in1[22]}}, in1};
wire signed [47:0] c = {{16{in... |
2,513 | false | Overview: top_module selects between a combinational output derived from the lower three bits of in_vec and a path with zero data outputs, four-bit input parity, and the shift register's serial bit.
Interface: input clk (1 bit, unsigned); input reset (1 bit, unsigned); input in_vec (4 bits, unsigned); input select (1 b... | 3 | null | false | false | null |
9,465 | true | Overview: aludec combinationally decodes aluop and, when aluop is 0010, funct to produce alucontrol, signd, and multseld.
Interface: Input funct is an unsigned 6-bit signal. Input aluop is an unsigned 4-bit signal. Outputs alucontrol, signd, and multseld are unsigned signals of 3, 1, and 1 bits, respectively.
Behavior:... | 1 | 0 | true | true | module aludec (
input wire [5:0] funct,
input wire [3:0] aluop,
output reg [2:0] alucontrol,
output reg signd,
output reg multseld
);
always @(*) begin
case (aluop)
4'b0000: begin
alucontrol = 3'b010;
signd = 1'b1;
... |
12,110 | true | Overview: top_module exposes the high and low bytes of a 16-bit input and has an 8-bit output, out_sum, with conflicting drivers. The out_sum value is therefore not uniquely defined by the design.
Interface: clk is a 1-bit input; in is a 16-bit input; out_hi, out_lo, and out_sum are 8-bit outputs. All data ports are un... | 1 | 0 | false | false | // Resolution of the conflicting out_sum specification:
// out_sum is driven by exactly one source (the combinational byte-sum module),
// so the port has a single, well-defined driver. The registered 3-bit sequencer
// described in the sheet is kept as internal state and is not connected to the
// out_sum net, which a... |
10,407 | true | Overview: PushButton_Debouncer synchronizes the asynchronous PB input and qualifies changes by counting while the synchronized input differs from PB_state.
Interface: Module PushButton_Debouncer. Inputs: clk (1-bit unsigned), PB (1-bit unsigned). Outputs: PB_state (1-bit unsigned), PB_down (1-bit unsigned), PB_up (1-bi... | 1 | 0 | true | true | module PushButton_Debouncer #(
parameter COUNTER_WIDTH = 16
) (
input wire clk,
input wire PB,
output reg PB_state,
output reg PB_down,
output reg PB_up
);
// Two-stage input synchronizer
reg sync_ff1;
reg sync_ff2;
// Debounce counter
reg [COUNTER_WIDTH-1:0] PB_cnt;
... |
10,559 | true | Overview: LED_DISPLAY is a combinational LED output selector. It applies the operation selected by SW to ALU_F, with ZF forcing the entire output off and OF controlling the leftmost LED bit otherwise.
Interface: Module LED_DISPLAY. Inputs: OF, unsigned 1 bit; ZF, unsigned 1 bit; SW, unsigned 3 bits; ALU_F, unsigned 32 ... | 1 | 0 | true | true | module LED_DISPLAY (
input wire OF,
input wire ZF,
input wire [2:0] SW,
input wire [31:0] ALU_F,
output reg [7:0] LED
);
reg [31:0] sel;
always @(*) begin
case (SW)
3'b000: sel = ALU_F;
3'b001: sel = ~ALU_F;
3'b010: sel = ALU... |
6,459 | true | Overview: ddr_interface provides the specified DDR/fixed-I/O pass-through interface and four counter-derived output bits.
Interface: inout DDR_addr[14:0], DDR_ba[2:0], DDR_cas_n, DDR_ck_n, DDR_ck_p, DDR_cke, DDR_cs_n, DDR_dm[3:0], DDR_dq[31:0], DDR_dqs_n[3:0], DDR_dqs_p[3:0], DDR_odt, DDR_ras_n, DDR_reset_n, DDR_we_n, ... | 1 | 0 | false | true | module ddr_interface (
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_... |
25,258 | true | Overview: debug_bridge passes the CPU data-interface signals through and produces a registered break output plus debug event outputs.
Interface: Module debug_bridge. Inputs: clk (1-bit unsigned), reset_n (1-bit unsigned), debugack (1-bit unsigned), d_read (1-bit unsigned), d_write (1-bit unsigned), d_waitrequest (1-bit... | 1 | 0 | true | true | module debug_bridge (
input wire clk,
input wire reset_n,
input wire debugack,
input wire d_read,
input wire d_write,
input wire d_waitrequest,
input wire [25:0] d_address,
input wire [31:0] av_ld_data_aligned_filtered,
input wire [3... |
25,254 | false | Overview: DBLC_3_64 is a combinational module that maps GIN to GOUT and selects the source of POUT according to PHI.
Interface: Module DBLC_3_64. Inputs: PIN, unsigned 63 bits; GIN, unsigned 65 bits; PHI, unsigned 1 bit. Outputs: POUT, unsigned 61 bits; GOUT, unsigned 65 bits.
Behavior: GOUT is a direct pass-through of... | 3 | null | false | false | null |
2,158 | false | Overview: top_module computes a 32-bit combinational result from a and b, forms a 9-bit even-parity vector from in, and ANDs that vector with the zero-extended upper eight bits of the result.
Interface: Inputs (all unsigned): clk (1 bit), reset (1 bit), in (8 bits), a (32 bits), b (32 bits). Outputs (unsigned): sum (32... | 3 | null | false | false | null |
14,082 | false | Overview: binary_adder combinationally adds two 4-bit unsigned inputs and a one-bit carry-in.
Interface: Inputs: A, unsigned 4-bit; B, unsigned 4-bit; CIN, unsigned 1-bit. Outputs: SUM, unsigned 4-bit; COUT, unsigned 1-bit; OVF, unsigned 1-bit.
Behavior: For every input combination, define SUM as the low 4 bits of the ... | 3 | null | false | false | null |
350 | false | Overview: ds8dac1 is a clocked digital-to-analog conversion element that produces DACout from an accumulated 10-bit value.
Interface: input clk, 1-bit unsigned; input DACin, 8-bit unsigned; output DACout, 1-bit unsigned and registered.
Behavior: Treat SigmaLatch as an unsigned 10-bit value. DeltaB is the 10-bit value w... | 3 | null | false | false | null |
16,650 | false | Overview: Synchronous receiver block that samples and processes rx_in and presents a registered decoded value on data_out. This specification describes the bluetooth_receiver top module only; it does not specify Bluetooth radio transmission or a transmitter.
Interface: Module bluetooth_receiver. Inputs: clk, 1-bit unsi... | 3 | null | false | false | null |
9,886 | false | Overview: calc_res samples inputs on rising clk edges and updates registered resolution outputs according to sampled sync and data-enable edge conditions.
Interface: Inputs: rst_n (1-bit unsigned), clk (1-bit unsigned), de (1-bit unsigned), hsync (1-bit unsigned), vsync (1-bit unsigned). Outputs: resX (16-bit unsigned)... | 3 | null | false | false | null |
6,424 | false | Overview: accu buffers accepted 8-bit inputs and accumulates the buffered value into a 10-bit result when its 3-bit count is 7. The result wraps modulo 1024.
Interface: clk: input, 1-bit unsigned. rst_n: input, 1-bit unsigned. data_in: input, 8-bit unsigned. valid_a: input, 1-bit unsigned. ready_b: input, 1-bit unsigne... | 3 | null | false | false | null |
3,021 | false | Overview: glitch_filter samples a 1-bit input and produces a registered 1-bit output according to the counter condition below.
Interface: Module glitch_filter. Inputs: clk, 1-bit unsigned; in, 1-bit unsigned. Output: out, 1-bit unsigned. Parameter n defaults to 10 and is used as the counter width and comparison thresho... | 3 | null | false | false | null |
1,770 | false | Overview: quadrature_decoder derives combinational count-enable and direction outputs from delayed quadrature inputs and provides a one-hot SPEED output based on an internal total.
Interface: CLOCK: input, 1-bit unsigned. RESET: input, 1-bit unsigned. A: input, 1-bit unsigned. B: input, 1-bit unsigned. COUNT_ENABLE: ou... | 3 | null | false | false | null |
1,705 | false | Overview: top_module shifts d[0] through eight serial flip-flops. A 3-bit counter cycles through the eight stage indices, and q registers the selected stage bit, zero-extended to 8 bits.
Interface: top_module has input clk (1-bit unsigned), input reset (1-bit unsigned), input d (8-bit unsigned), and output q (8-bit uns... | 3 | null | false | false | null |
25,760 | false | Overview: register_decoder produces three outputs associated with register-access readiness and CRT read enables. The implementation's decode logic is partially unresolved: some referenced signals are undeclared or unassigned, and one output is undriven.
Interface: Inputs: h_hclk (1-bit unsigned), h_reset_n (1-bit unsi... | 3 | null | false | false | null |
4,897 | false | Overview: xor_shift_register advances an 8-bit shift register under control of a 3-bit counter and periodically captures the bitwise XOR of the shift-register value and input d.
Interface: Module xor_shift_register. Inputs: clk (1-bit, unsigned), d (8-bit, unsigned). Output: q (8-bit, unsigned, registered). There is no... | 3 | null | false | false | null |
7,181 | false | Overview: The up_down_counter module provides a combinational three-bit up/down value derived from an internal register stage. Q is not the stored counter state; a second sampled register stage does not affect the output.
Interface: Module up_down_counter. Inputs: RST, 1-bit unsigned; UP_DOWN, 1-bit unsigned. Output: Q... | 3 | null | false | false | null |
18,663 | false | Overview: four_bit_adder is a clocked four-function arithmetic and logic unit. On each rising edge of clk, it registers results selected by Sel.
Interface: Inputs: A[3:0] unsigned, B[3:0] unsigned, Cin[0] unsigned, Sel[1:0] unsigned, clk[0]. Outputs: Sum[3:0] unsigned, Cout[0] unsigned, Z[3:0] unsigned.
Behavior: On a ... | 3 | null | false | false | null |
9,853 | false | Overview: fib_sequence_gen updates an internal 8-bit shift value under a three-state control cycle and presents selected values on fib. The behavior is defined by the rules below; it does not assert a conventional Fibonacci sequence.
Interface: clk is a 1-bit input. reset is a 1-bit input. fib is an unsigned 8-bit outp... | 3 | null | false | false | null |
3,268 | false | Overview: The shift_register module has a registered 8-bit output B and four internal 8-bit registers reg1 through reg4.
Interface: clk is a 1-bit input; A is an unsigned 8-bit input; L is a 1-bit input; B is an unsigned 8-bit output. No parameters.
Behavior: On each rising edge of clk, update B and all four internal r... | 3 | null | false | false | null |
24,944 | true | Overview: The bitwise_or_and_adder module forms a 17-bit combinational output from four 4-bit slices of its inputs, using OR or addition with derived carry terms. It does not compute a full-width OR result or a conventional full-width sum.
Interface: `bitwise_or_and_adder` has unsigned input `in1[15:0]`, unsigned input... | 1 | 0 | false | true | // Assumed definitions for the unspecified carry terms (the spec names them
// but does not define them):
// c4 = carry generated by the lowest nibble pair (bit 3 generate)
// carry_pred_1 = carry generated by the bit-7 pair, fed into the bits [11:8] slice
// carry_pred_2 = carry generated by the bit-11 ... |
6,042 | false | Overview: AllignAdder registers the idle input and, when not idle, aligns the operand with the smaller signed adjusted exponent while passing the other operand through. It also registers the `sout_Special` input unchanged.
Interface: Module `AllignAdder`. Inputs: `idle_Special` (1-bit unsigned), `cout_Special` (36-bit ... | 3 | null | false | false | null |
14,326 | false | Overview: top_module stores input data on a load clock edge or a selected rotation of the stored word otherwise, then combinationally ORs the stored word with a selected rotation of that word.
Interface: Inputs: data, unsigned 16-bit; load, 1-bit; shift, unsigned 4-bit; clk, 1-bit. Output: out, unsigned 16-bit.
Behavio... | 3 | null | false | false | null |
22,180 | false | Overview: top_module byte-reverses a 32-bit input, combines it with a mux-selected value using bitwise OR, and presents a one-bit result.
Interface: input in is 32 bits; inputs a, b, sel_b1, and sel_b2 are each 1 bit; output out_always is 1 bit. All ports are unsigned.
Behavior: The byte-reversed value has bytes in rev... | 3 | null | false | false | null |
24,120 | true | Overview: top_module generates a 16-bit one-hot output from an internal square-wave state.
Interface: clk is a 1-bit input; reset is a 1-bit input; q is an unsigned 16-bit output.
Behavior: q is combinational with zero-cycle latency. When reset is low and the internal state out is 0, q is 16'b0000000000001000. When res... | 2 | 1 | false | false | module top_module (
input wire clk,
input wire reset,
output wire [15:0] q
);
reg [31:0] counter;
reg out;
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 32'd0;
out <= 1'b0;
end else begin
... |
4,937 | false | Overview: top_module provides combinational outputs from inputs a, b, c, and select.
Interface: input a: 1-bit unsigned; input b: 1-bit unsigned; input c: 1-bit unsigned; input select: 1-bit unsigned; output out_assign: 1-bit unsigned; output out_alwaysblock: 1-bit unsigned; output final_output: 1-bit unsigned.
Behavio... | 3 | null | false | false | null |
5,467 | false | Overview: AddressGenerator updates a 16-bit address from lower- and upper-byte state. Updates are enabled by ce. Carry reports the combinational carry-out of the AL-side addition.
Interface: AddressGenerator has inputs clk (1-bit), ce (1-bit), Operation (5-bit), MuxCtrl (2-bit), DataBus (8-bit), T (8-bit), X (8-bit), a... | 3 | null | false | false | null |
3,024 | false | Overview: A combinational 4-to-1 multiplexer with an enable. It selects one bit from MUX_INPUTS and presents that value zero-extended to 32 bits; when disabled, the output is zero.
Interface: Module mux_4_1_enable. Inputs: MUX_INPUTS, unsigned 4-bit; MUX_SELECT, unsigned 2-bit; EN, unsigned 1-bit. Output: MUX_OUTPUT, u... | 3 | null | false | false | null |
19,502 | false | Overview: top_module registers the 8-bit input and combinationally reports whether the registered input has no set bit in common with a selected OR result.
Interface: module top_module has input clk (1-bit unsigned), reset (1-bit unsigned), in (8-bit unsigned), a (3-bit unsigned), b (3-bit unsigned), select (1-bit unsi... | 3 | null | false | false | null |
16,767 | false | Overview: DisplayPortReceiver implements the described receiver-side main-link interface at its available ports. It captures rx into the most-significant output bit only at the specified count/lane condition; it does not specify a transmitter.
Interface: module DisplayPortReceiver; input rx (1-bit unsigned), input clk ... | 3 | null | false | false | null |
18,876 | false | Overview: top_module produces the modulo-256 sum of an 8-bit shift-register value and a zero-extended 4-bit up/down-counter value.
Interface: input clk (1-bit unsigned), input rst (1-bit unsigned), input up_down (1-bit unsigned), input data_in (8-bit unsigned), output output_sum (8-bit unsigned).
Behavior: output_sum i... | 3 | null | false | false | null |
13,383 | false | Overview: The control module combinationally generates processor control signals from the 6-bit op input.
Interface: Module name: control. Input: op, unsigned 6-bit. Outputs: alu_op, unsigned 2-bit; regDst, aluSrc, memToReg, regWrite, memRead, memWrite, and branch, each unsigned 1-bit.
Behavior: All outputs are combina... | 3 | null | false | false | null |
24,518 | false | Overview: top_module produces a 1-bit combinational output from two 32-bit inputs.
Interface: in1: unsigned 32-bit input; in2: unsigned 32-bit input; out: unsigned 1-bit output.
Behavior: At all times, out is the complement of the AND of the NAND results for the corresponding input bits at positions 7 and 15. Specifica... | 3 | null | false | false | null |
4,511 | false | Overview: top_module registers the input byte and parity-related state, samples input a for rising transitions, and registers a qualified result on out.
Interface: top_module has input clk (1-bit, unsigned), input reset (1-bit, unsigned), input in (8-bit, unsigned), input a (1-bit, unsigned), and output out (1-bit, uns... | 3 | null | false | false | null |
17,868 | false | Overview: top_module stores a 4-bit value and provides a 4-bit output containing one selected stored bit. An internal 2-bit counter selects the bit.
Interface: input clk (1-bit unsigned), input areset (1-bit unsigned), input load (1-bit unsigned), input ena (1-bit unsigned), input data (4-bit unsigned), output q (4-bit... | 3 | null | false | false | null |
363 | false | Overview: A combinational 32-bit ALU selects an arithmetic, logical, comparison, shift, immediate, or zero result according to aluc.
Interface: Module alu. Inputs: a, 32-bit unsigned; b, 32-bit unsigned; aluc, 5-bit unsigned. Output: result, 32-bit unsigned.
Behavior: For aluc 0 or 1, result is the low 32 bits of a+b. ... | 3 | null | false | false | null |
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VeriLadder
VeriLadder is a Verilog dataset whose labels follow the order in which a hardware engineer checks a design, in five levels. Every accept or reject decision is made by an EDA tool (Yosys synthesis or a formal equivalence checker); LLM agents only write and revise specifications.
| Level | What it adds | File(s) | Rows |
|---|---|---|---|
| 1 | Synthesis label, failure family and category, critical warnings, post-synthesis metrics | level1/level1_rtlcoder.parquet, level1/level1_pyranet.parquet |
26,076 + 690,551 = 716,627 |
| 2 | Four grades of the original instruction (consistency, unambiguity, completeness, verifiability) with evidence, gaps and flags | level2/level2_grades.parquet |
14,385 designs (14,292 graded) |
| 3 | Refined specification verified to determine the circuit, and the refinement trajectory | level3/level3_refined.parquet, level3/level3_trajectories.parquet |
14,292 designs (11,247 accepted); 20,966 refined specifications over all rounds (11,247 accepted + 9,719 failed) |
| 4 | Paraphrases of the accepted refined specifications | level4/level4_paraphrases.parquet |
33,317 (32,393 verified) |
| 5 | One-fact variants (variant specification S' and variant code D') | level5/level5_variants.parquet |
9,306 (8,397 verified) |
| – | VeriLadder-Bench: 300 held-out problems with specification, reference code and evaluation prompt | VeriLadder-Bench/veriladder_bench.parquet |
300 |
| – | Full pipeline record of every design processed at Levels 2–5, with every builder attempt, log and counterexample | pipeline_records/ |
14,385 (8 Parquet shards, 130 MB) |
At Level 3, a design whose refined specification fails the round trip gets a new one, written from the counterexample, so a design can have several specifications. level3_refined.parquet keeps one row per design (its final specification), and level3_trajectories.parquet keeps every specification written, one row each: the 11,247 accepted specifications and the 9,719 that failed, 20,966 in total.
Each level has its own README with every attribute. The level files are compact extracts of pipeline_records/, which keeps everything the pipeline produced. counts.json lists every count above, as produced by the export
script, next to the value reported in the paper.
Joining the files
- Every file of Levels 2–5 uses
id, the line index of the design in the RTLCoder dataset (level1_rtlcoder.parquethas the sameid, together with the original instruction and code). - Level 2 has one row per design processed at Levels 2–5. Level 3 has one row per design that was graded and reached the round trip, and one row per refined specification in the trajectory file. Levels 4 and 5 contain only designs whose refined specification was accepted at Level 3.
- PyraNet designs (Level 1 only) are identified by
hf_index, the row index in the Hugging Face datasetbnadimi/PyraNet-Verilog, and byid, the position in the sampled subset of 692,000 rows.
import pandas as pd
rtl = pd.read_parquet("level1/level1_rtlcoder.parquet")
spec = pd.read_parquet("level3/level3_refined.parquet")
accepted = spec[spec.accepted].merge(rtl[["id", "instruction", "code"]], on="id")
License
The dataset is released under CC BY-NC-SA 4.0.
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Models trained or fine-tuned on anonymous-review-0000/VeriLadder
