Qwen3.8-Flash-Next AutoRound 3 bpw + MTP for Ampere

This is a public, mixed-precision AutoRound checkpoint of Qwen/Qwen3.8-Flash-Next, pinned to revision de4b8e4d43b917e7706784d8bb445c9af86a3540. It is intended for NVIDIA Ampere GPUs with a 64 GiB GPU-resident weight budget.

Qwen3.8-Flash-Next is an experimental preview model. Runtime support is also experimental; read the compatibility section before downloading.

Quantization

  • 48 routed-expert banks: depth-stratified 2.998 effective bpw (scale/zero-point overhead included): W3A16G128 on layers 0-11 and 36-47, W2A16G64 on layers 12-35.
  • Backbone QSA/GDN major linear projections: W8A16G128.
  • Routers, shared experts, hyperconnection/control paths, PLE projections, vision tower, embeddings, and LM head: BF16.
  • MTP experts: W4A16G128 symmetric RTN; MTP QSA and dense projections: W8A16G128 symmetric RTN.
  • Backbone optimization: calibrated AutoRound SignRoundV2, 50 iterations, using 128 sequences of 512 tokens from NeelNanda/pile-10k (seed 42).
  • Reproducibility: dataset selection and sampling were seeded, but PyTorch reported nondeterministic CUDA memory-efficient attention backward, so the calibration is not claimed to be bit-for-bit reproducible.
  • Packing: native AutoRound auto_round:auto_gptq mixed-bit format.

The effective packed qweight inventory by bit width is: {"2": 36864, "3": 36864, "4": 1536, "8": 175}.

Measured storage topology

  • GPU-resident weight tensors: 47.11 GiB.
  • Host-offloaded PLE n-gram table: 95.37 GiB (128 tensors).
  • MTP tensors are included in the checkpoint and counted in the GPU-resident figure.
  • Safetensor shards: 13; indexed tensors: 227702.

The 64 GiB figure is a weight budget, not a claim that every context length fits. KV cache and runtime workspaces require additional HBM. The 95 GiB n-gram table must remain in host memory; provision ample system RAM.

Runtime compatibility

At publication time, stock vLLM cannot serve this exact checkpoint topology. Two required changes are still open:

In addition, vLLM issue #53908 tracks auxiliary-device offload for the PLE table; PR #53896 currently allocates that embedding through the normal GPU embedding path. Combining the two PRs alone is therefore insufficient for this BF16 PLE checkpoint on one GPU.

The intended fallback is Transformers AutoModelForMultimodalLM with the layer-1 PLE embedding lookup on CPU and its projections plus the packed language backbone on CUDA:0. This pinned Transformers fallback performs ordinary autoregressive decoding and does not instantiate the included MTP speculative head. Provision at least 200 GiB of host RAM.

Validation

Validation details will be added.

License

Qwen Community License 1.0, inherited from the base model. Review the included LICENSE file and the base model card for its conditions and limitations.

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