Datasets:
instruction large_stringlengths 3 4.74k | module_header large_stringlengths 9 4.88k | code large_stringlengths 1.04k 19.7k | hash large_stringlengths 64 64 |
|---|---|---|---|
Create a non-functional Verilog stub module named sky130_fd_sc_ls__dlclkp that represents a clock-gating standard cell, intended only as an empty black-box definition for graphical symbol generation rather than simulation. Wrap the entire file in an include guard using the macro SKY130_FD_SC_LS__DLCLKP_SYMBOL_V, set th... | module sky130_fd_sc_ls__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
); | /**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | f757a81cf8352a294d8021c7336587bea4a79ae947788547fb0216a282fcf090 |
Create a Verilog wrapper module named `dcfifo_32in_32out_32kb` for an Artix-7 design that instantiates the Xilinx FIFO Generator as a dual-clock asynchronous FIFO using block RAM. The FIFO should store 1024 words of 32-bit data, with a 32-bit write-data input `din` and 32-bit read-data output `dout`, independent write ... | module dcfifo_32in_32out_32kb (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count
); | // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... | 3497f82894d8cc6eaf5addbdc772d3ea1918f9679a47dc939db742740c858fa3 |
Design a Verilog wrapper module named `ovl_always_on_edge_wrapped` that adapts an existing `ovl_always_on_edge` assertion-checker module into a simple single-bit alarm interface. The wrapper has six inputs—`clk`, `rst`, `enable`, `sampling_event`, `test_expr`, and `prevConfigInvalid`—and one output, `out`, all single-b... | module ovl_always_on_edge_wrapped(
clk,
rst,
enable,
sampling_event,
test_expr,
prevConfigInvalid,
out
); | /*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at... | 1b3a1c09972222f8e355419c9c8a37ac99fa1591ec41d9500d91ec494029e700 |
Write a Verilog testbench module named `test` that exercises a memory controller module called `mem_ctl` (included from "../mem_ctl.v"). Instantiate `mem_ctl` as `mem1`, connecting its ports in this order: read_n, write_n, ce_n, address_bus, data_bus, mem_data, mem_address, ceh_n, ce2, we_n, and oe_n. Declare active-lo... | module test; |
`include "../mem_ctl.v"
module test;
reg read_n,
write_n,
ce_n,
clk;
reg [6:0] address_bus;
wire [7:0] data_bus;
wire [7:0] mem_data;
wire [16:0] mem_address;
wire ceh_n;
wire ce2;
wire we_n;
wire oe_n;
mem_ctl mem1(r... | 7e184e8f81b13cc7394aba77a4c7fd856e68e66e5fffa767ea87eca0608b8934 |
Create a Verilog module named `pll` that serves as a black-box (empty-body) wrapper for an Altera ALTPLL megafunction targeting a Cyclone IV E device, to be filled in by the Quartus megafunction flow and simulated against the altera_mf library. The module should expose exactly two ports: a single clock input `inclk0` a... | module pll (
inclk0,
c0); | // megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// =============================================... | feb1f92bc5650d34552871483cb4028e87be56341c2057150895c565a4f7e7b4 |
Design a Verilog module named LCD_Controller that acts as a write-only host-to-LCD command/data bridge for a standard character LCD. The module should have a host-side interface consisting of an 8-bit data input iDATA, a register-select input iRS, a start input iStart, a done output oDone, a clock iCLK, and an asynchro... | module LCD_Controller ( // Host Side
iDATA,iRS,
iStart,oDone,
iCLK,iRST_N,
// LCD Interface
LCD_DATA,
LCD_RW,
LCD_EN,
LCD_RS ); | module LCD_Controller ( // Host Side
iDATA,iRS,
iStart,oDone,
iCLK,iRST_N,
// LCD Interface
LCD_DATA,
LCD_RW,
LCD_EN,
LCD_RS );
// CLK
parameter CLK_Divide = 16;
// Host Side
input [7:0] iDATA;
input iRS,iStart;
input iCLK,iRST_N;
output reg oDone;
// L... | 81892b05be02d338f867674468e07b9cab15ba05ac08e21db825e908b9ef764e |
Create a Verilog module named `ocxo_clk_pll_clk_wiz` (with `timescale 1ps/1ps) that generates a 100 MHz system clock from a 10 MHz single-ended reference clock (e.g., an OCXO) using a Xilinx 7-series MMCME2_ADV clock-management primitive. The module has four ports: an input clock `clk_in1`, an output clock `clk_out1`, ... | module ocxo_clk_pll_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked
); | // file: ocxo_clk_pll.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not... | 7ef52bb9cdb36152af8871d5995a3f1b1a0e867e813e1348fc94669dd5c512b7 |
Design a Verilog clock-generation module named altpll0 for an Altera Cyclone II FPGA that uses the ALTPLL megafunction to derive a 12 MHz clock from a 50 MHz board oscillator. The module should expose exactly two ports: a single-bit clock input inclk0 and a single-bit clock output c0. Instantiate the altpll primitive c... | module altpll0 (
inclk0,
c0); | // megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpll0.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// =============================================... | 9d5b12b84de9fe7084444fc4636fb3de456dc32fd87698f086dc6c8db4dfa4f7 |
Design a synthesizable synchronous FIFO module named fifo that stores 16-bit words in a circular buffer with registered output and flag generation. The interface consists of a clock clk, a synchronous active-high reset rstp, a 16-bit data input din, a write-request input writep, a read-request input readp, a registered... | module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp); | `begin_keywords "1364-2005"
//
// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either ve... | e65f1cb97dddd5962086d0a51d5f0a7e48d4ee101d19940a19df98a9baf9dab2 |
Design a Verilog module named `sobel` that implements Sobel edge detection on a 640×480 8-bit grayscale image held in on-chip memory, targeting a Zynq-7000 FPGA. The module acts as a Wishbone-style slave to an upper-level controller, with inputs `clk_i`, `rst_i`, `cyc_i`, `stb_i`, `we`, a 22-bit `adr_in`, a 32-bit `dat... | module sobel(
clk_i,
rst_i,
cyc_i,
stb_i,
start, //״̬»ú¿ªÊ¼ÐźÅ
we,
adr_in, //ÉϲãÄ£¿é¶ÁдsobelʱµÄµØÖ·ÊäÈë
dat_in, //ÉϲãÄ£¿éÏòsobelдÊý¾ÝʱµÄÊý¾ÝÊäÈë
dat_out, //ÉϲãÄ£¿é¶Ásobel½á¹ûʱµÄµØÖ·Êä³ö
ack_out, //ÓëÉϼ¶Ä£¿éµÄack
done //µ±Í¼Æ¬ÍêÈ«´¦ÀíÍêʱ£¬´ËÐźÅÓÐЧ£¬ÉϲãÄ£¿é¿ªÊ¼¶Ásobel... | `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Xy Chen
//
// Create Date: 14:46:02 03/26/2016
// Design Name:
// Module Name: sobel
// Project Name:
// Target Devices: zynq_7000
// Tool versions: vivado 2014.4
// Desc... | 93fbacdcb7da9cd6b4041725ae5a0ed15b3d52ab9d27fd303b0bfba27772de55 |
Design a parameterized register file module named Computer_Datapath_RegisterFile for a simple computer datapath, with parameters WORD_WIDTH (default 16), DR_WIDTH (default 3), SB_WIDTH and SA_WIDTH (both equal to DR_WIDTH), OPCODE_WIDTH (default 7), CNTRL_WIDTH (equal to DR_WIDTH+SB_WIDTH+SA_WIDTH+11), and COUNTER_WIDT... | module Computer_Datapath_RegisterFile(
output reg [WORD_WIDTH-1:0] ADDR_bus_out,
output reg [WORD_WIDTH-1:0] B_data_out,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in,
input [WORD_WIDTH-1:0] D_bus_in,
input CLK,
input RST
); | module Computer_Datapath_RegisterFile(
output reg [WORD_WIDTH-1:0] ADDR_bus_out,
output reg [WORD_WIDTH-1:0] B_data_out,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in,
input [WORD_WIDTH-1:0] D_bus_in,
input CLK,
input RST
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_W... | 15d8c1385d544270a4f5221cebddd23da5d4e4e4b4fc59766c681dcc936dca11 |
Design a Verilog module named I2C_Controller that acts as an I2C master capable of performing a three-byte register-write transaction or a combined write-then-read register-read transaction with a repeated start. The module has the following interface: a system clock iCLK; an asynchronous active-low reset iRST_N; a slo... | module I2C_Controller
(
input iCLK,
input iRST_N,
input I2C_CLK,
input I2C_EN,
input [23:0] I2C_WDATA,
output I2C_SCLK,
inout I2C_SDAT,
input WR,
input GO,
output ACK,
output reg END,
output reg [7:0] I2C_RDATA
); | module I2C_Controller
(
input iCLK,
input iRST_N,
input I2C_CLK,
input I2C_EN,
input [23:0] I2C_WDATA,
output I2C_SCLK,
inout I2C_SDAT,
input WR,
input GO,
output ACK,
output reg END,
output reg [7:0] I2C_RDATA
);
reg I2C_BIT;
reg SCL... | 97613f12e157aea284aed604a54b3df95d8b2d21f765cefe4f08657f1c70ff74 |
Create a Verilog wrapper module named sky130_fd_sc_ms__mux2_1 that implements a 2-input multiplexer standard cell of drive strength 1 for the SkyWater SKY130 medium-speed standard-cell library by simply instantiating the base functional cell sky130_fd_sc_ms__mux2 (included from "sky130_fd_sc_ms__mux2.v") and passing al... | module sky130_fd_sc_ms__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
); | /**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | c8293dbf43a3fe513d604047eb60aa637e585f9aa114da5f6f8d16753b9dd2df |
Design a Verilog module named DE0_NANO_SOC_QSYS_nios2_qsys_mult_cell that implements one 32-by-16 partial-product cell of a Nios II soft-core multiplier in a Qsys system targeting a Cyclone V FPGA (DE0-Nano-SoC). The module has two 32-bit unsigned operand inputs A_mul_src1 and A_mul_src2, a clock clk, an active-low asy... | module DE0_NANO_SOC_QSYS_nios2_qsys_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
... | //Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated do... | 055b83bd6ef8dd2b1031b73106041477a01ac84e0339818dfbe25370faa94d92 |
Create a Verilog stub module named `sky130_fd_sc_hdll__or2b` for the SkyWater sky130 hdll standard-cell library, representing a 2-input OR gate whose first input is inverted (i.e., a logic function of the form X = ~A OR B, with the second port named in active-low form as B_N). The module should have exactly three ports... | module sky130_fd_sc_hdll__or2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output X
); | /**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | 2ff9af69fb28d2abc776f31827372466831a4877fc099f74437034d3c281f716 |
Design a Verilog module named counter that implements a small programmable countdown-style timer with a one-shot done indicator. The module has four inputs: a clock called div_clk, an active-high asynchronous reset called rst, an enable input called contando, and a 4-bit programmable terminal value called time_value; i... | module counter(div_clk,rst,time_value,contando, terminado); | `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:36:03 09/06/2013
// Design Name:
// Module Name: counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
//... | ca605d5e68dd19c6e0896052e4ba2887c4260c10ad3ad8e21eb60ec37587e9a9 |
Create a black-box Verilog stub module named sky130_fd_sc_lp__mux2 that models a 2-input multiplexer standard cell from the SkyWater SKY130 low-power library, where the single-bit output X is driven by select input S choosing between data inputs A0 (when S is 0) and A1 (when S is 1), i.e., X = S ? A1 : A0. Declare X as... | module sky130_fd_sc_lp__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
); | /**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | 7a58830282811af3cad0107a90446ce0d193e22c8c5c22c3fb99280f0dd061c7 |
Create a Verilog wrapper module named `OpenSSD2_m00_regslice_0` that implements an AXI3 register slice for a Zynq-based design, inserting pipeline registers between an AXI slave-side port (`s_axi_*`) and an AXI master-side port (`m_axi_*`) so that timing is broken without changing transaction semantics. The module has ... | module OpenSSD2_m00_regslice_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
... | // (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... | aa489497246adc5ce645ae3dbecf814cadb12d1bb8d50ce3cfa0e27003d8734d |
Design a Verilog module named audio_driver that generates simple game sound effects (e.g., for a Pong-style game) as a single-bit square wave for a piezo speaker. It has inputs clk (assume 16 MHz), active-low reset rst_n, and a 2-bit sound-select snd_sel, plus one registered output audio_o. First build a 1 ms time base... | module audio_driver( clk,
rst_n,
snd_sel,
audio_o
); |
module audio_driver( clk,
rst_n,
snd_sel,
audio_o
);
input clk;
input rst_n;
input wire[1:0] snd_sel;
output reg audio_o;
reg [14:0] timer_1ms;
reg msec;
reg [3:0] cycle_cnt;
reg [3:0] t1,t2,t3,t4;
reg [3:0] on_time,off... | 936a77f20da655d64f4430034da034215fbc2d06a755009776323c5f7aae4929 |
Implement a Verilog module named der_reg_15 that serves as the second-level (level 15) command-parameter register stage in a 2D drawing engine pipeline. It takes a drawing engine clock de_clk, an asynchronous active-low reset de_rstn, and a single-bit load enable load_15, along with a set of level-1 command inputs: buf... | module der_reg_15
(
input de_clk, // drawing engine clock input
de_rstn, // reset input
input load_15, // load L15 command parameters
input [12:0] buf_ctrl_1, // buffer control register input
input [31:0] sorg_1, // source origin register... | ///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software... | 321762cbe754687771293edca2dcc5cdd0b40e10af65a675deeef51b2da83ff1 |
Write a Verilog 2001 testbench module named test_eth_demux_64_4 (with `timescale 1ns/1ps) for a parameterized Ethernet demultiplexer module called eth_demux. Define parameters M_COUNT=4, DATA_WIDTH=64, KEEP_ENABLE=(DATA_WIDTH>8), KEEP_WIDTH=(DATA_WIDTH/8), ID_ENABLE=1, ID_WIDTH=8, DEST_ENABLE=1, DEST_WIDTH=8, USER_ENAB... | module test_eth_demux_64_4; | /*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distri... | 265060c4d135c629f67e9453c0aca20a670799432611261f061f09481c5bfeda |
Create a Verilog wrapper module named sky130_fd_sc_hs__o31a_4 for the SkyWater sky130_fd_sc_hs standard-cell library that implements a 4-unit drive-strength "o31a" gate, whose logic function is X = ((A1 | A2 | A3) & B1), i.e., a 3-input OR (inputs A1, A2, A3) feeding a 2-input AND with B1, producing single output X. Ra... | module sky130_fd_sc_hs__o31a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
); | /**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | 2936a7683355d9f22a0866e780f54c5ab84f341eaa774ea8e023e41671565074 |
Design a motion-compensation control FSM module named mc_ctrl for a video encoder pipeline that sequences luma/chroma transform-quantization (TQ) and chroma interpolation in a fixed order. The module has a clock input clk, an active-low asynchronous reset rstn, a single-bit start input mc_start_i, and a single-bit done... | module mc_ctrl (
clk ,
rstn ,
mc_start_i ,
mc_done_o ,
mvd_access_o ,
chroma_start_o ,
chroma_sel_o ,
chroma_done_i ,
tq_start_o ,
tq_sel_o ,
tq_done_i
); | //-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FA... | 6b7b12fff6e9c9e6dbbfda3952397192e2c5098b4eb7921ea3af6f65d0e9e97d |
Create a Verilog wrapper module named `sky130_fd_sc_hd__mux2_2` for the SkyWater sky130_fd_sc_hd standard-cell library that represents a 2-input multiplexer with drive strength 2 (two unit sizes): the output `X` should follow data input `A0` when the select input `S` is logic low and data input `A1` when `S` is logic h... | module sky130_fd_sc_hd__mux2_2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
); | /**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | 21ddcc25d06c8db2d8db9108c49e1b51827c9ab38de37c178b5b140d009a7be4 |
Create a Verilog wrapper module named `sky130_fd_sc_ms__a21boi_1` for the SkyWater sky130_fd_sc_ms standard cell library that wraps the base cell `sky130_fd_sc_ms__a21boi` at drive strength 1; the cell's logic function is a 2-input AND feeding the first input of a 2-input NOR whose second input is inverted, i.e., Y = !... | module sky130_fd_sc_ms__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); | /**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | ca665f2b3baefd78d0cb3673531c1f50e9f0d9deadad1ba7432df9715ba6136b |
Create a Verilog wrapper module named sky130_fd_sc_lp__nor2_lp that implements a 2-input NOR gate (output Y = ~(A | B)) for a low-power standard-cell library by instantiating the existing base cell sky130_fd_sc_lp__nor2, which is brought in by including the file "sky130_fd_sc_lp__nor2.v". The wrapper must expose output... | module sky130_fd_sc_lp__nor2_lp (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); | /**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | d563724c2d9e146c7e79febbb995aab8234e4df15a79a9197befee8dbffcc2d6 |
End of preview. Expand in Data Studio
VeriLM instruction pairs
Synthetic (instruction → Verilog) training pairs used to fine-tune VeriLM, built to address a gap the VeriGen paper itself names as unfinished future work: a supervised dataset mapping natural-language hardware design requests to Verilog implementations.
What's new here vs. reused
- New: every
instructionin this dataset. VeriGen's corpus is raw code only -- no natural-language descriptions exist anywhere upstream of this project. All 874 instructions were generated by the pipeline in this repo (below), and didn't exist before it ran. The generation pipeline itself (prompt design, the pre-generation Icarus Verilog quality gate, the post-generation output-format validation, dedup logic across batches) is original to this project. - Reused, correctly cited: only the
codecolumn, sourced verbatim fromshailja/Verilog_GitHub. That's the narrow, specific scope of the citation andsource_datasetstag below -- it covers the source code, not the instructions built on top of it.
How this was built
For each of 874 modules sampled from
shailja/Verilog_GitHub
(VeriGen's own released, deduplicated GitHub Verilog corpus), Kimi K3 (via Fireworks AI)
was prompted to write the natural-language instruction a hardware engineer
could have given that would lead someone to write exactly that module
("reverse instruction" generation) -- see data/gen_instructions.py in the
VeriLM repo. Two quality gates were
applied before generation: the source had to parse cleanly in Icarus Verilog
(elaboration-only failures, like referencing an undefined vendor IP
submodule, are not treated as a syntax problem -- only genuine parse errors
are); and after generation, the model's response had to match a strict
<instruction>...</instruction> output format, so responses where the model
narrated its own reasoning instead of a clean instruction were discarded
rather than kept.
License
Same license as the source data it's derived from --
BigCode OpenRAIL-M v1
-- since the code column is largely verbatim from shailja/Verilog_GitHub,
which carries that license. This matches the precedent of VeriGen's own
released checkpoints.
Columns
instruction: the synthesized natural-language design requestmodule_header: the Verilog module's port declaration, extracted separatelycode: the original Verilog module fromshailja/Verilog_GitHubhash: SHA-256 ofcode, for dedup/leakage checks against the base corpus splits
Citation
This dataset has two distinct sources -- please cite both. VeriGen for the underlying code
column, and this dataset for the instruction column and the construction pipeline itself:
@article{thakur2024verigen,
author = {Thakur, Shailja and Ahmad, Baleegh and Pearce, Hammond and Tan, Benjamin and Dolan-Gavitt, Brendan and Karri, Ramesh and Garg, Siddharth},
title = {VeriGen: A Large Language Model for Verilog Code Generation},
journal = {ACM Transactions on Design Automation of Electronic Systems},
volume = {29}, number = {3}, articleno = {46}, year = {2024},
doi = {10.1145/3643681}, url = {https://doi.org/10.1145/3643681}
}
@misc{patel2026verilminstructpairs,
author = {Patel, Jal},
title = {VeriLM Instruction Pairs},
year = {2026},
url = {https://huggingface.co/datasets/jpate190/VeriLM-instruct-pairs}
}
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