Silica RTL Serving — Model Card
Status: Serving configuration + model selection artifact. No fine-tuned weights published here yet (training requires GPU). This repo documents the Silica model-serving layer and is the publication target for accepted LoRA adapters after the Phase 5 acceptance gate.
Intended use
Serving endpoint for Silica — autonomous semiconductor design (RTL -> verification -> synthesis -> signoff). Silica routes task types to model tiers by measured strength:
| Tier | Model | Use |
|---|---|---|
| orchestration_hard_repair | nvidia/Nemotron-3-Ultra-550B-A55B (via API) | hardest RTL repair, orchestration |
| primary_self_hosted | Qwen/Qwen2.5-Coder-32B-Instruct | RTL generation (LoRA-tunable) |
| frequent_low_latency | Qwen/Qwen2.5-Coder-7B-Instruct (this base) | synthesis/timing interpretation, spec |
| rtl_specialist | ai4b/RTLCoder-7B | EDA-log diagnosis (auto-fallback) |
| verification_repair | Qwen2.5-Coder-7B + VeriReason-style LoRA (target) | testbench, repair |
Selection rationale + benchmarks (CVDP, VerilogEval v2, RTLLM-v2, ChipVerilog) + licenses + hardware in training/MODEL_SELECTION_REPORT.md in the Silica repo.
Evaluation (real, executed)
Silica internal benchmark — 9/9 PASS with real Verilator 4.038 + Yosys 0.9: clean counters w4/w8/w16/w32, broken-RTL recovery (dual-fault in 2 attempts; isolated missing-semicolon in 1), invalid-RTL rejection, blocked-stage honesty (physical/timing never falsely passed), signoff honesty. LLM-augmented numbers pending HF_TOKEN + consent.
Training data provenance
SFT built only from real executed EDA runs (training/dataset_prep.py), preserving source/license, category, difficulty, constraints, reference output, tool versions, execution results, verification method. Public corpora: OpenRTLSet (131k modules), PyraNet-Verilog, shailja/Verilog_GitHub. Held-out test isolated. No fabricated logs or unverified RTL.
Limitations
- No GPU in build env -> no trained weights here. Reproducible LoRA/QLoRA script provided for external GPU (>=1xA100-80GB).
- Physical design / timing signoff BLOCKED (no OpenROAD/OpenSTA/PDK). Passing simulation is NOT fabrication-ready; Silica signoff states this.
- Deterministic fallback is default; external LLM requires SILICA_ALLOW_EXTERNAL_LLM=1 + HF_TOKEN. Fallback recorded in audit, never hidden.
- Do not send proprietary RTL to public serverless endpoints; use self-hosted endpoint (SILICA_LLM_ENDPOINT).
Rollback
Versioned by HF commit; set SILICA_LLM_MODEL/adapter env to previous revision. Ultimate fallback = deterministic Silica baseline (zero external dependency).