YOLOv6-N (ONNX) – Renesas X5H

Introduction

This repository hosts YOLOv6-Nano, targeting the Renesas R-Car X5H platform for object detection inference on the NPX6 NPU.

Note: The other YOLOv6 sizes (S, M, L) each have their own sibling repo (YOLOv6-S-ONNX, YOLOv6-M-ONNX, YOLOv6-L-ONNX). This repo documents the smallest, Nano, variant — confirmed via the compile-artifact filename (yolov6n_quantization_config.json) in the source benchmark export.

Model Architecture: YOLOv6 — Meituan's single-stage, industrial-oriented object detector (EfficientRep backbone, Rep-PAN neck), Nano size
Source Model: meituan/YOLOv6 — checkpoint yolov6n.pt
Task: Object Detection (COCO, 80 classes)
Parameters: ~4.7M (commonly cited YOLOv6-N figure from the Meituan release table; not independently re-verified cell-by-cell in this pass)
License note: Meituan YOLOv6 is distributed under GPL-3.0 — this differs from the Apache-2.0 default used by most other repos in this collection.

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

yolov6n_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	`fp32/yolov6n.onnx` — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Single AI Core · Batch size: 1 · Input: 3 × 640 × 640

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	6.314878	Measured

Only the 1-AI-core slice was run for this model in the source benchmark export — the 12-core slice was skipped, so no 12-core row is reported here.

Accuracy

TBD — not yet measured/published for this repo.

Runtime Details

MWMX Runtime

Engine: Renesas MWMX (Middleware MX) native inference runtime
Input format: FP32 ONNX (compiled by the MWMX toolchain)
NPU execution precision: INT8 (auto-cast by MWMX toolchain)
Execution target: NPX6-48K NPU on R-Car X5H

Prerequisites

To run inference on Renesas R-Car X5H, you need:

Renesas R-Car X5H board with NPX6 NPU
Renesas MWMX Runtime
Hugging Face CLI to download the model

Download

hf download Renesas/YOLOv6-N-ONNX --repo-type=model --include "fp32/*"

Benchmark Methodology

HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
Slices: only the 1 AI core slice was run for this model; the 12-core slice was skipped in the source export

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