Renesas/VGG16-ONNX

VGG16 (ONNX) – Renesas X5H

Introduction

This repository hosts VGG-16, targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

Note: The other VGG variants (VGG11-ONNX, VGG11-BN-ONNX) each have their own sibling repo.

• Model Architecture: VGG — deep convolutional network built from stacked 3x3 convolutions
• Source Model: timm/vgg16.tv_in1k — OpenMMLab config vgg16_8xb32_in1k
• Task: Image Classification (ImageNet-1k, 1000 classes)
• Parameters: 138.4M

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

vgg16_8xb32_in1k_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅ Provided	fp32/vgg16bn_8xb32_in1k.onnx — auto-cast to INT8 by the MWMX toolchain at compile time; no separate INT8 file is shipped

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input resolution: not available from source data (TBD)

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	14.659391	Measured
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 12 Cores · 850 MHz	12.065876	Measured

Accuracy

TBD — not yet measured/published for this repo.

---

Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

---

Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/VGG16-ONNX --repo-type=model --include "fp32/*"

---

Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: results reported for both 1 AI core and 12 AI cores per NPU instance