Renesas/SPNASNet-ONNX

SPNASNet-100 (ONNX) – Renesas X5H

Introduction

This repository hosts SPNASNet-100, targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

• Model Architecture: SPNASNet-100 — a mobile ConvNet discovered by Single-Path NAS, a differentiable one-shot neural architecture search method for designing hardware-efficient ConvNets in under 4 hours of search time
• Source Model: timm/spnasnet_100.rmsp_in1k
• Paper: Single-Path NAS: Designing Hardware-Efficient ConvNets in Less Than 4 Hours (Stamoulis et al., ECML PKDD 2019)
• Task: Image Classification (ImageNet-1k, 1000 classes)
• Parameters: 4.4M (timm model card figure for spnasnet_100.rmsp_in1k)
• License: Apache-2.0 (per timm model card)

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

spnasnet_100_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	fp32/spnasnet_100.onnx — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input resolution: 224×224 (NCHW 1,3,224,224)

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	0.873398	Measured

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/SPNASNet-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: only the 1 AI-core slice is available; the 12-core slice was Skipped in the source APM50 CI run for this model