Renesas/ResNet50V2-ONNX

ResNet50V2 (ONNX) – Renesas X5H

Introduction

This repository hosts ResNet50 V2 targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

• Model Architecture: ResNet50 V2 — pre-activation residual network variant
• Source Model: onnxmodelzoo/resnet50-v2-7 — ONNX Model Zoo resnet50-v2-7
• Task: Image Classification (ImageNet, inferred — dataset not explicitly stated in source data)
• Parameters: 25.6M (the v2 pre-activation variant does not change the total parameter count vs v1)
• Note: Unlike the rest of this batch of repos, this model has both hardware-measured (MWMX) and software-estimated (PPA Estimator) benchmark numbers available in the source data — see Performance and Benchmark Methodology below.

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 at load/compile time — no separate quantization step is required. Two independent benchmark sources are available for this model: the MWMX runtime (hardware-in-the-loop) and the Renesas PPA Estimator (software estimate).

resnet50_v2_sim.onnx (FP32)
        │
        ├─▶  MWMX Runtime     ──▶  INT8 auto-cast   ──▶  NPX6 NPU (measured)
        │
        └─▶  PPA Estimator    ──▶  INT8 (estimated) ──▶  NPX6 NPU (estimated)

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅ Provided	fp32/resnet50_v2_sim.onnx — auto-cast to INT8 by the MWMX toolchain/PPA Estimator at compile time; no separate INT8 file is shipped

Performance

Measured on Renesas R-Car X5H. This model is unusual within this batch: both hardware-measured MWMX (HIL) numbers and software-estimated PPA Estimator numbers are available, rather than MWMX-only.

Benchmark configuration: Single NPU · Batch size: 1 · Input resolution: not available from source data — TBD

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	4.605038	Measured
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 12 Cores · 850 MHz	4.140341	Measured
PPA Estimator	INT8	X5H · 1× NPU · 1 Core · 1066 MHz	2.041042	Estimated (APM rate vs. HW = 44.32%)
PPA Estimator	INT8	X5H · 1× NPU · 12 Cores · 1066 MHz	0.559915	Estimated (APM rate vs. HW = 13.52%)

"APM rate" figures above are the source data's reported ratio of the PPA-estimated latency to the corresponding measured MWMX (HW) latency for that slice — i.e. how closely the software estimate tracked the real hardware measurement. They are carried over as-is from the source CI data.

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H
• Type: Hardware-in-the-loop — measured on physical silicon

PPA Estimator

• Engine: Renesas PPA Estimator
• Input format: FP32 ONNX
• NPU execution precision: INT8
• Type: Software performance estimate — not measured on physical silicon; uses a higher default NPU clock (1066 MHz) than the MWMX HIL numbers (850 MHz)

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime, or the Renesas PPA Estimator tool for software estimates
3. Hugging Face CLI to download the model

Download

hf download Renesas/ResNet50V2-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target); single NPU, 850 MHz NPU clock
• Estimation: PPA Estimator software estimate; single NPU, 1066 MHz NPU clock
• Precision: FP32 ONNX input; INT8 execution
• Slices: results reported for both 1 AI core and 12 AI cores per NPU instance, for both the MWMX (measured) and PPA Estimator (estimated) sources — this is the only repo in this batch with both measured and estimated numbers