ResNet34-416x640 (ONNX) – Renesas X5H

⚠️ Task classification needs confirmation. The source checkpoint name (resnet34_1_3_416_640, i.e. an NCHW input shape of [1, 3, 416, 640]) uses a non-square input resolution. Plain ImageNet-style classification checkpoints are almost always square (e.g. 224×224); a non-square 416×640 input strongly suggests this is a ResNet34 backbone for an object-detection pipeline rather than a standalone classifier. This card defaults the task to object-detection — confirm the intended task/checkpoint before publishing.

Introduction

This repository hosts a ResNet34 model at a non-square 416×640 input resolution, targeting the Renesas R-Car X5H platform for inference on the NPX6 NPU.

Model Architecture: ResNet34 (likely used as a detection backbone — see caveat above)
Source Model: internal export resnet34_1_3_416_640 (no HuggingFace mirror of these weights; see model.source in .metadata.yaml)
Task: Object Detection (unconfirmed — see caveat above)
Input Resolution: 416 × 640 (inferred from the checkpoint name)
Parameters: not published — count them from the ONNX graph (sum(numpy_helper.to_array(t).size for t in model.graph.initializer))

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

resnet34_1_3_416_640.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	`fp32/resnet34_1_3_416_640.onnx` — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input resolution: 3 × 416 × 640 (inferred)

The 1-AI-core slice failed in the source CI pipeline, so only the 12-core result is available.

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 12 Cores · 850 MHz	1.370561	Measured

Accuracy

TBD — not yet measured/published for this repo.

Runtime Details

MWMX Runtime

Engine: Renesas MWMX (Middleware MX) native inference runtime
Input format: FP32 ONNX (compiled by the MWMX toolchain)
NPU execution precision: INT8 (auto-cast by MWMX toolchain)
Execution target: NPX6-48K NPU on R-Car X5H

Prerequisites

To run inference on Renesas R-Car X5H, you need:

Renesas R-Car X5H board with NPX6 NPU
Renesas MWMX Runtime
Hugging Face CLI to download the model

Download

hf download Renesas/ResNet34-416x640-ONNX --repo-type=model --include "fp32/*"

Benchmark Methodology

HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
Slices: only the 12-AI-core result is available (1-core run failed in the source CI pipeline)

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