Renesas/ConvNeXt-Base-ONNX

ConvNeXt-Base (ONNX) – Renesas X5H

⚠️ Renamed from ConvNeXt-Base-ONNX. The old name claimed object detection, but the source checkpoint (convnext_base_in21k_pre_3rdparty_in1k_optimized_448) and its single output tensor are an ImageNet-21k→1k classification head — there is no detection head in this graph. The repo is now named after what it actually contains. Confirm the intended checkpoint if object detection was the goal.

Introduction

This repository hosts ConvNeXt-Base targeting the Renesas R-Car X5H platform for inference on the NPX6 NPU.

• Model Architecture: ConvNeXt-Base
• Source Model: timm/convnext_base.fb_in22k_ft_in1k — OpenMMLab config convnext_base_in21k_pre_3rdparty_in1k
• Task: Image Classification (see caveat above)
• Input Resolution: 448 × 448 (inferred from _448 in the checkpoint name)
• Parameters: 88.6M

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

convnext_base_..._optimized_448.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅ Provided	fp32/convnext-base_in21k-pre_3rdparty_in1k.onnx — auto-cast to INT8 by the MWMX toolchain at compile time; no separate INT8 file is shipped

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM80 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input: 3 × 448 × 448 (inferred)

The 1-AI-core slice failed to compile in the source CI pipeline, so only the 12-core result is available.

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 12 Cores · 850 MHz	6.490	Measured

Reconfirmed: 1-core compile still fails as of the 2026-09-16 benchmark run.

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/ConvNeXt-Base-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM80" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: only the 12-AI-core result is available (1-core compile failed)