Arm/resnet-50-int8-per-channel-ethos-u-executorch

ResNet-50 optimized for Arm-based Ethos-U NPU

An INT8-quantized version of torchvision's resnet50 (IMAGENET1K_V2 weights) for image classification, exported to ExecuTorch (.pte) and compiled with the Arm Vela compiler for the Arm Ethos-U85 NPU.

Summary

This repository contains an Arm-optimized version of torchvision's resnet50 (ResNet-50 architecture originally introduced by Microsoft Research) for image classification, quantized to INT8 via static post-training quantization — per-channel symmetric weights, per-tensor affine activations. The model is provided in ExecuTorch (.pte) format, targeting Ethos-U NPU systems.

This version is intended to demonstrate efficient inference on Arm-based platforms while preserving the original model's intended behavior. Arm has evaluated this model on ImageNet-1k and measured performance on a representative evaluation target.

Key results

Area	Result
Model format	ExecuTorch (.pte)
Target device class	Ethos-U NPU
Reference device	Alif DK-E8 (Cortex-M55, bare-metal, Ethos-U85 NPU)
Primary performance result	p50 latency 151.44 ms (6.60 inferences/s)
Accuracy result	Top-1 80.57%, Top-5 95.31%
Size / memory result	21.76 MB (4.48x smaller), SRAM peak 3,504,333 bytes

Original model

Field	Value
Original model	torchvision resnet50
Original source	torchvision/models/resnet.py
Original developer	Microsoft Research (architecture); weights from torchvision's modernized training recipe (IMAGENET1K_V2)
Original model card	torchvision.models.resnet50
Original license	BSD-3-Clause

Model files

File	Description
resnet50_ethosu_optimized_channel.pte	Arm-optimized model for deployment
config.yaml	Model I/O contract used by the example
benchmarks/	FP32 baseline and Arm-optimized benchmark records

Performance

Performance was measured on the reference configuration below. Results are intended to make the optimization reproducible but do not guarantee identical performance on every Arm-based system.

Reference configuration

Field	Value
Device / platform	Alif DK-E8
CPU / accelerator	Cortex-M55 (1 core @ 400 MHz) + Ethos-U85 NPU (256 MACs/cycle @ 400 MHz)
OS	bare-metal
Runtime	ExecuTorch 1.1.0
Backend / delegate	Ethos-U85 NPU delegate (CMSIS-NN, Ethos-U-Driver)
Batch size	1
Precision	INT8, static PTQ — per-channel symmetric weights, per-tensor affine activations
Runs	100 measured runs, 10 warmup runs

Performance results

Metric	Original / baseline	Arm-optimized	Improvement
Model size (MB)	97.449	21.76	4.48x smaller
End-to-end latency p50 (ms)	N/A	151.4423	N/A
End-to-end latency p90 (ms)	N/A	151.4424	N/A
Frames per second	N/A	6.6032	N/A
SRAM peak (bytes)	N/A	3,504,333	N/A

The "Original / baseline" model size is the FP32 PyTorch state dict.

Because the Ethos-U85 NPU architecture natively processes integer workloads and does not support floating-point execution, the FP32 baseline cannot be compiled into an Ethos-U85 delegate .pte file, making NPU-accelerated baseline latency and throughput figures non-applicable.

Accuracy

Accuracy was evaluated on the ImageNet-1k validation split, comparing the FP32 baseline against the Arm-optimized INT8 model via a PyTorch FP32-vs-PT2E INT8 simulation, not on the exported .pte running on Ethos-U85.

Evaluation setup

Field	Value
Dataset	ImageNet-1k
Split	val
Number of samples	50000
Metric(s)	Top-1 accuracy, Top-5 accuracy
Evaluation runtime	PyTorch (FP32 vs. PT2E INT8 simulation)

Accuracy results

Metric	Original / baseline	Arm-optimized	Change
Top-1 accuracy (%)	80.854	80.5660	-0.29 pp
Top-5 accuracy (%)	95.438	95.3120	-0.13 pp

Accuracy was measured using the described evaluation setup. Users should re-evaluate the model on their own data before production use.

Arm optimization approach

Arm optimized this model for efficient inference on Arm-based platforms using a hardware-aware conversion and validation flow.

For this release, Arm used:

Optimization area	Applied?	Notes
Model conversion	Yes	Converted to ExecuTorch .pte and compiled with the Arm Vela compiler for the Ethos-U85 NPU
Quantization	Yes	INT8 static PTQ — per-channel symmetric weights, per-tensor affine activations; calibrated on 2,000 ImageNet-1k samples
Runtime/backend selection	Yes	Ethos-U85 NPU delegate (CMSIS-NN, Ethos-U-Driver)
Graph/runtime compatibility updates	Yes	Performed as part of the Ethos-U85 export pipeline
Accuracy validation	Yes	Compared against the original model or published baseline
Performance validation	Yes	Measured on the reference Arm platform

The goal of this process is to improve deployment characteristics such as latency, memory use, model size, and runtime compatibility while preserving the model's intended behavior. Detailed conversion scripts, calibration configuration, or backend-specific implementation details may be provided separately where appropriate.

Expected input

Property	Value
Shape	[1, 3, 224, 224]
Dtype	float32
Range	[0.0, 1.0]
Preprocessing	resize so the shorter side is 232 pixels, center crop to 224x224, to tensor, normalize (mean [0.485, 0.456, 0.406], std [0.229, 0.224, 0.225])

Expected output

Property	Value
Shape	[1, 1000]
Format	Raw class logits (unnormalized)
Postprocessing	softmax, top-5

Intended use

This model is intended for developers evaluating image classification workloads on Arm-based platforms. It is suitable as a reference implementation for benchmarking, prototyping, and integration exploration.

Limitations

• Evaluated on the full ImageNet-1k val set (50000 images)
• Accuracy was evaluated on ImageNet-1k val and may not generalize to all domains. The reported accuracy is based on a PyTorch quantized-vs-FP32 simulation pass, not a measurement of the exported .pte running on the Corstone-320 FVP or on Ethos-U85 silicon.
• Fixed input size of 224x224 — the shorter edge is resized to 232 with the aspect ratio preserved, then the center 224x224 region is cropped, so content outside that crop is discarded
• Performance measurements are from the Alif DK-E8 development board; results may differ on other Arm devices
• MAC utilization (26.39%) is well below the effective PMU cycle ratio (99.98%) — the NPU is rarely idle, but a meaningful share of active cycles is spent on memory movement rather than compute

Additional notes

Most operators are delegated to the Ethos-U85 NPU, with the remainder running on the Cortex-M55 host CPU. No layers were kept in FP32 — all layers were quantized.

About this version

Original Model: torchvision resnet50 by Microsoft Research (architecture); weights from torchvision's modernized training recipe (IMAGENET1K_V2) - Repository

Optimization/conversion: Arm-Optimized version for execution on Arm-based platforms.

Converted/optimized by: Arm

License: The Original Model and the Optimized Model are subject to BSD-3-Clause.

This repository contains a converted or optimized version of the Original Model (the “Optimized Model”). The Original Model has been converted or optimized as described above for execution on Arm-based platforms.

No retraining or fine-tuning of the Original Model was performed as part of the conversion or optimization. The conversion or optimization was not intended to change the Original Model’s behavior or intended use.

Original Model and Documentation

For information about the Original Model, including its development, training data, intended uses, limitations and other relevant information, please refer to the Original Model repository. Information in that repository was provided by the original developer or other third parties and, unless expressly stated otherwise, has not been independently verified by Arm.

Licenses and Third-Party Terms

Use of the Original Model and the Optimized Model is subject to the applicable licenses, usage restrictions and other terms identified above and in the relevant repositories. Publication of the Optimized Model does not grant any rights beyond those provided under the applicable license terms.

You are responsible for reviewing those terms and ensuring that your use of the Original Model and the Optimized Model is permitted.

Purpose of this Release

The Optimized Model is provided as a reference implementation to demonstrate and evaluate execution and performance on Arm-based systems. It is not a production-ready or supported solution.

Arm’s publication of the Optimized Model does not constitute an endorsement or certification of the Original Model or a representation that the Optimized Model is suitable for production use or any particular purpose.

To the fullest extent permitted by applicable law (i) the Optimized Model is provided “as is.” Arm makes no representations or warranties that the Original Model, the Optimized Model or their outputs are accurate, safe, secure, non-infringing, legally compliant, suitable for production use or fit for any particular purpose; and (ii) Arm will not be liable for any loss or damage arising from or in connection with the Optimized Model, its use or its outputs.

You are responsible for independently evaluating the Optimized Model, its outputs and its suitability for your intended use, including compliance with applicable legal, regulatory, safety and security requirements.

Arm does not commit to provide ongoing support, maintenance or updates for the Optimized Model. Any use of or reliance on the Optimized Model or its outputs is at your own risk.