G4_DGCO — DarWINN Graph Containers for the Tensor G4 NPU

Compiled DGC0 artifacts (DarWINN Graph Containers) for the Google Tensor G4 NPU — the ahead-of-time compiled form the hardware actually runs. Produced on-device. Tooling + full write-up: https://github.com/qbnasasn/Google-Tensor-Chips → g4-pixel/.

⚠️ Read this first — coherence is NOT solved

These files compile and dispatch on the NPU. That is the only claim made here. Coherent generation at aggressive sub-byte quant (int4 / int2 / ternary) is UNSOLVED. Several of these DGC0s run on the NPU but produce incoherent / garbage text. "Compiles + dispatches on the NPU" and "generates coherent text" are two separate claims — only the first holds. Do not treat anything here as a working, coherent on-device LLM. It is not one yet.

Contents

Folder	What
gemma3-1b-islands/	Gemma3-1B, layer-sharded into per-layer DGC0s via island chunking. Each island_L##-##.dgc0 is one transformer layer AOT-compiled to a DGC0 that dispatches on the NPU via VII_COMMAND.
embeddinggemma/	EmbeddingGemma-300M AOT DGC0 (seq256).
bonsai/	Bonsai AOT DGC0s (layer samples).
toy-ops/	single-op DGC0s across op × quant (int8 / int4 / int2 / ternary / fp8 / fp16) — the seed of a per-op/per-quant micro-benchmark map of the G4 NPU (op coverage, fusion, tiling/alignment, roofline).

Provenance / license

Source models are open and remain under their own licenses — Gemma3-1B and EmbeddingGemma under the Gemma Terms of Use; Bonsai under its upstream license. These files are our G4 compilations (derivative artifacts), not redistributed Google binaries. No proprietary vendor blobs or first-party (AICore/Nano) models are included.

Run

Load a DGC0 via the DarWINN dispatch stack (libLiteRtDispatch_GoogleTensor → Tachyon → VII_COMMAND) on a rooted Tensor G4. See the g4-pixel/ docs linked above. Expect it to run, not to be coherent.