ostlerai/vance-4b-instruct

VANCE (Verilog Assistant Novel Chatbot Entity)

VANCE is a specialized 4-billion parameter open-weight model designed to assist ASIC and FPGA developers in generating high-quality SystemVerilog RTL from natural-language specifications. Based on the Qwen3-4B-Base architecture, VANCE is engineered to provide GPT-4o-level performance while remaining small enough to run locally on a standard engineering laptop, ensuring data privacy and eliminating API costs.

Highlights

• Highly Efficient Spec-to-RTL Generation: Achieves a 69.4% Pass@1 on the VerilogEvalV2 benchmark, outperforming GPT-4o (64.1%) and several larger domain-specific models.
• Laptop-Ready: Optimized for local deployment.
• Verifiable Training: Trained using Reinforcement Learning with Verifiable Rewards (RLVR) utilizing Icarus Verilog and Yosys for formal correctness.
• Privacy-First: Enables high-end HDL assistance without sending proprietary specifications to external cloud providers.

Model Overview

VANCE is a fine-tuned version of Qwen3-4B-Base.

• Type: Causal Language Model
• Base Model: Qwen3-4B-Base
• Number of Parameters: 4.0B (3.6B non-embedding)
• Number of Layers: 36
• Attention: GQA (32 Q heads, 8 KV heads)
• Context Length: 12k (SFT) / 5k (RLVR)
• License: Apache-2.0

Training Methodology

VANCE was developed through a rigorous two-stage training pipeline to ensure both syntactic correctness and functional accuracy.

1. Data Curation

To avoid "LLM-collapse" and ensure high-quality organic code, the training set consists of:

• Organic HDL: SystemVerilog samples from GitHub (pre-Nov 2022) and OpenCores, filtered for utility and clarity via AI agents and syntax-checked via slang.
• Correct-by-Construction: 33k samples generated via rule-based generators (including CraftRTL) with accompanying testbenches.
• Specialized Reasoning: 1k boolean algebra simplification prompts and 94k synthetic SystemVerilog Q&A pairs.
• General Coding: 10k verified Python and 600 C++ pairs to maintain general logic capabilities.

2. Training Pipeline

• Supervised Fine-Tuning (SFT): Full parameter fine-tuning via Axolotl with a 12k token context window and a learning rate of 7.5e-5.
• RLVR (Reinforcement Learning with Verifiable Rewards): Employed the VeRL framework and GSPO algorithm. Rewards were binary (pass/fail) based on:
  • Simulation: Icarus Verilog (when testbenches were available).
  • Formal Verification: Yosys EQY (formal equivalence checking against golden references).

Performance

VANCE demonstrates exceptional performance in spec-to-RTL generation compared to both general-purpose foundation models and other Verilog-tuned models.

VerilogEvalV2 Spec-to-RTL Benchmark (Pass@1 %)

Model Type	Model	Size	Pass@1 (%)
Foundational	Gemini 3 Flash	-	90.7
	GPT-4o	-	64.1
	Qwen3-4B-Instruct-2507	4B	33.1
Verilog-tuned	ScaleRTL (Qwen3)	32B	76.3
	CodeV-R1-7B	7B	68.8
	CraftRTL	16B	68.0
Ours	VANCE (Qwen3)	4B	69.4

Quickstart

Requirement: This model requires transformers v5 (trained using 5.16.1).

from transformers import AutoModelForCausalLM, AutoTokenizer

model_name = "ostlerai/vance-4b-instruct"

# load the tokenizer and the model
tokenizer = AutoTokenizer.from_pretrained(model_name)
model = AutoModelForCausalLM.from_pretrained(
    model_name,
    torch_dtype="auto",
    device_map="auto"
)

# Example prompt: Specification to RTL
prompt = "Design a synchronous FIFO in SystemVerilog with a depth of 16 and a data width of 8 bits. Include full and empty flags."
messages = [
    {"role": "user", "content": prompt}
]
text = tokenizer.apply_chat_template(
    messages,
    tokenize=False,
    add_generation_prompt=True,
)
model_inputs = tokenizer([text], return_tensors="pt").to(model.device)

# Generate RTL
generated_ids = model.generate(
    **model_inputs,
    max_new_tokens=4096,
    temperature=0.7,
)
output_ids = generated_ids[0][len(model_inputs.input_ids[0]):].tolist() 
content = tokenizer.decode(output_ids, skip_special_tokens=True)

print(content)

Best Practices for RTL Generation

To get the most out of VANCE, we recommend the following settings:

1. Sampling Parameters: We suggest using Temperature=0.7,TopP=0.8, and TopK=20.
2. Prompting: Be explicit about module names, interfaces, clocking, and reset schemes (e.g., "Active-low asynchronous reset").
3. Verification: While VANCE is reasonably accurate, always verify generated RTL using a simulator (like VCS, Questa, Xcelium, Vivado, etc.) and a comprehensive testbench.

Citation

If you find VANCE helpful for your hardware development workflow, please cite our work:

@misc{vance2025,
      title={VANCE: The SystemVerilog Assistant That Runs on a Laptop}, 
      author={Patrick Ostler},
      year={2025},
      url={https://www.ostlerai.com/vance.pdf}, 
}

For more information, visit ostlerai.com.