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[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_367_7.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_348_27.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_64_4.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_720_9.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_999_9.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_36_11.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_886_3.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_310_3.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_1047_21.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_796_17.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_386_1.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_370_14.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_186_5.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_102_6.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_466_6.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_48_11.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_31_3.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_821_13.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_234_1.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_287_12.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_386_2.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_219_5.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_32_1.png" ]
[ { "role": "system", "content": "You are an AI assistant tasked with formal verification of register transfer level (RTL) designs.\nYour job is to translate a description of an assertion to concrete SystemVerilog Assertion (SVA) implementation.\n" }, { "role": "user", "content": "Here is the test...
[ "CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images/codev_seq_42K_367_8.png" ]
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CodeV-SVA-VL: Automated Hardware Assertion Generation from Natural Language Specifications and Waveform Diagrams

   

Introduction

We introduce CodeV-SVA-VL, a family of vision language models designed to translate natural-language verification properties and waveform diagrams into SystemVerilog Assertions (SVAs).

Open-Source Plan:

  • Benchmark ✓
  • Model ✓
  • Evaluation code ✓
  • Paper
  • Dataset ✓
  • Data synthesis and training code

This repository includes the NL-Waveform-SVA training data selected by bidirectional translation and equivalence verification.

  • CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-training.jsonl: Textual training data.
  • CodeV-SVA-dataset-83K-sva2wavedrom-qwen3p6-plus-diagram-wave2sva-self-verified-pass-images.tar: Waveform diagrams.

Citation

@misc{wu2026qimengcodevsvatrainingspecializedllms,
      title={QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis}, 
      author={Yutong Wu and Chenrui Cao and Pengwei Jin and Di Huang and Rui Zhang and Xishan Zhang and Zidong Du and Qi Guo and Xing Hu},
      year={2026},
      eprint={2603.14239},
      archivePrefix={arXiv},
      primaryClass={cs.CL},
      url={https://arxiv.org/abs/2603.14239}, 
}
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