tapeout-labs/hir-relationships

Hardware Integration Relationships (HIR)

A labeled dataset and multi-tier benchmark for cross-artifact relationship prediction in hardware designs: given a hardware artifact (a register or register field) and a firmware-visible artifact (a generated C #define), does a real relationship exist between them?

This is the concept-matching problem at the heart of SoC integration review — "is dma.CONTROL.EN the same thing the firmware calls DMA_CONTROL_EN_MASK?" — cast as a supervised binary task. To our knowledge no prior public benchmark targets register↔firmware relationships specifically; the dataset publication is the primary contribution.

Naming note: this benchmark is HIR, not "HWE-Bench". HWE-Bench is a separate, existing hardware-engineering benchmark that HIR consumes as one held-out test source (real co-modification pairs). They are distinct artifacts.

Why it exists

Labels in the convention-following tiers are mechanical, not hand-annotated: OpenTitan's regtool and Caliptra's PeakRDL generate C headers from register descriptions by a documented naming convention, so every generated define binds deterministically to its source register/field. We parse that convention exactly against the ground-truth name sets; any define that does not parse is excluded and counted, never guessed.

Because the easy labels are convention-derived, a trivial token-containment scorer reaches AUC ~0.995 on them — easy-tier AUC says almost nothing about a model. The dataset therefore ships HARD tiers that contain the ambiguous regime the task actually cares about.

Splits (BY IP / BY DESIGN — never random)

Split	Examples	Positives	Source
train	35,667	3,963	22 OpenTitan IPs (regtool-generated headers)
train_hard	35,667	~3,963	train with define names rewritten by a lexicon-grounded mutator (label-blind)
train_plus_hard	71,334	~7,926	union of the two (the actual training input)
val / val_hard	5,859 each	651 each	2 held-out OpenTitan IPs (hmac, usbdev); hard uses a DISJOINT lexicon partition
test_caliptra	24,552	2,728	Caliptra — a different design, register language (SystemRDL), and generator (PeakRDL)
test_hard	26,336	2,954	Caliptra mutations + HWE-Bench real merged-PR co-modification pairs + hand-labeled picorv32 pairs

Convention-family tiers (genuinely different naming conventions)

The splits above are dominated by ONE generator convention (OpenTitan regtool) plus one held-out design (Caliptra PeakRDL). These two tiers add genuinely different conventions from real, non-OpenTitan sources — the regime where convention-following labels stop being trivially token-encodable. Both are now BUILT and included (builders: evals/edge_dataset/build_litex_dataset.py, build_svd_dataset.py).

Split	Positives	Convention family	Source
litex_train	440	LiteX CSR_<MOD>_<REG>_ADDR (csr.json + csr.h)	REAL LiteX 2024.12 generated headers (litex_sim sim_vexriscv_eth + sim_picorv32_periph)
litex_test	116	LiteX (held-out config)	REAL LiteX 2024.12 (litex_sim sim_serv_video — SERV CPU + video peripheral held out)
svd_train	44,020	6 vendor conventions	REAL CMSIS-SVD paired against REAL downloaded vendor headers (STM32 F0/F1/F4/L4/F7, nRF51/52/52840, MK64F12 Kinetis, SAMD21)
svd_test	13,520	held-out vendors	REAL CMSIS-SVD from vendors NOT in train (RP2040, EFR32BG24, MSP432P401R)

The CMSIS-SVD tier spans 7 vendors / 6 naming conventions: ST/Nordic _Pos/_Msk, Kinetis _SHIFT/_MASK, MSP432 _OFS/bare mask, RP2040 _LSB/_BITS/_OFFSET, SiLabs _SHIFT/_MASK (leading underscore). Every SVD positive is anchored to a define that EXISTS in the real downloaded vendor header with value equality enforced (a build-time purity gate re-checks every emitted row); LiteX positives are value-equality-checked against csr.json ground truth. Unbound/unverifiable defines are excluded and counted, never guessed. Full per-device pairing/coverage accounting is in svd_stats.json.

v7 note: a v7 edge-classifier retrain on this diverse convention data PASSED its gate and is now the reference model — the first fine-tune to beat the frozen encoder rather than regress it (end-to-end joint BCE on the OpenTitan+LiteX+CMSIS-SVD union). See the reference-model table below.

Splits are partitioned by IP (train/val) and by design (test = Caliptra), so define-naming patterns never leak across the split boundary. The hard mutator's lexicon is partitioned so no word-pair transformation straddles train↔val. The LiteX and SVD tiers are held out by config (LiteX) and by vendor (SVD), so no convention leaks across their train/test boundary either.

Each example is one line of JSON: {"node_a": <artifact node>, "node_b": <define node>, "label": 0|1, "pair_kind": ..., "ip": ..., "negative_type": ...}. Negatives are ~8:1, mixed cross-IP / same-IP-wrong-register / same-register-wrong-field.

Benchmark tiers (report ALL of them)

1. Easy (test_caliptra): convention-following. Sanity/wiring check. A good model TIES the token baseline here (~0.99 AUC); "beating" it is not meaningful.
2. Hard — convention mutation (test_hard/convention_mutation): names rewritten to break the convention. This is where a model must add value over token overlap.
3. Hard — real co-modification (test_hard/hwe_bench): pairs mined from real merged PRs. The honest frontier.
4. Hard — hand-written (test_hard/picorv32): a real hand-written firmware header. Tiny (n=17) and near-chance for every scorer — reported for honesty, not as a headline.

Baseline and reference model

The reference scorer is models/edge_classifier_v7.pt in the Tapeout repo — an all-MiniLM-L6-v2 sentence encoder fine-tuned END-TO-END (jointly with its MLP head, under a single BCE classification loss) on the diverse OpenTitan+LiteX+CMSIS-SVD union. It is the FIRST fine-tune in the project to beat the frozen encoder rather than regress it. Honest results vs the token-containment baseline (full test_hard AUC; v6 = the prior frozen-encoder reference):

Tier	token_containment AUC	prior (v6) AUC	reference (v7) AUC
test_caliptra (easy)	0.9946	0.9942	0.9984
test_hard (overall)	0.9183	0.9660	0.9734
test_hard / convention_mutation	0.9568	0.9876	0.9921
test_hard / hwe_bench	0.8947	0.7992	0.8559
test_hard / picorv32 (n=17)	0.3857	0.6000	0.6286

Read this honestly: v7 beats the token baseline strongly on the hard tier overall and on convention mutations, and it substantially improves the real HWE-Bench co-modification tier over v6 (AUC 0.7992→0.8559, AP 0.4310→0.6721). But HWE-Bench is IMPROVED, not SOLVED — the token-containment baseline is still 0.8947 AUC there, ahead of v7's 0.8559 — and hand-written naming (picorv32, n=17, 0.60→0.629) stays within noise. Non-OpenTitan naming conventions remain an OPEN PROBLEM, narrowed not closed. The two levers earlier fine-tunes lacked — end-to-end training under the true classification objective (v3/v4/v5 used a proxy contrastive objective and all degraded) AND genuinely-different-convention data (CMSIS-SVD, LiteX; the convention-family tiers above) — are now VALIDATED in combination: v7 PASSED its gate and is the current reference model.

Honest counting

"100K+ examples" is reachable but the OpenTitan/Caliptra tiers are mostly same-convention inflation (≈30K positive ceiling × 8:1 negatives). The meaningful measures are positives and convention families, not raw rows. Those tiers are dominated by ONE generator convention (OpenTitan regtool) plus one held-out design (Caliptra PeakRDL). Genuinely different conventions (LiteX csr.json+csr.h, CMSIS-SVD XML) are now BUILT and included as the convention-family tiers above (builders: evals/edge_dataset/build_litex_dataset.py, evals/edge_dataset/build_svd_dataset.py) — LiteX adds 556 positives across held-out configs, CMSIS-SVD adds 57,540 positives across 7 vendors / 6 naming conventions with 3 vendors held out for test. (PULP re-uses OpenTitan's regtool verbatim — same convention, not cross-family — and bare cores like Ibex/CVA6 ship no register-description files to pair, so neither adds convention diversity.)

Related work

No existing HuggingFace dataset or EDA-ML benchmark does labeled register↔firmware-define relationship classification across naming conventions, to our knowledge. Adjacent work:

• SpecMap (arXiv 2601.11688) — the closest task: LLM-agent traceability-link recovery from datasheets to embedded C, covering macros/constants/register definitions. Different artifact pair (datasheet→code, not RDL/hjson→generated header); no public labeled-pair dataset found.
• HWE-Bench (arXiv 2604.14709, henryen/hwe-bench) — repository-level hardware bug repair; HIR consumes it as one held-out test source (real co-modification pairs). Its failure analysis names "cross-artifact coordination" as an open weakness. Distinct benchmark — hence HIR is NOT named "hwe-bench".
• Traceability Link Recovery (TLR) literature — HIR is a hardware-specific instance of TLR.
• EDA-ML datasets (ForgeEDA, OpenABC-D, CircuitNet) target netlist/PPA, not cross-artifact register↔firmware relationships.

Reproduce

See models/README.md (the v7 production section + the per-checkpoint regenerate blocks) in the Tapeout repository. The OpenTitan/Caliptra builders are evals/edge_dataset/build_dataset.py, expand_opentitan.py, and build_hard_dataset.py; the convention-family builders are evals/edge_dataset/build_litex_dataset.py (real LiteX csr.json+csr.h) and evals/edge_dataset/build_svd_dataset.py (real CMSIS-SVD against downloaded vendor headers via fetch_vendor_headers.sh). The honest evaluation is evals/edge_dataset/evaluate_matrix.py.

Provenance and licensing

Derived from OpenTitan (Apache-2.0), Caliptra (Apache-2.0), HWE-Bench, and picorv32 (ISC). Register descriptions and generated headers are transformed into labeled node pairs; original source files are not redistributed here. See datasets/CORPUS_NOTES.md and datasets/ACQUISITION_PLAN.md.

The LiteX convention-family tier is derived from LiteX-generated csr.json/csr.h (LiteX is permissively licensed); only transformed labeled node pairs are included, not the original headers.

The CMSIS-SVD convention-family tier is derived from vendor SVD files (via cmsis-svd-data) paired against vendor device headers. These vendor SVD/header files carry per-vendor licenses that vary. The derived labeled node pairs ARE included in this release with the maintainer's explicit acceptance of the per-vendor license terms; original vendor SVD/header files are NOT redistributed here (only transformed node pairs). Honest caveat for downstream users: if you redistribute or build on the SVD-derived pairs, you are responsible for checking the individual vendor SVD and header licenses (ST, Nordic, NXP/Kinetis, TI/MSP432, Raspberry Pi/RP2040, Silicon Labs, Atmel) for your own use case — the licenses are heterogeneous and not blanket-permissive.