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============================================================================== |
RTL-MP MACRO CLUSTERS (design: VeriGPU) |
============================================================================== |
1 macro clusters, 12 macros |
------------------------------------------------------------------------------ |
MACRO_CLUSTERS |
------------------------------------------------------------------------------ |
[ 44] <top>.p0.p0.p0.p1/macros |
type=Macro macro_count=12 macro_types={'small_mem': 12} |
inst_58676 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_58677 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_58678 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61847 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61848 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61849 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61850 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61851 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61852 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61853 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61854 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
inst_61855 type=small_mem size=75.56x149.125um orient=R0 pins=L38,R39,B10,T10 |
============================================================================== |
RTL-MP MACRO CLUSTERS (design: ariane133) |
============================================================================== |
14 macro clusters, 132 macros |
------------------------------------------------------------------------------ |
MACRO_CLUSTERS |
------------------------------------------------------------------------------ |
[137] i_cache_subsystem/i_icache/sram_block_0__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[139] i_cache_subsystem/i_icache/sram_block_1__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[141] i_cache_subsystem/i_icache/sram_block_2__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[143] i_cache_subsystem/i_icache/sram_block_3__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[145] i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[147] i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_0 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_1 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_2 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram/macro_mem_3 type=fakeram45_256x16 size=77.71x40.6um orient=R0 pins=L59,R0,B0,T0 |
------------------------------------------------------------------------------ |
[149] i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/macros |
type=Macro macro_count=8 macro_types={'fakeram45_256x16': 8} |
PlaceReasoner-Bench
An end-to-end macro-placement benchmark built entirely from open-source RTL, an open-source EDA flow, and an open technology node. Eight designs are each evaluated at 60% core utilization under two core aspect ratios (1:1 and 2:1), giving 16 placement tasks.
Used by OpenLayout, a multi-agent physical-design flow on OpenROAD.
Designs
| Design | Top module | #Macros | #Clusters | #Types | Clk (ns) |
|---|---|---|---|---|---|
| ariane133 | ariane |
133 | 14 | 1 | 4.0 |
| ariane81 | ariane |
81 | 8 | 6 | 4.0 |
| bp_be | bp_be_top |
10 | 3 | 3 | 2.6 |
| bp_fe | bp_fe_top |
11 | 4 | 3 | 1.8 |
| ethernet | eth_top |
64 | 2 | 1 | 8.0 |
| swerv_wrapper | swerv_wrapper |
28 | 3 | 3 | 2.0 |
| vga_lcd | vga_enh_top |
62 | 12 | 3 | 2.0 |
| VeriGPU | gpu_card |
12 | 1 | 1 | 1.2 |
| Total | 401 | 47 | -- | -- |
#Types counts distinct macro types; Clk is the target clock period.
Top module is the design top cell name, carried by both the DESIGN statement
in each DEF and the single (flattened) module in <design>.v — use it for
link_design / -top arguments. Note it differs from the directory name for
all but swerv_wrapper, and that ariane133 and ariane81 share the top name
ariane, so they must be kept in separate run directories.
Layout
Each design directory is self-contained:
<design>/
<design>.v gate-level netlist (flattened)
constraint.sdc timing constraints
lef/ tech LEF + macro LEFs (Nangate45, FakeRAM 2.0)
lib/ timing libraries
def/
1_1_u60_floorplan.def floorplan, aspect ratio 1:1 (ar1), 60% utilization
2_1_floorplan.def floorplan, aspect ratio 2:1 (ar2), 60% utilization
<design>_macro_clusters.txt macro cluster assignment
The two DEFs differ only in core geometry; both fix the die/core outline and IO pin placement, and leave macro locations to be determined. A placement method consumes the DEF plus the LEF/LIB/SDC and emits macro coordinates and orientations; everything downstream (standard-cell placement, CTS, routing, timing repair) is held identical across methods so that post-route differences are attributable to macro placement alone.
<design>_macro_clusters.txt gives a connectivity-based grouping of macros,
used as a soft placement constraint that encourages dataflow locality.
Usage
pip install huggingface_hub
hf download fenggev566/PlaceReasoner-Bench \
--repo-type dataset \
--local-dir Benchmark/PlaceReasoner-Bench
Or from Python:
from huggingface_hub import snapshot_download
snapshot_download(
repo_id="fenggev566/PlaceReasoner-Bench",
repo_type="dataset",
local_dir="Benchmark/PlaceReasoner-Bench",
)
To fetch a single design:
hf download fenggev566/PlaceReasoner-Bench \
--repo-type dataset --include "bp_fe/*" \
--local-dir Benchmark/PlaceReasoner-Bench
Provenance and licensing
- Designs and flow scaffolding derive from the open-source MacroPlacement testcases.
- Technology: Nangate45 open cell library (
NangateOpenCellLibrary.*). - Memory macros: FakeRAM 2.0 (
fakeram45_*). - Reference flow: Yosys for synthesis, OpenROAD for place-and-route.
All components are open source and redistributable, so the benchmark is fully
reproducible without commercial tools or proprietary PDKs. The constituent
parts carry their own upstream licenses (the RTL designs, the Nangate45
library, and the FakeRAM macros each have separate terms), which is why this
repository is tagged other rather than a single SPDX identifier — consult the
respective upstream projects before redistribution.
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