input stringlengths 193 2.76k | output stringlengths 18 91.5k |
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<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: FIFO module with simple read and write functionality [/INST]
| module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FI... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: SHA-256 Hash Transformation [/INST]
| module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: SHA-256 Digester [/INST]
| module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)],... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: AXI Processing System with Write and Read Channels [/INST]
| module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: "FIFO Module Implementation" [/INST]
| module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: AXI Protocol Converter [/INST]
| module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIG... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Bit manipulation module. [/INST]
| module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Bitwise XOR operation. [/INST]
| module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Bitwise operation. [/INST]
| module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Bitwise logic operation [/INST]
| module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Bit manipulations [/INST]
| module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Data manipulation [/INST]
| module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: FIFO Module Implementation [/INST]
| module axi_protocol_converter_v2_1_axi_protocol_converter #(
parameter C_FAMILY = "virtex6",
parameter integer C_M_AXI_PROTOCOL = 0,
parameter integer C_S_AXI_PROTOCOL = 0,
parameter integer C_IGNORE_ID = 0,
// 0 = RID/BID ar... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Arithmetic Control Module [/INST]
| module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overf... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: VGA module with wishbone signals, VGA pad signals, and CSR SRAM master interface. Includes registers, nets, and module instances. [/INST]
| module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
inpu... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Step generator and EPP interface [/INST]
| module main(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
input [15:0] din;
reg Spolarity;
re... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: AXI protocol converter [/INST]
| module axi_protocol_converter_v2_1_b2s_rd_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire ... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Rate Controller and Signal Processors [/INST]
| module ddc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_cordic_out, q_cordic_o... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Multiplexer module [/INST]
| module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Rotate Mux Array [/INST]
| module Rotate_Mux_Array
#(parameter SWR=26)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
output wire [SWR-1:0] Data_o
);
genvar j;//Create a variable for the loop FOR
generate for (j=0; j <= SWR-1; j=j+1) begin // generate enough Multiplexers modules for each bit
case (j)
SWR-1-j:be... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: AXI Protocol Converter [/INST]
| module axi_protocol_converter_v2_1_a_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIG... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Quadrature Decoder Module [/INST]
| module quad(clk, A, B, Z, zr, out);
parameter W=14;
input clk, A, B, Z, zr;
reg [(W-1):0] c, i; reg zl;
output [2*W:0] out = { zl, i, c };
// reg [(W-1):0] c, i; reg zl;
reg [2:0] Ad, Bd;
reg [2:0] Zc;
always @(posedge clk) Ad <= {Ad[1:0], A};
always @(posedge clk) Bd <= {Bd[1:0], B};
wire good_one = &Zc;
wire good_z... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: AXI protocol converter [/INST]
| module axi_protocol_converter_v2_1_b2s_wr_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire ... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: module, increment, transaction [/INST]
| module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
///////////////////////////////////////////////////////////////////////////... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: State Logic Module [/INST]
| module STATE_LOGIC_v8_2 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Multiplexer with 2 inputs [/INST]
| module beh_vlog_muxf7_v8_2 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Flip-flop with clear functionality [/INST]
| module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Flip-flop module [/INST]
| module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Flip-flop with clear [/INST]
| module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Write Netlist Module [/INST]
| module write_netlist_v8_2
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AW... |
<s>[INST] <<SYS>>
I want you to act as an IC designer, and implement the following in Verilog.
<</SYS>>
Generate a Verilog module with the following description: Read Netlist Interface Module [/INST]
| module read_netlist_v8_2 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
... |
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