id stringlengths 21 52 | categories listlengths 2 2 | system_message stringlengths 1.55k 1.84k | prompt stringlengths 573 7.74k | context unknown | patch unknown | harness unknown |
|---|---|---|---|---|---|---|
hqbd_agentic_64b66b_codec_0007 | [
"cid013",
"medium"
] | You are a language model that has the following file operations available at your disposal:
- **List files in a directory** by running one of the following commands:
- `ls`
- `tree`
- **Read files** by using:
- `cat <filename>`
- **Write files** by using:
- `echo <content> > <filename>`
- **Com... | I have a SystemVerilog testbench named `tb_top_64b66b_codec` in the `verif` directory. It provides comprehensive stimulus to the `top_64b66b_codec` RTL module, which implements 64b/66b encoding and decoding functionality. The corresponding design specification can be found in the `docs/specification.md` file. The given... | {
"docs/specification.md": "# **64b/66b Codec Specification Document**\n\n## **1. Overview**\nThe 64b/66b encoding scheme is a line coding technique defined by the IEEE 802.3 standard for high-speed serial communication (e.g., 10GbE, PCIe). It addresses two primary transmission challenges:\n- **Clock recovery**: Ensu... | {
"verif/tb_top_64b66b_codec.sv": ""
} | {
"docker-compose.yml": "services:\n\n xrun:\n image: __VERIF_EDA_IMAGE__\n volumes:\n - ./src/:/src/:ro # Infrastructure location\n env_file : ./src/.env\n working_dir: /code/rundir\n command: pytest /src/process.py -v -s\n networks:\n - licnetwork\n\nnetworks:\n licnetwork:\n name... |
hqbd_agentic_8b10b_codec_0001 | [
"cid003",
"hard"
] | You are a language model that has the following file operations available at your disposal:
- **List files in a directory** by running one of the following commands:
- `ls`
- `tree`
- **Read files** by using:
- `cat <filename>`
- **Write files** by using:
- `echo <content> > <filename>`
- **C... | Based on the contents of specification `docs/decoder_specification.md`, implement a complete SystemVerilog RTL design for the decoder module and create an accompanying SystemVerilog testbench.
**RTL Module Implementation**
- **Specification:** Refer to `docs/decoder_specification.md` for detailed functional requirem... | {
"docs/decoder_specification.md": "# 8b10b Decoder Module Specification Document\n\n## 1. Introduction\n\nThe **8b10b Decoder Module (decoder_8b10b)** is a high-speed digital block designed to convert 10-bit encoded words into their corresponding 8-bit symbols. This conversion is essential in serial communication pr... | {
"rtl/decoder_8b10b.sv": "",
"verif/tb_decoder_8b10b.sv": ""
} | {
"docker-compose.yml": "services:\n\n direct:\n image: __OSS_SIM_IMAGE__\n volumes:\n - ./src/:/src/:ro # Infrastructure location\n working_dir : /code/rundir \n env_file : ./src/.env\n command : pytest -s --log-cli-level=INFO -o cache_dir=/rundir/harness/.cache /src/test_runner.py -v\n ... |
hqbd_agentic_AES_encryption_decryption_0020 | [
"cid014",
"medium"
] | You are a language model that has the following file operations available at your disposal:
- **List files in a directory** by running one of the following commands:
- `ls`
- `tree`
- **Read files** by using:
- `cat <filename>`
- **Write files** by using:
- `echo <content> > <filename>`
- **Com... | I have a hierarchical AES encryption design with 3 main modules:
- `aes_enc_top` (top-level interface: key, mode, IV, counter, control),
- `aes_encrypt` (core round logic and key expansion).
- `sbox` (byte substitution in the AES rounds).
These modules are located in the `rtl` directory. Please enhance the design by a... | {
"rtl/aes_enc_top.sv": "module aes_enc_top #(\n parameter NBW_KEY = 'd256,\n parameter NBW_DATA = 'd128,\n parameter NBW_MODE = 'd3,\n parameter NBW_CNTR = 'd32\n) (\n input logic clk,\n input logic rst_async_n,\n input logic i_reset_counter,\n ... | {
"rtl/aes_enc_top.sv": "",
"rtl/aes_encrypt.sv": ""
} | {
"Dockerfile": "FROM __VERIF_EDA_IMAGE__\nRUN pip3 install cocotb==2.0.1",
"docker-compose.yml": "services:\n\n xrun:\n build: .\n volumes:\n - ./src/:/src/:ro # Infrastructure location\n env_file : ./src/.env\n working_dir: /code/rundir\n command: pytest /src/test_runner.py -v -s\n network... |
hqbd_agentic_Min_Hamming_Distance_Finder_0003 | [
"cid005",
"hard"
] | "You are a language model that has the following file operations available at your disposal:\n - **(...TRUNCATED) | "Extend the existing RTL folder that includes `Min_Hamming_Distance_Finder`(`rtl/Min_Hamming_Distanc(...TRUNCATED) | {"rtl/Bit_Difference_Counter.sv":"`timescale 1ns / 1ps\nmodule Bit_Difference_Counter\n#(\n param(...TRUNCATED) | {
"rtl/Adaptive_Binary_Pattern_Classifier.sv": "",
"verif/tb_Min_Hamming_Distance_Finder.sv": ""
} | {"Dockerfile":"FROM __OSS_SIM_IMAGE__\n\n# ----------------------------------------\n# - Install dep(...TRUNCATED) |
hqbd_agentic_Min_Hamming_Distance_Finder_0007 | [
"cid013",
"medium"
] | "You are a language model that has the following file operations available at your disposal:\n - **(...TRUNCATED) | "I have a SystemVerilog testbench `tb_Min_Hamming_Distance_Finder` for the `Min_Hamming_Distance_Fi(...TRUNCATED) | {"verif/tb_Min_Hamming_Distance_Finder.sv":"`timescale 1ns / 1ps\n\nmodule tb_Min_Hamming_Distance_F(...TRUNCATED) | {
"verif/tb_Min_Hamming_Distance_Finder.sv": ""
} | {"docker-compose.yml":"services:\n\n xrun:\n image: __VERIF_EDA_IMAGE__\n volumes:\n - .(...TRUNCATED) |
hqbd_agentic_alu_0003 | [
"cid014",
"medium"
] | "You are a language model that has the following file operations available at your disposal:\n - **(...TRUNCATED) | "I have an `alu_core` module available in the `rtl` directory, and its specification is in the `docs(...TRUNCATED) | {"docs/alu_core_specification.md":"# ALU Core Specification Document\n\n## Introduction\n\nThe **ALU(...TRUNCATED) | {
"rtl/alu_core.sv": ""
} | {"Dockerfile":"FROM __VERIF_EDA_IMAGE__\nRUN pip3 install cocotb==2.0.1\n","docker-compose.yml":"ser(...TRUNCATED) |
hqbd_agentic_alu_0007 | [
"cid013",
"medium"
] | " You are a language model that has the following file operations available at your disposal:\n - (...TRUNCATED) | "We currently have a SystemVerilog testbench `alu_core_tb.sv` in the `verif` directory that provides(...TRUNCATED) | {"docs/alu_core_specification.md":"# ALU Core Specification Document\n\n## Introduction\n\nThe **ALU(...TRUNCATED) | {
"verif/alu_core_tb.sv": ""
} | {"docker-compose.yml":"services:\n\n xrun:\n image: __VERIF_EDA_IMAGE__\n volumes:\n - .(...TRUNCATED) |
hqbd_agentic_async_fifo_compute_ram_application_0003 | [
"cid013",
"medium"
] | "You are a language model that has the following file operations available at your disposal:\n - **(...TRUNCATED) | "Create a self-checking test bench in SystemVerilog for a Verilog module named `async_fifo`. The **a(...TRUNCATED) | {"docs/fifo.md":"# Asynchronous FIFO Specification\n\n## 1. Overview\n\nThe **async_fifo** design is(...TRUNCATED) | {
"verif/async_fifo_tb.sv": ""
} | {"docker-compose.yml":"services:\n\n xrun:\n image: __VERIF_EDA_IMAGE__\n volumes:\n - .(...TRUNCATED) |
hqbd_agentic_async_fifo_compute_ram_application_0004 | [
"cid012",
"medium"
] | "You are a language model that has the following file operations available at your disposal:\n - **(...TRUNCATED) | "Create a test bench in SystemVerilog for a Verilog module named `async_fifo`. The **async_fifo** de(...TRUNCATED) | {"docs/fifo.md":"# Asynchronous FIFO Specification\n\n## 1. Overview\n\nThe **async_fifo** design is(...TRUNCATED) | {
"verif/tb_async_fifo.sv": ""
} | {"docker-compose.yml":"services:\n\n xrun:\n image: __VERIF_EDA_IMAGE__\n volumes:\n - .(...TRUNCATED) |
hqbd_agentic_axi4lite_to_pcie_config_0005 | [
"cid014",
"medium"
] | "You are a language model that has the following file operations available at your disposal:\n - **(...TRUNCATED) | "I have a AXI4Lite to PCIe config module `axi4lite_to_pcie_cfg_bridge.sv` available in the `rtl` dir(...TRUNCATED) | {"rtl/axi4lite_to_pcie_cfg_bridge.sv":"`timescale 1ns/1ps\n\nmodule axi4lite_to_pcie_cfg_bridge #(\n(...TRUNCATED) | {
"rtl/axi4lite_to_pcie_cfg_bridge.sv": ""
} | {"Dockerfile":"FROM __VERIF_EDA_IMAGE__\nRUN pip3 install cocotb==2.0.1\nRUN pip3 install coverage",(...TRUNCATED) |
End of preview. Expand in Data Studio
Important: see the files listed above for the current HQBD package contents.
HQBD v0.0.1 is a lightweight CVDP-style benchmark dataset package for hardware/RTL design and verification tasks.
The full HQBD dataset package, including the heavy Git bundle payloads, is hosted on HuggingFace at https://huggingface.co/datasets/cherrytreetree/HQBD. The documentation, contribution guidance, helper tools, and benchmark-integration notes are provided as part of the HQBD dataset package.
This release is derived from CVDP v1.1.0 and repackages it under HQBD v0.0.1 file, directory, and case ID naming for dataset organization. CVDP content and third-party-derived content are not relicensed as HQBD original content. The original CVDP v1.1.0 LICENSE, NOTICE, and CHANGELOG are preserved under hqbd_v0.0.1/.
Please see LICENSE, NOTICE, hqbd_v0.0.1/LICENSE, and hqbd_v0.0.1/NOTICE for licensing information. See CHANGELOG for changes.
User documentation
- docs/GETTING_STARTED.md: how to obtain HQBD, choose a split, install helper dependencies, and inspect the first testcase.
- docs/USAGE.md: JSONL task formats and common dataset-tool workflows.
- docs/CONTRIBUTING.md: how to contribute HQBD-original or derived cases, including ID, source, license, and validation requirements.
- docs/CLEANING.md: dataset cleaning policy for format, ID, source/license, harness, patch, heavy bundle, and benchmark checks.
- docs/BENCHMARK.md: how HQBD is intended to connect to an RTL benchmark runner.
- docs/dataset_format_usage_ip_report.md: comparison of dataset formats, HQBD usage tools, and source/license/IP guidance.
- reports/cleaning_report_v0.0.1.md: current v0.0.1 cleaning status and known limitations.
The JSONL case IDs have been renamed from cvdp_* to hqbd_*. The mapping from HQBD IDs to original CVDP IDs is provided in hqbd_v0.0.1/ID_MAPPING.csv. This renaming is an organizational transformation only; CVDP and third-party license and notice terms continue to apply.
Heavy bundle filenames and repository references have been renamed from cvdp_agentic_heavy_* to hqbd_agentic_heavy_* for HQBD organization. Original CVDP bundle filenames are preserved in hqbd_v0.0.1/BUNDLE_MAPPING.csv. If a .bundle file starts with version https://git-lfs.github.com/spec/v1, it is a Git LFS pointer rather than a usable Git bundle and run git lfs pull before running heavy tasks.
Tools
HQBD includes lightweight dataset helper tools under tools/ for inspecting testcases, analyzing dataset statistics, creating subsets, converting JSONL/YAML, and merging JSONL files. These tools are adapted from NVIDIA CVDP benchmark utilities and keep their original SPDX/Apache-2.0 headers. Python helper dependencies are listed in tools/requirements.txt.
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