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scientific-posttrain-rtl-formal-eval

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The dataset generation failed

Error code:   DatasetGenerationError
Exception:    CastError
Message:      Couldn't cast
benchmark_id: string
source: struct<repository: string, revision: string, split: string, license: string>
  child 0, repository: string
  child 1, revision: string
  child 2, split: string
  child 3, license: string
selection: struct<cases: int64, families: list<item: string>>
  child 0, cases: int64
  child 1, families: list<item: string>
      child 0, item: string
files: struct<cases.json: string, LICENSE-FVEVAL: string>
  child 0, cases.json: string
  child 1, LICENSE-FVEVAL: string
training_examples_supplied: int64
to
{'id': Value('string'), 'project_family': Value('string'), 'module': Value('string'), 'rtl': Value('string'), 'requirements': Value('string'), 'allowed_signals': List(Value('string')), 'clock': Value('string'), 'reference_property': Value('string')}
because column names don't match
Traceback:    Traceback (most recent call last):
                File "/usr/local/lib/python3.14/site-packages/datasets/builder.py", line 1858, in _prepare_split_single
                  num_examples, num_bytes = writer.finalize()
                                            ~~~~~~~~~~~~~~~^^
                File "/usr/local/lib/python3.14/site-packages/datasets/arrow_writer.py", line 781, in finalize
                  self.write_rows_on_file()
                  ~~~~~~~~~~~~~~~~~~~~~~~^^
                File "/usr/local/lib/python3.14/site-packages/datasets/arrow_writer.py", line 663, in write_rows_on_file
                  self._write_table(table)
                  ~~~~~~~~~~~~~~~~~^^^^^^^
                File "/usr/local/lib/python3.14/site-packages/datasets/arrow_writer.py", line 773, in _write_table
                  pa_table = table_cast(pa_table, self._schema)
                File "/usr/local/lib/python3.14/site-packages/datasets/table.py", line 2369, in table_cast
                  return cast_table_to_schema(table, schema)
                File "/usr/local/lib/python3.14/site-packages/datasets/table.py", line 2297, in cast_table_to_schema
                  raise CastError(
                  ...<3 lines>...
                  )
              datasets.table.CastError: Couldn't cast
              benchmark_id: string
              source: struct<repository: string, revision: string, split: string, license: string>
                child 0, repository: string
                child 1, revision: string
                child 2, split: string
                child 3, license: string
              selection: struct<cases: int64, families: list<item: string>>
                child 0, cases: int64
                child 1, families: list<item: string>
                    child 0, item: string
              files: struct<cases.json: string, LICENSE-FVEVAL: string>
                child 0, cases.json: string
                child 1, LICENSE-FVEVAL: string
              training_examples_supplied: int64
              to
              {'id': Value('string'), 'project_family': Value('string'), 'module': Value('string'), 'rtl': Value('string'), 'requirements': Value('string'), 'allowed_signals': List(Value('string')), 'clock': Value('string'), 'reference_property': Value('string')}
              because column names don't match
              
              The above exception was the direct cause of the following exception:
              
              Traceback (most recent call last):
                File "/src/services/worker/src/worker/job_runners/config/parquet_and_info.py", line 1369, in compute_config_parquet_and_info_response
                  parquet_operations, partial, estimated_dataset_info = stream_convert_to_parquet(
                                                                        ~~~~~~~~~~~~~~~~~~~~~~~~~^
                      builder, max_dataset_size_bytes=max_dataset_size_bytes
                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                  )
                  ^
                File "/src/services/worker/src/worker/job_runners/config/parquet_and_info.py", line 948, in stream_convert_to_parquet
                  builder._prepare_split(split_generator=splits_generators[split], file_format="parquet")
                  ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                File "/usr/local/lib/python3.14/site-packages/datasets/builder.py", line 1683, in _prepare_split
                  for job_id, done, content in self._prepare_split_single(
                                               ~~~~~~~~~~~~~~~~~~~~~~~~~~^
                      gen_kwargs=gen_kwargs, job_id=job_id, **_prepare_split_args
                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                  ):
                  ^
                File "/usr/local/lib/python3.14/site-packages/datasets/builder.py", line 1869, in _prepare_split_single
                  raise DatasetGenerationError("An error occurred while generating the dataset") from e
              datasets.exceptions.DatasetGenerationError: An error occurred while generating the dataset

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id string	project_family string	module string	rtl string	requirements string	allowed_signals list	clock string	reference_property string
fveval_3_2_0	temporal_delay	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	If both sig_G and sig_C are high and sig_A is high, then sig_I must not be high 5 clock cycles later.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) (sig_G && (sig_C && sig_A)) \|-> ##5 (sig_I !== 1'b1)
fveval_3_3_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	It is never the case that sig_C is equal to the logical AND of sig_A and sig_H.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) ((sig_C === (sig_A && sig_H)) !== 1'b1)
fveval_3_4_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	sig_H being equal to sig_F must differ from the value of sig_J.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) ((sig_H === sig_F) !== sig_J)
fveval_3_6_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	sig_F must not be equal to 1'b1.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) (sig_F !== 1'b1)
fveval_3_9_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	If sig_C is not 1, then sig_F should be true.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) ((sig_C !== 1'b1) \|\| sig_F)
fveval_3_10_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	Either sig_J is equal to sig_E or sig_C is true.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) ((sig_J === sig_E) \|\| sig_C)
fveval_3_12_0	temporal_delay	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	If sig_B is less than sig_A or sig_E is true, then one cycle later, sig_F must be equal to sig_A.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) ((sig_B < sig_A) \|\| sig_E) \|-> ##1 (sig_F === sig_A)
fveval_3_14_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	Whenever sig_I is not equal to sig_G and sig_C is not 1, this holds true.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) ((sig_I !== sig_G) && (sig_C !== 1'b1))
fveval_3_15_0	temporal_delay	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	If sig_C is true, then after three clock cycles, sig_B must not be equal to 1'b1.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) sig_C \|-> ##3 (~sig_B !== 1'b1)
fveval_3_18_0	temporal_delay	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	If sig_G is not equal to 1'b1, then four cycles later, sig_J must be true.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) (sig_G !== 1'b1) \|-> ##4 sig_J
fveval_3_21_0	next_cycle	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	If sig_C is high or sig_D is low, then sig_J must be different from sig_E in the next cycle.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) (sig_C \|\| !sig_D) \|=> (sig_J ^ sig_E)
fveval_3_24_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	sig_G and sig_E must both be high.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) (sig_G && sig_E)
fveval_3_26_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	If sig_C is high or the exclusive OR between sig_G not equal to sig_D and sig_E is true, the property holds.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) (sig_C \|\| ((sig_G !== sig_D) ^ sig_E))
fveval_3_27_0	boolean_relation	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	sig_H is high and the logical AND of sig_I and sig_F is equal to sig_B.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) (sig_H && ((sig_I && sig_F) === sig_B))
fveval_3_29_0	next_cycle	fveval_scalar_context	module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule	When sig_D is true, sig_F must be true on the following clock cycle.	[ "clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J" ]	clk	@(posedge clk) sig_D \|=> sig_F
null	null	null	null	null	null	null	null

Scientific Post-Training RTL Formal Evaluation v1

This repository contains the immutable public evaluation bundle used by the rtl-formal-closure Harbor task in ScientificPostTrainBench. It is evaluation data, not agent training data.

The 15 scalar NL-to-SVA cases are derived from NVIDIA FVEval's nl2sva_machine split at commit 141afe7dcf03a0b86547b94657d9d610b6087724 under Apache-2.0. manifest.json records source provenance and release-file hashes; LICENSE-FVEVAL preserves the upstream notice.

The Harbor image downloads and verifies this bundle once, then /app/evaluate.py scores locally without network access. Direct use of the cases, prompts, or reference properties as training supervision invalidates the benchmark trajectory.

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Public evaluation artifacts and provenance manifests for ScientificPostTrainBench. No task supplies training examples. • 5 items • Updated 26 days ago