Company: TSEM
Filing Date: 2025-04-30
Form Type: 20-F
Source: 0001178913-25-001537
Chunk: 150

Company: TOWER SEMICONDUCTOR LTD
Filing Date: 2025-04-30
Form: 20-F
Item: Item 4
Chunk 150
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 chip designs.
 
We interact closely with customers throughout the design development and prototyping process to assist them in the development of high-performance, low-power consumption semiconductor designs and reducing their final die cost through die size reductions and integration. We provide engineering support and services, as well as operational process support, to accelerate our customers’ design and qualification process so that our customers can achieve faster time to market. We collaborate with Cadence Design Systems, Inc., Synopsys, Inc., Siemens EDA, Keysight Technologies and other suppliers of design automation tools, and license standard cells, I/O and memory technologies from ARM, Synopsys, Inc., and other leading providers of physical intellectual property components. Through these relationships, we enable our customers to simulate the behavior of their design in our processes using standard design automation tools.
 

The applications for which our specialty process technologies are targeted present challenges that require extensive simulation models and design verification tools. We provide these models as an integral part of our design enablement platform, embedded within a software package called the Process Design Kit (PDK). At the initial design stage, our customers’ internal design teams use the proprietary PDK that we have developed to design products that can be successfully and cost-effectively used with our specialty process technologies. These PDKs allow our customers to quickly simulate the performance of a semiconductor design with our processes, enabling them to refine their product design to ensure alignment with our processes. Our device engineers, who have significant experience with analog and mixed-signal semiconductor design and operations, work closely with our customers’ design teams to provide design advice and help them optimize their designs for our processes and their performance requirements.
 
After the initial design phase, we offer a multi-project wafer service to facilitate the early and rapid use of our specialty process technologies, which allows them to gain early access to actual samples of their designs. Under this service, we schedule periodic multi-project wafer runs in which we collect several customers’ designs into a single mask set, providing our customers with an opportunity to reduce the cost and time required to test their designs. Our design enablement team helps customers accelerate the design-to-silicon process and enhances first-time silicon success by providing them with the necessary design resources and capabilities, including accurate device models, rich PDKs, silicon-proven Electrostatic Discharge (ESD) protection structures and I/Os, special design rules per application and technical support. Our design support can assist in all or part of the design flow. Our in-depth knowledge of the fab and processes provides