Company: AIP
Filing Date: 2025-02-18
Form Type: 10-K
Source: 0001667011-25-000010
Chunk: 23

Company: Arteris, Inc.
Filing Date: 2025-02-18
Form: 10-K
Item: Item 1
Chunk 23
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 implementation and floorplan of the target SoC in order to generate a design that meets physical implementation requirements in terms of timing, area and power;

■Sophisticated design verification methodologies to ensure the quality of configurable interconnect IP across millions of possible combinations, as well as complex test benches for simulation and emulation;

■In-depth knowledge of common interface protocols, graph theory, data models and graphical user interfaces;

■In-depth knowledge of safety standards including ISO 26262 ASIL B/D for automotive, IEEE 1685 IP-XACT IP standard for IP and SoC packaging, IEEE 1800 UVM verification standard; and

■Support a broad ecosystem of processors suppliers, other IP vendors, SoC design tool software providers, semiconductor foundries, and others.

SoC integration automation development is similarly challenging as it requires broad support of the IP packaging standard, IEEE 1685 IP-XACT, and the ability to deliver features and enhancements required as customers deploy ever-changing IP block libraries for their SoC projects, address hardware-software integrations. Our SIA solutions have to conform not only to industry standards, but also to ever-evolving SoC integration methodologies.

Once interconnect IP is designed into customer SoC projects, there are significant switching costs to adopting different interconnect IP and SIA solutions, especially in the automotive sector where switching interconnect IP solutions may involve product functional safety re-certification.

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Our research and development strategy includes offering customers several product enhancement releases per year, complemented with a planned introduction of at least one new interconnect IP or SIA product every year.

We believe we have assembled one of the premier engineering teams for interconnect IP development and SIA in the world. As of December 31, 2024, we had 105 engineers devoted to interconnect IP development and 54 engineers devoted to SIA solutions totaling 159 employees. In 2024, we spent $45.0 million on research and development, which represented 78% of our revenue.

Competition

For interconnect IP, we primarily compete with interconnect solutions developed internally by our SoC customers and potential customers. Many of the largest semiconductor companies have their own interconnect IP development teams which make customer penetration relatively difficult, time-consuming, and expensive. However, we believe that over time the expense and difficulty of developing a broad suite of interconnect IP and SoC integration automation has the potential to expand the use of commercial SoC integration solutions. In addition, we also compete with third-party