Company: AIP
Filing Date: 2025-02-18
Form Type: 10-K
Source: 0001667011-25-000010
Chunk: 16

Company: Arteris, Inc.
Filing Date: 2025-02-18
Form: 10-K
Item: Item 1
Chunk 16
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 SIA and interconnect IP products. By offering an unbiased, standards-based interconnect infrastructure to which other IP vendors can connect, and supporting a broad range of transaction protocols, we believe we have simplified the industry’s development of heterogeneous SoCs while solidifying our role as a neutral, technology-agnostic provider across the semiconductor industry. In addition to on-chip integrations with partners, we work with EDA companies such as Synopsys, Cadence and Siemens to provide prepackaged interfaces to their EDA tools such as simulators, modeling systems, and logic and physical synthesis tools. By working closely with semiconductor IP and EDA leaders, some of whom compete with each other, we believe we have established credibility as a trusted enabler for the integration of their products within our joint customers’ chips and design flows.

■We believe we benefit from distinct competitive advantages. We believe our interconnect IP technology benefits from barriers to entry due to our many years of experience and the strength of our proprietary solutions, as well as the significant technical expertise and research costs required to develop a competitive product. We were founded in 2003 when we believe we helped pioneer the industry’s NoC interconnect IP and have maintained our competitive position with our global team of 159 hardware and software engineers as of December 31, 2024. Developing interconnect IP requires an interdisciplinary engineering team with expertise and skill sets across a wide range of sciences and domains as well as a deep understanding of semiconductor physical design, design methodologies, and networking architectures. Building such teams and keeping them together over long periods of time presents a challenge for many companies. Additionally, strategic patience and focus are required to participate in the market. For example, we believe that the customer acquisition process has a typical duration of two to nine months; following this, a customer’s chip design cycle is typically between one to three years. Customers typically start shipping their products containing our interconnect IP solutions between one to five years following completion of their product design, known as mass production at which point we start to receive royalties; this lasts for up to seven years or longer depending on the particular market. We also leverage our long history of interconnect IP design to deliver customer-specific features, further deepening our relationship and integration with the customer’s product. With our System IP products embedded in our customers’ SoCs, there are significant switching costs in moving to alternative solutions. We believe that our product quality and technical strength have enabled our high customer retention rate.

■We offer global support for our System IP