Company: AIP
Filing Date: 2025-02-18
Form Type: 10-K
Source: 0001667011-25-000010
Chunk: 108

Company: Arteris, Inc.
Filing Date: 2025-02-18
Form: 10-K
Item: Item 7
Chunk 108
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Table of Contents

Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations

The following discussion and analysis of our financial condition and results of operations should be read in conjunction with our consolidated financial statements and related notes included under Part II, Item 8 in this Annual Report on Form 10-K. This discussion and analysis contains forward-looking statements based upon current beliefs, plans and expectations that involve risks, uncertainties and assumptions, such as statements regarding our plans, objectives, expectations, intentions and projections. Our actual results and the timing of selected events could differ materially from those anticipated in these forward-looking statements as a result of several factors, including those set forth under the heading “Risk Factors” and elsewhere in this Annual Report on Form 10-K. You should carefully read the “Risk Factors” section of this Annual Report on Form 10-K to gain an understanding of the important factors that could cause actual results to differ materially from forward-looking statements. Please also see the section under the heading “Cautionary Note Regarding Forward-Looking Statements.”

Unless the context otherwise requires, all references in this report to “we,” “us,” “our,” the “Company,” and “Arteris” refer to Arteris, Inc. and its subsidiaries.

Overview

We are a leading provider of semiconductor system IP, including interconnect and other intellectual property, (collectively, System IP) technology. Our System IP technology manages the on-chip communications and IP block deployments in System-on-Chip (SoC) semiconductors and systems of chiplets. Our leading proprietary System IP solutions achieve this by connecting client IP blocks such as processors, memories, artificial intelligence/machine learning (AI/ML) accelerators, graphics subsystems, safety and security, and other input/output subsystems (I/Os) via multiple Networks-on-Chips (NoCs) in order for our customers to experience faster SoC targeting, as well as, more efficient, and lower cost solutions. Growth for our solutions is being driven by growing SoC sophistication and associated complexity, now extending into disaggregation of SoCs into systems which implement the communication protocol aspects and partner with industry leading providers like Synopsys, Cadence, Alphawave and others to connect to their die-to-die interfaces. The addition of more processors, channels of memory access, machine learning sections, additional I/Os interface standards, and other subsystems within SoCs is driving the need for more advanced System IP