Company: SNPS
Filing Date: 2025-12-22
Form Type: 10-K
Source: 0000883241-25-000028
Chunk: 17

Company: SYNOPSYS INC
Filing Date: 2025-12-22
Form: 10-K
Item: Item 1
Chunk 17
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 extraction, IC ValidatorTM physical verification and 3DIC Compiler, the industry’s only unified exploration-to-signoff platform for multi-die/package co-design and co-optimization, aimed at enabling customers to integrate multiple dies in a single package. 

Our Custom Design Family is a unified suite of design and verification tools that accelerates the transistor-level design of robust analog, mixed-signal, and custom-digital ICs. This product family features visually assisted layout automation, high-performance circuit simulation, reliability-aware verification, and natively integrated parasitic RC extraction and physical verification. It includes Custom CompilerTM layout and schematic editor, StarRC parasitic extraction, IC Validator physical verification and PrimeSimTM. The PrimeSim solution provides a unified workflow of next-generation simulation technologies to accelerate the design and signoff of IC designs including PrimeSim SPICE, PrimeSimPro, PrimeSim HSPICETM and PrimeSimXA. The PrimeWaveTM design environment provides comprehensive analysis and improved productivity and ease of use across all tools in PrimeSim.

Our Silicon Lifecycle Management (SLM) family of products improves silicon health and operational metrics at every phase of the device lifecycle. This family of products is built on a foundation of enriched in-chip observability, analytics and integrated automation. Synopsys' SLM in-chip monitoring enables deep insights from silicon to systems by providing meaningful data for continuous analysis and actionable feedback. The solution is integrated with the Digital Design Family for design calibration and analytics and includes Yield Explorer® for product ramp analytics, Silicon.da for AI-driven test and production analytics, TestMAX ALE (adaptive learning engine) for intelligent data extraction and communication to the SLM database and PVT IP for in-chip monitoring and sensing.

FPGA Design

FPGAs are complex chips that can be customized or programmed to perform a specific function after they are manufactured. For the process of converting a high-level hardware description language design into an FPGA netlist, a process known as FPGA-logic synthesis, we offer Synplify® FPGA synthesis tools that provide fast runtime, performance, area optimization for cost and power reduction, multi-FPGA vendor support, and incremental synthesis capabilities for faster FPGA design development. 

Verification

Our Verification Family is built from our industry-leading verification technologies and provides virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug in a unified environment with verification IP, planning, and coverage technology. By providing consistent compile, runtime and debug environments across the flow of verification tasks and by enabling seamless transitions across