Company: AIP
Filing Date: 2025-02-18
Form Type: 10-K
Source: 0001667011-25-000010
Chunk: 7

Company: Arteris, Inc.
Filing Date: 2025-02-18
Form: 10-K
Item: Item 1
Chunk 7
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 further down the supply chain, such as system-level companies and automotive original equipment manufacturers (OEMs). Our SoC integration automation capabilities were significantly enhanced by our acquisitions of Magillem in 2020 and Semifore in 2022, complementing our interconnect IP solutions by helping to automate the customer configuration of its NoC IPs, the process of integrating and assembling all of the customer’s IP blocks into SoC hardware, and ensuring correct hardware-software integration for software development. Products incorporating our IP are used to carry important data inside today’s complex SoCs across a broad range of applications, including automotive, enterprise computing, communications, consumer electronics, and industrial markets. Our interconnect IP solutions can be found in multiple industry-standard designs supporting instruction set architectures such as x86, Arm, RISC-V, CEVA, Synopsys ARC, Cadence Tensilica and MIPS, as well as memory controllers, UCIe, BoW, and XSR controllers, I/O and a variety of IP subsystems, to enable customers to integrate such IP blocks with high levels of efficiency and performance. Our solutions enable customer innovation because they are configurable for each customer’s design flow and SoC development projects and have wide applicability for many types of SoCs. We estimate that our solutions have been incorporated into over three and a half billion production SoCs since inception.

Traditional on-chip communication methods, including bus and crossbar interconnect IPs, are generally inadequate in handling modern semiconductor communications, and even more so for sophisticated applications or more complex designs. Technological advancements have led to increasingly complex SoCs that integrate numerous functions into a single semiconductor device. Massive amounts of wires, challenging timing closure, and routing congestion lead to greater die area and chip cost. Increased transistor density and design frequencies create higher power consumption leading to heat dissipation challenges and shorter battery life for electronic devices. These challenges have significantly complicated SoC innovation and contributed to the increasing adoption of System IP, across the growing number of customer design starts coupled with the expanding number of NoC IPs used in current SoC.

We leveraged our extensive technical expertise to develop configurable IP for a new method for on-chip communication, the NoC, that has emerged over the past couple of decades to address these critical semiconductor development challenges. We accomplished this by pioneering the use of proprietary networking techniques for on-chip communications to remove the inherent architectural limitations of traditional on-chip communications, thereby improving ease of integration, performance, silicon area, and power consumption. In doing so,