Company: AIP
Filing Date: 2025-02-18
Form Type: 10-K
Source: 0001667011-25-000010
Chunk: 12

Company: Arteris, Inc.
Filing Date: 2025-02-18
Form: 10-K
Item: Item 1
Chunk 12
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, logistics, and consumer and business broadband. Already approaching the next generation network infrastructure, the industry has started the development of a roadmap towards 6G technology to be rolled out towards the end of this decade, with various 5G Advanced steps in-between.

We believe the transition to 5G and 6G will result in more stringent requirements for bandwidth, latency, and power consumption, making an easy-to-integrate, high performance and low power on-chip interconnect a critical requirement.

Other Applications and Technologies 

The consumer electronics and industrial markets are also expected to require increasingly complex chips primarily driven by the incorporation of AI/ML processing, particularly at the edge, increased use of 5G communications, and more stringent safety and security requirements. In addition, the chip market in these domains is sensitive to time-to-market pressures, which also generates the need for increased semiconductor design productivity and faster implementation as enhanced by sophisticated interconnect IP solutions. Our low-power features are valuable for battery life and power consumption in our targeted markets. 

Industry Challenges

Interconnect IP development is a challenging, time-consuming, and expensive process. The need for robust, maintainable interconnect technology becomes increasingly important as chip designs become more complex and larger in size, both driven by advances in semiconductor manufacturing technology. Key interconnect IP development requirements and challenges include:

■Deep technical expertise and knowledge. Interconnect development requires an interdisciplinary engineering team with expertise and skill sets across a wide-range of engineering and scientific domains including hardware architecture, design, verification, EDA-class software development, and SystemC modeling, as well as deep understanding of physical design, design methodologies and networking architectures. The design process requires expertise in developing advanced hardware architectures to handle data coherency and consistency across the interconnect to achieve a high-performance, low power implementation. The design process requires expertise in developing advanced hardware architectures, engineers that have an awareness of the physical implementation and floorplan of the target chip in order to generate an architecture that meets SoC requirements and in-depth knowledge of graph theory, common interface protocols, data models, and graphical user interfaces.

■High quality. Interconnect IP requires a systematic deployment of quality-oriented methodologies, as any customer-level problems in the interconnect will result in SoC project delays or even project failures. Engineering teams creating interconnects must invest heavily not only in skilled engineering resources to develop and verify, but also processes and methodologies that provide early indication of any potential quality issues.

■Safety standards. High reliability of the interconnect is a heightened