Company: AIP
Filing Date: 2025-02-18
Form Type: 10-K
Source: 0001667011-25-000010
Chunk: 19

Company: Arteris, Inc.
Filing Date: 2025-02-18
Form: 10-K
Item: Item 1
Chunk 19
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 from and writes to memory, into digital packets. Packetizing on-chip communications allows the interconnect to be configured for enhanced performance and simplifies the connections of on-chip IP blocks, similar to how the internet eases the simultaneous connectivity of large numbers of computing devices. FlexWay is targeted at simpler SoC while FlexNoC targets the mainstream application. We also provide optional add-on packages for FlexNoC and FlexWay, such as the resilience package, which provide on-chip data protection that enables customers to meet the ISO 26262 and IEC functional safety standards for markets like automotive, and a large design performance package that addresses highly scalable peer-to-peer on-chip communications required by large SoCs such as those which include machine learning neural networks. FlexNoC and FlexWay started shipping in 2011 and we estimate that our solutions have been incorporated into over three and a half billion production SoCs since inception. Our most recently announced product FlexGen builds upon the silicon-proven and physically aware FlexNoC IP to automate the creation of high-performance NoC designs. Supported by AI-driven automation, FlexGen reduces manual iteration providing expert-level NoC topologies. We believe these advancements are critical to meet the increasing computing demands of advanced technologies like AI, autonomous driving and cloud computing.

■Ncore: Silicon-proven, cache coherent interconnect IP product that provides scalable, configurable, and area-efficient features for use across multiple end markets. In an SoC, cache coherency is a special data traffic class that requires a corresponding coherent interconnect IP to manage it. In a multiprocessor system using shared memory, each processor has a local cache memory for efficiency, however, it is possible to end up with many copies of shared data in the system. One copy of the data may be in the main memory, whilst other copies may exist in one or more of the processor cache memories. When one of the copies of data is changed, the rest must also reflect that change. Ncore assists the timely propagation of data changes across the SoC in order to maintain cache coherency. Ncore is also more scalable and area-efficient than mesh-based interconnects and is optimized for heterogeneous cache coherent systems and offers multiple configurable snoop filters, multiple configurable proxy caches, and a modular, distributed architecture to provide system architects with the most advanced technology and more degrees of freedom to innovate. Since the initial shipment in 2016, we have launched multiple releases of Ncore which have been designed into various production SoCs for automotive,