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//-----------------------------------------------------------------------------
//
// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and
// international copyright and other intellectual p... |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and
// international copyright and other intellectual p... |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and
// international copyright and other intellectual p... |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and
// international copyright and other intellectual p... |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and
// international copyright and other intellectual p... |
`timescale 1ns / 1ps
module ps2_tx(
input clk,rst_n,
input wr_ps2,
input[7:0] din,
inout ps2d,ps2c,
output reg tx_idle,tx_done_tick
);
//FSM state declarations
localparam[2:0] idle=3'd0,
rts=3'd1,
start=3'd2,
data=3'd3,
stop=3'd4;
reg[2:0] state_reg,state_nxt;
reg[12:0] cou... |
`timescale 1ns / 1ps
module debounce_explicit(
input clk,rst_n,
input sw,
output reg db_level,db_tick
);
//FSM symbolic declaration
localparam[1:0] idle=2'b00,
delay0=2'b01,
one=2'b10,
delay1=2'b11;
localparam N=21; //21 bits is 42ms -> 2^N/50MHz=42ms
reg[1:0] state_reg,state_nxt;
... |
`timescale 1ns / 1ps
module ps2_rx(
input clk,rst_n,
input rx_en,
input ps2d,ps2c,
output[10:0] dout, //startbit,8databits,paritybit,stopbit
output reg rx_done_tick
);
//FSM state declarations
localparam[1:0] idle=2'd0,
scan=2'd1,
done=2'd2;
reg[1:0] state_reg,state_nxt;
reg[10:0] data_r... |
`timescale 1ns / 1ps
module vga_core(
input clk,rst_n, //clock must be 25MHz for 640x480
output hsync,vsync,
output reg video_on,
output[11:0] pixel_x,pixel_y
);
//640x480 parameters
localparam HD=640, //Horizontal Display
HR=16, //Right Border
HRet=96, //Horizontal Retrace
HL=48, //Left B... |
`timescale 1ns / 1ps
module vga_test_pattern(
input key,
input video_on,
input[11:0] pixel_x,pixel_y,
output reg[4:0] r,
output reg[5:0] g,
output reg[4:0] b
);
//640x480 resolution
localparam SCREEN_LENGTH=640,
SCREEN_WIDTH=480,
LENGTH=SCREEN_LENGTH/8,
WIDTH=SCREEN_WIDTH/8;
... |
`timescale 1ns / 1ps
module vga_core_800x600(
input clk,rst_n, //clock must be 50MHz for 640x480
output hsync,vsync,
output reg video_on,
output[11:0] pixel_x,pixel_y
);
//800x600 parameters
localparam HD=800, //Horizontal Display
HR=64, //Right Border
HRet=120, //Horizontal Retrace
HL... |
// ROM with synchonous read (inferring Block RAM)
// character ROM
// - 8-by-16 (8-by-2^4) font
// - 128 (2^7) characters
// - ROM size: 2048-by-8 (2^11-by-8) bits
// 16K bits: 1 BRAM(perfectly fit)
module font_rom
(
input wire clk,
input wire [10:0] addr, //[10:4] for ASCII char code, [3:0]... |
`timescale 1ns / 1ps
module ascii_conv( //converts the real data from kb module to ASCII
input[8:0] rd_data,
output reg[7:0] ascii
);
always @* begin
ascii=0;
case(rd_data)
{1'b0,8'h45}: ascii = 8'h30; //0
{1'b0,8'h16}: ascii = 8'h31; //1
{1'b0,8'h1e}: ascii = 8'h32; //2
{1'b0,8'h26}: ascii = 8'... |
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