code string | source string | file string |
|---|---|---|
module apb_slave_fsm(
input wire PCLK,
input wire PRESETn,
input wire PADDR,
input wire PWRITE,
input wire PWDATA,
output wire PRDATA
);
reg [31:0] addr;
reg [31:0] data;
reg [31:0] prdata;
reg [1:0] state;
always @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn) begin... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module apb_slave_fsm(
input wire PCLK,
input wire PRESETn,
input wire PADDR,
input wire PWRITE,
input wire PWDATA,
output wire PRDATA
);
reg [31:0] addr;
reg [31:0] data;
reg [31:0] prdata;
reg [1:0] state;
always @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn) begin... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module WatchdogTimer(
input wire clk,
input wire reset,
input wire kick,
output reg reset_out
);
parameter MAX_VALUE = 100; // Maximum value of the watchdog timer
parameter WINDOW_SIZE = 10; // Window size for the watchdog timer
parameter MAX_VALUE_WIDTH = $clog2(MAX_VALUE + 1); // Width of t... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module carry_skip_block_4bit (
input wire [3:0] A, B,
input wire cin,
output wire [3:0] sum,
output wire cout,
output wire G, P
);
// Internal wires for carry chain
wire [3:0] carry_in;
wire [3:0] partial_sum;
// Compute generate (G) and propagate (P) for MSB (wires, not reg)
a... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module kogge_stone_adder #(
parameter N = 8 // Number of input bits (must be power of 2)
) (
input wire [N-1:0] A, // First input
input wire [N-1:0] B, // Second input
input wire Cin, // Carry-in
output wire [N-1:0] Sum, // Sum output
output wire Cout // Carry... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module dadda_multiplier_16bit (
input wire [15:0] A, // 16-bit multiplicand
input wire [15:0] B, // 16-bit multiplier
output reg [31:0] P // 32-bit product
);
// Partial product generation (16x16 = 256 bits, but we only need 32 bits)
wire [255:0] partial_products;
// Generate partial... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module dadda_multiplier_16bit (
input wire [15:0] A, // 16-bit multiplicand
input wire [15:0] B, // 16-bit multiplier
output wire [31:0] P // 32-bit product (now a wire)
);
// Partial product generation (16x16 = 256 bits)
wire [255:0] partial_products;
genvar i, j;
for (i = 0; i < 16; i = i + 1)... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module manchester_adder_16bit (
input wire [15:0] A, // 16-bit input A
input wire [15:0] B, // 16-bit input B
input wire Cin, // Carry-in
output reg [15:0] Sum, // 16-bit sum output
output reg Cout // Carry-out
);
// Internal wires for combinational logic
wire [15:0] par... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module radix8_booth_multiplier #(
parameter WIDTH_A = 8, // Multiplicand width (A)
parameter WIDTH_B = 9 // Multiplier width (B), must be divisible by 3
) (
input wire clk,
input wire reset,
input wire [WIDTH_A-1:0] A, // Multiplicand
input wire [WIDTH_B-1:0] B, // Multiplier
output... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module restoring_divider (
input wire clk,
input wire reset,
input wire start,
input wire signed [15:0] dividend, // Signed 16-bit dividend
input wire signed [15:0] divisor, // Signed 16-bit divisor
output reg signed [15:0] quotient, // Signed 16-bit quotient
output reg done, ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module mac_unit #(
parameter A_WIDTH = 8,
parameter B_WIDTH = 8,
parameter ACC_WIDTH = 16
) (
input wire signed [A_WIDTH-1:0] A,
input wire signed [B_WIDTH-1:0] B,
input wire signed [ACC_WIDTH-1:0] accumulator,
output reg signed [ACC_WIDTH-1:0] result
);
// Compute product (A × B)
w... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module mac_unit #(
parameter A_WIDTH = 8,
parameter B_WIDTH = 8,
parameter ACC_WIDTH = 16
) (
input wire signed [A_WIDTH-1:0] A,
input wire signed [B_WIDTH-1:0] B,
input wire signed [ACC_WIDTH-1:0] accumulator,
output wire signed [ACC_WIDTH-1:0] result
);
// Compute product (A × B)
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module srt_divider (
input wire clk,
input wire reset,
input wire start,
input wire [7:0] dividend, // Dividend (A)
input wire [7:0] divisor, // Divisor (B)
output wire [7:0] quotient, // Quotient (Q)
output wire [7:0] remainder // Remainder (R)
);
// Internal registers
reg [7... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module exponentiation_unit (
input wire [7:0] exponent, // 8-bit exponent (0 to 255)
output reg [31:0] result // 32-bit result
);
// Compute result = 2^exponent, capped at 32 bits
always_comb begin
if (exponent >= 32) begin
result = 32'h0; // Overflow: result is 0
end
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module exponentiation_unit (
input wire [7:0] exponent, // 8-bit exponent input
output reg [31:0] result // 32-bit result output
);
always @(*) begin
if (exponent >= 32) begin
result = 32'b0; // Overflow case
end
else begin
result = 1 << exponent; // Shift 1 left by exponent... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module popcount_adder_tree_optimized (
input wire [15:0] data,
output reg [3:0] popcount
);
// Treat each bit as a partial sum and add them all
assign popcount = data[0] + data[1] + data[2] + data[3] +
data[4] + data[5] + data[6] + data[7] +
data[8] + data[9... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module full_adder (
input wire a, b, cin,
output wire sum, cout // Changed to wire (no assign needed)
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module tzc_32bit (
input wire [31:0] x, // 32-bit input
output reg [4:0] tzc // 5-bit output (max count = 32)
);
// Initialize tzc to 32 (worst case: all zeros)
assign tzc = 32'b00000000000000000000000000000000;
// Check each bit from LSB to MSB
always @(*) begin
tzc = 0;
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module tzc_32bit (
input wire [31:0] x, // 32-bit input
output reg [4:0] tzc // 5-bit output (max count = 32)
);
always @(*) begin
tzc = 0; // Default: no trailing zeros (input has a '1' at x[0])
// Check each bit from LSB to MSB
if (x[0] == 1'b1) begin
tzc ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module manhattan_distance (
input wire [7:0] x1, y1, x2, y2,
output reg [8:0] distance
);
// Compute absolute difference for x coordinates
wire [7:0] diff_x = x1 - x2;
wire [7:0] abs_diff_x;
assign abs_diff_x = (diff_x > x1) ? (x2 - x1) : diff_x;
// Compute absolute difference for y coordi... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module manhattan_distance (
input wire [7:0] x1, y1, x2, y2,
output wire [8:0] distance // Changed from reg to wire
);
// Compute absolute difference for x coordinates
wire [7:0] diff_x = x1 - x2;
wire [7:0] abs_diff_x;
assign abs_diff_x = (diff_x > x1) ? (x2 - x1) : diff_x;
// Compute ab... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module sequence_detector (
input wire clk,
input wire reset,
input wire d, // Input bit stream
output reg detected // Output: '1' when '11001' is detected
);
// Define states
typedef enum logic [2:0] {
IDLE,
STATE_1,
STATE_11,
STATE_110,
STATE_1100,... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module sequence_detector (
input clk,
input reset,
input d, // Input bit stream
output reg detected // Output: '1' when '11001' is detected
);
// Define states using integers (Verilog-2001 compatible)
parameter IDLE = 3'b000;
parameter STATE_1 = 3'b001;
parameter STATE_11 = 3'b010;
parame... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module vending_machine (
input wire clk,
input wire reset,
input wire [1:0] coin, // 00:1c, 01:5c, 10:10c, 11:25c
output reg dispense,
output reg [2:0] change // Binary-coded change (e.g., 5c=010, 10c=101)
);
// State encoding
typedef enum logic [1:0] {
IDLE,
INSE... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module vending_machine (
input wire clk,
input wire reset,
input wire [1:0] coin, // 00:1c, 01:5c, 10:10c, 11:25c
output reg dispense,
output reg [2:0] change // Binary-coded change (e.g., 5c=010, 10c=101)
);
// State encoding (integer constants)
parameter IDLE = 2'b00;
param... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module pipeline_stall_flush_controller (
input wire clk,
input wire reset,
input wire branch_mispredicted,
input wire data_hazard_detected,
input wire pipeline_empty,
input wire refetch_done,
output reg stall_signal,
output reg flush_signal,
output reg refetch_signal
);
// State... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module pipeline_stall_flush_controller (
input wire clk,
input wire reset,
input wire branch_mispredicted,
input wire data_hazard_detected,
input wire pipeline_empty,
input wire refetch_done,
output reg stall_signal,
output reg flush_signal,
output reg refetch_signal
);
// State enc... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module round_robin_arbiter (
input wire clk,
input wire reset,
input wire [3:0] req, // 4 requestors
output reg [3:0] grant, // 4 grant signals
input wire [3:0] time_slice // Time slices for R0-R3
);
// State encoding (pure Verilog)
parameter IDLE = 0;
parameter GRANT_R0 =... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module carry_select_adder_4bit (
input wire [3:0] A, B, // 4-bit inputs
input wire C_in, // Carry-in (0 or 1)
output wire [3:0] Sum, // 4-bit sum (wire, not reg)
output wire C_out, // Carry-out (wire, not reg)
input wire [1:0] C_in_0, // Carry-in for the tw... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module brent_kung_adder #(
parameter N = 8 // Default 8-bit adder (can be parameterized)
) (
input wire [N-1:0] A,
input wire [N-1:0] B,
input wire C_in,
output reg [N-1:0] S,
output reg C_out
);
// Internal signals for G and P at each level
wire [N/2-1:0] G1, P1;
wire [N/4-1:0] G2... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module brent_kung_adder #(
parameter N = 8 // Default 8-bit adder (can be parameterized)
) (
input wire [N-1:0] A,
input wire [N-1:0] B,
input wire C_in,
output reg [N-1:0] S,
output reg C_out
);
// Internal signals for G and P at each level (must be wire)
wire [N/2-1:0] G1, P1;
wi... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module KoggeStoneAdder #(
parameter N = 8 // Number of bits (parameterized)
) (
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sum,
output wire Carry_out
);
// Generate (G) and Propagate (P) signals
wire [N-1:0] G, P;
assign G = A & B;
assign P = A ^ B;
// Partial... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module wallace_tree_multiplier (
input wire [7:0] A, // 8-bit multiplicand
input wire [7:0] B, // 8-bit multiplier
output reg [15:0] P // 16-bit product
);
// Partial product generation (8x8 array)
wire [8:0] partial_products [7:0][7:0];
genvar i, j;
generate
for (i = 0; i ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module wallace_tree_multiplier (
input wire [7:0] A, // 8-bit multiplicand
input wire [7:0] B, // 8-bit multiplier
output reg [15:0] P // 16-bit product
);
// Partial product generation (8x8 array)
wire [8:0] partial_products [7:0][7:0];
genvar i, j;
generate
for (i = 0; i < 8; i = i + 1) begi... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module full_adder (
input wire a, b, cin,
output wire sum, cout // Changed from reg to wire
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module mcc_2bit (
input wire [1:0] A,
input wire [1:0] B,
input wire C_in,
output wire [1:0] Sum,
output wire C_out
);
wire [1:0] S0, S1;
wire G, P;
// Calculate sums assuming C_in=0 and C_in=1
assign S0 = A ^ B;
assign S1 = A ^ B ^ 1'b1;
// Carry chain logic
assign G =... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module non_restoring_divider (
input wire clk,
input wire reset,
input wire start,
input wire [15:0] dividend,
input wire [15:0] divisor,
output reg [15:0] quotient,
output reg [15:0] remainder,
output reg done
);
// Internal signals
reg [15:0] temp_remainder;
reg [15:0] tem... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module non_restoring_divider (
input wire clk,
input wire reset,
input wire start,
input wire [15:0] dividend,
input wire [15:0] divisor,
output reg [15:0] quotient,
output reg [15:0] remainder,
output reg done
);
// Internal signals
reg [15:0] temp_remainder;
reg [15:0] tem... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module srt_divider_8bit (
input wire clk,
input wire rst,
input wire [7:0] dividend, // A (dividend)
input wire [7:0] divisor, // B (divisor, non-zero)
output reg [7:0] quotient, // Q (quotient)
output reg [7:0] remainder // R (remainder)
);
// Internal signals
reg [7:0] partial_r... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module goldschmidt_division #(
parameter DATA_WIDTH = 16, // Bit-width for X and Y
parameter ITERATIONS = 4, // Number of iterations
parameter OUTPUT_WIDTH = 32 // Bit-width for output (X/Y)
) (
input wire clk,
input wire reset,
input wire signed [DATA_WIDTH-1:0] X, // Dividend
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module mac_unit #(
parameter A_WIDTH = 16,
parameter B_WIDTH = 16,
parameter ACC_WIDTH = 32,
parameter SIGNED_A = 1'b0,
parameter SIGNED_B = 1'b0,
parameter SIGNED_ACC = 1'b1,
parameter USE_SATURATION = 1'b1
) (
input wire clk,
input wire reset,
input wire signed [A_WIDTH-1:0] A,... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module fp32_adder (
input wire clk,
input wire reset,
input wire [31:0] a,
input wire [31:0] b,
output reg [31:0] sum,
output reg overflow,
output reg underflow,
output reg invalid
);
// Extract sign, exponent, and mantissa
wire [1:0] sign_a = a[31:31] ? 2'b10 : 2'b01;
wire [7:0] exp_a ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module log2_approx_8bit (
input wire [7:0] x, // 8-bit input
output reg [7:0] log2_approx // Approximated log2(x)
);
// Leading Zero Counter (parallel implementation)
wire [2:0] lz_count;
wire [7:0] shifted_x;
// Shift x right until the MSB is 1 (parallel approach)
assign shifted_x ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module log2_approx_8bit (
input wire [7:0] x, // 8-bit input
output reg [7:0] log2_approx // Approximated log2(x)
);
// Leading Zero Counter (parallel implementation)
wire [2:0] lz_count;
wire [7:0] shifted_x;
// Shift x right until the MSB is 1 (parallel approach)
assign shifted_x ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module cordic_sin_cos (
input wire clk,
input wire reset,
input wire signed [15:0] angle_in, // Signed input angle in Q15 format
output reg signed [15:0] sin_out,
output reg signed [15:0] cos_out
);
// Parameters
localparam DATA_WIDTH = 16;
localparam ITERATIONS = 15;
localparam K_SCALE = 32768 / ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module exponentiation_unit_2 (
input wire [7:0] exp, // 8-bit exponent (0 to 255)
output reg [8:0] result // 9-bit result (2^exp)
);
// Initialize result to 0
always @(*) begin
if (exp == 0) begin
result = 8'b00000001; // 2^0 = 1
end
else begin
r... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module exponentiation_unit_2 (
input wire [7:0] exp, // 8-bit exponent (0 to 255)
output reg [8:0] result // 9-bit result (2^exp)
);
// Initialize result to 0
always @(*) begin
if (exp == 0) begin
result = 9'b000000001; // 2^0 = 1 (9-bit representation)
end
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module bcd_to_binary_16bit (
input wire [15:0] bcd_in, // 16-bit BCD input (4 digits, each 4 bits)
output reg [15:0] binary_out // 16-bit binary output
);
// Internal signals for intermediate results
reg [15:0] temp_result;
// Process each BCD digit (4 digits total)
always @(*) begin
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
// Half-adder module (sum and carry of two bits)
module half_adder (
input wire a,
input wire b,
output wire sum,
output wire carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
// Full-adder module (sum and carry of three bits)
module full_adder (
input wire a,
input wire... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module abs_32bit (
input wire signed [31:0] a,
output wire signed [31:0] abs_a
);
// Compute absolute value
assign abs_a =
(a[31] == 0) ? a :
(a == -'d1 << 31) ? ('d1 << 31) - 1 : // Handle -2^31 case
~a + 1; // Two's complement negation
endmodu... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module abs_32bit (
input wire signed [31:0] a,
output wire signed [31:0] abs_a
);
// Compute absolute value
assign abs_a =
(a[31] == 0) ? a :
(a == -'d1 << 31) ? ('d1 << 31) - 1 : // Handle -2^31 case
~a + 1; // Two's complement negation
endmodu... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module manhattan_distance (
input wire [7:0] x1, y1, x2, y2, // 8-bit coordinates
output reg [8:0] distance // 9-bit output (max distance = 510)
);
// Compute differences
wire [7:0] x_diff = x1 - x2;
wire [7:0] y_diff = y1 - y2;
// Compute absolute values
wire [7:0] abs_x_diff, a... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module manhattan_distance (
input wire [7:0] x1, y1, x2, y2, // 8-bit coordinates
output wire [8:0] distance // 9-bit output (max distance = 510)
);
// Compute differences
wire [7:0] x_diff = x1 - x2;
wire [7:0] y_diff = y1 - y2;
// Compute absolute values
wire [7:0] abs_x_diff, a... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module up_down_counter(
input wire clk,
input wire reset,
input wire load_enable,
input wire load_value,
input wire direction,
output reg [3:0] counter,
output reg overflow
);
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 4'b0;
overflow <= 1'b0;
end else b... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module alu8bit(
input wire [7:0] a, b,
input wire [2:0] opcode,
output reg [7:0] result,
output reg overflow
);
// Define the ALU operations
always @(*) begin
case (opcode)
3'b000: result = a + b; // ADD
3'b001: result = a - b; // SUB
3'b010: result = a & b; // AND
3'b011: resul... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module uart_tx(
input wire clk,
input wire rst,
input wire start,
input wire [7:0] data,
input wire parity_en,
output reg tx_en,
output reg tx_data
);
parameter BAUD_RATE = 9600; // Baud rate in bits per second
reg [31:0] counter;
reg [3:0] bit_counter;
reg [7:0] data_reg;
reg parity_bit;
a... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module spi_master_controller (
input wire clk,
input wire rst,
input wire [15:0] data_in,
output reg [15:0] data_out,
output reg sck,
output reg cs
);
reg [3:0] state;
reg [15:0] shift_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= 4'b0000;
shift_reg <= 16'b0... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module barrel_shifter(input [31:0] data_in, input [4:0] shift_amount, input shift_direction, input arithmetic_shift, output reg [31:0] data_out);
reg [31:0] temp_data;
integer i;
always @(*) begin
temp_data = data_in;
if (shift_direction == 1'b0) begin // Left shift
if (arithmetic_shift == 1'b1) be... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module fifo_buffer #(
parameter N = 8
) (
input wire clk,
input wire rst,
input wire wr_en,
input wire rd_en,
input wire [N-1:0] data_in,
output reg [N-1:0] data_out,
output reg full,
output reg empty,
output reg half_full
);
reg [N-1:0] mem [0:2*N-1];
integer wr_ptr, rd_ptr;
always @(posedge clk)... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module sequence_detector(input wire clk, input wire reset, input wire data, output reg out);
reg [2:0] state;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 3'b000;
out <= 1'b0;
end else begin
case (state)
3'b000: begin
if (data) begin
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module clock_divider(clk_in, clk_out);
input clk_in;
output reg clk_out;
reg [27:0] counter;
always @(posedge clk_in) begin
counter <= counter + 1;
if (counter == 28'h1748765) begin
clk_out <= ~clk_out;
counter <= 0;
end
end
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module cla_adder_16bit(clk, reset, a, b, cin, sum, cout);
input clk, reset, cin;
input [15:0] a, b;
output reg [15:0] sum;
output reg cout;
// Implement the logic for the Carry Look-Ahead Adder
always @(posedge clk or posedge reset) begin
if (reset) begin
sum <= 16'b0;
cout <= 1'b0;
end... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module ping_pong_buffer_controller(
input clk,
input rst,
input [7:0] data_in,
output reg [7:0] data_out,
output reg full,
output reg empty
);
reg [3:0] counter;
reg [1:0] state;
always @(posedge clk or posedge rst) begin
if (rst) begin
counter <= 0;
state <= 0;
full <= 0;
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module pwm_generator(clk, duty, pwm_out);
input clk;
input [7:0] duty;
output reg pwm_out;
reg [7:0] counter;
always @(posedge clk) begin
counter <= counter + 1;
if (counter == duty) begin
pwm_out <= 1'b1;
end else if (counter == 255) begin
pwm_out <= 1'b0;
counter <= 0;
end... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | verilog_cot_dataset.jsonl |
module and_gate(
input wire a,
input wire b,
output wire y
);
assign y = a & b;
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module and_gate(
input wire a,
input wire b,
output wire y
);
assign y = a & b;
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module xor_gate(
input wire a,
input wire b,
output wire y
);
assign y = a ^ b;
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module xor_gate(
input wire a,
input wire b,
output wire y
);
assign y = a ^ b;
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module nand_gate_4_input(
input wire A,
input wire B,
input wire C,
input wire D,
output wire Y
);
assign Y = ~(A & B & C & D);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module nand_gate_4_input(
input wire A,
input wire B,
input wire C,
input wire D,
output wire Y
);
assign Y = ~(A & B & C & D);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module Half_Adder(
input wire A,
input wire B,
output wire Sum,
output wire Carry
);
assign Sum = A ^ B;
assign Carry = A & B;
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module Half_Adder(
input wire A,
input wire B,
output wire Sum,
output wire Carry
);
assign Sum = A ^ B;
assign Carry = A & B;
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module full_adder(A, B, cin, S, cout);
input A, B, cin;
output S, cout;
assign S = A ^ B ^ cin;
assign cout = (A & B) | (B & cin) | (A & cin);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module full_adder(A, B, cin, S, cout);
input A, B, cin;
output S, cout;
assign S = A ^ B ^ cin;
assign cout = (A & B) | (B & cin) | (A & cin);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module full_adder(
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module CarryLookaheadAdder(
input wire [3:0] A,
input wire [3:0] B,
output wire [3:0] Sum,
output wire CarryOut
);
wire [3:0] G;
wire [3:0] P;
assign G[0] = A[0] & B[0];
assign P[0] = A[0] | B[0];
for (genvar i = 1; i < 4; i++) begin
assign G[i] = (P[i-1] & (A[i] |... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module full_adder(
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module half_subtractor(
input A,
input B,
output D,
output B_out
);
assign D = (A ^ B);
assign B_out = (A & ~B);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module half_subtractor(
input A,
input B,
output D,
output B_out
);
assign D = (A ^ B);
assign B_out = (A & ~B);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module FullSubtractor(
input A, B, Borrow,
output D, Borrow_out
);
assign D = A ^ B;
assign Borrow_out = (A & B) | (Borrow & (A ^ B));
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module FullSubtractor(
input A, B, Borrow,
output D, Borrow_out
);
assign D = A ^ B;
assign Borrow_out = (A & B) | (Borrow & (A ^ B));
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module multiplexer_2_1(
input wire sel, // Control signal (select)
input wire a, // Input A
input wire b, // Input B
output wire y // Output
);
// Use a conditional operator to select the output based on the control signal
assign y = sel ? b : a;
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module multiplexer_2_1(
input wire sel, // Control signal (select)
input wire a, // Input A
input wire b, // Input B
output wire y // Output
);
// Use a conditional operator to select the output based on the control signal
assign y = sel ? b : a;
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module multiplexer_4_1(
input wire [1:0] sel, // Select lines (S1 and S0)
input wire [3:0] in0, // Input 0
input wire [3:0] in1, // Input 1
input wire [3:0] in2, // Input 2
input wire [3:0] in3, // Input 3
output reg [3:0] out // Output
);
always @(*)
begin
case (sel... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module eight_to_one_mux(
input wire [7:0] in,
input wire [2:0] sel,
output wire out
);
wire [3:0] sel1;
wire [3:0] sel2;
wire [3:0] out1;
wire [3:0] out2;
assign sel1 = sel[1:0];
assign sel2 = sel[1:0];
four_to_one_mux four_to_one_mux1(
.in({in[3:0], in[... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module four_to_one_mux(
input wire [3:0] in,
input wire [1:0] sel,
output wire out
);
assign out = in[3] ? in[3] : (sel[1] ? in[2] : (sel[0] ? in[1] : in[0]));
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module decoder_2to4(
input wire I0,
input wire I1,
output wire O0,
output wire O1,
output wire O2,
output wire O3
);
// Output O0 is active when I0 is 0 and I1 is 0
assign O0 = ~I0 & ~I1;
// Output O1 is active when I0 is 0 and I1 is 1
assign O1 = ~I0 & I1;
// Output O2 ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module decoder_2to4(
input wire I0,
input wire I1,
output wire O0,
output wire O1,
output wire O2,
output wire O3
);
// Output O0 is active when I0 is 0 and I1 is 0
assign O0 = ~I0 & ~I1;
// Output O1 is active when I0 is 0 and I1 is 1
assign O1 = ~I0 & I1;
// Output O2 ... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module decoder3to8(
input wire [2:0] A,
output reg [7:0] Y
);
// Generate each output bit using AND gates
assign Y[0] = ~A[2] & ~A[1] & ~A[0];
assign Y[1] = ~A[2] & ~A[1] & A[0];
assign Y[2] = ~A[2] & A[1] & ~A[0];
assign Y[3] = ~A[2] & A[1] & A[0];
assign Y[4] = A[2] & ~A[1] & ~A... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module decoder3to8(
input wire [2:0] A,
output wire [7:0] Y
);
// Generate each output bit using AND gates
assign Y[0] = ~A[2] & ~A[1] & ~A[0];
assign Y[1] = ~A[2] & ~A[1] & A[0];
assign Y[2] = ~A[2] & A[1] & ~A[0];
assign Y[3] = ~A[2] & A[1] & A[0];
assign Y[4] = A[2] & ~A[1] & ~... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module priority_encoder_4to2(
input wire [3:0] A,
output wire [1:0] Y
);
assign Y[1] = A[3];
assign Y[0] = A[3] ? 1'b0 : (A[2] ? 1'b1 : 1'b0);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module priority_encoder_4to2(
input wire [3:0] A,
output wire [1:0] Y
);
assign Y[1] = A[3];
assign Y[0] = A[3] ? 1'b0 : (A[2] ? 1'b1 : 1'b0);
endmodule | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module priority_encoder_8to3(
input wire [7:0] input_bits,
input wire clk,
output reg [2:0] output_bits
);
// Initialize output register to 0
reg [2:0] output_reg;
// Priority encoder logic
always @(*) begin
case (input_bits[7])
1'b1: output_reg = 3'b111; /... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module magnitude_comparator(
input wire A,
input wire B,
output reg greater_than,
output reg less_than,
output reg equal_to
);
always @(*) begin
if (A == 1'b1 && B == 1'b0) begin
greater_than <= 1'b1;
less_than <= 1'b0;
equal_to <= 1'b0;
end
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module magnitude_comparator(
input wire A,
input wire B,
output reg greater_than,
output reg less_than,
output reg equal_to
);
always @(*) begin
if (A == 1'b1 && B == 1'b0) begin
greater_than <= 1'b1;
less_than <= 1'b0;
equal_to <= 1'b0;
end
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module bcd_to_7seg(
input wire [3:0] bcd,
output reg [6:0] seg
);
always @(*)
begin
case(bcd)
4'b0000: seg = 7'b1111110;
4'b0001: seg = 7'b0011111;
4'b0010: seg = 7'b01001110;
4'b0011: seg = 7'b01000111;
4'b0100: seg = 7'b01100110;
4'b0101: seg = 7'b01101101... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module alu(
input [3:0] A, B, // 4-bit operands
input [1:0] op, // 2-bit operation code (00: ADD, 01: SUB, 10: AND, 11: OR)
output [3:0] result, // 4-bit result
output zero // zero flag
);
// Define the control signals
wire [3:0] add_sub;
wire [3:0] and_or;
wire [3:0] xor_result;
// Ca... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module alu(
input [3:0] A, B, // 4-bit operands
input [1:0] op, // 2-bit operation code (00: ADD, 01: SUB, 10: AND, 11: OR)
output [3:0] result, // 4-bit result
output zero // zero flag
);
// Define the control signals
wire [3:0] add_sub;
wire [3:0] and_or;
wire [3:0] xor_result;
// Ca... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module SR_Latch(
input wire S, // Set input
input wire R, // Reset input
output wire Q // Output
);
reg Q_reg; // Internal register to store Q
reg Q_reg_not; // Internal register to store Q'
always @(posedge S or posedge R) begin
if (S) begin
Q_reg <= 1'b1;
end else if (R) begin
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
module SR_Latch(
input wire S, // Set input
input wire R, // Reset input
output wire Q // Output
);
reg Q_reg; // Internal register to store Q
reg Q_reg_not; // Internal register to store Q'
always @(posedge S or posedge R) begin
if (S) begin
Q_reg <= 1'b1;
end else if (R) begin
... | SAIFIINDUSTRIES/Verilog-CoT-Dataset | train-00000-of-00001.parquet |
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