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1f7577c | src/hdl/mac/rx_mac.sv | src/hdl/mac/rx_mac.sv | // MIT License
// Copyright (c) 2023 Tom Chisholm
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, me... | // MIT License
// Copyright (c) 2023 Tom Chisholm
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, me... | Improve spurious message rejection
| Improve spurious message rejection
| System Verilog | mit | 10g-low-latency-ethernet | 0 | |
a8b3f58 | src/hdl/mac/rx_mac.sv | src/hdl/mac/rx_mac.sv | // MIT License
// Copyright (c) 2023 Tom Chisholm
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, me... | // MIT License
// Copyright (c) 2023 Tom Chisholm
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, me... | Rollback rx-mac crc timing changes
| Rollback rx-mac crc timing changes
| System Verilog | mit | 10g-low-latency-ethernet | 0 | |
dbeb395 | sim/testbench_3.sv | sim/testbench_3.sv | `timescale 1ns / 1ps
`default_nettype none
`include "src/iverilog_hack_thresh.svh"
/******************************COMMANDS*********************************
iverilog -g2012 -o sim/testbench_3.out sim/testbench_3.sv src/xilinx_single_port_ram_read_first.v src/find_corners.sv src/card_isolator.sv
vvp sim/testbench_3.o... | `timescale 1ns / 1ps
`default_nettype none
`include "src/iverilog_hack_thresh.svh"
/******************************COMMANDS*********************************
iverilog -g2012 -o sim/testbench_3.out sim/testbench_3.sv src/xilinx_single_port_ram_read_first.v src/find_corners.sv src/card_isolator.sv
vvp sim/testbench_3.o... | Update testbench_3.sv
| Update testbench_3.sv
| System Verilog | mit | 6205-fp | 0 | |
20fe085 | verilog/rans_decoder.sv | verilog/rans_decoder.sv |
module rans_decoder
#(
parameter SYMBOL_WIDTH = 4,
parameter LOG_M = 10, // ideally we make M a power of 2
parameter CONST_T = 1,
parameter BIN_PARALLELISM = 8
)(
input clk,
input rst_n,
input config_en,
input [SYMBOL_WIDTH-1:0] config_symbol,
input [LOG_H-1:0] config_freq,
inpu... |
module rans_decoder
#(
parameter SYMBOL_WIDTH = 4,
parameter LOG_M = 10, // ideally we make M a power of 2
parameter CONST_T = 1,
parameter BIN_PARALLELISM = 8
)(
input clk,
input rst_n,
input config_en,
input [SYMBOL_WIDTH-1:0] config_symbol,
input [LOG_H-1:0] config_freq,
inpu... | Merge branch 'main' of github.com:somewhatdistracted/EE274-Project
| Merge branch 'main' of github.com:somewhatdistracted/EE274-Project
| System Verilog | mit | EE274-Project | 0 | |
b95b8f4 | FIFO_design.sv | FIFO_design.sv | module fifo(
input clock, rd, wr,
output full, empty,
input [7:0] data_in,
output reg [7:0] data_out,
input rst);
//global control signal clock and reset are present
//data control signals rd and wr
// coditional flags full emppty to represent status of FIFO
reg [7:0] mem [31:0]; // depth is 32
reg [4:0] wr_ptr... | // Code your design here
module fifo(
input clock, rd, wr,
output full, empty,
input [7:0] data_in,
output reg [7:0] data_out,
input rst);
//global control signal clock and reset are present
//data control signals rd and wr
// coditional flags full emppty to represent status of FIFO
reg [7:0] mem [31:0]; // dept... | Update FIFO_design.sv | Update FIFO_design.sv | System Verilog | mit | FIFO_Layered_TB | 0 | |
59f3810 | Transaction.sv | Transaction.sv | class transaction
rand bit rd,wr;
rand bit[7:0] data_in;
bit full , empty;
rand bit[7:0] data-out;
//No need to randomize the global signals (clk or rst)
//constraint because we added random generator
constraint wr_rd{
rd != wr; // whenever rd high rd must not be high or viceversa
wr dist {... | class transaction;
rand bit rd,wr;
rand bit[7:0] data_in;
bit full , empty;
rand bit[7:0] data-out;
//No need to randomize the global signals (clk or rst)
//constraint because we added random generator
constraint wr_rd{
rd != wr; // whenever rd high rd must not be high or viceversa
wr dist ... | Update Transaction.sv | Update Transaction.sv | System Verilog | mit | FIFO_Layered_TB | 0 | |
54e1e58 | src/Modules/Components/RegisterFile.sv | src/Modules/Components/RegisterFile.sv | // Register File
// Integer register file, can be configured for all RISC-V base ISAs, default is for RV32I
module RegisterFile #(
parameter REG_WIDTH = 32, // Width of the internal registers (32 for RV32I, 64 for RV64I, etc.)
parameter NUM_REGS = 32, // Number of registers in the file (16 for RV32E, 32 for... | // Register File
// Integer register file, can be configured for all RISC-V base ISAs, default is for RV32I
module RegisterFile #(
parameter REG_WIDTH = 32, // Width of the internal registers (32 for RV32I, 64 for RV64I, etc.)
parameter NUM_REGS = 32, // Number of registers in the file (16 for RV32E, 32 for... | fixed regfile to init + don't write to zero reg
| fixed regfile to init + don't write to zero reg
| System Verilog | mit | PillowCore-RISC-V-Processors | 0 | |
a7094fc | testbench.sv | testbench.sv | ////////////////TEST BENCH CODE FOR ELECTRONIC LOCK//////////////////
module electronic_lock_tb;
reg clk, rst;
reg [1:0]b ;
wire unlock;
integer i;
reg [15:0]data;
electronic_lock dut(clk, rst, b[0], b[1], unlock);
always #1 clk = ~clk;
initial
begin
$monitor("time=%0t, b[o]=%b, b[1]... | // Code your testbench here
// or browse Examples
module tb;
reg clk,in,rstn;
wire out;
integer i;
reg[15:0] data;
always #10clk=~clk;
det_01011 u0(.clk(clk),.rstn(rstn),.in(in),.out(out));
initial begin $monitor("i=%0d,Time=%0d,rstn=%b,in=%b,out=%b",i,$time,rstn,in,out);
$dumpfile("tb.vcd");
$dum... | first commit | first commit | System Verilog | mit | Project_Electronic_Lock-using-verilog | 0 | |
eb00d42 | design.sv | design.sv | /////////////DESIGN BENCH CODE FOR ELECTRONIC LOCK SYSTEM///////////
module electronic_lock(clk, rst, b[0],b[1], unlock);
output reg unlock;
input clk,rst;
input [1:0]b;
reg [2:0] state;
reg [2:0] next_state;
//State Assignments//
parameter [2:0] s_rst = 3'b000;
parameter [2:0] s0 = 3'b001;
paramete... | // Code your design here
module det_01011(input clk, input rstn, input in , output out);
parameter s0 =0,
s01 =1,
s010 =2,
s0101 =3,
s01011 =4,
s2 =5;
reg[2:0]cur_state,next_state;
assign out= cur_state == s01011 ? 1:0;
always @(posedge clk)begin
if(!rstn)... | first commit | first commit | System Verilog | mit | Project_Electronic_Lock-using-verilog | 0 | |
d90652a | step_1_dut_core.sv | step_1_dut_core.sv | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | resolving error
| resolving error
| System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
1bc5bd3 | step_1_dut_core.sv | step_1_dut_core.sv | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | adding error | adding error | System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
2172065 | step_4_pixel_testbench.sv | step_4_pixel_testbench.sv | // Module pixel_testbench implements a first testbench for the design under test.
module pixel_testbench();
reg clk;
reg rst;
reg start;
logic [11:0] size_x = 40, size_y = 40;
logic [23:0] count;
typedef enum {IDLE, RUNNING, READY} t_feeder_states;
t_feeder_states feeder_state;
// Feed... | // Module pixel_testbench implements a first testbench for the design under test.
module pixel_testbench();
logic clk;
reg rst; // @suppress "'logic' should be used instead of 'reg'"
reg start; // @suppress "'logic' should be used instead of 'reg'"
logic [11:0] size_x = 40, size_y = 40;
logic [23:... | Some warnings corrected or suppressed
| Some warnings corrected or suppressed
| System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
aacbde2 | step_1_dut_core.sv | step_1_dut_core.sv | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | introduce error
| introduce error
| System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
a95e444 | step_1_dut_core.sv | step_1_dut_core.sv | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | fixing issues
| fixing issues
| System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
f314819 | step_1_dut_core.sv | step_1_dut_core.sv | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | correct error | correct error | System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
98c0b36 | step_1_dut_core.sv | step_1_dut_core.sv | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | changing to a different error message | changing to a different error message | System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
ce05eff | step_1_dut_core.sv | step_1_dut_core.sv | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | re-introducing syntax error for CLI
| re-introducing syntax error for CLI
| System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
5209cc6 | step_1_dut_core.sv | step_1_dut_core.sv | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | ////////////////////////////////////////////////////////////////////////////////
// Welcome!
////////////////////////////////////////////////////////////////////////////////
// You made a great choice installing Sigasi Studio, and now you are ready to
// unlock its power.
//
// This demo file will guide you through you... | fix error | fix error | System Verilog | bsd-3-clause | Sigasi_CLI_in_CI_demo | 0 | |
2c28aca | hdl/tbn/vip/tcb_vip_mem.sv | hdl/tbn/vip/tcb_vip_mem.sv | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) VIP (Verification IP) memory
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2.0 (the "License");
... | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) VIP (Verification IP) memory
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2.0 (the "License");
... | VIP: removing unused package dependancy
| VIP: removing unused package dependancy
| System Verilog | apache-2.0 | TCB | 0 | |
80acf8e | hdl/rtl/gpio/tcb_gpio.sv | hdl/rtl/gpio/tcb_gpio.sv | ////////////////////////////////////////////////////////////////////////////////
// TCB interface GPIO controller
//
// NOTE: In case this module is connected to asynchronous signals,
// the input signals `gpio_i` require a CDC synchronizer.
// By default a 2 FF synchronizer is implemented by the CFG_CDC pa... | ////////////////////////////////////////////////////////////////////////////////
// TCB interface GPIO controller
//
// NOTE: In case this module is connected to asynchronous signals,
// the input signals `gpio_i` require a CDC synchronizer.
// By default a 2 FF synchronizer is implemented by the CFG_CDC pa... | RTL: GPIO, fixed write access
| RTL: GPIO, fixed write access
| System Verilog | apache-2.0 | TCB | 0 | |
701b2aa | hdl/rtl/tcb_pkg.sv | hdl/rtl/tcb_pkg.sv | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) SystemVerilog package
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you ... | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) SystemVerilog package
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you ... | HDL: since using Questa, reverting back to unpacked struct for parameters
| HDL: since using Questa, reverting back to unpacked struct for parameters
| System Verilog | apache-2.0 | TCB | 0 | |
2cef3e6 | hdl/tbn/vip/tcb_vip_pkg.sv | hdl/tbn/vip/tcb_vip_pkg.sv | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) VIP (Verifivation IP) PacKaGe
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2.0 (the "License");... | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) VIP (Verifivation IP) PacKaGe
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2.0 (the "License");... | VIP package: commenting out an unfinished subclass which would create transaction_t arrays from an access function
| VIP package: commenting out an unfinished subclass which would create transaction_t arrays from an access function
| System Verilog | apache-2.0 | TCB | 0 | |
06e1d8f | hdl/tbn/vip/tcb_vip_man.sv | hdl/tbn/vip/tcb_vip_man.sv | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) VIP (Verifivation IP) MANager
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2.0 (the "License");... | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) VIP (Verifivation IP) MANager
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2.0 (the "License");... | VIP: add a bit of verbosityto HDL variable names
| VIP: add a bit of verbosityto HDL variable names
| System Verilog | apache-2.0 | TCB | 0 | |
f152787 | hdl/tbn/lib/tcb_lib_converter_tb.sv | hdl/tbn/lib/tcb_lib_converter_tb.sv | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) library mode/alignment/order converter testbench
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2... | ////////////////////////////////////////////////////////////////////////////////
// TCB (Tightly Coupled Bus) library mode/alignment/order converter testbench
////////////////////////////////////////////////////////////////////////////////
// Copyright 2022 Iztok Jeras
//
// Licensed under the Apache License, Version 2... | TBN: since using Questa, parameter propagation to interfaces/classes works
| TBN: since using Questa, parameter propagation to interfaces/classes works
| System Verilog | apache-2.0 | TCB | 0 |
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