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dh1dm/q27 | src/vhdl/PoC/arith/arith_counter_free.vhdl | 2 | 2946 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module: Poc.arith_counter_free
--
-- Authors: Thomas B. Preusser
--
-- Description:
-- ------------
-- Implements a free-running counter that generates a strobe signal
-- every DIVIDER-th cycle the increment input was asserted.
-- There is deliberately no output or specification of the counter
-- value so as to allow an implementation to optimize as much as
-- possible.
-- The implementation guarantees a strobe output directly from a
-- register. It is asserted exactly for one clock after DIVIDER cycles
-- of an asserted increment input have been observed.
--
-- License:
-- ===========================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity arith_counter_free is
generic (
DIVIDER : positive
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
inc : in std_logic;
stb : out std_logic -- End-of-Period Strobe
);
end arith_counter_free;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of arith_counter_free is
begin
genNoDiv: if DIVIDER = 1 generate
process(clk)
begin
if rising_edge(clk) then
stb <= inc;
end if;
end process;
end generate genNoDiv;
genDoDiv: if DIVIDER > 1 generate
-- Note: For DIVIDER=2**K+1, this could be marginally reduced to log2ceil(DIVIDER-1)
-- if it was known that the increment input inc would never be deasserted.
constant N : natural := log2ceil(DIVIDER);
signal Cnt : unsigned(N downto 0) := (others => '0');
signal cin : unsigned(0 downto 0);
begin
cin(0) <= not inc;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= to_unsigned(DIVIDER-2, N+1);
else
Cnt <= Cnt + ite(Cnt(N) = '0', (Cnt'range => '1'), to_unsigned(DIVIDER-1, N+1)) + cin;
end if;
end if;
end process;
stb <= Cnt(N);
end generate genDoDiv;
end rtl;
| agpl-3.0 |
dh1dm/q27 | src/vhdl/queens/queens_slice.vhdl | 1 | 8378 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-- Benedikt Reuter <breutr@gmail.com>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity queens_slice is
generic (
N : positive; -- size of field
L : positive -- number of preplaced outer rings
);
port (
-- Global Clock
clk : in std_logic;
rst : in std_logic;
-- Inputs (strobed)
start : in std_logic; -- Strobe for Start
BH_l : in std_logic_vector(0 to N-2*L-1); -- Blocking for leftmost Column
BU_l : in std_logic_vector(0 to 2*N-4*L-2);
BD_l : in std_logic_vector(0 to 2*N-4*L-2); -- 0 to 6
BV_l : in std_logic_vector(0 to N-2*L-1);
-- Output Strobes
sol : out std_logic;
done : out std_logic
);
end queens_slice;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of queens_slice is
---------------------------------------------------------------------------
-- Matrix to iterate through
-- These types are plain ugly but the multidiemsional tMatrix(<>, <>)
-- is not slicable. Thus, these types are still better than lots of
-- generate loops working through the columns.
subtype tColumn is std_logic_vector(L to N-L-1);
type tField is array(L to N-L-1) of tColumn;
-- Placed Queen Matrix
signal QN : tField := (others => (others => '-'));
component arbit_forward
generic (
N : positive -- Length of Token Chain
);
port (
tin : in std_logic; -- Fed Token
have : in std_logic_vector(0 to N-1); -- Token Owner
pass : in std_logic_vector(0 to N-1); -- Token Passers
grnt : out std_logic_vector(0 to N-1); -- Token Output
tout : out std_logic -- Unused Token
);
end component;
-- Blocking Signals
signal BH : std_logic_vector( L to N-L-1) := (others => '-'); -- Window: L to N-L-1
signal BV : std_logic_vector(2*L+1 to 2*N-2*L-1) := (others => '-'); -- Window: N
-- put shifts left
signal BU : std_logic_vector(2*L+1 to 3*N-4*L-2) := (others => '-'); -- Window: N to 2*N-2*L-1
-- put shifts right
signal BD : std_logic_vector(2*L+1 to 3*N-4*L-2) := (others => '-'); -- Window: N to 2*N-2*L-1
-- put shifts left
signal s : std_logic_vector(L to N-L-1);
signal put : std_logic;
begin
assert false
report LF&
"Queens@TUD Solver Slice " &LF&
"Copyright (C) 2015 Thomas B. Preusser <thomas.preusser@utexas.edu> " &LF&
" Benedikt Reuter <breutr@gmail.com>" &LF&
"This design is free software, and you are welcome to redistribute it " &LF&
"under the conditions of the GPL version 3. " &LF&
"It comes with ABSOLUTELY NO WARRANTY. " &LF&
"For details see the notice in the file COPYING."&LF
severity note;
---------------------------------------------------------------------------
-- Queen Matrix
process(clk)
begin
if rising_edge(clk) then
if put = '1' then
QN(L to N-L-2) <= QN(L+1 to N-L-1);
else
QN(L to N-L-2) <= tColumn'(tColumn'range => '-') & QN(L to N-L-3);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Blocking Signals
process(clk)
begin
if clk'event and clk = '1' then
-- Initialization
if start = '1' then
BH <= BH_l;
BV <= (BV'left to N-1 => '-') & BV_l;
BU <= BU_l & (2*N-2*L to BU'right => '-');
BD <= (BD'left to N-1 => '-') & BD_l;
else
-- In Progress
if put = '1' then
-- Add placed Queen
BH <= BH or s;
BV <= BV(BV'left+1 to BV'right) & '-';
BU <= '-' & BU(BU'left to N-1) & (BU(N to 2*N-2*L-1) or s) & BU(2*N-2*L to BU'right-1);
BD <= BD(BD'left+1 to N-1) & (BD(N to 2*N-2*L-1) or s) & BD(2*N-2*L to BD'right) & '-';
else
-- Clear Queen
BH <= BH and not QN(N-L-2);
BV <= '-' & BV(BV'left to BV'right-1);
BU <= BU(BU'left+1 to N) & (BU(N+1 to 2*N-2*L) and not QN(N-L-2)) & BU(2*N-2*L+1 to BU'right) & '-';
BD <= '-' & BD(BD'left to N-2) & (BD(N-1 to 2*N-2*L-2) and not QN(N-L-2)) & BD(2*N-2*L-1 to BD'right-1);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Placement Calculation
blkPlace : block
-- State
signal CS : std_logic_vector(L to N-L-1) := (others => '0'); -- Column Front Selector
signal Fwd : std_logic := '-'; -- Direction
signal H : std_logic_vector(L to N-L-1) := (others => '-'); -- Last Placement in active Col
-- Combined Blocking
signal pass : std_logic_vector(L to N-L-1);
signal tout : std_logic;
signal st : std_logic_vector(L to N-L-1);
signal tt : std_logic;
begin
-- Combine Blocking Signals
pass <= BH or BD(N to 2*N-2*L-1) or BU(N to 2*N-2*L-1);
col : arbit_forward
generic map (
N => N-2*L
)
port map (
tin => Fwd, -- Richtung (=put)
have => H, -- FWD-> 000000 ; -FWD-> QN(N-2)
pass => pass, -- BH or BU or BD
grnt => st,
tout => tt -- overflow (q(N)) -> Reihe fertig -> keine dame gesetzt
);
tout <= not Fwd when BV(N) = '1' else tt;
s <= (others => '0') when BV(N) = '1' else st;
QN(N-L-1) <= s;
-- Column Front Selector, a shift-based counter with:
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
CS <= (others => '0');
elsif start = '1' then
CS <= (others => '0');
CS(CS'left) <= '1';
else
if put = '1' then
CS <= '0' & CS(CS'left to CS'right-1);
else
CS <= CS(CS'left+1 to CS'right) & '0';
end if;
end if;
end if;
end process;
-- Direction Control
process(clk)
begin
if clk'event and clk = '1' then
if start = '1' or put = '1' then
H <= (others => '0');
Fwd <= '1';
else
H <= QN(N-L-2);
Fwd <= '0';
end if;
end if;
end process;
-- Control
put <= (not tout) and not CS(CS'right);
-- Outputs
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' or start = '1' then
sol <= '0';
done <= '0';
else
sol <= (not tout) and CS(CS'right);
done <= tout and CS(CS'left);
end if;
end if;
end process;
end block blkPlace;
end rtl;
| agpl-3.0 |
dh1dm/q27 | src/vhdl/queens/unframe.vhdl | 1 | 6282 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity unframe is
generic (
SENTINEL : std_logic_vector(7 downto 0); -- Start Byte
PAY_LEN : positive
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dat : in std_logic_vector(7 downto 0);
rx_vld : in std_logic;
rx_got : out std_logic;
odat : out std_logic_vector(7 downto 0);
oeof : out std_logic;
oful : in std_logic;
oput : out std_logic;
ocommit : out std_logic;
orollback : out std_logic
);
end unframe;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of unframe is
-- CRC Table for 0x1D5 (CRC-8)
type tFCS is array(0 to 255) of std_logic_vector(7 downto 0);
constant FCS : tFCS := (
x"00", x"D5", x"7F", x"AA", x"FE", x"2B", x"81", x"54",
x"29", x"FC", x"56", x"83", x"D7", x"02", x"A8", x"7D",
x"52", x"87", x"2D", x"F8", x"AC", x"79", x"D3", x"06",
x"7B", x"AE", x"04", x"D1", x"85", x"50", x"FA", x"2F",
x"A4", x"71", x"DB", x"0E", x"5A", x"8F", x"25", x"F0",
x"8D", x"58", x"F2", x"27", x"73", x"A6", x"0C", x"D9",
x"F6", x"23", x"89", x"5C", x"08", x"DD", x"77", x"A2",
x"DF", x"0A", x"A0", x"75", x"21", x"F4", x"5E", x"8B",
x"9D", x"48", x"E2", x"37", x"63", x"B6", x"1C", x"C9",
x"B4", x"61", x"CB", x"1E", x"4A", x"9F", x"35", x"E0",
x"CF", x"1A", x"B0", x"65", x"31", x"E4", x"4E", x"9B",
x"E6", x"33", x"99", x"4C", x"18", x"CD", x"67", x"B2",
x"39", x"EC", x"46", x"93", x"C7", x"12", x"B8", x"6D",
x"10", x"C5", x"6F", x"BA", x"EE", x"3B", x"91", x"44",
x"6B", x"BE", x"14", x"C1", x"95", x"40", x"EA", x"3F",
x"42", x"97", x"3D", x"E8", x"BC", x"69", x"C3", x"16",
x"EF", x"3A", x"90", x"45", x"11", x"C4", x"6E", x"BB",
x"C6", x"13", x"B9", x"6C", x"38", x"ED", x"47", x"92",
x"BD", x"68", x"C2", x"17", x"43", x"96", x"3C", x"E9",
x"94", x"41", x"EB", x"3E", x"6A", x"BF", x"15", x"C0",
x"4B", x"9E", x"34", x"E1", x"B5", x"60", x"CA", x"1F",
x"62", x"B7", x"1D", x"C8", x"9C", x"49", x"E3", x"36",
x"19", x"CC", x"66", x"B3", x"E7", x"32", x"98", x"4D",
x"30", x"E5", x"4F", x"9A", x"CE", x"1B", x"B1", x"64",
x"72", x"A7", x"0D", x"D8", x"8C", x"59", x"F3", x"26",
x"5B", x"8E", x"24", x"F1", x"A5", x"70", x"DA", x"0F",
x"20", x"F5", x"5F", x"8A", x"DE", x"0B", x"A1", x"74",
x"09", x"DC", x"76", x"A3", x"F7", x"22", x"88", x"5D",
x"D6", x"03", x"A9", x"7C", x"28", x"FD", x"57", x"82",
x"FF", x"2A", x"80", x"55", x"01", x"D4", x"7E", x"AB",
x"84", x"51", x"FB", x"2E", x"7A", x"AF", x"05", x"D0",
x"AD", x"78", x"D2", x"07", x"53", x"86", x"2C", x"F9"
);
-- State Machine
type tState is (Idle, Load, CheckCRC);
signal State : tState := Idle;
signal NextState : tState;
signal CRC : std_logic_vector(7 downto 0) := (others => '-');
signal Start : std_logic;
signal Append : std_logic;
signal Last : std_logic;
signal CRC_next : std_logic_vector(7 downto 0);
begin
-- State
CRC_next <= FCS(to_integer(unsigned(CRC xor rx_dat)));
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
CRC <= (others => '-');
else
State <= NextState;
if Start = '1' then
CRC <= FCS(255);
elsif Append = '1' then
CRC <= CRC_next;
end if;
end if;
end if;
end process;
process(State, rx_vld, rx_dat, oful, Last, CRC)
begin
NextState <= State;
Start <= '0';
Append <= '0';
odat <= (others => '-');
oeof <= Last;
oput <= '0';
ocommit <= '0';
orollback <= '0';
rx_got <= '0';
if rx_vld = '1' then
case State is
when Idle =>
rx_got <= '1';
if rx_dat = SENTINEL then
Start <= '1';
NextState <= Load;
end if;
when Load =>
if oful = '0' then
odat <= rx_dat;
oput <= '1';
rx_got <= '1';
Append <= '1';
if Last = '1' then
NextState <= CheckCRC;
end if;
end if;
when CheckCRC =>
if rx_dat = CRC then
ocommit <= '1';
else
orollback <= '1';
end if;
NextState <= Idle;
end case;
end if;
end process;
-- Payload Counter
genPayEq1: if PAY_LEN = 1 generate
Last <= '1';
end generate genPayEq1;
genPayGt1: if PAY_LEN > 1 generate
signal Cnt : unsigned(log2ceil(PAY_LEN-1) downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= (others => '-');
else
if Start = '1' then
Cnt <= to_unsigned(PAY_LEN-2, Cnt'length);
elsif Append = '1' then
Cnt <= Cnt - 1;
end if;
end if;
end if;
end process;
Last <= Cnt(Cnt'left);
end generate genPayGt1;
end rtl;
| agpl-3.0 |
UnofficialRepos/OSVVM | ResolutionPkg.vhd | 1 | 16067 | --
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@SynthWorks.com
-- Contributor(s):
-- Jim Lewis email: jim@SynthWorks.com
--
-- Package Defines
-- resolved resolution functions for integer, real, and time
-- types resolved_integer, resolved_real, resolved_time
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2021 2021.06 Moved To/FromTransaction and SafeResize to Resize package
-- 12/2020 2020.12 Updated ToTransaction and FromTransaction with length parameter.
-- Downsizing now permitted when it does not change the value.
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Removed Asserts as they are not working as intended.
-- See ResolutionPkg_debug as it uses Alerts to correctly detect errors
-- 05/2015 2015.05 Added Alerts
-- -- Replaced Alerts with asserts as alerts are illegal in pure functions
-- 02/2009 1.0 VHDL-2008 STANDARD VERSION
-- 09/2006 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package ResolutionPkg is
constant MULTIPLE_DRIVER_SEVERITY : severity_level := ERROR ;
--
-- Note that not all simulators support resolution functions of the form:
-- subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
--
-- Hence, types of the form are offered as a temporary workaround until they do:
-- std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
--
-- resolved_max
-- return maximum value.
-- No initializations required on ports, default of type'left is ok
function resolved_max ( s : std_ulogic_vector) return std_ulogic ;
subtype std_logic_max is resolved_max std_ulogic ;
subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
type std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype unsigned_max is (resolved_max) unresolved_unsigned ;
type unsigned_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype signed_max is (resolved_max) unresolved_signed ;
type signed_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
function resolved_max ( s : bit_vector) return bit ;
subtype bit_max is resolved_max bit ;
subtype bit_vector_max is (resolved_max) bit_vector ;
type bit_vector_max_c is array (natural range <>) of bit_max ; -- for non VHDL-2008
function resolved_max ( s : integer_vector ) return integer ;
subtype integer_max is resolved_max integer ;
subtype integer_vector_max is (resolved_max) integer_vector ;
type integer_vector_max_c is array (natural range <>) of integer_max ; -- for non VHDL-2008
function resolved_max ( s : time_vector ) return time ;
subtype time_max is resolved_max time ;
subtype time_vector_max is (resolved_max) time_vector ;
type time_vector_max_c is array (natural range <>) of time_max ; -- for non VHDL-2008
function resolved_max ( s : real_vector ) return real ;
subtype real_max is resolved_max real ;
subtype real_vector_max is (resolved_max) real_vector ;
type real_vector_max_c is array (natural range <>) of real_max ; -- for non VHDL-2008
function resolved_max ( s : string) return character ;
subtype character_max is resolved_max character ;
subtype string_max is (resolved_max) string ;
type string_max_c is array (positive range <>) of character_max ; -- for non VHDL-2008
function resolved_max ( s : boolean_vector) return boolean ;
subtype boolean_max is resolved_max boolean ;
subtype boolean_vector_max is (resolved_max) boolean_vector ;
type boolean_vector_max_c is array (natural range <>) of boolean_max ; -- for non VHDL-2008
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
function resolved_sum ( s : integer_vector ) return integer ;
subtype integer_sum is resolved_sum integer ;
subtype integer_vector_sum is (resolved_sum) integer_vector ;
type integer_vector_sum_c is array (natural range <>) of integer_sum ; -- for non VHDL-2008
function resolved_sum ( s : time_vector ) return time ;
subtype time_sum is resolved_sum time ;
subtype time_vector_sum is (resolved_sum) time_vector ;
type time_vector_sum_c is array (natural range <>) of time_sum ; -- for non VHDL-2008
function resolved_sum ( s : real_vector ) return real ;
subtype real_sum is resolved_sum real ;
subtype real_vector_sum is (resolved_sum) real_vector ;
type real_vector_sum_c is array (natural range <>) of real_sum ; -- for non VHDL-2008
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
function resolved_weak (s : std_ulogic_vector) return std_ulogic ; -- no init, type'left
subtype std_logic_weak is resolved_weak std_ulogic ;
subtype std_logic_vector_weak is (resolved_weak) std_ulogic_vector ;
-- legacy stuff
-- requires ports to be initialized to 0 in the appropriate type.
function resolved ( s : integer_vector ) return integer ;
subtype resolved_integer is resolved integer ;
function resolved ( s : time_vector ) return time ;
subtype resolved_time is resolved time ;
function resolved ( s : real_vector ) return real ;
subtype resolved_real is resolved real ;
function resolved (s : string) return character ; -- same as resolved_max
subtype resolved_character is resolved character ;
-- subtype resolved_string is (resolved) string ; -- subtype will replace type later
type resolved_string is array (positive range <>) of resolved_character; -- will change to subtype -- assert but no init
function resolved ( s : boolean_vector) return boolean ; --same as resolved_max
subtype resolved_boolean is resolved boolean ;
end package ResolutionPkg ;
package body ResolutionPkg is
-- resolved_max
-- return maximum value. Assert FAILURE if more than 1 /= type'left
-- No initializations required on ports, default of type'left is ok
-- Optimized version is just the following:
-- ------------------------------------------------------------
-- function resolved_max ( s : <array_type> ) return <element_type> is
-- ------------------------------------------------------------
-- begin
-- return maximum(s) ;
-- end function resolved_max ;
------------------------------------------------------------
function resolved_max (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : bit_vector ) return bit is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : integer_vector ) return integer is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : time_vector ) return time is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : real_vector ) return real is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : string ) return character is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : boolean_vector) return boolean is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
-- resolved_sum - appropriate for numeric types
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
------------------------------------------------------------
function resolved_sum ( s : integer_vector ) return integer is
------------------------------------------------------------
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : time_vector ) return time is
------------------------------------------------------------
variable result : time := 0 sec ;
begin
for i in s'RANGE loop
if s(i) /= time'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : real_vector ) return real is
------------------------------------------------------------
variable result : real := 0.0 ;
begin
for i in s'RANGE loop
if s(i) /= real'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant weak_resolution_table : stdlogic_table := (
-- Resolution order: Z < U < W < X < - < L < H < 0 < 1
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'X', '0', '1', 'U', 'W', 'L', 'H', '-'), -- | U |
('X', 'X', '0', '1', 'X', 'X', 'L', 'H', '-'), -- | X |
('0', '0', '0', '1', '0', '0', '0', '0', '0'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), -- | Z |
('W', 'X', '0', '1', 'W', 'W', 'L', 'H', '-'), -- | W |
('L', 'L', '0', '1', 'L', 'L', 'L', 'H', 'L'), -- | L |
('H', 'H', '0', '1', 'H', 'H', 'W', 'H', 'H'), -- | H |
('-', '-', '0', '1', '-', '-', 'L', 'H', '-') -- | - |
);
------------------------------------------------------------
function resolved_weak (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
variable result : std_ulogic := 'Z' ;
begin
for i in s'RANGE loop
result := weak_resolution_table(result, s(i)) ;
end loop ;
return result ;
end function resolved_weak ;
-- legacy stuff.
-- requires ports to be initialized to 0 in the appropriate type.
------------------------------------------------------------
function resolved ( s : integer_vector ) return integer is
-- requires interface to be initialized to 0
------------------------------------------------------------
variable result : integer := 0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0 then
failed := failed or (result /= 0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on integer" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on integer") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : time_vector ) return time is
-- requires interface to be initialized to 0 ns
------------------------------------------------------------
variable result : time := 0 ns ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) > 0 ns then
failed := failed or (result /= 0 ns) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on time" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on time") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : real_vector ) return real is
-- requires interface to be initialized to 0.0
------------------------------------------------------------
variable result : real := 0.0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0.0 then
failed := failed or (result /= 0.0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on real" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on real") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved (s : string) return character is
-- same as resolved_max
------------------------------------------------------------
variable result : character := NUL ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= NUL then
failed := failed or (result /= NUL) ;
result := maximum(result, s(i)) ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on character" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on character") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : boolean_vector) return boolean is
-- same as resolved_max
------------------------------------------------------------
variable result : boolean := FALSE ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) then
failed := failed or result ;
result := TRUE ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on boolean" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on boolean") ;
return result ;
end function resolved ;
end package body ResolutionPkg ;
| artistic-2.0 |
hterkelsen/mal | vhdl/step6_file.vhdl | 13 | 10297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 |
hterkelsen/mal | vhdl/stepA_mal.vhdl | 11 | 17057 | entity stepA_mal is
end entity stepA_mal;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of stepA_mal is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
procedure is_pair(ast: inout mal_val_ptr; pair: out boolean) is
begin
pair := is_sequential_type(ast.val_type) and ast.seq_val'length > 0;
end procedure is_pair;
procedure quasiquote(ast: inout mal_val_ptr; result: out mal_val_ptr) is
variable ast_pair, a0_pair: boolean;
variable seq: mal_seq_ptr;
variable a0, rest: mal_val_ptr;
begin
is_pair(ast, ast_pair);
if not ast_pair then
seq := new mal_seq(0 to 1);
new_symbol("quote", seq(0));
seq(1) := ast;
new_seq_obj(mal_list, seq, result);
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol and a0.string_val.all = "unquote" then
result := ast.seq_val(1);
else
is_pair(a0, a0_pair);
if a0_pair and a0.seq_val(0).val_type = mal_symbol and a0.seq_val(0).string_val.all = "splice-unquote" then
seq := new mal_seq(0 to 2);
new_symbol("concat", seq(0));
seq(1) := a0.seq_val(1);
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
else
seq := new mal_seq(0 to 2);
new_symbol("cons", seq(0));
quasiquote(a0, seq(1));
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
end if;
end if;
end procedure quasiquote;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure is_macro_call(ast: inout mal_val_ptr; env: inout env_ptr; is_macro: out boolean) is
variable f, env_err: mal_val_ptr;
begin
is_macro := false;
if ast.val_type = mal_list and
ast.seq_val'length > 0 and
ast.seq_val(0).val_type = mal_symbol then
env_get(env, ast.seq_val(0), f, env_err);
if env_err = null and f /= null and
f.val_type = mal_fn and f.func_val.f_is_macro then
is_macro := true;
end if;
end if;
end procedure is_macro_call;
procedure macroexpand(in_ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, macro_fn, call_args, macro_err: mal_val_ptr;
variable is_macro: boolean;
begin
ast := in_ast;
is_macro_call(ast, env, is_macro);
while is_macro loop
env_get(env, ast.seq_val(0), macro_fn, macro_err);
seq_drop_prefix(ast, 1, call_args);
apply_func(macro_fn, call_args, ast, macro_err);
if macro_err /= null then
err := macro_err;
return;
end if;
is_macro_call(ast, env, is_macro);
end loop;
result := ast;
end procedure macroexpand;
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure fn_apply(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn: mal_val_ptr := args.seq_val(0);
variable rest: mal_val_ptr;
variable mid_args_count, rest_args_count: integer;
variable call_args: mal_val_ptr;
variable call_args_seq: mal_seq_ptr;
begin
rest := args.seq_val(args.seq_val'high);
mid_args_count := args.seq_val'length - 2;
rest_args_count := rest.seq_val'length;
call_args_seq := new mal_seq(0 to mid_args_count + rest_args_count - 1);
call_args_seq(0 to mid_args_count - 1) := args.seq_val(1 to args.seq_val'length - 2);
call_args_seq(mid_args_count to call_args_seq'high) := rest.seq_val(rest.seq_val'range);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, result, err);
end procedure fn_apply;
procedure fn_map(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn: mal_val_ptr := args.seq_val(0);
variable lst: mal_val_ptr := args.seq_val(1);
variable call_args, sub_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
new_seq := new mal_seq(lst.seq_val'range); -- (0 to lst.seq_val.length - 1);
for i in new_seq'range loop
new_one_element_list(lst.seq_val(i), call_args);
apply_func(fn, call_args, new_seq(i), sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
new_seq_obj(mal_list, new_seq, result);
end procedure fn_map;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
elsif func_sym.string_val.all = "apply" then
fn_apply(args, result, err);
elsif func_sym.string_val.all = "map" then
fn_map(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, catch_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
macroexpand(ast, env, ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "quote" then
result := ast.seq_val(1);
return;
elsif a0.string_val.all = "quasiquote" then
quasiquote(ast.seq_val(1), ast);
next; -- TCO
elsif a0.string_val.all = "defmacro!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
val.func_val.f_is_macro := true;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "macroexpand" then
macroexpand(ast.seq_val(1), env, result, err);
return;
elsif a0.string_val.all = "try*" then
EVAL(ast.seq_val(1), env, result, sub_err);
if sub_err /= null then
if ast.seq_val'length > 2 and
ast.seq_val(2).val_type = mal_list and
ast.seq_val(2).seq_val(0).val_type = mal_symbol and
ast.seq_val(2).seq_val(0).string_val.all = "catch*" then
new_one_element_list(ast.seq_val(2).seq_val(1), vars);
new_one_element_list(sub_err, call_args);
new_env(catch_env, env, vars, call_args);
EVAL(ast.seq_val(2).seq_val(2), catch_env, result, err);
else
new_nil(result);
end if;
end if;
return;
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! *host-language* " & '"' & "vhdl" & '"' & ")", repl_env, dummy_val, err);
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
RE("(defmacro! cond (fn* (& xs) (if (> (count xs) 0) (list 'if (first xs) (if (> (count xs) 1) (nth xs 1) (throw " & '"' & "odd number of forms to cond" & '"' & ")) (cons 'cond (rest (rest xs)))))))", repl_env, dummy_val, err);
RE("(def! *gensym-counter* (atom 0))", repl_env, dummy_val, err);
RE("(def! gensym (fn* [] (symbol (str " & '"' & "G__" & '"' & " (swap! *gensym-counter* (fn* [x] (+ 1 x)))))))", repl_env, dummy_val, err);
RE("(defmacro! or (fn* (& xs) (if (empty? xs) nil (if (= 1 (count xs)) (first xs) (let* (condvar (gensym)) `(let* (~condvar ~(first xs)) (if ~condvar ~condvar (or ~@(rest xs)))))))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
RE("(println (str " & '"' & "Mal [" & '"' & " *host-language* " & '"' & "]" & '"' & "))", repl_env, dummy_val, err);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 |
foresterre/mal | vhdl/step6_file.vhdl | 13 | 10297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/tg_status.vhd | 20 | 5700 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: tg_status.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:42 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
-- Error signal will be asserted if the comparsion is not equal.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity tg_status is
generic (
TCQ : TIME := 100 ps;
DWIDTH : integer := 32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
manual_clear_error : in std_logic;
data_error_i : in std_logic;
cmp_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
cmp_addr_i : in std_logic_vector(31 downto 0);
cmp_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
mcb_wr_full_i : in std_logic;
mcb_rd_empty_i : in std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
error : out std_logic
);
end entity tg_status;
architecture trans of tg_status is
signal data_error_r : std_logic;
signal error_set : std_logic;
begin
error <= error_set;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_error_r <= data_error_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i or manual_clear_error) = '1') then
-- error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
error_status <= (others => '0');
error_set <= '0';
else
-- latch the first error only
if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
error_status(31 downto 0) <= cmp_addr_i;
error_status(37 downto 32) <= cmp_bl_i;
error_status(40) <= mcb_cmd_full_i;
error_status(41) <= mcb_wr_full_i;
error_status(42) <= mcb_rd_empty_i;
error_set <= '1';
error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
end if;
error_status(39 downto 38) <= "00"; -- reserved
error_status(63 downto 43) <= "000000000000000000000"; -- reserved
end if;
end if;
end process;
end architecture trans;
| cc0-1.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/example_design/rtl/memc1_wrapper.vhd | 2 | 47712 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc1_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector (15 downto 0) := x"0000";
C_MC_CALIBRATION_BA : bit_vector (2 downto 0):= "000";
C_MC_CALIBRATION_CA : bit_vector (11 downto 0):= x"000";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
-- memory interface signals
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
-- mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb1_dram_dqs : inout std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc1_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011";
constant C_PORT_CONFIG : string := "B32_B32_B32_B32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb1_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_lpddr_s6, Coregen 14.7";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb1_lpddr_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=LPDDR, CLK_PERIOD=6000, MEMORY_PART=mt46h16m16xxxx-6-it, MEMORY_DEVICE_WIDTH=16, PA_SR=FULL, OUTPUT_DRV=HALF, PORT_CONFIG=Four 32-bit bi-directional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=4, CLKOUT_DIVIDE=2, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc1_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb1_dram_a,
mcbx_dram_ba => mcb1_dram_ba,
mcbx_dram_ras_n => mcb1_dram_ras_n,
mcbx_dram_cas_n => mcb1_dram_cas_n,
mcbx_dram_we_n => mcb1_dram_we_n,
mcbx_dram_cke => mcb1_dram_cke,
mcbx_dram_clk => mcb1_dram_ck,
mcbx_dram_clk_n => mcb1_dram_ck_n,
mcbx_dram_dq => mcb1_dram_dq,
mcbx_dram_odt => open,
mcbx_dram_ldm => mcb1_dram_dm,
mcbx_dram_udm => mcb1_dram_udm,
mcbx_dram_dqs => mcb1_dram_dqs,
mcbx_dram_dqs_n => open,
mcbx_dram_udqs => mcb1_dram_udqs,
mcbx_dram_udqs_n => open,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb1_rzq,
zio => mcb1_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| cc0-1.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/wr_data_gen.vhd | 20 | 18946 | --*****************************************************************************
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: wr_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose:
-- Reference:
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wr_data_gen is
generic (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
MODE : string := "WR"; --"WR", "RD"
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
last_word_o : out std_logic;
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
data_wr_end_o : out std_logic
);
end entity wr_data_gen;
architecture trans of wr_data_gen is
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
MEM_BURST_LEN : integer := 8;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
cmd_startE : IN STD_LOGIC;
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal cmd_rdyB : std_logic;
signal cmd_rdyC : std_logic;
signal cmd_rdyD : std_logic;
signal cmd_rdyE : std_logic;
signal cmd_rdyF : std_logic;
signal cmd_start : std_logic;
signal cmd_startB : std_logic;
signal cmd_startC : std_logic;
signal cmd_startD : std_logic;
signal cmd_startE : std_logic;
signal cmd_startF : std_logic;
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal walk_cnt : std_logic_vector(2 downto 0);
signal fifo_not_full : std_logic;
signal i : integer;
signal j : integer;
signal w3data : std_logic_vector(31 downto 0);
-- counter to count user burst length
-- bl_i;
signal u_bcount_2 : std_logic;
signal last_word_t : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_o <= data_o_xhdl0;
fifo_not_full <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
data_wr_end_o <= '1';
else
data_wr_end_o <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_start <= cmd_validC_i and cmd_rdyC;
cmd_startB <= cmd_valid_i and cmd_rdyB;
cmd_startC <= cmd_validB_i and cmd_rdyC;
cmd_startD <= cmd_validB_i and cmd_rdyD;
cmd_startE <= cmd_validB_i and cmd_rdyE;
cmd_startF <= cmd_validB_i and cmd_rdyF;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000" ;
elsif (cmd_start = '1') then
if (FAMILY = "SPARTAN6") then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (fifo_not_full = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001" ;
else
user_burst_cnt <= "0000000" ;
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
u_bcount_2 <= '1' ;
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0' ;
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
cmd_rdy_o <= cmd_rdy and fifo_not_full;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1' ;
elsif (cmd_start = '1') then
if (bl_i = "000001") then
cmd_rdy <= '1' ;
else
cmd_rdy <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdy <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyB <= '1' ;
elsif (cmd_startB = '1') then
if (bl_i = "000001") then
cmd_rdyB <= '1' ;
else
cmd_rdyB <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyB <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyC <= '1' ;
elsif (cmd_startC = '1') then
if (bl_i = "000001") then
cmd_rdyC <= '1' ;
else
cmd_rdyC <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyC <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyD <= '1' ;
elsif (cmd_startD = '1') then
if (bl_i = "000001") then
cmd_rdyD <= '1' ;
else
cmd_rdyD <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyD <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyE <= '1' ;
elsif (cmd_startE = '1') then
if (bl_i = "000001") then
cmd_rdyE <= '1' ;
else
cmd_rdyE <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyE <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyF <= '1' ;
elsif (cmd_startF = '1') then
if (bl_i = "000001") then
cmd_rdyF <= '1' ;
else
cmd_rdyF <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyF <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(1)) = '1') then
data_valid <= '0' ;
elsif (cmd_start = '1') then
data_valid <= '1' ;
elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
data_valid <= '0' ;
end if;
end if;
end process;
data_valid_o <= data_valid and fifo_not_full;
s6_wdgen : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_startB,
cmd_startC => cmd_startC,
cmd_startD => cmd_startD,
cmd_startE => cmd_startE,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
v6_wdgen : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_starta => cmd_start,
cmd_startb => cmd_startB,
cmd_startc => cmd_startC,
cmd_startd => cmd_startD,
cmd_starte => cmd_startE,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --m_addr_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
end architecture trans;
| cc0-1.0 |
qu1x/fsio | src/lib/fsio_put.vhd | 1 | 1412 | -- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <n3vu0r@qu1x.org>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
library fsio;
use fsio.fsio.all;
entity fsio_put is
generic (
cap: integer := CAP;
len: integer := LEN
);
port (
clk: in std_logic;
hsi: in std_logic;
hso: out std_logic;
fsi: in std_logic_vector(cap - 1 downto 0);
fso: out std_logic_vector(cap - 1 downto 0);
dat: in std_logic_vector(len - 1 downto 0);
req: out std_logic;
ack: in std_logic
);
end fsio_put;
architecture behavioral of fsio_put is
begin
fso(len - 1 downto 0) <= dat;
req <= hso xor hsi;
ctl: process(clk)
begin
if rising_edge(clk) then
if fso = fsi then
hso <= hso xor (req and ack);
end if;
end if;
end process ctl;
end behavioral;
| agpl-3.0 |
chastell/art-decomp | kiss/opus_nov.vhd | 1 | 3496 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_nov;
architecture behaviour of opus_nov is
constant init0: std_logic_vector(3 downto 0) := "0001";
constant init1: std_logic_vector(3 downto 0) := "1000";
constant init2: std_logic_vector(3 downto 0) := "1100";
constant init4: std_logic_vector(3 downto 0) := "0011";
constant IOwait: std_logic_vector(3 downto 0) := "0000";
constant RMACK: std_logic_vector(3 downto 0) := "1101";
constant WMACK: std_logic_vector(3 downto 0) := "0010";
constant read0: std_logic_vector(3 downto 0) := "1010";
constant read1: std_logic_vector(3 downto 0) := "1111";
constant write0: std_logic_vector(3 downto 0) := "1110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "------";
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
else
case current_state is
when init0 =>
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
elsif std_match(input, "--0--") then next_state <= init1; output <= "110000";
end if;
when init1 =>
if std_match(input, "--00-") then next_state <= init1; output <= "110000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when init2 =>
if std_match(input, "--0--") then next_state <= init4; output <= "110100";
end if;
when init4 =>
if std_match(input, "--01-") then next_state <= init4; output <= "110100";
elsif std_match(input, "--00-") then next_state <= IOwait; output <= "000000";
end if;
when IOwait =>
if std_match(input, "0000-") then next_state <= IOwait; output <= "000000";
elsif std_match(input, "1000-") then next_state <= init1; output <= "110000";
elsif std_match(input, "01000") then next_state <= read0; output <= "101000";
elsif std_match(input, "11000") then next_state <= write0; output <= "100010";
elsif std_match(input, "01001") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "11001") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when RMACK =>
if std_match(input, "--0-0") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= read0; output <= "101000";
end if;
when WMACK =>
if std_match(input, "--0-0") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= write0; output <= "100010";
end if;
when read0 =>
if std_match(input, "--0--") then next_state <= read1; output <= "101001";
end if;
when read1 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when write0 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when others => next_state <= "----"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/ex6_rnd.vhd | 1 | 4231 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_rnd;
architecture behaviour of ex6_rnd is
constant s1: std_logic_vector(2 downto 0) := "101";
constant s3: std_logic_vector(2 downto 0) := "010";
constant s2: std_logic_vector(2 downto 0) := "011";
constant s4: std_logic_vector(2 downto 0) := "110";
constant s5: std_logic_vector(2 downto 0) := "111";
constant s6: std_logic_vector(2 downto 0) := "001";
constant s7: std_logic_vector(2 downto 0) := "000";
constant s8: std_logic_vector(2 downto 0) := "100";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--------";
case current_state is
when s1 =>
if std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11000000";
elsif std_match(input, "10---") then next_state <= s4; output <= "00101000";
end if;
when s2 =>
if std_match(input, "0-0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--1--") then next_state <= s5; output <= "00001110";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s3 =>
if std_match(input, "10---") then next_state <= s4; output <= "00111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11010000";
elsif std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "01---") then next_state <= s6; output <= "00110101";
end if;
when s4 =>
if std_match(input, "010--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "--1--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "000--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s5 =>
if std_match(input, "1-10-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--11-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "0-10-") then next_state <= s5; output <= "00001110";
end if;
when s6 =>
if std_match(input, "----1") then next_state <= s2; output <= "11000001";
elsif std_match(input, "10--0") then next_state <= s4; output <= "00101001";
elsif std_match(input, "00--0") then next_state <= s2; output <= "11000001";
elsif std_match(input, "11--0") then next_state <= s3; output <= "10111001";
elsif std_match(input, "01--0") then next_state <= s6; output <= "00100101";
end if;
when s7 =>
if std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "011--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "001--") then next_state <= s2; output <= "11000000";
end if;
when s8 =>
if std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "0-1--") then next_state <= s8; output <= "10000100";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
end if;
when others => next_state <= "---"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/dk16_jed.vhd | 1 | 12212 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk16_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk16_jed;
architecture behaviour of dk16_jed is
constant state_1: std_logic_vector(4 downto 0) := "11000";
constant state_3: std_logic_vector(4 downto 0) := "11100";
constant state_2: std_logic_vector(4 downto 0) := "01000";
constant state_4: std_logic_vector(4 downto 0) := "01010";
constant state_5: std_logic_vector(4 downto 0) := "01001";
constant state_6: std_logic_vector(4 downto 0) := "11011";
constant state_7: std_logic_vector(4 downto 0) := "11001";
constant state_9: std_logic_vector(4 downto 0) := "11010";
constant state_8: std_logic_vector(4 downto 0) := "10010";
constant state_15: std_logic_vector(4 downto 0) := "11110";
constant state_10: std_logic_vector(4 downto 0) := "10100";
constant state_14: std_logic_vector(4 downto 0) := "11101";
constant state_11: std_logic_vector(4 downto 0) := "10110";
constant state_12: std_logic_vector(4 downto 0) := "10000";
constant state_20: std_logic_vector(4 downto 0) := "01110";
constant state_13: std_logic_vector(4 downto 0) := "11111";
constant state_16: std_logic_vector(4 downto 0) := "10011";
constant state_17: std_logic_vector(4 downto 0) := "10001";
constant state_18: std_logic_vector(4 downto 0) := "01111";
constant state_19: std_logic_vector(4 downto 0) := "01100";
constant state_21: std_logic_vector(4 downto 0) := "00100";
constant state_22: std_logic_vector(4 downto 0) := "00101";
constant state_23: std_logic_vector(4 downto 0) := "01101";
constant state_24: std_logic_vector(4 downto 0) := "10111";
constant state_25: std_logic_vector(4 downto 0) := "10101";
constant state_26: std_logic_vector(4 downto 0) := "01011";
constant state_27: std_logic_vector(4 downto 0) := "00111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "00") then next_state <= state_3; output <= "001";
elsif std_match(input, "01") then next_state <= state_10; output <= "001";
elsif std_match(input, "10") then next_state <= state_11; output <= "001";
elsif std_match(input, "11") then next_state <= state_12; output <= "001";
end if;
when state_2 =>
if std_match(input, "00") then next_state <= state_1; output <= "001";
elsif std_match(input, "01") then next_state <= state_2; output <= "001";
elsif std_match(input, "10") then next_state <= state_8; output <= "001";
elsif std_match(input, "11") then next_state <= state_9; output <= "001";
end if;
when state_3 =>
if std_match(input, "00") then next_state <= state_4; output <= "001";
elsif std_match(input, "01") then next_state <= state_5; output <= "001";
elsif std_match(input, "10") then next_state <= state_6; output <= "001";
elsif std_match(input, "11") then next_state <= state_7; output <= "001";
end if;
when state_4 =>
if std_match(input, "00") then next_state <= state_4; output <= "010";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "010";
elsif std_match(input, "11") then next_state <= state_7; output <= "010";
end if;
when state_5 =>
if std_match(input, "00") then next_state <= state_1; output <= "010";
elsif std_match(input, "01") then next_state <= state_2; output <= "010";
elsif std_match(input, "10") then next_state <= state_16; output <= "010";
elsif std_match(input, "11") then next_state <= state_17; output <= "010";
end if;
when state_6 =>
if std_match(input, "00") then next_state <= state_3; output <= "010";
elsif std_match(input, "01") then next_state <= state_21; output <= "010";
elsif std_match(input, "10") then next_state <= state_10; output <= "010";
elsif std_match(input, "11") then next_state <= state_22; output <= "010";
end if;
when state_7 =>
if std_match(input, "00") then next_state <= state_9; output <= "010";
elsif std_match(input, "01") then next_state <= state_18; output <= "010";
elsif std_match(input, "10") then next_state <= state_19; output <= "010";
elsif std_match(input, "11") then next_state <= state_20; output <= "010";
end if;
when state_8 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_26; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_9 =>
if std_match(input, "00") then next_state <= state_1; output <= "000";
elsif std_match(input, "01") then next_state <= state_5; output <= "000";
elsif std_match(input, "10") then next_state <= state_6; output <= "000";
elsif std_match(input, "11") then next_state <= state_7; output <= "000";
end if;
when state_10 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_1; output <= "000";
elsif std_match(input, "11") then next_state <= state_2; output <= "000";
end if;
when state_11 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_24; output <= "000";
elsif std_match(input, "11") then next_state <= state_25; output <= "000";
end if;
when state_12 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_13 =>
if std_match(input, "00") then next_state <= state_3; output <= "101";
elsif std_match(input, "01") then next_state <= state_10; output <= "101";
elsif std_match(input, "10") then next_state <= state_11; output <= "101";
elsif std_match(input, "11") then next_state <= state_12; output <= "101";
end if;
when state_14 =>
if std_match(input, "00") then next_state <= state_1; output <= "101";
elsif std_match(input, "01") then next_state <= state_2; output <= "101";
elsif std_match(input, "10") then next_state <= state_8; output <= "101";
elsif std_match(input, "11") then next_state <= state_9; output <= "101";
end if;
when state_15 =>
if std_match(input, "00") then next_state <= state_4; output <= "101";
elsif std_match(input, "01") then next_state <= state_5; output <= "101";
elsif std_match(input, "10") then next_state <= state_6; output <= "101";
elsif std_match(input, "11") then next_state <= state_7; output <= "101";
end if;
when state_16 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_17 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_27; output <= "000";
end if;
when state_18 =>
if std_match(input, "00") then next_state <= state_4; output <= "100";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "100";
elsif std_match(input, "11") then next_state <= state_7; output <= "100";
end if;
when state_19 =>
if std_match(input, "00") then next_state <= state_18; output <= "100";
elsif std_match(input, "01") then next_state <= state_23; output <= "010";
elsif std_match(input, "10") then next_state <= state_24; output <= "100";
elsif std_match(input, "11") then next_state <= state_25; output <= "100";
end if;
when state_20 =>
if std_match(input, "00") then next_state <= state_19; output <= "100";
elsif std_match(input, "01") then next_state <= state_20; output <= "010";
elsif std_match(input, "10") then next_state <= state_9; output <= "100";
elsif std_match(input, "11") then next_state <= state_26; output <= "100";
end if;
when state_21 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_22 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "100";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_23 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_24 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_25 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_26 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_21; output <= "000";
end if;
when state_27 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/dk512_hot.vhd | 1 | 4742 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_hot;
architecture behaviour of dk512_hot is
constant state_1: std_logic_vector(14 downto 0) := "100000000000000";
constant state_8: std_logic_vector(14 downto 0) := "010000000000000";
constant state_2: std_logic_vector(14 downto 0) := "001000000000000";
constant state_4: std_logic_vector(14 downto 0) := "000100000000000";
constant state_3: std_logic_vector(14 downto 0) := "000010000000000";
constant state_5: std_logic_vector(14 downto 0) := "000001000000000";
constant state_6: std_logic_vector(14 downto 0) := "000000100000000";
constant state_13: std_logic_vector(14 downto 0) := "000000010000000";
constant state_7: std_logic_vector(14 downto 0) := "000000001000000";
constant state_9: std_logic_vector(14 downto 0) := "000000000100000";
constant state_10: std_logic_vector(14 downto 0) := "000000000010000";
constant state_11: std_logic_vector(14 downto 0) := "000000000001000";
constant state_12: std_logic_vector(14 downto 0) := "000000000000100";
constant state_14: std_logic_vector(14 downto 0) := "000000000000010";
constant state_15: std_logic_vector(14 downto 0) := "000000000000001";
signal current_state, next_state: std_logic_vector(14 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---------------"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_9; output <= "000";
end if;
when state_2 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "000";
end if;
when state_3 =>
if std_match(input, "0") then next_state <= state_5; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when state_4 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_11; output <= "000";
end if;
when state_5 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_12; output <= "000";
end if;
when state_6 =>
if std_match(input, "0") then next_state <= state_13; output <= "000";
elsif std_match(input, "1") then next_state <= state_14; output <= "000";
end if;
when state_7 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_15; output <= "000";
end if;
when state_8 =>
if std_match(input, "0") then next_state <= state_1; output <= "001";
elsif std_match(input, "1") then next_state <= state_2; output <= "001";
end if;
when state_9 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_10 =>
if std_match(input, "0") then next_state <= state_1; output <= "010";
elsif std_match(input, "1") then next_state <= state_2; output <= "010";
end if;
when state_11 =>
if std_match(input, "0") then next_state <= state_3; output <= "010";
elsif std_match(input, "1") then next_state <= state_4; output <= "010";
end if;
when state_12 =>
if std_match(input, "0") then next_state <= state_4; output <= "100";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_13 =>
if std_match(input, "0") then next_state <= state_5; output <= "100";
elsif std_match(input, "1") then next_state <= state_6; output <= "100";
end if;
when state_14 =>
if std_match(input, "0") then next_state <= state_3; output <= "100";
elsif std_match(input, "1") then next_state <= state_7; output <= "100";
end if;
when state_15 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when others => next_state <= "---------------"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/sse_jed.vhd | 1 | 6957 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_jed;
architecture behaviour of sse_jed is
constant st11: std_logic_vector(3 downto 0) := "0010";
constant st10: std_logic_vector(3 downto 0) := "0011";
constant st4: std_logic_vector(3 downto 0) := "1011";
constant st12: std_logic_vector(3 downto 0) := "1001";
constant st7: std_logic_vector(3 downto 0) := "0001";
constant st6: std_logic_vector(3 downto 0) := "0000";
constant st1: std_logic_vector(3 downto 0) := "1000";
constant st0: std_logic_vector(3 downto 0) := "1111";
constant st8: std_logic_vector(3 downto 0) := "1110";
constant st9: std_logic_vector(3 downto 0) := "1101";
constant st3: std_logic_vector(3 downto 0) := "0101";
constant st2: std_logic_vector(3 downto 0) := "0111";
constant st5: std_logic_vector(3 downto 0) := "1010";
constant st13: std_logic_vector(3 downto 0) := "1100";
constant st14: std_logic_vector(3 downto 0) := "0100";
constant st15: std_logic_vector(3 downto 0) := "0110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/dk27_nov.vhd | 1 | 2406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_nov;
architecture behaviour of dk27_nov is
constant START: std_logic_vector(2 downto 0) := "110";
constant state2: std_logic_vector(2 downto 0) := "010";
constant state3: std_logic_vector(2 downto 0) := "001";
constant state4: std_logic_vector(2 downto 0) := "111";
constant state5: std_logic_vector(2 downto 0) := "000";
constant state6: std_logic_vector(2 downto 0) := "100";
constant state7: std_logic_vector(2 downto 0) := "011";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/s27_jed.vhd | 1 | 3869 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_jed;
architecture behaviour of s27_jed is
constant s000: std_logic_vector(2 downto 0) := "110";
constant s001: std_logic_vector(2 downto 0) := "100";
constant s101: std_logic_vector(2 downto 0) := "000";
constant s100: std_logic_vector(2 downto 0) := "010";
constant s010: std_logic_vector(2 downto 0) := "011";
constant s011: std_logic_vector(2 downto 0) := "001";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s000 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
elsif std_match(input, "00-0") then next_state <= s000; output <= "1";
elsif std_match(input, "-0-1") then next_state <= s010; output <= "0";
end if;
when s001 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s101 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s100 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "00--") then next_state <= s000; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "10--") then next_state <= s100; output <= "1";
end if;
when s010 =>
if std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "000-") then next_state <= s010; output <= "0";
elsif std_match(input, "010-") then next_state <= s011; output <= "0";
elsif std_match(input, "1101") then next_state <= s101; output <= "1";
elsif std_match(input, "1111") then next_state <= s100; output <= "1";
elsif std_match(input, "10-1") then next_state <= s010; output <= "0";
elsif std_match(input, "1100") then next_state <= s101; output <= "1";
elsif std_match(input, "1110") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
end if;
when s011 =>
if std_match(input, "0-0-") then next_state <= s011; output <= "0";
elsif std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/lion_jed.vhd | 1 | 1832 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion_jed;
architecture behaviour of lion_jed is
constant st0: std_logic_vector(1 downto 0) := "10";
constant st1: std_logic_vector(1 downto 0) := "00";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "-0") then next_state <= st0; output <= "0";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "0-") then next_state <= st1; output <= "1";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "1-") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "0-") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/shiftreg_nov.vhd | 1 | 2558 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_nov;
architecture behaviour of shiftreg_nov is
constant st0: std_logic_vector(2 downto 0) := "000";
constant st1: std_logic_vector(2 downto 0) := "100";
constant st2: std_logic_vector(2 downto 0) := "011";
constant st3: std_logic_vector(2 downto 0) := "111";
constant st4: std_logic_vector(2 downto 0) := "010";
constant st5: std_logic_vector(2 downto 0) := "110";
constant st6: std_logic_vector(2 downto 0) := "001";
constant st7: std_logic_vector(2 downto 0) := "101";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st0; output <= "1";
elsif std_match(input, "1") then next_state <= st4; output <= "1";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st1; output <= "1";
elsif std_match(input, "1") then next_state <= st5; output <= "1";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st2; output <= "1";
elsif std_match(input, "1") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st3; output <= "1";
elsif std_match(input, "1") then next_state <= st7; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 |
End of preview. Expand
in Dataset Viewer.
Dataset Card for AI-HDLCoder
Dataset Description
The GitHub Code dataset consists of 100M code files from GitHub in VHDL programming language with extensions totaling in 1.94 GB of data. The dataset was created from the public GitHub dataset on Google BiqQuery at Anhalt University of Applied Sciences.
Considerations for Using the Data
The dataset is created for research purposes and consists of source code from a wide range of repositories. As such they can potentially include harmful or biased code as well as sensitive information like passwords or usernames.
Languages
{
"VHDL": [".vhdl",".vhd" ]
}
Dataset Structure
Data Instances
{
"repo_name": "sebgod/linguist",
"path": "samples/VHDL/foo.vhd",
"copies": "91",
"size": "217",
"content": "-- VHDL example file\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity inverter is\n\tport(a : in std_logic;\n\t b : out std_logic);\nend entity;\n\narchitecture rtl of inverter is\nbegin\n\tb \u003c\u003d not a;\nend architecture;\n",
"license": "mit"
}
Data Fields
| Field | Type | Description |
|---|---|---|
| content | string | content of source file |
| repo_name | string | name of the GitHub repository |
| path | string | path of file in GitHub repository |
| license | string | license of GitHub repository |
| size | int | size of source file in bytes |
Data Splits
The dataset contains a train split only
Licensing Information
[
'agpl-3.0',
'artistic-2.0',
'mpl-2.0',
'cc0-1.0',
'mit',
'gpl-2.0',
'gpl-3.0',
'lgpl-3.0',
'apache-2.0',
'bsd-3-clause'
]
v1.0
- Initial release of dataset
- The query was executed on 21.07.2023, 00:02:38 UTC+2
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