repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
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stringclasses 15
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|---|---|---|---|---|---|
UVVM/uvvm_vvc_framework | bitvis_vip_sbi/src/sbi_vvc.vhd | 1 | 21046 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: In addition to being a VVC for the SBI, this module is also used as a template
-- and a well commented example of the VVC structure and functionality
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.sbi_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity sbi_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8; -- SBI address bus
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32; -- SBI data bus
GC_INSTANCE_IDX : natural := 1; -- Instance index for this SBI_VVCT instance
GC_SBI_CONFIG : t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
clk : in std_logic;
sbi_vvc_master_if : inout t_sbi_if := init_sbi_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (sbi_vvc_master_if.addr'length = GC_ADDR_WIDTH) report "sbi_vvc_master_if.addr'length =/ GC_ADDR_WIDTH" severity failure;
assert (sbi_vvc_master_if.wdata'length = GC_DATA_WIDTH) report "sbi_vvc_master_if.wdata'length =/ GC_DATA_WIDTH" severity failure;
assert (sbi_vvc_master_if.rdata'length = GC_DATA_WIDTH) report "sbi_vvc_master_if.rdata'length =/ GC_DATA_WIDTH" severity failure;
end entity sbi_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of sbi_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_sbi_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_sbi_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_sbi_transaction_info(GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_SBI_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK or v_cmd.operation = POLL_UNTIL then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_write() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_write() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_write(addr_value => v_normalised_addr,
data_value => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when READ =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_read() called with to wide addrress. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_read(addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH - 1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
when CHECK =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_check() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_check(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when POLL_UNTIL =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_poll_until() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_poll_until() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_poll_until(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
max_polls => v_cmd.max_polls,
timeout => v_cmd.timeout,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
terminate_loop => terminate_current_cmd.is_active,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
| mit |
UVVM/uvvm_vvc_framework | bitvis_irqc/src/irqc_pif.vhd | 3 | 4203 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.irqc_pif_pkg.all;
entity irqc_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end irqc_pif;
architecture rtl of irqc_pif is
signal p2c_i : t_p2c; -- internal version of output
signal dout_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
dout_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_IRR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_irr;
when C_ADDR_IER =>
dout_i(C_NUM_SOURCES-1 downto 0) <= p2c_i.rw_ier;
when C_ADDR_IPR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_ipr;
when C_ADDR_IRQ2CPU_ALLOWED =>
dout_i(0) <= c2p.aro_irq2cpu_allowed;
when others =>
null;
end case;
end if;
end process p_read_reg;
dout <= dout_i;
-- Writing to registers that are not functionally manipulated
p_write_reg : process(clk, arst)
begin
if arst = '1' then
p2c_i.rw_ier <= (others => '0');
elsif rising_edge(clk) then
if cs = '1' and wr = '1' then
case to_integer(addr) is
when C_ADDR_IER =>
p2c_i.rw_ier <= din(C_NUM_SOURCES-1 downto 0);
-- Auxiliary write (below)
when others =>
null;
end case;
end if;
end if;
end process p_write_reg;
-- Writing to registers that are functionally manipulated and/or located outside PIF (or dummy registers)
p_aux : process(wr, addr, din)
begin
-- Note that arst is not considered here, but must be considered in any clocked process in the core
-- Default - always to return to these values
p2c_i.awt_icr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_itr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_irq2cpu_ena <= '0';
p2c_i.awt_irq2cpu_disable <= '0';
if (cs = '1' and wr = '1') then
case to_integer(addr) is
when C_ADDR_ITR =>
p2c_i.awt_itr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_ICR =>
p2c_i.awt_icr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_IRQ2CPU_ENA =>
p2c_i.awt_irq2cpu_ena <= din(0);
when C_ADDR_IRQ2CPU_DISABLE =>
p2c_i.awt_irq2cpu_disable <= din(0);
when others =>
null;
end case;
end if;
end process p_aux;
end rtl;
| mit |
UVVM/uvvm_vvc_framework | bitvis_vip_uart/src/uart_bfm_pkg.vhd | 1 | 26306 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: This BFM is only intended as a simplified UART BFM to be used as a test
-- vehicle for presenting UVVM functionality.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library STD;
use std.textio.all;
--=================================================================================================
package uart_bfm_pkg is
--===============================================================================================
-- Types and constants for UART BFMs
--===============================================================================================
constant C_SCOPE : string := "UART BFM";
-- Configuration record to be assigned in the test harness.
type t_parity is (
PARITY_NONE,
PARITY_ODD,
PARITY_EVEN
);
type t_stop_bits is (
STOP_BITS_ONE,
STOP_BITS_ONE_AND_HALF,
STOP_BITS_TWO
);
constant C_MAX_BITS_IN_RECEIVED_DATA : natural := 8;
constant C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR : string := "; ";
type uart_expect_received_data_array is array (natural range<>) of std_logic_vector(C_MAX_BITS_IN_RECEIVED_DATA-1 downto 0);
type t_uart_bfm_config is
record
bit_time : time; -- The time it takes to transfer one bit
num_data_bits : natural range 7 to 8; -- Number of data bits to send per transmission
idle_state : std_logic; -- Bit value when line is idle
num_stop_bits : t_stop_bits; -- Number of stop-bits to use per transmission {STOP_BITS_ONE, STOP_BITS_ONE_AND_HALF, STOP_BITS_TWO}
parity : t_parity; -- Transmission parity bit {PARITY_NONE, PARITY_ODD, PARITY_EVEN}
timeout : time; -- The maximum time to pass before the expected data must be received. Exceeding this limit results in an alert with severity ‘alert_level’.
timeout_severity : t_alert_level; -- The above timeout will have this severity
num_bytes_to_log_before_expected_data : natural; -- Maximum number of bytes to save ahead of the expected data in the receive buffer. The bytes in the receive buffer will be logged.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the UART BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the UART BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the UART BFM
id_for_bfm_poll_summary : t_msg_id; -- The message ID used for logging polling summary in the UART BFM
end record;
constant C_UART_BFM_CONFIG_DEFAULT : t_uart_bfm_config := (
bit_time => -1 ns,
num_data_bits => 8,
idle_state => '1',
num_stop_bits => STOP_BITS_ONE,
parity => PARITY_ODD,
timeout => 0 ns, -- will default never time out
timeout_severity => error,
num_bytes_to_log_before_expected_data => 10,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL,
id_for_bfm_poll_summary => ID_BFM_POLL_SUMMARY
);
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
------------------------------------------
-- uart_transmit
------------------------------------------
-- - This procedure transmits data 'data_value' to the UART DUT
-- - The TX configuration can be set in the config parameter
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- uart_receive
------------------------------------------
-- - This procedure reads data from the UART DUT and returns it in 'data_value'
-- - The RX configuration can be set in the config parameter
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call: in string := "" -- External proc_call; used if called from other BFM procedure like uart_expect
);
------------------------------------------
-- uart_expect
------------------------------------------
-- - This procedure reads data from the UART DUT and compares it to the data in
-- 'data_exp'.
-- - If the read data is inconsistent with the 'data_exp' data, a new read will
-- be performed, and the new read data will be compared with 'data_exp'.
-- This process will continue untill one of the following conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_receptions'
-- c) The time spent reading is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_receptions' is set to 0, it will be interpreted as no limitation on number of reads
-- - The RX configuration can be set in the config parameter
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- odd_parity
------------------------------------------
-- - This function checks if the data parity is odd or even
-- - If the number of '1' in the 'data' input is odd, '1' will be returned
-- - If the number of '1' in the 'data' input is even, '0' will be returned
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic;
end package uart_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body uart_bfm_pkg is
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic is
begin
return xnor(data);
end odd_parity;
---------------------------------------------------------------------------------
-- uart_transmit
---------------------------------------------------------------------------------
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_transmit";
constant proc_call : string := proc_name & "(" & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- check if tx line was idle when trying to transmit data
check_value(tx, config.idle_state, FAILURE, proc_call & " Bus was active when trying to send data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
tx <= not config.idle_state;
wait for config.bit_time;
for j in data_value'low to data_value'high loop
tx <= data_value(j);
wait for config.bit_time;
end loop;
-- parity?
if (config.parity = PARITY_ODD) then
tx <= odd_parity(data_value);
wait for config.bit_time;
elsif(config.parity = PARITY_EVEN) then
tx <= not odd_parity(data_value);
wait for config.bit_time;
end if;
-- stop bits
tx <= config.idle_state;
wait for config.bit_time;
if (config.num_stop_bits = STOP_BITS_ONE_AND_HALF) then
wait for config.bit_time/2;
elsif(config.num_stop_bits = STOP_BITS_TWO) then
wait for config.bit_time;
end if;
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
---------------------------------------------------------------------------------
-- uart_receive
---------------------------------------------------------------------------------
-- Perform a receive operation
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call: in string := "" -- External proc_call; used if called from other BFM procedure like uart_expect
) is
constant start_time : time := now;
-- local_proc_* used if uart_receive is called directly from sequencer or VVC
constant local_proc_name : string := "uart_receive";
constant local_proc_call : string := local_proc_name & "()";
-- Helper variables
variable v_transfer_time : time;
variable v_proc_call : line; -- Current proc_call, external or internal
variable v_remaining_time : time; -- temp variable to calculate the remaining time before timeout
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_terminated : boolean := false;
variable v_timeout : boolean := false;
begin
-- check whether config.bit_time was set properly
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
data_value := (data_value'range => 'X');
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- If timeout enabled, check that timeout is longer than transfer time
if config.timeout /= 0 ns then
v_transfer_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_transfer_time := v_transfer_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
check_value(v_transfer_time < config.timeout, TB_ERROR, "Length of timeout is shorter than or equal length of transfer time.", C_SCOPE, ID_NEVER, msg_id_panel);
end if;
if ext_proc_call = "" then
-- called from sequencer/VVC, show 'uart_receive()...' in log
write(v_proc_call, local_proc_call);
else
-- called from other BFM procedure like uart_expect, log 'uart_expect() while executing uart_receive()...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name & ". ");
end if;
-- check if bus is in idle state
check_value(rx, config.idle_state, FAILURE, v_proc_call.all & "Bus was active when trying to receive data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait until the start bit is sent on the bus, configured timeout occures or procedure get terminate signal
if config.timeout = 0 ns then
wait until (rx /= config.idle_state) or (terminate_loop = '1');
else
wait until (rx /= config.idle_state) or (terminate_loop = '1') for config.timeout;
end if;
if terminate_loop = '1' then
if ext_proc_call = "" then
log(ID_TERMINATE_CMD, v_proc_call.all & "=> terminated." & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- termination handled in calling procedure
end if;
v_terminated := true;
end if;
-- if configured timeout, check if there is enough time remaining to receive the byte
if config.timeout /= 0 ns and not v_terminated then
v_remaining_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_remaining_time := v_remaining_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if now + v_remaining_time > start_time + config.timeout then
-- wait until timeout
wait for ((start_time + config.timeout) - now);
if ext_proc_call = "" then
alert(config.timeout_severity, v_proc_call.all & "=> timeout. " & add_msg_delimiter(msg),scope);
else
-- timeout handled in upper module
end if;
v_timeout := true;
end if;
end if;
if not v_terminated and not v_timeout then
-- enter the middle of the bit period
wait for config.bit_time/2;
check_value(rx , not config.idle_state, FAILURE, v_proc_call.all & " Start bit was not stable during receiving. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait for data bit
wait for config.bit_time;
-- sample the data bits
for i in 0 to config.num_data_bits-1 loop
v_data_value(i) := rx;
-- wait for middle of the next bit
wait for config.bit_time;
end loop;
-- check parity, if enabled
if config.parity = PARITY_ODD then
if rx /= odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
elsif config.parity = PARITY_EVEN then
if rx /= not odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
end if;
-- check the stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect stop bit received. " & add_msg_delimiter(msg),scope);
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
wait for config.bit_time/2 + config.bit_time/4; -- middle of the last half. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second half stop bit received. " & add_msg_delimiter(msg),scope);
end if;
elsif config.num_stop_bits = STOP_BITS_TWO then
wait for config.bit_time; -- middle of the last bit. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second stop bit received. " & add_msg_delimiter(msg),scope);
end if;
end if;
-- return the received data
data_value := v_data_value;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. uart_expect)
end if;
end if;
end procedure;
----------------------------------------------------------------------------------------
-- uart_expect
----------------------------------------------------------------------------------------
-- Perform a receive operation, then compare the received value to the expected value.
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1; -- 0 = any occurrence before timeout
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_expect";
constant proc_call : string := proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
constant start_time : time := now;
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_num_of_occurrences : natural := 0;
variable v_check_ok : boolean;
variable v_num_of_occurrences_ok : boolean;
variable v_timeout_ok : boolean;
variable v_config : t_uart_bfm_config := config;
variable v_received_data_fifo : uart_expect_received_data_array(0 to v_config.num_bytes_to_log_before_expected_data-1) := (others => (others =>'0'));
variable v_received_data_fifo_write_idx : natural := 0;
variable v_received_output_line : line;
variable v_internal_timeout : time;
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- if timeout = -1 function was called without parameter
if timeout = -1 ns then
v_internal_timeout := config.timeout;
else
v_internal_timeout := timeout;
end if;
assert (v_internal_timeout >= 0 ns) report "configured negative timeout(not allowed). " & add_msg_delimiter(msg) severity failure;
-- Check for v_internal_timeout = 0 and max_receptions = 0. This combination can result in an infinite loop.
if v_internal_timeout = 0 ns and max_receptions = 0 then
alert(ERROR, proc_name & " called with timeout=0 and max_receptions = 0. This combination can result in an infinite loop. " & add_msg_delimiter(msg),scope);
end if;
if v_internal_timeout = 0 ns then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences. " & msg, scope, msg_id_panel);
elsif max_receptions = 0 then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
else
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences and " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
end if;
-- Initial status of check variables
v_check_ok := false;
v_timeout_ok := true;
if max_receptions < 1 then
v_num_of_occurrences_ok := true;
else
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Setup of v_config with correct timeout
v_config.timeout := v_internal_timeout;
-- Check operation
while not v_check_ok and v_timeout_ok and v_num_of_occurrences_ok and (terminate_loop = '0') loop
-- Receive and check data
uart_receive(v_data_value, msg, rx, terminate_loop, v_config, scope, msg_id_panel, proc_call);
for i in 0 to v_config.num_data_bits-1 loop
if (data_exp(i) = '-' or
v_data_value(i) = data_exp(i)) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
-- Place the received data in the received data buffer for debugging
-- If the FIFO is not full, fill it up
if v_received_data_fifo_write_idx < v_config.num_bytes_to_log_before_expected_data then
v_received_data_fifo(v_received_data_fifo_write_idx)(v_data_value'length-1 downto 0) := v_data_value;
v_received_data_fifo_write_idx := v_received_data_fifo_write_idx + 1;
else
-- If the FIFO is full, left shift all input and append new data
for i in 1 to v_config.num_bytes_to_log_before_expected_data-1 loop
v_received_data_fifo(i-1) := v_received_data_fifo(i);
end loop;
v_received_data_fifo(v_received_data_fifo_write_idx-1)(v_data_value'length-1 downto 0) := v_data_value;
end if;
-- Evaluate number of occurrences, if limited by user
if max_receptions > 0 then
v_num_of_occurrences := v_num_of_occurrences + 1;
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Evaluate timeout if specified by user
if v_internal_timeout = 0 ns then
v_timeout_ok := true;
else
v_timeout_ok := now < start_time + v_internal_timeout;
end if;
end loop;
-- Concatenate the string FIFO into a single string with given separators
for i in 0 to v_received_data_fifo_write_idx-1 loop
write(v_received_output_line, to_string(v_received_data_fifo(i), HEX, SKIP_LEADING_0, INCL_RADIX));
if i /= v_received_data_fifo_write_idx-1 then
write(v_received_output_line, C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR);
end if;
end loop;
if max_receptions > 1 then
-- Print the received string of bytes
log(v_config.id_for_bfm_poll_summary, "Last "& to_string(v_received_data_fifo_write_idx) & " received data bytes while waiting for expected data: " & v_received_output_line.all, scope, msg_id_panel);
end if;
if v_check_ok then
log(v_config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & " after " & to_string(v_num_of_occurrences) & " occurrences and " & to_string((now - start_time),ns) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
elsif not v_timeout_ok then
alert(config.timeout_severity, proc_call & "=> Failed due to timeout. Did not get expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " before time " & to_string(v_internal_timeout,ns) & ". " & add_msg_delimiter(msg), scope);
elsif not v_num_of_occurrences_ok then
if max_receptions = 1 then
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences, received value " & to_string(v_data_value, HEX, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope);
else
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences. " & add_msg_delimiter(msg), scope);
end if;
else
alert(warning, proc_call & "=> Failed. Terminate loop received. " & add_msg_delimiter(msg), scope);
end if;
end procedure;
end package body uart_bfm_pkg;
| mit |
UVVM/uvvm_vvc_framework | bitvis_vip_i2c/src/vvc_methods_pkg.vhd | 1 | 29522 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.i2c_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the I2C VVC
--===============================================================================================
constant C_VVC_NAME : string := "I2C_VVC";
signal I2C_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is I2C_VVCT;
alias t_bfm_config is t_i2c_bfm_config;
constant C_I2C_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_i2c_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_I2C_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_I2C_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_I2C_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0);
data : t_byte_array(0 to C_VVC_CMD_DATA_MAX_LENGTH-1);
num_bytes : natural;
action_when_transfer_is_done : t_action_when_transfer_is_done;
exp_ack : boolean;
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
addr => (others => '0'),
data => (others => (others => '0')),
num_bytes => 0,
operation => NO_OPERATION,
msg => (others => ' '),
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
exp_ack => true
);
shared variable shared_i2c_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_I2C_VVC_CONFIG_DEFAULT);
shared variable shared_i2c_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_i2c_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT);
--==============================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order to queue BFM calls
-- in the VVC command queue. The VVC will store and forward these calls to the
-- I2C BFM when the command is at the from of the VVC command queue.
-- - For details on how the BFM procedures work, see i2c_bfm_pkg.vhd or the
-- quickref.
--==============================================================================
-- *****************************************************************************
--
-- master transmit
--
-- *****************************************************************************
-- multi-byte
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER
);
-- single byte
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER
);
-- *****************************************************************************
--
-- slave transmit
--
-- *****************************************************************************
-- multi-byte
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string
);
-- single byte
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
);
-- *****************************************************************************
--
-- master receive
--
-- *****************************************************************************
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER
);
-- *****************************************************************************
--
-- master check
--
-- *****************************************************************************
-- multi-byte
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error
);
-- single byte
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error
);
procedure i2c_master_quick_command(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error
);
-- *****************************************************************************
--
-- slave receive
--
-- *****************************************************************************
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant msg : in string
);
-- *****************************************************************************
--
-- slave check
--
-- *****************************************************************************
-- multi-byte
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0' -- Default write bit
);
-- single byte
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0' -- Default write bit
);
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant rw_bit : in std_logic;
constant msg : in string;
constant alert_level : in t_alert_level := error
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
-- master transmit
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT);
end procedure;
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_transmit(VVCT, vvc_instance_idx, addr, v_byte_array, msg, action_when_transfer_is_done);
end procedure;
-- slave transmit
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT);
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
send_command_to_vvc(VVCT);
end procedure;
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
) is
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_transmit(VVCT, vvc_instance_idx, v_byte_array, msg);
end procedure;
-- master receive
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_NARROWER, "addr", "shared_vvc_cmd.addr", msg);
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_RECEIVE);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.num_bytes := num_bytes;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT);
end procedure;
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_RECEIVE);
shared_vvc_cmd.num_bytes := num_bytes;
send_command_to_vvc(VVCT);
end procedure;
-- master check
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT);
end procedure;
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_check(VVCT, vvc_instance_idx, addr, v_byte_array, msg, action_when_transfer_is_done, alert_level);
end procedure;
procedure i2c_master_quick_command(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_QUICK_CMD);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.exp_ack := exp_ack;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.rw_bit := rw_bit;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT);
end procedure;
-- slave check
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0' -- Default write bit
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK);
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.rw_bit := rw_bit;
send_command_to_vvc(VVCT);
end procedure;
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0' -- Default write bit
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_check(VVCT, vvc_instance_idx, v_byte_array, msg, alert_level, rw_bit);
end procedure;
-- slave check
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant rw_bit : in std_logic;
constant msg : in string;
constant alert_level : in t_alert_level := error
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_dummy_byte_array : t_byte_array(0 to -1); -- Empty byte array to indicate that data is not checked
begin
i2c_slave_check(VVCT, vvc_instance_idx, v_dummy_byte_array, msg, alert_level, rw_bit);
end procedure;
end package body vvc_methods_pkg;
| mit |
UVVM/uvvm_vvc_framework | uvvm_util/src/license_pkg.vhd | 2 | 5312 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
package license_pkg is
impure function show_license(
constant dummy : in t_void
) return boolean;
impure function show_uvvm_utility_library_info(
constant dummy : in t_void
) return boolean;
impure function show_uvvm_utility_library_release_info(
constant dummy : in t_void
) return boolean;
end package license_pkg;
package body license_pkg is
impure function show_license(
constant dummy : in t_void
) return boolean is
constant C_SEPARATOR : string :=
"*****************************************************************************************************";
constant C_LICENSE_STR : string :=
LF & LF & LF &
C_SEPARATOR & LF &
" This is a *** LICENSED PRODUCT *** as given in the LICENSE.TXT in the root directory." & LF &
C_SEPARATOR & LF & LF;
begin
report (C_LICENSE_STR);
return true;
end;
impure function show_uvvm_utility_library_info(
constant dummy : in t_void
) return boolean is
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
"This info section may be turned off via C_SHOW_UVVM_UTILITY_LIBRARY_INFO in adaptations_pkg.vhd" & LF & LF &
"Important Simulator setup: " & LF &
"- Set simulator to break on severity 'FAILURE' " & LF &
"- Set simulator transcript to a monospace font (e.g. Courier new)" & LF & LF &
"UVVM Utility Library setup:" & LF &
"- It is recommended to go through the two powerpoint presentations provided with the download" & LF &
"- There is a Quick-Reference in the doc-directory" & LF &
"- In order to change layout or behaviour - please check the src*/adaptations_pkg.vhd" & LF &
" This is intended for personal or company customization" & LF & LF &
"License conditions are given in LICENSE.TXT" & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
if C_SHOW_UVVM_UTILITY_LIBRARY_INFO then
report (C_LICENSE_STR);
end if;
return true;
end;
impure function show_uvvm_utility_library_release_info(
constant dummy : in t_void
) return boolean is
constant C_IMPORTANT_UPDATE_FOR_THIS_VERSION : boolean := false; -- ***** NOTE: Evaluate a change here
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
"This release info may be turned off via C_SHOW_UVVM_UTILITY_LIBRARY_INFO in adaptations_pkg.vhd" & LF & LF &
"Important Issues for this version update: " & LF &
"- First release" & LF & LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
if C_SHOW_UVVM_UTILITY_LIBRARY_INFO and C_IMPORTANT_UPDATE_FOR_THIS_VERSION then
report (C_LICENSE_STR);
end if;
return true;
end;
end package body license_pkg;
| mit |
UVVM/uvvm_vvc_framework | bitvis_vip_gpio/tb/gpio_vip_tb.vhd | 1 | 15090 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file (see LICENSE.TXT), if not, contact Bitvis AS <info@bitvis.no>.
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
-- Include Verification IPs
library bitvis_vip_gpio;
use bitvis_vip_gpio.vvc_methods_pkg.all;
use bitvis_vip_gpio.td_vvc_framework_common_methods_pkg.all;
use bitvis_vip_gpio.td_target_support_pkg.all;
use bitvis_vip_gpio.gpio_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.vvc_methods_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
-- Test case entity
entity gpio_vip_tb is
end entity;
-- Test case architecture
architecture func of gpio_vip_tb is
constant C_CLK_PERIOD : time := 10 ns;
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant C_GPIO_WIDTH : natural := 8;
constant C_GPIO_SET_MAX_TIME : time := 1 ps;
signal gpio_1_input : std_logic_vector(C_GPIO_WIDTH-1 downto 0);
signal gpio_2_output : std_logic_vector(C_GPIO_WIDTH-1 downto 0);
-- Procedure for sanity checking, logging and setting "data" on "pins"
procedure set_gpio(
signal pins : out std_logic_vector;
constant data : std_logic_vector;
constant msg : string
) is
begin
if pins'length /= data'length then
alert(TB_ERROR, "pin length " & to_string(pins'length) & " and data length " & to_string(data'length) & " does not match.");
end if;
log("Setting GPIO to " & to_string(data, BIN) & ". " & add_msg_delimiter(msg));
pins <= data;
end procedure;
begin
-----------------------------------------------------------------------------
-- Instantiate test harness, containing DUT and Executors
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-- GPIO as input
i1_gpio_vvc : entity work.gpio_vvc
generic map(
GC_DATA_WIDTH => C_GPIO_WIDTH,
GC_INSTANCE_IDX => 1,
GC_DEFAULT_LINE_VALUE => x"ZZ"
)
port map (
gpio_vvc_if => gpio_1_input
);
-- GPIO as output
i2_gpio_vvc : entity work.gpio_vvc
generic map(
GC_DATA_WIDTH => C_GPIO_WIDTH,
GC_INSTANCE_IDX => 2,
GC_DEFAULT_LINE_VALUE => x"00"
)
port map (
gpio_vvc_if => gpio_2_output
);
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main : process
-- Helper variables
variable v_received_data : t_vvc_result;
variable v_set_data : std_logic_vector(7 downto 0);
variable v_expect_data : std_logic_vector(7 downto 0);
variable v_vvc_id : natural;
variable v_cmd_idx : natural;
variable v_is_ok : boolean;
begin
await_uvvm_initialization(VOID);
set_alert_stop_limit(error, 2);
set_alert_stop_limit(TB_WARNING, 5);
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
--disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_SEQUENCER);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_BFM);
disable_log_msg(GPIO_VVCT, 1, ALL_MESSAGES);
enable_log_msg(GPIO_VVCT, 1, ID_BFM);
disable_log_msg(GPIO_VVCT, 2, ALL_MESSAGES);
enable_log_msg(GPIO_VVCT, 2, ID_BFM);
log(ID_LOG_HDR, "Verifying TLM + GPIO executor + BFM", C_SCOPE);
wait for C_CLK_PERIOD*10;
------------------------------------------------------------
--------------------------------------------------------------------------------------
--
-- Checking of initial state
--
--------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Checking initial state of output VVC", C_SCOPE);
--
-- Check GPIO initial setting is 0x00
--
check_value(gpio_2_output, "00000000", error, "Checking initial value of GPIO VVC 2");
--------------------------------------------------------------------------------------
--
-- Test of GPIO VVC Set method
--
--------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Test of GPIO Set", C_SCOPE);
--
-- Set GPIO setting to 0xAA. Check GPIO setting
--
v_set_data := x"FF"; -- "1111 11111"
v_expect_data := v_set_data;
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
wait for C_CLK_PERIOD; -- Margin
--
-- Set GPIO setting to 0xAA. Check GPIO setting
--
v_set_data := x"AA"; -- "1010 1010"
v_expect_data := v_set_data;
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
wait for C_CLK_PERIOD; -- Margin
--
-- Set GPIO setting to 0x00. Check GPIO setting
--
v_set_data := x"00"; -- "0000 0000"
v_expect_data := v_set_data;
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
wait for C_CLK_PERIOD*4; -- Margin
--
-- Set GPIO setting to 0xFF. Check GPIO setting
--
v_set_data := x"FF"; -- "1111 1111"
v_expect_data := v_set_data;
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
wait for C_CLK_PERIOD*4; -- Margin
--------------------------------------------------------------------------------------
--
-- Test of GPIO VVC Set method with don't care
--
--------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Test of GPIO Set with don't care", C_SCOPE);
--
-- GPIO status is 0xFF. Test by setting bit 4-7, don't touch bit 0-3
--
v_set_data := x"5-"; -- "0101 ----", should now be 0x5F
v_expect_data := x"5F";
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
--
-- GPIO setting is 0x5F. Test by setting bit 0-3, don't touch bit 4-7
--
v_set_data := x"-A"; -- "---- 1010", should now be 0x5A
v_expect_data := x"5A";
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
wait for C_CLK_PERIOD*4; -- Margin
--
-- Set GPIO setting to 0x55. Check bit 0 and bit 4, ignore bit 1-3 and 5-7
--
v_set_data := "01010101"; -- 0x55
v_expect_data := "---1---1";
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
--
-- Set GPIO bit 1-3 and bit 5-7. Change bit 1-3 and 5-7, check bit 0 and bit 4
--
v_set_data := "101-101-";
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
wait for C_CLK_PERIOD; -- Margin
--
-- Set GPIO setting to 0xAZ. Check bit 4-7 is A, ignore bit 0-3
--
v_set_data := x"AZ";
v_expect_data := "1010----";
gpio_set(GPIO_VVCT, 2, v_set_data, "Setting gpio 2 to 0x" & to_string(v_set_data, HEX) & " (" & to_string(v_set_data, BIN) & ").");
await_completion(GPIO_VVCT, 2, C_GPIO_SET_MAX_TIME);
check_value(gpio_2_output, v_expect_data, error, "Checking value of GPIO VVC 2");
wait for C_CLK_PERIOD; -- Margin
--------------------------------------------------------------------------------------
--
-- Test of GPIO VVC Get method
--
--------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Test of GPIO Get", C_SCOPE);
log("Testing get on GPIO VVC 1");
--
-- Set GPIO 1 input manually to 0x1D. Test GPIO Get method and check
-- received data from GPIO setting.
--
v_set_data := x"1D";
v_expect_data := v_set_data;
set_gpio(gpio_1_input, v_set_data, "GPIO 1 input");
-- Perform get, which stores the data in the VVC
gpio_get(GPIO_VVCT, 1, "Readback inside VVC");
v_cmd_idx := get_last_received_cmd_idx(GPIO_VVCT, 1); -- for last get
await_completion(GPIO_VVCT, 1, v_cmd_idx, 100 ns, "Wait for gpio_get to finish");
-- Fetch the result from index v_cmd_idx (last index set above)
fetch_result(GPIO_VVCT, 1, v_cmd_idx, v_received_data, v_is_ok, "Fetching get-result");
-- Check if get was OK and that the data is correct
check_value(v_is_ok, error, "Readback OK via fetch_result()");
check_value(v_received_data, v_expect_data, error, "Readback data via fetch_result()");
wait for C_CLK_PERIOD*4; -- Margin
--------------------------------------------------------------------------------------
--
-- Test of GPIO VVC Check method
--
--------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Test of GPIO Check", C_SCOPE);
log("Testing check on GPIO VVC 1");
--
-- Set GPIO 1 input manually to 0x55. Call GPIO Check and check actual GPIO
-- setting with expected GPIO setting.
--
v_set_data := x"55";
v_expect_data := v_set_data;
set_gpio(gpio_1_input, v_set_data, "GPIO 1 input");
wait for C_CLK_PERIOD;
-- Perform get, which stores the data in the VVC
gpio_check(GPIO_VVCT, 1, v_expect_data, "Readback inside VVC", error);
wait for C_CLK_PERIOD*4;
--------------------------------------------------------------------------------------
--
-- Test of GPIO VVC Expect method
--
--------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Test of GPIO Expect", C_SCOPE);
log("Testing gpio_expect as instant change check");
--
-- Set GPIO setting to 0xFF. Test GPIO Expect and that GPIO setting is
-- updated immediately (within 0 ns).
--
v_set_data := x"FF";
v_expect_data := v_set_data;
set_gpio(gpio_1_input, v_set_data, "Setting GPIO 1 input to 0xff");
gpio_expect(GPIO_VVCT, 1, v_expect_data, 0 ns, "Checking GPIO 1", error);
v_cmd_idx := get_last_received_cmd_idx(GPIO_VVCT, 1); -- for last get
await_completion(GPIO_VVCT, 1, v_cmd_idx, 100 ns, "Wait for gpio_expect to finish");
--
-- Set GPIO setting to 0xFF, then to 0x12 after 90 ns. Test GPIO Expect
-- with delay by checking that GPIO setting is set to 0x12 after 100 ns.
--
log("Testing gpio_expect where value is correct after a delay");
v_set_data := x"FF";
v_expect_data := x"12";
set_gpio(gpio_1_input, v_set_data, "Setting GPIO 1 input to 0xff");
wait for C_CLK_PERIOD;
gpio_expect(GPIO_VVCT, 1, v_expect_data, 100 ns, "Checking GPIO 1", error);
wait for 80 ns;
v_set_data := x"12";
set_gpio(gpio_1_input, v_set_data, "Setting GPIO 1 input to 0x12");
v_cmd_idx := get_last_received_cmd_idx(GPIO_VVCT, 1); -- for last get
await_completion(GPIO_VVCT, 1, v_cmd_idx, 100 ns, "Wait for gpio_expect to finish");
--
-- Set GPIO setting to 0xFF, 0xAA, 0xAB, 0xAC and finally 0x00. Test GPIO
-- Expect by checking that GPIO setting is set to 0x00 after 10 clk persiods.
--
log("Testing gpio_expect where value is not first to arrive");
v_set_data := x"FF";
v_expect_data := x"00";
set_gpio(gpio_1_input, v_set_data, "Setting GPIO 1 input to 0xff");
wait for C_CLK_PERIOD;
gpio_expect(GPIO_VVCT, 1, v_expect_data, C_CLK_PERIOD*10, "Checking GPIO 1", error);
wait for C_CLK_PERIOD;
set_gpio(gpio_1_input, x"aa", "Setting GPIO 1 input to 0xaa");
set_gpio(gpio_1_input, x"ab", "Setting GPIO 1 input to 0xab");
set_gpio(gpio_1_input, x"ac", "Setting GPIO 1 input to 0xac");
set_gpio(gpio_1_input, x"00", "Setting GPIO 1 input to 0x00");
v_cmd_idx := get_last_received_cmd_idx(GPIO_VVCT, 1); -- for last get
await_completion(GPIO_VVCT, 1, v_cmd_idx, 100 ns, "Wait for gpio_expect to finish");
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(VOID);
log(ID_LOG_HDR, "SIMULATION COMPLETED");
wait;
end process p_main;
end func;
| mit |
UVVM/uvvm_vvc_framework | bitvis_vip_axilite/src/vvc_context.vhd | 1 | 1458 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_axilite;
use bitvis_vip_axilite.axilite_bfm_pkg.all;
use bitvis_vip_axilite.vvc_cmd_pkg.all;
use bitvis_vip_axilite.vvc_methods_pkg.all;
use bitvis_vip_axilite.td_vvc_framework_common_methods_pkg.all;
end context; | mit |
UVVM/uvvm_vvc_framework | bitvis_vip_spi/src/vvc_context.vhd | 1 | 1434 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_spi;
use bitvis_vip_spi.spi_bfm_pkg.all;
use bitvis_vip_spi.vvc_cmd_pkg.all;
use bitvis_vip_spi.vvc_methods_pkg.all;
use bitvis_vip_spi.td_vvc_framework_common_methods_pkg.all;
end context; | mit |
UVVM/uvvm_vvc_framework | bitvis_vip_avalon_mm/src/vvc_cmd_pkg.vhd | 3 | 7444 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
WRITE, READ, CHECK, RESET, LOCK, UNLOCK);
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 1024;
constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 64;
constant C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH : natural := 128;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
max_polls : integer;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
operation => NO_OPERATION, -- Default unless overwritten by a common operation
addr => (others => '0'),
data => (others => '0'),
byte_enable => (others => '1'), -- All bytes enabled by default
max_polls => 1,
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
--=================================================================================================
--=================================================================================================
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodDigitizerController/src/PkgTWI_Utils.vhd | 1 | 2750 | ----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: PkgTWI_Utils - Package
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Description: This package provides enumeration types for TWI (Two-Wire
-- Interface) bus status and error conditions.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
package PkgTWI_Utils is
type busState_type is (busUnknown, busBusy, busFree);
type error_type is (errArb, errNAck);
end PkgTWI_Utils;
package body PkgTWI_Utils is
end PkgTWI_Utils;
| mit |
Digilent/vivado-library | ip/rgb2dvi/src/DVI_Constants.vhd | 26 | 3151 | -------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
| mit |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign | matrix/matrix.vhd | 1 | 3107 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity matrix is
Port (
clock : in std_logic;
selector : out std_logic_vector( 2 downto 0 );
display : out std_logic_vector( 7 downto 0 )
);
end matrix;
architecture Behavioral of matrix is
--signal count:std_logic_vector( 15 downto 0 );
signal count:std_logic_vector( 6 downto 0 );
signal number:std_logic_vector( 2 downto 0 );
begin
process( clock )
begin
if clock'event and clock = '1' then
count <= count + 1;
if count = 0 then
if number = 0 then
selector <= "000";
-- display <= "11100000";
elsif number = 1 then
selector <= "001";
-- display <= "11000000";
elsif number = 2 then
selector <= "010";
-- display <= "10110111";
elsif number = 3 then
selector <= "011";
-- display <= "00110111";
elsif number = 4 then
selector <= "100";
-- display <= "00110111";
elsif number = 5 then
selector <= "101";
-- display <= "10110111";
elsif number = 6 then
selector <= "110";
-- display <= "11000000";
else
selector <= "111";
-- display <= "11100000";
end if;
number <= number + 1;
end if;
end if;
-- A
--display <=
-- "11100000" when number = 1 else
-- "11000000" when number = 2 else
-- "10110111" when number = 3 else
-- "00110111" when number = 4 else
-- "00110111" when number = 5 else
-- "10110111" when number = 6 else
-- "11000000" when number = 7 else
-- "11100000" ;
end process;
-- A
display <=
"11100000" when number = 0 else
"11000000" when number = 1 else
"10110111" when number = 2 else
"00110111" when number = 3 else
"00110111" when number = 4 else
"10110111" when number = 5 else
"11000000" when number = 6 else
"11100000" ;
-- runhorse
-- display <=
-- "11111110" when number = 0 else
-- "11111101" when number = 1 else
-- "11111011" when number = 2 else
-- "11110111" when number = 3 else
-- "11101111" when number = 4 else
-- "11011111" when number = 5 else
-- "10111111" when number = 6 else
-- "01111111" ;
-- I
-- display <=
-- "01111110" when number = 1 else
-- "01111110" when number = 2 else
-- "01111110" when number = 3 else
-- "00000000" when number = 4 else
-- "00000000" when number = 5 else
-- "01111110" when number = 6 else
-- "01111110" when number = 7 else
-- "01111110" ;
-- C
-- display <=
-- "11100111" when number = 1 else
-- "11011011" when number = 2 else
-- "10111101" when number = 3 else
-- "01111110" when number = 4 else
-- "01111110" when number = 5 else
-- "01111110" when number = 6 else
-- "10111101" when number = 7 else
-- "11011011" ;
end Behavioral;
| mit |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/vhdl/fifo_w8_d2_A.vhd | 1 | 4426 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d2_A_shiftReg;
architecture rtl of fifo_w8_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d2_A is
component fifo_w8_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d2_A_shiftReg : fifo_w8_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| mit |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enrcU.vhd | 1 | 1686 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_enrcU_DSP48_2 is
port (
a: in std_logic_vector(19 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(27 - 1 downto 0));
end entity;
architecture behav of hls_saturation_enrcU_DSP48_2 is
signal a_cvt: unsigned(19 - 1 downto 0);
signal b_cvt: unsigned(8 - 1 downto 0);
signal p_cvt: unsigned(27 - 1 downto 0);
attribute keep : string;
attribute keep of a_cvt : signal is "true";
attribute keep of b_cvt : signal is "true";
attribute keep of p_cvt : signal is "true";
begin
a_cvt <= unsigned(a);
b_cvt <= unsigned(b);
p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 27));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_enrcU is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_enrcU is
component hls_saturation_enrcU_DSP48_2 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_enrcU_DSP48_2_U : component hls_saturation_enrcU_DSP48_2
port map (
a => din0,
b => din1,
p => dout);
end architecture;
| mit |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enpcA.vhd | 1 | 2675 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_enpcA_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(29 - 1 downto 0);
b: in std_logic_vector(28 - 1 downto 0);
p: out std_logic_vector(47 - 1 downto 0));
end entity;
architecture behav of hls_saturation_enpcA_MulnS_0 is
signal tmp_product : std_logic_vector(47 - 1 downto 0);
signal a_i : std_logic_vector(29 - 1 downto 0);
signal b_i : std_logic_vector(28 - 1 downto 0);
signal p_tmp : std_logic_vector(47 - 1 downto 0);
signal a_reg0 : std_logic_vector(29 - 1 downto 0);
signal b_reg0 : std_logic_vector(28 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(47 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed('0' & b_reg0))), 47));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_enpcA is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_enpcA is
component hls_saturation_enpcA_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_enpcA_MulnS_0_U : component hls_saturation_enpcA_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| mit |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign | switch/switch.vhd | 1 | 523 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity switch is
Port (
dip : in std_logic_vector(15 downto 0);
display : out std_logic_vector(15 downto 0)
);
end switch;
architecture Behavioral of switch is
begin
display <= dip;
end Behavioral;
| mit |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign | lab1_three_leds/lab1_three_leds.vhd | 1 | 797 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--lab1_three_leds UNISIM;
--use UNISIM.VComponents.all;
entity lab1_three_leds is
Port ( dipsw1 : in std_logic_vector(7 downto 0);
dipsw2 : in std_logic_vector(7 downto 0);
dipsw3 : in std_logic_vector(7 downto 0);
led1 : out std_logic_vector(7 downto 0);
led2 : out std_logic_vector(7 downto 0);
led3 : out std_logic_vector(7 downto 0));
end lab1_three_leds;
architecture Behavioral of lab1_three_leds is
begin
led1 <= dipsw1;
led2 <= dipsw2;
led3 <= dipsw3;
end Behavioral;
| mit |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign | Interpolation_my_part/absolute.vhd | 2 | 678 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity absolute is
generic( width : integer := 8 );
Port
(
x : in std_logic_vector( width downto 0 );
y : out std_logic_vector( width downto 0)
);
end absolute;
architecture Behavioral of absolute is
begin
process( x )
begin
if x( width ) = '1' then
y <= not x + '1';
else
y <= x;
end if;
end process;
end Behavioral;
| mit |
Digilent/vivado-library | ip/rgb2dvi/src/rgb2dvi.vhd | 1 | 8777 |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 source interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure (optional), encoding and serialization logic.
-- On the input side it has 24-bit RGB video data bus, pixel clock and synchronization
-- signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb2dvi is
Generic (
kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kD0Swap : boolean := false; -- P/N Swap Options
kD1Swap : boolean := false;
kD2Swap : boolean := false;
kClkSwap : boolean := false);
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
-- Auxiliary signals
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video in
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic; --pixel-clock recovered from the DVI interface
SerialClk : in std_logic); -- 5x PixelClk
end rgb2dvi;
architecture Behavioral of rgb2dvi is
type dataOut_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type dataOutRaw_t is array (2 downto 0) of std_logic_vector(9 downto 0);
signal pDataOut : dataOut_t;
signal pDataOutRaw : dataOutRaw_t;
signal pDataOutRaw_q : dataOutRaw_t;
signal pVde, pC0, pC1 : std_logic_vector(2 downto 0);
signal aRst_int, aPixelClkLckd : std_logic;
signal PixelClkIO, SerialClkIO, aRstLck, pRstLck : std_logic;
signal pClkOut : std_logic_vector(9 downto 0);
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
-- Generate SerialClk internally?
ClockGenInternal: if kGenerateSerialClk generate
ClockGenX: entity work.ClockGen
Generic map (
kClkRange => kClkRange, -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive => kClkPrimitive) -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port map (
PixelClkIn => PixelClk,
PixelClkOut => PixelClkIO,
SerialClk => SerialClkIO,
aRst => aRst_int,
aLocked => aPixelClkLckd);
--TODO revise this
aRstLck <= not aPixelClkLckd;
end generate ClockGenInternal;
ClockGenExternal: if not kGenerateSerialClk generate
PixelClkIO <= PixelClk;
SerialClkIO <= SerialClk;
aRstLck <= aRst_int;
end generate ClockGenExternal;
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRstLck,
OutClk => PixelClk,
oRst => pRstLck);
-- Clock needs no encoding, send a pulse
ClockSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Clk_p,
sDataOut_n => TMDS_Clk_n,
--Encoded parallel data (raw)
pDataOut => pClkOut,
aRst => pRstLck);
DataEncoders: for i in 0 to 2 generate
DataEncoder: entity work.TMDS_Encoder
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
pDataOutRaw => pDataOutRaw(i),
aRst => pRstLck,
pDataOut => pDataOut(i),
pC0 => pC0(i),
pC1 => pC1(i),
pVde => pVde(i)
);
DataSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Data_p(i),
sDataOut_n => TMDS_Data_n(i),
--Encoded parallel data (raw)
pDataOut => pDataOutRaw_q(i),
aRst => pRstLck);
end generate DataEncoders;
-- Swap each bit
D0_direct: if kD0Swap = false generate
pDataOutRaw_q(0) <= pDataOutRaw(0);
end generate;
D0_reverse: if kD0Swap = true generate
pDataOutRaw_q(0) <= not pDataOutRaw(0);
end generate;
D1_direct: if kD1Swap = false generate
pDataOutRaw_q(1) <= pDataOutRaw(1);
end generate;
D1_reverse: if kD1Swap = true generate
pDataOutRaw_q(1) <= not pDataOutRaw(1);
end generate;
D2_direct: if kD2Swap = false generate
pDataOutRaw_q(2) <= pDataOutRaw(2);
end generate;
D2_reverse: if kD2Swap = true generate
pDataOutRaw_q(2) <= not pDataOutRaw(2);
end generate;
Clk_direct: if kClkSwap = false generate
pClkOut <= "1111100000";
end generate;
Clk_reverse: if kClkSwap = true generate
pClkOut <= "0000011111";
end generate;
-- DVI Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason vid_data is packed in RBG order
pDataOut(2) <= vid_pData(23 downto 16); -- red is channel 2
pDataOut(1) <= vid_pData(7 downto 0); -- green is channel 1
pDataOut(0) <= vid_pData(15 downto 8); -- blue is channel 0
pC0(2 downto 1) <= (others => '0'); -- default is low for control signals
pC1(2 downto 1) <= (others => '0'); -- default is low for control signals
pC0(0) <= vid_pHSync; -- channel 0 carries control signals too
pC1(0) <= vid_pVSync; -- channel 0 carries control signals too
pVde <= vid_pVDE & vid_pVDE & vid_pVDE; -- all of them are either active or blanking at once
end Behavioral; | mit |
Digilent/vivado-library | ip/axi_dynclk/src/axi_dynclk_S00_AXI.vhd | 1 | 19407 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
kRefClkFreqHz : natural := 100_000_000;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_dynclk_S00_AXI;
architecture arch_imp of axi_dynclk_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(kRefClkFreqHz, 32));
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
--slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"0001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
-- slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"1000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 7
-- slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when others =>
slv_reg0 <= slv_reg0;
--slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= slv_reg0;
when b"0001" =>
reg_data_out <= slv_reg1;
when b"0010" =>
reg_data_out <= slv_reg2;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= slv_reg4;
when b"0101" =>
reg_data_out <= slv_reg5;
when b"0110" =>
reg_data_out <= slv_reg6;
when b"0111" =>
reg_data_out <= slv_reg7;
when b"1000" =>
reg_data_out <= slv_reg8;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- Users to add ports here
CTRL_REG <= slv_reg0;
slv_reg1 <= STAT_REG;
CLK_O_REG <= slv_reg2;
CLK_FB_REG <= slv_reg3;
CLK_FRAC_REG <= slv_reg4;
CLK_DIV_REG <= slv_reg5;
CLK_LOCK_REG <= slv_reg6;
CLK_FLTR_REG <= slv_reg7;
-- User logic ends
end arch_imp;
| mit |
chrismasters/fpga-notes | vga_test/ipcore_dir/vga_clk/example_design/vga_clk_exdes.vhd | 1 | 5394 | -- file: vga_clk_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity vga_clk_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end vga_clk_exdes;
architecture xilinx of vga_clk_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component vga_clk is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : vga_clk
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
| mit |
chrismasters/fpga-space-invaders | project/onebyteregister.vhd | 1 | 779 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity OneByteRegister is
Port (
clk : in STD_LOGIC;
load : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0)
);
end OneByteRegister;
architecture Behavioral of OneByteRegister is
begin
loadproc:
process (clk)
begin
-- if (rising_edge(clk)) then
if (falling_edge(clk)) then
if (load = '1') then
dataOut <= dataIn;
end if;
end if;
end process loadproc;
end Behavioral;
| mit |
nussbrot/code-exchange | tpl/wb_reg_no_rst.tpl.vhd | 2 | 5995 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : %TPL_PROJECT%
-- File : %TPL_VHDLFILE%
-- Created : %TPL_DATE%
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by '%TPL_SCRIPT%' based on '%TPL_TPLFILE%'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author %TPL_USER%
--* @date %TPL_DATE%
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- %TPL_DATE% %TPL_USER%: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
%TPL_LIBRARY%
-------------------------------------------------------------------------------
ENTITY %TPL_MODULE% IS
GENERIC (
g_addr_bits : INTEGER := %TPL_WBSIZE%);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
%TPL_PORTS%
);
END ENTITY %TPL_MODULE%;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF %TPL_MODULE% IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
%TPL_PROCEDURES%
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
%TPL_CONSTANTS%
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
%TPL_REGISTERS%
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN -- PROCESS wb_ctrl
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
-- check if anyone requests access
IF (s_wb_ack = '0' AND s_wb_err = '0' AND i_wb_cyc = '1' AND i_wb_stb = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
IF (i_wb_we = '1') THEN
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
s_int_trd <= '1';
END IF;
END IF;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
%TPL_ADDR_VALIDATION%
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
%TPL_REG_DEFAULT%
-- WRITE registers
CASE to_integer(s_int_addr) IS
%TPL_REG_WR%
WHEN OTHERS => NULL;
END CASE;
-- READ-ONLY registers (override WRITE registers)
%TPL_REG_RD%
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
-- WB output data multiplexer
WITH to_integer(s_wb_addr) SELECT
s_int_data_rb <=
%TPL_REG_DATA_OUT%
(OTHERS => '0') WHEN OTHERS;
-----------------------------------------------------------------------------
-- output mappings
%TPL_PORT_REG_OUT%
END ARCHITECTURE rtl;
| mit |
thejameskyle/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
chrismasters/fpga-space-invaders | project/ipcore_dir/vram/example_design/vram_prod.vhd | 1 | 10495 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: vram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 00
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 7168
-- C_READ_DEPTH_A : 7168
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 7168
-- C_READ_DEPTH_B : 7168
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY vram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END vram_prod;
ARCHITECTURE xilinx OF vram_prod IS
COMPONENT vram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : vram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| mit |
UVVM/UVVM_All | bitvis_vip_axi/src/axi_read_data_queue_pkg.vhd | 1 | 6529 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : Package for the read data queue
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library work;
use work.vvc_cmd_pkg.all;
use work.axi_bfm_pkg.all;
package axi_read_data_queue_pkg is
type t_axi_read_data_queue is protected
impure function exists(
constant rid : in std_logic_vector
) return boolean;
impure function fetch_from_queue(
constant rid : in std_logic_vector
) return t_vvc_result;
procedure add_to_queue(
constant rid : in std_logic_vector;
constant rdata : in std_logic_vector;
constant rresp : in t_xresp;
constant ruser : in std_logic_vector
);
procedure set_scope(
constant scope : in string
);
end protected t_axi_read_data_queue;
end package axi_read_data_queue_pkg;
package body axi_read_data_queue_pkg is
package axi_read_data_generic_queue_pkg is new uvvm_util.generic_queue_pkg
generic map (t_generic_element => t_vvc_result);
use axi_read_data_generic_queue_pkg.all;
type t_axi_read_data_queue is protected body
variable v_queue : axi_read_data_generic_queue_pkg.t_generic_queue;
impure function exists(
constant rid : in std_logic_vector
) return boolean is
variable v_queue_count : natural;
variable v_read_data : t_vvc_result;
variable v_normalized_rid : std_logic_vector(v_read_data.rid'length-1 downto 0);
begin
if v_queue.is_empty(VOID) then
return false;
else
v_queue_count := v_queue.get_count(VOID);
if rid'length = 0 then
-- If the RID length is zero, all read data must arrive in order. All we need to check is that the queue is not empty
if v_queue_count > 0 then
return true;
end if;
else
v_normalized_rid := normalize_and_check(rid, v_normalized_rid, ALLOW_NARROWER, "rid", "v_normalized_rid", "Normalizing rid");
for i in 1 to v_queue_count loop
v_read_data := v_queue.peek(POSITION, i);
if v_read_data.rid = v_normalized_rid then
return true;
end if;
end loop;
end if;
return false;
end if;
end function exists;
impure function fetch_from_queue(
constant rid : in std_logic_vector
) return t_vvc_result is
variable v_queue_count : natural;
variable v_read_data : t_vvc_result;
variable v_normalized_rid : std_logic_vector(v_read_data.rid'length-1 downto 0) := (others=>'0');
begin
if exists(rid) then
if rid'length > 0 then
v_normalized_rid := normalize_and_check(rid, v_normalized_rid, ALLOW_NARROWER, "rid", "v_normalized_rid", "Normalizing rid");
end if;
v_queue_count := v_queue.get_count(VOID);
for i in 1 to v_queue_count loop
v_read_data := v_queue.peek(POSITION, i);
if rid'length = 0 or v_read_data.rid = v_normalized_rid then
v_queue.delete(POSITION, i, SINGLE);
return v_read_data;
end if;
end loop;
end if;
tb_error("Trying to fetch a non-existing element from queue");
return v_read_data;
end function fetch_from_queue;
procedure add_to_queue(
constant rid : in std_logic_vector;
constant rdata : in std_logic_vector;
constant rresp : in t_xresp;
constant ruser : in std_logic_vector
) is
variable v_read_data : t_vvc_result := C_EMPTY_VVC_RESULT;
variable v_index : integer;
begin
if not exists(rid) then
v_read_data.len := 0;
if rid'length > 0 then
v_read_data.rid := normalize_and_check(rid, v_read_data.rid, ALLOW_NARROWER, "rid", "v_read_data.rid", "Normalizing rid");
end if;
v_read_data.rdata(0) := normalize_and_check(rdata, v_read_data.rdata(0), ALLOW_NARROWER, "rdata", "v_read_data.rdata(0)", "Normalizing rdata");
v_read_data.rresp(0) := rresp;
if ruser'length > 0 then
v_read_data.ruser(0) := normalize_and_check(ruser, v_read_data.ruser(0), ALLOW_NARROWER, "ruser", "v_read_data.ruser(0)", "Normalizing ruser");
end if;
v_queue.add(v_read_data);
else
v_read_data := fetch_from_queue(rid);
v_index := v_read_data.len + 1;
v_read_data.len := v_index;
v_read_data.rdata(v_index) := normalize_and_check(rdata, v_read_data.rdata(v_index), ALLOW_NARROWER, "rdata", "v_read_data.rdata(" & to_string(v_index) & ")", "Normalizing rdata");
v_read_data.rresp(v_index) := rresp;
if ruser'length > 0 then
v_read_data.ruser(v_index) := normalize_and_check(ruser, v_read_data.ruser(v_index), ALLOW_NARROWER, "ruser", "v_read_data.ruser(" & to_string(v_index) & ")", "Normalizing ruser");
end if;
v_queue.add(v_read_data);
end if;
end procedure add_to_queue;
procedure set_scope(
constant scope : in string
) is
begin
v_queue.set_scope(scope);
end procedure set_scope;
end protected body t_axi_read_data_queue;
end package body axi_read_data_queue_pkg; | mit |
UVVM/UVVM_All | uvvm_util/src/data_stack_pkg.vhd | 1 | 8653 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.string_methods_pkg.all;
use work.data_queue_pkg.all;
package data_stack_pkg is
shared variable shared_data_stack : t_data_queue;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the stack.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the stack
--
-- - Returns: The index of the initiated stack (natural).
-- Returns 0 on error.
--
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the stack
--
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_stack_push
------------------------------------------
-- This procedure puts data into a stack with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the stack size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_stack_pop
------------------------------------------
-- This function returns the data from the stack
-- and removes the returned data from the stack.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the stack size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_flush
------------------------------------------
-- This procedure empties the stack given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be flushed.
--
procedure uvvm_stack_flush(
buffer_index : natural
);
------------------------------------------
-- uvvm_stack_peek
------------------------------------------
-- This function returns the data from the stack
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the stack size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The number of elements occupying the stack (natural).
--
--
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_stack_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the stack (natural).
--
--
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural;
end package data_stack_pkg;
package body data_stack_pkg is
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_stack.init_queue(buffer_size_in_bits, "UVVM_STACK");
end function;
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_stack.init_queue(buffer_index, buffer_size_in_bits, "UVVM_STACK");
end procedure;
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
) is
begin
shared_data_stack.push_back(buffer_index,data);
end procedure;
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.pop_back(buffer_index, entry_size_in_bits);
end function;
procedure uvvm_stack_flush(
buffer_index : natural
) is
begin
shared_data_stack.flush(buffer_index);
end procedure;
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.peek_back(buffer_index, entry_size_in_bits);
end function;
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_stack.get_count(buffer_idx);
end function;
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural is
begin
return shared_data_stack.get_queue_count_max(buffer_index);
end function;
end package body data_stack_pkg;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_rddata_cntl.vhd | 5 | 79644 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
| mit |
UVVM/UVVM_All | bitvis_vip_spec_cov/demo/advanced_usage/uart_vvc_th.vhd | 2 | 4728 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_vvc_framework;
library bitvis_vip_sbi;
library bitvis_vip_uart;
library bitvis_uart;
-- Test harness entity
entity uart_vvc_th is
end entity;
-- Test harness architecture
architecture struct of uart_vvc_th is
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- SBI VVC signals
signal cs : std_logic;
signal addr : unsigned(2 downto 0);
signal wr : std_logic;
signal rd : std_logic;
signal wdata : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(7 downto 0);
signal ready : std_logic;
-- UART VVC signals
signal uart_vvc_rx : std_logic := '1';
signal uart_vvc_tx : std_logic := '1';
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity bitvis_uart.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => cs,
addr => addr,
wr => wr,
rd => rd,
wdata => wdata,
rdata => rdata,
-- UART signals
rx_a => uart_vvc_tx,
tx => uart_vvc_rx
);
-----------------------------------------------------------------------------
-- SBI VVC
-----------------------------------------------------------------------------
i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc
generic map(
GC_ADDR_WIDTH => 3,
GC_DATA_WIDTH => 8,
GC_INSTANCE_IDX => 1
)
port map(
clk => clk,
sbi_vvc_master_if.cs => cs,
sbi_vvc_master_if.rena => rd,
sbi_vvc_master_if.wena => wr,
sbi_vvc_master_if.addr => addr,
sbi_vvc_master_if.wdata => wdata,
sbi_vvc_master_if.ready => ready,
sbi_vvc_master_if.rdata => rdata
);
-----------------------------------------------------------------------------
-- UART VVC
-----------------------------------------------------------------------------
i1_uart_vvc: entity bitvis_vip_uart.uart_vvc
generic map(
GC_INSTANCE_IDX => 1
)
port map(
uart_vvc_rx => uart_vvc_rx,
uart_vvc_tx => uart_vvc_tx
);
-- Static '1' ready signal for the SBI VVC
ready <= '1';
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD;
-----------------------------------------------------------------------------
-- Clock process
-----------------------------------------------------------------------------
p_clk: process
begin
clk <= '0', '1' after C_CLK_PERIOD / 2;
wait for C_CLK_PERIOD;
end process;
end struct; | mit |
UVVM/UVVM_All | bitvis_vip_spec_cov/src/csv_file_reader_pkg.vhd | 1 | 5967 | -- The CSV reader package was Retrieved from https://github.com/ricardo-jasinski/vhdl-csv-file-reader
-- The package has been modified for use with UVVM.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.local_adaptations_pkg.all;
-- Define operations to read formatted data from a comma-separated-values file
-- (CSV file). To use this package:
-- 1. Create a csv_file_reader: variable csv: csv_file_reader_type;
-- 2. Open a csv file: csv.initialize("c:\file.csv");
-- 3. Read one line at a time: csv.readline;
-- 4. Start reading values: my_integer := csv.read_integer;
-- 5. To read more values in the same line, call any of the read_* functions
-- 6. To move to the next line, call csv.readline() again
package csv_file_reader_pkg is
type csv_file_reader_type is protected
-- Open the CSV text file to be used for subsequent read operations
impure function initialize(file_pathname: string; csv_delimiter : character := ',') return boolean;
-- Release (close) the associated CSV file
procedure dispose;
-- Read one line from the csv file, and keep it in the cache
procedure readline;
-- Read a string from the csv file and convert it to an integer
impure function read_integer return integer;
-- Read a string from the csv file and convert it to real
impure function read_real return real;
-- Read a string from the csv file and convert it to boolean
impure function read_boolean return boolean;
-- Read a string with a numeric value from the csv file and convert it to a boolean
impure function read_integer_as_boolean return boolean;
-- Read a string from the csv file, until a separator character ',' is found
impure function read_string return string;
-- True when the end of the CSV file was reached
impure function end_of_file return boolean;
end protected;
end;
package body csv_file_reader_pkg is
type csv_file_reader_type is protected body
constant C_CSV_READER_SCOPE : string := "CSV_READER";
variable v_CSV_delimiter : character := ';';
file my_csv_file: text;
-- cache one line at a time for read operations
variable current_line: line;
-- true when end of file was reached and there are no more lines to read
variable end_of_file_reached: boolean;
-- True when the end of the CSV file was reached
impure function end_of_file return boolean is begin
return end_of_file_reached;
end;
-- Open the CSV text file to be used for subsequent read operations
impure function initialize(
file_pathname: string;
csv_delimiter : character := ','
) return boolean is
variable v_file_open_status : FILE_OPEN_STATUS;
begin
v_CSV_delimiter := csv_delimiter;
log(ID_FILE_OPEN_CLOSE, "Opening CSV file " & file_pathname);
file_open(v_file_open_status, my_csv_file, file_pathname, READ_MODE);
check_file_open_status(v_file_open_status, file_pathname);
end_of_file_reached := false;
if v_file_open_status = open_ok then
return true;
else
return false;
end if;
end;
-- Release (close) the associated CSV file
procedure dispose is begin
log(ID_FILE_OPEN_CLOSE, "Closing CSV file");
file_close(my_csv_file);
end;
-- Read one line from the csv file, and keep it in the cache
procedure readline is begin
readline(my_csv_file, current_line);
end_of_file_reached := endfile(my_csv_file);
end;
-- Skip a separator (comma character) in the current line
procedure skip_separator is
variable dummy_string: string(1 to C_CSV_FILE_MAX_LINE_LENGTH);
begin
dummy_string := read_string;
end;
-- Read a string from the csv file and convert it to integer
impure function read_integer return integer is
variable read_value: integer;
begin
read(current_line, read_value);
skip_separator;
return read_value;
end;
-- Read a string from the csv file and convert it to real
impure function read_real return real is
variable read_value: real;
begin
read(current_line, read_value);
skip_separator;
return read_value;
end;
-- Read a string from the csv file and convert it to boolean
impure function read_boolean return boolean is begin
return boolean'value(read_string);
end;
impure function read_integer_as_boolean return boolean is
begin
return (read_integer /= 0);
end;
-- Read a string from the csv file, until a delimiter is found
impure function read_string return string is
variable return_string: string(1 to C_CSV_FILE_MAX_LINE_LENGTH) := (others => NUL);
variable read_char: character;
variable read_ok: boolean := true;
variable index: integer := 1;
begin
read(current_line, read_char, read_ok);
while read_ok loop
if read_char = v_CSV_delimiter then
return return_string;
else
return_string(index) := read_char;
index := index + 1;
end if;
read(current_line, read_char, read_ok);
end loop;
return return_string;
end;
end protected body;
end;
| mit |
UVVM/UVVM_All | bitvis_vip_avalon_st/src/local_adaptations_pkg.vhd | 1 | 2182 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package local_adaptations_pkg is
-------------------------------------------------------------------------------
-- Constants for this VIP
-------------------------------------------------------------------------------
-- This constant can be smaller than C_MAX_VVC_INSTANCE_NUM but not bigger.
constant C_AVALON_ST_MAX_VVC_INSTANCE_NUM : natural := C_MAX_VVC_INSTANCE_NUM;
constant C_AVALON_ST_CHANNEL_MAX_LENGTH : natural := 8;
constant C_AVALON_ST_WORD_MAX_LENGTH : natural := 512;
constant C_AVALON_ST_DATA_MAX_WORDS : natural := 1024;
end package local_adaptations_pkg;
package body local_adaptations_pkg is
end package body local_adaptations_pkg; | mit |
UVVM/UVVM_All | bitvis_vip_avalon_st/src/avalon_st_vvc.vhd | 1 | 23617 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.C_SB_CONFIG_DEFAULT;
use work.avalon_st_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.transaction_pkg.all;
--================================================================================================================================
entity avalon_st_vvc is
generic (
-- When true: This VVC is an Avalon-Stream master. Data is output from BFM.
-- When false: This VVC is an Avalon-Stream slave. Data is input to BFM.
GC_VVC_IS_MASTER : boolean;
GC_CHANNEL_WIDTH : integer := 1;
GC_DATA_WIDTH : integer;
GC_DATA_ERROR_WIDTH : integer := 1;
GC_EMPTY_WIDTH : integer := 1;
GC_INSTANCE_IDX : natural;
GC_AVALON_ST_BFM_CONFIG : t_avalon_st_bfm_config := C_AVALON_ST_BFM_CONFIG_DEFAULT;
-- Common VVC fields
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
avalon_st_vvc_if : inout t_avalon_st_if := init_avalon_st_if_signals(GC_VVC_IS_MASTER, GC_CHANNEL_WIDTH, GC_DATA_WIDTH, GC_DATA_ERROR_WIDTH, GC_EMPTY_WIDTH)
);
end entity avalon_st_vvc;
--================================================================================================================================
--================================================================================================================================
architecture behave of avalon_st_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated executor
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_avalon_st_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_avalon_st_vvc_status(GC_INSTANCE_IDX);
-- Transaction info
alias vvc_transaction_info_trigger : std_logic is global_avalon_st_vvc_transaction_trigger(GC_INSTANCE_IDX);
alias vvc_transaction_info : t_transaction_group is shared_avalon_st_vvc_transaction_info(GC_INSTANCE_IDX);
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
--UVVM: temporary fix for HVVC, remove function below in v3.0
function get_msg_id_panel(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config
) return t_msg_id_panel is
begin
-- If the parent_msg_id_panel is set then use it,
-- otherwise use the VVCs msg_id_panel from its config.
if command.msg(1 to 5) = "HVVC:" then
return vvc_config.parent_msg_id_panel;
else
return vvc_config.msg_id_panel;
end if;
end function;
begin
--==========================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--==========================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AVALON_ST_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--==========================================================================================
--==========================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--==========================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
variable v_temp_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc( name => C_VVC_NAME,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- Update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the executor if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
--UVVM: temporary fix for HVVC, remove two lines below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
v_temp_msg_id_panel := vvc_config.msg_id_panel;
vvc_config.msg_id_panel := v_msg_id_panel;
end if;
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
-- Await completion of all commands in the cmd_executor executor
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd, executor_is_busy);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
--UVVM: temporary fix for HVVC, remove line below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
vvc_config.msg_id_panel := v_temp_msg_id_panel;
end if;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--==========================================================================================
--==========================================================================================
-- Command executor
-- - Fetch and execute the commands
--==========================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_result : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_data_array_ptr : t_slv_array_ptr;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = TRANSMIT or v_cmd.operation = RECEIVE or v_cmd.operation = EXPECT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when TRANSMIT =>
if GC_VVC_IS_MASTER then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
v_data_array_ptr := new t_slv_array(0 to v_cmd.data_array_length-1)(v_cmd.data_array_word_size-1 downto 0);
for i in 0 to v_cmd.data_array_length-1 loop
v_data_array_ptr(i) := v_cmd.data_array(i)(v_cmd.data_array_word_size-1 downto 0);
end loop;
avalon_st_transmit(channel_value => v_cmd.channel_value(GC_CHANNEL_WIDTH-1 downto 0),
data_array => v_data_array_ptr.all,
msg => format_msg(v_cmd),
clk => clk,
avalon_st_if => avalon_st_vvc_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
deallocate(v_data_array_ptr);
else
alert(TB_ERROR, "Sanity check: Method call only makes sense for master (source) VVC", C_SCOPE);
end if;
when RECEIVE =>
if not GC_VVC_IS_MASTER then
-- Set vvc_transaction_info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
v_data_array_ptr := new t_slv_array(0 to v_cmd.data_array_length-1)(v_cmd.data_array_word_size-1 downto 0);
avalon_st_receive(channel_value => v_result.channel_value(GC_CHANNEL_WIDTH-1 downto 0),
data_array => v_data_array_ptr.all,
msg => format_msg(v_cmd),
clk => clk,
avalon_st_if => avalon_st_vvc_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
for i in 0 to v_cmd.data_array_length-1 loop
v_result.data_array(i)(v_cmd.data_array_word_size-1 downto 0) := v_data_array_ptr(i);
end loop;
v_result.data_array_length := v_cmd.data_array_length;
v_result.data_array_word_size := v_cmd.data_array_word_size;
deallocate(v_data_array_ptr);
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
alert(tb_warning, "Scoreboard type for Avalon-Stream RECEIVE data not implemented");
else
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result);
end if;
else
alert(TB_ERROR, "Sanity check: Method call only makes sense for slave (sink) VVC", C_SCOPE);
end if;
when EXPECT =>
if not GC_VVC_IS_MASTER then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
v_data_array_ptr := new t_slv_array(0 to v_cmd.data_array_length-1)(v_cmd.data_array_word_size-1 downto 0);
for i in 0 to v_cmd.data_array_length-1 loop
v_data_array_ptr(i) := v_cmd.data_array(i)(v_cmd.data_array_word_size-1 downto 0);
end loop;
avalon_st_expect(channel_exp => v_cmd.channel_value(GC_CHANNEL_WIDTH-1 downto 0),
data_exp => v_data_array_ptr.all,
msg => format_msg(v_cmd),
clk => clk,
avalon_st_if => avalon_st_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
deallocate(v_data_array_ptr);
else
alert(TB_ERROR, "Sanity check: Method call only makes sense for slave (sink) VVC", C_SCOPE);
end if;
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
check_value(vvc_config.bfm_config.clock_period > -1 ns, TB_ERROR, "Check that clock_period is configured when using insert_delay().",
C_SCOPE, ID_NEVER, v_msg_id_panel);
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Set VVC Transaction Info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--==========================================================================================
--==========================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--==========================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--==========================================================================================
end behave; | mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/mult_gen_v12_0/b78716ad/hdl/mult_gen_v12_0.vhd | 2 | 9504 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
UyXQwkUObVrGCrQeWBRDzNzHSmxz0+tXmCDiikEzuwG7p+MOvi5now6c6XhFQHhRDLZqrTCJWGVY
uVMi7GoGag==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
i5kFZPoOW4AbrHICVt04gLioHJ/lXQCVR+36ZomPa7Uhk2VGKJwiH+6I59ia5ib443IW5VCbmy/r
gnO5lAmOjOXrf+28RyOfxhyCRgHKh6mRiH0tlgZUxbFCb24jFd8F2ON6eZARrIbx4Vu5v/7L6X5o
oTd41gw6CHpypaHAd88=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
d4UDVzST4F/GIUQK7Q/mgyckJ8hrUJmJYmR7IrVlH2X6hv2uAAk4gpmfB6E2dVAnuOOE4STY1OeO
4QqPqvp/zC7S/aYld/u+eRjgH778AqwHmdMBU3BX1e3j2lWzDCoDQianx13lD0Ihcvv2hpUg3My9
R2dUGaAs/YrnckB0Xsyif1gPs12BFskCvSBa0HZidrW6UXqeUc5Y+Y18oAX2L10OimzYS3Jo+han
FbcTbpApf4PkFyRzckA+yzqct0XOkXLsuWu6dE34gxuaUw9BCMtj5rnbQ0G0Xote0ldMp+AIN/vj
bJafuR2HkqxTvqwCTed3PqEy4xVdmr/ecywIlw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ZzJe3CosxBQtdtXIXPjUB1PIjPHRzRe+TcPVuazVXoOV6QQ4DY8D8TRP6/DZEeIUzxe5gMRXz2yf
RclEq20zSfPMaB3h6L9uECxIUPiPZJ03aglicg+QjHFDLo1XgOo1ItxSaGSam80SUko6TFrRjWV7
DlVH8SFB0gTLxJpXLeU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k0pB4lrRLLpdtNnVRXv7qxU15dyKF9BuJVYUlIA955FRzEtgaMMCmzDybCNTUJh5QGLsvLYdRVSK
VcBOlgtImwe2FJEsDE/buKE8+W7HPOSiP0Elo4jDRWfwpueOq6VQ4zL5XMAGi+70gMxxGQr7Z5E8
4lvDxjOzkqAIn3EC1esPBOdcmzCt1V55YsxrHdN/eAnUWBvEPaGJfoZKGT4IZ1fx0hJCdrrnel+V
0HuJqYSPOCB8SJpuoB2p3Y1d93yF5xcy8wSWeVWgM3E2z++VHQIjT4DTFlyqNFbe2YxMhMTY8SGk
pV+7oyzvQjUyYpAt0GiJuzwTVRTBCgpo3qFmbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5296)
`protect data_block
TRMXPryOktDPwy6BDRqg5kA3yJNP8nK0yjhXjcR0H50W+GUpPKFWSJCecweKlBp3IC6rhy63O7G5
M3/NOT6ayNqfyYHioCW+FNW3IubPJYUPxfLZnDkN3O8lEic8eSjoUY66kO0BhedKKbJcgwXqRRFa
/iImeCT7caqjZZQUgGMG9CfExaSRDuNKg/yaMzmuXDgPljIr+fUkAU4ZWtRLJZs+7ZuOCBObPeBg
ihd8P8V4Qkjn4HxsdhhEXvrUiH9JY4KOIGeaYHrXHWiDOyWDyO+QVYzvQG/U0dQaQjuFElafgnyc
2fUFrB+EmWiz9D/ESFHBxoMOLXkAAyPkNWbx4OheNFGR32nfcGPCiT0sgoXPAbKkNMtLQb4izlbD
rjS5ZA17FqpcgPP5tqdZTuq4r/s1tOd3lENPyK4GtVtijB9d6i8nLiOUZGhlKfbjrNML7BmD5SXI
5hm3iCmmlduEdtsxUaA+y3zzC/i+Q/7u9N1emNbaXGldWWTshBmGP06NJKtUmJBepQ2IjItHFTll
EY4VoW1LJ+mv7Zhs7VC8AiJibQGqE+JQfkb397XN0SV6X/0P5F2CdXxw12nwQ3tDFJzo17xnXRCl
JboVcqTWG3v/8Td7lrpGaKM3h1+pWpI8141liIvnb1L9yTYRLDri4L19wwk/EeORXYxbYyzA/PSD
QScvZeSqSUAscvyN0voB3o1/BWextXL5Ce39FtdC0x6Dl5B5CA9pbV5NtTA6PYMPrGKKFBhMWWKy
6YFpeJ3BjedPsKMnmvYIS2eZAy6U2IRMsfiv37Z8urps6Q+srxYQyetD2+kgq72cjKKt7P393ZfM
LVEbK5+n7oVkGBN83c1SQSSM8AwrTyGTNpcf07pgjrop/gtpJ7hIqdn8Wwqqd+KcFXIHkt/5xFvt
CyNfOQTJn1R0akoEPeeQPDssHuNySF4db2ni949o8DURfEeJCO0jLiWH8LV18i2EYXUCoKL2NPPN
swDlhDivqyLhq+vlTqKHfKssJG4U2/Ni4NYHj+R4IrMYTocSiXVMVs8Et/xrzKjUwhKdULkgn6ge
eD6eF9YdTJRE5bPPNqK5JtywybTjO8wzJBnruPZKimhbTMZPlEP0dNOkGUDEWpsI4Q6JAEHnwdlf
ztjnxyyCBltiDCGKTbzkdxQtVxP9u2U0Q3OXSWS1q9GoFOZ37M35iT5Rk9CMVe58Zf/cAOwX/3Y6
rEmO+OCoARv46YuMy2ktQ43jimjBHp/5qeN8RFBA1W44K8lY1W8JA33MJsmkHiD32ghCdNkv5gfk
uVlwJhEbgKatpybCYVy7WDGvGfqsto0dSeG60BOE3DSOmzC4sRuNkrAEujRepUHVWx3OZkZiIzCq
J090cUaFdeGuIYi2JTo3p5l15wTl55hCmxr73PleTw7JchhFyah+yCs+LqgXauvKr6XBtNdY5jLP
NI8TRS63vOBCMdhaSgy5Vm4CScpNQKqbHYQ4802T1ZgdiZ9LcMplt0JSYwdefjRRtYVpZZbzueUP
QYATuyIQ7URQiimlWlE+gq9/uHplMmmM4pWhUlhoN/B3Na9R0X1MSj7ZoSjW3KZZ7aeerKEjqEPd
89d9km4TpBqpxiec3mt+6MZpmoeoXQJDb6+mUQwGsnF0RdU6aiJXY0coE1vkGfoPnFBdlgU+c3Bn
wvEfT3CRWoSo4qA8rKT6gE0jWOF3mpthT0MXg8hgyyKm+5sYH6C2sTGWY9dB5kO5FQeE57Q+3QdN
8jGo9JzVPWQ8t6ZimCOjpuyNlhJM8hFbzRz54qBcX6fC29vlWilbUvLl1CPeYQPshUmcJfTLklC+
bCtYRHYvk3qIPAzOOVt0byp1/06cq9KEorXbupLukk9BbXMNtKH/e+2NeuRcxJD236ht//qkXLFF
AEv+33L+zyPgZHBLs4wKv+tgpH9wpgazEKjpJDbV9/GZ3PS+es5Pv1OKXZV05SjeLkk+kpYKgspU
mxmMcC97b1kgsq5BiP1rm9jubJzloCxDq86Ycdp4oHa2oUf6CUkNZurCHBCRQCy58uN4mbIKIppD
QfV2noqEzGrgUr7+4DpYITMV7N6qwn17BxTYfDifmTYq+yClz33aL/3VxMpOt8LBqfC8NOafCT2z
QxhoIGo6Ob0CUzE1V0olhiiPUK5s02a9/830v8buG1cs8PZhRTjTjx+IX9SHfsRmy+hTXSf6zWfQ
/QyxjTrka5fWcmRIaLBDZcDBOqaXI1Egjr3K0fU8EYgaorU0P/r01t/Qm1WYTIFyJHufYN8DqrNZ
ehE7ClavK+DgbL11aGeTEeiMnOHEEMwaIZvmPewBGaMviWtgMSaZ9RR8TfrLaMqjmA10YEh8r4DL
rO25Fbt+kwq+6FnB2YfCblOjANrvRt82TCsSFG302yLq5puwX2lPyH/K61RoLiOvHVYT+sU98rXw
d530yc0x/yi9hP7b5dynn3Q9gv445J0n6Wr4OGvv++VZ4lPsQ+0ulJAlAGwBc5PrQ7p7r0K8YY6v
tA8GLwF7p0/TuhRzxtOZTZMvxriGgKBpjC0N+VIwp9GrRYm/4qiOHD/tFoCZViEuzTrsuchjfPZ4
J4EXPXVEPf59TlAK4/xXouIY7RZPfbmk/Fbl3U6fHZ2ZpCvNdGWcVfMlhf4ytt1F9yLHAhedCHW/
MEZ5tXAh/WP6v5lHml9v3HHKoHidEbvSHkU0D2KNMgZGji9VMs98WKAmaRcfxrK53aSooOhcG3iF
9C7yMnkpTylwPfBWXIAPxSy4NLRFqaagzcA/OcfRqbyWiXr2EiSb8kDvXfIKS2sRZj0SNLU5YWRm
F0Wd7NvlXXhxLunJtJ0N9RUQ0bmgMcktwNCuShkqUmNkd7vXe2Vhto7RzJrbyL3tbeDVRXmgkIHi
GyiMa4+AxdUOdCdjz8EK5qHXyVQRuPyEGlH4iMXNvywwfRp7IHW2LDzg7VDXCgsL15JKPQQwvcUT
74kPEnl2bboUHl6iO4ZdfUHDMC6DTkcHrOjEqS0CWG3FZV9emO5Iuy/jNqorEWv4jVQCSSQu6xzp
kBXm3wrG4R3PPhi5lt3SJp0Q9c6OCe9Jz2oX3qAz/tgbM8D/n+Wk/7OZ3wBJuwEElGxhOLG8AZnA
hI0rtFEWX7e0FnxXis80WK/YyGQpSWfITsGBBEOUfJC+9Q0L+Jd7Bo0BPTI6cw5277KV6EYsXLNW
34v++iFA2QGCurslNh7aZWNUb25r5s2BaayHJ37AhAyj5wjHjX7k99+uO8a13L8zhrszZBGsiKFz
PxjkBUM4nH3eTRH6TlnK7/Rq+9Q1nVTE37gjF4P6WpyBFhCOKbm3W4D42EVIbYFJ1YOUD1HoEpVu
nMxtLvIujl4+zPgDUuyiouEFzNtDaOHp8GOtddNN18Bh3+oVPnpaIZqP5cAKDGxetLhrccLEqFl4
03N9VG/7pGThwLp6bjrJwrlBfg+m2eNgpBm7eyi4KB2aQOa8CbDs70IJ2bj/h24zBHLLL8gtPk1x
dpG3fPcsaEHmEajELrpyrto7mSC2Wys7LhQfKvKc0x+u0ygDsMwvs6US6Su0K/hhrOCYSCLoA0ON
sX3BYLFq5pomYF3lXXJvZD9Qozgi1K24M8ccvGdLYjdOHoeBHuAbUH5zufzLbdVisLTv+EvfJLqC
cZwgNNbV+Hl6qxN7WGqu8iwqe2Q+I+0ZfjQo3p/CzVarzxv+QRIofyXFpdKIo+NhtaDR7UKZLMyU
UcTjd2Sg/I8b9uURhrSW0Oq806jjket9u5lESyYCGJ9OiAG3AgasY49AoMQjQlrFkYO7/utVDEJg
a7O22t40+yoK0cgrsUhz5F6wNVZTCcBV07MiitAt/VjimtZhK6XVh0Jjqwg0g8LY+DL+1SGGi8hb
L4OCaR5GPKWeMfj+mag7OdnOxxHGsknw4gc+9Zngtwuhpa32zy2tcps73L16S7lEUgB910c12Shq
EL2dWDXLvd7JQNx2kjDVJtXiAxLZUDwn8EnuS4wdgv1Efk2udmwv0JydDtpaMi95FsyCseAEsgB5
XFq80DIHGLBWw8S+ZD8FQ91X78l0PmJM5y3NkscUqNASjamXkSFw03XlQl3eUz3vKe/GrzXmUphK
H6quEZeSimY4wQPGWdTlQJWQIsNvLPY522fb01HVuhR2UM91x22X6Tmvr0FH+ScW6mwWGsU3xR4G
0E8pJt0I1NvR83rqnG7EgYJgVukUzVnrQh6tbh1xvTHqZNKmX7SB7UdKk+s9qBel6hFat/kNBGeT
2QH91rMWGsb3ylJxOSig5mSRQxWtAU/gj7DThhA13iMqqiueIKOc7J8QDl7Fzvd8Z4IFZAb4uIac
L0stP4qBn2FU6yBM/T1VbuSoAXiOejLhN2C+F+fATxLfPyzu5RoXBWm791G48aOg3/WcLwe60hp8
LQAYxXZT80kv58Bnua4rUkL8RFv3VX4hg0CPbVuO94wGsJhld6wh65DlszuOnoxAvDIMTOL5len0
qo71FtinCbCPsTBI8CHFsaWmfxsaEnpgdoP7MtIomSSz471RlSxozqu1DoykurAcaZgJl/xLwbLI
fhxefawGufjLvYPK8BDXE/X5J4XxS9Cq56AZeYXuy7DTcaEToPpRNw045EcgeC/Rc+hPq/FftI0r
of9+7YKiKluxTRGWkGvqMKVWmMn59C1ebqj0RgSSlnYtxwPouMmpgYcD5ZaX1hvOnZ1pKUDAg1EJ
nR4z5vJCCoI2zKSS9aO39l0ihxvdVKtvfXAfnNieVnLMOFrGKvIsu/+Qf9na9AbJ9tWy3mLohqWO
xswSzO54pM4RxM/01CohYutXVloTWvQYwPPIMGClc33HI5wDnYHkrRJBOKk3vswKTcE5oW26jn0P
sypruFxK/KBcc0Hig0jfuw17FW/XWHRl/Wg+sBKkjMdxYL3fQtpI1izqP4S+89FBARh3hwi5/1HA
BXDAZ1YVyyqaM60p14RCW9+EPoZAPbTeqF+Ht1iN2A7nMQSc64hVhAXfgUeWwXkAd7yM+Geuf4rk
AhKpKRVdSr6TQEKOULI8NLVIlyjAl2YXYM9I7WyFftqfJfEZ7KJgy0AL7iK5LYXOWZ8vFDw6kf3N
hI6cA8SRs8WJbSqGvyshHioDHYvwmRfN9TdM7egrG7DcdfMVaaWWNhX0gWCu2YboSxQb0OIoCO4H
2+O1L48uIYaWuKykTMaGrIQR/dfv09MyqqWzn/4B6EIRQq7W+9ZhRj0ATmYBZ/H9dLTl33iCKwFz
JCBVC1A3MraW+7FUdfAEO2Iboh3nEF4N3DfQLPO+tbO6z5j3dDlgYhLito6VdkScPrYoG4T0v5VN
om+xPOF49Vy5A6mK8Z9N+8k1Smandx7w+mNXahi3/ltCItXCvXecJktD/rrA7vZIXqFKqWQ116/Y
fFt7daoH1oFwgDZTuQve91S6K837X3cDL25Aoq8kMU8iUx7KC+Yeyos8GpnE7hnZphJ+weE4E+Nu
sQtXGeM2L1CycvLfZ9LzsUtG95irE6j2p0P+dpFBNIhTUghMpyndSu6yhQWTMHTYTSdNj4kv3387
/KqbL7XcXhgoPObm79X8bTjJ2wQtV364FnSfqXhDXtuUjxOhycGjX3Uc4h5zHdpNRI1AU78DFccM
SA4K+CuP21QH92JC/GlR3h7gO7wHNLqoVyY/YkUqRHXpL9AOmMr7uwsKgFGg3+jIL7aMLuwuYFLN
mze0fUGZ/jFNtHJmofm/54Cu8KIUigrQPuBR7co2iSSAAh8VJ2+3qp961tV88MZCk8qu/0ETbU0W
O3zhtY6PHlW4hOdCgKy4BJG+cWgVnEP2vV5I5TVKGANgocRz8FKy6OgOYIJc1n0fhqvv1jkite0k
DdSdooUEFX1owK8MTEbfcxzMt3Nx/bWiOg8a6v/kOLjiJ53Pfa7M83r0wFvaZeiQZDtfeWKA1Ivk
xDywRyT2vH3/VYCz7gfiycqjfzvPfClz43voSCCnlEaaGMUoyEogvUlJTtCITF/MHFKXT3gQjuUB
bK5VgZxLh3h1WI0+pMMXXwZozWSK+8fifEXzfL6UuGvG5xRGJaVQ9JEJaBLejk87LaGu9fFv+3SH
XYFKfP6yp3MUzfwkVWd6Pl/D/P/o5EDcfpy2/oWgu1oMlW7vZfT+2oivHzGqgb783OMtlTThUnuj
b1IslRxIYs0scQBNf6ZvqT7iqECJi9w4qdYGuA4e3iXJt4osTTpRgJ/MwmF438A3Ld/YSYsKZCFQ
TvgoS2gj5RwZr44Tr3TW5Ndc+rdZFpPlqtk+XkeqKJ47M5kkdMsiHG5OP9J2EBvAXIeTpjo6mj++
CkLOzt4026KoCteZ8NBxJ1oA+CxavdFbup8dbPq+qX+8A21ZoIkttoeQrEzBOmtGkZEnu368yB9p
7LPV/DJeBnsCJuBIUseZAGHviUbFG7MVBQvOgX20Lvr5FnA4NdsKFGl9x8X0/aH7FARtI6tYDi67
OuZ2Npa1kl4TPlHqj75LLv+d8nLhunPYWuMxGcDs8vELPG4oxbn71LymJ3TC8aSfIkUupJzq2wHD
CYYOggBpoNMcwggle0JJ8sCP4MjO4uR6hm4ScDbrFr2Qq6OrodHLT/jsZeUYNV+yeMc+zu2kLLfT
4HHuTMj6ZLcWCCtuDR6SzBy6OWgQuW/RM3qg0ie/zlWdP0S9D2/03vpluXFloPobKyg6mvI0UaFI
4/ew4IWErq/uF+AReid7sMnR3wJwyhwxZXEVTQ4HFtr8b2lVo2Ozu4ydeecidnZk7pyjlN6eg1bh
E7RQ/hNFE6wez8d1t2GO3vGIJpIbPHRB1P5eV1jSncGm1/RMtR/qb8uAAqeyWQOuELmSv1/+ST2a
6TFe0/1G0RIJx1sMqOf0E3Qlt/XsQS75/6Va6kaYiQpqZxvOo5PScxMwc0pvGFcw1nQeXHY+MQWy
fwmcqwatq8Eg6A0FAdkCrMFUo80ENd+VWcfdgonyBwinH5cWPUu/s/Ro+2gzSsQItr5VMl25dX8K
i4Z4uh6EjiKtot9Z/Y8lYi1ntfLv2vYbvqsryOg2DL+KDwlYzVs+AUz2k/T+XksOFrE2Zw==
`protect end_protected
| mit |
UVVM/UVVM_All | bitvis_vip_axistream/src/axistream_bfm_pkg.vhd | 1 | 129623 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis VIP AXISTREAM Library : axistream_bfm_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s).
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--========================================================================================================================
--========================================================================================================================
package axistream_bfm_pkg is
--========================================================================================================================
-- Types and constants for AXISTREAM_BFM
--========================================================================================================================
constant C_SCOPE : string := "AXISTREAM_BFM";
--========================================================================================================================
-- C_MAX_*_BITS : Maximum number of bits per data word supported by the BFM.
-- These constant can be increased as needed.
constant C_MAX_TUSER_BITS : positive := 8;
constant C_MAX_TSTRB_BITS : positive := 32; -- Must be large enough for number of data bytes per transfer, C_MAX_TSTRB_BITS >= tdata/8
constant C_MAX_TID_BITS : positive := 8; -- Recommended maximum in protocol specification (ARM IHI0051A)
constant C_MAX_TDEST_BITS : positive := 4; -- Recommended maximum in protocol specification (ARM IHI0051A)
constant C_RANDOM : integer := -1;
constant C_MULTIPLE_RANDOM : integer := -2;
type t_user_array is array(natural range <>) of std_logic_vector(C_MAX_TUSER_BITS-1 downto 0);
type t_strb_array is array(natural range <>) of std_logic_vector(C_MAX_TSTRB_BITS-1 downto 0);
type t_id_array is array(natural range <>) of std_logic_vector(C_MAX_TID_BITS-1 downto 0);
type t_dest_array is array(natural range <>) of std_logic_vector(C_MAX_TDEST_BITS-1 downto 0);
--========================================================================================================================
-- Interface record for BFM signals
type t_axistream_if is record
tdata : std_logic_vector; -- Data. Width is constrained when the procedure is called
tkeep : std_logic_vector; -- One valid-bit per data byte
tuser : std_logic_vector; -- User sideband data
tvalid : std_logic; -- Data valid
tlast : std_logic; -- Active high during last data word in packet.
tready : std_logic; -- Backpressure
tstrb : std_logic_vector; -- Treated as sideband data by BFM: tstrb does not affect tdata
tid : std_logic_vector; -- Treated as sideband data by BFM
tdest : std_logic_vector; -- Treated as sideband data by BFM
end record;
-- Configuration record to be assigned in the test harness.
type t_axistream_bfm_config is record
-- Common
max_wait_cycles : integer; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready or valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
bfm_sync : t_bfm_sync; -- Synchronisation of the BFM procedures, i.e. using clock signals, using setup_time and hold_time.
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
byte_endianness : t_byte_endianness; -- Byte ordering from left (big-endian) or right (little-endian)
-- config for axistream_transmit()
valid_low_at_word_num : integer; -- Word index where the Source BFM shall deassert valid
valid_low_multiple_random_prob : real range 0.0 to 1.0; -- Probability of how often valid shall be deasserted when using C_MULTIPLE_RANDOM
valid_low_duration : integer; -- Number of clock cycles to deassert valid
valid_low_max_random_duration : integer; -- Maximum number of clock cycles to deassert valid when using C_RANDOM
-- config for axistream_receive()
check_packet_length : boolean; -- When true, receive() will check that last is set at data_array'high
protocol_error_severity : t_alert_level; -- severity if protocol errors are detected by axistream_receive()
ready_low_at_word_num : integer; -- Word index where the Sink BFM shall deassert ready
ready_low_multiple_random_prob : real range 0.0 to 1.0; -- Probability of how often ready shall be deasserted when using C_MULTIPLE_RANDOM
ready_low_duration : integer; -- Number of clock cycles to deassert ready
ready_low_max_random_duration : integer; -- Maximum number of clock cycles to deassert ready when using C_RANDOM
ready_default_value : std_logic; -- Which value the BFM shall set ready to between accesses.
-- Common
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the BFM
end record;
-- Define the default value for the BFM config
constant C_AXISTREAM_BFM_CONFIG_DEFAULT : t_axistream_bfm_config := (
max_wait_cycles => 100,
max_wait_cycles_severity => ERROR,
clock_period => -1 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => -1 ns,
hold_time => -1 ns,
bfm_sync => SYNC_ON_CLOCK_ONLY,
match_strictness => MATCH_EXACT,
byte_endianness => LOWER_BYTE_LEFT,
valid_low_at_word_num => 0,
valid_low_multiple_random_prob => 0.5,
valid_low_duration => 0,
valid_low_max_random_duration => 5,
check_packet_length => false,
protocol_error_severity => ERROR,
ready_low_at_word_num => 0,
ready_low_multiple_random_prob => 0.5,
ready_low_duration => 0,
ready_low_max_random_duration => 5,
ready_default_value => '0',
id_for_bfm => ID_BFM
);
--========================================================================================================================
-- BFM procedures
--========================================================================================================================
-- - This function returns an AXI Stream interface with initialized signals.
-- - All input signals are initialized to 0
-- - All output signals are initialized to Z
function init_axistream_if_signals(
is_master : boolean; -- When true, this BFM drives data signals
data_width : natural;
user_width : natural;
id_width : natural;
dest_width : natural;
config : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) return t_axistream_if;
--------------------------------------------------------
--
-- AXIStream Transmit
--
--------------------------------------------------------
--
-- Source: BFM
-- Sink: DUT
--¨
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
--------------------------------------------------------
--
-- AXIStream Receive
--
--------------------------------------------------------
--
-- Source: DUT
-- Sink: BFM
--
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
-- Overloaded version without records
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
--------------------------------------------------------
--
-- AXIStream Expect
--
--------------------------------------------------------
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overloaded version without records
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default strb_array, id_array, dest_array
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
end package axistream_bfm_pkg;
--========================================================================================================================
--========================================================================================================================
package body axistream_bfm_pkg is
function init_axistream_if_signals(
is_master : boolean; -- When true, this BFM drives data signals
data_width : natural;
user_width : natural;
id_width : natural;
dest_width : natural;
config : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) return t_axistream_if is
variable init_if : t_axistream_if(tdata(data_width-1 downto 0),
tkeep(data_width/8-1 downto 0),
tuser(user_width-1 downto 0),
tstrb(data_width/8-1 downto 0),
tid (id_width-1 downto 0),
tdest(dest_width-1 downto 0)
);
begin
if is_master then
-- from slave to master
init_if.tready := 'Z';
-- from master to slave
init_if.tvalid := '0';
init_if.tdata := (init_if.tdata'range => '0');
init_if.tkeep := (init_if.tkeep'range => '0');
init_if.tuser := (init_if.tuser'range => '0');
init_if.tstrb := (init_if.tstrb'range => '0');
init_if.tid := (init_if.tid'range => '0');
init_if.tdest := (init_if.tdest'range => '0');
init_if.tlast := '0';
else
-- from slave to master
init_if.tready := config.ready_default_value;
--init_if.tready := '0';
-- from master to slave
init_if.tvalid := 'Z';
init_if.tdata := (init_if.tdata'range => 'Z');
init_if.tkeep := (init_if.tkeep'range => 'Z');
init_if.tuser := (init_if.tuser'range => 'Z');
init_if.tstrb := (init_if.tstrb'range => 'Z');
init_if.tid := (init_if.tid'range => 'Z');
init_if.tdest := (init_if.tdest'range => 'Z');
init_if.tlast := 'Z';
end if;
return init_if;
end function;
--------------------------------------------------------
--
-- AXIStream Transmit
--
--------------------------------------------------------
-- Send a packet on the AXI interface.
-- Packet length and data is defined by data_array
-- tuser is set based on user_array,
-- tstrb is set based on strb_array, etc
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axistream_transmit";
constant proc_call : string := "axistream_transmit(" & to_string(data_array'length) & "B)";
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
-- Helper variables
variable v_byte_in_word : integer range 0 to c_num_bytes_per_word-1 := 0; -- current byte within the data word
variable v_clk_cycles_waited : natural := 0;
variable v_wait_for_next_transfer_cycle : boolean; -- When set, the BFM shall wait for at least one clock cycle, until tready='1' before continuing
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_valid_low_duration : natural := 0;
variable v_valid_low_cycle_count : natural := 0;
variable v_timeout : boolean := false;
variable v_tready : std_logic; -- Sampled tready for the current clock cycle
begin
-- DEPRECATE: data_array as t_byte_array will be removed in next major release
deprecate(proc_name, "data_array as t_byte_array has been deprecated. Use data_array as t_slv_array.");
check_value(axistream_if.tdata'length >= 8, TB_ERROR, "Sanity check: Check that tdata is at least one byte wide. Narrower tdata is not supported.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tdata'length mod 8 = 0, TB_ERROR, "Sanity check: Check that tdata is an integer number of bytes wide.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tuser'length <= C_MAX_TUSER_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TUSER_BITS is high enough for axistream_if.tuser.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tid'length <= C_MAX_TID_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TID_BITS is high enough for axistream_if.tid.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tdest'length <= C_MAX_TDEST_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TDEST_BITS is high enough for axistream_if.tdest.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tkeep'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tkeep equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tstrb'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tstrb equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(data_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for byte order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(user_array'ascending, TB_ERROR, "Sanity check: Check that user_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(strb_array'ascending, TB_ERROR, "Sanity check: Check that strb_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(id_array'ascending, TB_ERROR, "Sanity check: Check that id_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(dest_array'ascending, TB_ERROR, "Sanity check: Check that dest_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
end if;
axistream_if <= init_axistream_if_signals(is_master => true, -- this BFM drives data signals
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length);
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
log(ID_PACKET_INITIATE, proc_call & "=> " & add_msg_delimiter(msg), scope, msg_id_panel);
------------------------------------------------------------------------------------------------------------
-- Send byte by byte. There may be multiple bytes per clock cycle, depending on axistream_if'tdata width.
------------------------------------------------------------------------------------------------------------
for byte in 0 to data_array'high loop
log(ID_PACKET_DATA, proc_call & "=> Tx " & to_string(data_array(byte), HEX, AS_IS, INCL_RADIX) &
-- ", tuser=" & to_string(user_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tstrb=" & to_string(strb_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tid=" & to_string(id_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tdest=" & to_string(dest_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
", byte# " & to_string(byte) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
-------------------------------------------------------------------
-- Set tvalid low (once per transmission or multiple random times)
-------------------------------------------------------------------
if v_byte_in_word = 0 and (config.valid_low_duration > 0 or config.valid_low_duration = C_RANDOM) then
v_valid_low_cycle_count := 0;
-- Check if pulse duration is defined or random
if config.valid_low_duration > 0 then
v_valid_low_duration := config.valid_low_duration;
elsif config.valid_low_duration = C_RANDOM then
v_valid_low_duration := random(1,config.valid_low_max_random_duration);
end if;
-- Deassert tvalid once per transmission on a specific word
if config.valid_low_at_word_num = byte/c_num_bytes_per_word then
while v_valid_low_cycle_count < v_valid_low_duration loop
v_valid_low_cycle_count := v_valid_low_cycle_count + 1;
wait until rising_edge(clk);
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
-- Deassert tvalid multiple random times per transmission
elsif config.valid_low_at_word_num = C_MULTIPLE_RANDOM and random(0.0,1.0) <= config.valid_low_multiple_random_prob then
while v_valid_low_cycle_count < v_valid_low_duration loop
v_valid_low_cycle_count := v_valid_low_cycle_count + 1;
wait until rising_edge(clk);
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
end if;
end if;
axistream_if.tvalid <= '1';
-- Byte locations within the data word is described in chapter 2.3 in "ARM IHI0051A"
axistream_if.tdata(7+8*v_byte_in_word downto 8*v_byte_in_word) <= data_array(byte);
-- Set sideband data for this transfer (i.e. this word)
if v_byte_in_word = 0 then
axistream_if.tuser(c_num_user_bits_per_word-1 downto 0) <= user_array(byte/c_num_bytes_per_word)(c_num_user_bits_per_word-1 downto 0);
axistream_if.tstrb(c_num_strb_bits_per_word-1 downto 0) <= strb_array(byte/c_num_bytes_per_word)(c_num_strb_bits_per_word-1 downto 0);
axistream_if.tid(c_num_id_bits_per_word-1 downto 0) <= id_array(byte/c_num_bytes_per_word)(c_num_id_bits_per_word-1 downto 0);
axistream_if.tdest(c_num_dest_bits_per_word-1 downto 0) <= dest_array(byte/c_num_bytes_per_word)(c_num_dest_bits_per_word-1 downto 0);
end if;
-- TKEEP[x] is associated with TDATA[(7+8*v_byte_in_word) : 8*v_byte_in_word].
axistream_if.tkeep(v_byte_in_word) <= '1';
-- Default: Go to next 'byte' iteration in zero time (when tdata is not completely filled with bytes).
v_wait_for_next_transfer_cycle := false;
if byte = data_array'high then
-- Packet done.
axistream_if.tlast <= '1';
v_wait_for_next_transfer_cycle := true; -- No more bytes to fill in tdata
else
axistream_if.tlast <= '0';
end if;
if v_byte_in_word = c_num_bytes_per_word-1 then
-- Next byte is in the next clk cycle
v_byte_in_word := 0;
v_wait_for_next_transfer_cycle := true; -- No more bytes to fill in tdata
else
-- Next byte is in the same clk cycle
v_byte_in_word := v_byte_in_word + 1;
end if;
--
-- If no more bytes to fill in tdata, wait until the transfer takes place (tvalid=1 and tready=1)
--
if v_wait_for_next_transfer_cycle then
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
v_tready := axistream_if.tready;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
v_clk_cycles_waited := 1;
-- Check tready signal is asserted (sampled at rising_edge)
while v_tready = '0' loop
wait until rising_edge(clk);
v_tready := axistream_if.tready;
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
-- If timeout then exit procedure
if v_clk_cycles_waited >= config.max_wait_cycles then
v_timeout := true;
exit;
end if;
end loop;
if v_timeout then
exit;
end if;
-- Default values for the next clk cycle
axistream_if <= init_axistream_if_signals(is_master => true, -- this BFM drives data signals
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length
);
end if;
end loop;
-- Done. Check if there was a timeout or it was successful
if v_timeout then
alert(config.max_wait_cycles_severity, proc_call & "=> Failed. Timeout while waiting for tready. " &
add_msg_delimiter(msg), scope);
else
log(ID_PACKET_COMPLETE, proc_call & "=> Tx DONE. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Helper variables
variable v_bytes_in_word : integer := (data_array(data_array'low)'length/8);
variable v_num_bytes : integer := (data_array'length) * v_bytes_in_word;
variable v_data_array : t_byte_array(0 to v_num_bytes-1);
variable v_data_array_idx : integer := 0;
variable v_check_ok : boolean := false;
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- t_slv_array sanity check
v_check_ok := check_value(data_array(data_array'low)'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte", scope, ID_NEVER, msg_id_panel);
if v_check_ok then
-- copy byte(s) from t_slv_array to t_byte_array
v_data_array := convert_slv_array_to_byte_array(data_array, v_byte_endianness);
-- call t_byte_array overloaded procedure
axistream_transmit_bytes(v_data_array, user_array, strb_array, id_array, dest_array, msg, clk, axistream_if, scope, msg_id_panel, config);
end if;
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Helper variables
variable v_check_ok : boolean := false;
variable v_data_array : t_slv_array(0 to 0)(data_array'length-1 downto 0);
begin
-- t_slv_array sanity check
v_check_ok := check_value(data_array'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte", scope, ID_NEVER, msg_id_panel);
if v_check_ok then
v_data_array(0) := data_array;
-- call t_slv_array overloaded procedure
axistream_transmit(v_data_array, user_array, strb_array, id_array, dest_array, msg, clk, axistream_if, scope, msg_id_panel, config);
end if;
end procedure;
-- Overload that doesn't use records for the AXI interface:
-- (In turn calls the record version)
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading procedure
axistream_transmit_bytes(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading t_slv_array procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading slv procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Overload with default value for strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
axistream_transmit_bytes(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
-- call overloading t_slv_array procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
-- call overloading slv procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Overload with default value for user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another overload that fills in strb_array, id_array, dest_array
axistream_transmit_bytes(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another t_slv_array overload that fills in strb_array, id_array, dest_array
axistream_transmit(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another slv overload that fills in strb_array, id_array, dest_array
axistream_transmit(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
--------------------------------------------------------
--
-- AXIStream Receive
--
--------------------------------------------------------
-- Receive a packet, store it in data_array
-- data_array'length can be longer than the actual packet, so that you can call receive() without knowing the length to be expected.
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
constant local_proc_name : string := "axistream_receive"; -- Internal proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "()"; -- Internal proc_call; used if called from sequncer or VVC
-- Helper variables
variable v_proc_call : line; -- Current proc_call, external or local
variable v_byte_in_word : integer range 0 to c_num_bytes_per_word-1 := 0; -- current Byte within the data word
variable v_byte_cnt : integer := 0; -- # bytes received
variable v_timeout : boolean := false;
variable v_done : boolean := false;
variable v_invalid_count : integer := 0; -- # cycles without valid being asserted
variable v_byte_idx : integer;
variable v_word_idx : integer;
variable v_ready_low_duration : natural := 0;
variable v_ready_low_cycle_count : natural := 0;
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_sample_data_now : boolean := false;
begin
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'axistream_receive...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing axistream_receive...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- DEPRECATE: data_array as t_byte_array will be removed in next major release
deprecate(local_proc_call, "data_array as t_byte_array has been deprecated. Use data_array as t_slv_array.");
check_value(axistream_if.tuser'length <= C_MAX_TUSER_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TUSER_BITS is high enough for axistream_if.tuser.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdata'length >= 8, TB_ERROR, "Sanity check: Check that tdata is at least one byte wide. Narrower tdata is not supported.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdata'length mod 8 = 0, TB_ERROR, "Sanity check: Check that tdata is an integer number of bytes wide.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tid'length <= C_MAX_TID_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TID_BITS is high enough for axistream_if.tid.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdest'length <= C_MAX_TDEST_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TDEST_BITS is high enough for axistream_if.tdest.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tkeep'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tkeep equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tstrb'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tstrb equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(data_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for knowing which byte is sent first", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(user_array'ascending, TB_ERROR, "Sanity check: Check that user_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(strb_array'ascending, TB_ERROR, "Sanity check: Check that strb_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(id_array'ascending, TB_ERROR, "Sanity check: Check that id_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(dest_array'ascending, TB_ERROR, "Sanity check: Check that dest_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end if;
-- Avoid driving inputs
axistream_if <= init_axistream_if_signals(
is_master => false,
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length,
config => config );
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
log(ID_PACKET_INITIATE, v_proc_call.all & "=> Receive packet. " & add_msg_delimiter(msg), scope, msg_id_panel);
------------------------------------------------------------------------------------------------------------
-- Sample byte by byte. There may be multiple bytes per clock cycle, depending on axistream_if'tdata width.
------------------------------------------------------------------------------------------------------------
while not v_done loop
--------------------------------------------------------------------------------------
-- Set tready low before given byte (once per transmission or multiple random times)
--------------------------------------------------------------------------------------
if v_byte_in_word = 0 and (config.ready_low_duration > 0 or config.ready_low_duration = C_RANDOM) then
v_ready_low_cycle_count := 0;
-- Check if pulse duration is defined or random
if config.ready_low_duration > 0 then
v_ready_low_duration := config.ready_low_duration;
elsif config.ready_low_duration = C_RANDOM then
v_ready_low_duration := random(1,config.ready_low_max_random_duration);
end if;
-- Deassert tready once per transmission on a specific word
if config.ready_low_at_word_num = v_byte_cnt/c_num_bytes_per_word then
axistream_if.tready <= '0';
-- Wait until tvalid goes high before counting the deassertion cycles
while axistream_if.tvalid = '0' and v_invalid_count < config.max_wait_cycles loop
v_invalid_count := v_invalid_count + 1;
wait until rising_edge(clk);
-- If tvalid was asserted right before the rising_edge then we have already waited
-- one cycle with tready deasserted
if axistream_if.tvalid = '1' then
v_ready_low_duration := v_ready_low_duration - 1;
end if;
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
-- TValid timed out
if v_invalid_count >= config.max_wait_cycles then
v_timeout := true;
v_done := true;
v_ready_low_duration := 0;
end if;
while v_ready_low_cycle_count < v_ready_low_duration loop
v_ready_low_cycle_count := v_ready_low_cycle_count + 1;
wait until rising_edge(clk);
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
-- Deassert tready multiple random times per transmission
elsif config.ready_low_at_word_num = C_MULTIPLE_RANDOM and random(0.0,1.0) <= config.ready_low_multiple_random_prob then
axistream_if.tready <= '0';
while v_ready_low_cycle_count < v_ready_low_duration loop
v_ready_low_cycle_count := v_ready_low_cycle_count + 1;
wait until rising_edge(clk);
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
end if;
end if;
------------------------------------------------------------
-- Assert the tready signal (after tvalid is high) and wait
-- for the rising_edge of the clock to sample the data
------------------------------------------------------------
if v_byte_in_word = 0 then
-- To receive the first byte wait until tvalid goes high before asserting tready
if v_byte_cnt = 0 and axistream_if.tvalid = '0' and not(v_timeout) then
while axistream_if.tvalid = '0' and v_invalid_count < config.max_wait_cycles loop
v_invalid_count := v_invalid_count + 1;
wait until rising_edge(clk);
-- If tvalid was asserted right before the rising_edge then we should sample
-- the data right away, otherwise we wait
if axistream_if.tvalid = '1' and axistream_if.tready = '1' then
v_sample_data_now := true;
else
v_sample_data_now := false;
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
end loop;
if not(v_sample_data_now) then
-- TValid is now high, assert tready
if v_invalid_count < config.max_wait_cycles then
axistream_if.tready <= '1';
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
-- TValid timed out
else
v_timeout := true;
v_done := true;
end if;
end if;
-- TValid was already high, assert tready right away
else
axistream_if.tready <= '1';
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
end if;
end if;
if not(v_timeout) then
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
end if;
------------------------------------------------------------
-- Sample the data
------------------------------------------------------------
if axistream_if.tvalid = '1' and axistream_if.tready = '1' then
v_invalid_count := 0;
-- Sample data
data_array(v_byte_cnt) := axistream_if.tdata(7+8*v_byte_in_word downto 8*v_byte_in_word);
-- Sample sideband data for this transfer (this word): There is one array entry per word
if v_byte_in_word = 0 then
v_word_idx := v_byte_cnt/c_num_bytes_per_word;
if (v_word_idx <= user_array'high) then -- Include this 'if' to allow a shorter user_array if the caller doesn't care what tuser is
user_array(v_byte_cnt/c_num_bytes_per_word)(c_num_user_bits_per_word-1 downto 0) := axistream_if.tuser(c_num_user_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= strb_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tstrb is
strb_array(v_byte_cnt/c_num_bytes_per_word)(c_num_strb_bits_per_word-1 downto 0) := axistream_if.tstrb(c_num_strb_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= id_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tid is
id_array(v_byte_cnt/c_num_bytes_per_word)(c_num_id_bits_per_word-1 downto 0) := axistream_if.tid(c_num_id_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= dest_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tdest is
dest_array(v_byte_cnt/c_num_bytes_per_word)(c_num_dest_bits_per_word-1 downto 0) := axistream_if.tdest(c_num_dest_bits_per_word-1 downto 0);
end if;
end if;
log(ID_PACKET_DATA, v_proc_call.all & "=> Rx " & to_string(data_array(v_byte_cnt), HEX, AS_IS, INCL_RADIX) &
-- ", tuser=" & to_string(user_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tstrb=" & to_string(strb_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tid=" & to_string(id_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tdest=" & to_string(dest_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
" (byte# " & to_string(v_byte_cnt) & "). " & add_msg_delimiter(msg), scope, msg_id_panel);
-- Stop sampling data when we have filled the data_array
if v_byte_cnt = data_array'high then
-- Check tlast='1' at expected last byte
if config.check_packet_length then
check_value(axistream_if.tlast, '1', config.protocol_error_severity, "Check tlast at expected last byte = " & to_string(v_byte_cnt) & ". " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
end if;
v_done := true;
end if;
-- Allow that tlast arrives sooner than indicated by data_array'high
-- if receive() is called without knowing the length to be expected.
if axistream_if.tlast = '1' then
if axistream_if.tkeep(v_byte_in_word) = '1' then
if v_byte_in_word = c_num_bytes_per_word-1 then
-- it's the last byte in word and tlast='1', thus the last in packet.
v_done := true;
else
if axistream_if.tkeep(v_byte_in_word+1) = '0' then
-- Next byte in word is invalid, so this is the last byte
v_done := true;
-- Check that tkeep for the remaining bytes in the last word are also '0'. (Only continous stream supported)
v_byte_idx := v_byte_in_word+1;
l_check_remaining_TKEEP: loop
check_value(axistream_if.tkeep(v_byte_idx), '0', ERROR, "Check that tkeep doesn't go from '1' to '0' to '1' again within this last word. (The BFM supports only continuous stream)", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if v_byte_idx < (axistream_if.tkeep'length-1) then
v_byte_idx := v_byte_idx + 1;
else
exit l_check_remaining_TKEEP;
end if;
end loop;
else
-- Next byte in word is valid but the data_array has finished
if v_done then
alert(ERROR, v_proc_call.all & "=> Failed. data_array too small for received bytes. " & add_msg_delimiter(msg), scope);
end if;
end if;
end if;
end if;
else -- tlast = 0
-- Check that all tkeep bits are '1'. (Only continous stream supported)
check_value(axistream_if.tkeep(v_byte_in_word), '1', ERROR, "When tlast='0', check that all tkeep bits are '1'. (The BFM supports only continuous stream)" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end if;
-- Next byte is in the next clk cycle
if v_byte_in_word = c_num_bytes_per_word-1 then
-- Don't wait on the last cycle
if not(v_done) then
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
v_byte_in_word := 0;
-- Next byte is in the same clk cycle
else
v_byte_in_word := v_byte_in_word + 1;
end if;
-- Next byte
v_byte_cnt := v_byte_cnt + 1;
------------------------------------------------------------
-- Data couldn't be sampled, wait until next cycle
------------------------------------------------------------
elsif not(v_timeout) then
-- Check for timeout (also when max_wait_cycles_severity = NO_ALERT,
-- or else the VVC will wait forever, until the UVVM cmd times out)
if v_invalid_count >= config.max_wait_cycles then
v_timeout := true;
v_done := true;
else
v_invalid_count := v_invalid_count + 1;
end if;
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
end loop; -- while not v_done
-- Wait according to bfm_sync config
if not(v_timeout) then
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
-- Set the number of bytes received
data_length := v_byte_cnt;
-- Log the received frame
if is_log_msg_enabled(ID_PACKET_PAYLOAD, msg_id_panel) then -- large frames may affect performance
log(ID_PACKET_PAYLOAD, v_proc_call.all & "=> Rx Frame (" & to_string(v_byte_cnt) & "B) " & to_string(data_array) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
-- Check if there was a timeout or it was successful
if v_timeout then
alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout while waiting for valid data. " & add_msg_delimiter(msg), scope);
else
if ext_proc_call = "" then
log(ID_PACKET_COMPLETE, v_proc_call.all & "=> Rx DONE (" & to_string(v_byte_cnt) & "B)" & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. axistream_expect)
end if;
end if;
-- Done, set axistream back to default
axistream_if <= init_axistream_if_signals(
is_master => false,
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length,
config => config );
DEALLOCATE(v_proc_call);
end procedure axistream_receive_bytes;
-- Overloaded t_slv_array procedure
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is -- helper variables
variable v_bytes_in_word : integer := (data_array(data_array'low)'length/8);
variable v_num_bytes : integer := (data_array'length) * v_bytes_in_word;
variable v_data_array_as_byte : t_byte_array(0 to v_num_bytes-1);
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- call overloaded t_byte_array procedure
axistream_receive_bytes ( v_data_array_as_byte,
data_length, user_array, strb_array, id_array, dest_array, msg,
clk, axistream_if, scope, msg_id_panel, config, ext_proc_call );
data_array := convert_byte_array_to_slv_array(v_data_array_as_byte, v_bytes_in_word, v_byte_endianness);
end procedure axistream_receive;
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
begin
-- Simply call the record version
axistream_receive_bytes(
data_array => data_array,
data_length => data_length,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config,
ext_proc_call => ext_proc_call);
end procedure axistream_receive_bytes;
-- Overloading t_slv_array procedure
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
begin
-- Simply call the record version
axistream_receive(
data_array => data_array,
data_length => data_length,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config,
ext_proc_call => ext_proc_call);
end procedure axistream_receive;
--------------------------------------------------------
--
-- AXIStream Expect
--
--------------------------------------------------------
-- Receive data, then compare the received data against exp_data_array
-- - If the received data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axistream_expect";
constant proc_call : string := "axistream_expect(" & to_string(exp_data_array'length) & "B)";
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
-- Helper variables
variable v_config : t_axistream_bfm_config := config;
variable v_rx_data_array : t_byte_array(exp_data_array'range); -- received data
variable v_rx_user_array : t_user_array(exp_user_array'range); -- received tuser
variable v_rx_strb_array : t_strb_array(exp_strb_array'range);
variable v_rx_id_array : t_id_array(exp_id_array'range);
variable v_rx_dest_array : t_dest_array(exp_dest_array'range);
variable v_rx_data_length : natural;
variable v_data_error_cnt : natural := 0;
variable v_user_error_cnt : natural := 0;
variable v_strb_error_cnt : natural := 0;
variable v_id_error_cnt : natural := 0;
variable v_dest_error_cnt : natural := 0;
variable v_first_errored_byte : natural;
variable v_alert_radix : t_radix;
begin
-- Receive and store data
axistream_receive_bytes(data_array => v_rx_data_array,
data_length => v_rx_data_length,
user_array => v_rx_user_array,
strb_array => v_rx_strb_array,
id_array => v_rx_id_array,
dest_array => v_rx_dest_array,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => v_config,
ext_proc_call => proc_call);
-- Check if each received bit matches the expected
-- Find and report the first errored byte
for byte in v_rx_data_array'high downto 0 loop
for i in v_rx_data_array(byte)'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_data_array(byte)(i) = '-' or check_value(v_rx_data_array(byte)(i), exp_data_array(byte)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
-- Received byte does not match the expected byte
--log(config.id_for_bfm, proc_call & "=> NOK, checked " & to_string(v_rx_data_array(byte), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_data_array(byte), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
v_data_error_cnt := v_data_error_cnt + 1;
v_first_errored_byte := byte;
end if;
end loop;
end loop;
-- Check tuser matches exp_user_array
-- Check all bits the exp_user_array. If the caller (Test Sequencer or VVC) don't care, the length of exp_user_array input shall be only one
for word in exp_user_array'high downto 0 loop
for i in c_num_user_bits_per_word-1 downto 0 loop -- i = bit
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_user_array(word)(i) = '-' or check_value(v_rx_user_array(word)(i), exp_user_array(word)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_user_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_user_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tuser word does not match the expected word
v_user_error_cnt := v_user_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_strb_array matches received tstrb
for word in exp_strb_array'high downto 0 loop
for i in c_num_strb_bits_per_word-1 downto 0 loop -- i = bit
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_strb_array(word)(i) = '-' or check_value(v_rx_strb_array(word)(i), exp_strb_array(word)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_strb_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_strb_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tstrb word does not match the expected word
v_strb_error_cnt := v_strb_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_id_array matches received tid
for word in exp_id_array'high downto 0 loop
for i in c_num_id_bits_per_word-1 downto 0 loop -- i = bit
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_id_array(word)(i) = '-' or check_value(v_rx_id_array(word)(i), exp_id_array(word)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_id_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_id_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tid word does not match the expected word
v_id_error_cnt := v_id_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_dest_array matches received tdest
for word in exp_dest_array'high downto 0 loop
for i in c_num_dest_bits_per_word-1 downto 0 loop -- i = bit
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_dest_array(word)(i) = '-' or check_value(v_rx_dest_array(word)(i), exp_dest_array(word)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_dest_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_dest_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tdest word does not match the expected word
v_dest_error_cnt := v_dest_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- No more than one alert per packet
if v_data_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data_array(v_first_errored_byte), exp_data_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_data_error_cnt) & " data bits. First mismatch in byte# " & to_string(v_first_errored_byte) & ". Was " &
to_string(v_rx_data_array(v_first_errored_byte), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_data_array(v_first_errored_byte), v_alert_radix, AS_IS, INCL_RADIX) &
"." & LF & add_msg_delimiter(msg), scope);
elsif v_user_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_user_array(v_first_errored_byte), exp_user_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_user_error_cnt) & " tuser bits. First mismatch in word# " & to_string(v_first_errored_byte) &
". Was " & to_string(v_rx_user_array(v_first_errored_byte)(c_num_user_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " &
to_string(exp_user_array(v_first_errored_byte)(c_num_user_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_strb_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_strb_array(v_first_errored_byte), exp_strb_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_strb_error_cnt) & " tstrb bits. First mismatch in word# " & to_string(v_first_errored_byte) &
". Was " & to_string(v_rx_strb_array(v_first_errored_byte)(c_num_strb_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " &
to_string(exp_strb_array(v_first_errored_byte)(c_num_strb_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_id_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_id_array(v_first_errored_byte), exp_id_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_id_error_cnt) & " tid bits. First mismatch in word# " & to_string(v_first_errored_byte) &
". Was " & to_string(v_rx_id_array(v_first_errored_byte)(c_num_id_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " &
to_string(exp_id_array(v_first_errored_byte)(c_num_id_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_dest_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_dest_array(v_first_errored_byte), exp_dest_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_dest_error_cnt) & " tdest bits. First mismatch in word# " & to_string(v_first_errored_byte) &
". Was " & to_string(v_rx_dest_array(v_first_errored_byte)(c_num_dest_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " &
to_string(exp_dest_array(v_first_errored_byte)(c_num_dest_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received " & to_string(v_rx_data_array'length) & "Bytes. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axistream_expect_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "axistream_expect"; -- Internal proc_name; used if called from sequncer or VVC
-- helper variables
variable v_bytes_in_word : integer := (exp_data_array(exp_data_array'low)'length/8);
variable v_num_bytes : integer := (exp_data_array'length) * v_bytes_in_word;
variable v_exp_data_array : t_byte_array(0 to v_num_bytes-1);
variable v_exp_data_array_idx : integer := 0;
variable v_check_ok : boolean := false;
variable v_dummy : t_slv_array(0 to 0)(31 downto 0);
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- t_slv_array sanity check
v_check_ok := check_value(exp_data_array(exp_data_array'low)'length mod 8 = 0, TB_ERROR, "Sanity check: Check that exp_data_array is N*byte", scope, ID_NEVER, msg_id_panel);
if v_check_ok then
-- copy byte(s) from t_slv_array to t_byte_array
v_exp_data_array := convert_slv_array_to_byte_array(exp_data_array, v_byte_endianness);
-- call t_byte_array overloaded procedure
axistream_expect_bytes(v_exp_data_array,
exp_user_array,
exp_strb_array,
exp_id_array,
exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end if;
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "axistream_expect"; -- Internal proc_name; used if called from sequncer or VVC
-- helper variables
variable v_exp_data_array : t_slv_array(0 to 0)(exp_data_array'length-1 downto 0);
variable v_check_ok : boolean := false;
begin
-- t_slv_array sanity check
v_check_ok := check_value(exp_data_array'length mod 8 = 0, TB_ERROR, "Sanity check: Check that exp_data_array word is N*byte", scope, ID_NEVER, msg_id_panel);
if v_check_ok then
v_exp_data_array(0) := exp_data_array;
-- call t_slv_array overloaded procedure
axistream_expect(v_exp_data_array,
exp_user_array,
exp_strb_array,
exp_id_array,
exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end if;
end procedure;
-- Overloaded version without records
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the record version
axistream_expect_bytes(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the t_slv_array record version
axistream_expect(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the slv record version
axistream_expect(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-- Overload without exp_strb_array, exp_id_array, exp_dest_array arguments' argument
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
axistream_expect_bytes(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded t_slv_array procedure
axistream_expect(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded slv procedure
axistream_expect(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-- Overload without arguments exp_user_array, exp_strb_array, exp_id_array, exp_dest_array arguments
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
axistream_expect_bytes(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded t_slv_array procedure
axistream_expect(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded slv procedure
axistream_expect(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
end package body axistream_bfm_pkg;
| mit |
UVVM/UVVM_All | bitvis_vip_gmii/src/vvc_cmd_pkg.vhd | 1 | 7651 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.transaction_pkg.all;
--==========================================================================================
--==========================================================================================
package vvc_cmd_pkg is
alias t_operation is work.transaction_pkg.t_operation;
--==========================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--==========================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data_array : t_slv_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1)(7 downto 0);
data_array_length : natural;
num_bytes_read : natural;
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data_array => (others => (others => '0')),
data_array_length => 0,
num_bytes_read => 0,
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL
);
--==========================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--==========================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--==========================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in uvvm_vvc_framework/Common_VVC_Methods QuickRef.
-- - t_vvc_result includes the return value of the procedure in the BFM. It can also
-- be defined as a record if multiple values shall be transported from the BFM
--==========================================================================================
type t_vvc_result is record
data_array : t_slv_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1)(7 downto 0);
data_array_length : natural;
end record;
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--==========================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in VVC interpreter.
--==========================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--==========================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from VVC to sequencer
--==========================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
--==========================================================================================
-- Procedures
--==========================================================================================
function to_string(
result : t_vvc_result
) return string;
function to_string(
bytes : t_slv_array
) return string;
function gmii_match(
constant actual : in t_slv_array;
constant expected : in t_slv_array
) return boolean;
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
-- Custom to_string overload needed when result is of a record type
function to_string(
result : t_vvc_result
) return string is
begin
return to_string(result.data_array'length) & " Bytes";
end;
function to_string(
bytes : t_slv_array
) return string is
begin
return to_string(bytes'length) & " Bytes";
end function to_string;
-- Compares two GMII byte arrays and returns true if they are equal (used in scoreboard)
function gmii_match(
constant actual : in t_slv_array;
constant expected : in t_slv_array
) return boolean is
begin
return (actual = expected);
end function gmii_match;
end package body vvc_cmd_pkg; | mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_dre_mux8_1_x_n.vhd | 18 | 6145 | -------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux8_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 8 to 1 xn bit wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 8 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux8_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 8x Mux slice
);
port (
Sel : In std_logic_vector(2 downto 0);
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 input
I2 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 2 input
I3 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 3 input
I4 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 4 input
I5 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 5 input
I6 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 6 input
I7 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 7 input
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux8_1_x_n; --
Architecture implementation of axi_datamover_dre_mux8_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT8_1
--
-- Process Description:
-- This process implements an 8 to 1 mux.
--
-------------------------------------------------------------
SELECT8_1 : process (Sel, I0, I1, I2, I3,
I4, I5, I6, I7)
begin
case Sel is
when "000" =>
Y <= I0;
when "001" =>
Y <= I1;
when "010" =>
Y <= I2;
when "011" =>
Y <= I3;
when "100" =>
Y <= I4;
when "101" =>
Y <= I5;
when "110" =>
Y <= I6;
when "111" =>
Y <= I7;
when others =>
Y <= I0;
end case;
end process SELECT8_1;
end implementation; -- axi_datamover_dre_mux8_1_x_n
-------------------------------------------------------------------------------
-- End 8 to 1 xN Mux
-------------------------------------------------------------------------------
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_mm2s_sg_if.vhd | 2 | 45394 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sg_if.vhd
-- Description: This entity is the MM2S Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_cdc_v1_0;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Master AXI Control Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 ;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96 downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
desc_fetch_done : out std_logic ; --
updt_pending : out std_logic ;
packet_in_progress : out std_logic ; --
--
-- MM2S Descriptor Update Request (from mm2s_sm) --
desc_update_done : out std_logic ; --
--
mm2s_sts_received_clr : out std_logic ; --
mm2s_sts_received : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_done : in std_logic ; --
mm2s_interr : in std_logic ; --
mm2s_slverr : in std_logic ; --
mm2s_decerr : in std_logic ; --
mm2s_tag : in std_logic_vector(3 downto 0) ; --
mm2s_halt : in std_logic ; --
--
-- Control Stream Output --
cntrlstrm_fifo_wren : out std_logic ; --
cntrlstrm_fifo_din : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : in std_logic ; --
--
--
-- MM2S Descriptor Field Output --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_new_curdesc_wren : out std_logic ; --
--
mm2s_desc_baddress : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : out std_logic ; --
mm2s_desc_sof : out std_logic ; --
mm2s_desc_cmplt : out std_logic ; --
mm2s_desc_info : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_mm2s_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(4 downto 0) := (others => '0');
-- Used to determine when Control word is coming, in order to check SOF bit.
-- This then indicates that the app fields need to be directed towards the
-- control stream fifo.
-- Word Five Count
-- Incrementing these counts by 2 as i am now sending two extra fields from BD
--constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "1011"; --"0111";
constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "0001";
-- Word Six Count
--constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0101"; --"1000";
constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0010";
-- Word Seven Count
--constant NINE_COUNT : std_logic_vector(3 downto 0) := "1010"; --"1001";
constant NINE_COUNT : std_logic_vector(3 downto 0) := "0011";
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal desc_fetch_done_i : std_logic := '0';
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Fetch control signals for driving out control app stream
signal analyze_control : std_logic := '0';
signal redirect_app : std_logic := '0';
signal redirect_app_d1 : std_logic := '0';
signal redirect_app_re : std_logic := '0';
signal redirect_app_hold : std_logic := '0';
signal mask_fifo_write : std_logic := '0';
-- Current descriptor control and fetch throttle control
signal mm2s_new_curdesc_wren_i : std_logic := '0';
signal mm2s_pending_update : std_logic := '0';
signal mm2s_pending_ptr_updt : std_logic := '0';
-- Descriptor Update Signals
signal mm2s_complete : std_logic := '0';
signal mm2s_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_xferd_bytes_int : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- Update Descriptor Pointer Holding Registers
signal updt_desc_reg0 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
-- Update Descriptor Status Holding Register
signal updt_desc_reg2 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
-- Pointer shift control
signal updt_shftenbl : std_logic := '0';
-- Update pointer stream
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Update status stream
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status control
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal packet_start : std_logic := '0';
signal packet_end : std_logic := '0';
signal mm2s_halt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cdc_d2 : std_logic := '0';
signal mm2s_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cdc_d2 : SIGNAL IS "true";
signal temp : std_logic := '0';
signal m_axis_mm2s_ftch_tlast_new : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
mm2s_desc_blength <= mm2s_desc_blength_i;
mm2s_desc_blength_v <= mm2s_desc_blength_v_i;
mm2s_desc_blength_s <= mm2s_desc_blength_s_i;
-- Drive fetch request done on tlast
desc_fetch_done_i <= m_axis_mm2s_ftch_tlast_new
and m_axis_mm2s_ftch_tvalid_new;
-- pass out of module
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_mm2s_ftch_tvalid_new
and ftch_tready
and desc_fetch_req
and not mm2s_pending_update;
-- Passed curdes write out to register module
mm2s_new_curdesc_wren <= desc_fetch_done_i; --mm2s_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch1_desc_available; --m_axis_mm2s_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_d1_cdc_tig <= '0';
-- -- mm2s_halt_d2 <= '0';
-- -- else
-- mm2s_halt_d1_cdc_tig <= mm2s_halt;
-- mm2s_halt_cdc_d2 <= mm2s_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_d2 <= mm2s_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_d2 <= mm2s_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
packet_start <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_SOF_BIT) = '1'
else '0';
packet_end <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_EOF_BIT) = '1'
else '0';
REG_PACKET_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or packet_end = '1')then
packet_in_progress <= '0';
elsif(packet_start = '1')then
packet_in_progress <= '1';
end if;
end if;
end process REG_PACKET_PROGRESS;
-- Status/Control stream enabled therefore APP fields are included
GEN_FTCHIF_WITH_APP : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
-- Control Stream Ethernet TAG
constant ETHERNET_CNTRL_TAG : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH - 1 downto 0)
:= X"A000_0000";
begin
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); -- downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65);
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_curdesc_msb <= (others => '0'); --desc_reg1;
mm2s_desc_baddr_lsb <= desc_reg2;
mm2s_desc_baddr_msb <= (others => '0'); --desc_reg3;
-- desc 5 are reserved and thus don't care
-- CR 583779, need to pass on tuser and cache information
mm2s_desc_info <= (others => '0'); --desc_reg4; -- this coincides with desc_fetch_done
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= desc_reg8;
mm2s_desc_app1 <= desc_reg9;
mm2s_desc_app2 <= desc_reg10;
mm2s_desc_app3 <= desc_reg11;
mm2s_desc_app4 <= desc_reg12;
-- Drive ready if descriptor fetch request is being made
-- If not redirecting app fields then drive ready based on sm request
-- If redirecting app fields then drive ready based on room in cntrl strm fifo
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
redirect_app <= '0';
cntrlstrm_fifo_din <= (others => '0');
cntrlstrm_fifo_wren <= '0';
end generate GEN_FTCHIF_WITH_APP;
-- Status/Control stream diabled therefore APP fields are NOT included
GEN_FTCHIF_WITHOUT_APP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7(DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_curdesc_msb <= (others => '0'); --desc_reg1;
mm2s_desc_baddr_lsb <= desc_reg2;
mm2s_desc_baddr_msb <= (others => '0'); --desc_reg3;
-- desc 4 and desc 5 are reserved and thus don't care
-- CR 583779, need to send the user and xchache info
mm2s_desc_info <= (others => '0'); --desc_reg4;
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_mm2s_ftch_tdata_mcdma_new (31 downto 0); --63 downto 32);
desc_reg5 <= m_axis_mm2s_ftch_tdata_mcdma_new (63 downto 32);
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_curdesc_msb <= (others => '0'); --desc_reg1;
mm2s_desc_baddr_lsb <= desc_reg2;
mm2s_desc_baddr_msb <= (others => '0'); --desc_reg3;
-- As per new MCDMA descriptor
mm2s_desc_info <= desc_reg4; -- (31 downto 24) & desc_reg7 (23 downto 0);
mm2s_desc_blength_s_i <= "0000000" & desc_reg5(15 downto 0);
mm2s_desc_blength_v_i <= "0000000000" & desc_reg5(31 downto 19);
mm2s_desc_blength_i <= "0000000" & desc_reg6(15 downto 0);
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= '0' ; --desc_reg7(DESC_STS_CMPLTD_BIT); -- we are not considering the completed bit
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_MCDMA;
-- Drive ready if descriptor fetch request is being made
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
end generate GEN_FTCHIF_WITHOUT_APP;
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH = 64 generate
mm2s_desc_baddress <= mm2s_desc_baddr_msb & mm2s_desc_baddr_lsb;
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH = 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_msb & mm2s_desc_curdesc_lsb;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_lsb;
end generate GEN_NEW_32BIT_CURDESC;
mm2s_new_curdesc_wren_i <= desc_fetch_done_i;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 <= DESC_LAST
& mm2s_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
-----------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg1 <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg1 <= DESC_LAST
& mm2s_desc_curdesc_msb;
-- Shift data out on shift enable
elsif(updt_shftenbl = '1')then
updt_desc_reg1 <= (others => '0');
end if;
end if;
end process UPDT_DESC_WRD1;
-- Shift in data from SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_mm2s_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1' and updtptr_tlast = '1'
and s_axis_mm2s_updtptr_tready = '1'
else '0';
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
--*****************************************************************************
--** Status Update Logic
--*****************************************************************************
mm2s_complete <= '1'; -- Fixed at '1'
---------------------------------------------------------------------------
-- Descriptor queuing turned on in sg engine therefore need to instantiate
-- fifo to hold fetch buffer lengths. Also need to throttle fetches
-- if pointer has not been updated yet or length fifo is full
---------------------------------------------------------------------------
GEN_UPDT_FOR_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic; -- xfer'ed bytes fifo reset
signal xb_fifo_full : std_logic; -- xfer'ed bytes fifo full
begin
-----------------------------------------------------------------------
-- Need to flag a pending pointer update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
mm2s_pending_ptr_updt <= '0';
elsif (desc_fetch_done_i = '1') then --(mm2s_new_curdesc_wren_i = '1')then
mm2s_pending_ptr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pointer pending update or xferred bytes fifo full
mm2s_pending_update <= mm2s_pending_ptr_updt or xb_fifo_full;
updt_pending <= mm2s_pending_update;
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
mm2s_xferd_bytes <= (others => '0');
xb_fifo_full <= '0';
end generate GEN_MICRO_DMA;
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => desc_fetch_done_i, --mm2s_new_curdesc_wren_i ,
Data_In => mm2s_desc_blength_i ,
FIFO_Read => sts_received_re ,
Data_Out => mm2s_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
end generate GEN_NO_MICRO_DMA;
xb_fifo_reset <= not m_axi_sg_aresetn;
-- clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
mm2s_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= mm2s_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= mm2s_sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_QUEUE;
---------------------------------------------------------------------------
-- If no queue in sg engine then do not need to instantiate a
-- fifo to hold buffer lengths. Also do not need to hold off
-- fetch based on if status has been updated or not because
-- descriptors are only processed one at a time
---------------------------------------------------------------------------
GEN_UPDT_FOR_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
mm2s_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
mm2s_pending_update <= '0'; -- Not needed for the No Queue configuration
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_xferd_bytes <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
mm2s_xferd_bytes <= mm2s_desc_blength_i;
end if;
end if;
end process REG_XFERRED_BYTES;
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= mm2s_done or mm2s_interr or mm2s_decerr or mm2s_slverr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_NO_QUEUE;
-----------------------------------------------------------------------
-- Receive Status SG Update Logic
-----------------------------------------------------------------------
-- clear flag when updating status and see a tlast and target
-- (i.e. sg engine) is ready
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tlast = '1'
and updtsts_tvalid = '1'
and s_axis_mm2s_updtsts_tready = '1'
else '0';
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done
-- or datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- -- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg2 <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_reg2 <= DESC_LAST
& mm2s_tag(DATAMOVER_STS_TAGLSB_BIT) -- Desc_IOC
& mm2s_complete
& mm2s_decerr
& mm2s_slverr
& mm2s_interr
& RESERVED_STS
& mm2s_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
updtsts_tdata <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- MSB asserts last on last word of update stream
updtsts_tlast <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive tvalid
updtsts_tvalid <= updt_sts;
-- Drive update done to mm2s sm for the no queue case to indicate
-- readyd to fetch next descriptor
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
-- Update Pointer Stream
s_axis_mm2s_updtptr_tvalid <= updtptr_tvalid;
s_axis_mm2s_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_mm2s_updtptr_tdata <= updtptr_tdata ;
-- Update Status Stream
s_axis_mm2s_updtsts_tvalid <= updtsts_tvalid;
s_axis_mm2s_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
s_axis_mm2s_updtsts_tdata <= updtsts_tdata ;
-----------------------------------------------------------------------
end implementation;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_intrpt.vhd | 4 | 28207 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 2 | 96005 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ncUawuo3vR1ZycZF8xtqqfVI6gCrdI+PWd72xdzgvbKVjiUqedCWSUEBFuuQDLCwTlT4hYrqtcoA
k+jkF6hUqA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
N3KVU8m7dp9m/o5klJahn6JrAp4dPvJ5px8Qjfdd/9teg+MgeqRSyR4a+nedbYovR1iG1M+OV4GZ
eedyUHeQwlftb33WHTgiSQcQOeDYQHOhB1q+SjuhN26SLFWK3YFERu3kL1tM5w3W0nuFqj+bXHZu
R4gQdtVWH/+OjyCytQw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZuxsHcVs7eB3t+mMECRU+c4tWaV00xKC1y8JMSw6ZK4lGIrGd9iKbAKZ3Blwh1vsVCQb3NTC7N3r
Y605Rnu1VKPlFpM556/vIzoPVRgcSvlo0qBj3oTSzlA5eJk5FVF3mP4v0RD6iY8xceU38ESPNbz9
tslYUbhOJVSsY7yCjCM7p+456bByCG6ed5+0nGONoXPAT0zF3Hxdnq8qgQDMjEIvOsaFSADZUSxL
WwjD6WPmcry72t5+zgCtiIUOoGhbFWqTndKP66O5YJAWE6dVlP4zMLQZZAfmdfQyazOsgs1uciSH
+eAOcN/r5BkNmFBVWZOF8biq4mt3PmniNwcfbg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ygy9fvZbqToh8lhxP+oGEoqQi72mLbOonZqXDBQOfdz3oQWE3Hi1Zc2hfB1uR17TPoqAq2eJIm6k
q8c0om7asQ06vgODSHayDyQ+hyxq53TnIlLVx1AtJPfm0kI21kep00Mfc/Dwi7Qyt/ia2tlS/tQw
4OktcMlj77AyGCR8zdc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mcqNli4YixoMqmYwzxOZ0byTQYAQvCZuCaZ7iJ4keY79GxqKVx5edvY5HqwqCRXfHCDzwy4qGKcN
pXmE+CGNG2mMTGEfU6W2QQ+HDW5dsb4d7quBuFh6+SnA7XZEst6UjKRr26YyBGTL5qgiRLyYbkFW
QKRK7TmdgdCAj37TPbTPR6zjrQ3PTlWUwzVToIPxndDd6Jgk0ZyBHqXveC/6PEihQuzGKgS5GKHX
85sYZQakcEpa7RtFdztUyxh1/Do/cjYhmERWgZJD9wSCPweFJCsvo6MP2JripEEkasaBYRqfxMPN
DPHGfcHemBvMggmA1I4jVeD0GpW65Lo9IxE2YQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 69328)
`protect data_block
SzsPkdK/1I7crNTpc3RI4Zzo7EDlvi9ZmdqF3v/0mOM1nMfLWuVA5xM+ceSYhRiIoUv52p20oOr3
+cPj/EZvd58/OJUhWlYMurzRPuH/t5scT+ttvebEypym3cw62Mxp54aDbb8XdQaQ4v40uIvFOcXU
1Oee/B3GOidaLHMdKyMcBxCuxsp+v87qzFvNW4I43lzaT7pbWGxZdigKT8VYs/DLU7nQbqO6iRhO
UGyMQOPYuqRH9zEPH/0p0vHbo+KJ7yQ6HF8rTmaHoaSlts3Vvzy5gmJ8pm8kJ2WyHuzToyZ7YrWh
1ZH3zbIo1VbiCtyvygxmPxuwD9EHCV1Y0d4lmGdJCItDclTuzLeDpdmQxpwXecyxvxSHYcT8rNDB
pshQBBEI+cBa33B+weASypUzSS0tPQFFGwRUKUhArutmF0wNnqwTmCcBFdA2jBy56sZ1cW3wzBqP
3NNmXrADRR+XarHAjMrwLRpx3xHMsuC0hsuF1gLQQQ9Xpkcel4RXp0LRnWacb69ij5V03XdmC79f
5M+BJum2AQcUN/m6YVnzM+fxEhIOpPGCwEOWA7xOR1lSvusx57ZUfzpN8/cB3uB/8dq141zhuijR
XcvcLfDvoJ/T8WW2jNQoLP1i4hHXXS6o/tJsOjENrdPLi+Z+MEHSzvQkVFyWBen6ri2hhVg0kljt
ZS71ZhHsYrVhoN3k/5uFnWmDHxg6BLGDX0qIgDhV58ZFX9RAW9kopZjpMdCg0e07nJtO3nAEJR+l
ITNJY9RPZBs1wWgl1K3mL2xgAS9q0fD8mmZNtv79tzcAPfkZhJ9tdojv1Wl/XsD7wfyVkGRyRCKu
hm4bVmpCaFRUEhZJ44kPH8BVd50Krd5mbFttm8ztOkDtEH0kJJxd1FFFPOuCtFG3N7jnAps2ofGr
fHwmDl1T8gKzRn8osbcGRRh/r1ANaB6kOk/Zdu7fcHi2wQgenwWj0aU/dtSdyHcyFuA+xbukS7Gz
fOZb+/col2lgz1AIVVU6DxAcY/g1CymSCg8VOEJAKNM1CJZQ0WZ4VyTOBvudpRn7kdscugIq4QJu
1MKApGHLw3TH834I9RXSPdHhFowK9+VCQATkbZyM9/dxue4KJPPKYg9Pc9yG0QEqsPTLFA3eeBb5
oD8kx1VSn16MB5xz2U80jAchR4L1aLyOra0Y9nZg8+i6Fcs2VpMzngM9O6Tj9eJSXCv2UqjDwxcK
Q9+efuajo3/WU1djteQvKvrj2/oRy45j1vGlXUIAqU/ZbU2FJvXu0D4pdZgJGEbEHAALs7sAzMtf
9MUVwzPwU2emkbB1OBtyvEnEFGzIy8JWMkyuIt6NQ0XVSe84ZPuD/Df502GAh2yJ44KE1l8YYvgo
Hd7PPtgujH28yE4B9h4cFT2JYuXocWh3WUv29bkzjfHG6wTGR2IpTtUWqbtxiwc2v6F1IeR5h2a8
K/bvf/G0HeSpdQ89U9Z1Tmg4ljm2kZGhiH1JXMj9we+vQojZjwYcVQCFU0c+Hje2nLWtXpsDQMf8
/IMVw3aRYRES+dI8iM+3ed1jYwjaa2RlGIuMLn7eUegpmQ9roRqRrfyo7fFwJh6WHdodIckPpQvf
8GLgyfJmiJ54CKN/WjIA2025UR4RUuZ/m93mycBoebN8UCYE6n88Ggr0aCRLxxLxbbRn1Q2JN9xT
rY1I/MAWY3m+N8smDk7zeuB8AwW7ToZDlU2D8nbXx+4VSVGLEikYA4RqmnWOPtymzHenIx1/zBc/
qMXxSYDFlHQpSUHMd5C4yRuMxpprv2MxtHyYnv8I+3zRDG+gz55NRUVW5DvIEmeLGRV1rD4e+G42
t9z9f5kEMKbULNVjl7gHuzhIdORYaYVDSPP/HEX0hsGNNIuKImGYhrEqIGCmq/5CC9pfXsWMZ/KV
7fImzMmJrACl1+K07Uw0n0UudKp/MKLjQxDYXwLsxHphjFi4foYBABt3A8Hp80NZNZQznFnv/eBI
M0fd2MYuZ6lfldBVd66fz1TUxH/U4dzyPi0cpEuEv92pzIV/amRgjKE6UQpdkUXqaW0T5pFRalji
KoXt4Kf/6nA1JhzkSXhA8ryV4zIeB/W2IFjskRe4iqUaHETIp0DtmnmR4AP5Ii7P5JppPANzfcwd
Yy9esEkX5MGCcIS2Auypu/WONJ669YygC5k5X3OQV9Evp0T0yE/Bp4n5PpCw5eh9WVffHLykeetl
uHgL3MkEiBjQKMMSx47COuifSBBcaFhXBHeASY7XZ2DhLdrIWP/Ym12PvhwJSKXgHgGHm//0NLpT
42gvIDXUlrJEw/9zKfO+VFC10zucXpFuE/QgRTSVz1lCr6fqz28C0Qtn2xspoOkEllgdwI5rQAXN
bRDQORYCX2teCHgoL/GvXZVIO7Vkqc049qib8SPKt02s5rc2K9t4TmzhzPNKYsgipraDKLXMf0KY
maH8MWovIUd7ZjWQXCERExW2+H3RzPon4DFQBRzgVuQTpOXBDYYMXTZCfXdCLU3Uq3eVHO7oQ9N5
EsWCEflI9IzBLlEF/y/YJSmhaQcsQYcN6By7mY9hg1YgLwcf3dUhSAOmMe7Azj36zdFGffN+Z0Ty
VFqRbHzF7R8WEKI7Q+kMQ1lZQHbc7MF8Z5TbSQp1rsV1R2RzBp+ZVBSB3C2GAt8N9L7Xe0hS7SKj
nt+/qAnvnNHk7EDjmap7ohATrESHrYYDEEYtPK1mgh/OB0DysFnBQBSEJbzFOrvDHaV/C3w2gZLo
s5Rw8OuTP0hr4PiR7/N6vHOa/JgvVCXqiDX/mz5WH/7UtkMjPwKCbfOLKFHUj7e1PnD8vNlvVCD/
YOk7zf6LbemqwLNUYwN+hP07VxXKWZk02Bg6DQSeOTQZ1dieDCvLTaN4uTFkpp4wvDHbdCQLJaF/
XgD/+XPeTrtJJEBE3uiT6vHq1MaqTOUU/d4D2uq0r+K01j3/lhDWEtFGkrv4QcHS1M6nXV8pRAxw
t456+FPk0r4XeslgjK/eoDy85YTvgcadfZIJn9oW48xkspDj+TRKBEfvYEK7PYttT92FrNEHhHJk
0kuH5HGXNxO725iKNLMIRvTO9s7X5cQ7vhIMvYAPP8HihkItsu6MLZSI1mLbisCzK0rE5gODmUwF
nnty3fuH1t8YF41GA3gQrrqWwTXdSSl7+RYxozbpbhLH9gFTkhbo1ARb5hrJtkWm5T3O0YOUEoPC
ETEeDd0mHukmhq9g/7ORnTNvD3/4ZukRcOKA8bFvKtqK1CMALi2bsizjQ7JOLSEqKmjwyWer1vcx
eIQlbCQzLSpTWuKuaW+FKMrhXXmCq6NnH1e5WYbs6B9V9S2d6132y7QYa9h9EDZ+t+H+31cpfRkm
/xDJqdkBFqZD4RYpzqaRmfaTXzZzqhjlClULx77nSixfQeYQEFVK5fhv14L+jLOmFxJQPxAgubsO
LQyYSyAhlDLyhEojpT5F8QPkYRq15nlunwwxucLjSJbErxPqRl5r5kPrswE2NwmRR0TT/f/ZaLJl
SmSktJ6R+jMk+bzRVfzn9ys0bORbwNztjvLlP0ELQiRV9qrGw5Hz1e2Ye4Gu13S9UQXxK7wPt/lp
TNRZbZcoT57T43B6tdVKdDOeDt8AEmbxebROv3CE0gd6CsskCDrOaJ8lp0I+NxvYNlg49p5qffDz
ErGdesoMTO80Mw9nXrEuCXq9iq8ScH/qfUZD6/jkxfn/LXbp24yTw3k13LpghPDl23MFSKtNjV26
dpzJTM1EgiMbuy2KMF5ctBj6O3YihBZOsYrMJrzQBIeijRAcpcXNai9GgWsc36PXvaPzahV5wZqa
BNmfSaWScXNG9fV8AHRAaqBbjoZ9oPyzLVCALoFGnJcuYR1Ic341cCKSk3RYezCJI1DSkmKA18ZY
pKy73PFL8+TGAqwB+lbIciKChC0ViAs06Ppr45mO5uxlsAPRaMcAmHhoZgFh+Razq8L82Vjb8tKM
MeRbeOTefpx6YL+s8M+dW+HPh3lzT8wv7OlClovFPfFt7pJMGfz0jMWk9UftCykdv8JLGhPIsxon
Olu9SlMifSeBnr23LcVsYocV/Ee+yhClH87AKsKUWVUIDX/agviFPNtYyOWlpDf2fwxx6HiXLgU5
0QcSWzVWli4XglqGiIrZbLYIScTXvj7PoAuUuDdATaJ7NHtfE1zkl3WgY5fsqSO8MflWwEqYEfUJ
+c9GmQY+5FDST+6lBXjvURgJsghtjEC6ENsiOtKZk9wqITLQVCI6+4J09a7eov1R4ymg2JpdaALA
z+hUjtRjImoURBlXvttJGWC6v2ITlDuj4l3/5+QOdxe70k7eQLcxj4B7yHCPYEkC2eWhWRMWMmds
BhXq7VouOGrA2bXtELjnXoVImTQJBN4/zjZnDCSPfc2JJucnoXED3TRPgqEMR/hwHX2HTVoh0BEE
Iwhx/65eMU6r1M4GytOdUIHzckyoS8LNMSOfrEPKha/cKal/s0JbW7bM8fCQ55SUu3Rekn/FtOB0
h6oWvS5F8y6kbr1dKw8jgI5NZKnWCRN8HHnFucjNeENl4GX8SPR3qewVI2ZOkLVl+clSwDchob7U
c5loRWzb8UIFYzG45W1kJzB6njbuBkgHBuZtWk2yGHS7Y+bxKdC0gZSb6dj6EfhWTwDs1eBJCzzb
s1A221XNM+XcsHOm6XEIuVzK8vpvZ4rgSGqfTo2Dvb2U0c+44i7NTXxFjF0KfiB/FeOSdBqId8/o
HEFffV14llmpgyy7O3/CFJlhOhYdMK7+8zuC9koDpw6zqbC1TOx4+9OqyxBWQETz65/1nSh7eoq3
/pxknZxEsJQx1jbdfU2Zq3JOzOAy/s3wmvqTZAidPXcpCwBaOu/ewh3O7Ro37ypQ502Dpsn7zQMW
hoW3wYUfFqapXusSebtDW2VE9rloVHidF0+tkxMx/ps20uw6Fx8dyroMUbhiVfzUX2WT3wbVCNC8
jax4np+J3YoKkYbAOzY+CJsH/UWd0fh9TW6ONVqn9MtBwGaIe1kd9PnYTgaTnKnQ/Gjie54RtCwM
LVO5n5qDzmef1RiFXlZdH3JAv4UDp40CeoMeY6VeBhkJMyndtgrwmKHyFGEV5b/i7CVOUiQdSoH6
487y/rxDJCnmiPHvL3amD/iI3OQlhaPgBwmyeLMspFHyOQ29QY97Tx1T76b7OWXkuvhnlTUBNP2n
XFn2Z4jin7eglBKTmAHIf9bt0VIbTPzeVS0DBTgHQhtYca0sT9VqOT+c4pMGb+MN2Q2o76Xf4bug
TVgRvqMjfFuyjdWMQAchk5B72elD3aiFP9MjkfVtW12FbWQ3CQ4gmP3/KSA8fiOp84YAmEVXaiLl
l9xgjHrucFdfJVIZBelI/zTg+5pRh2bOPkDS1Bf3aLoBd9Cf3w8ERKNqvlP5rWsfgehBqdfkWJOv
ru7bM1HuAUzZhf+tqYFixJWcBaeAckRM8XjTF8YvSpiSBjyrZNIae44w0GjChspFYw8kJvTo06In
p79R4ZOYcElATQFHEdYvVHkLYWd16QOtilCJ9Mr2Q1JcjoY9yvMz/XDce9rAC9i7yXP00KzEfYHJ
3ehQWb3AtGwOvWA5Jv9ad+DenSISffPjiq+SgUl3a+JAmnKvYWuOKm6xnj0n+eb1QQf8i7oZ9RDh
hZPy5ulrxLKuzK+7SzwMLUg+ACpw8P0SyiEapVewXcVcaQr7u36RPyIdIey2M7u2zIiP53/UEB6S
jvXEnxpK7LZ9nvNMXXSdAHdxl9bXByUQOmKiWwYn0T80Tv1p6kyk/w7JidXnEc/V0+RGZTArDGQc
Q27wM4nqHXjWz7fSkWfrdD9lvZ1BGrTEIFgWmhQ/OWqTqw4dLO3+d8PuD3Nk/Knfq/flzwV/mccc
6GoGfHZr/k3nGdn+hBICpo0JAJ6Rb1KEiS8a+u7Xy2wF4cT6Gtq9v5Tu6fIIFuv8XLwqgh9G+EJg
4Og27wAZUTxCzx4OxMmHkWiYewuUTIs0UK7gEtqaBGxIaAWfplBEUZLR6+5q98gFm5PZ+q43y0GO
Bl96+sr5mA94TvkOI+hrHPWY84yUq5XgWytSE//hz7TFWbFl6Zy2zhPQ1UAGNMkeynsiLm4GFmhK
QaRaQdORjAuuEryNVacsDTNL32TMw5uv7QMt7Qo4PgfZNRx+3vF1NCX/FSSEibVGpNQ2gMWRZ5uP
7KwMP8o+XJU9S3IQfg8d5EUmpwn0C/LbXVGffvYMn/HLaLBlHL/QYPgXYrBx5yTKiwDRx9r1UPAo
5hetK/8GD77dfsWYF698UFb8H1gzJCa7ey7RztVVVFiusKjXpj907oX4KTKnpPTcNbX55MqqMpo8
E97MhSUzs0Wl6zebSTGOUAjxodbYr4DTuE+buhzaIiH8uyv7AqL4LgW6j5PGzZOhlWGHT+T0WBnv
ii2D2mmeZ6lBidO4+wrO74NgVMnia6LOG5h2uZ5YiyFdoBWlZI8NV1fQ3Fy/lb5RmwmCTC71BSmh
ouJ/H8vQrGe1dHYiZLhsqtOreLOMUf6ujMLsGlHTe0CidFLiT4OcOBGGXEMB48Ju/XK8NzahTUDp
LkbdddpbebhCl/rqFqf6NDP8cAHvRVRlJA3QwhagjWGJDpOKEqJtRnvf27nU31gP8CcH8y1ytyhb
nF2q0gvPguTj/Zi6mEBcqph1dkymsGha6QiFsk7qHW+R3tcCafHAvQmTJ88ER91A1qTjiBaWVQsU
st3zKSIZoZhDIHmrcFpCmriq7Va6sCp/WCGHRC0pbpoCOA2KZGXSqtWlfHeWh1tplolqVR6SBAr5
oPEtFednabiSeHkD4RzPqGJdcixZETFtxHK7pumGwQIbotG8LRHGcYBL5nPob+SufzcMo3yTkmX/
uVKB/tUzL4uUwQ98jzjCQnJwMljRs4S7C6S4v4DnFu/i0My/oj1TRdw4f7BsO+22+WHbJ8LMNG8m
5yyim++YCJU3Jh9SSgZ+GqEmm9AzMwS3zZJoPKZCHmwarLwWmVFMvYHaAKEflXcSs3TZrOou/SUq
U1+wO4nqxXZuH4iVR7ivVcgHnr9y+0BzXPz3z97T/PW3UO2BqGB8QwokiuVX3fGwxqejIHYUeuUf
SK7kwpBcwa81zpeRVKpaDxSMPtlnL2oKLKWwgjGOj2Wso1zCGfpf1oLDeiJ220Zj0KSNYWaGt97K
hOrO3m3NvJWLEIXJvpWzgR4Mq46OldDSb7tAI5EUa8zAWf4BCcjs8H97pTTCFZvVD3lUCjsJgawQ
UMzMY4xS8mDvB0XNlOgh6rnyzAqam7yafmY9FDZ3/yKMM6m1cKU6CvEJ6oSlMwO/qZdwi3s5ORfV
rLRa1o+fMDbdb3MjSSjfkl8bgYjQainh0kvsSQV8JrtkfF4D6jr1Sq0DvbeAYLMtZbdAPpZ+WubB
BABYB6AAW865vZPds587qT/w7S0z8RssvzqwgaYXZxk5qUjo6q5UMA0KYDDXXqzOMLNaEPzb2XW5
KOHeY5nLr5AeNDIafO29C14afrW3TrCrRdlv3M/iIYbTEpK29blRdEip5Q/wVxzEeudf6M4yCO0Q
7EHpcsrKl8v7SICusG5ewQu7AfBCcPOMzjOFV3rrR5K7x6IZg9y2JD+s/nmZMnCc5lvB0QY8/s01
bOgLIOu4GfVK/uqdm6swbObT78wIsHhI0bn8C1wfzhx/jfC3/UO3J1L98HfvEvKULJVIzDxxYLoV
BTX/THPokHYEDTTdkmj+NJyomk1ATri/+l6xzTEPnjfiHMCccgSv2aYG8dWF7xbRtxoqm3wXGIdT
lYb7ZZwGmOPz4X2CigYUrTYK1aZ2b0Gtsi7cxlFLVM9fw4fnPw9Jdnq5n0kSA2emiYFKxrb9nPiI
P4ITsHtrkMdW0XS4XKeClCfZV/m12YpdTUrGBuY6woNrOhn/c4JUSeNvWErBmXiV1p3o2/6sXgBU
fI8mtnlU+YgQFO6ROFDvKWb7ismvgbTmGjMd9pYKf9D4YzNE4n7lkwYpWIM5KmFeSWs2mG6apkGh
SUq2hRa9BRsXNuu9t6mnGOxAoe8t0vXNZDdrw8poytgALFtkBl8/+GLxN3dkuvs4wEjEudMz7fE7
SoTYyd7MWAmXAEN1E59BGwI3SMgqN6XAIPHe1376blpPBT0OfxXOpHBrX8+LDbIs0qoTKVc/0b/3
8KS9CbMnh1KRr3XWyU0gCpbT9qnGU/m6rvlpNJPHi4XiEygTk4zoKQP3/nqewxRFy5/v1yhbQmvK
CeAMllnL7m8SVMqwBTCIYEgw+N3H/JwvFiatu4Grq0gRQI5Dttb4/NYRKQytNRklJ1HrccZMej5n
GiV26Mst01u0JgNbc4yVcc+cU72zHsKbuaoimh3NFFwBCbGLLO+1epzJWtDw5l4gKng8PvuFkuEC
EsNYwjlVYk3ZPCzpJI2hxNKPFPzBurF+zn11zDEqTfl0f7LUUv2Qp6TjiEf+oxqIWRuPcqOV259r
9Y/h39A5/RCU5cCMrJWteYi75v4PmFvKDk2phc6MLflS3QdKwiv1C22qeG7B+O3CWT2HQ3ic/VyX
2ewUkqNuSurGqR+EhBoSy48dLvcY0M2HiLfB3HeQYHV/A6bsXNubvHr6GC22hT/S8e12BGuIfe67
32yY2BLUUG0uPNRBBiqTakfMpKFDbsXi3uwta9iBe1VG0AonY7UH8jFyCLzphhcn+oUa/E6klT08
R0pn0jbVAftb2iubL/SQmsnRXy8rGOv749dh5Xo/zCGXldkcQ84026dmREfSTpPen5BrNS39ARBr
CjRsvhG40J13qwF/ja0zE+6yQ16M4NjMl9JA3NHc8doaJkEOq30ZSgUGCx4gIRHRKsgODJ+qmT3z
9LxsZK2N82ALqhRLoj48Kax7+ATpKWbeVqTfHGyXGfGfm/2vU6C9ORJPD9eVdFk6YkwyyRACvfjf
0hUCdDaAsJqhDN7lDKojhUZ5qt/b/YODvsGoxRy2lfIB4OvnmlBfswPAj4P/4SZ3cR7xA3kh561H
bG2KbFd9X5qN6SJX+5ukb6YZyTlFX7/eptbv+etklJe0799sMPStujMgcer+rWOelCKg3vJnICDK
5WsFTHfn1QgYMe8ynbmZZK1tVYYpbAjzP7k8xt1P1HajO6H7BfaB2dwsv1MsyTZS+USCGxW1auxS
udx9IWjmtkLzcivquzIotwzWAeVr0djuS1i7U3PQxHTrbw6arvIRS58Q3+xtKUdEI9MYbY9MwHeL
5R1Dl4CLlPmz6zqqfBXERgeC6Le1GDhQF9WfKv0PsNtdQduPVvJe5kw4lNtjeRLIEAxdsMTssya4
yldF7fJrv54vgmtzj9pjtb0qhTox6itcL/yU7KCJqoGILkdwL9C3GgP7t8/aOjTjOe4P9bpnCa/V
zLC2whDqrmdZJsjSD3Oac5q8rsq00KkxBxxxFKa7wOslZl66JxHIyaqowoITfVFH5VeeKsK/eNl7
/q/ddff4cHXpM2+dwy4Py3TGK5Gi0HJer1Dq4TRbKh3rrAA8TQfi1m4x61lhtLqXcOGnDaPw6wA1
ogoAJ8ZmAcuzK1keArQOAWRxNWTyHFCIiuC2bI97rhtI9OEWGTWlZTs/i9EczwnK/X24HRpEjT/h
QxF+r35cBOGO0AHUI26KXsa7MTx28JYZDJQ3McfECt9vnV2x9W6B4gnksoSZcvFh8vcO9/4Iuzxy
bTBcsnMSQ3N9rG/UzxxRMUvHgcgu7SzcT7thF82jQ9dAjM1bx6XP5vATVhLSZI7rZNYwXo0o9Uzp
V1YfsHpTk9rixibiC/LwKoNFOAyKTfwifKJe9dqxAd+0Gu+lRyCwdabjTEjB3LVTLHqnSuzpXSUW
yZBVwJH1sMZlpbKOmgtQUBZGqdc5GTz6vqa4K/pY6kHQvNgLE4yaLzvPGQJNZHzLez28VdCQvazL
yNgj8XJfQ3Ope7vGk61BCcOuWFrU14qR5HlHXsnDn3KTMin4dfbW4R20lYMmpREqWfUuu0TfzOmQ
D3QbWzuLAY/ASkEyGB7l1AeLz49opNNW3QaESRCA/SxyMBWmnR2wgVPevHadPITLjRdFgrUGAN7s
WZOottKqpTIE9rrY7GPGWZmNDru/pSjgz+v1MqV7qebnB4pjSy6ZErTzKBvXIVbC39U4tY7X8mER
JJFjPmoz6h8S48Ejr7osi/wKuuKrlsdSWSUbi9kAnKuw1BNlSaHImBg8GWXenAIDROdVAdoLjDuK
IdBT05pHEdfZvE0kVdfAZAWXICs5ukxZ83BbzRf4tCgj7WM+8GAiVnUhBs/HyHMpSGWjPsSVVwHP
pVNTyLroiGtUt4nKZeiPCrSTD6eM3n6ktTqTpU/DFM9cAH7/p5QX8d3Lck6/2OwmksDx73nxreOe
4nrLQYiOW9nFs/ZyPXsnj0eMSYrK4oRdrO8VNIhwP2ojC3WtZcvsgy2hpUL4hISMMA+VSPk8HBSy
URLgAC3tMDDrIfvh1J3IUAD2Z/PRia9NcsRdcQxSA+CQdWo7Yw7FSQs3+DhuOVWNCCdsXADvuFjs
E01pGCU1FhQM2Y8UVA0VU94CDL96JtiXzag5emBqzz/5icYQaIzHCilkH1FtStqGXWIrJI6beeWB
G5HJSkSw5v7JL40bP32fayyXxUrUY6/L6fqeD+vjaKrbXGQjdaMPgBzq/oYTLMsyt4R8wCya7czZ
odDr8o4EBgC7UvRATmzx1xSfZBWqyIFVC/TKZTFsXbAy9mkdHvnRJVrfE9WsM7AnE0pD5vwlU7N4
6XdgACb7VHne3KbUN6UkMTEld0kV+ekxZxliV8lGj8nrgN2XF2WYgKzoGP48W1u55Uj03D+H0eDT
yjNmc+Sb0+T2vFbwGmAhav3hiX5dhwUvKSC2CHo0XJymaxRnvOSf/YFqLeSEJX5zw13XZM0QIciG
i6Ba9hqXHA8eGUckajctPoP3sm9uy5RGkRcIuVAeB/cIFtYiSauiteavMj5+rvRxOs6M8Edh9kmp
OyJ2MiR1VKVHQV4zbfuJHCOx0/xvwW31gWbQD4vRqF+u3MKsdZiJYmARRsSWXK7HcfYV/vIzgCch
htSNshYMl8wPuNFZ8TThy9U9LTt3OxnYqXTKR1s1licCRt6lf5KXlBABwj+nchgz0SSh4i629cFb
4jjepDfzu4DD6Q/w1CJzNFqkYIkYLvk6canc6CtjvmnNGWpFvGuZDO4bIamcIM/mzy7/TKPggGOX
/vuWHudrhPGMcAw9H+ExJKoMZyGSCrPwTCJtEWyel/YjmoXEGzOprPAUyrr6hc9B9GGoYhyOC7hz
HrYF6Ck314tGqagGz4M/n6zrbzE6jc6P0eSS/u1txxHuDFrfcU91nQeU8jD4BfElYSp+ByDJLvsK
MTFObTVN23T4+m1qcv23llm9/9F/nWM0CNMmZDk1bB2u3FO1/hXH0e3t+Y9iKxtgLFlkPue0Pw13
6ASe1Pl2Mf13krXRLViT/v2QGF64V2I0BWNnD5ES/rZoALMYXNUA24iabVZkvyqZN9HdiEs8TC/R
kun/q/iTOQ2ybtyRHC5443uAKvMSPppeYXIib8z6RjbjXYK+d8t9Odih9ADqhZf/4CO4JHUeDIL9
E+kU9NARxswCjuSz/PKaXBdS62VTHmWDLHwX8BrccfkcoWmfmBcraZZesreLWfv6V4Wboa/LRCBA
HdE8kUrrPqVtNBTnBGoO2ANzHGH2y00lP4oUj4g0jBQoCUyXgfAZd5AhP/TraLrgJAwTnEpNXINE
nX2RBu9WKww/ZsBWSaOwM/reu6+B3zDYBD/PWojaLBVKO0sRwveOP6w/mTlCngOA36/mt+XdDuLe
/3ZsOT2qE/E2PaxRJTs0VFXCpoMr8Y3FeqvUZZO1YdZco5pMYNkOJLfRckTtCNfcXtsudNL0cVJI
lnZQj21Lw1ajn897ttf8XUUtyaqKcAJN0EKZ9gpZYMqEzqS9VuGvP4lXY8hrav24mFK7623L0HmX
O6jObYwiZ082R6d2ZUiE+MFZ6uyuVkssCAAsIf6GS5dO7VvvDUh0WSqi3wuzp0QO9j382WEH14Qu
bSii7cHido91llVQCU5pyrzwL0TYxlNt0Oxm6F1IXXEHHMxGAsPLebkyL5FTHgPhh3qnGb9NFP7r
oJu5Wz3fqL8It7pezLaRbI86XCjR7BUeqt/YnAHT5o/RQ6ss8F2/Rc/I/Ef23BotuyKTLhL5eSQ8
n1hBWsB0pUnlbAW1a5Pu0QQ5QF25oEXDV3vaoSQ4gN773AEGljDqb39hwrGf89ysHOD0s5DfzZZn
6YpvZczC+CVPoWqiexAaIGpCb32pDG4Lwsu8O6l6iMb/SjLlX+EDbBfqVgIKSb/wr4Bn9TewUgCK
AyxZv4oL3rqbyswbbTC7JzB+3KetIIxmZyyR2MqKp2ZSJLMOQa2wOg43eSBQKWLXCQUgFTUwmL9V
0hrBJkAF/TEJVeCbLBoIJs3VsIzU1fKdscJCwEBkL64BcLjf88NWL7/DgBuY56EcNuSbq0YpUNob
TqaRvvDy6obkPB++tl8MEUvQ7HqNYwaABxdXF+2AQn0qHhwdmVhUBl5ZljGsIbCdpEGaNIoK5rPY
cDZKPY3JKYZ7/EB1EBuwYEuOlSdtkAIJwyVNSbuwFIgHwWBLqUeS9CUylZC7A23F720SPKsq0kb4
hFZNpTBmpVGAe6Zg7eEDXh/47q9ug5bFQ6O1Rzb0lU8L9Xef1R9zyKwlv78SdnMcSyUBW2CFgw58
G6041qyCZSeP+yOSbPtRxRYAyxaK9Q+91X05AoFrBhLwjX9zwOx2Og3kfBYAoGxuYtoivuuEyb4O
E+QCdrFUYg/IDzfnH0Y8OhhwMN3z3ZXLhns3O+XmnY6S/UiwWzFO48IVoJl5nzG19i5f2sPZxJyK
JDv27e4D5G9lzIqdEI7Pr1gw4Z0NNoEjnYH/YnqdHpIuyc2l0dn18+xGladMBxhZBXvBd+OdC5Nr
dVyrrCo73rchyxyNQOgNaDt7NCuBHnjbA5woNLdQXnITWc2inmOX1LcoV5hdu3Fu9ipri+awHgdv
Gh/M/XK9tFXe9e/Czc3zft3n/QS5WOZG6+qRC+5AfUVygXbLMFITz8V0o4RS0ud8TW/EZRYv99un
UrTWjWmI5QvZk1jDa+qqHxpQtcoW1HwACJN7VMGNQfp1AvnfTYjvEKmpqyCPVC1zyZTOv0LgDCkH
GqKsLUdlhnG152OlXF0uRjRpQtzmekLuJXUIuzhoj7cOya/BSVzFTCnLyyOdU3m+KIzl0lc9PQkM
6aVp+L+cBVdT67Z4YuiVh6JyVjjMUjsMDdk+C6+lA1dbge1MXZP7wW6XWwaiPnkj4n5Oh2x/eBGA
/WCLduN+nw1UyvmJ19VS4f8Oj5S9iFtE2tWPmQ/XmFwUhf/9w48viTcwM8u8Riih7/5YXAcvOp84
tyJEOPwaA2KuaBN2YDGaoYVZVIgDFz5y5NYiUnNgfnhLmkp9Qzw8lvmbabAhjJUEhC23cEnUDh9k
GpYX0w60160cQHKO/Nqtr/gZAT1mUGCEGevlLG29B9iw4dB9RlQK+Pa0RmMHUDgGEEdbpKMIlMP6
bjzNhcwctnE/bQyBDyeqRwE+DQ4oBiB7zTGUquKCVDVHiTX/lhlu66qSpD9gflA7tsotYOQKnydW
CDK4FlXb1AgjGQO7llYC6otfF61WMSwu9h+WGZYXZlua7fn2IjIOLiOz5GTGMqePkV/5qpLOvp73
lbuZP7xVR460EqK7ziLg7UmHcTntfmWUW+slmpBQzv6KPQrToHJOVz5HPw2AXJXJCFuF9M5ZEjD1
zVxVPb5B/iOZXdyFPZRHC+6bGInQBrOO/LGYIYyVsXiq9RXvrK9EQSHpbcurpgyqSlwKq6wPIOPg
c4mk2rvhffgtfMVtYWz3FFOC1hWd0qwC7IcN8iGcIT2NuiQWiG2c05ALLraQskCOBzSpMuyV2IKq
zALcRGBreCUX16q2axIpvyIhmrRdBnbyxF3t3l9Q5PVL5GRgyZ8Q6ucEvGhv/mX3KMrf7Sk1YnMQ
5q14Mcb9gDixv9YLp5zQZ01yCFSLZU+dpUDQ6jkAVGqLGJIqyqEO2DAO3gUjfpQs5ot8/aZiJwO5
PwL0/IK0TVgkywyVMtxV5uph9mHY7202bSKyhb75z8eatgK1y7tS/jGH9pLz1oyrROH6TYt48gGW
l+OaDUQSixNOEg5ra/8PlHFq3tHfiEmX2pOyaS4DqJ1HnkuGhRjMr5e1Jvnly+ZnhFqafaQubSU9
77iPmuVTl/VpKSi54pWjAB9fnMu8a+w1wzE5hllTLmEnVCw9OzGn0VUO+jMvQ8M7qJS5GhQWwejj
NsyltW2rwaekwUzbJhsYlOrwmBX4czsc7b+KLnEZrloZGQ+SXpdDdNDlK/SmHVV7CRVfmotOeUXg
eQIsOaEuZGRle5ahsU3fsLTqPe6KO//SIZgsQiWrTQboulOzaOvtpni3XWQt2c6hbwBSa2oP+Wzq
8UNM8/pCY6WYxbitKK4wdr+PBvMbJFZfDP+A3lanmEoDS6BjEEFt+lsB1hG1AulDuDpN9ilYLGqT
BIGKFXL+4/joUvoochRUUD7LmfRoBh2LbTo7KXL2QHymrWTFgbzXaVZg1/xKzGN6AaXcuh8StCGA
a+zu/hL6bqLItLUlC2bg2OfZZIwoYsL0UrzIvtOYEwb/AcGaOvsUOv5+2mDIbdENzSi1d05cFmUf
BRkrzNulr/IV0pNG9qHJrLZf6OcWZ2e0WP2EbRlYOYQaqEU0xYhEIZ7QEldYAyMEybpUsVxq9iCN
TaFf/ZRxkKvy5BEdv8O7BWz9uqlAWTIoRjeD9Ue2ooQiEUefOZ5m0NYj8q9xuicH6P2Ol6JwgVsj
yDwYCcgIjPx725xHnOFpkg8TKtbUKZX2ft3sR5EljK9k4LN+95LvePMjvg3MZu/n3PyeHlbkjJAi
yxFiOLc/m3zTL4FR44y/sO7NtWJpmRfMKsLs7Dqe9EF3sKaxDAm1abPLCii0ECaKPcFsUMC3ALVi
A28GLDmif9XSJ2QOa0Fv3KX3e0IV1q0Qhf/QX4cnhx1VzX8vyXZ+t6ukBqqV4kfXim3RFpIKBcWc
HmySucnAyQrcjvn+qDlsNdAfprHGsJnl2Ib6Y3NLF6taUcxWkYlHExaUpY1KW+qjVGiuoKw0cpcT
KGQBoRq4C+I/lYMMozCynr2bmE3P2hMHZWc1XsFw6WIcr9EBjtCY2j3ySetRwnZ74U9peyt1gpQ5
BJ97Ipa+Qj7DRF5ozE1Ccn9SjFpP32/HNklRQill2m6Yl7taUyEOewExUCzi2arNIQDFsY/a3sf2
OieNeAIAvbbBcF8GJaAR2uAPoqiSeyHqanv6oko4bxx8BU/ZVh3tHDCWo6j1nMJn82eL5LwR/6OE
5RHJ4nB0NZTkrvTu/D3VV9wSJRv4nQAFkY7Rcd6V4ApHTVX0AnqeNU7NaviIbQXHdzTfo27DvJ32
rnTJsUvI7gthOi3qxzWTVpIYT1cutUdtnvWVDF3uj7fS48wjFfqJ+/QYOTeVBHGZU36mhw0KGkLs
3Efsgs0VMTbh9PqlHVd/OFf06tVgrIMm9/4n0GW8yttW65aP8uvQ7199/lLVW1AWjwJsbiqef8Uc
ewwJ4vVXfPUnOwistIVrzS6Yxmf/wuNBRtfSloZvxUjN7D0jmzpBxwuUqmf72LliEvBr5YW4KXfm
rZ1JjqfVSBAvXdENXPGXauDzDjVIgIJUEKttuobn4WymfqVuyQIWwiNhSRw20yOLLuKPjdRMXOmI
r2LDvGRP93uDsjFP/q32mLsXbleyPhqplDZljZm1MHdbt/7iu9YQWoIocc/5mxUYn+QqSCk4pAvc
xDgMpqADZ5cNcagnEG4I6w64waID3knc9d5rQ4m0UsS3uXmuaBl0nWDqR0rHgm8OdR8wJogAup3b
tK2kyK8snOhGn6VgR7ilOmjWlYSa8j4IBHV8kr04cf3QqeY97Jc+gFMm+UspnikklhbZQHdzydRb
+HDwx8ynxTWhwnew7JrysSUvJAbUpQMcXSWWY9L79SsN7uqCtQh8YRpjRCCpNPIRj56rdHb9tOrc
1JoBQu8Xz04hZ0kiwkwmioiNfbN03NHDiTdS+n/wkutP4uBQ9SloYfwB8qxo3dQlujfMZKV5eEix
i64De7vjfpUxPIeKBQlVlWSl9rXrnIb1fOTSt7N3jqOyIVRRQRI7x+4Y88nmkLJ8mLK7ETSp11pE
VWVA3x1f4go5ETXNScuFqDFFO8s4CUCAHbDulOSQeNF5zs88natifJObBI5iPSqqVKquvyRWo92f
py9hceUlzwZnXzlQFQ6E4rxbcffdzdgYDoc7aV39uFZTQ96QSMntusxhiUEv0NKcaIZ338nWmawi
6X4FUxS2MzVCId18kiHfisKqCazcHTma57xz+55buo9P+lQwBMgoeY0rjtUwRlYhJjfD9HTKu42D
z26+QgApYYBWH/h2aY1zElTRlrZa7qZYw/aEITtcVqvwqwudvzN/BUENAH6GQK28TnBAi49oPib+
z/ZM51GnFi4Mt3j37VW5X4MIEOhz8PKv5Y3dFMcA1RCic3QNrvL4nglFXpzNidzL0iaEFa8TGetm
B4TzRMaRTcKhOi8j6un7m0xpNadFQ4LpASzsIi1isf8pRfqm3DFG7pLSlCedNRCBnGMF3BDQqmuF
UKS4spCpEz5MHuNaS+cnJ70uM28pgr2KxtfQabY7bfR5bEWcT7+T/Qij2cxlPPgwVFbPq2DyzMhf
YHj64SgtmH60Np14h4LmoceIHWdpbQkMfD9kcgPcDxvG+ffkj5NtwfD97it0toDSMA4HyV/ecI4O
D194wZssPA5+EU3VvjRscS8zo0RCJBUNF6/I6yqWmXiaqMAeXrKI1J1ugAoEMk4uBK471VeszGkr
7NlqW5m67HkSggVy7y9Fv1nh/rFy7VYhJrVDMzRv9DJcTlLz9zSEtQN01P+SAcUtwoimiPHhwdwC
QEw8Sd8sLQ+Dy69OkSOTdUOJvo/VkB9wQrCw+OgbM21bDaToALAhPWDDVxNK7t23Mq46SoRRZkMM
Y1LyMM+JwEHrgMBKYzLkbZ1wV8NxWxmBadaLeQ12YFDlZgg37RAMHX3unHJu/f2WTJTBY7P/cp1X
rSnAlq2wo4TscdfTJNxU283ijnNRjnUVOgpGqc/BQGs2/LJV2ACJwD5QIIuT36IXk6px4fEHfSk/
DtqroZY9VOwsHMDZv7gDIvFe0yWhlWRPPA8ykeZcZrELQ93O5v8Rartcpua/99BXHTqV/kvCif1H
++gaMoelktEIm8GslZeBbSky+xASyihJ/h8gu9MQ+V6y+HCBfwphjGA2d9w9JDeygeZxvbGGQqXP
Vwd5Q78MFBKlkTqe+og0vdCMfcM/b8hLaYsbycTxOn0l8mHefly7iliS3C5AE5oIb5Ed2xO23QPA
GzdVUAknDrFj2GPhMzx8WBjTxCZ5Ap08iZi1aY9LVEXVZaUYfj0HLRAQKDV87GIB94q77i0vVJS1
d9b4qR4nMZBmZcFjAPuJbeMRpJM6ZOZhVhBTD+v4tGHy+4SCPeV2J8//+qmFlYjBvSLl1SwTof5a
DhwqNg1o28OZRlkzRFimZ8ttUzqQlCJVf1p9ZdB2TWXlqe9xb9r0SaBPUbHF6NeI986hNdnwp0+d
pLqc+tUvQktra7SvyCsu5CGHrklIM1r+TOykT6GKip8FA/JZIOOYPuyKmpHMaTfUYgDIgugpGgDe
QmVDWVKCWxwmdbDKe/glgckrAKu/YmLQiM7ZqL/qAa0gpKq6HPCFAsXEeiUsggBPsgznQKgyX6sM
Ycc8h4KPLcqr5lblW4s1mYlEgpvBeJ4ADxhD0bjWRLNRfJ4k8TDnOSgxL1dPL5wZgnf9LVhUTN2R
QExfU6fshawYmNE6XZUEl6rOKileie8DZcAMmlBkMLcyzoq9ifoimIz3i6YD1dBuA8PLjyNgBNYp
8fYB/Y7XnR9OjZ93LnymwICZx5KlFx/V8JHW2BojwyBzU5lGjlILPu+8y9ajwtmoo+ppo3/yCB4c
rIwesXYQF7LDMtvJYbyMRYyuVKk278L4mCnNmtkQe9NYkdglztpwfow0T5F8RgciiiLE557mLm4S
rBa4K9ZOOPEua63hW8Ty5O4U490goeaoTyjiKwZEKBnTqslB+xz9yJCMLdAAmyRIl1xYNoB9Uc/u
uIoSRmHebXlpRMGz9M+am6iNw5eKDmxZZd5nABJCkP5Gq+Ds2AiFwFIxb4dPwzou30ctiaIFxiwq
FrpfpA2Qdn+46eb+R7rCdWhXM1jD0fb7ZD6mMkd8j7Cf4zNsqi9CUZfhqu7BrHiDoFK0vkXqrqRx
JZSxRBdpq5V2y3mz6LXwP77dFHMseE1LeY8ei3e5u2jzxUsH3NGFcaF4+EoKFIbk9+/T8oBolHFb
C3Fi85qinGLVIapPSez45Ff1ZoSvu5flGYsUN1QtiVcBTVaCTxajOL96JO1Keaso+I+Sk8E6YJco
Xxtzzen571a9X++JaumOMKcy9AQJpSJE1PuPiBIXaccyK7Z+NJy6ptgu7kzDYWqZVEqp75jLKstF
D3465baAfBZL0OqSEVD6gfkWu23iYnCdnYcXMFCAOJWBoEsGp6SXgvsHav1Ybd1ZhbGac1f7QiQr
nXjNHH3lMMpiNyhSnqZ7hjqkLzOsPHWFKI9Ep20NBRbwXoLx4OvJVs0Y1lTPW2nuR5CdcsCJAaXX
t/A/RZS3Xzz8ddYfScWwcSqGY1X4VOGHR1dC3vDQ8mUtPw0caOP4Lq6EWOdHICdIV0DDCvlzZH08
iarxUc8pjB7lrz7Nq6QL2jDl25UuK0uwZar8b1dcKWDhtvxn5IGcIxm8bG4d8g3y1EvnvrdIqk/p
hlhPM6j4ZLgvBS/mO7WWzqgGQsKirw70bY2PyEoS/BWVfwNlzGxJ7sYWOA2ir159ksBay2j3OUlG
NMvhbggI1PomkPqtpswz8B4YHmO72JW9T8I0NwLt6uW1GuDzq3sVMgqs1CX34i7FHs+209eVDmpI
LsXR9nhO1VicHB4mYLTqeTNQ9PVHzeKNKHZbwUD9Eh+BS4Tn1XtNKXdOd8OPvH8yvFHlPYPhh0ie
lzr90kA6UyKwlLI5R0xj/aULkFdWdSL+hVbn3Jp8aS52tQ0XZLnHUPWgV0DD6Zop+2vmFGKLJ6gW
7j7b54Itzc6H7LFJUeW/ggP32+rhvkRU0zZy7zQlHOj20IWMayJ2Hu7C3RsT/hK9AP27kQxz+4Pc
40psHu73XiiSQ3U8WYd9AAL1Gmzl04n2ZFQpAYi24oOi4UhncfQKVxInEqJIkEChMHmoGq7ajtoD
iVxDH6oZYlBEroJaZcpqFvFLMqBCHaod4Xg6wRe2uIjSIdbARumILk5yquKhy0E68hwzHT6CQLNT
i7VVDrXFBBTaEzN4Eq9KBA/mi4E+v1IvQ9b/QSWYbw35TNCB187T4ZuE+zMObt+wq40JELIRo4f4
72SIKVIm/oxj8jjA6mS6TF2K5tVY5yQdGpO3NtAuzLhkYtmpkt5/oLsMZ+2HUa1DnsvVoYA1UQYW
GzLYrKhimrP9PFwCsJ2VKF68mmmQ1WWyuqEheXl8QrnwMj/Sufz0rVR1i/HLseFEpYn8wf3AhRH0
wdAM2EKSPmllN8hCjsZu4o5csFy71GJKEzE+sXdQF0iThpA5InE7XTQbKJ2CO+084XkM8PxV6OiR
xE9CDtTL4Tc4Z1U53z/fxUo/cHunZ19+Z2jyI4j5b8WCHmmix/dp8/EVZwlOEgAy0EAqsHlQ9xtc
6Tst85Hyx/1vezHz0b64l9Xqmw8JrMb9E0xhjaNBeOSrEzAyHa49N0rfgp36SzEBPVETbk/f0zTV
xazkUKVYhS82YlXNX2BIqZ1fB0vgJhDVEQmN0ZbF3XpGahFAC+7a4Y+0/Gd/Ic5XbFpS6BbZ6pSp
V27+ZqxvC9TLYDWVpdFdl2+4++aLz6PVKNxAVIDL6WUYFtq3DIKGhV/BJDGsuycqp2iWGiIXNMUn
+N6gDOcNxLuboz0LzyWwSQvzflB6+FUCj6kOWSoJkGTUWjFq0UqOOX1QdCUCK9mb1CCfCJHIt3At
JH6S6qfHYPwaqf7Qxq/P4LVPOzV5hVjFYZai6LNqplyRIcXTkkTAjZriAt8jmJyDbMyPGWnNWfqF
96Rl7p2wDVDTR7ViKPdASBhs5JLPs4ATg1zkoOBA3Uq2vF/AEat5i2wvpW/Ddr3/HucEc6vPKI7Y
WmbYSr+D8MA2n8gQLORlyFSOtdetGkOBynglWK0L0PYqJru0/KfYaRbZAkIfsVRpaq9mX4vh1Ogc
Chj1IYbmsE991Gsaexnf661sOFJCl+p7UZ67IpSUb+hhRzmKQpL5xbi5pwHg+OfvSBlzoE6v9Qxl
bBzVbFxi7G/QhzSREXCRsSHPEiFI+vw8xFKKW8p7Hs2JnLH8HNVcElSZCOtf9z7EkOX0tMgukXrc
pU9nxrNohHc3+lA7ZMCUXcne7zjzWGTuVEApTLYF/D46vmi+tciQJLzlG1ZgDpI7iN94sXIRabq7
O7WvNrVVkYXSPjwcZmE52COvj/cuMqm39BjrkjvwGLRo6e7dn0sUfw7gH4svcePm+6NCQADUEt3d
qHRu/Ido/WdUGcAoS+efR2P6+zbnXUGkdtgrl5Y2njenSbGYJPpdjUpxb/VKVnyPHHzAmhBQvrUs
xQ3XreUwRmr/iz1rjxePvc0M+DyQt9unYWHcN8tsaKPfZKdYIAg6JjKcISBRyoVE1ZQ3uDCmSXzu
pgA7Jk4t/BxIddr3yu6NPj1+zSfRj213zE6v6UTVyjUGYmGUFSprpR8rVxuoEqTGek1CvJ8KeT/9
nTty2w8eQZeto0eH8gQesMR7rYATgurIz4iW6VP24zWU4J1ia2DeSo4F44rNyEx3jYAJAzmDJoQe
znU7Tuj/ES3MGlIALROkBuRbC6qioRFkIlaNwSv4y8MwxJ+DeDFkZjUgEiPBWZXhWfRTIXhyS5hr
Ok27tAJoxtuZ2DIomv9IIkdGWt+IBu7IQ+NxKXSVanqU3AAo6//Pw0LBZgFe4NgMREB5nW5pjZuH
f39GqIhf4khUVVYT7gr2+9xzvGq3E/+4qjxG01QW4TynbQEop3VCaPPIb+JWDDM8Wyj3e806wMVU
DHRHdV7z7OFc06nhNfqpdghS3PmelQapW/Uzqm7pnLsdH0+QFmTx5C4h0GxMCRqTsReCTIelQ7V1
5xLvodOUCdrb3/MuXUOlUr1tcq2fkUZtPcOiPS06OL7oF8vnRTzW+K3ljfjc86ph1KOpT2GYxyEE
LfD6Q9dywoB+zcyirZYzSLzKg8HKG/QlyW+RdeTf863UZQvMtadVQTGP+NeNDsPPoXArovbVgMiy
H9aM9jF+tNd2Po2Xs05mo30Md4pwVXM+IHRfXWDEP6sFpvEpepifUGfrtsv/zz+a3hwHY153muuS
ckaL6Go1x34Krx3nJnzHXar9EOJ5VomivUp1RSPA9w7119pCCEibT3v7GiPB1EvsI0Dqlb5Dnzjf
dDmxeNo82eCCAnGG00tw7AisZlFqgAlXa8NET6u94UmBqdOczftpgewIQHl10Mg4DDeyZq7UnTtE
cT3Rrp3m9XPVkT+MvbJ7foAMl2dAGqKmBAf4janaSoIgpj9wfXYsemFcfjcNLqkaCqjlbbYjicTr
i5g8HlkkEoWvJ9voeDjOlfMOF/K/KGwyq9w1M+7YBGkEAYtRiH4fciB12vZar2YhKxJujtIKwj/O
eWCm394MhZAico1MQgrVGx4ODNAc2WeoMVIpQt57qZ2NZCZ61tdhm9XIzmyd3egs1BeQQa7ddhYn
S1LellTBxA0y8PCb43CpqBtgRasTqg3+deDflr3d3XmF74sSlgvtWHl+VlSHOWIRcvGleb/shsvt
uckrvBDbSHUSiMLRe/zJgLTRIOTyj5H9lWQpE2jAcDsFJSG9vSUEV/pZxEVIIdwE6MRmsVWl0xm6
Qd2NM6ypC6qgqW8wQ3E2rNDlMKBQGFlPpFFYGMg7j2VKnNR0UhWXj0pn/qJk8VKlOmUmcW+IvrAN
g12eWr57zJmR4qeL5Sj5dvVXwm3AAUAyJJTosOYfDawpW3xL/Vkjrs1qlM38PdiIbgxnBDUuOE0m
CoSZiDI09sE2vjcq1CDbT9dPql9EcpbJ3dsFrGpcw+NyzOBarl3jjBvC9fLgqcXeYSFJfzRwwADL
L8G+7BKUEcIr5Yigws787jPoZ/CLmJ5HZEdL8/qyq0m1dYXPQAVPjOigSWRL+VkNTLUJpLw5aNt8
ZjYybR8DKJ3ZBk2b275tIXfaJFxpNOMOQgv4hDecC6RBzGl+8H5EZ2F1MTXIqevhUgtAgY49PpgF
wfSlBod26ZH+7FsjHJlZeuOQXd4/xVq4GpFW3JUtowtEht/1QPnLKFscR8zygY7HgUFl0FaeR5Ac
SkNuKbCKgPNbP7iWNXoKNQTZoY/tYCRsFNPejF6WX3KNy/ofBoOkFrZ2KPEjMsCkxBBbC5Tc+6BM
pX1GwCQ8bPLprlygotYUychR9pXmWEp1rDZ5HEZ4pz8Jk2mM2+DtHl0AdYk476RQj505EyGzSf10
VhCjvmAxl7ZvPDnY7yZO2df2ygDAaC8WHCURfeQ2hwzCTOtN2CzbKBvL7R0TLSY7qN+YqNnDX3aT
CYzMFyko5tHTSLNrUfZauNoXfNRqhZPbb1n821HyIRhQpact6ICLyBtiaxms28fgKSkkudTB2QyU
cIGasxvflt3Vg5fOVRpY7XgBvJZlS0AcgHjcBaWyC3LLn4jNFO5gUAcycdqO6EdVfXTZ67KSa/z4
m5U3pOxXdvcOBsW3FTvvMp8R6yrxm79Tfe0Z8aGTCRLGZUmYt87g9bRGXvg4XK2ibVO+t1m34QpH
zJruPB7Ao0MlqQv3hef0wWaxHeDIFCDxlFL+gYFA0N7Hyz4b63WJMHmsBOc7iFfArCTVqwwb+7DT
L3R5VeSbhvAWglvg6HWeN/WuGbj18yeOyFUydclVXlFSB57fxrN9ARM0lCMlvEgrLk8pf0u6y5ch
Fc8pV1P3vJFBtUDGXW7Yjc8Vf/UoHJ/qJaKc95lfIZ2Cogj1jD0Nhc4noH0fgaYnNp3PJpZVTCvO
mnfky73tNzQv/5Tj3+iiA4t4q/MEAktR/0E38y5Ujn1nWI/SRcnkAJaQ75ndsu+NNiPrQELt+Hk6
he6nKYmuiKSNgustw2jZKvIRoKnUTInLzGUtwsXst44bapCO7RdPkZ5WdEmUDfLLbm26ec+V/jTa
DZkez8bt8tSFHMaSNJiyr+jdDsxL3BulMTm0AmXnA2CvVZg39/Ini0OUJ/eIXlF9RCx0zTynHkHK
OZyaDZAcQcVUR8RiZy+hHdBYITG/o+9dG+xaYU77AkrpP41guqoG42eBkZ1FXrrV2M4Fl8C9BckR
3s7+RVeKc44cqkpiQMO4xqRoa1BMi2cYLshPfLFklE1yq1bhY8eD0XlLMG0oSc/eRdsMM8GTvtDH
Cz1WHcix8/up3k7CWYNdvF66Rwn+ohdYcZv7SU5W4dlBfHP41fF18GcIw8tZhFmcAST/4P3g72Fj
9iIOrig6qMGRkpGWVpP9FKW8dR2P3rZb1Pd6ipr9HSD5zOBLzx/M+jf4K6ozbCuiDS8REQllPY/w
1JIjay3U4K9ytStTtMy30ZUuXvB7A+SHglB6e2r4CKG5p00nxGoo3zqoFi2i37kYpWHmmVbVFPzg
bH+6pOEJo6ssohnOO7p4w8cUplBhZZzaYiDIVtXq8WZHJWty4M7OK1rNdXk2uTNTfdX+A/3WbM1R
FKrfO2H92ts4jt+yb6MBH3n/Tc9+azrvikFj3NSZDTwoL+VVYo6AvVz6Wp8CF5cHcaUm+dMfh8o/
EjKp/qLD6+1dX5SKi3uFmz9oaXFCPiR6SzdsZQwqOKFGQG32yp7rPnsLkxPX4XgoLfiinCxpEVvM
nGlaZojNu03F41R9eh9BEDtbzxchyZygF9ueTpusrAn+bXuFh0uieZiiAOduMJe9F7FETBS43PoF
2Bi55XrifTgVGujoKy8vDpQppz/wsDM8ddpKTnk7ItXKM3ti5vnOWjtm4pspugMJH4V+QwJHdayu
5QyDIB+upqT5kDdTmhuTHSchovinvw3oK+6UcACegg4lMQwNvVdH8FmzQaOrF6BSFnsQQC5LFsbt
4d/RA+VRwNoJtHLYyUWMsKfAeefDGEkDa9SEpJEgbLnPiDZjTjgPymjN0nRQjEf+7ISp4QxnulTj
2EdC2FYTBLpm1msx+PmRdc2TZcyDw1vvMFcgLgB8yor448L51AOgyZmhrSI+RCHTSBvCDq+EC6zT
EmogsFhSJaDL7L79x6fbXNKgKIF56hD8fEbyJYCOPN3J7fUNOt+1wqEm4E3AleyIOXFpvFWHBO+v
BF5/GArGewFWTqMp+CslCF8Bx3ohuovN64lPX1bsnZTnUbjJNMBZzI0yd415/fUxzxaniQQ+ufUQ
jzYdo0DkZ6qf/Ae5wdgkZD5NvhrTFBXmXSR1ywUvg1O1KvsvCLOX4iqsORYTcxCKJazC+a25FlmX
ObfKbIbvBGWnf8USqJiXS62YFunc6WSq+GKA8jGyoQ2yT/piQ8ajpxEk0fb+dp8YLNcKUgBFw3OE
VvC0YQELSNmiFwq7xUo38FU9cXnn5GsAVCtt5KP/XKoVgj5K3St/LFa3gEBlpcUt30R2CvbIi2qo
d2VayCzC4U8osTpe3SzCnQ/y3PnyJbnzZHzdyEVvDv74uAmd1UivEAf4NnO7mZ6bm1xNvQKCIqsQ
7BV2iAWe5o3Y1ZvFXO7IiGgxGy07nFQf2ch8LNvF9lr2NIyoZwvMqx+sB9G7XbA/0Fi7yggeDrft
MnNZGm1xJoZKWJ7QOOHY5zurly+6GmeOj4OdEFduCqFlqte799FQYn4iUbKzzPfm2yP5twa65oiy
ORiZrgvf/RU5SI7lSASSDG3AqpldkzpZSVRbxY70/0syr2uO7pNBaTBfcOmkH9893aglmsXKUN3A
HWvcXjzBOXbFKt/eKkJnMJw+gZqReaS+yQBO7aEbBbCVp71JEt8gKfDoOvy+E925QZ1x0ha11iu3
Jg5cG4SSdDL/qnNGhRk/Sfyw2D1MZstlWBqoHkVEmn5pUYKh2Vx1vUzWWra6FBxamuTEmbwXYGwf
ZfBb3eDNNA9rxSmrTv0JncENHBKFInDLPM8puF+NVRN0CzB1ykFe7qAgNeljL/d3UcYLVVxe6qRE
tPS47IhSnWEJt48yI4zujX1p4DrIbuXPr1oEz+LGvCNMr8fuvIFIdZGdwGoeRb93nUrb/Y/05B0x
7hqx8cKfUYA3GBemCkXkluKxBW/J0XJ2I015wgj61FHYbK3A2k4jTq8IxChs8HjFSwVpElv5O17I
QLwa4/3IMYCqY03856g94LToxradrc51Tdv4qOePoLjWUykaVbEA77Mmr5kAtQ9TEDIypw2pB3js
iQTASwQXYcKXsg6yEf5HhpRX1Ij/2Txzifwkxlqis4w8av/JRs17tD0+cc14dW8S1vJFfW16yPnL
Gm1EqgmGncpPgLmaJvg7zEudlw2fYYDlRN8vPS8HIsxuwLUhBRUN4MHJVOKCgYzO0KZXIF0f7Ijf
1J8XIRKEFet7RseL7DS+tg0rlUcs75L3GlZHopKbz8DQaokeAitfOjfqxQ2A166BDTpyeprbNikq
AFj5u3qB0I5wkiwG3qtZmFcbO+BRIR2PcRKeDrh4tMnMUlMQM8L05L36foD9tY9yj10OtGBh48aV
2ZUkko/sGGwIENZaBus3DdTqsSEmeGfS1FI+xspSTmIc8+whSERM4jktY5jJhQJ8bdV8MVT3o9T7
zzPaVhwOiC/76wmOMfCvivokWu4Gme8xYcdafxq9qgPAvK+4NPXqo+6aqtT7Hk+DdKXoJrUh+Shr
6RSIqMGSqs2uYi4Pe4J1JwkeNhShX7R9BMBLaPnO2m2zkuPAkEc1meploRXPzTvIlDr6wxK15yHq
deZ0m0VM1NbUTjX12uGuB54JYlNHnoflgNGj1UUm2Wqbbm3bM0h0r5qz9ESlwGZQ/4Ct2hXpVLJt
ATiiCE49XO5NuFTpZgovXi1GZj2Ybr4Sf69+szmrxtagm7USyb6K6KOq53M+8FoPniWjucf4XW9J
q9iaX4MVjOsqqFuWLaImSHAQRmIQ08+ez4jKLHPGz1mjXZhkyibyVa76u7RvsTjOkSyQmFqValH7
wNXPNxkZaMpeKpkKwoNC8Cnr8C/VzyrM5ZCBAdWxfDpG6iWkg/5OTzqSUgeaCJhqEmCOpyFwaS9Z
I6IG5r99qd3FHKcgK/4Wjd/ahG0/cuDc8Sy7mJ+qslXvzLnq5o4EEA10DxC3dsSkwOjJB3J4/20+
YnakZPAO/z4zfr/JErxjQkMTFxC4tU4a2hdM6LsssbB7Yhg4n9XlztQdGU13Il1k9htne2cLvY9y
sCxMiPqGzHEjSh1XOZYZy73ynsFypnVhdQM+ZJGIjAWKWx0llostAXf+MGcmlXil1m099uCOAELM
HRsLjdjy1MmsbVm0WNkiFyuEdcGZmJp9NeOFRyltyZ1g1ACjq3iySWq2QSMRA4O+umi4dDd4X0Sd
M5gZ5p51zSAuuLQjX8SXd2L9O5dX5lh7SbIeWL1bXZjZ3Khu7CArnB9aDf/eLfXYdXaTVO1dgzO3
leAzpVpnAe4C+L42b3DiHWWYHyuhQ+Zg/B/o7LAqqQpr0e2ussr7PzzHrulpl2Om5vaRnQZboqB+
U3slAiBpz1gZVon2xthHh7+/M1+PIVii+lUNzGoeczCrxlV0yMiU41rzaxuJVy8BkHXSBp0HSgln
u764v73UuRgwBKTr/Ie3qhrjCy2xhcnaiSQPbk6vfZSNAU5pStv0rDF1roslkXN2IbhbPmIIvZvS
5sI9pX0CDLNV7z4F0dZypBuUyleHl6T9IRIy8OJJ74AnIU+/GYm+qhH0GWCFfYyh4RPKVfe6QQLk
1dz5YpfHK5EiSrX8XBoPEEGpHpJ1Xmm2yJfhgrARgTgRIbSACpVMtsYhKQtYKCKQ0I038EL3U984
BacsB4fvUM45mIxD5kDW2hIby6UYqGYy3OlkvGgHC4uCL93RdiWLqXXDZhy89fhQlgAYhJNEFTqM
cbCNCOc0MxJhbqQHO6y5JB3U/dtNau1myaxTE25OERZRkfmq8pVSH7NF+t2qmZHok7gn26qV8etJ
QkBmEWAiAh9QLIwGQx7tyDZKxf8vxkz1AXitek1emm/zHArdgG7+X1jBgzMrjYpKZOo68mV8b569
uHvnmMB3qAFbbOlKtQuYDB+J4q3KnuQPq3oWcnjMtRdGoRth5fyWstHSUd8XLlLxYVFk+V8S28zp
g4J4x1Jm1qq/92CQlMsrXiDuNxjDJvbPUDnucLTLh+qj1Hxg17XzsQNKJhfeqbkVDKPeOt0XnrRN
5cwMNRRX1Ry5SaFWkbAHwOytpu0pzrtrfb0EGO+ltBfGn+t7txto1N2bTly4iZQ8i1qgpdhuC4bk
OwLAvfRqiHJEpdO7PUyT3hZnK/yznNSCQXpDgHMbIZI4hRqSx1+99cLiG4vMfJeTn0ZZbW+4SeJL
a9kRfLUKRnJv5zrT9ibx7z2wMoBpfBCjeCCjv11Y0mKwwUJ7XqYyPtPfrJvZoqGjvXoEsUeI9fwz
tWC9ICd3R+6oABWRWRs6786yMh5oIuSOaKHKt+Kye/iRDyL4bbrpMEa/uZC59iYm0ODxMIwhMrGQ
L3vWFpCers2TNec026BeXj9pE5WeBUF9HhILMMcrt5Utwe2wo5jJc/tHzP8NjtCqGMFieAV0JDoE
yHCcUhOJjPZDYpywtVX4j9g2LyZPjupxyODDWMcs9s+MCzMUYcHXF42heZSPk8TpN4/XvlucyJaz
Fi6OrTnkbAZBSIzUWA08wBXKI9TUj09DEIWz5JNoVsoWUW11Siop9MJwAwOi51YS28+mDnaXaeod
eYGhvhp7ibzDIQcY2moGT6Alcg4WEcgCM32xcT7GfKxs+bQOuJ4Bujb3+VW61L+x+GMXbAkt+mw6
2dJgS9vrCbaiPzquxj/p1D2W24YvDmIlrWNjpEWC/DFNdO7n+2TfR6zjvhG110sRpN5Y3J80q/nG
8Svxyx7R3MKTFCBE+7JDSZp1S3L3FB7yA604v3W89LsK44LLmcgH7IjnucBUC147Anay+ppnW2ka
uzgKkpPJngXebzBQhEk+1DYLlt0yo22yi8XlMzz1gbkLRfWxRLGpT2nstekHbagIiZICzhHlUa5K
7V2ulcVO4MhtB+YQ2DXOOEBwpUOydQlFEFIAW9p6Q8oJEoBonp04PaDq8tmvb+CThAAf9SCrqNw/
LQWgLCY40Y0zr0T0pKEaMx3iGGsXqEpUO+sh70xF1U3GwKbaC33GJbzvb7CgMVUBFJhfn0x8xMt9
7Eoo96HphD3uluSOerG8RZuVRgHXMxUjmesKxnGjfgpOiXpsunNs9bq+GxYHs37blv+EkkHYqsAk
QztdHvSv4ibBZPMJt107Jrqs59ddeori9nCTde96TMeyKL9cRwJdx9Fr4lz5rzM+/f9kkoyZYBek
4mCL7BMajmXV1KATvzs+MkHXMgt8sS0C+DmQFq1eb19AWpIXMyr8qFTBcfsNHQJrOyUlDzgziKGV
Zuu565TjSWWUOwzTQGAbtismucMD/AdY3pm93uJDpxffF6oKACFMpRIA7/d+nLKqAuMY/kHjUorI
tp53zBn3R6njb/dTKYEi9KJ/29hxIBrYL0+DFi99xz+/2Dl1SP/uZd48BUgepsVOIQrapedvnOw+
n1/sGEMbAv6rSlqIb95j4fjK7xD1DcztgADp3qvqzpU87TxID7JmJj7TklPxq5UVD26kK5zurowQ
oWaBPSzTGf8VEgcdfWaozSOyxRcPgdAQUDlFBd7ifE/4m0T7LqgOzRX1ImOLEdZzUqvLZjFJ87hn
mJWLwuqbloLkVsd4mVdnUHuYuVrorWxhp8QHZvYAD3ZOiFEDmbx2tyTC7TNoDFUH6FlvrjDbv09K
HFEu6U9Y89b9d4bAWsHc4AO2vfM7EJ3kdY5Kko+lwH7yLVXecClVt6l5iRmfCsdYhlCzWxhol5fg
EFgKobzinLRVIv5OyBi9l1gHrNBOztlVNWcUoP3E/MAYRSUGqucijai+I7aTnwADZ8FqQbemyKii
6pk1jV1sEJlVA/7EN/7G9IY6gVnmJIrbPBht/K3wX3IjuRKxPZmw91B4KI1nRRWDVZg78sXsdmkO
SB0YLps9v0VsrHcIxTo2JDrpABZJ4ik8e78mxvTXmjLrrD2nt9oiOLsLkkmAHvvS/DEq9ggmMlEy
CkZrQatoDAduHzfqLr0En7GwKT8q02j+24Aa51/VhoMpRQTf3FkRl8nYrcbMif91179YWbidPN9o
u6e/zDB+SmjYau/5nXdS/D6gXxIllPgvWer8vKuAO9TTT0pxtWzkXy53bZft0kPe6s9kHZALt/mR
PVuSdCFYsxpSJR6Dq/yfR6wxU+10nOusxZOfo8h0YEi0no2Ins5dDYkN2P2XJcdS3pDq6sl2I77e
CPcr7j/KYiA1DPrNwidifrxjbT1CJgxIJV5YagY1Hi13VKIX6cV+fzzIkMI7DAaWZ9+qwKdBtB0X
cqa2zOa9Ug28rHQZicbTJp/cXJbe3Fk5jTwXa0jxY10mUmLCc7Lm1Jmy73qHfKQddcAA9JmY9iKY
hbj2dUKt+YDbDn7TkMLTAK4wQ6qRijg2GrPd+pAWtihhNkcNhAmowL3ZXJVqNjUYr0+SGM1OxpeR
1X1U1x2v2DxjT3kGTqn7cD+ISVo6sFHTDhhAk55ul34DI+LJFve5BRrlBpXsjiXIZVzEAc/p6ieP
hNBlFyVPvBbSWyOK/t34aEZmE6njCBhtqgPICLevVeJ/EL+rtgo76KWtRVVxrrbFDuM2kTWRYSiu
t58ARc+37XQj93pxpQrv0wTqXYBVjZQh3BIKu4GSez28+4G1kZBf9uddYNDELmqfpMV/o3bkX/ll
PLqmxHs2M2s5MA/vVEPA9/COf8wBBEZs92pM/4JDlHnsQ0c58ux15ocxRAwbo7vKxKGNladlVUcL
MsJapL+Zll0lD3tGEAcMDxZxizKt3VUNmW0od9YNumNT6FZejN5LjnRMr4v3Qk9j2k4FDLvfFLWv
b38J7j5jPvO9uEFuharN1QSzI7FhPE2ELiMqovrLjNjwXXvrvSFGdrfePDErb+Wx9aqMW2E2bvq9
BEeB1Tj/2S25mIUV22hsFszoLZiXJ/z2+jBrJ3IcExcgj7Wulq+Fp+rTwQ/Vt4vkAquCsV30boXh
CPcbQqVPyPdQHW/GxyH/2zAL8GByeB8+PbzbQPAmjnmy9cm6ZmiHu9OgkzOLnyhnkgzn4Px47TDm
qW+UpINTy2JY3pPFAiyXCaQXD0yOVzmve4lQfzT5TVmD4gjZ9fKX5oRnbuxRB1uHuBMaNM59HRUF
J9edTgczFCSoNcR2A4OFtxkAo5VpN85xO53HuWP/oZyxrLhRz+KHaGbScXG04aMKsXTjIWSFFMrG
0+BIrQktQ1YJstWTHz9PXTOwGm7nxym27NtEB1Io+7WZroR82nywjfYSzR3dWTl7skfqNBibJQOd
bBdLbTOB5eReJfTxA8QPVoXwxuyJPeXr7+5zJACBu/A2UxLP8Gf8XUIYAaft5Y9wHQ2V/qVVG23h
UTwkiXSIsP2BHcK5Bps2Qg9WzJsvZmLv1ZFZSjAfxH+MNmlPWBGCD71OVN3R/OILpLC4ivcqN19j
31oeVjN6XSHpAI/VYq7w0C2bGnxx4CvwKsdxHYbB0J0oncbk8oVmjjUX+yeU21Wymts55dHpTJSd
GgZGWuxA/IHH9jccb6IOMWSlUCVo20/WVZRrqnT1Gm03BbTfOXKzETPpqwMJ+/ZdcPacAUILTSGz
hgD0BFjxb5l/a3R+3IZOt9oHcKxgfbvcNGGmgT2a/LhlJxf+Kcb3U0jP2YDS2Wh3CyU4BqdDBLnt
MZaG1MwiyWG+4ujVBIxIUkd8xj8jYDBzrf9eT5w9b43o5aF3VH9ze/oGZlPeZQ3ZgWDOSydW8dzI
M7pgRvSYE9eHJqVnkQCkYbzo2dx4EcmhuJA24/LafCQ1HuR9kHC/cXUewJ1SDEcaThFR2Qn4ne8O
H/HyPxaOJFyH4I+qSnZgWur1kChfthS7GkeH7F/8p8pKo7BEKARdHWMRaP8ZULgjqHKDj3pspxnA
3gR98XSrJU1sKp8qfM3/UZC6CeG1E95AhaxqikYXuJxyLyM8HGl1h44ehtvuWET2wPyKa+EzLmpY
f+qZBzcku/TPoUsl0Y+9dKEs8EIG5xxUYgsidnZP2NHP8D8d+YNfyUqUJcTAw7mYH4L1zsYHhACh
ttLgQlKzgAygqSHlM4B7SknyzS7tluI21MOWy18KV7RvwTGDGnh2BmbsmC4mnyvzMnVc2xNckkwB
dE5wkwBPS5remp7BijAKho1llFX8v8+oVIrNUU20yeyUHL/aJ/9DFovjRb+ZSV/u5ScCtt84nkiY
kYewuZhZhbdUVz2RUDiT5EhHTXYxAHmo0w7tZKNF6VzQMdXO6hsgLZpMI3xiECS+AOo/aUhrbq8Q
yw0kYvtfXLyYkfFv5uC1s5EvN/ve9u83P3Er0WBm0X9R1DQCKr7DJYsRGrpMTcKRgVFo7OA3DxOY
G8jPKeaO0Wi59FVmnKcDAm5tBKFPK7mWbOksnlZSiunOH2x2Qv8WKwtfZ6SYsbUlJZTSVer7L3Hl
Uj1dKU1sDhWqCuWsVAxfmRMSvKnMO3HnTVGfrNfmu3T9yIgEEPFKX3sCDR/4T/cWUgDVD34CG+yv
7LkTMHNEpFutRY/S18znvSu0mRtRXHe0mn3+JOhKbR3biLP4C+h4VS1c2wCX4jtMk+fbkw1IzvlA
aXqCW+c5R/zW0ok5Zn42LLXAoEAlSFLfQ/ZLkDQ0EoKm+hNBB+LQI8FcXmA+KuMcasGqSnmLi+ZM
H0O6LnBD7qaDGTkWhHU5FgBdA06l5ehUcUAnAE3QcCvPT8ZUIVmKAYLiyoF0q43PsJWfQV9qDbZb
M+1sdHw87RDI+IYBnexJNIeXjSOLNVFdQLL8YSQCx+evX/t4EW220xB5FmHV1TGc1b0Gh/EkZX0L
+LpOvCOzjfSy4pvNxuY46XkTN6CbLZC6wgAQIgvV4LFY9vGsu7XlIDQuXsRTzJVQj/Hyv1+uqXZq
uibFyYX1wJOGgd/vJhy4iIWlr8UFL5BGxQ8P/yJiDMxmHa79AnvVw4NM/Jg/QUZ8v3q/JqOyn1Uu
83KGucKEnSFp+Usbc0bB5rkZR6JfGTputJUjlU4UpT/eMvQx4X4zrA2fqztt3+y0KMFHnL95xknm
VvHxppw06t9EgiY6+xa0+fcvxgPLVhlSvxFDRrcjYfduIcqGJncxyAHJyGYJ2pGgGDk+j/3XFgDl
OSZPMzxT8/5OOIkIJtsMh+LR3pFEE2W6uRdylhC3wHkQgA4c1OqPyCJ/lZMFov7uQTpIw5wgzPte
WfoA0j8iuSBbwL3DbH1Ck3EHgoGGsqvBbCU591Vl3gGWViY0ExPWnBcxKI/rw5CqzuRzvl/9ZIcO
GOwrfoMBybVXqdg1PcES4pu+dKcUNFodLZetisI1zZYyRqBRGlIAOwofByEnWelcoKlt7TSeKtx+
CQhMM8WgFXSgD9RvCZ/VhvEgeAjn6pgCWach0nf+AcxokLA5LP41WyFmuco877+mXaezdKhx5bDQ
pJ5sbZc0fz549owJYHRVJyMkiCzjGDZoVR106putASF8R4poLd0RiGfTr18xcrxu6A1+x7zWM4ka
Helfayy2kL+ghM3t8JQCRB71WYJTYBS7bUYp16AQV05laud0lfuw8RNYbxlr4t3jBRNfIArfE+KH
x0IIzlztLv8FyQW4KdtelK+OQ6b8H8bN+scFaaS0OXCrFsm94WexEV3cNG7F3tDKRq/IiiN6OiiM
3tBrPaB7v7uhUJwjOt/xlKlVQQPrv9jSlXh5ftUfTfcNOXWoY7p1R2sE7wD2z2tLf+/AdWuFpzjd
SP5A/tFzXTKNJahdR2/tfBIVh7rr63W8Ofu181W9KDahCMWjkmg4QiuKo2Hjwk1rXKrCIQjLhrwN
Cf4YKWdjqYIGvVxncXMmOWI0JofrS9DhWZRWEIjBoD9yS7mzQlPtIFcEyoP3Amqr2LuXfYHALTgy
HHzkYgtLeCE5tCP/aNLYbnPK9Bu6N5Qd0WP4qMiUYFHvJoGEd3x7SNuHEcHIlQzFvOi7YmCgXoJY
Z4ROKzD5rXJhes6LfgTsQUrRV+IEdgLrjcNzOp5kjSiq0+W+RIPfzz6D47HoVzBoD1rbNGSucOkA
XK4+jQ3yit442b0m20mH8Q/dWlgq6iQngGkgaEcCS0M6l4jMDlnPVmuoRYNBnM9w1yUUfZeyXTMM
ZDqP6JXU8S19rirxychIk+ruNyBX3jlcXdXftsidneiw4PyIWQZSC1f0zfwj2F/TTpiz0/j8svft
9SXRfOtBa3FlWyXV/SNnV8ajm5dJ/VJomCOYlxkVpVvy5YD0MvMdDHy7yZQ2N68S0ua0VEwuBqVV
24s5ssRdbYMW3Wt3zT/gn/rB9sgb183816YouLNbkbgC6POlMqsHEBdNlY8Huy3bvCJRX+4fo8wu
iLtsYSaBvBtGxKtDDwHVAnj6DaoB0Y5/Nz28j2o4uARgooDm/WJs+tEGVcykClKmiNG9dDEI6NqI
6D+rSezQHC6ebOuOwVkIu0DnGCwsXrNH4qd9VjCeRvUVjCe3g4tHdS7jqL1/p5G1QteLQGmSh+R7
4QZ8uZUbiZgVF99YiNRrKQSiMx0hnCLnLrSoAfA2os5iA6R1RtzswDA1W+2C2GrWgxvNpl0QqA6Z
Ecw/4gSfUHnGTlwIYRnq/twwMg1fV0Ej5aShhasP81/DsYvboMVWcP6QwsiptHKvcPF56mHXNRWL
x7Nz5m/HmY9jJlv+gFfsu5f8kGYuD8Nvk5gX46lfdH7rjL+7hwg5bG7Yzj+7A1XzcC6fwfnM4sX6
FlhhsX9xCnTxMZwguncpmJqlAnIDwhFnyr91lr8tkB3PVsEwHeEjQHNcAArF8DenreXGrNqtp6q6
mJocqFZsHNqz2Kn9sUhDLGUakpTBM10Xhu112w88YEqzQWozelJAOhIa+aXiguvCBZ7ywlvi+zc2
7D1Dt2Xlc42rE4MNxTf1N+xRTVNwuagwFYcuKhxbfilf/lzU/SxVIbMTv3lqoUgWFu1zxA11d3LW
R5G/v0l6dHPA7jDlRSz5nqccPaTRxjOtba20VcLz+ztm1sgLcrFs/Ex57qlxsY1Blh5URjPByWDD
O+XQEOB/AHQpF94t2mtUFoM5v1XJo3QalDtj6EVrKdnWjpLMDfjSy6eWhuAU9l8rfm09zMzt62Nz
7J2j/Fxo1FLKIs4o8t9dNL7VqB7ULrFa59Afgyn1EQ1fGfayz1XpUE/xJXIxGyWNkDIMvvdTVvP6
McNx4PwcLqTNtod7p4rxEDpymVY07ngzPYfNVlMU1dK9dMAfq1TB32rjUGlJo+pn6A6jHQZXeZy8
4aoplZFNSxA1d8SpEyz8krzSo1nsbYUnFy0S/33u9zGAZ2dN52LbaIH3KFjP3d2GapDGGi39rZHA
5u/Q70RVG6WDubcLobwnVVQQgQRp6pln3df9w0iVB5YYFeF+WeBzHG1pCKjq9zlKHihaqGbuXycy
t0PJRReArSwBf2tB3RSJrF7+JsEu+mAhIltZTQUG1MsahDWeNq9kxHuQ7kveWFXoz//AERjEnsSs
GjTp+2DAAThFAD1Df94EA3VcJateEdeUy1WIH5NxKv6AR5SVlrq52Q9GfDQ7ZWkn3raLvLoQTAai
yK4Iocs0mjM5LQrhunrXdxtyHg0VH8NKpb3DOwZdnTbf4+ADi2d+5arzmBpXQbWNOfq/NUP9GsOW
OmSrrZ9zGgnqMhRV825ldxU509wieytcVYGaJnDrJKDzFJSjGp9Nd/7EC8XS58JcYUv9xrjW8gtM
LJBgArDC55fgB2IMfzBuMEI+Q60wHqUOX20VtLlL00tXOGHIv6HN4EBlYgNEZn/QpBD/++ac8yTp
RJfEPgOOuCRBOZfAZw6X9D8TpGLcjDEGDsZdy8KpzRzxjiiuP87syradcSE3DLyVx25MlECBnLHE
A3r8xFHWlROuDeE6LFgue/DZvUHt/81WW7o9LoBDcntwzIZQl8pc9B784vfNzyWYBk+MUqvrUcwl
FSKssObgfItFZlMdhAAOqTbcnL855gfjgzLmkig8ShqQJuqvw6JOeOBme1tAYTHr+a9gxj0xOsdh
E9gJvZ+xSvkWOQc/mZwTIn5M87+jO1Nzhkbv1MBBDmYIeyOOB7m/mTqRt8sR6rwDy2LIPawX18fa
UmDUv5a5K2lyitUNxe+vpdTcWnKnTTeRQLDTaTmINEE/WV+VuU0jSTMC6jETAwIwpYV6hk19gwx0
8GHY4Olf9tCKdl9at66mMHvun1nRDt0x7qgGmA5E6iVyWY1PWPMEjq6QajYfaWqypeqyZks33hep
XgK+zbxfT5wIJEcwsypkdst1QvpGmUq6OEg03ea8qCUHnzAr86uSr6McPDrx6zuEFsbQDJTM+7Nd
n/RU+WsjdL+EkSEreVxfc1GLjclQAI+hudB/RtiVX+Uo1g5vU3SpV64Je7jjURyZyihmkddzObXA
d4ZwN1LHUsvQO/uG5OGscbaU1tJzcQxgZQmdQXlsDru0F7MBrCDrw1qhuALrPnILaMvGR9bfDRlJ
MPBQAykI3qnnmf3CSc0iUZBd4m36IyJVwvFRFL2f3mCUn3KKHEFC6T53C+ynbVQGFH+qF3RGxv98
GldBVmifFRP76+g0CEcSIvwMQwN0BONl7TteL0a6yAM2tr2bgEEtRTK9fYqLlHuAKfe+mBvIpRVf
96vM7AZUiiZj/BbnR8rdKz7oXJ7HdFX2WxETHDejeMexbytACCwxXY6qA9BcH5m5L1SlcguCitH5
yihEeOmT7w/TLRkJQk519maLPUH3K20iz/MyaGAAlVXYhhMGbEOpISViLzlCJfY1RVTMYfL7LLhm
KGcI48/oZYC9g2Dh0zKzoUpXXiB+ONivEZKc0lFn7gPynYqwCxjZpkPvAulXOMJWpuUgELDFm8LH
5eQgPunzWJZoWhKgeMg5WoseC6bkgMUO/FKwwPmBKrexXdZFUfEykrWGW9+8CLGUdAeya1XJaM8O
xLCieXT4kujaC9Q9UzcWrzVJ/Q/DOIBx88WS/7ukqyELxxahIJsEFBBWP3BwZ1FgM/TIxjgFiDwC
XOwZEhwnigHsBMOSxwyBdZdd6kJS7pDt8bwMADYOMvkn3Jj5CppQ2xy5By32+EHLhEnEStoz2kW/
/WeWmiifOBp/HGXZoAAsmqtJ89OIiAdU+xV0/tY+mXraax+xwfdbUWOv50HMbldT5lizDDSS+MYZ
H8wIuC9x8wbGOcUUkfSAPU4CW2TVvEbzmZS47Lvez1DscskY9oEYlFbkRJO+mtiZRG94YfDDqqMf
v9YTENpqoMGEs6k3VeHOwcUHN2pK0tjWMWXu9L9CsA1Mf1jUX3rQYC81gqCT7eoviXfmIorNSLJ4
vnfXBD+OBp22vQopxgZu/JmY4gGOzSkDCEQ7b0W30PAwFQYrEf7/9kgYeHveGoxcNjQOP5CHbz4Z
sZ+SffN2hWhERFs/WCV8MzhGRCj2NW8eBb4avp3eD65Uy8jPlPZ21qn4mBquDnSuyLzP9dA+AYZO
/a6L1tbROhLr91WIgg82Wv6ZCBuvTZ/oRvWziL7om/c6vzEaT57nA6sojiVMY+GUgrUNDHk+cV2J
t6hzcxAkMmW3NEELYR6+6VbbP82n9oEwVb+iA2Gx1ZMxGzgS32K/POzZ/MnpDF28fhzCDzxb5wOQ
hnGT+lOCjL3vZG7WDZfndEy8rrQ6C6WYqlGRVGKS1ohN0I8SoFvoOFKlHCiUMSpOh8J9JxZXYJ75
Cdavec7yk8Ab5XJizIBHCqb6+XWEzhHkZBrhgDz7scmLh3Xo55ZmKMxpz7FQTNQuJzmc075qQeFG
C2cyswwRhBmPxbX31ZyHBCKgl3EsKBkzUVOg82GqqDU1gJK1jsz74CeJqWt1bTJCq2Qr1GAvHZhP
6AHDJ8tyyGJCMAJ4odx3S9TnwiLaAeWlqfrAZXszjok0oD99cfO+XQMKYyhkB5muT9DLBIUcO+1t
9oMorbxP7l7cKWvQuk2fcc8O0fw7Yp8HyzPzbtyCAjyX6pH1vxT86wa19VzGP80LnkL+D06Bgwuo
9j7OsnYMD7hvHOmp26EUx4GDZ1LC/kE2B+Hdidsr4sPgtBf5yPPXBe7hT23iVCMl2T2hOjYmCFLW
/5bBzlJZpB45zIDaip9c3Mh8asw2M8pChVOSdV6w9+NNMNndoY91ql7WW79KpycR5+iCE4IIP468
EcuG2m+FfU5wK5Je5f0bWot6Wn0lVTRpXQcnEgo6uGZaNBSW815eiALd2THEqztzJgKTWONSrUr4
0nUe41hUP9Y6ryDs7wNhvqS4uuVXbYPsDiGvyLtQ1phe4+uNaTFcs5yithgLluBRs7jBCqgtunXJ
RZiBt2q9On+RFrAMWBfbXgDRzFOYLL1eV2YY2OwnixRqmd5V7d95vyIprWGDiA6kFuc7IKc2YjJd
tJuzAfa6jUQ0drbuEPIUmNK8cyftyaNx2YMwHadR3tUmCc0mf8FD5ES5DpgjPmxYkYV/7QFcoQb7
xCE851OlP+x10/2hARmZLC9u+V7HcRWiV43Tlory5JIgTBxqa+bsmrz8jGRLXoQE0F2Rn0HWQymK
X/5yq66lRIc17WvqcqAekhJmemeIP7w8wlxlgNlKcNs3TMuXKR/t5eKRITKD4LM4i/Hacn7adxr+
xCtGjDpaz1WBzs37Y2y1ipgeXKlHlcRQ0CDOlHgMgQZOKVons7sbFqYMXZom5cS01Jtf/1dbOCkz
P4kPMOwyxq6ZlewBXj2aHxh+ZVTR+0AJQmTZr4ybD7aVJpNylzjLpsbVoP3qbJGZbUszGUl+rbZc
Cwe/8AHsj1/RkuXu7dprnEO/SmPFb2iLg+7qUAT+EV7L2lPVZUr2VD1oGp5bEdVYQ/N84OzIvQqY
AtWQDmLqBuYiwhdX9l8NzLp9mReuHDQVSs3QOx7hdXMYCNslvoavkggoUFFQY0ymkq+zvnnDVKF0
uFw4u3hamd/X7pR2QKasTEqrvrqunXbrJdPYApfk750ej4n8nC+LMai2sOI+68kC0u/DkKc779uU
/oSOVt4JtpkiZzYTY03g4wWBzgL3OXBJ+2g8/1Wq2Fvhe+q6WXBIEx+tOHa0dC3nPTidOvZbM3IY
jbYdFteB+wF1e9W6hqrBgrwSky9Io51wWNsj3dLK+3azlxyXMV1DpNJTW+s67OlBjxJmO0gMqlv7
c7rzLY9xDoz2mNswf94xHOoqkw1NFMBMR6G8YOhhoAacYDlX0gZZ36S4UdRlYxHyx43Exsq+JNuI
/S1iqn/rnLpGP7m+Q0UJtbQQGwR/8kjw2tIdr0G33jVzRwBzZt6SLDpewnKMgoDPU6GLPPpdGTfR
C2MgxHqrJKzUPyABStdmDKC6JuHVsDqtjJyuS54AS1PAvdkt2l5b3y5TieoKHycobUsiwumIogEx
ADfCcEAJqIO6DLB5pbB6BHTed+jK5/FV0eEuS9xL1jB/kFsO7kwjiWPZ2AbMXFWj8W/lZDInu0tG
eu57B3QmBQb9L/jy69J4n6yVDqGTOJkhf3ycGEvmV2L4zNUUXZGPa8qjv4G53aybblmM+BFcPoC+
CBYNAg77NLDx6NhEWFdhVQwerWMllBvaGKwzl6t5b9vr9SAY/sjOwu9vRaQEi0H3rcDmDiXzqrL3
kUdMCw4prPaijNf5hOgYYOmRWSDyaNa7AEJK1XigCUKiYMxwK2OtTjHhOzs4Ox4cSNH+vhteBUnq
svKnThpQoNLKCOwiEdoLoz73bNoFgOsHDknT/gBW2C/vNBeEqWLYy/bWET+LagUOQLEC87/t/n/P
Ovq64p4/EECab4dOaNZ3fAyfXxcEUhYdmQn1bCGyJnEreF4UFmXVQGdpuoeBrIE8nVfHEFUzM1/l
VONOJUtlp2bSB57S2OwfkL3elH7x4wysZtHgpz6NPofZn0Q9V7L20PH2oiF6ocxqlNSnYgq/Ls1K
weugzqaUX1/g+at+BEBpYKXjCelrXiHtcVZenOK4e83/vNxM7/wNn+ww9+3wLsfUru45DV3o3BuT
5/jGfoHmmOmTqltvNwr5h7vTB0qY2ap3MgmAhvDcThn89qoUmHTLVXEo6QjPoUrXPtwgR1jAVIXm
wAohtU/6yNGVC5P7efuhdevGQXlFxmFo1ocwsl7HR/o5tkx1Ezk/Y7oivc+Z29+iKUTYG1/sSHev
Nsg1QH8LgPYCfR8y6O6QpoSc8hssq/xFO/S43QwFiRDMli7NwrmCdgdLQSuPOMS19RGmATZ20rF7
nxVbuAKJRnEBMtFt+mUGh+TiA+Ol/g0QV4yeW2mzxn9O1GIALrP1uZqyk1GrKE7AdzRqFjWeIhR2
e0Oez14dr0iFawqlerA9ZEAP/VTFkfCsP4mLnhuRymthr7D7CLwPKi2UqPTgLmmDrGSQfR64lZXg
T+awcDWP2xZlIf4lq1Ic6IWpeYQSOMOgRt5w4kIDaiV7pBRyQxY1dI+S1HgmjDi3O9DrTEeC0zs9
EcoVepdwcJI9JKDqRGhhIQtLuw4w6mwLw3bL7SBybAYkiQFWRai5UXJQBY4/udB1OFiCBWw7nwUx
Tptt7v1iSB2jcOVYDEzv7uj7OrgtxF2p4R02epZBjNwYi1qqIbPn3wjBEt7ubStJPpvO5Jw2LeVn
p5NLlS2XCI4ZU2xSZp8X+iGw9JYtjf9C30ojJ0bX6V6erC2Fw5xCb06o8ZUAYpJZxuzGdn3E/Qoj
zZkrwyid83/W344cTYA8TkJkG9x5In7ewhVxQHb/qA9+HsfeFegEtHd5tAikeqKWKmabWemmGdo/
9N1AW5EYryjDXoIgI9139ZRF+6JiJXTnsRLK4zcxyuE0MPfCJw8/4Myuf6AXzVASGQCYsqmNYccH
3iGRNiPwBOlQfVGk0fuo/+yXaeLuXaLBbilWKR8/Bkn/r8NsDxfCXj5B3fezNFQrPTOj4EDvEqyC
dyXD+5NyZoPuzqLXGLIDiodStkFglx464bHspdg2Q4pEKB0vgoAFczjrNMVLy4HNN5Y6yAoDsKTC
xtYeTAje6D5RLf8wldZz+E7o92tUvWFb40JaNO8xTKyVgHPq4b4Qlwf4Nssp9aT+N9DBM9wwa/bf
5Yt+bsc0RMI2V5ihuVKNv0irOMAZ4S4i1E1iSW1QBlptYpGRsDsYcuyqSidHkOahc0+nzmTfhQpe
AJTvXvpp6ozjiZWn+K3l7Z0N9rVQBYPgDSErizkdnVAGH8WE0/2QM4wF8HTbVQkp2FXU6dRZ+i0Q
ABlLvQHFNMKqkwiYWOxGcqLTvPR7a1UV7egS4boOoXnrtb7va6DW2n15YVibPJctLJ7kPBYzYGM8
FUslMUH5gqhD0V8HN7YPAIEJiRwufJpVHRZ36delR5TeuOmnSkGZU3bEFJeQ2ficb98fdZUlBzla
12rIe5Nyv4fZWX2O2FNj9qJry1/gVpPhEj23l+vkmcxoRtz6M39xUu//NX0MSYqeJiIqzfJa7+dr
P7BPd9fhgpcrScer34jZsgbFFfHe8GX2XJsXmt724ASxlpPaBayE6y6cnJIY4mUV0vHI7B8ZT4o6
72kSEkYA7Ya3QslwixKFBzsNxkSALdvcSfQG7Bld7FazvlTVOHsyWRmghK1dFWtlCpnYFvxsN0iu
WDeo7yyUhhDkXg//HOKGIy3z4CW27faYYchiZzh8tu01kmj6qvNgygbblSso+DKmA4mnR1EqE2wK
Y/xQ5Jv/kNw4l7NZV1nRA5neEw79pJN/1Thb88uIuhhrRt86Df14wJfwyw/pKRE1RPAHUewqPa3j
ViZXgVIH8B9yunXcSHV2TVHgHMHQ5hoSrIMCkgKO3u8Ttdtr9yIgEDAKSUBlO8kzE7BzUrcSQ4oJ
MaGmrUiN4a4RjgZa1z0bUpjqRYEkZjhKNXsmjvsTgeQv65F8AQ74Bf03LM1+E9oYNsn7W/Dlm8rU
2FQzz41z5ZqtaN9JEeAr6SSZXBv59s6xeilLWZWoqWCFjZ/sqsV+GJeUfgceBFSwgr8EdQ8ocwQN
a/6mjcuWKHzYv+P/ngY/ZA4UYi1NXTEkRpqEP9vhyExtf95nD5t6ZdwpHtlEcetU6PHQYZfnJ5j1
Oboevfabv5qfR8XHAXcVAzYX4Js0uCnqbiR1GqGKxwdSiu8meMftFq1ger61gRhoyKFp1sNx8Vxk
Bc2z9c1xSGQ7bzjleCZVMO9RDReQpwpMAM96kdqoGSMJiLTnlOkS16nxvCgDO7I7yHa9MYY4ZZ4B
N+g3Y1jaA1O4gSBcmCOsAPrjdB+dViuPd/u0ToHC2TSbsRsB96zw/OwlP5yesedwlMnN7DMQ42m0
oVhgqPo667zXScw67FDRGB3tJOZ3s1ruUr/Jy+yBP0jcdSIoA3xmvqnk4TyOPaVP43d/XbEMQogm
1E6JtM+ZXThfk1OjdGxaFisxoy+GCkDIFcRc6tVdBElHX/QNFetRaLq7VcmMg26nJa9wqCgCH+69
CekhZWB6OrMAcjzirJmW7aVBLbq9hcMJvfciC2fnQ1ov8Vakj/H2U3DAh8IfBj6JBFiXgC/qVIGj
xtlIrRDCCl4bNm/v65gYw4ipvlpHhShB8GqLBo9nL/AdmlMDEp4xrxz4s2nOcHApDS6IdRkrKnTV
gLejGfWVqV7Z2nwUDoydXRAhEFjcNsu9gju/lATduEyTmc7RY31CeLtUwwPLOBWs1Ly3TtmWXMIy
SUrO3KQ7dcP0eK5X3YPiHsEnHEYkU4xTI8U+tmTrah9g7AVbqOUBLpAj3GdKcgkvXIhtC9uH1zhR
dbIyx/Hn1oO30eF2erKIr3MPgwv0zRY2+/dN2vLjNKMNT1ph8GJ2edtywyp9ntGc5lxId+VO4ps6
qhYtkehtIoISTcw6vwdSGGz/mic1/8QfyzTKgMir+FGwXmyN2CMyDi6xZHA9MSeGBkl9C8yrbNg1
TXcRDoI2fsPhDRhCQDO3KBAOhuWYNb4YdO0ZLa79U5EuD/SC/2frUrxIlvQSnqAzrIi56d2MQkE0
O5ooakfsnl3pDx8l6DAUN5ddKfHPgVrs73wKana8eMWvqZGztzWwrZ4pui/sDsnjPFkIk0OLYqhw
baneozxD1v6nE9TxqHTOT64nOyDCmSl6sIWTeHiy3tp+vr3tTTyHFAoA3N1plWIDliv98VRRi8LG
TbTUGfbP46yvN1rOlP9vCk54RR776pRRqw0i6RaTqEchXr8DNrkK3pPMRJtPLRO40WmBkx90kqZc
WKPWiEk3VhaLvKb6ZLM9UtxrM3khkD3r3K/CldE0BdDUfksstBZDZQY9Y46fV/IVsChJKljF/YBp
C9kXLNOJZ0bf52mwurN3soCFF0sOK+aZQA3tEnh9DWYjUTghbjC1FDwPK3BvgAZOfK1xir0wWfrp
q2xvTyyhTv/II+3WcTjxfpxAKsgbqrzb6kY7Tv8cMO1mIr8eE6R7222epj8LkDsEzfVbfTENelR0
NdC1uMHOzNrHiKoglLZl87mXovGyZ+QTpoGjKcxJSI0d/eG80VfWYZxwuBEgCQBni3Eum7wYpxmX
R3dh6RPuFhuxq0MSlh5hLzs2dm9Zc/v1gVby+Ru2DUJJd7LvAW9j6hIJs91mUGnJ6KEPl216tc+M
UKX+Brj9fnHTG6waThBmU6FPU865J9cE28Ql8j1CtikAIy6SL+HVaDZ5kqNLJuO6WOOCdR8bAVA0
/32Zyt7/KkLP61TtV0B1H/XlZ+MN02NfEhVdW3LMVg7/Uf06KgMElNCC39bJc2ede6KrU8aHnCVc
e+YQAWx+S+sKSF0udu3GPRKm2hD6zU/i47g8TYEROxocfapP5uPP1YTHAdy0JwcVsRyKk2+Pi0ag
iiE98L/IPn42ctbhynb4c+Rav/bSumtY4oqKOZ4Fqmt/KzyXCPw14VyKtLmpX7mTkqqrxVPWsF4I
eow/E6UmjVlL7ZqCjC6jEABu3w08QWGldukaWS7jRTtUfTarXNgbh2IZOmvgqNxloMJzWvnOVgAp
iQ/1nTrDYYDDZ4V+Z3jlOoNjc7quZaCkMlV+3gmP6ZbQjkzhQJzq/KuTOI4x3slhQyh0uPucz7u4
IQHc44HdeBKJJb61eDEvbm0YDkwMaULvWYYmHG0uZR04cj0D22KUkbZNjNcbE3nHkh+uVeDRNdUs
e4vJVpvscJV1TKjyNXotB/k0+/y4IHxjzDZAdzvJTjOkqDw2gHag4EET24cqpXZ7CwI517BMTsB9
U+TQ+GOIpTfCV9IptHtzMf4zHgEn2vIezacngu3iUnAD2LCT5xhqUJ8+25oIBGfOzgsQbQbFU2wd
XcOuPt7C/sga5RWoPpLD8qp1H7vIaoBAl+SaN6EDEh7zXw6CUBIdcWVKDJl4Md91LWQLg30inuQD
EPc7Sc4X3MvG6W3giUq+4LZ+Ps4ixxVuAZAgRmrGkk469/gtCgfF4Wzvavzblu/kJybFwmCGeJDW
oxIYCWxhQJe/EPuy8p9zWOosx9aWhMObiYalOwAjDwXk/YkDDRvFdaywbvYhTPkqvLNQw9qR+I0v
MHKv/IWE7rdfbS18C7ogr5VOwLaE8l6DeM/2l8iE/KYj5nXdtj1PQRQN7EBAF31kqa9I5AOn/4vf
L04kt6bamdLK1thAreI5BeHmgfK/KxUQXMbD00PI0jWAXOP4GcIVNnBVGz/ploZsAkbdXZtWobxo
JfYeSDjEDhdoJJXPGXc1F7GSdD18/71Juw71V0d5Py+WAywPo2EMyr5A8+6JlMnWQ2K/Kh5AvkJI
FH/xFugDF9pxd5Bgs/3z7IuSs6rVje8oml2f78RxjW9LnV0oAWUYC+7Q50lbB+aCGn1XIGiMDTzy
W132Ma2Mdihqd/oDdPRqrTj/4zqY0I9HlUME18qaxcorqsHDge1CpCgXdDuoqEnulcSpBzGQ74+N
v0xpvBfcSCFHEgP+zyR5x59xfkFmy0mQmarX0+QraMhU85jwCYATcwGkLU4mo79iTUkdY7fqNou3
9YuYCMKl9TTGbP9s6HlQFrZbcIe1/hVf1zdrk9iaSffXrx+JX1jXToXboHZa8wdENeELfLWfw4Aa
S800ZRQQU8T8KxrCXvDbD1RLhMqEiLkekBArRs0E3J6tHRP+KieFKKQMA6O1z5LcH6rkw1YVvhF3
vxgx4kBZ4xWlDh0X+NMr663vK/2M+kS147XA15Tcwzr3a+3pm+1COON4Ek+6wY6KlMxDEqaMuM0g
xGOySNrmMd0u45ix2w5ykwimyOnRqdven4gg/QoCxQeMMQTDTY83519o1RTZ32lrwNT3ULB5k6YJ
VMVolDLE42SgvfIvy3h4bIWy2I2YRGMOHTSr7PAwASup2RZUdu4E6/gZSqUfd72V97kl3bIc7Yip
MICRvfnBLHNN8ZIL0S8Pt21JRZvrWJIO4dH1ta8XtlJQ3A7u8Cs7DIHxxrrj+PkWhMrbWapfz6y2
BOZS1/O5W01Y+c48AISo0GYjH+Tz8OsxFgj4/GR752GNvqxBVQB1H8NVO0t7MkIIxwNQ2j4TXvav
BKt5RQlQCgZHStC8uEJCcOMMkOVijORhPWXFCVHHkcMV8Xg6Lqb+71qvhIUsBgX2G+X5oRptBhlQ
C8UCkgavaTYf7+kvtq8DJamOuE2aqkqFF2qMkTVeQS/XAKPeGJUUT29U5UCujClnQhJ8GywfhzIT
qeHq2u+gfhSFPmp7gM2G6h14RDtjCvDzimUqBVfYilrf2Az7R6+JBk3bCWeHqfTB1b6pivLld2Ae
6gJl/QYV0V07q8pW+1FCjg1DEZ3S8cpUFq/AVLPSls3Kb0LVsJxBnYdw9i9DWcnvqHIvR53DXz74
D5fo6slJ+9uoC2f4ndl7swQMw4iK7gXaVNCdc6B/78dVeYwEbwTRvqzab70FF32mrqoVSJyuXeds
a3RyItNfsNZf++xoEYVYhXX62tOnmgcvlI1PEhYQoEBlI2Bg0jfR/ugewuulCuzdu0l7BS1e1p23
NFEkRCBArjiKXdHKZ58A/LlYLbGHqD9tJISoe+Wj/Zmbl9GqXoJcBTx2tbhRHmjlaGyXyXNOnQV0
++anSfdnDcUbigYEFfNraGx8aW+RE8aJudQ4MUJo64l1mdbniCIrhzTndOxe7kLOPPJt45BNO3Y2
QxIe376WY4JDCIi4oWAS8ymjAnM7q+EuEtZL5w6RSKW886fMfN/1X85MgsJMHz0VegqFKxtfO3B4
jJRsDM99Ne1A+ZCbpHGozMQIbxcPvwQ1x9/V2NZv6mslQ2/fXa9QizMnOxpiEMAzHTxYOEsgb2Sz
rYnX64TcWRcz+8PLbxPYRFdx290TiYpTQjc8kayJsBeC8WCX9Y41CqBXZmDS/RRyUqusZYEnc8YX
OoIjf9Vl83CpIgKopbmyiHTQlp+WIiUalyMgUtLbVuG+PhRNhMFP+tvsz6NoXl0FwOoHCOq7tV2L
NiMABw/tz2WWPivwU4J4JtOd+lDJbOBvSaM0R9LC+VG/COjZ0C4k24toUW5xZDOAMOMQw3Jniubv
FcW1ywztHlnQ0sEWnAKmsqOKvXt5mzpvYWQ9yAK4GNj+gcHEuiCY7DU/29u5MNtkUgK0FK7bUD+T
u1+EIav6q4PWgzdIkPyZV8vw5UI+EuMf5pB4VGY0onGClnJAajjjLrxnY2vq8ynO8Fte0N8TX89J
7ExXPH4XaALNbNnZ4isr3V9ODyByH5gJFD7NicITiV/ze4SNx1bRe+AYgqNHpPwidsfgeLVjJLCg
4/lLOVyElHPNjx8OJMqx8aj5rTzfljTP+FNPm+BfpA47vpMM5tBGIc7X4cGnTwjWyTJzbRUqCcfe
ZYKi1+srhRcwhF6pXGVA4KQ/unqt9LseYkH46Y7kaCNBuLU6Jm3OJGediq7cxAFVdruozDB5H83C
hK996liEUwlw1wPKo0eR8KvI9cPHFH896IP7w3xBOiTjAFUf050PdJ97bQnHJLLTvCSa6f13O2RG
FeuSoLg9xksj3J1xkGvyusEqg7VJ4o7A1TwHq2qXbeQhTxbgR5UItj35TtR8EMjcyMqKudsKQFl/
wcnJsd05bhd0laSk/jwjOcwk6lbINBhnxj2Dw1+liaJDF+Za+qLFkKzmKe3mlkHOdwTipgwskvkW
D9qpkS/JXw3jOi9iPI3wkBFncPnaGDF4ffPPO41R7jQiwoDYlwniUZUMZWDDsh9jZWAx2Av7KxLf
fNul4dqN21DZuE6JZRdSDla2Ugl2fRNPcNkxLS6SAiDNaZoEEV0K0eeMhejvD+NC4KQjBQ10f7Vf
PaQpCSa3d0i2NsGxN6Nh5OIUrHRSZmNijEeQ5A8oamMAOn28xcaThZ2gbEbhYbkUCirMN9DavmEY
BaVw76NK8ERak+OdJEDBL8YttwnCO7AsOkoZWYpB9JB3pzLs0JJ1giOhD0I+k2E2eaT9BSP7d306
3FWL3GDjfsfWsQHj8t99ocwKzGUMY/G/2m5ef1iVCH4DacSCQnQCqXMc2SGPJzcpkOEGzG8+Svjr
FOOYprbWeryKX83veAKRzX3w5vQc5WP4Jb3lN3gCPyNUrU1jcp/8Z9xDBTUXH7EMvRU+Sb+OmhOP
t4TH3sil7S9ZtOWhFXp0jCz/MMyVCZhCNN5pD/2v8kS+qOGeRH+B3eXy9F+1rm+ldkAsJurnOEuU
xaV6INAX6vjmQYYgIqDk7qyMWYCwCgxzliMu2sbAfL9091A4B8y4xiSSodxYl3UzapRyKTz9Y7Si
Z1WKSvM3g5tIaLUhI9oooVrLxA3liVMq1S8zmXOBl1bdy0h9vl6wFzRQltn5WA4sMbjpkjM9B2Fi
hudsMrB6rYSsX4TRgkcJonS7QEcQonWtDC0aHOlJkz42FRllzZuFNSMwiq9gKiilds+Sg73UaXDq
xktXh66GbZRIQAmxGV31XEIvplz4rEEPZEhnoffnY0zzGJkcYMz6AvHROnDcB0povkmQRRDACSEi
tCPxEa1MQ3YildtTaq8jCnbb94HyvnTSrPrODMbIialQJtTIEaV3xu081Hste9XaMRQsWsnP6jt9
8M0uqgpqfkgszR/KdjkHzSb2fo+RUJqr/Jp4NP6JvzIxS0IiNoQFpXjz15na4tckvp1eSvNuRagE
rp3QlkRtqfEWlCi6t7yMKBIUEkREridl/ue6FMq+lwg2QqLZjIk23/i3xMRAALjAK0+FvaQubEdt
N5kB4MAYn2iXXx/sUlbJc5WXDyEn1eYhK2OtQT/sV023zno9ZWC63iKL3hfD1w4+b41TqFpxVPNt
RHjAZfYlbkjy8E/05UbY07iJvkpLusm1V+7ZGAAh+zA1yBuDlSAbnXC/0oUT2ZtwAXyO6s18jc08
dpDmun/CDRzt2pEMJf5yGl14fxsJmRL+evYOb/mvMYkHqygpSfyAQyS32gcGedmD1eNavkiKJ3k/
SiPYOsW0mAEbzpMu2/4bNGWQJT5rmD9gGzTdx7vmLlylsfxwz2/KYfK7J4wtoZNp8WeiYT/LJPNK
RQrnkapoj7tgZCRqlwjFw2vQlDDSjh9m/uJByEqzB9Ehem9W1pI1vQkA4jJiiixtAu7Y0RrjH8/f
rHbGHdwZKtulE2WKjdatwGd0LsH4AoE6DBBQSzTsZtG8Zz16zn1ZdBe37ZDA2a61xihiGfss/D9K
b+gnONbqHaXRjm8rs/Vu+x5ELq+5DOAxlV+LtTiIz9eaJ6rmkOXV4/CKbiWZnDdSTAoLb66jB0DM
5jROIT/M80oziQqYb1OTALzJAyEgBXd5lSjtGCY5kP3BRPCoM3/3GZSXFBsIT86ZFpT/a9PovZBC
i4Rs5lE0B0pimdkpIPHLZGXDasn1NPPEelAyzC+2zHHjcSB/GghPg3wzyaVRoEQuFkA6ieOXaXWA
hJ9SwpfDOKD4aY7R8t6U71uOt6ZO2Pjp208XP5Hd9+K3EXZ3qVfYusqix28niUkA8MF0Pz3YYyZF
YX7JLFQUaCd9BGP+7Xmj68VWiNpsDW6nbnEupIRoPe8rCvieor455uApU/BTUDjjuQwmUHagAufk
sWaKhzJ7OqlglknrjOEKdNpe6hKytMDGi7gf4xqWrtZktd8R26B5ZgDDOVgCmoG+R6ttyUiOrtQL
NIsnb8kuvFV6nu1I2vhXoJB/xA/OPxbNCoJsfQc9dbvxVuTvKsZqB0jGgrRqZUwkIHqq5Wi7PM0P
v0mGlFLOF2bag25xkG03OsOoKAdVrPdzlP7syQxhtL8ZHlLWpr0H7STPFA1LMJe9jIfaA8ABa6Bw
Pd/cAa0WY1D9imhrD0eI6QaJ8xeR+olgb48tSRQN4muQwy3sgiSCUjgoG5dy0lKBsu1AcXX6kQKR
SaMVNw/xd07lbstu3L7yY3dsIoegHo+XRYqG2ejsZVHnvGPVvSktVjRsIx+hBHpm+aw/S96aOqIV
SBl0/cjW6yKPUhqFSJF/rt9Ka86rGeonpMrhUoCvkwJoIx7wpqe/x1iJU5quOZyEG9CCRo8UZwj/
VrG6uzdBgjjPPi/yCkYIrwZD1ihejgCW/9NUE5Mxfwx04C2Gc/zFx40pjkz+OzURfwWhhK5PIVhm
EAWHqLQspeLVjstZym45xN+RD9oIi2KHeCQEerRWaNdy2Ic6xbm8V71IiQM2E9S2heHNQZvlaXwh
sgQ1BgDuVU0ZUhBq6421prwwbatEh2+q7pPJcdjYbUPTS9jbizH5kguj5hlF0u/+5o7nO16SFtds
SfDFTQoEq17Huka2qBow4l5UbJltTQDuNK1+nwlW+MDH/tNMC06vT6BlyRLgysTkfVRPJeBh37Z2
FVwJStvZZUg6IC3uI26bpZyEtpz+ZKhrVmX9SzzTrmCH7ChEAtNNMz/FfA9q42yp53YEVIKwYTjv
NCEvzwfRVsIqohfxsoGFP46XgiZ3EE7ZYw240kyV+gMYZQKIlu6h8uRvOVn9jQle74+RdeAcvfVu
rA7KjC41dBOOPjcVdAqbujAWMTqJXmfWl4saEP6zaQ4MdLXVcl9H+PpFkyhm4onDcCcA2mgVLr2P
E3i4PrMRLlV43Yv6uHu+hziwwwJswd+Ew5rBzNrTr+bJregZxqYTclB1YGZOE41REJ/qpGHVYUiP
HOEUx4uOImASRFCSFXIwLysi/lNybhqQqXUdYmESPz8r8PJKPUJ5oFfFB35DkDrr2VsY3Pthj5KD
zRNYYpbFwAG3/u03ySyOSbdfN11rUK7mb+B3pSMrlFX5rjzgnSGWeUAA170NjtrXWYOLqEXS34CC
0RODSQp+ffrDNA2qP7V1Bmezj08RCnztioWBCjLwmyxYSCSigxai4IqlxgjsFuGPbwOcEgKy9kjB
mgiE/VWfEmKwCo8s5FpOKNumMbLPdYUq8EkywfMCziG/3r8la8kRspEaLH+XQiP/mKYjA2q7aItn
84EpFYdr6ZLKgbSuaz6rGsSqBdetSSq5nb74wc2Lv0DqoSP2V5zebK1uJoEiSVhAEjVxxiHYq5gM
xPpieznTNf8frpT8TamnqWSaYcp+4xRFxhy/ZhR/zx5NAizd8NVegbFpGS9jRFG29wFKAXyjrDMj
VziehGH45cpUKzkw/Hmu0zOfpbDjfnuj7fRsTsOVdS9cyWk69ZjHq4pjvSCp6AjvueHycFULpRen
KH8KkZ7mQE2kbGXajZmC/uNA9Sljhn+XC9wXIuERZU2xx3hDH2rAQ4xuoCML0piwwoP5ogwGluZk
nVZ3eh+ya25RHQnAnU0Ucd1wN1Ir0EuBV8k99xUmvRkME6YmsGu80ypGndv8iDH2k4p+Gk63WpJ4
jpYO7de/caUEOXdY3sWGEE++r82ZbwMWy6nnNv371k5yMBU8OmK1VYLT87WeUCD8h0rase6R3uC+
EzcwJqNzz+X8voNFzCYg6zmqPLEaE+8WaeY2Y86oI+pI9LXgvjq7yW+L+pG7Ho73YOgRhDplwU1k
Qz5jOii4bonudxQ4IzNq7Wc8FNv0jQwLYGg/AB3IpgYag84gMG6f2rcQcFyKOqzv0Ks3RZtJFE8t
ALPSzzx1cLXNe2fSeryNJKicPdByRPICEUuPDnsRGLOp9fJXPseMnH4yUCWBFqCnzNQdsgYplSIX
HrkFfZ9QDQ3ausHrh1yLL+BjjKiPSGTm18IbKeARjOEIcpfsK6W+hogdL8O5sNEKMnwOrYNXRVYR
ChXJZ/j1bib4/nNySoFxG5+wCSMSj9quysJV6IH9HNRF0K89XwhwC/CXD95Hv7DH+Bx3IiHq9gvE
iHuOMyPtY8dBVO7+DOmaZndcyD9fP+7tQLwk4c2mgHAGLz5HuKDrACkYQPTEfPKApTAU5YRjWd70
lvlo2x/19ds1ZOjpgp+NpKDNfYARbIVvaEXEaloc09OGqFuTAlFhi/u+yVHyot3vPx9HcVTO3BJH
bF4TDO1vofCp7C+HFJZQPJT2uFpXEMeohm6p8Po9IAbKMuqxm63FPNYld92l3+fAhDCRPI4rLaB2
fzRdQiRkpUu2D4FFiuMz9J5p8DCU0KaCSsBCAiy3HyhBjvXWjZhW+NANouIw2J7PpfBkfVPF6c+e
EDhCCysn4cL24EDYrVQJ6nqBtuIGFbumplWdczHWXcjbJi5x/mcKfWrqx2gq05if59jBRe1tBvna
obWV3Oaq6PsDw2DsIqliwyBSmm1EFYn+2cdQgl1u9xhw+46Q3mcspyZarnkUbosYxGaIkaRkrVJL
Zi4cFkADxIhvsIz1U5jBRfCNw6xuzD6dyDQOL/8QKkyGE46p5EuCvTvLz6ivGiwt2MoayLomHQ3l
FasBS4gEgZaM1q9tMnQIAbSgLwEkStfmzUL2eCt9it9m6azBgS0EUkh1V7YURNCzucaZUQSSicG+
wNvW2YJXBereCfq83+ZGqcYnA/SgJLiAwJxvky9yp22wXlifxKJjf6XOIaRVnpXddm0vf7QSVWYZ
H3fkILXXik0Lmu+xe3lRYePPt+e+37hKhGRptRmOmXljxa2CVWzfTk/fQxnvDTHFs5jkTWpFqjUG
VL+qrXbfvU1dg5cZIuML3f7+LGK9QaMYKhSTou8rpk1jChuzSTAS4Z2lwfsH9QmqQJlkDqjjHbKa
fUmNvdA0nP05tfc1iJOiNfBNGzqhjpy2P1UA2YzCXXBdgLo6Wz8fYCoetPEzxmVmxLRJfEB9Fp97
GPA61x+oAJBQ/PVEdeyzkVXr5G/n+3r/xuz/HMIqzLVq7ZV8GRgCxuN40aPmEUT3nNKIaI9Y7M3l
ra01lQKwWtPqEMGv+tpBM6x+mD0SaWGDZXv2NBzOdnzl03oz9XIOfqVKbZAEQWlEps7bgQ0fOMzu
7WaNjCqd3pnt0TTKeeyGADWexad9JGMJ+19irrzkLkC7YL7II2EU7Njw7+tE5WrQLCOFw+3f59OY
LIgjLAU/LY/E+TJRXtWirszhTS+arV2cSNBJk3Q74RjtyyEofr8K/2q23YLy4L2DK/PLEy1/SXn8
PQD6xBKcicyXSI0ZCMfDJcs4F8K788Ej4UkHChbpnLhZJdKfuxBnyQzQzu2jouP6Y+l8og3hVBH5
Ymb/bRB3z8hVtSRNCATaZZvmjmZdxiDaNq5vfX4l+kBQ86/mAF4BISbzS7YjO4BQpokI+JKnwtcv
yOGt/J5VYp/ApIUP4K+DhO9KABzJWXzEixAZoWRtyBWtWc6ZlHmv7oELy5+PTlM1ZauH45tUM4WA
LfYvfyAussGJBy61sOQNQCQeJqDAIorCN2tIoP/SRpUkoVBu+QiNDVwmOJOOWGMR1b0phSEnGWzU
74mG4lj9SP3fMNBoq9cLOWSXNVTZr/92AbilsqZcchPHmFXNeWoXL4pCLM0YBy5VT3uAp71uzCHq
rrWl6dxH0Kuwk8AvA0CxVtn3PyCVe7PVqBDpEY4/VUHWfSeVuO1+VWbd/qHvIQYSMsaKWBg7Rv6T
sWyk9AfYT/yWdJ3YFqBQV8Lb0XspU9LAmVCJVirvThLZc+rS6YdEqaZm9LxK/fW4FmGSCk0XPll4
esIbxjqB1GOfWNzMeRbp2BMYTFRjADcka1iqA2//dQDizgykMhMYmvrZ40W4bcMgPUgOxx6hLJ/T
Min4x04FmbjTaj9IYTnzQq6Vc0XPcAkS4glDP0ZYqlnqdPUJMfOkWwST7U+iArzyAqWd9ybvZJdt
kmj7+aqkTjZOPYwJH8EzsxoArsgLt24EV/vmpXc6A8TUX1bRHG1FXvgj3uHsU4/r4nOmEsHvXS2D
BkucNmb9RMv3rDtoTxwV50v+uWMhIhQK97RBt+wjqD9tr2MNM+B2V9/6ckS2GUL1mcJuew7VGndg
sTqCtZeptnsrs4e+/ZWEiVT7oG2EMCJP3n0A4yAUtpPlehEJGwsuuoPrDXcwVpNvn2HeB8EvMyw5
XtT/z7K3GRcHB/hN2wqmBXot7r54CmMGGeNFl4BMCMmYj2k+AnHc06UiFlg7NaSqPB5xEOEqG8aH
suyfBJse/kH49mD9pR2MecFzN0sfRN8cr+DADMTi/u3eGhkxr9ixOK+B3KKv8c2GRBYaGxD3xB6o
JRArwXJDsGLOJeCbZ7pg3Dg2+I9tPo2dIUgribAwSTrJYMfJNJbr28Z7/M7Oh5XYQe0zKz+N1J5T
zSC8LDi45FQfwUhwKKDf9wTZeimqxCVOHuhnbxs/c2Sw/2d2TVdlFjC6vxZc1P4SRb7VVk3kHgp7
ifoIgXrS32o/W2l1Huiujji8FatOCJ6RFWYW/BOQZvsAJ1ypoYvdAXdlmGOZuqYSUwHYB+q72Fz9
qSXiQAAoEMWNa3DrJ2SA4m5WjdGr4vLN4YD20s0aiQXgD7sSFAMqqltvOmFKPb6wzxxaMEFXxril
T6qHHW4eHn/IfxLXgn9vLxvN6liGpN0MJgH9ea7Kp2JXzubMfaghvUZnv2rP/bvP81RZbIm/bphP
RKyPG0SEtnu27gwLPEkeC6rw6m5Csr/ddxUDU1hEj01wfjtPP63a0A/0f+qTda6xCXNz6VmWxXZb
Cpu/noTCw3cjjssArwbsR9ROMCaNpS7krMtjhG9cmiUBqpYM+iPD5H76i79Fl3aWnsdE/Ir4Lq8R
Tqs/OANbB7wMWXzn/KCEmQ/YTzg+PTQeJQTRN8yU4qmEL5Vx0yaCF3nAe0jXpjoTCbBL0W6e2+g4
FjE3kcYUMi7TDVOP7sGD82UQwzFMEkWoF3oYNh/R1lTEhZ0el/dh2czwGN1U/YRva1cqd+bfHUfc
cNp0ocdSTRf+CgFZsziPuwuchJaeEPOKfSsLZMigsbY2EEYr7wOyK5vDHU9EFdWLHXJL2C5rFZxD
AtqxVdEsWvxGO+hEUNPuxaw028i/sKX+te281CJCEKFKsfL1IcOADJIACeXGcmit/0oraZw3wrML
hmc64PPVGPq48QWTE7j5gr3h0N+rQ3cwjqHza1WjGux7hPASHN21gqsXnAxWpgjzjWPW9ckCtshg
PvMHqY4w/lgS0XAs5ccu9UWqSeA/AXROl/Dhy3cZokXm39mrBZacIMtJDydtMMBiAgt+kUW1PtFx
0kcNB42uJro6kI9qLUXdYugetaHXouhLslEsTvJJE3olCLcOrLsX1AkFSCrwemEYD1fl56tC4r+z
fQQvG2yU10QKPhIlnz7WoD8YNtkFn8w+XLFrh1cxmX23pZxbhIXpVMRzrtKHX71Q6mfZm2MLqQ+C
xFuFMJjCmiebZoI0+k8qaqVlHHpj+e4jZC5hphEIIE9cchGI2YkpTB4RLeN1A8AuGDwzHlAulHX/
mdJpZfnDqOC0k1GLsoeJXJrKTL3L8VEGxC0ff02PjPVil+J03kGy5/o/pPU9W7JHI2iWRaMiZvE8
aiL9ukgWDSYV81RsuliMMCzFonbx7sDdkfOvYH2CHK3bz1paUqZ5a8NlkOLpDJYxgaThhY6Egcuf
iqFEom1q8jHzStNo88ombqpXs3PVtW3h3OUpzAbG7iMjxAZ0Txga4ZgnnGH4lfFWOgFI9aMur98v
kaAg6RCsp4ytJ1b01ZLwgjOaJj5PjJdX/Fxv2TX/ziFMP9dzH1Od7YDEWI1UVO5pBjmHVTG66h2P
0d4odbo/y11Gg7xHekj/SqW5sySmxXnismNkNIBZW1h3z+7DmF0HCB6uDjxq/WAJkzVzfdknMDTo
+9HnZhZsIuiR2rLvbQ1EUNFlptIaaCC99zbLS36uWlJKn/zebhl3txy+v3Kgn2pbfSKaqNSsjse0
jV+YxKn7hS26R9ys/hniw51CIsDcVPqNEJR9VjMn+z3fpqymj/LmzOgqlSKs81kAwKzNJtoHYqit
hFsiBbL5k3maT48PCc6+wcOKNR43lbQKeaVzYZW6Y3gkOdUg7/gQHphHxuZlUJt9N5HmHz0JKKpm
lymoKJ0oYAZ2yqj8dT1ki5SqIdCP+Rv/0BFeqqG6c2P6sxKY04KjVgt2Vlc6HppntMVEfCv1T2I5
Evju6EtdXnGvZLLdmD/+vLA1SbBTaykZ8aeULkjfvE4vJcvNkPv3ELbn6wMMIX2MiuSNtTV5r2o0
kyIvOlCPgFz9ceEwZc5s2WfryKta29dJIxyFvWL4vi6jzFoITTnh+CJYLhBYDeKdUaJ0JDnJjkjV
fNGjUi8xg599fcunj73+nDm22qIinrmk2ApujqzFwt+tff2OSvxTtkxa7M1/IC3GyGB23frWPK89
RJmD+MbjnK7PyyngBOz0nKbhOF3jA+GqeTDovZLNXtbs1DxBmFpNcAsxZ/DkfnJLt30gjcMbgCa6
S/LHoVlOIFDg5t61cZ6O7EezobzOmrYUfZeokDH9cJ0PbWmJbOMH2ruuYKuq6aG+pIHRQuI1xDNW
KcFb71ZeTfGQDjl5YiH3hy2n4XiYVoczBzuYIrPdTUDvF8hR+Zya+4f+oOKjH+kQ2gaJPHxocPVJ
XnuLGx9zRtSIrJRZGXql2ZuDGqksA/YKIGzzwEwH/BY0HAOoJ2JcuSKhcqBIy4BiTnVYhcQLTShN
i399VsKlDk3QMav2k++u0CxzXC88+k9ef55lYAs0B0vv+RaAJbfIUilfXxzl1BHTZMza0gqyqDph
uaxOM8+qfg6mT87PPeNge494VWxMPANh7hJDfk+bNFn1VBN6rDvPzmPlprXyzqGeh7n/8AOe2vhP
89CrzPnJsNkHXvOekamMrR5AJhGu/xL8myxIX+ZefaIus867a49ZjjdLqcj79eZAKNFGsnaN0lLJ
ukVA4qZBiWsbnzAF+4ETRbztrwzhlv3UsWFsD5F4mfB1YblnaUiS+NUgdkhyH8XX7n9gEaP7ERpb
EtzujgFfPlu0urcaIm9SRE2Nv9OGemgarfNgTZIygOqC3rOesJURwavJOJdMJfhu7zF08xw1DZt7
vEbkX5MnoeBpjl+sXrpuXeKaFgxN7o04AglVHwn36P6tPF83AnGwU0d+hSkmngO+e82TFD48piXB
n+G1EF1SnH65sggHP6c5qVBVQnvhi0eXMPGTPLlU4tTrjBHkdzZlAAREMtlyPy5pGmr1ZvXyLltV
DWc+c4j5Kcn0BdM6OfIDyH0cj8vrgscYHAdh+X2uncvoB8rX9QJIL7Io4wvpSo3W1bT6hZbVXud2
/o0PbkCdTL8jcQKNwulf3+rKsZ6OfygM4zFHQoAnaZSZg+cnu/Xr+NqpexdEwrjJ1qBuDs2rLn7r
k7dnAinXFjdALyVrC7uQdzTLNEqRulRiNEWubM869a4SkcLrGFjjkQPI6HzzUuIJvp/Fw5l1sRxJ
9nuTWhVYV5AOUfJ77K3TzUnOq/q9Vm7E6/7Ru2XmhfqSwT7oC1dpSIeWCGHwqBkSgOcuoVxATFFn
FpCQOxx8X85nkaIFN53U5PyKh+pMnFCHuxlxS1oXUMYpggElwRs9vRtkU63bTRwxu3dY8ro6Mwpf
+j3PzxopzzHlxbZm3Jdvan297ZMqaI/UefpswSvXmzFe7wnr/rpzyQ9FvgP/Yu2kw4057DJIdPXH
ScSVw2alxBuPMV6qXQJuzqg7s7obQjN11n+pmg0ctavrnQ87STeGaN1PTcFAco/WXEhKawdGwqih
lhN5dFEmflIlijnEu0wTmR5PYpZJ2vP0dP0QE/MnD3fIIDQqxj5cs+L5mNQ3eH2re25Lu4gTYBXN
+6LKKqZid/UBtqY9cQMbIMr3mteMvMTj1UH69EwUK7US82eIQC50pFt5qFcQYFNAGTcsZSyewNiJ
n6D5Km4330j9q61zDfddNacHBtYnZ8hr9Y7u9ESLj8VtCCUDq2uLT3BwZhdfe62y9KTuh49L8YaX
g9lR1+rhEKuR9d/5dExcFL8DuMa0W0oFaYV6RmSt9ECq7UJ9KSpjCEoa9+ue6gPKor4gqWCcrAUH
C9fa4mDd+7ExM4oDZ1UTugfadmF67+UJ1mkzHrx5zSljnFUahuk6GQWGheJo/qFKnvbmujZF5UDl
DFtaq2kz5LK66hUCWAASwwHDGg/owg4Fi21E5BAdn/zAkee8lMxkA5NuDA6oo5mlIjo08Psf6CSg
SPgZXxJBLR8SuqhJrGk8TInwsvRUSDUzi+SWDoNXE5KbhHRlvCFZugb+5WK8lx7XezV9iqpMxdyF
UnQFd49oRefgDpnBwHeN8AcpT9rW6RpdtIA0EEHRQoP0n/fDcWnVxkj7MlMXU6rcpvL/wsUG84Ss
gNLwxdBRtx1XxqmXJK9djeZXNvaTkqr7FM/cdY1J1yyiFlqWyoRENmURHnxOspXP/+r3IZ7qYmhu
+jIoUTU556DqEnQlwIqUyIWZjb4m03+On/ro41i7MGEP6yBZfMoiQNLqcjuelUnC4daLmZ38EPJz
leI3aivzGYUHaNlmru0JFyEyLM2l4rfQ6S2YhNZrieA3dAt1UL8dME+69SNRNmUJMHVZa9EHy5rh
6zfa0zVHBhOBONi85pw2bLJnxHqh8PweobVJuqzChvBVcr1LRkO9esmyPYNyIGDpRM+Hr2W4CchV
0jnUyd6H7XB1nY/SH8MVYUPSEUlBWl/lKCLzaftRxSxDV7u0O7HabOKMXIM8VX5ffIrtd+TaVPD8
XLZ0W/zQZTX7BflNlU9iJSSHJz5EebwNudgRtoSlAKAZZFjNkk5oieK0AI1rYZXAfIw8DoXUVEE6
D0TFK0CCeheQW8v9UTZEaWAnfEY+toYR1bW2a9+ZCp1dSXRfc0YZLHU6ExN09dy9gjJSv04DkePR
9dDFqt6FIX6Gng7jJIjz/hw/TcLhLMVqiNmCHA3FLhiZB9G8NzzXJg5lKbLEcecqWdc5EwRZDllo
YiTe51PiYK2ipoedO+JYrqizkLDet29r3Br+NlzVGFILdWhef3TCYIxl6bdo3UbaSYgxzjZ5Gv7R
aCMhZYSYbEiHcQgXLi1kDNu3kwliH0zLwa8+AYaQiUrtK9+nOy5ldWS45MnlMC+9CdkMGo/6A342
jjOaF1lehTDLNXHecJ0gdbdu86Gt8HPxeGvd41AFl95mKUiSsddz3B7Dajz2/r0OAdyY3hmvnGw1
J3jWcgneTxBtG11fqKU1exOqxATxEfdyJ0nkz45Ee9O94GltUnamPdemI2wPjuIvjoUakG+9M/Vw
JrSRQ6hefeGPc+0rU1czVmZhZhL8ywh/Jot8uMUt7OGs35bQRiU5Qy2vGfKAtdiGCz5zQp9srl68
tlHl4ND+hEso3YLdyzztd5QR7FVPgrit8MdKi7nhBVy7YzqpgusATv0u+CLGNZzroVY2ITtW/ox5
o4oataZXztQvDee9o6913KVhbvVK611RVyTw0qNupIgv9aBhuyogPc0ZJilzly7WhNs29AJItBE4
KkRcmThhgGT6Nabw0T+qbYvoY62BFrTEl7qLEYoatBxdoG48BiRgbwFEiHMkrmj5+IAu+bYhB7QJ
hnAhCr2/QdWx3qDpxdldf8iQK2NSABz4muong3VitxdQL+qHJkiI8iBvwvjR7QIb5JOfl4eQIISX
cyqZAb3kuJv+oI5WNawjRD3Ef2yE9yP+1aQddf24hFOldlnSop/SdVFKMZqKsNG4Rh/yjgq2HnRi
w3oU6JTwqtbUAw9yIG7UgnlAoG/ZbymoUDWVTC0BQy4nc077Jnd8/ySztCUaAk8KAZ/h4sLhhaMj
rizuHaz+jrPwAd+eweonfFNWqlpdFoLTL1/Xwuawn1fLzfTgB53G0S8zt1wsRBuzw+BL2znqszhL
A/nWO0yaEREtuafYd5aDNlIoQA5kk9/ltquNpmxH6PUm/mqi4gZkeXkaAhfwjNCU8TKHAdsng/G/
/goPPx6fzya9r+SrqVi0HF3MjMsq+4kF8cHd+mh8jELUF6R2nwzm3uffaTHjfH+yNL6nR+eSNOhn
nD0cANr03XbiHYGHsHgZoGNhzWAy/u6XC9ewCtoI8agzOn3eXQLoK75nTp7GY3u1KDE9CLgfH458
cPY/BFeKZU+72k7pY8WZEnZ3JfJPIEigYjGS5n218zTnkEFGtRkicHsz/sVMENlO9OblnzH1FP5s
uKr8RbXI1aYVlNe0dyZS5yCBmx8elzJLhth+k+GzqiN4H+lYFV7Zls57dDnLn3e6btE8QI269+Tj
XjtPZ9Ihhb5iE2drmI7z4pTIABIWoHU098LfX78OdzzU6L8/P5AvFuzET4vlkch1Yqh20e+MWlP9
UWcyU7Z/5r3a7hBzGTsBBBl/4guISjFYu1p+50AOSzF3BMgyiiTkoBcpLj+8qZGBULtF4P2lhlBO
aIOSfcVr8ZZ0owky3L4+zu47GZ8kH8OMple8LiItCB7nbdUOwol41qvKkDbjHxjkjIBM5SRF0GcI
EM30hNMEdTFK94bOu8xxMMoSPrspBxxIVzFDN54uCWB8ZEmTNt1ri9XmFcFbN/fMdLEO880o3EJx
yEt+J6gAxhzzz182pqNT3Upueh+dJ8bQ4b26Fg6nC4RQu278XZYuFW6jI2V5spB2IsOyVprRg/HX
S+rr31DCTBhgTJp0wg0bJl2q2UMvgqQY96vqD+JrrqzVNeSUHo2rh3KqLseZR05OJNGxFuZbD2bf
P9MJ/eLtrhrB+zZM5cy5aLrgOzoN7PamMXxVKz9PFbQwkKCDcvcOpTUcw22OTriH+O3ifu5rJroS
yBiEz+Q3TDEPBkqQ94pPvla2HEwj91F8v9c+nQrJCzv8JGWvQ1avgLv9GWaKTs9fPhPk6TGB2jJW
+6Q6UJzGv2xMAi4I4LlJvcwFVJ6G0CtpxV1/QAXbae2Y5JThnOYlDOKFdEP7LHtOmOfpUCoMBf8R
EO0zIzNSt9MXqOXxh53yvLQgK/p+ZcVO64rm44RU5FtbP5CvIz2R9oyVxYyK5PKPNi/YAVj6Xc2A
RchNs+ay3HO5z4xCLME8nBAYETguhWXNIXHX7U/lit08ju/57loxk3LDnL/xhc0FALwn14cVigGe
GAcNigXWCdIEE2gGAQodhZFr8hfMSFQ7gAj3fRYGhb8qxb3DBMKBQ5wqNq0VQxG5MfTQq2B+JJpH
0EIuoPgOCFtqqV1dKuoYzEjYx4rRvgHop9F5R49bP97RlOmyhuRq7alffw+57mTJzCxo42t6YMcY
ffZ6j8SejTFhjxezp6SWZXc8vg/SCF+2Pg6RdU/1IDmWB/QzOM5uwEFyzy+NP6kYo3bLRrJOfB5p
SwrCwo4SPuqeQ6Zhd2uQs1PdwN0/a6kS96jzXsrtAodHGuoFSGgLa04cu1NjfZCXBkRr+qCAB2Rc
7VuX2gur5EnJAyZRg7RNqedQj/Ql6EEgGQcySVE2V8gOalO98UCN7xzfMvXIOhv9/OscxGWmYWd3
4gCeBMMLgd+5itMBlu2406XzHZQoU+VYXupObAWCqkyO/vna67vBNBNEyqCGD0/zKIUM5/QQ8x8M
39CTtYexYJcjQhqlNFTshPXEzPTPnE4xV3GFA4+il7wHeWqDaqioGPHmUe1UOgwX9NeIIkNe+847
Mi3JD2kCCEMM/XTQ1GpspC6XI3iNNQnIOyBTKm3AJWNb2DdWNdni8utdRdRp0/eOyZNvf1D8QBoH
+psON6Nyy0d9XPnnewnPhE628kvCeULk38zd//MwoGOGez18oYS7hn7W3tQLD3VzOjzJioswmy2X
gL5+S+6mSdwgp4VGav2iDhiaF7w+SRcp0wXhqCk3QMAERuW+R7FSY7ifMH39NAYbnIAtbFRDZPVq
ShyQJeGLCmBdPld4Fh7OHeFgS7q3lxQCmRlpxqlijk5t/aObvIYu7eJBwpHLyQKU2kD+45HXvkPX
21o0Cp8TBkQpwSTqcUZX76xwOK+uVhzb/mZxVjp0GzmKRt+yVMiiRVgMOnwZis4HF3UlRiJa1XwW
5lhqPvFhGXK8/zXfrKW1hs8qJx8E/2dxdjmYKNur5MbpNY5Y9zsUtW7uWVwtGrejnJ+7xd74U9U2
8bJWC69aTpPFAeeUQ8TooSdK08M8H7YMbkuCoSEOnbzeov9fBv6/wMqlJq9DOHkYlgBQ5CyTxMs6
/ilJGfxvGSf39SMFjvZ184Gd8JL4ShBhT8COIBN5Sv4oHHlQt0RQOEB0qGpFGf57+a3+g5cYGqQ2
RRAxVlpzxUObS3cZpbO9PY2K+boMXb1G1hkw8wW+DnTq5ymsHIWe8KuPAcdsg02HzZycz9+ExjSH
adQ2S8KSp3X4dKqpe6qDrSlIDIY71aP2MvFPInBTFSy/bPgRBGlOLg2dXih0DylqCVBbonq2op0N
zs1uGYmBwy/nFC6Spux41jPkzVLl1xSVzpIUtUmG32ZNA+oVcssFm8HP4ihf8wZATteTe9ulEv9J
w0qVB33IsTEQtvzmryFlsopmq8VHzovdyYL+x7dTx/EX2cfQTgaz4yr0L/DdE8nvRu+hODkysawH
eU3v7Py8FSMU21k/bu0q8dA11CbkfVB+a+5X1T0OQhoqcf2YvCPBg08Xa4lykRiYN8LJ1vIQN5NU
JJ+OVFbe4GRqCJ39R4WvSaf4YXnkrh4f5oAidqXNGUID4mvEWWUd4Q0+3I+DJgLdhVK0QnGZy3Vp
bVeoI9DAbjpuU/oVxu1qO2/3QpEQpVA+zeB2ph8tD74iqT3t/CbX9z535iBoxPgfSHPbw9Uy7ioq
HWbjZBOouCknsbdQsDfgFgrqmq4OgYmaoEvS/oiHbSc/hofvuHPoOLabwa3cljmNL6ssVdMpciE/
KicVkeLhFpKWhbzKYKAO3PuGqygvm7JruTPHOvnsgEC9O8gXVhxuyBpg61JKDYIpa0TH5OsfsQ8D
QnqzeX1wHoYkCK+wXn6AdI/LZncTYdFnbswW+OB1DOiSaCrVWvhw1iHq+mf5hR/0lhzV6TzwuA5O
r326V33BbnoQC3CW2wDUxWx8ATsZOp34QLl66txWR1QB8+lAGIe9iVKTun3XokMMX5DdMiYjbJTD
cEtWG7Zp0gE2z8qiZGGBEJG9azUScv/fYflGoFkShYc3XIkOkK2YDT9c+qJPqvRauWPbtFfd2VTm
eubHFL8x7Hwaq/aLRdkkHzCsK/pTpB9JHn7oeVc/sJQq8XCavhSX13s1H8PvHZXFa/QmhebSmvE8
QLqcmR9HR3PeoLtGESblvCSJ0P4BZKqI/wWdrhSxuCAVM8j21+9kFz0olgIZkHGfJmdrVNYVE38K
v+8ErLi6VlNkkiXtl1k3+I1VzGLOrlDOmpaVY6UvAhnuxoJW1zM1F4rLLNRtubnPtz+YH9Ari2N6
9swn6nqGaflI8ka+fj9xCItUZpjUuGktJf4AuQfeZ7geXwj/9OCDsUBWaPOXeM54A2qOrw6MroOf
CUdQHaj7zjLr1/ikWj8nc5waM3U+r079sIOS8R24TUydw3L2PvbvQjzNLfZY30op1X9EaPIEfL3Y
7ZhZviU7G267+wre2CbbDVlLNW186MfgcBJ8Ibt+ruJD9fWpBSW//+Mpgm5pN2URXJf3KNER6If3
+/FRguPdNi82LqKXHv9UBv/71F9cI5xeSGhdccf2wWUrj4JAxSzDKZzQeDIzgtLYCJWF9IVLr0cp
AjHpBWffuyKs1CO4S/zhIMb1yrYR34+LE9h+zkXluSDE+S6d/+cnszVwx+VvTYNnI67UdhJ/eCR/
MAYTl4JBZcNwSwUy3oDsypEe1CoN3yQ4zLfz2UyVtcrdZ6/dpozI6MNPaEdAb88Yrdfg01j1JWcQ
EaNjgoaD2IW+1gPNruWNuifuZk2S3yPfBVGem3IWzoo2Mz+0vxqzO6FM6OX9r0CTVhGoRn3tt3t6
fUjJ5OinfEYSFyW4dde8OIFJ9YHagRQSztWP1oyLv6E2mnci2TfooGWifTTJmLK9C6vDczrRI1qI
4WkQKjX2ELv5PfYhhVCJhE0S1S56/Phyc0M2x1yV5w9Au2jqvyq6hOaSmXDWTMePfIxpVKnfo8lF
pLGlNz2sGXN/MzP0cBwa6pWvf4nWANAj2gE7mySY+i7cf3sS5cNPKgTr6g8s++50Xv8x3IEbGnpR
BuMGNZ7GNN1QyzkoSKtPp04ca0AE2wr0xsSHW77QxnjLlRGG0XucR3wM2eDJy8qhOtiUkBjkkWvK
oheMkBiOngfZaoZ1AaFQVbTB2VHFAkZffqrbNI6IAD/NQkVm+Xc2BCTEaLUwSVZLMaNzbhKNxCl0
u+q3HJCQZwgHgu2BNNT+Nhx6dLkHRF76zLF03ufB3eOd9xheFbqDsXNWTqga9Y2+NeZ0RCe+vlgv
2F8RuCwUYJDOwWxnzOWQ+tg73ubJVlkN/D9uq3CXi9L1ZJpDiPtuMA+tQn0TayarHSuzdBeyg/OC
3wvBxohhT9yBXWNgj1Uq68nZqQbfW92ceJooKXMHll5XpbGZTBmDJtsUU9rHBflRU4IT1RDufvPO
240dUGBW5geUAmdDAlKg69s+m2Y/sgtWNuwaIzzS8vllHRxS0X+o0OkNpCcDh1fc9LnKk1c0CJT6
KOZgwiv2QXZrl9qJ6TdSdy/z7xueYbONnl7jzLD4q1LLQbUdO+xlPEhuCIBY4rNS0DQ0UY9Kw11r
hNnJSbITBUxj0yrlrYEXz0zgbhPdD46YY+cRkfs2u9gLFjyytQnWeSZOMzApSiFyrKJB7gPVC73I
aV++QqIiUnuLFPv81HqhXGsfOplqF/hCZoM4fzcEq8isa0vwcFoCzRNQDakJKgApXzi85+SjzlvP
52pnemkPtJBrkqX+a5gjng6yWYnwnU45D5VJtyQL3mRnRjVRI0oFVDNiXeSslk6cvfMtXJKxBo34
wD7V9CWjexPLRkNasDr4OxOQGpKegbndyeghXK75TexZBa81r7yI0NAL+8z10tTWP90DKbHFpFAm
jYaE2YGMwTO9JqfngUz6XJDVHSoTB98D6az9G6CycmFO14qv/sX9+2TSWee6/PQvVKcvFxhYKGRf
GSPi/P5k91yWnWm7QyLDHtI8R1deFZUpAPtHPA1YP9NOtos+3VeOnKDnAmTz1WHyJbmPZcW7qgb7
3X2h7wEVdTpeYPA1FnGA61yMESgqLcDB77LDL2mHjEFx4Nh3P1iiHu426daB2iqZ45DKOEmK+RiP
SY86x4+ulBaYt0X6zKbgSrF3CBVKLFLKDJ1/Ku11/YidBAL9k8qUX1/9gSGCDNRb8eArWd5gXOKd
SSZZf7PmG0GKs63lff3Qusb5YKwLiGeh74PeCsdVgZ2DPUUwwxbm5N8Ua/PE1Av8Sr8oOnIYNZkI
gD5Ef8V4+JSoOwf8QYCkuL89Bpb+gOHn62mY34BiHtAJQp6TY48S/9SRwzTcPABexa9686f/1An+
emac8seRZA2Jrs9KVNgI8ctmZhc9l/mgAAbs1XUuNap0cF8SN50X4NhWH2xidiu7V6Kd9bRdbEin
mWFz5Fb7nx6ocvW/9YntA0mNOPdKgsrUiq50ROJ5aSzC+LJmgiqxy/e+M3SxcFuDKV3UMC6WeIi/
i6EpypUwqlW8sJgR27kFboZNzgIbqdF7kxp7z1B2BXWlHlYJzm55c2vDR5DtkItKiEUTUZlG7ET0
7oaxbFYFEMpgUVcI/FSAxAv+WjT96TgR5b07KU5T8kuuyxBg5T0BSDnkQxwMlKfY+pQ6LvuE85QZ
ZVCSYDNZlzUjNGkpic0JeNdlMiaEZ/MStUcjK4Hya8N9oNunTtCkryGLsHnKqypp9JYEgEl1fzLs
u6TMCQfX5gtFl1yMuzQqO5NF/sz1jYTTuJmPumiYbZjfCAMUWyio6HZcCa2/pvliEgxPdFsmC1WK
3c2Er7kYVwLeQ0f87K9/CNI7AyJj8FIkDyHcB19hpAQwEYjks0hLc6Z8KPQpMBDvNKqDPMX0JmV8
/MUi2sk1BzFnvENNc3yeKmageao4rvpW/9GlfUjepKC33s7ig3OhFw+GXk/mQNqHTqP2geEt7VWr
GTQMWE7EctfquCZp8FJbh2M3RjifS/hMAudeon6nw7WfhN0FwN19khSUjl97lVVTqzpOg+SdKrcz
c+iofWStb1YFJo1ccMcU/zTG2sPT/Sq51ABdEyInL5IIohjM+UUQLS+HuaMRYunxHWzx+8ocAQ9C
UuQg8z32uJJBHE0pQ4u6el+0GyQMFYZTaZTnUxIdQnvQItmKpHhMbSYy0YX6BsroPKHFtUoYBvN/
42syJlK5CGD3RXRc1+sy7Q6RkooWg59W7zDMBtrqZG2PfOhMprQqo8GJtbA00ZehbpyhBbUDUnUA
3JyWrqDDm/bsqBBv7Gu0BbiI+uW2XYUi7+w7cO5HDAu6ZrJmjM56D11qQWVY95CFb7oR+dhkDCnJ
xSlKSYc+Szarl4wqOCU74oufQYljMCYT+GRw8Be+VTcXWNxDqrDYU13q+IFQg+HHMER/nHvpwfY0
+E+s/A5Ss6ztVvGeyZ5I0bMGSE77meSTatpcYoYto0ZETLRVWMLnQsjoJUC+7idaMtNNGGKjtbC/
PT7wrat5xybtO58o2Wawvl4xzuQjxp5weu/f+9gf1T1kP3ABV3IJdBj9LQE6JzxVqEsFP0jqi6nS
vxkVxYXTR5OT+R4HYBYbO8X1IpUmV9aa+qJAm/V81c3fegjTOw98TkNVhskzUOrgMO8+kph5vpWg
E9RM9Ru0iOq9fw+CbLHj9C8VkHDKS6UtxBqYEH2Wgn1HgdT5ziMepFMxFGGyR8sDkrC2Krx55eCM
d3D1KwKE22rv4uD0JSoa75ubKrsjt+BHxyyXpHuL+Fo1KLFi9XJ2mom7rvFb11kr9Ol3B2V5kCdr
RkZS+pf3ynTKa7bh6qXD6QRnXgjDtK/EWgYWREO3kLZhwRW/rl0/D1jGCSV0UARbMvbpiD38kxkk
/xRVmN8A7lJ3qBlfS64X1o1VausBJfrjSkid2T8pd7NLYwtsPzU4YU7UHXo/PClYkigsxQVZg739
w4alfcrRYGak74gBClbJIyCZKpY/Pb0IJHvNN15zCFcK/CaSn/ziaRkoNhCxL220LekoYmMH2xgB
ZFzbzh7mRd3NgCokwcsl1is8JjqU8cxq+GQCn2gLsEEf4AgdL58U5PvYMIHG2HrGHpZFzaVHI/ea
kfMSk5tdZijto0PKv+p5f2LMH1VMx2ZQf6GTu/4QGAxgGf7yId3QMqJ6rxfAkrQh9wwy2k7Q60te
sKspGtbcMGSqX85SjKwokHV2gyzpX6F942w6fE14hPPIIAGXxCLUn+P435IdwWcJdO4Q6uG1G8jl
ISIdjbn4ST4rDeletmRLXE/dpcMVaTPFeMDSYOCkXUGWL6iGFNjxdJoWxx7n5XuYMKX4+sa5e9Ox
6OUbBNS8E9Cu/pAYa6k8NOfC0Vzp5V7eDmgo2z5ZfwqdghdTVCr3Cmfw1ittBgbwL2Xs7CCFRQGp
AdCVpsRtj77iIPFMdb1P+ssxemZQwVIafQf4sqi7oLcG8U4Z0b96bD4l/aQp6WLfKTkFel6OKh6z
cHEVmYsRDwno6ybSsJjEfFeCQzelH6qx0Z+5E3nj51q5e1/DDp72wEQvbUQzHB7B09Z3s/FGP/Em
xD3ySUpwOK0bnjO2qB0iz5+gU1vAjY0+05WOGgO/a4mC5f2F+1KBR30b3z4/XWoSptjc5PEa/TJ/
N8oCSduII81GiOsLpXj0CQY2VF8T4pom4FDELhvNKJ17KuapeJS5eFMSfafgKGJ/3I/tXP/GNV1q
Rhbux6KQSKPVuvCvsR7xjDNWTBP4Nqsh32wPOVsRfAT1WZZfN0MeuuqUEg9yks6CRfWI6iccrtxw
sLiXx4M7wNIXGghiMFXSCRq/y+ColXUzsD3ZOFHAfcU9506H4mykbHRcsAf0eH0G6FYudmQkFNUC
rw31T21OgUa+OMXt4a8ILcAO3M0w7CcFVZT/93QoEyxxP4kAlkb90MgtTyQxYsBFiw3Qr6QEqZoB
oZPWv9rjyFCT/6ZXe6RtdYLewv9j/sNnhRx9ujQetHVDmDgrg3NArwtRSsaiRa1aBnCd1E1GL91k
D1BJngVfijr+zTHTjU7UthfUuMnouz1gE4StcZOu4rw3DyN/Lf5O63rbRxWb7/jvP2ZEV1zUaPFq
cnMb9IiMQuWT98rqR/9TYkfvkoFUPHS/d+xa/Jnrdy1vVfyw//k9X2mMiFgMnnfrEEB4BWQyJklf
S8AZDhUWlDciVHNa62q+M5+qht67ab4hke0rWW2J31c4xZLBsKFtAcpI4lu9GzLRysJYLh5Wzxx6
oxRvPQo6jO3+9BADpkcM/46Xj4iCjRXRwm0EBMt8nj1uxX7Bz4iaAcaJPYwkgwdiym+r4DJnTk7b
JapKjeUTylBXp1igOhVZGmurgAk2XTbxuMwsBSOWWzc3PLs/fDYf57n9TJfd4h72yZozWVARZRFN
/8LoAljPaXletYFuCb9WKTvrNE/15+nlz0zJ9UYTMDT1fipB0SkMVwSCyQI1ZrIddzxyta/Rx2Yj
kzEF9YdyRiR20ZwisEl4CMjso3Qs+74zn+mMxCw7/uSrB+we68MX8+4hlr73kx0IVyatLlRAludH
x8VqB7Xto9X9Wu/l+8sObmNyztLKNUgvy/OR3DruMgdF4cCrRG3Y0o04LhyZiNAIxt0yQJfDaCeD
NmNYARCLSsfAh6PdaDKvE1qAdhvoav5vpl4V3YKO79zpsPhdf4NyaBEKKMiB5EbR3tVGafOlsyYU
COOlN5XlR3HHkDPXifHyCHuiuE1N7XX3i5yz+m9n5sOxczdhpwwXfFtsWNq6IC+s2ZUeKgnMvSfH
Tdy1yykhYz4WRLpNGNK13SSOAOq22SPIKd8F8H8/L6aUhzI40ypKR2W3nxsi0ZFcxCH6aQMM5Pyr
GppMFUyJKVMk/vHcixW7ct1afb8ox4/OWqwzE/XXRUBHwVk4hclnU2khDQkFyWbYL5cQBiFENNbR
uQwJy6T8w6tv43qnLIrqXwdU7b3Ctw38enwUIRrtrNYBGhTi4S+X8l5XsDuwSuxV2T9Qql0lszrc
EoDVQjCcXkCsEmMf8oJJ1EB55mr8Y0/yPBcksYuNXPxlAH89hK32GuSjS6glBLnrIcqEIaOla0lH
n40lPVaAWgOoUnSn47d4vLnQJu6vCOhIjnoci0lQiGHYI+Jqpe1hmxV1/degQfqIWjDrgEq/vC9Y
G/yKYeoO0VEHtSY6f/drHbh2vYM6S1P+Sugywj6TB6hf2oz2Z0ePZOmrHalLBzqsO24LGLjbl4/s
CzAL89G28IEMH96aBwKuX4T+3AiCeZen103G0F1FEFVd56yO74DCIaiI19CXXTajjgFiEULvHrti
UhTzSV86eV7yuBcs4eVzDAZs4lprwkMdy1Eu4BYT2yd2ipb/59pL9Vs1yn+e9PE55SDPN/V3rk9q
FylOSAB8Exyv9/aCatvk8PbV/T4eKguu0beGgE+D0cgkX14VkRDG0Oo6KXtY/k3Toy0yQ6Zttdwg
6rinRQp3sGj1dEsY/cpd99EUmJ0im/aq7KTojYos/cXBzHKFZsEwgljKPL4otJkwCNlT8CZJ/KgW
OY2Pn93dJhkwn+/cXj3omBXMJw0gw4BuHMMOXynDYT42H+aYfrShj0Q8hAuzoLEsXWqnpr946tKk
UHPdJLQpNXRkeJNURQ+O1yXw8j+ABWIguA88PXPlL0wMO8y50VEEe7sNKNdNl55uOWmU4D/XWL/4
463AFZbJPn8BAAXxzU7T6lk0KHvSA+gqemmUntzCeb+/rFnP603mM+CGTDp0Q9fXVgkaIN90ov/N
/mfPBkZB0x1M0XoC35YP9dX7ZqSCihyNmLWJhIiK85nhzU+I0EVSjwdOhGwVCIN1JAaKFR0iLOt8
xloRHojrwbwXzALjxHcd17BGqRi3oNWg6yl39UEIzSMb6iLliPTTCy9qC4ws5mKam2hg93zYfRSe
64fRHSSspnNcanjSAqH9t0MuoMvRJjcUJtuwD0LxzpG+PmuJOOq/qUf+Ne0swR6XBH2w+jz4bevo
b0piWIQ0wnWeL5SjiIQQZ1kEnz9JzTJDXKR74vVhQEW1edKtnEiJTIqZlLYom9/Uk8pB1Qs8+OoF
qYZ5aLYm2H+psUCwEwKQ1ikSgLA5bOCLD+QZGdiuqusG+hhF8W8zbSuNZw4vFz2Rps0yAbCIAiES
+Y58B5FlTDhDBm3SsV66B39jahTBcXEJfIy5u0ArXr3oPWwATG2PFamF+EdCGnVU2JUANXBqGq+4
/RuA6JA81+yhZONYnHVuka22gvZZJ0n5hvOd+bEegm3VYnbPhWNglXbN9CWKoU/tBwWLC1y0YT9/
TghHGAVIr9AiMhoHBsnRMDoH946MSZFBAVr3ARJ17g6l3XKlsQloD9Q+HukvjO3lHql+6NpayOCB
q6QmDbMuGu1/rAtpTBK31f1GeczxuACq7x/cvjXiemwwtITh09u3CuYRRVzOyzuZ1mU96SNJvkFt
X6Fy60m++9w9kq8nLvDltl3Cp/26NyoOV22zzVJ1emcLW5Ty0Z2itCUQD7X+CPa/p32tOxLfzzUN
c4oR7zhO+I6TctUrUY2RZuBIB4wRZup1bh6bBRsILKCm/fISDngQtQfj8HrWDExryOrXNpCpBift
N75FfZpCI1MHtuernffhC41cUjQ7ftMEW7/uE3IUULXznfqvmWhTHKf0lXUTb8OcqrNUkyjkGdeR
uJViBcs2NHeSZvjocL/bwDPSbjNuITCzQ5zz/bThBETEYY7GeIdU2U5rkCSyLNrrrR4lxCBHnPqT
1a0frhCKwzvrcFGSKpNsRZCHq8aVljNZCC3b3ukjo2tnfQAFNSv/7RmUDLOiVmOCOSk14ie5Et9v
QZPD07WxXbwUDV7y+QjvjhuLaImiUaL3TIhNzsM0Y7TCQlmG6a5hN1eeOgVGQUOvglpjkDzt4TI/
GLRqhwqfdS3vP5IHKrALbGNhsS0owbxP4ZB3r3JCrWuJIk5yM0JiBHikqYvnKIUh5I+DzqSSuTBI
QUyrTNRhLVGAgrIdIuU1VicCqvHLrvdaqD507IxmHEqeAoqyxJ8Y0Z7ZHhbMSNsF/M7bW/FoABQa
No4viX5zTA2aMRrq3UW4x4PyqzYjz76MyMbqnCbJLvce4VuwFEwm2XU1knxb3Z945o7jzdUcfcp+
5f746Mi7snsmHeI4e3wWZJHcb79koqiH4Z7Slu/WSkJvIxdVIH4GLKvWZ5z7G5PUY47aTtcYV2CD
qVP0QqwQpofOaRox36Z5AyRjdcxW6bwbcS8RApWuXhY8cvTfGbnqNJej4w89AYfcI/TD6sHVGuC+
xqzOe9quTER7A9uK3GKegask2H5XAlJ7XzSgL60+X0UstYaD6sFp9r8Vz7Y6tOx+wdlPbQFQWWzE
hy0m5eWt3YkCo2YwoXPOKK37TqYRidN0lOqtovp85PSNuXwiv8AdO8VTtsMqHtAvehs+GSZ4OGJV
X6gP00HVHCwKhjql6t1qJQDwDmoyj+Kzo7+1NAyt6WCziiEJPzW1irsltoX0RyDx+2WCybx1jmc5
Sv/k9BRTf0OtXRinr3raZ+91c74KqormPgpLf31h+TNwIvwcvHEjybbupAtv4bEZNWrc+lHF7f7M
wBN2Gp1gB/6YfrIn05PciYX9FDGkrBUZXZJf3rX942iyn4f1Eig402EnEXBeJl4BbStJQp3ZMvoP
D1yNgYfObo9aJWbVn5PW4eUAIr6zA1wcODm9OmByXHB97a+sEbCCOBGy3adGv+M8YltiSie8TwRL
7tozdQ8PJ6dO8yUItUcRN2fK+KBrrErybgSZL0M24YuMs+keP5oWzk/XVYd5Qce43t4kQJHleUTj
nt+2Mth5A1uydGnPuENHZ6GQZPY+YG9y4v+SlcJ6EiOo2suDTl7fhGRx7pxyshbZdmlyxTlvh8ez
vT3ymK97Rt1cAxIwFlJxS3c+SfOWV7Qr2mEfK2Bj/o3qJiFp8z2mX248CGHxBjcBpMN4R4sFOUY9
bFAYyOkDTwyX3vXcMcmqoioh/LyNbExwi3Zfi+H4i1womheI+8vY22uIx/4nwhkVJStNmoJZ6yn5
Us7a2upLNWHIrEjHkm426fw9JNOcCgZfDNrc/mP8igedeqA1R93ZRa75AhJ1rklU/NuAOLtjLoV1
SIo8/tdAnLZfgSYQgVNsW3HFctsEQe0CTbgYpmJ31RtqE3/tQjsSO78dBExA+2WiAQcG6OBkc4RJ
7ssnV0XMtPnwUZNQtVuAKnUb9XGctLg6aEFLhowYKmPvigJvlPXnxfShZ6DPAEBMsB4TwE1oVwBL
KAJ0jgsYS4Dd8ugz3e3iD02H5ZBxLu/wmKoqQWp8euouJgBiFwetyf7yNCcgQ2hEh147XgDTtmSr
LRI3iMEc9JoTPyuw0k3rhjNKX6vCaNMuXeOuKx45fyP/ZBMosmD83cKgYfXfLw2UF3bDWma+pGD5
lw3pXeB/3fyBMCGKxFQQwpPt8QLdIk5LfilmaJcpWWilRYZSuc/eka6Rn+xAZZ9ZWDsTZhyOnnop
h8AroLI2DyqfDD7Oa2Wss+5vr/fBgfrwhv99vg5wecLdta7FpJikYuSScZuFxaVUFYjfJSqatBOu
P0EYwcROvm6eINIg3UXom15blkju3z3yfZRCHxjk6e7uxnzAmgKZCbuK4VyjV1Vx9fgHvK6iFo+c
9vCM0RQVn8TS3UOoyfbIS1ZZot/y80aiA84CHObhV0lLm5ExtCAgcBgfuslGVOECALSpbfyJ5Dtt
aAnjweqbZ/3jjzl/rG89bkv/i2BBZqIKX6JqEkFID+qsMo+bNN78FSnrHJA+Y9HM+jA4hd0pOhUw
bqJRDRYwy+ZNcDZP0k2h0Bco2w/WfG0lwz4qJXDFHE8mRZ5uDm8ZpJ6waXLxCsaJGETNXcCUlzWt
hwW1W8RWOVq9Q0KdsGbimKPp7aMtASsIXlNFUjT0ymxH7L1YdziMwExWtoTDhuAVHI0z6ycAXH/P
3REDDunGQeDbSQdtDjKfaZ1ysMGORwJqoGnBhvOkuHF4AL4x2n5dlMYufjfquZ6bhuWTapbleC/K
IWcNojl1awAS8xMwe4vajFREwimZgTMxN4Xi3rNHFH3WyTOXV+ayNxoAsA7owLBRMbVa+/GYUOPV
kcrl6KcxuvYmxhaFvg7dohpiSlsg0JtH+7/y2039Lu0rs/++d+TDhd7MKsPHbVyHzEmCsIBtZdkN
0WuGlclmNWdu2LNOXHsa+8ZgzackXu29OcBvtQQIkub+ekv9NjL4wnzdEfIvU2yOzJu/zXcMASpJ
WiT0ZACrANLYTwRLJThSQMIW2XNvwXm3nINTQEhYKiebG2hICaA6b8hdaGC/UfkL4BhnKEsZie+M
+jvNrFwJDOUeObCwKygz/Wixi56CCI2whBRWxYDQl19H8RnERxFCp5hPpbAa5clkW5gxTcjWjWKr
8dtTARh4OBJAU/l9p1sJlmSJe1qV/hx7aloNsdcawBcUzeTYZE/pkTSADc2q1e0DXDaUDM90brE8
BnfvqT+q0K+wSrP3N/O0ZZmIBR6cS23979DpfEu6/xaiXLOF64duAfH0IuFoWvvgXirXborprKeG
cvb0G4omI2whudf6YeuzB99ksX9Oia8pl8IcoGZXEG/pvTtxFcNi6c62fUzxZtYgUPd3l5l9bG9Y
ygUSrj6v6StSG+oes46eXWJJxQbW5Py7uUu7++Mzj+bY0H1T3g+PtalEw5Yk5jXAreBhR9lkFG89
g48YGyyCQYz4A6pX57vTiWYlUnEXEzNK6kXuYFNexLx+zoMaKogqOO7yZZLdcSzAFHwmb6eiEnFb
yhQmiE05Oafy62ApsCpWUxV3f8xrGN3aK87vFuFo3zgC0S4vCD4fGaFEBVBqHGh1kK/yNoi9Iohn
8nKXB06+j4Mt+Tdk1S0tJR+QPuAn0UyzNAXwVYpV8+2IzzyDkOrotSZk8lVuMHprrE6gXibq5j9P
OCwhsjihzFaMpQd/KEmJW5t4/ycUe8K9HNwdPCs8AomIwiETx6Y1cvuiW9D9DOMlqT9gpAFpF0Pa
a4ENS5yLt45jE3WgPjHIZwWBhgyEGjyw4fDQ40e/Y1urVu1jVA41GPSw+IzlhiukiXuxN0/7zydL
F1b2trv6mwoF2K+Edf9raSwy4Av8JrEKuWG7cQlTpOUjzStUOfNBu6UFfNFpfjjiX6qKkNOtay2O
wxJh1rtY+ENK7ZMdlPzF9q/mYz95mHiWjUzaJBfKY0v+cCYISCqhBd9RkRpYRmFY8Qqnk1U1WAVX
3yh0Uxx7JLBe4O1vBTUNYTNMv+WuMwj0Te+1U9sapfgysNvXxbTfaBGQziPjZadi38AxCiFtRM/0
hQ6mC+6tZnrk5WwW6ryBFYrS0Lvtzy9+DyrGr4VY6PCwgQyZmTWUdA/gbw5JHTshYw9N++kZ+Jk8
pkybJkv0teDup2oXSf8jl75mseh2QSQ6JPfNMceKPnmOTeXl//D7BQvj3qfz7gf1EeyySqZk9ghl
Dm3d7AOhKNkHaqOBfIxAgrNVAQuWBW/5aTkl37d5CWC/Lzq8sF+x3o2LO0NiYJ9c9aGjXaNQV/2V
YtgaLH1PqODSWRONVGAhW+5dyrMaPNOeoxQTINZ/AamUzYVSZP/b84J1kGBFINorLsyb1mlTrVmC
BooFGgweb1nJRran7OUofPHFgy6N8Eva6lfov4wXUxCTeOaczam6epHP22eVnLVSNLlNo/DUXj/j
yixnLI0x6C+CgRvZbivWXwuiXGMj4Li+lQiL/+sb4zxCt/KpLojpUu2bxkBGCjVUIbCass5BepQm
VTdC1ICAQiNZ04KlwMk8FdSIfA4E8zTgiWwQU0w5jfXjafFsNw4X6oLdOSRUjZPdNYcYbleBGdS6
KiJWpoeZccDS2hEdS5lSEHgcGcB02ch/NEcwFPowTvvEOOgDGRbCD2LRQtNl0ILNBR+/CckX1U2F
mKkLseMEHRY8v3fcXUcTOhy5nmsdxfhPnK1kE6pqkvwMQlYV9F+FbA0JRSNrdA0R++bEOVK0/kXp
YJAyhuAlHNhatNzaEAwmNA1OnMHBnVV0VjyTKYl3K0sq+UYcOdXgJ+VKjw1c1Opyfn9D6kxNudhf
kc9Tqup6OZDlq++1xlxLqZhXAYFNtGu3ayFtmlqxYM7Sl4ItHZrg+ZpSh0uXnsj657ZU31PEaEKr
dgFpLLFNoQyFZRJSrPGhWepTMf4MrOZByFTgdUC1gf4AY3XqOUjFKtSep4uxfz0dTl+yMnTabn0v
Sbp4w8nnajhDRXtSwl86P8v3Q/7wOV+8w89c8G5pN6+7GG+Sg6OELlLNTcJymV4Ngy4QvJeEDbBy
jTwDmcQqCIGSJVaiCwu6dBNyZD3ysvSCapLNLjjFZbTWt5MuZqbvkyqpm8KzEssJHRLeEFwYMNay
O7ReYNFh4Vuk1Fc0JzZxZMX+x0MGvi7V3voLzCTWcmfLkkVoZHB47/iTA121Mpidgj6DOvONGknS
Y64oe8qdh4EdKq2YUhrpKhk9lWgb1fhURyywYExS1xaYIcoBT1nFL+RpW1QVus9yn4yFg2pp55Pv
lOWkKp/pIM1hpHWS5PKbiVrvngtINg7HWGFJgje3tp2Ah4lEzuDACVswYPNQAkT6fQ0vzV2nq17X
UqMVCJw5QX3X3x0DsWlUziEbXmijmvkya6+v63jhq1sgzNc4ZGTjhOuhtvfDkH9dFERZ54vrNA0u
jFjh6bh5nYq9HLBuMYmDZML9EBCP6MREtFUVd826Xlb+9Sx4gevuRfPRLMpb502WlsLLG88QlMGg
iFdk+edYQGud8f0wajbgP8pQIWwyjPxX5ha23O8JmUym5JMqPZgu3rrFqxJ1dh9N8A2lFtXwAols
1s/YWTg+sW2XSbYt/ZV05Y6pY/5fUGJ+ZtdsE+pwpupXR1OSXEfSpPEfIzI6iYPcy6JWZ62bGAzY
HAXZXRtNmSugtNA3+x4edcRqAkDKPmsHXhQdz3nZKN5AzgFIxpmlVWbaoH/JFdcaBkSMycwwqtLl
nx7b/1s3NrzAQdd3UUMNLJ50eyQb30+WEOzFlMPgtXNnq/WJcO1rw5A6W8N6AycFO3/VSLw7hpIr
5sRl9hc9PbUMbDzOu7lc/rcLOfDzFLUZR8eX8ZY/zJEuE9DpgKVp23NGq28lAFL3Hl76IVsSnan5
35L0WHfnW85FsZWnxUpJVcANUrEgjtQ7eSzOCCcp/CbFWsSFis6cQoVH++CzhfQMGfWFTWkrlV2I
9G/g+7oH9tlCf0YREzzkzYu03y/Rc0BpEh8oPlMRj6oGabjafwI2iVk6GFCVECy1wAJyD5Jjkm55
n+YBfoHXMJMq/Xi0pEQ4h9s9xARkAYQLthbScBbhjSX3mssxkd8zc8yvXGyA0EPfQNR20IyuMc3W
ixacoBmtdfg0A1b2jw1h64LrrPVf6nNELmycpOMjtTCb+pK7BtM1/6O86vX1s2TwUCbkkZeSYRIm
ThAl7+HsbOWWCfliDks6ONgfZ5kerXskI+Eg/792vln8ccZGuEigh+yB5ct4iGysyvbpX/bPYIeS
d4+BolFrt9/fQ6YCJfwk60ZDGXCYvzYH5JpEPJpMLSqp6793gr5/Qo3PDpeRj3IXqy8wHoeNExlC
G4sO8w7Yt7ie+s7TkzgjRGTsXblXGc0IMcsah69pzVBvnjthIffN8BeNOpAIkzhqDEyOXh/D8ksH
SyTsbf7EI8Z61eL8B+SFeonoxfcTa/v1n1t05/sI63Jf+yW9L7FSCyB8Vle5p0H2+X/khmuieApH
xLwdgmhtE9wFo0r3lS/UBrW+rFMwHE6WvXABI/xIRsxUwvZeFuNFNjl2QiuaqzL9aa64pb/elNpR
Ke94KoXPq//Y4sni7HQN85q6EKPWoBGxOhe6nybQGIafJZ7/xRt8zRUEQTzsETBOIOmaeEJenRD8
LiM1ev8kz8256iky+GgRed7f2rUw/2bFVwKMFfxI6Sp8KY2xmaThx9OYJZ8qFx3++h9wBq40wM8A
K/ioVB2eLQyA8rg46RHVP969bRZPqE8t0UZ6AYtY6ejC8qmxTquN/ZGNaqGXOsbD909FcmxmyeHN
Fx/5BEzncFgTgAlLk5i7yddY5hktRqSW+oommqOqZkHlREcOp+x0NH/cqj3naSzMoqtIO/12D4lo
6rI/loG7IHwrrxs5NfNxyHnTugktpjrC79FtWKnreIqsZHMqgZWYKxzZDEJ2pa1aJKBeTB0oCBX9
RXlBYZ9H+PBhPBAiig8/wU6IsNprl7RBHIU9pbTg44YfufZW/WIfL95AjVydEAIFATv9EFID1Lcm
YgDK12YHrHrl1yeoKNuUP3uDZ1rrVsZ4YlJG1tMijkwr25sYoUTm8AKqAeiA96LPKC4DVnGlj7XK
MVL/40+Dx9G/FcIIEHY1s9OgOxeT8Rup2e5l8ij2Sk1apR5A/LDw3ceeupZh4nL24JLYy7yJTUTS
WqOcdoj09m2L06Qa5iYfxRSrXOGLv8Y3G9U9FVrE9N1Pqev72PCfCGXlkboOGn8ZxW3+THBZ6uaU
2HekjdFXEupTGzVSwGZ0Cl98MabISGQhddVAMlw+E27q38EasieiFEqYVZKK0+4WciWW0yFZSu9h
z3bubIw4PxTzYZa1wrbn6jxBtBUxBTPWVEHpVtoOz0zu6B55gA6HR4UkTrOuQYJ4mNR988/y47A1
YAj66gQhU2wxNe/0sibm9rOzkAKNL5de7wR/1ght73MDLgccYZ4XHhpZdV27vK/91W6PRWy85ltc
dhQ2Mc4U0rMSRCT/cKxd1M0wUcsdStafNIWXOv9qM/qO2oC2RoPe4FntLiLYIBaMFJTUIZp6HutR
EejAzN1ndxvqTEaGvBh56wxKNeSjlXhgqWd4rIHYHdIZ4V/0O2ne9Sdxb3OLYDmh8wx/qX2M8rov
cbNBRKSHJ7KAsGhFcHAf+84BgTp55v/+l7zYKkV/MXh5SIImoYQVS9Wqea2L5SlzGzZgcr8Iv9VX
GD4FP3ujrtIW8g5/+qLZ3o0TQXo9dBpmvbxlEp7IVKQE+Vfrho6lQG/gDVLktbtmYgo1mckSNcdD
AnhR6U/KBPsNQ/iyswLHjGmwzZyLH7UKtYH9+fkrTZfNE8tBY3hjBrkLtFLsWq/xd/fLs9wkfyZO
mH7TW0XIKrF+oQuwpCGsVSWbgQzUxWU8RxoeNsOwgVRCAmbb6Jogackoo5OmOC4o8Hhgd55YCNTk
WYlWch0eFRaeGiLIJmahxUUqFVdUgKa+HrpEJnNxC57VRFFzvL1BNYXHr98o3oYWWLICDEjk+rUb
YpCzCDJy2qPvyOpdI4NWDhsvp3eCUH4spiy5jsfjhzNd5s8WFh0rbyaYY5Q/UOCkL+uJ6+sxESOI
Yfl6MMrAxUKdUsFUWcBJR8EYy1xW56W0iNhBDx01w+W0k5DABxEa5NNaPWDmieZG8plfHu2WL9KG
HXi17B9AANDwzBrctHEFIQ+oFS4rUthWpqS55scIVxGh/fZ6LllBGdY0JFQ5inDgLW6bQ9c61P3F
xdRFHS8oGVKwZaSsIafsAJKlqxLHz9qJgBvLpysJY8K4RQ21khOP2dyfi2hvysaLIr68/AolPKFT
X/DBPSfhWEt6mwb5EROu/C39YwD/mWnNdn61XNCG4/NFeT2njNnhBFGhmKTftnR0WlIYC6ZUHjPB
X39TO+khfMWUKchMXU08tHTahyg1lvtOEcmSv70wK4t0UWevReCD4QEc32WwRIK9Ix427dgUZEaF
7jmSjVrvLeEjx9uj4CtrPRxwBb+l+KMrNT1zVsU7PDCzbICWkfb4OZTCg2mTyV462QVyK1TTuNu6
IQLXevDktdVndG8GdFNWKkIdIeF44VojFbVe/PcqzHuF+n+NphhO1vIRHL4S1pACBdOaZTAQPPJ5
ccykG8kMGZ8+hnCy3fOhkU1XorfWVa2V6w2hKjp0gqg+KntVkB+QWPd538Za6m8p55K/5YwwIrnQ
bxmAqbCZWIPzJ7q5mVs2fXr4hX5euPtPQoRo17vXZA4lekL3l3Uk7FKglX5w2TQI0Ym0KpX0/BtT
Q3zeeTKHgqXG01psOzKS5dpilhsVKAdHPICbZiu3o7A8aL7q5WXf9h6/eNCuXw8nCMQtm0iyIEO3
+sbRSJuEFvMiGmPrkirzXZcc0twDFXFNAPs6lx3FGjbYumjrKvGEwJaHbpy7DOwjiC+hqzM/GUim
uWDhd8zKleyj7iS4Fmj4HUTpFrAiy0EAm+ysrxcmhfnccmGgu6Y4M78p3fa+Pr06vT9O7cZs8K3C
Mu2W9+8MFXWNdq0N6Nx238SoHaEnkYN5eV4liMpAko8ONOra38XxigwFEK91uG+Xgzj+/N+GSDDo
BNtnY6joiOnT6zpVOI6Z3SixzlpJ3+UT/4Jr/m/khvNPfRwYCC6PO5n7D+oZuFeuL2bNHJ5xFNJp
3r69pcSFufA+khv5gvbAWvqbgos3m7njLhTnDqAR0m1yC++Q7RS4+RSbfxu0t0tm9dWgH09dR+9v
qtQPVwMUex3RunPsyWpZlENBBCK7FAh1TRRyN2x2E7hNlmr/mrwXLHItcgCRGkE+fb/sg2SgkeD0
sk+i45XQExvEBKDYXz8c239IaDmWj/mfx6NQrnboyxZ39cl4UJJidYfZoz+CyDZjpliQH0q/MywD
u62gU0PIgcmHymEKTWVidIqWCYmYNPZCGIIfRjPzr1Sr8kXOPJOBJ9dF96mbHhVGk+RcjSMNLY4K
6eS4LANjvRF/xg6huvz1x4rPkkcs5LaMrzDCckDhR2NCODzXByBOTbcg/v72ZFM08WF35eYphi9q
aOVzIj3vaxPIFC6YgY/SEYxrPT7NhmozV22t/8BIuTC95msrKn/6uya1lmHB3iH/OzTBxBq2azSC
a33Nz72TVWj0MqaLJkQ32VK/PETBUxe2vXgC7Lwgn0x/Gib0BjjWwADiinDkRFf2w7oSi3jqeFmO
/hffEC/VzJHS/LoIkpi5CU0YdH0NhO+N7mYz4ggX18zYWeKGbwRhF06xa3wYwaHhq8c2D++enUos
4cdHZssHHEOBVJKo73KLtWWu30O0P8a+Ox05edDWoxFSS0nY/gwJzhwAWy7imn+cOOuHEQ0v+dgG
LpknyQYvxXj2yy8NLYgHn4vapTRmbb5gx8nhCDgO/uppEcGCSLhndVQ2OayhKmpOaCJOCEnaKQLN
CYxINR+VsA3orAbK/t0a1jdlaB7zHcruFddrmi2hFjq3daLmlWzLGLrEtVkXcA48WNy6uF/z1CUi
jLJphFDBAkxbSPrFppwkN6azFyjmhO6QvGrMaejFwbFEJU53MXtanJfC8pPS+kqMbU+wucVSHxyI
RudzGl82MJZKmBNEyYI7BlG7F80ka8takRFjxDkiWk6IiJf3PQCtBCMD7RIorveDaOp0m799Tlnz
vXuHTbuH8eBYBY6VoFgdZXuDShdlOCaq77yMkVvskWD3XQyGRDL9C3JdaTwbt2nOaBdMs7znjQYz
20AeWBr/K9gQHRPCOo7OOTUpkyT6KW7dcifusuFPG5fBcxdrldcCNNHF/kHaEidWeOYj/aHq3xPV
GqfWIARNVv03RJoixXUgnLEfH3xVJ7tIBvnQV5yL7ZsFVt56+Gmid6Y2SEvsU0cDz+Yj7hBSMgk4
yfXJCgVagsgPOuyTs5gPgrsEbih2CGlVUUfSB9OaJEc5SmarLL7fv5AERpZTi3UCE+OVvBU6TasO
pR7eHHxk6K0ankhx4r7kAfaLGxKQMLDak24D/iFu3i8jrZ+fmL7Apa5z9JND6BbdEZfeekhBdFTL
tadLLQRlLfDUJVJvvvVL9y2qJVCzU3zryZHS8cRnUq1CUUzNiSjuokr8xY4Gx2kkXumfaimR+d+O
KnZO+xInifMaIgrhYTY60T8XlbH+BSBmT52ZA99pjoci3DxdeisnFAtLmCU6pnUZHnWOYQDJIqjT
yRDmB4cBdYaBZJsAGUpxGCDY2oPrVtolw1cxL5qgRX1F2oj5d8tVbyUI+vZKXsM+qM3MInjtMm5f
fRxSCh5LxRdjhW1xUDbPkRX3JLl6tLDNDk79/GOCdAgfr+1aTBl19ogDul5O4RgKM7RDvk5Fxoli
/35q4hSYwm/OPRVD9SSnfYawvF7tlbWJbTFHgi9JLhH4MB3qcFsD3Zag+nmYgurZAtbqRwHfR0bZ
Lw0sll6J9uSDCKds7JW1vYSdrGbx0RIEBGwZV1fJDEICbhFo0ns4nNF4QPAuCZ//0pk6yAkEPt/g
AQwO/zlO4qCZoECRxo2LK4XFXHVJhetgVL+6vZx7u1pPss18FixQBum9uM+DtzQDmAHqzP+eFu9h
Asj/HFCz7xEOZhgJYFrgOvROWLGNmU7XUm1hyxBZfIdL2w8b3RzrTYCSI4GEvnbVgHBVBnhly79/
CULmH3UcBlK067LqTHLDTz8AAXoSsrYJNkCUuEQiJOzQ81kaqal2lac1HRgaNs4usZEbJ5NU13qE
RR0o0V9v7zNRFNjoZTslUOYQ/ETRWD69nbxjnm2+j+k2t/SKmo2tTEwLgRM4JXAvntmUy0jMPxti
zUCfeJ5L2f+LQWC8XaupdH3OceuiLvgyPVlqmWZSnXOlJaQvZzQZEpHSiYd62eHh79l2V+NlBQzO
nldg3sSg9TeYZc6PIhUNjkH4OxC2qQdpNf9aikpKoukGZSi87s0AqZ30qcBEfQTlGvqRfxPPycvk
3+AsNbztIi5hHNxsHiTrdUPVoN806x+9XbLBSRyoD6Toq+Pu8DrG7hiv2fz4K24cBzpa4K0qxYyc
czDukg9b9X5smrO1sHLwUza9TgLeidOOkSnv9b43T3SNVKSzqF8ApUDrTuweroDq1sfNVJT/Vh9w
FuFXN3+pJfmK6zq4+H/YN+MuWdaSU3ywKj4EuYEU04eaCf1HeOWVT/8b11oD6LuRPBZ21ACTWFk1
Dyjj+j+U9iMoXAm6RorBrTlLAdcrJ+BXEJoj6KAkYQ8PQ+LUyIH8SQwjDceJEzM6GGQZKy00lnpP
6t+Bf4oF2KuadWhNmPgDbfEBR2m4qtYDaNQzvMaipABHRhPqkRvctu/XFSK8769L6PNSS4engM5j
fW8H7P/tK18K96XbFPIsxPNLEHtZ7PFfaV9cPqm1WUFcDIJKXByn3ZefNsOeHSSG3i9QkySQn7Tn
XccMmm+PGGoiDbwHDHYG3r3j9rkY7wxs7iZOgH7Uiwu5DJVjlJI/ywD7+lHC46IFCUhXBSu4SFnZ
k9/YUQPfQqb6VC0XEjqFw5Khjxugke7j0iMR5gxMGc22iDA0TQwaoPXUGmkxoninAWfjuPGxyAIb
oBa79K5V8UMYIyvMbHOqlVpPUMI00Hi4FtIP669LktxcmK8PsTaEFBfl4y8cERlzKBq072LmH9v2
pKtc/+a6WtJ9PxgLZKkoTsmQ9GvNPHo4lWLdePNdMTh398eOeNdherc2r4vC5H7OyE4Kq+noaVUM
ni1aI9q+G0D4KKZkMqbxnrPqzsW3czdmRDmy0MSxoUyOR4lbOqLM5QA1U424l/pm8q+MJyOLo9ht
qCgIZyrPjGgj/EK9eE5A0A7XSCYRoyKw8Pf8jfjKmTt6Yg+N4HwULRQObOF3nOJ51CA27nm4dHWl
3wh1BDIWAdURMtHJswXnEoJU8oxC2S3XBJIPzPW4SSHMBikK6ithliV0rK34UrsMZHpt82PbnoqR
+1ye5SrF6oHNm90cnR0cnqrVxtGS9oTn6lW62tZXiLfj6GoZm9JW74bx2kFjMNRVS5oxBuzPyS2G
39RYv3UwBsH9SXeT4B9jMxDbutXdNRK9a4ZXygLiRGpUBc5C6Jg0L03L3uc39PC4dnFNFRoPmF6N
wRnkFzqxiEKDhdP/Sw327ZeqH5QpHfMeTC3eeSjgQ7sfrjAOWhHd6nm/w7MITgIVXxfb1+XlT4j7
6ubQZsnPKqOJiYySbIAlIcTNpyv29sB8vggH0UJztENSxYhYhmWhExmfX+FxKwSFUfR0jgvHtQjT
G9PPbzqP2duD+/513A+lophsTd2VPyhnt4IIvLJQuVE9mgFYDzRMno39o1Mur9U3OBwL+ODq05IU
FIoehI5KYM13jmrl3GitDFgqoFQEXp91LoOIvfWJ0o4ewbFz0sxTmspEL+nEEUgV8sG+IAyckbaV
CwAT6Edb+tSCewi9GEEJwH66tViMsXaaxo0c2BJh/+jAszQvX9oj8X015Z1CZh76LGwdR+Bh+XZC
xXij1wMFQdvPZ7N5/1wea0l4Xko7HUPKqROxEglmnoBYeap68nUKwEkFBzDqlGps0oqLWcDRf77S
WIbQpRhmO/jARmVpRHVx8IiKl25fl0E7/Nj14r4qA0FH9dALceBYNIcd4BOgtjd/f+8Mx+khS/Wx
6fL4fcbP4jttsTwKy54hLfSZeXY1z5rald9RP5mzHgVwiRJBgGT0IOxXywh7R3QZgUMH/5XfHjLX
mhyMqw7bLPjGlZuZxu5YapDvKmOrvUI84RSm+Fo7mBiz4c9O0GaPcNp0Ypyfj50BGfEq3bDeOPP9
kht3LvE1HxvvlZhjw3Tb7Zjebo8x8zEBdgkQa8Tp2jqrSQzLNHoV2W/n111FMJPNNwn1GFEXlib2
tsxGr40jaXH+M5Ey0iRN/ON1hnJ5RllPjbshO/TAhAi88SsUy/E2mrILo1FL9Jg012yJvgQYnlCf
ZXikat6Z5RJNt4+BK2pBjZUC4O++lyyEo9dwDlgZBPGTJLwc30Mq7NVr1jFQwUuB3hiiarSJ8kUd
mh7B0zVOXvW9tNLdgORonIswMkuZ5Mv6qPI2q57nz4qiGXEpfoRGGtY26xKhtfdN08Terl8qswGY
NDto1cql9o5r6WG7vO2MB31eju2Yy8QA7afdW+Q5sk6NyfOqmCt9WKPPdjdbGctpY1jmXfDL04V5
fmtldjm5oL0kej4NepCgY+45DJheTr5W3zp/R2m1qMwYCKdGVgQ2lpbt0SGvF70KF0lJwfuRE4Y9
HqMItlFn8IMCZeMR8b+Ly8VSuPJQ9gX3TMJQesYjT5t86kWh2ich7CZcGLwrPLMV1tBJ9YBAhOou
VxwWCYyvB4dPl98URckxtex3BNh4vko8ojcMUnEw04FzGiSQ/tee6kUvT9JdrrOwUNmzDQe4ZJbG
FSchWhWZABEW5u5KSZbdCmUuBuiukSTuw89nxpeZrmxfpZLypIsicFHrmtiNzRLCdbIxcA0Bsbsq
fQZX602jTCt7NS+FjHWOYPA+kXLDO12+PD9I3Da5/vMhYGILXbdUlpAUt3MJaIU77tJ4pujMTZZ2
Cj0SIxXbpdgsi5IN+3UQ2AsGT+YQxE0IJFFz37a6qRTMwE3oJQkRXzz9kZn5DnkcqrmDbj+sTTR3
SfZzoJPqQb7MdYBeDHl6xiqpPWMKP4BU61jDOxPNJj5NuWQrCPWgkvT4zr/0MN2jcqBWmrLsB30t
UQUkKFRlFiaQUJW729p2HwE9KkYe8saVyfV6JrSTYAdjsQMyo/EmTNleBoc1DIBsV2kn6L49c4HN
0gW3WPy0oT9osIAGwiRClWJRD/hqwHfOkxVAmH0wrIvOY8OSDGJiju9Xz0WHGYeV51J4RWEF0EYJ
eR3hXs6H2ABqNk6SZcvwIZsNHc5s0HTrFRqjPK35pJiVLYn4drN/m4EHh3/LxAcpyNi/SXOExx9m
M0Ae8FOb1TpO3d0thRG2y4yBBYzNBaE04UXNWDvq+pXxZBI3emn/YtIu/oZ1V516X0ebG1Y0gKeM
U5XmTBbJzTQ8hd7uWZzl5uplnKk+dnYnZSbVF1Cl2633+MMnF6nZtijqwv1j7bZscdn/BqJrGJEE
Q7sfEvwJIpRNSB/LNt5ZKtC/SNQ3r4IrmTKo2IuzVcqhmWwF4XMeparQOX4uMK8bnjv9mn1XuIoV
6/kF48aSd2yCTxoplkAAQqiudZsq98GSYRy09/Y6bRCBKQhaZt/5qWWC3wXOFqGAHDbiq4T62Uqc
eCAvhSPAgRA7trW4aWJitQof4oBPRYXML4t2wytC9XcgykjDZAZGhKBpV/84GJ0yzWJhRL363kmy
zHA3YDFtc7RwLl2hFCr+q3u7E9PJJATMD+yH65IB3TzD1dMXAAQWv2Lz3sWnNOyDpMG3n6tfcyPY
4lQG3BytE1t2eovLuBG3BaxnrXe2FbjQMvZZs7aNhHp+QY3wK9oBC4dPAU4CQCEI/fHuNV64E/9o
FOakXIKVXQQWRGxw0afgMqzKgzCt6AiwrHuXkfv5N3AAKa06clW7tANBl0fGQMRMwHYt04AjNMBH
ehjMalnDEPzS8msE0bJMS7sgdlbrMdRfVtdSV0dyjSLDZOMgyGdbzc764Ic6tSDbwMZvfXab0Ct4
Ghw644DIkjjqCTAHjBKa1ZYjdc8Suol91EXzvu3QBUaGw0L05uXTOwM1d0CP3fCMoLNV/m7/Nmyl
vOXBTykwtREu4t4qt8JRfRAyWUDPT4Dbee1OyCzlxFoEgaYSFS0AOYiOetBbe1FLX3bGJ3AD7F8I
CqPNfVxVJe0eUTXlMzjeS1dDMAo2FNczVCGMql2OQB99G3CZ7lBupQhy98wLSTgKL1pVsGb+ifHJ
+5MnXEE1U73m6EhBKDDpe7/EAaKxQl5hBSzKKDogljmZWSXv8ay2vlGVpjoKZUne+zLaYFTLyirj
sBZLaaN+a3JM8MhPde2RNT/TsD42ygc3LTtao588tpaKqlKk21Tm6tRp0ZBwmk0fdhrY1/2SCIht
zpjNsaNWk7w2HIvsD1ICME0i9teowle8njR3G6kU5fiXFjzrH1skSKOyxf1yQ0VFsRHt+2PGyO9F
GzOdEkEQLUgvP0t22Mu/7dTuK9etkFdncm41vdI8Gr055X1+uSdSBhtYGLVJWtIujVqc6jL1waiW
j0yzhPtWus7ychrQAjmRDA3OTBLsNSaK2cqFIL74a5sOno973o4yNinkAg7gkKomPNiRfC6OLiH1
OiU6ENDzmoteCIFvETb6g3vCH+MKYdacv8JWNOrQHl/cU903VO9NcH691NNVlhtD9xyuOPOlBpg+
XibkNBh1QtqjspDBwG/LXWXONk36cJxX7LuExM8/0qk+lW/HrXNxzsspMFh8G69qkusaChcB0thD
HZCoK5dKydnKwTuPqyFkkRvr5Zp9csQYQckxAAeGmk+uuisPixW6ZJh/kzckawWUwtL1IJZMqjcu
4OZSGp1Ur4Jj7waYlYG62l7oAchkMZz8dDAx9eT9Yq4ipFNHYMMR1O8D4ILYtOEfWBZ8sKZlhnHR
eF5t69bUf+SU33FI8M1r2EfGur+UmmQsdoLMTcoZre8uMHvsxX6cKHen3wa8/BCXK/pzqkh+/P1n
KuRQn/nZk5+aAXAAyxuYQ0cvRlbFlZvRmtLB6wzQSx+kxZ9trUrOkd2nA9KQHIsT5yjF9EgOpt/S
KrIpLVapRoHCpAy3XrG/02rrrt9JUTn0RYHqyEwsfr6C1dYGbPSZdf6yRJfdRWfWLgmxyHZ28HSh
wRaxARQoQyFbEcJQFHMxNnqd4rOiGuUlUJPtb75UMeKQ8kCVBGXAKp93zdrdCogIIHKCxJy3LRM0
KAFJ1TIZaP7aJ4agWogXTSIta2t/JHCIu5HUR7nh6AwH9VX0ISRlmmcPahSZs0olms5zd/2XNZyN
MDfU9W+0gPT2aEp8b8C562GI2TGGFgbrwmQT5OmOO6iwvsZSkWSlheqlfVK3M8kGFFrHhuFImrel
zTC2iliMLIBtvzlDqIJcfH9HAi1+XP3k2ZwgUf0qEPOxjIcvshSzsWYHnb8xJxx5yOalATYX/L1J
2nlaNs8qqC9FDTv1BOvX3F+ILKFF0t9chWfG87rBE9WwwsO+PyLjGI5i5/w372wd6gGefDBMAOXr
YcX7ApdkcyvIFpbyNUWRk7Ny980zihQWQ6GizsCOvRsY7eVwl17rAmh7QfHkXhhLLDIRQpmA7xKz
J7QExFFsjKEi6vRvRkP6Qf9q/+4e4dk9TvTGb2OPurG/seSdrFKsqs9M0f2bffX4cFpLid6MDY0R
+UR77HW+VITGPLgrbi6Xqq1tAND2jnq1ypNM1frqcz+JR78Eh/Hzx/U2dKGbQvjIJfqB0L1decQD
8ei/PS+i39ZQrMdvIkPyF3LeYYnPuexV6uRX36U9dnYGbDJOL7FFDUirbqPs5RdR7TKeTtbFJRHm
2Ef/VzHK2jmINaTZ5HBb65w+uWZLi41CqMsZdDc3Mn9c+7C7f4f9tilIpTWvas+ws4T+18TIgu6s
2MF4joYxdmOCW6CpQ38Bl6onAg/NUzBEO3F3ddjinQeX4ahj1oN2y9L+sdSwOBv8J4QL9rBf45sC
d9c0MZLW/lwl89wom9rz+A+rX/GsU3Mq1GtanMicDA2/V7SRBTuve0F43x0c/QfjIhGoLENfHpGD
Fm6JMidx/BYo9+whBbJQbq4Lz9kdtTBVKO1QS4+26xKpgktsuZu3axhur7+uYOR1SNbQlF4LFgM1
FM2f2b2sTuGWntD2F2c2hvnuBohF3zmnOOrwU5AU5OxrIsI0cykVuh+vFBnDzeDG53FDXen019Fg
bCB6O48ws036BFpfRT9zgLQtdf8ohefmHi/upwVV6yStW7qEnGglQEq9VhnOOhkZVCSzvFBkRifG
hNcxuUSV5qfkZbHjAUx1nccFalUD/1vDLXPIde17CgqVONsZEU+04fFovxVYCItZeVG2d5TED8om
CT09DkOkEl9vbq3UkCWisEP2ePvDBpJcmCVNb6piZzGMAg+SSVopuMj+mS8mchht/bge67ltG0+L
jdaSmDd8EqD7JdFFWEHV/wvrqstxByln9YFzqH4CxFKMcHnZ0/zmzUliAIMVQTy3n6IwJDQBpdf5
ujt6lX5MFxaLbFHr5jq23WOQdjc0uksNREBJPty3Cct9TM3EVAuWf978j61bLngDr2lScgFA6dMG
3K/7LZsBE12aPfggSb+Lg/AV99OnJ6TW64tBhFzATZgJQAOX8yiEfFHMaqbh1uVVmHMnq4XrL2HU
nCz9B2hFtPgCIq4202/ndQcbZA6I9OzdYUpC62o/aQqlg+/jJd/OiflyuVUjL0gSLAumgX8IGi9w
RVtTc5R4gu9pxNkQj3xzMItj5oaxl3myw8zbYn71+beO4KWOvkGUlcPzP9SIZVpW6UPV5BgnaorM
yqCBTzC/gR27lBMMhy97iuOWU2ghJW7bftC98QdTUZeyEWpPKUyimdVu5SOgqr1NSr4E+QFUwQsq
umIUqr8jvlpOiGOlXCfDVW4oJybE6BFvkofhSkyaxSnOMVci1eBldN7YFwHqJwCwuwJleaNKVLPE
XM9v/sM/DmU+fRwe0gk0ZqO3Glkxy61SPJk6Bec1x9h7fGAlLxGQ+oCNhehfDnczMOd+lkn2Tvhm
RTxtPbfsth9dh/QmGYESPBrT9igrb8fKnJRQQLv9rI2hs20yewcfW4Vy7hA2KBcg2zBq3EQsdKTM
hMbOZPYBsOVd5KqvbxP9kLlRtySUVLsEEmWsWJdXXmbUw4eTlBZ1c6O0aVAVFInpsTvAriUT+fE/
7uF8VlN/jpYSIwW2Je4K9kLswBIZEhmJrZ5P9BCJ3hrV+83Twz0BR/UjI7jGRj1PFHIA+kxpTjRO
BlPF5ckxj8FnM9uO9Lx0NbaGLIOqbnvU14jGhde0VpHVsAjjI54GTrU4nb5A5loUboofe6I1GyvT
H6medSTOGYxM0FfZxfYG417bFTItfIZ3qW3oSOZsmAWA1trkjaIkCWOO0RV8sp0dOVLgUo5DqdDI
4QWQ1/Yi4LpE5N2u3i9Z836BmTjuMUdHfRfaVjQNleOHQcz9CptaCbgWgKyrJs2yI7n2syyfWikw
xE2AgW4yBCGZsbbBSCUQyzEw6DtFGQw2PxImdHlOhF85BQkeZMObn7JvCo8c7aGiVVBp/T/ODkt9
XhUFFoludbdVHxe6tEM/fPsVo+saIZ9mlUpeNfrJjBgGI7J170a4jawZH+Z5670qi/ERsf/grhQq
0BLrRNqDFeb/oj0mCHGAFsGYqj+7e7jgALW5Y2dozyocp7h9/5qYnCVvMfA7cOC2U+7BAh864Jtz
OiOKDwC07qZ/9LqsDw6hEitKOJeek437rNuuxgtZDSgJYnjiOwPwhl5nrQFHBiRJqvYJA+9W8unw
C7lIKGfZJMzCI7+r2K6JvYPXCciHT9xx/dAmvfZQD0pK5h/xgdSTqi0YilMBZGURvFAuHPlTRMSu
n2wmRmWgURT8GL9PdQOA/9/oqR1Gc7pHgAl/Fh8mwP7+5Zw8y8qUFfIGOWRmb8lmHFbvBJw7hbWh
7L/nd0dJy24FCg6QZYdIONuqoiHlbpU4F16b87evjci9iL+ufnXU/+kJK3Tt4XZl1bRqC4bIpJfB
Zp9fgdSisJEIT55ZtHFNwlIIKpGSfjqL6WxxfkKquY2ImJHYi0O/4+0lkCdVX+D61a/O4OBXsaVY
kYhtH57wa7B7vlRAjdpSlSAIDkF0TCEd4epfkZKPOkAeLdFhxrBGzdPgz3QiuvJteDJzl95p8+/O
c0yfPfb7R+CSn1s1v9Lo6asXaetk2uybPcbTg/dzLSvOaABHYE/tijISmWM+5iH+5meBHDtHRuD8
F6Vz8o6uLA6RgkLyKkWKIBbmfdZgh+1+Zel4858RvDOdMESNjeBOjHr0EVZJ+nhpI6GUZupFpmmc
6whyzCSg9o82aOPe1bJ81IWlY6ojNcXt/OXMQTcbCq01Z5hw3P9yIjBBUJXN25iP/ft8hjJ/UsQa
Kpm6eD8DTBbCvvpE/7UMJLaLULKk2hCiIxhKTwaN+/GH41nL7wBsXAnoHGDVUHawh0tgpBFlEWeA
gcScEMT48eEKnSD6DUgcby8Cp/TWyMBOX74WXTpinHrSatzjR8c9IxOQ+FNxYnovGDoRN3SRSCas
f81FmqLUG33Whn+JNd2nUYEJtodCk05A1gWPbbfCD+VsTtOH4TNysPYofhAKQUO1fo0uLvCUPJIy
K/kT72LpsaFKWIKVKV26Tgw3kZZKJEbfvrM5g9hsiLruPZ2CpXLhxsH7OC7eEpzKcWjfkYqVg2bX
y3xwtEe/AVN8e5XEIaudbHFmrn/dhJpJ+6zNN0sPW1TfixZcZOZcfJWtp4bGgn6jSesr74D6Gc71
aPOlE1/xspAzrdZ59GK7+T2fE6inmxByRtonjYKyoXkIgA81+xMkzJ2sAeG0Xoiu0CCk/NBksTjk
o2+T8e57578/YzqBf3O6VqQa7xh+APG3tvZ1S3/ElLqRkCBrkTIUopMPd8v8gs3W2nN2RkNubXZV
ugPXP6YYLZ7YkHXFt8GgvNtegJLGwZAKd6JM45qqA0UwsSwYwvPgHaYZLeIByF+/26MS8qHGiKV1
uzGn0Iks10l6a7kEgWitIhUIfjtAWfBh7NVOPd+5r535bCvMGfakX6oQi7h+IZ0P/WmNuegpMwWS
PlJTLFLWt7Jv4BQX43AlQbgKvYvCi2lnYdmVM6qI6FbniPwQDnozxq4F+LFU+2CdPnm56WT5ikdS
Tq7Jt8fmVBrpXcRkh8QW3h736qp0ElL83nIdO4kkvTRo9oVxJ+AY8Q3Brl6J+jwWVEgZl7eqAszV
fC2f3sOJx2ABvzO3NZ6J3gIYQ6+dHhmtKB/mvgPSpys4/iDaf+JyEXnyOv2XpNSrAfjMiyUROqbk
toPE0vdmP93wRu64grfCg/BQsQ5ERh3FA6VpwCIAaPDWttB6diOrxoNfDM9kAupRIkPwUSRhmlty
OyiR4/HvKwmVpM0s5SWRqHUeiJNpjbgINgWul8LVobYL/u+MOv9psbRVZ2vqqXlpIGMFp+qXalVn
Gon1DleIUnxexRagk2lBb0bpkzZWil+bibh8KrWn4Jyn/iUoKPSVigEgCmGX+voMNPs/px7cwqwq
1yYKwvh9IV8YWSxcwGraE/zMM+Mqx7lt/bEfMQo4sPieC2iSf3g4Z5Bdbrhzuh8p/kwoZ+008sp8
4rADA4I5GpEFMuqKsWiAZYBmEwLpZ4EGSTRprwt2smhOYq33d0VNzZttintA83+dUppYqKDIkEIH
7ytNnKghalxDvSeaXQHpjrxNGaIKFopU+UKKw53SDb+GvA020zs7sFD/XU8L7Z/23gXIDC3wDoz3
KbEKglUDqUdEn02/rQ88c6yAmwX8st//C+sjRdu8pNLXnfxPIEG69KhMXFb4b8JjvNYZGms/cy6E
Em8ROgau88L0o0jzS3PRyXHvu+Q1RrNPEaG3MtUAWmf/nH5vOZDrgEncxXML4WZl6s5+b5hpBB2H
pqvHexcvWdIx00reEyuSK/JLst2aUOCmHIiNdJDr/C2UqfVk2h+3L6VUnaMthShp8764FrStifrF
EkHn4KHoFLg/iQdNaq1gLurMXPpxWQAri5FXIr2GZ61V+ScqZnceLQcs/vF91RcLO32tp9xsi4M1
Sv+q32XmrxlPIFJrJLd1soYEl4ofCZH/+P5Qxzo+Lh09R+RCGl8D5fY+XiP3IXBDoMTMkELWUtRR
bMo1CV1lMlQbr/02yvnSKzcpCoBg08MjaSwUJ7CjiaSTdi7iCJ1CbHUkm/aWguTc1AEnC7N2tWm2
ddpZaS3QmFNTDqOLI8dpnAkxt5q4LzMCrOsljRsmULpUW/sWFfWvQQoVhc3/i3z0JDyxIZ2nSN90
1o3s7CyiJ165WlpsewyST/5Pq2YS1WFFIyBXEyFUGEyvbZ5MuX9bEuFMYVAX5+0JXdLi7x4qDN29
bD8jRyvjftsFmWlvYDHgZyuq7xgYLbyO5Y/90um6l+yQjKN0N2VrG73kC8EY6Gt3e+vZyHgLY9SP
z2MvGiRLsKyz+zKmYTYVYqQTsnGfNhKypmXm/TNY3JOMTio01ElQGRMvWl5ScvtX/Q7PufCRa6Tm
8awT3FbYwkU9FNsDtHT63d9AffQOB88MoAR3LseXxh32p4euwQvDPSZ8am8gS5wRivNbGspP+SAE
Adq+YtoNdDEX1m1S5/dIkap9STGUEkAjLcZlXeURsiOOrskfmINHUrqR9X7B67Nt7hfKaaVhTqQq
96hRbVaji24yXMyjsOi1J8kPiYukBsrSpxKvYW5NHUyRypzyo5Eii0P79lHfU7YiP2hMkbSMKvOq
p6fLTIk9gQjxXWwf89Djs1s5c57vG1Po51CK6LUSx9Na8dpSqlGup301HG9wrWOaz41b/G9/q/na
v96GGC6c5ZSYQLdazfc+vqqWQRnSg3Hmry8oBsRHIPt+ABe08L48Q3qppIiRjh8yYJy8u/5BdEfV
0UAt8aye4NzRTXyIFJOd5MONLX0+bSVLtYIW2q54/1i2Km8nvG0qfk98t5ZbUCraWVkCGuhqRkvI
AhgkQLyNiMoNxLn3czFXmJsLY6jsMKGhkNvwgUFwKq+1PoBndQILlDjnlVzYG4s7hirxMXlkagIf
Q822Oi3KmSUV2oVl7sBsP555LShiYtpdoShAg8dMGBN9W41stDSafqBEfegdswqLwAAO9gEe860M
wbOrDAZgqLlDzKoBZgah044XwbNosNoL3YsbhOXP1fsI46njHJCkPShRkwBx16eFaSkGfB7cKLxu
wFQJ14COp5zMfVlaZZVV4eXvzfz2B8LieoUieZFRR9y9JQk9iApLl0olGFhmRQKUADslZguWRMw0
OXn/M1zZQvh/LIgCqLypSIEK4wm38zhrVGuwmTKw4uPBgRoDERCM5n5PB7U6xmIjKQNK+Y7ij/bu
h8umWd53k5JeKCaCjv1Jz2+vdtWuooabt9GyDJgeebSXV+0Ebiq/LYPx11ie/jpVGjggh8kYeteE
0BsCvQzwql0LWtWzQB5xdmsLG8J26XoErDjwK8BeWYna91Z7nJfX9GXGxaeeF74RAnmMbKi0N/M9
NEN453NJqD5fRdIogBJcpujimF+tHDLQwegVQYtumFr8fWJD5CBq+7an42af19pm/iZ0wPUvcj3C
JCOkHEY5OpKznpZOumRZKKWtGZ+gdxZiatbzYcSLA2st/xRkPOLGE6jU+7shifgtl3mNJfR2GYM1
jF1b3hMzlUjXEawMQdH5he5r7yqikUJOc8lo/M3m2p1GTVLG1kiHoI86VQJVtBP93s0S86sGo15G
eMZmnqhZVSV6RO+cUd3+/FEUR5T74kkhwlK/osap+OUUNdnCNredC0ecEZr3i0sIFlDGhWJqRM7Q
U4aY5XLDQlfLg3EKVQDGIDTWi8RZh8o6rHvr7WoGoMFBD4aDsgnjOl+R2P3TBWA6FoyR/hfS/k9A
824eh0Hgjx5k95kRsgC2QNf0r5kibpgd8+Atr+XBx3sYa3xijTN+yjgslm/XA+5L/DI8Yn6Hwgec
ahTlFUPLQ6D46fise9VkNLjGdx7/yQFRcSDroAhNRaeSaNglXrFVPUStDdR3NZpWn/CdSMbYN1on
BTFtVZaugUifFJOdD6KWaKyl5ZYsBJyy53LdQuVjAQdIQmqLwKuC5w4W3lc8UfH+4Csvr9NlImfE
9z3JL6q/urjOXZq7lVUc5VqR10byvXws8Jfu8Yb0Xjp5WA22zHNBqKth8IqyclONwBgxXLAxXlFs
v/jTERiWjMFR+JEDRpZ6C6NJZE9lUSkQP5NOIblSLugsaqI8PbOIJ9bSxsMTiHrv10PAhg48EmJb
TCwuN75CW7ySSgucJSmwEeU04Y7SLYQJ64oCangjALfBoTPEZjQRb5vOwMEezY6ilN0gm+dxL4kw
qxHHzm/9rWhrlNJ+qKHUn0tJ2cqs9VeFawvDKhW17BLMrJOX4vo4fdphlTeohPVYtpkNBn5knF2o
HXnPnnxS5p22/KcE1uzIAkKhr6H0BXQczuKsC9jWtT799/vBf26WP9cwTbLdrtlwksOwoycpYxGC
n8Pv2BjGHEEcdjSzkxifqw==
`protect end_protected
| mit |
UVVM/UVVM_All | bitvis_vip_axi/src/axi_bfm_pkg.vhd | 1 | 48475 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package axi_bfm_pkg is
--===============================================================================================
-- Types and constants for AXI BFMs
--===============================================================================================
constant C_SCOPE : string := "AXI_BFM";
constant C_EMPTY_SLV_ARRAY : t_slv_array(0 to 0)(0 downto 0) := (others=>"U");
type t_xresp is (
OKAY,
EXOKAY,
SLVERR,
DECERR,
ILLEGAL
);
type t_xresp_array is array (natural range <>) of t_xresp;
constant C_EMPTY_XRESP_ARRAY : t_xresp_array(0 to 0) := (others=>ILLEGAL);
type t_axprot is (
UNPRIVILEGED_NONSECURE_DATA,
UNPRIVILEGED_NONSECURE_INSTRUCTION,
UNPRIVILEGED_SECURE_DATA,
UNPRIVILEGED_SECURE_INSTRUCTION,
PRIVILEGED_NONSECURE_DATA,
PRIVILEGED_NONSECURE_INSTRUCTION,
PRIVILEGED_SECURE_DATA,
PRIVILEGED_SECURE_INSTRUCTION
);
type t_axburst is (
FIXED,
INCR,
WRAP
);
type t_axlock is (
NORMAL,
EXCLUSIVE
);
-- Configuration record to be assigned in the test harness.
type t_axi_bfm_config is record
max_wait_cycles : natural; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready and valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
bfm_sync : t_bfm_sync; -- Synchronisation of the BFM procedures, i.e. using clock signals, using setup_time and hold_time.
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
num_aw_pipe_stages : natural; -- Write Address Channel pipeline steps.
num_w_pipe_stages : natural; -- Write Data Channel pipeline steps.
num_ar_pipe_stages : natural; -- Read Address Channel pipeline steps.
num_r_pipe_stages : natural; -- Read Data Channel pipeline steps.
num_b_pipe_stages : natural; -- Response Channel pipeline steps.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the AXI BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the AXI BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the AXI BFM
end record;
constant C_AXI_BFM_CONFIG_DEFAULT : t_axi_bfm_config := (
max_wait_cycles => 1000,
max_wait_cycles_severity => TB_FAILURE,
clock_period => -1 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => -1 ns,
hold_time => -1 ns,
bfm_sync => SYNC_ON_CLOCK_ONLY,
match_strictness => MATCH_EXACT,
num_aw_pipe_stages => 1,
num_w_pipe_stages => 1,
num_ar_pipe_stages => 1,
num_r_pipe_stages => 1,
num_b_pipe_stages => 1,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
-- AXI Interface signals
type t_axi_write_address_channel is record
-- Source: Master
awid : std_logic_vector;
awaddr : std_logic_vector;
awlen : std_logic_vector(7 downto 0);
awsize : std_logic_vector(2 downto 0);
awburst : std_logic_vector(1 downto 0);
awlock : std_logic;
awcache : std_logic_vector(3 downto 0);
awprot : std_logic_vector(2 downto 0);
awqos : std_logic_vector(3 downto 0);
awregion : std_logic_vector(3 downto 0);
awuser : std_logic_vector;
awvalid : std_logic;
-- Source: Slave
awready : std_logic;
end record;
type t_axi_write_data_channel is record
-- Source: Master
wdata : std_logic_vector;
wstrb : std_logic_vector;
wlast : std_logic;
wuser : std_logic_vector;
wvalid : std_logic;
-- Source: Slave
wready : std_logic;
end record;
type t_axi_write_response_channel is record
-- Source: Slave
bid : std_logic_vector;
bresp : std_logic_vector(1 downto 0);
buser : std_logic_vector;
bvalid : std_logic;
-- Source: Master
bready : std_logic;
end record;
type t_axi_read_address_channel is record
-- Source: Master
arid : std_logic_vector;
araddr : std_logic_vector;
arlen : std_logic_vector(7 downto 0);
arsize : std_logic_vector(2 downto 0);
arburst : std_logic_vector(1 downto 0);
arlock : std_logic;
arcache : std_logic_vector(3 downto 0);
arprot : std_logic_vector(2 downto 0);
arqos : std_logic_vector(3 downto 0);
arregion : std_logic_vector(3 downto 0);
aruser : std_logic_vector;
arvalid : std_logic;
-- Source: Slave
arready : std_logic;
end record;
type t_axi_read_data_channel is record
-- Source: Slave
rid : std_logic_vector;
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rlast : std_logic;
ruser : std_logic_vector;
rvalid : std_logic;
-- Source: Master
rready : std_logic;
end record;
type t_axi_if is record
write_address_channel : t_axi_write_address_channel;
write_data_channel : t_axi_write_data_channel;
write_response_channel : t_axi_write_response_channel;
read_address_channel : t_axi_read_address_channel;
read_data_channel : t_axi_read_data_channel;
end record;
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_axi_if_signals
------------------------------------------
-- - This function returns an AXI interface with initialized signals.
-- - All AXI input signals are initialized to 0
-- - All AXI output signals are initialized to Z
function init_axi_if_signals(
addr_width : natural;
data_width : natural;
id_width : natural;
user_width : natural
) return t_axi_if;
function axprot_to_slv(
axprot : t_axprot
) return std_logic_vector;
function xresp_to_slv(
xresp : t_xresp
) return std_logic_vector;
function slv_to_xresp(
value : std_logic_vector(1 downto 0)
) return t_xresp;
function axburst_to_slv(
axburst : t_axburst
) return std_logic_vector;
function bytes_to_axsize(
constant bytes : positive
) return std_logic_vector;
function axlock_to_sl(
constant axlock : t_axlock
) return std_logic;
------------------------------------------
-- axi_write
------------------------------------------
-- This procedure writes data to the AXI interface specified in axi_if
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axi_write (
constant awid_value : in std_logic_vector := "";
constant awaddr_value : in unsigned;
constant awlen_value : in unsigned(7 downto 0) := (others=>'0');
constant awsize_value : in integer range 1 to 128 := 4;
constant awburst_value : in t_axburst := INCR;
constant awlock_value : in t_axlock := NORMAL;
constant awcache_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant awprot_value : in t_axprot := UNPRIVILEGED_NONSECURE_DATA;
constant awqos_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant awregion_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant awuser_value : in std_logic_vector := "";
constant wdata_value : in t_slv_array;
constant wstrb_value : in t_slv_array := C_EMPTY_SLV_ARRAY;
constant wuser_value : in t_slv_array := C_EMPTY_SLV_ARRAY;
variable buser_value : out std_logic_vector;
variable bresp_value : out t_xresp;
constant msg : in string;
signal clk : in std_logic;
signal axi_if : inout t_axi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axi_read
------------------------------------------
-- This procedure reads data from the AXI interface specified in axi_if,
-- and returns the read data in rdata_value.
procedure axi_read (
constant arid_value : in std_logic_vector := "";
constant araddr_value : in unsigned;
constant arlen_value : in unsigned(7 downto 0) := (others=>'0');
constant arsize_value : in integer range 1 to 128 := 4;
constant arburst_value : in t_axburst := INCR;
constant arlock_value : in t_axlock := NORMAL;
constant arcache_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant arprot_value : in t_axprot := UNPRIVILEGED_NONSECURE_DATA;
constant arqos_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant arregion_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant aruser_value : in std_logic_vector := "";
variable rdata_value : out t_slv_array;
variable rresp_value : out t_xresp_array;
variable ruser_value : out t_slv_array;
constant msg : in string;
signal clk : in std_logic;
signal axi_if : inout t_axi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- axi_check
------------------------------------------
-- This procedure reads data from the AXI interface specified in axi_if,
-- and compares it to the data in data_exp.
-- - If the received data inconsistent with data_exp, an alert with severity
-- alert_level is issued.
-- - If the received data was correct, a log message with ID id_for_bfm is issued.
procedure axi_check (
constant arid_value : in std_logic_vector := "";
constant araddr_value : in unsigned;
constant arlen_value : in unsigned(7 downto 0) := (others=>'0');
constant arsize_value : in integer range 1 to 128 := 4;
constant arburst_value : in t_axburst := INCR;
constant arlock_value : in t_axlock := NORMAL;
constant arcache_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant arprot_value : in t_axprot := UNPRIVILEGED_NONSECURE_DATA;
constant arqos_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant arregion_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant aruser_value : in std_logic_vector := "";
constant rdata_exp : in t_slv_array;
constant rresp_exp : in t_xresp_array := C_EMPTY_XRESP_ARRAY;
constant ruser_exp : in t_slv_array := C_EMPTY_SLV_ARRAY;
constant msg : in string;
signal clk : in std_logic;
signal axi_if : inout t_axi_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
);
end package axi_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body axi_bfm_pkg is
----------------------------------------------------
-- Support procedures
----------------------------------------------------
function axprot_to_slv(
axprot : t_axprot
) return std_logic_vector is
variable v_axprot_slv : std_logic_vector(2 downto 0);
begin
case axprot is
when UNPRIVILEGED_SECURE_DATA =>
v_axprot_slv := "000";
when PRIVILEGED_SECURE_DATA =>
v_axprot_slv := "001";
when UNPRIVILEGED_NONSECURE_DATA =>
v_axprot_slv := "010";
when PRIVILEGED_NONSECURE_DATA =>
v_axprot_slv := "011";
when UNPRIVILEGED_SECURE_INSTRUCTION =>
v_axprot_slv := "100";
when PRIVILEGED_SECURE_INSTRUCTION =>
v_axprot_slv := "101";
when UNPRIVILEGED_NONSECURE_INSTRUCTION =>
v_axprot_slv := "110";
when PRIVILEGED_NONSECURE_INSTRUCTION =>
v_axprot_slv := "111";
end case;
return v_axprot_slv;
end function axprot_to_slv;
function xresp_to_slv(
xresp : t_xresp
) return std_logic_vector is
variable v_xresp_slv : std_logic_vector(1 downto 0);
begin
case xresp is
when OKAY =>
v_xresp_slv := "00";
when SLVERR =>
v_xresp_slv := "10";
when DECERR =>
v_xresp_slv := "11";
when EXOKAY =>
v_xresp_slv := "01";
when ILLEGAL =>
v_xresp_slv := "XX";
end case;
return v_xresp_slv;
end function xresp_to_slv;
function slv_to_xresp(
value : std_logic_vector(1 downto 0)
) return t_xresp is
begin
case value is
when "00" =>
return OKAY;
when "01" =>
return EXOKAY;
when "10" =>
return SLVERR;
when "11" =>
return DECERR;
when others =>
return ILLEGAL;
end case;
end function slv_to_xresp;
function axburst_to_slv(
axburst : t_axburst
) return std_logic_vector is
variable v_axburst_slv : std_logic_vector(1 downto 0);
begin
case axburst is
when FIXED =>
v_axburst_slv := "00";
when INCR =>
v_axburst_slv := "01";
when WRAP =>
v_axburst_slv := "10";
end case;
return v_axburst_slv;
end function axburst_to_slv;
function bytes_to_axsize(
constant bytes : positive
) return std_logic_vector is
variable v_return_value : std_logic_vector(2 downto 0);
begin
case bytes is
when 1 =>
v_return_value := "000";
when 2 =>
v_return_value := "001";
when 4 =>
v_return_value := "010";
when 8 =>
v_return_value := "011";
when 16 =>
v_return_value := "100";
when 32 =>
v_return_value := "101";
when 64 =>
v_return_value := "110";
when 128 =>
v_return_value := "111";
when others =>
tb_error(to_string(bytes) & " is not a valid number of bytes for AxSISE. Need to be 2^n where n is between 0 and 7", C_SCOPE);
v_return_value := "XXX";
end case;
return v_return_value;
end function bytes_to_axsize;
function axlock_to_sl(
constant axlock : t_axlock
) return std_logic is
begin
case axlock is
when NORMAL =>
return '0';
when EXCLUSIVE =>
return '1';
end case;
end function axlock_to_sl;
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
function init_axi_if_signals(
addr_width : natural;
data_width : natural;
id_width : natural;
user_width : natural
) return t_axi_if is
variable init_if : t_axi_if(write_address_channel( awid( id_width -1 downto 0),
awaddr( addr_width -1 downto 0),
awuser( user_width -1 downto 0)),
write_data_channel( wdata( data_width -1 downto 0),
wstrb(( data_width/8) -1 downto 0),
wuser( user_width -1 downto 0)),
write_response_channel(bid( id_width -1 downto 0),
buser( user_width -1 downto 0)),
read_address_channel( arid( id_width -1 downto 0),
araddr( addr_width -1 downto 0),
aruser( user_width -1 downto 0)),
read_data_channel( rid( id_width -1 downto 0),
rdata( data_width -1 downto 0),
ruser( user_width -1 downto 0)));
begin
-- Write Address Channel
init_if.write_address_channel.awid := (others=>'0');
init_if.write_address_channel.awaddr := (others=>'0');
init_if.write_address_channel.awlen := (others=>'0');
init_if.write_address_channel.awsize := (others=>'0');
init_if.write_address_channel.awburst := (others=>'0');
init_if.write_address_channel.awlock := '0';
init_if.write_address_channel.awcache := (others=>'0');
init_if.write_address_channel.awprot := (others=>'0');
init_if.write_address_channel.awqos := (others=>'0');
init_if.write_address_channel.awregion := (others=>'0');
init_if.write_address_channel.awuser := (others=>'0');
init_if.write_address_channel.awvalid := '0';
init_if.write_address_channel.awready := 'Z';
-- Write Data Channel
init_if.write_data_channel.wdata := (others=>'0');
init_if.write_data_channel.wstrb := (others=>'0');
init_if.write_data_channel.wlast := '0';
init_if.write_data_channel.wuser := (others=>'0');
init_if.write_data_channel.wvalid := '0';
init_if.write_data_channel.wready := 'Z';
-- Write Response Channel
init_if.write_response_channel.bid := (others=>'Z');
init_if.write_response_channel.bresp := (others=>'Z');
init_if.write_response_channel.buser := (others=>'Z');
init_if.write_response_channel.bvalid := 'Z';
init_if.write_response_channel.bready := '0';
-- Read Address Channel
init_if.read_address_channel.arid := (others=>'0');
init_if.read_address_channel.araddr := (others=>'0');
init_if.read_address_channel.arlen := (others=>'0');
init_if.read_address_channel.arsize := (others=>'0');
init_if.read_address_channel.arburst := (others=>'0');
init_if.read_address_channel.arlock := '0';
init_if.read_address_channel.arcache := (others=>'0');
init_if.read_address_channel.arprot := (others=>'0');
init_if.read_address_channel.arqos := (others=>'0');
init_if.read_address_channel.arregion := (others=>'0');
init_if.read_address_channel.aruser := (others=>'0');
init_if.read_address_channel.arvalid := '0';
init_if.read_address_channel.arready := 'Z';
-- Read Data Channel
init_if.read_data_channel.rid := (others=>'Z');
init_if.read_data_channel.rdata := (others=>'Z');
init_if.read_data_channel.rresp := (others=>'Z');
init_if.read_data_channel.rlast := 'Z';
init_if.read_data_channel.ruser := (others=>'Z');
init_if.read_data_channel.rvalid := 'Z';
init_if.read_data_channel.rready := '0';
return init_if;
end function;
procedure axi_write (
constant awid_value : in std_logic_vector := "";
constant awaddr_value : in unsigned;
constant awlen_value : in unsigned(7 downto 0) := (others=>'0');
constant awsize_value : in integer range 1 to 128 := 4;
constant awburst_value : in t_axburst := INCR;
constant awlock_value : in t_axlock := NORMAL;
constant awcache_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant awprot_value : in t_axprot := UNPRIVILEGED_NONSECURE_DATA;
constant awqos_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant awregion_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant awuser_value : in std_logic_vector := "";
constant wdata_value : in t_slv_array;
constant wstrb_value : in t_slv_array := C_EMPTY_SLV_ARRAY;
constant wuser_value : in t_slv_array := C_EMPTY_SLV_ARRAY;
variable buser_value : out std_logic_vector;
variable bresp_value : out t_xresp;
constant msg : in string;
signal clk : in std_logic;
signal axi_if : inout t_axi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "axi_write(A:" & to_string(awaddr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(wdata_value, HEX, AS_IS, INCL_RADIX) & ")";
variable v_await_awready : boolean := true;
variable v_await_wready : boolean := true;
variable v_await_bvalid : boolean := true;
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axi_if.write_address_channel.awaddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(awaddr_value), axi_if.write_address_channel.awaddr, ALLOW_WIDER_NARROWER, "awaddr", "axi_if.write_address_channel.awaddr", msg);
variable v_normalized_data : std_logic_vector(axi_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(wdata_value(0), axi_if.write_data_channel.wdata, ALLOW_WIDER_NARROWER, "wdata", "axi_if.write_data_channel.wdata", msg);
-- Variables for the unconstrained inputs
variable v_awid_value : std_logic_vector(axi_if.write_address_channel.awid'length-1 downto 0);
variable v_awuser_value : std_logic_vector(axi_if.write_address_channel.awuser'length-1 downto 0);
variable v_wstrb_value : t_slv_array(0 to to_integer(unsigned(awlen_value)))(axi_if.write_data_channel.wstrb'length-1 downto 0);
variable v_wuser_value : t_slv_array(0 to to_integer(unsigned(awlen_value)))(axi_if.write_data_channel.wuser'length-1 downto 0);
-- Helper variables
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_wready : std_logic;
variable v_awready : std_logic;
begin
-- Setting default values
if awid_value'length = 0 then
v_awid_value := (others=>'0'); -- Default value
else
v_awid_value := normalize_and_check(awid_value, axi_if.write_address_channel.awid, ALLOW_WIDER_NARROWER, "awid", "axi_if.write_address_channel.awid", msg);
end if;
if awuser_value'length = 0 then
v_awuser_value := (others=>'0'); -- Default value
else
v_awuser_value := normalize_and_check(awuser_value, axi_if.write_address_channel.awuser, ALLOW_WIDER_NARROWER, "awuser", "axi_if.write_address_channel.awuser", msg);
end if;
if wstrb_value'length = 1 and wstrb_value(0)'length = 1 and wstrb_value(0) = "U" then
v_wstrb_value := (others=>(others=>'1')); -- Default value
else
v_wstrb_value := normalize_and_check(wstrb_value, v_wstrb_value, ALLOW_WIDER_NARROWER, "wstrb", "v_wstrb_value", msg);
end if;
if wuser_value'length = 1 and wuser_value(0)'length = 1 and wuser_value(0) = "U" then
v_wuser_value := (others=>(others=>'0')); -- Default value
else
v_wuser_value := normalize_and_check(wuser_value, v_wuser_value, ALLOW_WIDER_NARROWER, "wuser", "v_wuser_value", msg);
end if;
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
end if;
for write_transfer_num in 0 to to_integer(unsigned(awlen_value)) loop
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
if cycle = config.num_w_pipe_stages then
v_normalized_data := normalize_and_check(wdata_value(write_transfer_num), axi_if.write_data_channel.wdata, ALLOW_WIDER_NARROWER, "wdata", "axi_if.write_data_channel.wdata", msg);
axi_if.write_data_channel.wdata <= v_normalized_data;
axi_if.write_data_channel.wstrb <= v_wstrb_value(write_transfer_num);
axi_if.write_data_channel.wuser <= v_wuser_value(write_transfer_num);
axi_if.write_data_channel.wvalid <= '1';
if write_transfer_num = unsigned(awlen_value) then
axi_if.write_data_channel.wlast <= '1';
end if;
end if;
if cycle = config.num_aw_pipe_stages and write_transfer_num = 0 then
axi_if.write_address_channel.awid <= v_awid_value;
axi_if.write_address_channel.awaddr <= v_normalized_addr;
axi_if.write_address_channel.awlen <= std_logic_vector(awlen_value);
axi_if.write_address_channel.awsize <= bytes_to_axsize(awsize_value);
axi_if.write_address_channel.awburst <= axburst_to_slv(awburst_value);
axi_if.write_address_channel.awlock <= axlock_to_sl(awlock_value);
axi_if.write_address_channel.awcache <= awcache_value;
axi_if.write_address_channel.awprot <= axprot_to_slv(awprot_value);
axi_if.write_address_channel.awqos <= awqos_value;
axi_if.write_address_channel.awregion <= awregion_value;
axi_if.write_address_channel.awuser <= v_awuser_value;
axi_if.write_address_channel.awvalid <= '1';
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Sample ready signals
v_wready := axi_if.write_data_channel.wready;
v_awready := axi_if.write_address_channel.awready;
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
if v_wready = '1' and cycle >= config.num_w_pipe_stages then
axi_if.write_data_channel.wdata <= (axi_if.write_data_channel.wdata'range => '0');
axi_if.write_data_channel.wstrb <= (axi_if.write_data_channel.wstrb'range => '0');
axi_if.write_data_channel.wlast <= '0';
axi_if.write_data_channel.wuser <= (axi_if.write_data_channel.wuser'range => '0');
axi_if.write_data_channel.wvalid <= '0';
v_await_wready := false;
end if;
if v_awready = '1' and cycle >= config.num_aw_pipe_stages then
axi_if.write_address_channel.awid <= (axi_if.write_address_channel.awid'range => '0');
axi_if.write_address_channel.awaddr <= (axi_if.write_address_channel.awaddr'range => '0');
axi_if.write_address_channel.awlen <= (others=>'0');
axi_if.write_address_channel.awsize <= (others=>'0');
axi_if.write_address_channel.awburst <= (others=>'0');
axi_if.write_address_channel.awlock <= '0';
axi_if.write_address_channel.awcache <= (others=>'0');
axi_if.write_address_channel.awprot <= (others=>'0');
axi_if.write_address_channel.awqos <= (others=>'0');
axi_if.write_address_channel.awregion <= (others=>'0');
axi_if.write_address_channel.awuser <= (axi_if.write_address_channel.awuser'range => '0');
axi_if.write_address_channel.awvalid <= '0';
v_await_awready := false;
end if;
if not v_await_awready and not v_await_wready then
exit;
end if;
end loop;
check_value(not v_await_wready, config.max_wait_cycles_severity, ": Timeout waiting for WREADY", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(not v_await_awready, config.max_wait_cycles_severity, ": Timeout waiting for AWREADY", scope, ID_NEVER, msg_id_panel, proc_call);
v_await_wready := true;
end loop;
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Brady - Add support for num_b_pipe_stages
if cycle = config.num_b_pipe_stages then
axi_if.write_response_channel.bready <= '1';
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
if axi_if.write_response_channel.bvalid = '1' and cycle >= config.num_b_pipe_stages then
-- Checking response
check_value(axi_if.write_response_channel.bid, v_awid_value, error, "Checking BID", scope, BIN, KEEP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
buser_value := normalize_and_check(axi_if.write_response_channel.buser, buser_value, ALLOW_WIDER_NARROWER, "axi_if.write_response_channel.buser", "buser_value", msg);
bresp_value := slv_to_xresp(axi_if.write_response_channel.bresp);
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
axi_if.write_response_channel.bready <= '0';
v_await_bvalid := false;
end if;
if not v_await_bvalid then
exit;
end if;
end loop;
check_value(not v_await_bvalid, config.max_wait_cycles_severity, ": Timeout waiting for BVALID", scope, ID_NEVER, msg_id_panel, proc_call);
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure axi_write;
procedure axi_read (
constant arid_value : in std_logic_vector := "";
constant araddr_value : in unsigned;
constant arlen_value : in unsigned(7 downto 0) := (others=>'0');
constant arsize_value : in integer range 1 to 128 := 4;
constant arburst_value : in t_axburst := INCR;
constant arlock_value : in t_axlock := NORMAL;
constant arcache_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant arprot_value : in t_axprot := UNPRIVILEGED_NONSECURE_DATA;
constant arqos_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant arregion_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant aruser_value : in std_logic_vector := "";
variable rdata_value : out t_slv_array;
variable rresp_value : out t_xresp_array;
variable ruser_value : out t_slv_array;
constant msg : in string;
signal clk : in std_logic;
signal axi_if : inout t_axi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant local_proc_name : string := "axi_read"; -- Local proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "(A:" & to_string(araddr_value, HEX, AS_IS, INCL_RADIX) & ")"; -- Local proc_call; used if called from sequncer or VVC
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axi_if.read_address_channel.araddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(araddr_value), axi_if.read_address_channel.araddr, ALLOW_WIDER_NARROWER, "addr", "axi_if.read_address_channel.araddr", msg);
-- Variables for the unconstrained inputs
variable v_arid_value : std_logic_vector(axi_if.read_address_channel.arid'length-1 downto 0);
variable v_aruser_value : std_logic_vector(axi_if.read_address_channel.aruser'length-1 downto 0);
-- Helper variables
variable v_proc_call : line;
variable v_await_arready : boolean := true;
variable v_await_rvalid : boolean := true;
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
begin
-- Setting default values
if arid_value'length = 0 then
v_arid_value := (others=>'0'); -- Default value
else
v_arid_value := normalize_and_check(arid_value, axi_if.read_address_channel.arid, ALLOW_WIDER_NARROWER, "arid", "axi_if.read_address_channel.arid", msg);
end if;
if aruser_value'length = 0 then
v_aruser_value := (others=>'0'); -- Default value
else
v_aruser_value := normalize_and_check(aruser_value, axi_if.read_address_channel.aruser, ALLOW_WIDER_NARROWER, "aruser", "axi_if.read_address_channel.aruser", msg);
end if;
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'axi_read...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing axi_read...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Brady - Add support for num_ar_pipe_stages
if cycle = config.num_ar_pipe_stages then
axi_if.read_address_channel.arid <= v_arid_value;
axi_if.read_address_channel.araddr <= v_normalized_addr;
axi_if.read_address_channel.arlen <= std_logic_vector(arlen_value);
axi_if.read_address_channel.arsize <= bytes_to_axsize(arsize_value);
axi_if.read_address_channel.arburst <= axburst_to_slv(arburst_value);
axi_if.read_address_channel.arlock <= axlock_to_sl(arlock_value);
axi_if.read_address_channel.arcache <= arcache_value;
axi_if.read_address_channel.arprot <= axprot_to_slv(arprot_value);
axi_if.read_address_channel.arqos <= arqos_value;
axi_if.read_address_channel.arregion <= arregion_value;
axi_if.read_address_channel.aruser <= v_aruser_value;
axi_if.read_address_channel.arvalid <= '1';
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
if axi_if.read_address_channel.arready = '1' and cycle >= config.num_ar_pipe_stages then
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
axi_if.read_address_channel.arid <= (axi_if.read_address_channel.arid'range => '0');
axi_if.read_address_channel.araddr <= (axi_if.read_address_channel.araddr'range => '0');
axi_if.read_address_channel.arlen <= (others=>'0');
axi_if.read_address_channel.arsize <= (others=>'0');
axi_if.read_address_channel.arburst <= (others=>'0');
axi_if.read_address_channel.arlock <= '0';
axi_if.read_address_channel.arcache <= (others=>'0');
axi_if.read_address_channel.arprot <= (others=>'0');
axi_if.read_address_channel.arqos <= (others=>'0');
axi_if.read_address_channel.arregion <= (others=>'0');
axi_if.read_address_channel.aruser <= (axi_if.read_address_channel.aruser'range => '0');
axi_if.read_address_channel.arvalid <= '0';
v_await_arready := false;
end if;
if not v_await_arready then
exit;
end if;
end loop;
check_value(not v_await_arready, config.max_wait_cycles_severity, ": Timeout waiting for ARREADY", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
for read_transfer_num in 0 to to_integer(unsigned(arlen_value)) loop
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Brady - Add support for num_r_pipe_stages
if cycle = config.num_r_pipe_stages then
axi_if.read_data_channel.rready <= '1';
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
if axi_if.read_data_channel.rvalid = '1' and cycle >= config.num_r_pipe_stages then
v_await_rvalid := false;
check_value(axi_if.read_data_channel.rid, v_arid_value, config.match_strictness, error, "Checking RID", scope, HEX, KEEP_LEADING_0, ID_POS_ACK, msg_id_panel);
rdata_value(read_transfer_num) := normalize_and_check(axi_if.read_data_channel.rdata, rdata_value(read_transfer_num), ALLOW_WIDER_NARROWER, "axi_if.read_data_channel.rdata", "rdata_value(" & to_string(read_transfer_num) & ")", msg);
rresp_value(read_transfer_num) := slv_to_xresp(axi_if.read_data_channel.rresp);
ruser_value(read_transfer_num) := normalize_and_check(axi_if.read_data_channel.ruser, ruser_value(read_transfer_num), ALLOW_WIDER_NARROWER, "axi_if.read_data_channel.ruser", "ruser_value(" & to_string(read_transfer_num) & ")", msg);
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
axi_if.read_data_channel.rready <= '0';
end if;
if not v_await_rvalid then
exit;
end if;
end loop;
check_value(not v_await_rvalid, config.max_wait_cycles_severity, ": Timeout waiting for RVALID", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
v_await_rvalid := true;
end loop;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(rdata_value(0 to to_integer(unsigned(arlen_value))), HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. axi_check)
end if;
DEALLOCATE(v_proc_call);
end procedure axi_read;
procedure axi_check (
constant arid_value : in std_logic_vector := "";
constant araddr_value : in unsigned;
constant arlen_value : in unsigned(7 downto 0) := (others=>'0');
constant arsize_value : in integer range 1 to 128 := 4;
constant arburst_value : in t_axburst := INCR;
constant arlock_value : in t_axlock := NORMAL;
constant arcache_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant arprot_value : in t_axprot := UNPRIVILEGED_NONSECURE_DATA;
constant arqos_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant arregion_value : in std_logic_vector(3 downto 0) := (others=>'0');
constant aruser_value : in std_logic_vector := "";
constant rdata_exp : in t_slv_array;
constant rresp_exp : in t_xresp_array := C_EMPTY_XRESP_ARRAY;
constant ruser_exp : in t_slv_array := C_EMPTY_SLV_ARRAY;
constant msg : in string;
signal clk : in std_logic;
signal axi_if : inout t_axi_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "axi_check(A:" & to_string(araddr_value, HEX, AS_IS, INCL_RADIX) & ")";
variable v_rdata_value : t_slv_array(0 to to_integer(unsigned(arlen_value)))(axi_if.read_data_channel.rdata'length-1 downto 0);
variable v_rresp_value : t_xresp_array(0 to to_integer(unsigned(arlen_value)));
variable v_ruser_value : t_slv_array(0 to to_integer(unsigned(arlen_value)))(axi_if.read_data_channel.ruser'length-1 downto 0);
variable v_rresp_exp : t_xresp_array(0 to to_integer(unsigned(arlen_value))) := (others=>ILLEGAL);
variable v_ruser_exp : t_slv_array(0 to to_integer(unsigned(arlen_value)))(axi_if.read_data_channel.ruser'length-1 downto 0);
variable v_check_ok : boolean := true;
begin
if rresp_exp'length = 1 and rresp_exp(0) = ILLEGAL then
v_rresp_exp := (others=>OKAY); -- Default value
else
if not rresp_exp'ascending then
tb_error("The array rresp_exp is instantiated as 'downto', but only 'to' is supported" & add_msg_delimiter(msg), scope);
else
for i in 0 to minimum(v_rresp_exp'length, rresp_exp'length) - 1 loop
v_rresp_exp(i) := rresp_exp(i);
end loop;
end if;
end if;
if ruser_exp'length = 1 and ruser_exp(0)'length = 1 and ruser_exp(0) = "U" then
v_ruser_exp := (others=>(others=>'0')); -- Default value
else
v_ruser_exp := normalize_and_check(ruser_exp, v_ruser_exp, ALLOW_WIDER_NARROWER, "ruser_exp", "v_ruser_exp", msg);
end if;
axi_read(arid_value => arid_value,
araddr_value => araddr_value,
arlen_value => arlen_value,
arsize_value => arsize_value,
arburst_value => arburst_value,
arlock_value => arlock_value,
arcache_value => arcache_value,
arprot_value => arprot_value,
arqos_value => arqos_value,
arregion_value => arregion_value,
aruser_value => aruser_value,
rdata_value => v_rdata_value,
rresp_value => v_rresp_value,
ruser_value => v_ruser_value,
msg => msg,
clk => clk,
axi_if => axi_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config,
ext_proc_call => proc_call);
if not check_value(v_rdata_value, rdata_exp, alert_level, "Checking RDATA", scope, HEX, KEEP_LEADING_0, ID_POS_ACK, msg_id_panel) then
v_check_ok := false;
end if;
if not check_value(v_rresp_value = v_rresp_exp, alert_level, "Checking RRESP", scope, ID_POS_ACK, msg_id_panel) then
v_check_ok := false;
end if;
if not check_value(v_ruser_value, v_ruser_exp, alert_level, "Checking RUSER ", scope, HEX, KEEP_LEADING_0, ID_POS_ACK, msg_id_panel) then
v_check_ok := false;
end if;
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axi_check;
end package body axi_bfm_pkg;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_sfifo_autord.vhd | 4 | 20288 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_wr_demux.vhd | 13 | 75458 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_demux.vhd
--
-- Description:
-- This file implements the DataMover Master Write Strobe De-Multiplexer.
-- This is needed when the native data width of the DataMover is narrower
-- than the AXI4 Write Data Channel.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Write Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the native data width of the DataMover S2MM. If
-- S2MM Store and Forward with upsizer is enabled, the width is
-- the AXi4 Write Data Channel, else it is the S2MM Stream data width.
);
port (
-- AXI MMap Data Channel Input --------------------------------------------
--
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- data input --
----------------------------------------------------------------------------
-- AXI Master Stream ------------------------------------------------------
--
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
--De-Mux strb output --
----------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------
--
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
----------------------------------------------------------------------------
);
end entity axi_sg_wr_demux;
architecture implementation of axi_sg_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
--when 2 =>
-- var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 1;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- assume 1024 bit width
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH);
Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX);
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when others => -- 1 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when others => -- 3 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when others => -- 7 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when others => -- 15 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when others => -- 31 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel demux case
--
--
------------------------------------------------------------
GEN_64XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_64XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when others => -- 63 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
end case;
end process DO_64XN_DEMUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel demux case
--
--
------------------------------------------------------------
GEN_128XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_128XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when 63 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
when 64 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in;
when 65 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in;
when 66 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in;
when 67 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in;
when 68 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in;
when 69 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in;
when 70 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in;
when 71 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in;
when 72 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in;
when 73 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in;
when 74 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in;
when 75 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in;
when 76 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in;
when 77 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in;
when 78 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in;
when 79 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in;
when 80 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in;
when 81 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in;
when 82 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in;
when 83 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in;
when 84 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in;
when 85 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in;
when 86 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in;
when 87 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in;
when 88 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in;
when 89 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in;
when 90 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in;
when 91 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in;
when 92 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in;
when 93 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in;
when 94 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in;
when 95 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in;
when 96 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in;
when 97 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in;
when 98 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in;
when 99 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in;
when 100 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in;
when 101 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in;
when 102 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in;
when 103 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in;
when 104 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in;
when 105 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in;
when 106 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in;
when 107 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in;
when 108 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in;
when 109 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in;
when 110 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in;
when 111 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in;
when 112 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in;
when 113 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in;
when 114 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in;
when 115 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in;
when 116 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in;
when 117 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in;
when 118 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in;
when 119 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in;
when 120 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in;
when 121 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in;
when 122 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in;
when 123 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in;
when 124 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in;
when 125 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in;
when 126 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in;
when others => -- 127 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in;
end case;
end process DO_128XN_DEMUX;
end generate GEN_128XN;
end implementation;
| mit |
UVVM/UVVM_All | bitvis_vip_error_injection/tb/ei_demo_tb.vhd | 1 | 42928 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_error_injection;
use bitvis_vip_error_injection.error_injection_pkg.all;
--hdlunit:tb
entity ei_demo_tb is
generic (GC_TESTCASE : natural := 0);
end entity ei_demo_tb;
architecture func of ei_demo_tb is
constant C_SCOPE : string := "EI_DEMO_TB";
constant C_SL_EI_IDX : natural := 1;
constant C_SLV_EI_IDX : natural := 2;
constant C_DATA_WIDTH : natural := 8;
constant C_SL_SIGNAL_DEFAULT : std_logic := '0';
constant C_SLV_SIGNAL_DEFAULT : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
constant C_PULSE_WIDTH : time := 20 ns;
-- Error Injection VIPs input/output signals
-- std_logic
signal output_sl : std_logic := C_SL_SIGNAL_DEFAULT;
signal input_sl : std_logic := '0';
-- vector
signal input_slv : std_logic_vector(C_DATA_WIDTH-1 downto 0) := x"00";
signal output_slv : std_logic_vector(C_DATA_WIDTH-1 downto 0) := C_SLV_SIGNAL_DEFAULT;
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-----------------------------------------------------------------------------
-- Error injector
-----------------------------------------------------------------------------
error_injector_sl: entity work.error_injection_sl
generic map (
GC_INSTANCE_IDX => 1
)
port map (
ei_in => input_sl,
ei_out => output_sl
);
error_injector_slv: entity work.error_injection_slv
generic map (
GC_INSTANCE_IDX => 2
)
port map (
ei_in => input_slv,
ei_out => output_slv
);
-----------------------------------------------------------------------------
-- Testbench sequencer
-----------------------------------------------------------------------------
p_sequencer : process
variable v_timestamp_sl : time;
variable v_timestamp_slv : time;
variable v_valid_interval : boolean := true;
-- Generate EI VIP input signals.
procedure run_test(slv_value : integer; msg : string := "Setting EI VIPs input signal") is
begin
log(ID_SEQUENCER_SUB, msg, C_SCOPE);
input_slv <= std_logic_vector(to_unsigned(slv_value, C_DATA_WIDTH));
gen_pulse(input_sl, C_PULSE_WIDTH, NON_BLOCKING, "pulsing SL");
end procedure run_test;
-- Set EI VIP configurations back to default values.
procedure reset_config is
begin
-- Set default config.
shared_ei_config(C_SL_EI_IDX) := C_EI_CONFIG_DEFAULT;
shared_ei_config(C_SLV_EI_IDX) := C_EI_CONFIG_DEFAULT;
-- Set inputs to '0' and 0x0.
run_test(0, "Resetting EI VIP inputs");
-- Add small delay for next test.
wait for 100 ns;
end procedure reset_config;
--==================================================================
-- Test declarations
--==================================================================
--------------------------------------------------------------------
-- Test case for DELAY error innjection
--
-- This test will test delay error injection on a SL and a SLV signal
-- with defined delay values, random delay values, and with
-- interval settings set to 1 and 2.
--
-- Note: test is self checking.
--------------------------------------------------------------------
procedure test_delay_error_injection(void : t_void) is
variable v_init_delay : time := 7 ns;
begin
log(ID_LOG_HDR_XL, "Delay error injection tests");
-----------------------------------------------------------------
-- Delay test
-----------------------------------------------------------------
log(ID_LOG_HDR, "Delay test with delay = 7 ns and interval = 1.", C_SCOPE);
-- Configure SL Error Injection VIP
shared_ei_config(C_SL_EI_IDX).error_type := DELAY;
shared_ei_config(C_SL_EI_IDX).initial_delay_min := v_init_delay;
shared_ei_config(C_SL_EI_IDX).interval := 1;
-- Configure SLV Error Injection VIP
shared_ei_config(C_SLV_EI_IDX).error_type := DELAY;
shared_ei_config(C_SLV_EI_IDX).initial_delay_min := v_init_delay;
shared_ei_config(C_SLV_EI_IDX).interval := 1;
-- Create 2 EI input events and verify outputs
for idx in 1 to 2 loop
-- Verify initial values
check_value(output_sl = '0', TB_ERROR, "verify SL output");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8) - 1), TB_ERROR, "verify SLV output");
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values
wait until output_sl = '1';
log(ID_SEQUENCER, "Verify delayed initial edge "&to_string(idx)&".", C_SCOPE);
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV delayed output");
-- Verify correct delay
check_value(input_sl'last_event - output_sl'last_event = v_init_delay, TB_ERROR, "check SL initial delay time");
check_value(input_slv'last_event - output_slv'last_event = v_init_delay, TB_ERROR, "check SLV initial delay time");
-- For SL signal: verify output return value and timing
wait until output_sl = '0';
log(ID_SEQUENCER, "Verify delayed final edge "&to_string(idx)&".\n", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event = v_init_delay, TB_ERROR, "verify SL return delay time");
-- For SL signal: wait low period
wait for C_PULSE_WIDTH - v_init_delay;
end loop;
-----------------------------------------------------------------
-- Interval tests
-----------------------------------------------------------------
log(ID_LOG_HDR, "Delay test with delay = 7 ns and interval = 2.", C_SCOPE);
-- Reconfigure EI VIPs error injection interval
shared_ei_config(C_SL_EI_IDX).interval := 2;
shared_ei_config(C_SLV_EI_IDX).interval := 2;
-- Create 5 EI input events and verify outputs
for idx in 3 to 8 loop
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values
wait until output_sl = '1';
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV output");
-- Verify correct delay
if v_valid_interval = true then
log(ID_SEQUENCER, "Verify delayed initial edge "&to_string(idx-2)&".", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event = v_init_delay, TB_ERROR, "check SL delay time");
check_value(input_slv'last_event - output_slv'last_event = v_init_delay, TB_ERROR, "check SLV delay time");
else
log(ID_SEQUENCER, "Verify non delayed initial edge "&to_string(idx-2)&".", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event = 0 ns, TB_ERROR, "check SL no delay time");
check_value(input_slv'last_event - output_slv'last_event = 0 ns, TB_ERROR, "check SLV delay time");
end if;
-- For SL signal: verify output return value and timing
v_timestamp_sl := now;
wait until output_sl = '0';
check_value(output_sl = '0', TB_ERROR, "verify SL low");
check_value( (now - v_timestamp_sl) = C_PULSE_WIDTH, TB_ERROR, "verify SL high period");
if v_valid_interval then
log(ID_SEQUENCER, "Verify delayed final edge "&to_string(idx-2)&".\n", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event = v_init_delay, TB_ERROR, "check SL delay time");
wait for C_PULSE_WIDTH - v_init_delay;
else
log(ID_SEQUENCER, "Verify non delayed final edge "&to_string(idx-2)&".\n", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event = 0 ns, TB_ERROR, "check SL no delay time");
wait for C_PULSE_WIDTH; -- low period
end if;
-- Flip next expected interval validity
v_valid_interval := not(v_valid_interval);
end loop;
-- Reset VIPs for next test
reset_config;
-----------------------------------------------------------------
-- Random delay tests
-----------------------------------------------------------------
log(ID_LOG_HDR, "Delay test with randomised delay = 1-10 ns and interval = 1.", C_SCOPE);
-- Reconfigure SL EI VIP with randomised interval
shared_ei_config(C_SL_EI_IDX).error_type := DELAY;
shared_ei_config(C_SL_EI_IDX).initial_delay_min := 1 ns;
shared_ei_config(C_SL_EI_IDX).initial_delay_max := 10 ns; -- setting max = randomisation
shared_ei_config(C_SL_EI_IDX).interval := 1;
for idx in 1 to 2 loop
-- Verify initial value
check_value(output_sl = '0', TB_ERROR, "check SL delayed output");
-- Activate SL pulse on EI VIP
run_test(idx);
-- Verify correct initial delay range
wait until output_sl = '1';
log(ID_SEQUENCER, "Verify delayed initial edge "&to_string(idx)&".", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event < 11 ns, TB_ERROR, "check SL delay time");
-- Verify correct final delay range
wait until output_sl = '0';
log(ID_SEQUENCER, "Verify delayed final edge "&to_string(idx)&".\n", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event < 11 ns, TB_ERROR, "verify SL delay time");
wait for 20 ns; -- low period
end loop;
-- Reset VIPs for next test
reset_config;
end procedure test_delay_error_injection;
--------------------------------------------------------------------
-- Test cases for JITTER error injections
--
-- This test will test jitter error injection on a SL signal
-- with defined jitter values and with interval settings set
-- to 1 and 2.
--
-- Note: test is self checking.
--------------------------------------------------------------------
procedure test_jitter_error_injection(void : t_void) is
variable v_init_delay : time := 7 ns;
variable v_return_delay : time := 3 ns;
begin
log(ID_LOG_HDR_XL, "Jitter error injection tests");
-----------------------------------------------------------------
-- Jitter test
-----------------------------------------------------------------
log(ID_LOG_HDR, "Jitter test with jitter = 7 ns - 3 ns and interval = 1.", C_SCOPE);
-- Configure SL EI VIP
shared_ei_config(C_SL_EI_IDX).error_type := JITTER;
shared_ei_config(C_SL_EI_IDX).initial_delay_min := v_init_delay;
shared_ei_config(C_SL_EI_IDX).return_delay_min := v_return_delay;
-- Jitter for SLV EI VIP is not supported
shared_ei_config(C_SLV_EI_IDX).error_type := JITTER; -- SLV jitter not supported!
shared_ei_config(C_SLV_EI_IDX).initial_delay_min := v_init_delay;
for idx in 1 to 2 loop
-- Verify initial values
check_value(output_sl = '0', TB_ERROR, "verify SL output");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8) - 1), TB_ERROR, "verify SLV output");
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values and timing
wait until output_sl = '1';
log(ID_SEQUENCER, "Verify jittered initial edge "&to_string(idx)&".", C_SCOPE);
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV output");
check_value(input_sl'last_event - output_sl'last_event = v_init_delay, TB_ERROR, "check SL initial delay time");
check_value(output_slv'last_event = input_slv'last_event, TB_ERROR, "check SLV static");
-- For SL signal: verify output return value and timing
wait until output_sl = '0';
log(ID_SEQUENCER, "Verify jittered final edge "&to_string(idx)&".\n", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event = v_return_delay, TB_ERROR, "verify SL return delay time");
wait for C_PULSE_WIDTH; -- SL low period
end loop;
-----------------------------------------------------------------
-- Interval tests
-----------------------------------------------------------------
log(ID_LOG_HDR, "Jitter test with delay = 7 ns and interval = 2.", C_SCOPE);
-- Reconfigure EI VIPs error injection interval
shared_ei_config(C_SL_EI_IDX).interval := 2;
shared_ei_config(C_SLV_EI_IDX).interval := 2;
for idx in 3 to 8 loop
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values
wait until output_sl = '1';
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV output");
if v_valid_interval then
log(ID_SEQUENCER, "Verify jittered initial edge "&to_string(idx-2)&".", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event = v_init_delay, TB_ERROR, "check SL delay time");
check_value(output_slv'last_event - input_slv'last_event = 0 ns, TB_ERROR, "check SLV static");
else
log(ID_SEQUENCER, "Verify non jittered initial edge "&to_string(idx-2)&".", C_SCOPE);
check_value(input_sl'last_event - output_sl'last_event = 0 ns, TB_ERROR, "check SL no delay time");
check_value(input_slv'last_event - output_slv'last_event = 0 ns, TB_ERROR, "check SLV delay time");
end if;
-- For SL signal: verify output return value and timing
v_timestamp_sl := now;
wait until output_sl = '0';
check_value(output_sl = '0', TB_ERROR, "verify SL low");
if v_valid_interval then
log(ID_SEQUENCER, "Verify jittered final edge "&to_string(idx-2)&".\n", C_SCOPE);
check_value( (now - v_timestamp_sl) = (C_PULSE_WIDTH - v_init_delay + v_return_delay), TB_ERROR, "verify SL high period");
check_value(input_sl'last_event - output_sl'last_event = v_return_delay, TB_ERROR, "check SL delay time");
wait for C_PULSE_WIDTH - v_return_delay;
else
log(ID_SEQUENCER, "Verify non jittered final edge "&to_string(idx-2)&".\n", C_SCOPE);
check_value( (now - v_timestamp_sl) = C_PULSE_WIDTH, TB_ERROR, "verify SL high period");
check_value(input_sl'last_event - output_sl'last_event = 0 ns, TB_ERROR, "check SL no delay time");
wait for C_PULSE_WIDTH; -- low period
end if;
-- Flip next expected interval validity
v_valid_interval := not(v_valid_interval);
end loop;
-- Reset VIPs for next test
reset_config;
end procedure test_jitter_error_injection;
--------------------------------------------------------------------
-- Test cases for INVERT error injections
--
-- This test will test inverting error injection on a SL and SLV
-- signal, with interval settings set to 1 and 2.
--
-- Note: test is self checking.
--------------------------------------------------------------------
procedure test_invert_error_injection(void : t_void) is
begin
log(ID_LOG_HDR_XL, "Invert error injection tests");
-----------------------------------------------------------------
-- Invert test
----------------------------------------------------------------
log(ID_LOG_HDR, "Invert test with interval = 1.", C_SCOPE);
-- Configure SL and SLV EI VIPs
shared_ei_config(C_SL_EI_IDX).error_type := INVERT;
shared_ei_config(C_SLV_EI_IDX).error_type := INVERT;
for idx in 1 to 2 loop
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values
wait on output_sl;
log(ID_SEQUENCER, "Verify inverted signal "&to_string(idx-2)&".\n", C_SCOPE);
check_value(input_sl = not(output_sl), TB_ERROR, "verify SL invert");
check_value(input_slv = not(output_slv), TB_ERROR, "verify SLV invert");
wait for C_PULSE_WIDTH; -- SL low period
end loop;
-----------------------------------------------------------------
-- Interval tests
-----------------------------------------------------------------
log(ID_LOG_HDR, "Invert test with interval = 2.", C_SCOPE);
-- Reconfigure EI VIPs error injection interval
shared_ei_config(C_SL_EI_IDX).interval := 2;
shared_ei_config(C_SLV_EI_IDX).interval := 2;
for idx in 3 to 8 loop
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
wait for 0 ns; -- add delta cycle for signal update
-- Verify output values
if v_valid_interval then
log(ID_SEQUENCER, "Verify inverted signal "&to_string(idx-2)&".", C_SCOPE);
check_value(input_sl = not(output_sl), TB_ERROR, "verify SL invert, high period");
check_value(input_slv = not(output_slv), TB_ERROR, "verify SLV invert");
else
log(ID_SEQUENCER, "Verify non inverted signal "&to_string(idx-2)&".", C_SCOPE);
check_value(input_sl = output_sl, TB_ERROR, "verify SL no invert, high period");
check_value(input_slv = output_slv, TB_ERROR, "verify SLV no invert");
end if;
-- wait for SL high period
wait for C_PULSE_WIDTH; -- SL high period
wait for 0 ns; -- add delta cycle for signal update
-- Verify output values
if v_valid_interval then
log(ID_SEQUENCER, "Verify inverted signal "&to_string(idx-2)&".\n", C_SCOPE);
check_value(input_sl = not(output_sl), TB_ERROR, "verify SL invert, low period");
check_value(input_slv = not(output_slv), TB_ERROR, "verify SLV invert");
else
log(ID_SEQUENCER, "Verify non inverted signal "&to_string(idx-2)&".\n", C_SCOPE);
check_value(input_sl = output_sl, TB_ERROR, "verify SL no invert, low period");
check_value(input_slv = output_slv, TB_ERROR, "verify SLV no invert");
end if;
wait for C_PULSE_WIDTH; -- SL low period
-- Flip next expected interval validity
v_valid_interval := not(v_valid_interval);
end loop;
-- Reset VIPs for next test
reset_config;
end procedure test_invert_error_injection;
--------------------------------------------------------------------
-- Test case for PULSE error injection
--
-- This test will test pulse error injection on a SL and a SLV signal
-- with defined pulse values and interval settings set to 1 and 2.
--
-- Note: test is self checking.
--------------------------------------------------------------------
procedure test_pulse_error_injection(void : t_void) is
variable v_init_delay : time := 7 ns;
variable v_width : time := 6 ns;
begin
log(ID_LOG_HDR_XL, "Pulse error injection tests");
-----------------------------------------------------------------
-- Pulse test
----------------------------------------------------------------
log(ID_LOG_HDR, "Pulse test with pulse start = 7 ns, pulse width = 6 ns, and interval = 1.", C_SCOPE);
-- Configure SL and SLV EI VIPs
shared_ei_config(C_SL_EI_IDX).error_type := PULSE;
shared_ei_config(C_SL_EI_IDX).initial_delay_min := v_init_delay;
shared_ei_config(C_SL_EI_IDX).width_min := v_width;
shared_ei_config(C_SLV_EI_IDX).error_type := PULSE;
shared_ei_config(C_SLV_EI_IDX).initial_delay_min := v_init_delay;
shared_ei_config(C_SLV_EI_IDX).width_min := v_width;
for idx in 1 to 2 loop
-- Verify initial values
check_value(output_sl = '0', TB_ERROR, "verify SL output");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8) - 1), TB_ERROR, "verify SLV output");
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values
v_timestamp_sl := now;
wait until output_sl = '1';
log(ID_SEQUENCER, "Verify normal signal start "&to_string(idx)&".", C_SCOPE);
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV pre pulse");
-- Verify output values
v_timestamp_slv := now;
wait for v_init_delay;
log(ID_SEQUENCER, "Verify pulse start "&to_string(idx)&".", C_SCOPE);
check_value(output_sl = '0', TB_ERROR, "verify SL pulse set");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)-1), TB_ERROR, "verify SLV pulse set");
check_value( (now - v_timestamp_slv) = v_init_delay, TB_ERROR, "verify pulse init_delay");
-- Verify output values
v_timestamp_slv := now;
wait for v_width;
log(ID_SEQUENCER, "Verify pulse end "&to_string(idx)&".", C_SCOPE);
check_value(output_sl = '1', TB_ERROR, "verify SL pulse done");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV pulse done");
check_value( (now - v_timestamp_slv) = v_width, TB_ERROR, "verify pulse width");
-- Verify output values
wait until output_sl = '0';
log(ID_SEQUENCER, "Verify signal end "&to_string(idx)&".\n", C_SCOPE);
check_value( (now - v_timestamp_sl) = C_PULSE_WIDTH, TB_ERROR, "verify SL high period");
wait for C_PULSE_WIDTH; -- SL low period
end loop;
-----------------------------------------------------------------
-- Interval tests
-----------------------------------------------------------------
log(ID_LOG_HDR, "Pulse test with interval = 2.", C_SCOPE);
-- Reconfigure EI VIPs error injection interval
shared_ei_config(C_SL_EI_IDX).interval := 2;
shared_ei_config(C_SLV_EI_IDX).interval := 2;
for idx in 3 to 8 loop
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values
v_timestamp_sl := now;
wait for 0 ns;
log(ID_SEQUENCER, "Verify normal signal start "&to_string(idx-2)&".", C_SCOPE);
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV pre pulse");
if v_valid_interval then
-- Verify output values
v_timestamp_slv := now;
wait for v_init_delay;
log(ID_SEQUENCER, "Verify pulse start "&to_string(idx-2)&".", C_SCOPE);
check_value(output_sl = '0', TB_ERROR, "verify SL pulse set");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)-1), TB_ERROR, "verify SLV pulse set");
check_value((now - v_timestamp_slv) = v_init_delay, TB_ERROR, "verify pulse init_delay");
-- Verify output values
v_timestamp_slv := now;
wait for v_width;
log(ID_SEQUENCER, "Verify pulse end "&to_string(idx-2)&".", C_SCOPE);
check_value(output_sl = '1', TB_ERROR, "verify SL pulse done");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV pulse done");
check_value((now - v_timestamp_slv) = v_width, TB_ERROR, "verify pulse width");
else
log(ID_SEQUENCER, "Verify non pulsed signal "&to_string(idx-2)&".", C_SCOPE);
check_value(input_sl = output_sl, TB_ERROR, "verify SL no pulse, high period");
check_value(input_slv = output_slv, TB_ERROR, "verify SLV no pulse");
end if;
-- Verify output values
wait until output_sl = '0';
log(ID_SEQUENCER, "Verify signal end "&to_string(idx-2)&".\n", C_SCOPE);
check_value( (now - v_timestamp_sl) = C_PULSE_WIDTH, TB_ERROR, "verify SL high period");
wait for C_PULSE_WIDTH; -- SL low period
-- Flip next expected interval validity
v_valid_interval := not(v_valid_interval);
end loop;
-- Reset VIPs for next test
reset_config;
end procedure test_pulse_error_injection;
--------------------------------------------------------------------
-- Test case for STUCK_AT_OLD error injection
--
-- This test will test stuck at old value error injection on a SL
-- and a SLV signal, with interval settings set to 1 and 2.
--
-- Note: test is self checking.
--------------------------------------------------------------------
procedure test_stuck_at_old_error_injection(void : t_void) is
variable v_width : time := 13 ns;
begin
log(ID_LOG_HDR_XL, "Stuck at old error injection test.", C_SCOPE);
-----------------------------------------------------------------
-- Stuck at old test
----------------------------------------------------------------
log(ID_LOG_HDR, "Stuck at old test with stuck = 13 ns and interval = 1.", C_SCOPE);
-- Configure SL and SLV EI VIPs
shared_ei_config(C_SL_EI_IDX).error_type := STUCK_AT_OLD;
shared_ei_config(C_SL_EI_IDX).width_min := v_width;
shared_ei_config(C_SLV_EI_IDX).error_type := STUCK_AT_OLD;
shared_ei_config(C_SLV_EI_IDX).width_min := v_width;
for idx in 1 to 2 loop
-- Verify initial values
check_value(output_sl = '0', TB_ERROR, "verify SL output");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8) - 1), TB_ERROR, "verify SLV output");
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values
v_timestamp_sl := now;
wait until output_sl = '1';
log(ID_SEQUENCER, "Verify stuck period "&to_string(idx)&".\n", C_SCOPE);
check_value((now-v_timestamp_sl) = v_width, TB_ERROR, "verify stuck period");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV new value");
check_value(output_slv'last_event = 0 ns, TB_ERROR, "verify SLV updated");
-- Verify output values
v_timestamp_sl := now;
wait until output_sl = '0';
log(ID_SEQUENCER, "Verify signal duration "&to_string(idx)&".\n", C_SCOPE);
check_value((now-v_timestamp_sl) = (C_PULSE_WIDTH - v_width), TB_ERROR, "verify stuck period");
wait for C_PULSE_WIDTH; -- SL low period
end loop;
-----------------------------------------------------------------
-- Interval tests
-----------------------------------------------------------------
log(ID_LOG_HDR, "Stuck at old test with interval = 2.", C_SCOPE);
-- Reconfigure EI VIPs error injection interval
shared_ei_config(C_SL_EI_IDX).interval := 2;
shared_ei_config(C_SLV_EI_IDX).interval := 2;
for idx in 3 to 8 loop
-- Verify initial values
check_value(output_sl = '0', TB_ERROR, "verify SL output");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8) - 1), TB_ERROR, "verify SLV output");
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Verify output values
v_timestamp_sl := now;
wait until output_sl = '1';
if v_valid_interval then
log(ID_SEQUENCER, "Verify stuck at old period "&to_string(idx-2)&".\n", C_SCOPE);
check_value((now-v_timestamp_sl) = v_width, TB_ERROR, "verify stuck period");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV new value");
check_value(output_slv'last_event = 0 ns, TB_ERROR, "verify SLV updated");
else
log(ID_SEQUENCER, "Verify not stuck at old "&to_string(idx-2)&".\n", C_SCOPE);
check_value((now-v_timestamp_sl) = 0 ns, TB_ERROR, "verify update period");
check_value(output_slv'last_event = 0 ns, TB_ERROR, "verify SLV updated");
check_value(input_sl = output_sl, TB_ERROR, "verify SL no invert, high period");
check_value(input_slv = output_slv, TB_ERROR, "verify SLV no invert");
end if;
-- Verify output values
wait until output_sl = '0';
wait for C_PULSE_WIDTH; -- SL low period
-- Flip next expected interval validity
v_valid_interval := not(v_valid_interval);
end loop;
-- Reset VIPs for next test
reset_config;
end procedure test_stuck_at_old_error_injection;
--------------------------------------------------------------------
-- Test case for STUCK_AT_NEW error injection
--
-- This test will test stuck at new value error injection on a SL
-- and a SLV signal, with interval settings set to 1 and 2.
--
-- Note: test is self checking.
--------------------------------------------------------------------
procedure test_stuck_at_new_error_injection(void : t_void) is
variable v_slv_stuck_width : time := 45 ns;
variable v_sl_stuck_width : time := 35 ns;
variable v_idx : natural := 0;
begin
log(ID_LOG_HDR_XL, "Stuck at new error injection tests");
-----------------------------------------------------------------
-- Stuck at new test
----------------------------------------------------------------
log(ID_LOG_HDR, "Stuck at new test with stuck = 35 ns (SL) / 45 ns (SLV) and interval = 1.", C_SCOPE);
-- Configure SL and SLV EI VIPs
shared_ei_config(C_SL_EI_IDX).error_type := STUCK_AT_NEW;
shared_ei_config(C_SL_EI_IDX).width_min := v_sl_stuck_width;
shared_ei_config(C_SLV_EI_IDX).error_type := STUCK_AT_NEW;
shared_ei_config(C_SLV_EI_IDX).width_min := v_slv_stuck_width;
-- Verify initial values
check_value(output_sl, '0', TB_ERROR, "verify SL initial value");
check_value(output_slv, x"00", TB_ERROR, "verify SLV initial value");
--------
-- # 1
-- SL valid interval
-- SLV valid interval
--------
-- Activate SL pulse and set SLV input value on EI VIPs
v_idx := 1;
run_test(v_idx);
log(ID_SEQUENCER, "Verify stuck periods, valid interval for SL and SLV "&to_string(v_idx)&".\n", C_SCOPE);
-- Verify output values
wait until output_sl = '1';
v_timestamp_sl := now;
v_timestamp_slv := now;
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
-- Verify output values
wait until output_sl = '0';
check_value((now - v_timestamp_sl), v_sl_stuck_width, TB_ERROR, "verify SL stuck width");
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
wait for 2*C_PULSE_WIDTH - v_sl_stuck_width; -- SL low period
--------
-- # 2:
-- SL valid interval
-- SLV initial event is during stuck period and not detected for this run
--------
v_idx := 2;
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(v_idx);
log(ID_SEQUENCER, "Verify stuck periods, valid interval for SL "&to_string(v_idx)&".\n", C_SCOPE);
-- Verify output values
v_timestamp_sl := now;
wait until output_sl = '1';
check_value(output_slv, std_logic_vector(to_unsigned(v_idx-1, 8)), TB_ERROR, "verify SLV value still at previous");
-- Verify SLV output value
wait until output_slv = std_logic_vector(to_unsigned(v_idx, 8));
check_value((now-v_timestamp_slv), v_slv_stuck_width, TB_ERROR, "verify SLV stuck period "&to_string(v_idx));
-- Verify output values
v_timestamp_slv := now;
wait until output_sl = '0';
check_value((now - v_timestamp_sl), v_sl_stuck_width, TB_ERROR, "verify SL stuck width");
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
-----------------------------------------------------------------
-- Interval tests
-----------------------------------------------------------------
log(ID_LOG_HDR, "Stuck at new test with interval = 2.", C_SCOPE);
-- Reconfigure EI VIPs error injection interval
shared_ei_config(C_SL_EI_IDX).interval := 2;
shared_ei_config(C_SLV_EI_IDX).interval := 2;
-- wait remaining SL low period
wait for (2*C_PULSE_WIDTH) - v_sl_stuck_width;
--------
-- # 3
-- SL valid interval
-- SLV valid interval
--------
v_idx := 3;
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(v_idx);
log(ID_SEQUENCER, "Verify stuck periods, valid interval for SL and SLV "&to_string(v_idx)&".\n", C_SCOPE);
-- Verify output values
v_timestamp_sl := now;
v_timestamp_slv := now;
wait until output_sl = '1';
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
wait until output_sl = '0';
check_value(now-v_timestamp_sl, v_sl_stuck_width, TB_ERROR, "verify SL stuck width");
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
-- wait remaining SL low period
wait for (2*C_PULSE_WIDTH) - v_sl_stuck_width;
--------
-- # 4
-- SL not valid interval
-- SLV initial event is during stuck period and not detected for this run
--------
v_idx := 4;
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(v_idx);
log(ID_SEQUENCER, "Verify stuck periods, valid interval for SL "&to_string(v_idx)&".\n", C_SCOPE);
-- Verify output values
v_timestamp_sl := now;
wait until output_sl = '1';
check_value(output_slv, std_logic_vector(to_unsigned(v_idx-1, 8)), TB_ERROR, "verify SLV value still at previous");
-- Verify output values
wait until output_slv = std_logic_vector(to_unsigned(v_idx, 8));
check_value(now - v_timestamp_slv, v_slv_stuck_width, TB_ERROR, "verify SLV stuck width");
v_timestamp_slv := now;
-- Verify output values
wait until output_sl = '0';
check_value(now-v_timestamp_sl, C_PULSE_WIDTH, TB_ERROR, "verify SL high period");
-- wait SL low period
wait for C_PULSE_WIDTH;
--------
-- # 5
-- SL valid interval
-- SLV not valid interval
--------
v_idx := 5;
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(v_idx);
log(ID_SEQUENCER, "Verify stuck periods, valid interval for SL "&to_string(v_idx)&".\n", C_SCOPE);
-- Timing timestamps
v_timestamp_sl := now;
v_timestamp_slv := now;
-- Verify output values
wait until output_sl = '1';
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
-- Verify output values
wait until output_sl = '0';
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
check_value(now-v_timestamp_sl, v_sl_stuck_width, TB_ERROR, "verify SL stuck width");
-- wait remaining SL low period
wait for (2*C_PULSE_WIDTH) - v_sl_stuck_width;
--------
-- # 6
-- SL not valid interval
-- SLV valid interval
--------
v_idx := 6;
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(v_idx);
log(ID_SEQUENCER, "Verify stuck periods, valid interval for SLV "&to_string(v_idx)&".\n", C_SCOPE);
-- Timing timestamps
v_timestamp_sl := now;
v_timestamp_slv := now;
wait until output_sl = '1';
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
wait until output_sl = '0';
check_value(now-v_timestamp_sl, C_PULSE_WIDTH, TB_ERROR, "verify SL high period");
check_value(output_slv, std_logic_vector(to_unsigned(v_idx, 8)), TB_ERROR, "verify SLV value "&to_string(v_idx));
-- wait remaining SL low period
wait for C_PULSE_WIDTH;
--------
-- # 7
-- SL valid interval
-- SLV initial event is during stuck period and not detected for this run
--------
v_idx := 7;
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(v_idx);
log(ID_SEQUENCER, "Verify stuck periods, valid interval for SL "&to_string(v_idx)&".\n", C_SCOPE);
-- Timing timestamps
v_timestamp_sl := now;
wait until output_sl = '1';
check_value(output_slv, std_logic_vector(to_unsigned(v_idx-1, 8)), TB_ERROR, "verify SLV value still at previous");
wait until output_slv = std_logic_vector(to_unsigned(v_idx, 8));
check_value(now-v_timestamp_slv, v_slv_stuck_width, TB_ERROR, "verify SLV stuck width");
v_timestamp_slv := now;
wait until output_sl = '0';
check_value(now-v_timestamp_sl, v_sl_stuck_width, TB_ERROR, "verify SL stuck width");
-- wait remaining SL low period
wait for (2*C_PULSE_WIDTH) - v_sl_stuck_width;
-- Reset VIPs for next test
reset_config;
end procedure test_stuck_at_new_error_injection;
--------------------------------------------------------------------
-- Test case for BYPASS error injection
--
-- This test will test bypass setting for error injection on a SL
-- and a SLV signal, i.e. no error is injected.
--
-- Note: test is self checking.
--------------------------------------------------------------------
procedure test_bypass_error_injection(void : t_void) is
begin
log(ID_LOG_HDR_XL, "Bypass error injection tests");
-----------------------------------------------------------------
-- Stuck at new test
----------------------------------------------------------------
log(ID_LOG_HDR, "Bypass test and interval = 1.", C_SCOPE);
-- Configure SL and SLV EI VIPs
shared_ei_config(C_SL_EI_IDX) := C_EI_CONFIG_DEFAULT;
shared_ei_config(C_SLV_EI_IDX) := C_EI_CONFIG_DEFAULT;
for idx in 1 to 8 loop
-- Verify initial values
check_value(output_sl = '0', TB_ERROR, "verify SL output");
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8) - 1), TB_ERROR, "verify SLV output");
-- Activate SL pulse and set SLV input value on EI VIPs
run_test(idx);
-- Timing timestamps
v_timestamp_sl := now;
wait until output_sl = '1';
log(ID_SEQUENCER, "Verify SLV on SL high period "&to_string(idx)&".\n", C_SCOPE);
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV output");
wait until output_sl = '0';
log(ID_SEQUENCER, "Verify SLV on SL low period and width "&to_string(idx)&".\n", C_SCOPE);
check_value(output_slv, std_logic_vector(to_unsigned(idx, 8)), TB_ERROR, "verify SLV output");
check_value((now-v_timestamp_sl) = C_PULSE_WIDTH, TB_ERROR, "verify pulse width");
wait for C_PULSE_WIDTH; -- SL low period
end loop;
-- Reset VIPs for next test
reset_config;
end procedure test_bypass_error_injection;
begin
-- Wait for UVVM to finish initialization
await_uvvm_initialization(VOID);
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
set_alert_stop_limit(TB_ERROR, 1);
disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_SEQUENCER);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_LOG_HDR_XL);
enable_log_msg(ID_SEQUENCER_SUB);
log(ID_LOG_HDR, "Starting simulation of Error Injection VIP TB.", C_SCOPE);
--============================================================================================================
--
-- Note!
--
-- 1. Tests can be commented out to run single tests
--
-- 2. Tests are run with 8 signal events, and error injection with interval set to 1 on
-- the two first signal events, then reconfigured with interval set to 2 on the remaining
-- sixs signal events.
--
-- 3. Randomisation setting is tested in test_delay_error_injection().
--
test_delay_error_injection(VOID); -- with randomisation
test_jitter_error_injection(VOID);
test_invert_error_injection(VOID);
test_pulse_error_injection(VOID);
test_stuck_at_old_error_injection(VOID);
test_stuck_at_new_error_injection(VOID);
test_bypass_error_injection(VOID);
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_sequencer;
end func;
| mit |
UVVM/UVVM_All | uvvm_util/src/generic_queue_pkg.vhd | 1 | 50840 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.string_methods_pkg.all;
package generic_queue_pkg is
generic (type t_generic_element;
scope : string := C_SCOPE;
GC_QUEUE_COUNT_MAX : natural := 1000;
GC_QUEUE_COUNT_THRESHOLD : natural := 950);
-- When find_* doesn't find a match, they return C_NO_MATCH.
constant C_NO_MATCH : integer := -1;
-- A generic queue for verification
type t_generic_queue is protected
procedure add(
constant instance : in integer;
constant element : in t_generic_element);
procedure add(
constant element : in t_generic_element);
procedure put(
constant instance : in integer;
constant element : in t_generic_element);
procedure put(
constant element : in t_generic_element);
impure function get(
constant instance : in integer)
return t_generic_element;
impure function get(
constant dummy : in t_void)
return t_generic_element;
impure function is_empty(
constant instance : in integer)
return boolean;
impure function is_empty(
constant dummy : in t_void)
return boolean;
procedure set_scope(
constant instance : in integer;
constant scope : in string);
procedure set_scope(
constant scope : in string);
procedure set_name(
constant name : in string);
impure function get_scope(
constant instance : in integer)
return string;
impure function get_scope(
constant dummy : in t_void)
return string;
impure function get_count(
constant instance : in integer)
return natural;
impure function get_count(
constant dummy : in t_void)
return natural;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural);
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural);
impure function get_queue_count_threshold(
constant instance : in integer) return natural;
impure function get_queue_count_threshold(
constant dummy : in t_void) return natural;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void) return t_alert_level;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level);
impure function get_queue_count_max(
constant instance : in integer) return natural;
impure function get_queue_count_max(
constant dummy : in t_void) return natural;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural);
procedure set_queue_count_max(
constant queue_count_max : in natural);
procedure flush(
constant instance : in integer);
procedure flush(
constant dummy : in t_void);
procedure reset(
constant instance : in integer);
procedure reset(
constant dummy : in t_void);
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
);
procedure delete(
constant element : in t_generic_element
);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant instance : in integer
) return t_generic_element;
impure function peek(
constant dummy : in t_void
) return t_generic_element;
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant instance : in integer
) return t_generic_element;
impure function fetch(
constant dummy : in t_void
) return t_generic_element;
impure function find_position(
constant element : in t_generic_element) return integer;
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean;
impure function exists(
constant element : in t_generic_element
) return boolean;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive) return integer;
impure function get_entry_num(
constant position_val : in positive) return integer;
procedure print_queue(
constant instance : in integer);
procedure print_queue(
constant dummy : in t_void);
end protected;
end package generic_queue_pkg;
package body generic_queue_pkg is
type t_generic_queue is protected body
-- Types and control variables for the linked list implementation
type t_element;
type t_element_ptr is access t_element;
type t_element is record
entry_num : natural;
next_element : t_element_ptr;
element_data : t_generic_element;
end record;
type t_element_ptr_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of t_element_ptr;
type t_string_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of string(1 to C_LOG_SCOPE_WIDTH);
variable vr_last_element : t_element_ptr_array := (others => null); -- Back entry
variable vr_first_element : t_element_ptr_array := (others => null); -- Front entry
variable vr_num_elements_in_queue : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0);
-- Scope variables
variable vr_scope : t_string_array := (others => (others => NUL));
variable vr_scope_is_defined : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
-- Name variables
variable vr_name : string(1 to C_LOG_SCOPE_WIDTH) := (others => NUL);
variable vr_name_is_defined : boolean := false;
variable vr_queue_count_max : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_MAX);
variable vr_queue_count_threshold : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_THRESHOLD);
variable vr_queue_count_threshold_severity : t_alert_level := TB_WARNING;
variable vr_entry_num : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Incremented before first insert
-- Fill level alert
type t_queue_count_threshold_alert_frequency is (ALWAYS, FIRST_TIME_ONLY);
constant C_ALERT_FREQUENCY : t_queue_count_threshold_alert_frequency := FIRST_TIME_ONLY;
variable vr_queue_count_threshold_triggered : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
------------------------------------------------------------------------------------------------------
--
-- Helper methods (not visible from outside)
--
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
-- Helper method: Check if an Alert shall be triggered (to be called before adding another entry)
------------------------------------------------------------------------------------------------------
procedure perform_pre_add_checks (
constant instance : in integer
) is
begin
if((vr_queue_count_threshold(instance) /= 0) and (vr_num_elements_in_queue(instance) >= vr_queue_count_threshold(instance))) then
if((C_ALERT_FREQUENCY = ALWAYS) or (C_ALERT_FREQUENCY = FIRST_TIME_ONLY and not vr_queue_count_threshold_triggered(instance))) then
alert(vr_queue_count_threshold_severity, "Queue is now at " & to_string(vr_queue_count_threshold(instance)) & " of " & to_string(vr_queue_count_max(instance)) & " elements.", vr_scope(instance));
vr_queue_count_threshold_triggered(instance) := true;
end if;
end if;
end procedure;
------------------------------------------------------------------------------------------------------
-- Helper method: Iterate through all entries, and match the one with element_data = element
-- This also works if the element is a record or array, whereas all entries/indexes must match
------------------------------------------------------------------------------------------------------
procedure match_element_data (
instance : in integer; -- Queue instance
element : in t_generic_element; -- Element to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr -- valid if found_match=true
) is
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
variable v_element_ptr : t_element_ptr; -- Entry currently being checked for match
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
if vr_num_elements_in_queue(instance) > 0 then
-- Search from front to back element
v_element_ptr := vr_first_element(instance);
loop
if v_element_ptr.element_data = element then -- Element matched entry
found_match := true;
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else -- No match.
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop;
end if;
end procedure;
-- Find and return entry that matches the identifier
procedure match_identifier (
instance : in integer; -- Queue instance
identifier_option : in t_identifier_option; -- Determines what 'identifier' means
identifier : in positive; -- Identifier value to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr; -- valid if found_match=true
preceding_element_ptr : out t_element_ptr -- valid if found_match=true. Element at position-1, pointing to elemnt_ptr
) is
-- Search from front to back element. Init pointers/counters to the first entry:
variable v_element_ptr : t_element_ptr := vr_first_element(instance); -- Entry currently being checked for match
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
preceding_element_ptr := null;
-- If queue is not empty and indentifier in valid range
if (vr_num_elements_in_queue(instance) > 0) and
((identifier_option = POSITION and identifier <= vr_num_elements_in_queue(instance)) or
(identifier_option = ENTRY_NUM and identifier <= vr_entry_num(instance))) then
loop
-- For each element in queue:
-- Check if POSITION or ENTRY_NUM matches v_element_ptr
if (identifier_option = POSITION) and (v_position_ctr = identifier) then
found_match := true;
end if;
if (identifier_option = ENTRY_NUM) and (v_element_ptr.entry_num = identifier) then
found_match := true;
end if;
if found_match then
-- This element matched. Done searching.
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else
-- No match.
if v_element_ptr.next_element = null then
-- report "last v_position_ctr = " & to_string(v_position_ctr);
exit; -- Last entry. All queue entries have been searched through.
end if;
preceding_element_ptr := v_element_ptr; -- the entry at the postition before element_ptr
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop; -- for each element in queue
end if; -- Not empty
end procedure;
------------------------------------------------------------------------------------------------------
--
-- Public methods, visible from outside
--
------------------------------------------------------------------------------------------------------
-- add : Insert element in the back of queue, i.e. at the highest position
procedure add(
constant instance : in integer;
constant element : in t_generic_element
) is
constant proc_name : string := "add";
variable v_previous_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
-- Increment vr_entry_num
vr_entry_num(instance) := vr_entry_num(instance)+1;
-- Set read and write pointers when appending element to existing list
if vr_num_elements_in_queue(instance) > 0 then
v_previous_ptr := vr_last_element(instance);
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
v_previous_ptr.next_element := vr_last_element(instance); -- Insert the new element into the linked list
else -- List is empty
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
vr_first_element(instance) := vr_last_element(instance); -- Update read pointer, since this is the first and only element in the list.
end if;
-- Increment number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1;
end procedure;
procedure add(
constant element : in t_generic_element
) is
begin
add(1, element);
end procedure;
procedure put(
constant instance : in integer;
constant element : in t_generic_element
) is
begin
add(instance, element);
end procedure;
procedure put(
constant element : in t_generic_element
) is
begin
put(1, element);
end procedure;
impure function get(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance);
end function;
impure function get(
constant dummy : in t_void
) return t_generic_element is
begin
return get(1);
end function;
procedure flush(
constant instance : in integer
) is
variable v_to_be_deallocated_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "Scope name must be defined for this generic queue " &to_string(instance), "???", ID_NEVER);
-- Deallocate all entries in the list
-- Setting the last element to null and iterating over the queue until finding the null element
vr_last_element(instance) := null;
while vr_first_element(instance) /= null loop
v_to_be_deallocated_ptr := vr_first_element(instance);
vr_first_element(instance) := vr_first_element(instance).next_element;
DEALLOCATE(v_to_be_deallocated_ptr);
end loop;
-- Reset the queue counter
vr_num_elements_in_queue(instance) := 0;
vr_queue_count_threshold_triggered(instance) := false;
end procedure;
procedure flush(
constant dummy : in t_void
) is
begin
flush(1);
end procedure;
procedure reset(
constant instance : in integer) is
begin
flush(instance);
vr_entry_num(instance) := 0; -- Incremented before first insert
end procedure;
procedure reset(
constant dummy : in t_void) is
begin
reset(1);
end procedure;
impure function is_empty(
constant instance : in integer
) return boolean is
begin
if vr_num_elements_in_queue(instance) = 0 then
return true;
else
return false;
end if;
end function;
impure function is_empty(
constant dummy : in t_void
) return boolean is
begin
return is_empty(1);
end function;
procedure set_scope(
constant instance : in integer;
constant scope : in string) is
begin
if instance = ALL_INSTANCES then
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope := (others => scope(1 to C_LOG_SCOPE_WIDTH));
else
for idx in vr_scope'range loop
vr_scope(idx) := (others => NUL);
vr_scope(idx)(1 to scope'length) := scope;
end loop;
end if;
vr_scope_is_defined := (others => true);
else
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope(instance) := scope(1 to C_LOG_SCOPE_WIDTH);
else
vr_scope(instance) := (others => NUL);
vr_scope(instance)(1 to scope'length) := scope;
end if;
vr_scope_is_defined(instance) := true;
end if;
end procedure;
procedure set_scope(
constant scope : in string) is
begin
set_scope(1, scope);
end procedure;
procedure set_name(
constant name : in string) is
begin
vr_name(1 to name'length) := name;
vr_name_is_defined := true;
end procedure;
impure function get_scope(
constant instance : in integer
) return string is
begin
return to_string(vr_scope(instance));
end function;
impure function get_scope(
constant dummy : in t_void
) return string is
begin
return get_scope(1);
end function;
impure function get_count(
constant instance : in integer
) return natural is
begin
return vr_num_elements_in_queue(instance);
end function;
impure function get_count(
constant dummy : in t_void
) return natural is
begin
return get_count(1);
end function;
impure function get_queue_count_max(
constant instance : in integer
) return natural is
begin
return vr_queue_count_max(instance);
end function;
impure function get_queue_count_max(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_max(1);
end function;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural
) is
begin
vr_queue_count_max(instance) := queue_count_max;
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, "set_queue_count_max() new queue max count (" & to_string(vr_queue_count_max(instance)) & ") is less than current queue count(" & to_string(vr_num_elements_in_queue(instance)) & ").", vr_scope(instance), ID_NEVER);
end procedure;
procedure set_queue_count_max(
constant queue_count_max : in natural
) is
begin
set_queue_count_max(1, queue_count_max);
end procedure;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural
) is
begin
vr_queue_count_threshold(instance) := queue_count_alert_level;
end procedure;
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural
) is
begin
set_queue_count_threshold(1, queue_count_alert_level);
end procedure;
impure function get_queue_count_threshold(
constant instance : in integer
) return natural is
begin
return vr_queue_count_threshold(instance);
end function;
impure function get_queue_count_threshold(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_threshold(1);
end function;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void
) return t_alert_level is
begin
return vr_queue_count_threshold_severity;
end function;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level) is
begin
vr_queue_count_threshold_severity := alert_level;
end procedure;
----------------------------------------------------
-- Insert:
----------------------------------------------------
-- Inserts element into the queue after the matching entry with specified identifier:
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element)
is
constant proc_name : string := "insert";
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_preceding_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_found_match : boolean;
variable v_matched_position : integer;
begin
-- pre insert checks
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
if (identifier /= 1) then
if (identifier_option = POSITION) then
check_value(vr_num_elements_in_queue(instance) >= identifier, TB_ERROR, proc_name & "() into position larger than number of elements in queue. Use add() instead when inserting at the back of the queue", vr_scope(instance), ID_NEVER);
else -- identifier_option /= POSITION
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() into empty queue isn't supported. Use add() instead", vr_scope(instance), ID_NEVER);
end if;
end if;
-- Search from front to back element.
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Make new element
vr_entry_num(instance) := vr_entry_num(instance)+1; -- Increment vr_entry_num
-- POSITION: insert at matched position
if identifier_option = POSITION then
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr,
element_data => element);
-- if match is first element
if v_preceding_element_ptr = null then
vr_first_element(instance) := v_new_element_ptr; -- Insert the new element into the front of the linked list
else
v_preceding_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
--ENTRY_NUM: insert at position after match
else
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr.next_element,
element_data => element);
v_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; -- Increment number of elements
elsif identifier_option = POSITION then -- v_found_match = false
if identifier = 1 then
add(instance, element);
end if;
elsif identifier_option = ENTRY_NUM then
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier) &
", element...", scope);
end if;
end if;
end procedure;
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element) is
begin
insert(1, identifier_option, identifier, element);
end procedure;
----------------------------------------------------
-- delete:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
constant proc_name : string := "delete";
variable v_matched_element_ptr : t_element_ptr; -- The element being deleted
variable v_element_to_delete_ptr : t_element_ptr; -- The element being deleted
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
variable v_deletes_remaining : integer;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
-- delete based on POSITION :
-- Note that when deleting the first position, all above positions are decremented by one.
-- Find the identifier_min, delete it, and following next_element until we reach number of positions to delete
if (identifier_option = POSITION) then
check_value(vr_num_elements_in_queue(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > generic queue size", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- Find min position
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier_min,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr; -- Delete element at identifier_min first
while v_deletes_remaining > 0 loop
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_element_to_delete_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
v_deletes_remaining := v_deletes_remaining - 1;
-- Prepare next iteration:
-- Next element to delete:
if v_deletes_remaining > 0 then
if (v_preceding_element_ptr = null) then
-- We just removed the first entry, so there's no pointer from a preceding entry. Next to delete is the first entry.
v_element_to_delete_ptr := vr_first_element(instance);
else -- Removed an intermediate or last entry. Next to delete is the pointer from the preceding element
v_element_to_delete_ptr := v_preceding_element_ptr.next_element;
end if;
end if;
end loop;
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier_min), scope);
end if;
end if; -- v_found_match
-- delete based on ENTRY_NUM :
-- Unlike position, an entry's Entry_num is stable when deleting other entries
-- Entry_num is not necessarily increasing as we follow next_element pointers.
-- This means that we must do a complete search for each entry we want to delete
elsif (identifier_option = ENTRY_NUM) then
check_value(vr_entry_num(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > highest entry number", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- For each entry to delete, find it based on entry_num , then delete it
for identifier in identifier_min to identifier_max loop
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_element_to_delete_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier), scope);
end if;
end if; -- v_found_match
end loop;
end if; -- identifier_option
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
begin
delete(1, identifier_option, identifier_min, identifier_max);
end procedure;
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
) is
variable v_entry_num : integer:= find_entry_num(element);
begin
delete(instance, ENTRY_NUM, v_entry_num, v_entry_num);
end procedure;
procedure delete(
constant element : in t_generic_element
) is
begin
delete(1, element);
end procedure;
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
case range_option is
when SINGLE =>
delete(instance, identifier_option, identifier, identifier);
when AND_LOWER =>
delete(instance, identifier_option, 1, identifier);
when AND_HIGHER =>
if identifier_option = POSITION then
delete(instance, identifier_option, identifier, vr_num_elements_in_queue(instance));
elsif identifier_option = ENTRY_NUM then
delete(instance, identifier_option, identifier, vr_entry_num(instance));
end if;
end case;
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
delete(1, identifier_option, identifier, range_option);
end procedure;
----------------------------------------------------
-- peek:
----------------------------------------------------
-- Read the entry matching the identifier, but don't remove it.
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "peek";
variable v_matched_element_data : t_generic_element; -- Return value
variable v_matched_element_ptr : t_element_ptr; -- The element currently being processed
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_matched_element_data := v_matched_element_ptr.element_data;
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return peek(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function peek(
constant instance : in integer
) return t_generic_element is
begin
return peek(instance, POSITION, 1);
end function;
impure function peek(
constant dummy : in t_void
) return t_generic_element is
begin
return peek(1);
end function;
----------------------------------------------------
-- Fetch:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "fetch";
variable v_matched_element_ptr : t_element_ptr; -- The element being fetched
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Keep info about element before removing it from queue
v_matched_element_data := v_matched_element_ptr.element_data;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_matched_element_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_matched_element_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_matched_element_ptr);
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return fetch(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function fetch(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance, POSITION, 1);
end function;
impure function fetch(
constant dummy : in t_void
) return t_generic_element is
begin
return fetch(1);
end function;
-- Returns position of entry if found, else C_NO_MATCH.
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element --
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_position: Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
-- Don't include this check, because we may want to use exists() on an empty queue.
-- check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_position() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_matched_position;
else
return C_NO_MATCH;
end if;
end function;
impure function find_position(
constant element : in t_generic_element
) return integer is
begin
return find_position(1, element);
end function;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean is
begin
return (find_position(instance, element) /= C_NO_MATCH);
end function;
impure function exists(
constant element : in t_generic_element
) return boolean is
begin
return exists(1, element);
end function;
-- Returns entry number or position to entry if found, else C_NO_MATCH.
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_element_ptr.entry_num;
else
return C_NO_MATCH;
end if;
end function;
impure function find_entry_num(
constant element : in t_generic_element
) return integer is
begin
return find_entry_num(1, element);
end function;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive
) return integer is
variable v_found_match : boolean;
variable v_matched_position : integer;
variable v_matched_element_ptr : t_element_ptr;
variable v_preceding_element_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "get_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "get_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => POSITION ,
identifier => position_val,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
return v_matched_element_ptr.entry_num;
else
return -1;
end if;
end function get_entry_num;
impure function get_entry_num(
constant position_val : in positive
) return integer is
begin
return get_entry_num(1, position_val);
end function get_entry_num;
-- for debugging:
-- print each entry's position and entry_num
procedure print_queue(
constant instance : in integer
)
is
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_position_ctr : natural := 1; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
-- Search from front to back element. Initalise pointers/counters to the first entry:
v_element_ptr := vr_first_element(instance);
if v_element_ptr = NULL then
return; -- Return if queue is empty
end if;
loop
log(ID_UVVM_DATA_QUEUE, "Pos=" & to_string(v_position_ctr) & ", entry_num=" & to_string(v_element_ptr.entry_num) , scope);
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end loop;
end procedure;
procedure print_queue(
constant dummy : in t_void) is
begin
print_queue(1);
end procedure;
end protected body;
end package body generic_queue_pkg;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_ibttcc.vhd | 18 | 112659 | -------------------------------------------------------------------------------
-- axi_datamover_ibttcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ibttcc.vhd
--
-- Description:
-- This file implements the DataMover Indeterminate BTT Command Calculator
-- (SFCC) for the Indeterminate BTT operation mode of the DataMover S2MM
-- function. Since Indeterminate BTT is totally dependent on the data
-- received from the S2MM input Stream for command generation, Predictive
-- child request calculation is not needed.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ibttcc is
generic (
C_SF_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- sets the width of the sf2pcc_xfer_bytes port which is
-- used to indicate the number of actual bytes received
-- by the IBTT functions
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16 ;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions incorporating
-- upsizer/downsizer logic.
);
port (
-- Clock and Reset input ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- Master Command FIFO/Register Interface ------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at least 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Store and Forward Block Interface -----------------------------------------------
--
sf2pcc_xfer_valid : In std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the IBtt --
-- XFER_DESCR_FIFO. --
--
pcc2sf_xfer_ready : Out std_logic; --
-- Indicates to the Store and Forward module that the xfer descriptor --
-- is being accepted by the SFCC. --
--
--
sf2pcc_cmd_cmplt : In std_logic; --
-- Indicates that the next Store and Forward pending data block --
-- is the last one associated with the corresponding command loaded --
-- into the Realigner. --
--
--
sf2pcc_packet_eop : In std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor. --
--
--
sf2pcc_xfer_bytes : In std_logic_vector(C_SF_XFER_BYTES_WIDTH-1 downto 0); --
-- This data byte count is used by the SFCC to increment the Address --
-- Counter to the next starting address for the next sequential transfer. --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface -----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ---------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
-- Special S2MM DRE Controller Interface -------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_ibttcc;
architecture implementation of axi_datamover_ibttcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calcilates the AXi MMAP Size qualifier based on the data width
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH + 1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant SF_BYTE_XFERED_WIDTH : integer := C_SF_XFER_BYTES_WIDTH;
Constant BTT_UPPER_WIDTH : integer := CMD_BTT_WIDTH - BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_UPPER_LS_INDEX : integer := BTT_RESIDUE_WIDTH;
Constant BTT_UPPER_ZERO : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PARENT_SM_STATE_TYPE is (
P_INIT,
P_WAIT_FOR_CMD,
P_LD_FIRST_CMD,
P_LD_CHILD_CMD,
P_LD_LAST_CMD ,
EXTRA, EXTRA2,
P_ERROR_TRAP
);
type CHILD_SM_STATE_TYPE is (
CH_INIT,
WAIT_FOR_PCMD,
CH_WAIT_FOR_SF_CMD,
CH_LD_CHILD_CMD,
CH_CHK_IF_DONE,
CH_ERROR_TRAP1,
CH_ERROR_TRAP2
);
-- Signal Declarations --------------------------------------------
-- Parent Command State Machine
Signal sig_psm_state : PARENT_SM_STATE_TYPE := P_INIT;
Signal sig_psm_state_ns : PARENT_SM_STATE_TYPE := P_INIT;
signal sig_psm_halt_ns : std_logic := '0';
signal sig_psm_halt : std_logic := '0';
signal sig_psm_pop_input_cmd_ns : std_logic := '0';
signal sig_psm_pop_input_cmd : std_logic := '0';
signal sig_psm_ld_calc1_ns : std_logic := '0';
signal sig_psm_ld_calc1 : std_logic := '0';
signal sig_psm_ld_calc2_ns : std_logic := '0';
signal sig_psm_ld_calc2 : std_logic := '0';
signal sig_psm_ld_realigner_reg_ns : std_logic := '0';
signal sig_psm_ld_realigner_reg : std_logic := '0';
signal sig_psm_ld_chcmd_reg_ns : std_logic := '0';
signal sig_psm_ld_chcmd_reg : std_logic := '0';
-- Child Command State Machine
Signal sig_csm_state : CHILD_SM_STATE_TYPE := CH_INIT;
Signal sig_csm_state_ns : CHILD_SM_STATE_TYPE := CH_INIT;
signal sig_csm_ld_xfer : std_logic := '0';
signal sig_csm_ld_xfer_ns : std_logic := '0';
signal sig_csm_pop_sf_fifo : std_logic := '0';
signal sig_csm_pop_sf_fifo_ns : std_logic := '0';
signal sig_csm_pop_child_cmd : std_logic := '0';
signal sig_csm_pop_child_cmd_ns : std_logic := '0';
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_last_xfer_valid : std_logic := '0';
signal sig_btt_residue_slice : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_child_addr_cntr : std_logic := '0';
signal sig_incr_child_addr_cntr : std_logic := '0';
signal sig_child_addr_cntr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_is_seq : std_logic := '0';
signal sig_xfer_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
-- PCC2 stuff
signal sig_first_child_xfer : std_logic := '0';
signal sig_bytes_to_mbaa : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_lsh_rollover : std_logic := '0';
signal sig_child_addr_lsh_rollover_reg : std_logic := '0';
--signal sig_child_addr_msh_rollover : std_logic := '0';
--signal sig_child_addr_msh_rollover_reg : std_logic := '0';
signal sig_child_addr_msh_eq_max : std_logic := '0';
--signal sig_child_addr_msh_eq_max_reg : std_logic := '0';
signal sig_predict_child_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_child_addr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_cntr_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_lt_b2mbaa : std_logic := '0';
signal sig_btt_eq_b2mbaa : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
--signal sig_adjusted_child_addr_incr_reg : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_realigner_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realigner_btt2 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
-- Store and forward signals
signal sig_ld_realigner_cmd : std_logic := '0';
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(SF_BYTE_XFERED_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_push_realign_reg : std_logic := '0';
signal sig_pop_realign_reg : std_logic := '0';
signal sig_realign_reg_empty : std_logic := '0';
signal sig_realign_reg_full : std_logic := '0';
signal sig_first_realigner_cmd : std_logic := '0';
signal sig_realign_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_src_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_dest_align_reg : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_drr_reg : std_logic := '0';
signal sig_realign_eof_reg : std_logic := '0';
signal sig_realign_cmd_cmplt_reg : std_logic := '0';
signal sig_realign_calc_err_reg : std_logic := '0';
signal sig_last_s_f_xfer_ld : std_logic := '0';
signal sig_skip_align2mbaa : std_logic := '0';
signal sig_skip_align2mbaa_s_h : std_logic := '0';
signal sig_dre_dest_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0);
signal sig_realign_btt_cntr_decr : Unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_input_addr_reg1 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_push_child_cmd_reg : std_logic := '0';
signal sig_pop_child_cmd_reg : std_logic := '0';
signal sig_child_cmd_reg_empty : std_logic := '0';
signal sig_child_cmd_reg_full : std_logic := '0';
signal sig_child_burst_type_reg : std_logic := '0';
signal sig_child_cache_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_user_type_reg : std_logic_vector (3 downto 0) := (others =>'0');
signal sig_child_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_child_error_reg : std_logic := '0';
signal sig_ld_child_qual_reg : std_logic := '0';
signal sig_child_qual_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_child_qual_burst_type : std_logic := '0';
signal sig_child_qual_cache_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_user_type : std_logic_vector (3 downto 0) := (others => '0');
signal sig_child_qual_first_of_2 : std_logic := '0';
signal sig_child_qual_error_reg : std_logic := '0';
signal sig_needed_2_realign_cmds : std_logic := '0';
signal sig_btt_upper_slice : unsigned(BTT_UPPER_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_upper_eq_0 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
signal sig_realign_strt_offset_reg : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_realign_strt_offset : std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_input_addr_reg1 : signal is "TRUE"; -- definition
Attribute KEEP of sig_input_addr_reg : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg1 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_input_addr_reg : signal is "no";
begin --(architecture implementation)
-- sf Interface signals
pcc2sf_xfer_ready <= sig_pcc2sf_xfer_ready ;
sig_sf2pcc_xfer_valid <= sf2pcc_xfer_valid ;
sig_sf2pcc_cmd_cmplt <= sf2pcc_cmd_cmplt ;
sig_sf2pcc_xfer_bytes <= sf2pcc_xfer_bytes ;
sig_sf2pcc_packet_eop <= sf2pcc_packet_eop ;
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_psm_halt) and
sig_input_reg_empty;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg ;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid ;
mstr2addr_calc_error <= sig_xfer_calc_err_reg ;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg ;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the S2MM Realigner Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by S2MM DRE
mstr2dre_tag <= sig_realign_tag_reg ; -- Used by S2MM DRE
mstr2dre_dre_src_align <= sig_realign_src_align_reg ; -- Used by S2MM DRE
mstr2dre_dre_dest_align <= sig_realign_dest_align_reg; -- Used by S2MM DRE
mstr2dre_btt <= sig_realign_btt_reg ; -- Used by S2MM DRE
mstr2dre_drr <= sig_realign_drr_reg ; -- Used by S2MM DRE
mstr2dre_eof <= sig_realign_eof_reg ; -- Used by S2MM DRE
mstr2dre_cmd_cmplt <= sig_realign_cmd_cmplt_reg ; -- Used by S2MM DRE
mstr2dre_calc_error <= sig_realign_calc_err_reg ; -- Used by S2MM DRE
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_realign_strt_offset_reg;
-- Start internal logic.
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); -- always incrementing (per Interface_X guidelines)
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input Parent command Register design
sig_push_input_reg <= not(sig_psm_halt) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_psm_pop_input_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
-- used by the parent Command calculation.
-------------------------------------------------------------
HIGH_STREAM_WIDTH_REG_GEN : if (C_STREAM_DWIDTH >= 128) generate
begin
REG_INPUT_DUP_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_addr_reg1 <= (others => '0');
elsif (sig_push_input_reg = '1') then
sig_input_addr_reg1 <= sig_cmd_addr_slice;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_DUP_QUAL;
end generate HIGH_STREAM_WIDTH_REG_GEN;
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_addr_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_addr_reg <= sig_cmd_addr_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
-------------------------------------------------------------------------
-- SFCC Parent State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PARENT_SM_COMBINATIONAL
--
-- Process Description:
-- SFCC Parent State Machine combinational implementation,
-- This state machine controls the loading of commands into
-- the Realigner block. There is a maximum of two cmds per
-- DataMover input command to be loaded in the realigner.
--
-------------------------------------------------------------
PARENT_SM_COMBINATIONAL : process (sig_psm_state ,
sig_push_input_reg ,
sig_calc_error_reg ,
sig_first_realigner_cmd ,
sig_skip_align2mbaa ,
sig_skip_align2mbaa_s_h ,
sig_realign_reg_empty ,
sig_child_cmd_reg_full)
begin
-- SM Defaults
sig_psm_state_ns <= P_INIT;
sig_psm_halt_ns <= '0' ;
sig_psm_pop_input_cmd_ns <= '0' ;
sig_psm_ld_calc1_ns <= '0' ;
sig_psm_ld_calc2_ns <= '0' ;
sig_psm_ld_realigner_reg_ns <= '0' ;
sig_psm_ld_chcmd_reg_ns <= '0' ;
case sig_psm_state is
--------------------------------------------
when P_INIT =>
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_halt_ns <= '1';
--------------------------------------------
when P_WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_psm_state_ns <= P_LD_FIRST_CMD;
else
sig_psm_state_ns <= P_WAIT_FOR_CMD;
End if;
--------------------------------------------
when P_LD_FIRST_CMD => -- (load first Realigner Command)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD; --EXTRA;
sig_psm_ld_realigner_reg_ns <= '1';
sig_psm_ld_calc1_ns <= '1';
else
sig_psm_state_ns <= P_LD_FIRST_CMD;
End if;
-- when EXTRA =>
-- sig_psm_state_ns <= P_LD_CHILD_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1';
-- sig_psm_ld_calc1_ns <= '1';
--------------------------------------------
when P_LD_CHILD_CMD => -- (load Child Command Register)
If (sig_child_cmd_reg_full = '1') Then
sig_psm_state_ns <= P_LD_CHILD_CMD;
Elsif (sig_calc_error_reg = '1') Then
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_ld_chcmd_reg_ns <= '1' ;
Elsif ((sig_skip_align2mbaa = '1' and
sig_first_realigner_cmd = '1') or
sig_skip_align2mbaa_s_h = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD;
sig_psm_ld_chcmd_reg_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
sig_psm_ld_chcmd_reg_ns <= '1';
End if;
--------------------------------------------
when P_LD_LAST_CMD => -- (load second Realigner Command if needed)
If (sig_realign_reg_empty = '1') Then
sig_psm_state_ns <= P_WAIT_FOR_CMD; --EXTRA2;
sig_psm_ld_realigner_reg_ns <= '1' ;
sig_psm_ld_calc2_ns <= '1' ;
sig_psm_pop_input_cmd_ns <= '1' ;
else
sig_psm_state_ns <= P_LD_LAST_CMD;
End if;
-- when EXTRA2 =>
-- sig_psm_state_ns <= P_WAIT_FOR_CMD;
-- sig_psm_ld_realigner_reg_ns <= '1' ;
-- sig_psm_ld_calc2_ns <= '1' ;
-- sig_psm_pop_input_cmd_ns <= '1' ;
--------------------------------------------
when P_ERROR_TRAP =>
sig_psm_state_ns <= P_ERROR_TRAP;
sig_psm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_psm_state_ns <= P_INIT;
end case;
end process PARENT_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SFCC_SM_REGISTERED
--
-- Process Description:
-- SFCC State Machine registered implementation
--
-------------------------------------------------------------
SFCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_psm_state <= P_INIT;
sig_psm_halt <= '1' ;
sig_psm_pop_input_cmd <= '0' ;
sig_psm_ld_calc1 <= '0' ;
sig_psm_ld_calc2 <= '0' ;
sig_psm_ld_realigner_reg <= '0' ;
sig_psm_ld_chcmd_reg <= '0' ;
else
sig_psm_state <= sig_psm_state_ns ;
sig_psm_halt <= sig_psm_halt_ns ;
sig_psm_pop_input_cmd <= sig_psm_pop_input_cmd_ns ;
sig_psm_ld_calc1 <= sig_psm_ld_calc1_ns ;
sig_psm_ld_calc2 <= sig_psm_ld_calc2_ns ;
sig_psm_ld_realigner_reg <= sig_psm_ld_realigner_reg_ns ;
sig_psm_ld_chcmd_reg <= sig_psm_ld_chcmd_reg_ns ;
end if;
end if;
end process SFCC_SM_REGISTERED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_REALIGNER_CMD
--
-- Process Description:
-- Implements the register flop signalling the first realigner
-- transfer flag. The Realigner is loaded with 1 command if
-- the starting address is aligned to the mbaa, else two
-- commands are required.
--
-------------------------------------------------------------
IMP_FIRST_REALIGNER_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_realigner_reg = '1' and
sig_push_input_reg = '0')) then
sig_first_realigner_cmd <= '0';
elsif (sig_push_input_reg = '1') then
sig_first_realigner_cmd <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_REALIGNER_CMD;
--------------------------------------------------------------
-- Parent BTT Counter Logic (for Realigner cmd calc)
sig_ld_btt_cntr <= sig_push_input_reg;
sig_decr_btt_cntr <= sig_push_realign_reg;
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice <= sig_btt_cntr(BTT_RESIDUE_WIDTH-1 downto 0);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation. This is only used
-- to set up the Realigner commands.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr <= sig_btt_cntr-UNSIGNED(sig_realigner_btt2);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
IMP_BTT_CNTR2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_realigner_btt2 <= (others => '0');
Else
sig_realigner_btt2 <= sig_realigner_btt;
end if;
end if;
end process IMP_BTT_CNTR2;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
-- sig_realigner_btt <= STD_LOGIC_VECTOR(RESIZE(sig_child_addr_cntr_incr, CMD_BTT_WIDTH))
sig_realigner_btt <= STD_LOGIC_VECTOR(sig_realign_btt_cntr_decr)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else STD_LOGIC_VECTOR(sig_btt_cntr);
----------------- Parent Address Calculations ------------------------------
HIGH_STREAM_WIDTH : if (C_STREAM_DWIDTH >= 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg1(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate HIGH_STREAM_WIDTH;
LOW_STREAM_WIDTH : if (C_STREAM_DWIDTH < 128) generate
begin
sig_mbaa_addr_cntr_slice <= UNSIGNED(sig_input_addr_reg(MBAA_ADDR_SLICE_WIDTH-1 downto 0));
end generate LOW_STREAM_WIDTH;
-- Check to see if the starting address is already aligned to Max Burst byte aligned
-- boubdary
sig_addr_aligned <= '1'
when (sig_mbaa_addr_cntr_slice = BTT_RESIDUE_0)
Else '0';
-- Calculate the distance in bytes from the starting address to the next max
-- burst aligned address boundary
sig_bytes_to_mbaa <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH)
When (sig_addr_aligned = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice,ADDR_CNTR_WIDTH);
sig_btt_upper_slice <= sig_btt_cntr(BTT_UPPER_MS_INDEX downto BTT_UPPER_LS_INDEX);
sig_btt_upper_eq_0 <= '1'
When (sig_btt_upper_slice = BTT_UPPER_ZERO) or
(BTT_RESIDUE_WIDTH = CMD_BTT_WIDTH)
Else '0';
sig_btt_lt_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
sig_btt_eq_b2mbaa <= '1'
when ((RESIZE(sig_btt_residue_slice, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa) and
(sig_first_realigner_cmd = '1') and
(sig_btt_upper_eq_0 = '1'))
Else '0';
-- This signal used to flag if the SFCC can skip the initial split and
-- align process to get subsequent burst starting addresses aligned to
-- the Max burst aligned address boundary (needed to support the 4k byte
-- boundary crossing guard function).
sig_skip_align2mbaa <= '1'
when (sig_addr_aligned = '1' or
sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1' or
sig_calc_error_reg = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKIP_ALIGN_FLOP
--
-- Process Description:
-- Just a FLOP to sample and hold the flag indicating that a
-- aligment to a Max Burst align address is not required. This
-- is used by the parent command state machine.
--
-------------------------------------------------------------
SKIP_ALIGN_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_psm_ld_chcmd_reg = '1' and
sig_psm_ld_realigner_reg = '0')) then
sig_skip_align2mbaa_s_h <= '0';
elsif (sig_psm_ld_realigner_reg = '1') then
sig_skip_align2mbaa_s_h <= sig_skip_align2mbaa;
else
null; -- Hold current state
end if;
end if;
end process SKIP_ALIGN_FLOP;
-- Select the Realigner BTT counter decrement value to use
sig_realign_btt_cntr_decr <= RESIZE(sig_btt_residue_slice, CMD_BTT_WIDTH)
When (sig_first_realigner_cmd = '1' and
(sig_btt_lt_b2mbaa = '1' or
sig_btt_eq_b2mbaa = '1'))
else RESIZE(sig_bytes_to_mbaa, CMD_BTT_WIDTH)
when (sig_first_realigner_cmd = '1' and
sig_skip_align2mbaa = '0')
else sig_btt_cntr;
-----------------------------------------------------------------
-- Realigner Qualifier Register design
sig_dre_dest_align <= sig_input_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_realign_strt_offset <= sig_input_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX)
When (sig_psm_ld_calc1 = '1') -- Specified starting addr offset used for IBTT Upsizer
Else (others => '0'); -- Second command is always aligned to addr offset 0
sig_cmd2dre_valid <= sig_realign_reg_full;
sig_push_realign_reg <= sig_psm_ld_realigner_reg; -- a clock of latency
sig_pop_realign_reg <= sig_cmd2dre_valid and
dre2mstr_cmd_ready; -- Realigner taking xfer
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REALIGNER_QUAL
--
-- Process Description:
-- Implements the output Realigner qualifier holding register
-- for the Realigner Block used with the Store and Forward
-- module.
--
-------------------------------------------------------------
REG_REALIGNER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_realign_reg = '1' and
sig_push_realign_reg = '0')) then
sig_realign_tag_reg <= (others => '0');
sig_realign_src_align_reg <= (others => '0');
sig_realign_dest_align_reg <= (others => '0');
sig_realign_btt_reg <= (others => '0');
sig_realign_drr_reg <= '0';
sig_realign_eof_reg <= '0';
sig_realign_cmd_cmplt_reg <= '0';
sig_realign_calc_err_reg <= '0';
sig_realign_strt_offset_reg <= (others => '0');
sig_realign_reg_empty <= '1';
sig_realign_reg_full <= '0';
elsif (sig_push_realign_reg = '1') then
sig_realign_tag_reg <= sig_input_tag_reg ;
sig_realign_src_align_reg <= sig_input_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0);
sig_realign_dest_align_reg <= sig_dre_dest_align ;
sig_realign_btt_reg <= sig_realigner_btt2 ;
sig_realign_drr_reg <= sig_input_drr_reg and
sig_first_realigner_cmd ;
sig_realign_eof_reg <= (sig_input_eof_reg and
sig_skip_align2mbaa and
sig_first_realigner_cmd) or
(sig_input_eof_reg and
not(sig_first_realigner_cmd));
sig_realign_cmd_cmplt_reg <= (sig_skip_align2mbaa and
sig_first_realigner_cmd) or
not(sig_first_realigner_cmd) or
sig_calc_error_reg ;
sig_realign_calc_err_reg <= sig_calc_error_reg ;
sig_realign_strt_offset_reg <= sig_realign_strt_offset;
sig_realign_reg_empty <= '0';
sig_realign_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_REALIGNER_QUAL;
----------------------------------------------------------------------
-- Parent Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-----------------------------------------------------------------
-- Child transfer command register design
sig_push_child_cmd_reg <= sig_psm_ld_chcmd_reg;
sig_pop_child_cmd_reg <= sig_csm_pop_child_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_CMD_REG
--
-- Process Description:
-- Implements the Child command holding register
-- loaded by the Parent State Machine. This is a
-- 1 deep fifo-like command queue.
-------------------------------------------------------------
CHILD_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_child_cmd_reg = '1') then
sig_child_tag_reg <= (others => '0');
sig_child_addr_reg <= (others => '0');
sig_child_burst_type_reg <= '0';
sig_child_cache_type_reg <= (others => '0');
sig_child_user_type_reg <= (others => '0');
sig_needed_2_realign_cmds <= '0';
sig_child_error_reg <= '0';
sig_child_cmd_reg_empty <= '1';
sig_child_cmd_reg_full <= '0';
elsif (sig_push_child_cmd_reg = '1') then
sig_child_tag_reg <= sig_input_tag_reg ;
sig_child_addr_reg <= sig_input_addr_reg;
sig_child_burst_type_reg <= sig_input_burst_type_reg;
sig_child_cache_type_reg <= sig_input_cache_type_reg;
sig_child_user_type_reg <= sig_input_user_type_reg;
sig_needed_2_realign_cmds <= not(sig_skip_align2mbaa_s_h);
sig_child_error_reg <= sig_calc_error_reg;
sig_child_cmd_reg_empty <= '0';
sig_child_cmd_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process CHILD_CMD_REG;
sig_ld_child_qual_reg <= sig_pop_child_cmd_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_qual_tag_reg <= (others => '0');
sig_child_qual_burst_type <= '0';
sig_child_qual_cache_type <= (others => '0');
sig_child_qual_user_type <= (others => '0');
sig_child_qual_error_reg <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_tag_reg <= sig_child_tag_reg ;
sig_child_qual_burst_type <= sig_child_burst_type_reg ;
sig_child_qual_cache_type <= sig_child_cache_type_reg ;
sig_child_qual_user_type <= sig_child_user_type_reg ;
sig_child_qual_error_reg <= sig_child_error_reg;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_QUAL_DBL_CMD_REG
--
-- Process Description:
-- Implements the child intermediate command qualifier holding
-- register.
--
-------------------------------------------------------------
CHILD_QUAL_DBL_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_csm_pop_sf_fifo = '1' and
sig_sf2pcc_cmd_cmplt = '1')) then
sig_child_qual_first_of_2 <= '0';
elsif (sig_ld_child_qual_reg = '1') then
sig_child_qual_first_of_2 <= sig_needed_2_realign_cmds;
else
null; -- Hold current State
end if;
end if;
end process CHILD_QUAL_DBL_CMD_REG;
------------------------------------------------------------------
-- Data and Address Controller Transfer Register Load Enable logic
sig_last_s_f_xfer_ld <= sig_push_xfer_reg and
sig_sf2pcc_cmd_cmplt;
-------------------------------------------------------------------------
-- SFCC Child State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CHILD_STATE_MACHINE_COMB
--
-- Process Description:
-- Implements the combinational portion of the Child Command
-- processing state machine.
--
-------------------------------------------------------------
CHILD_STATE_MACHINE_COMB : process (sig_csm_state ,
sig_child_cmd_reg_full ,
sig_sf2pcc_xfer_valid ,
sig_child_error_reg ,
sig_cmd2data_valid ,
sig_cmd2addr_valid ,
sig_child_qual_first_of_2 ,
sig_sf2pcc_cmd_cmplt ,
sig_sf2pcc_packet_eop)
begin
-- Set defaults
sig_csm_state_ns <= CH_INIT;
sig_csm_ld_xfer_ns <= '0';
sig_csm_pop_sf_fifo_ns <= '0';
sig_csm_pop_child_cmd_ns <= '0';
case sig_csm_state is
-----------------------------------------------------
when CH_INIT =>
sig_csm_state_ns <= WAIT_FOR_PCMD;
-----------------------------------------------------
when WAIT_FOR_PCMD =>
If (sig_child_error_reg = '1' and
sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_ERROR_TRAP1;
sig_csm_pop_child_cmd_ns <= '1';
elsif (sig_child_cmd_reg_full = '1') Then
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
sig_csm_pop_child_cmd_ns <= '1';
Else
sig_csm_state_ns <= WAIT_FOR_PCMD;
End if;
-----------------------------------------------------
when CH_WAIT_FOR_SF_CMD =>
If (sig_sf2pcc_xfer_valid = '1') Then
sig_csm_state_ns <= CH_LD_CHILD_CMD;
Else
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
End if;
-----------------------------------------------------
when CH_LD_CHILD_CMD =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_CHK_IF_DONE;
sig_csm_ld_xfer_ns <= '1';
sig_csm_pop_sf_fifo_ns <= '1';
Else
sig_csm_state_ns <= CH_LD_CHILD_CMD;
End if;
-----------------------------------------------------
when CH_CHK_IF_DONE =>
If (sig_sf2pcc_cmd_cmplt = '1' and
(sig_child_qual_first_of_2 = '0' or
sig_sf2pcc_packet_eop = '1')) Then -- done
sig_csm_state_ns <= WAIT_FOR_PCMD;
else -- more SF child commands coming from the parent command
sig_csm_state_ns <= CH_WAIT_FOR_SF_CMD;
end if;
-----------------------------------------------------
when CH_ERROR_TRAP1 =>
If (sig_cmd2data_valid = '0' and
sig_cmd2addr_valid = '0') Then
sig_csm_state_ns <= CH_ERROR_TRAP2;
sig_csm_ld_xfer_ns <= '1';
Else
sig_csm_state_ns <= CH_ERROR_TRAP1;
End if;
-----------------------------------------------------
when CH_ERROR_TRAP2 =>
sig_csm_state_ns <= CH_ERROR_TRAP2;
-----------------------------------------------------
when others =>
sig_csm_state_ns <= CH_INIT;
end case;
end process CHILD_STATE_MACHINE_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CHILD_SM_REGISTERED
--
-- Process Description:
-- Child State Machine registered implementation
--
-------------------------------------------------------------
CHILD_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_csm_state <= CH_INIT;
sig_csm_ld_xfer <= '0' ;
sig_csm_pop_sf_fifo <= '0' ;
sig_csm_pop_child_cmd <= '0' ;
else
sig_csm_state <= sig_csm_state_ns ;
sig_csm_ld_xfer <= sig_csm_ld_xfer_ns ;
sig_csm_pop_sf_fifo <= sig_csm_pop_sf_fifo_ns ;
sig_csm_pop_child_cmd <= sig_csm_pop_child_cmd_ns ;
end if;
end if;
end process CHILD_SM_REGISTERED;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_child_addr_cntr <= sig_ld_child_qual_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_child_addr_cntr <= sig_push_xfer_reg and
sig_child_qual_burst_type;
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice <= sig_child_addr_cntr_lsh(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH) +
RESIZE(sig_start_addr_offset_slice, ADDR_CNTR_WIDTH);
-- Select the address counter increment value to use
sig_child_addr_cntr_incr <= RESIZE(UNSIGNED(sig_sf2pcc_xfer_bytes), ADDR_CNTR_WIDTH); -- bytes received value plus the addr
-- offset.
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1 <= sig_adjusted_addr_incr-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_child_addr_lsh <= sig_child_addr_cntr_lsh + sig_child_addr_cntr_incr;
sig_predict_child_addr_lsh_slv <= STD_LOGIC_VECTOR(sig_predict_child_addr_lsh);
sig_child_addr_cntr_lsh_slv <= STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_child_addr_lsh_rollover <= '1'
when (
(sig_child_addr_cntr_lsh_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_child_addr_lsh_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
-- sig_child_addr_msh_eq_max <= '1'
-- when (sig_child_addr_cntr_msh = ADDR_CNTR_MAX_VALUE)
-- Else '0';
-- sig_child_addr_msh_rollover <= sig_child_addr_msh_eq_max and
-- sig_child_addr_lsh_rollover;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_lsh_rollover_reg <= '0';
--sig_child_addr_msh_rollover_reg <= '0';
--sig_child_addr_msh_eq_max_reg <= '0';
--sig_adjusted_child_addr_incr_reg <= (others => '0');
else
sig_child_addr_lsh_rollover_reg <= sig_child_addr_lsh_rollover ;
--sig_child_addr_msh_rollover_reg <= sig_child_addr_msh_rollover ;
--sig_child_addr_msh_eq_max_reg <= sig_child_addr_msh_eq_max ;
--sig_adjusted_child_addr_incr_reg <= sig_adjusted_addr_incr;
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_lsh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_lsh <= UNSIGNED(sig_child_addr_reg(ADDR_CNTR_WIDTH-1 downto 0));
Elsif (sig_incr_child_addr_cntr = '1') Then
sig_child_addr_cntr_lsh <= sig_predict_child_addr_lsh;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_child_addr_cntr_msh <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
sig_child_addr_cntr_msh <= UNSIGNED(sig_child_addr_reg((2*ADDR_CNTR_WIDTH)-1 downto
ADDR_CNTR_WIDTH));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover_reg = '1') Then
sig_child_addr_cntr_msh <= sig_child_addr_cntr_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_child_addr_cntr = '1') then
sig_first_child_xfer <= '0';
elsif (sig_ld_child_addr_cntr = '1') then
sig_first_child_xfer <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_msh) &
STD_LOGIC_VECTOR(sig_child_addr_cntr_lsh);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_child_addr_cntr_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_child_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_child_addr_reg(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_child_addr_cntr = '1' and
sig_child_addr_lsh_rollover = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Child Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
------------------------------------------------------------------
-- Sequential transfer flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEQ_FLAG
--
-- Process Description:
-- Sequential transfer flag flop
-- The sequential flag is an indication to downstream modules
-- (such as Data Controllers) that the following command in the
-- transfer queue is address sequential to the current transfer.
-- This is used to minimize/eliminate transfer bubbles between
-- child transfer boundaries.
--
-------------------------------------------------------------
IMP_SEQ_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_xfer_is_seq <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_is_seq <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_SEQ_FLAG;
-----------------------------------------------------------------
-- Output xfer register design
-- Pop the Store and Forward Xfer FIFO under command of the
-- Child State Machine
sig_pcc2sf_xfer_ready <= sig_csm_pop_sf_fifo;
sig_push_xfer_reg <= sig_csm_ld_xfer;
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid)) or -- Data taking xfer after Addr
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid)) or -- Addr taking xfer after Data
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid); -- Addr and Data both taking xfer
-- SFCC Simplifications
-- sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt;
sig_last_xfer_valid <= sig_sf2pcc_cmd_cmplt and -- from Store and forward
(not(sig_child_qual_first_of_2) or
sig_sf2pcc_packet_eop );
-- DRE Stuff is sent via the Realigner command,
sig_xfer_drr_reg <= '0'; -- not used here
-- ---------------------------------------------------------------------
-- Strobe Generator Logic
-- Actual Strobes used are sent directly to the Data Controller from
-- Store and Forward module. Set these Strobe values to all ones in
-- this module.
sig_xfer_strt_strb_reg <= (others => '1');
sig_xfer_end_strb_reg <= (others => '1');
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CHILD_XFER_QUAL
--
-- Process Description:
-- Implements the child command output xfer qualifier
-- holding register.
--
-------------------------------------------------------------
REG_CHILD_XFER_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
sig_xfer_cache_reg <= (others => '0');
sig_xfer_user_reg <= (others => '0');
sig_xfer_tag_reg <= (others => '0');
sig_xfer_addr_reg <= (others => '0');
sig_xfer_len_reg <= (others => '0');
sig_xfer_eof_reg <= '0';
sig_xfer_is_seq_reg <= '0';
sig_xfer_cmd_cmplt_reg <= '0';
sig_xfer_calc_err_reg <= '0';
sig_xfer_type_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
sig_xfer_cache_reg <= sig_child_qual_cache_type ;
sig_xfer_user_reg <= sig_child_qual_user_type ;
sig_xfer_tag_reg <= sig_child_qual_tag_reg ;
sig_xfer_addr_reg <= sig_xfer_address ;
sig_xfer_len_reg <= sig_xfer_len ;
sig_xfer_eof_reg <= sf2pcc_packet_eop ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid or
sig_child_qual_error_reg ;
sig_xfer_calc_err_reg <= sig_child_qual_error_reg ;
sig_xfer_type_reg <= sig_child_qual_burst_type ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_CHILD_XFER_QUAL;
end implementation;
| mit |
UVVM/UVVM_All | bitvis_vip_rgmii/src/vvc_context.vhd | 1 | 1804 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_rgmii;
use bitvis_vip_rgmii.transaction_pkg.all;
use bitvis_vip_rgmii.vvc_methods_pkg.all;
use bitvis_vip_rgmii.td_vvc_framework_common_methods_pkg.all;
use bitvis_vip_rgmii.rgmii_bfm_pkg.t_rgmii_tx_if;
use bitvis_vip_rgmii.rgmii_bfm_pkg.t_rgmii_rx_if;
use bitvis_vip_rgmii.rgmii_bfm_pkg.t_rgmii_bfm_config;
use bitvis_vip_rgmii.rgmii_bfm_pkg.C_RGMII_BFM_CONFIG_DEFAULT;
end context;
| mit |
UVVM/UVVM_All | bitvis_vip_sbi/src/transaction_pkg.vhd | 1 | 5988 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- Transaction
WRITE, READ, CHECK, POLL_UNTIL);
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--==========================================================================================
--
-- Transaction Info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction type
type t_base_transaction is record
operation : t_operation;
address : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
address => (others => '0'),
data => (others => '0'),
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Compound transaction type
type t_compound_transaction is record
operation : t_operation;
address : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
randomisation : t_randomisation;
num_words : natural;
max_polls : integer;
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_COMPOUND_TRANSACTION_SET_DEFAULT : t_compound_transaction := (
operation => NO_OPERATION,
address => (others => '0'),
data => (others => '0'),
randomisation => NA,
num_words => 1,
max_polls => 1,
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
ct : t_compound_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT,
ct => C_COMPOUND_TRANSACTION_SET_DEFAULT
);
-- Global transaction info trigger signal
type t_sbi_transaction_trigger_array is array (natural range <>) of std_logic;
signal global_sbi_vvc_transaction_trigger : t_sbi_transaction_trigger_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => '0');
-- Type is defined as array to coincide with channel based VVCs
type t_sbi_transaction_group_array is array (natural range <>) of t_transaction_group;
-- Shared transaction info variable
shared variable shared_sbi_vvc_transaction_info : t_sbi_transaction_group_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => C_TRANSACTION_GROUP_DEFAULT);
end package transaction_pkg; | mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_fifo.vhd | 4 | 24358 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_sfifo_autord;
use axi_sg_v4_1.axi_sg_afifo_autord;
-------------------------------------------------------------------------------
entity axi_sg_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
-- coverage off
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- coverage on
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_sg_v4_1.axi_sg_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/hdl/ip/HLS_accel_ap_fptrunc_0_no_dsp_64.vhd | 2 | 12395 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY HLS_accel_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END HLS_accel_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE HLS_accel_ap_fptrunc_0_no_dsp_64_arch OF HLS_accel_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "HLS_accel_ap_fptrunc_0_no_dsp_64,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "HLS_accel_ap_fptrunc_0_no_dsp_64,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END HLS_accel_ap_fptrunc_0_no_dsp_64_arch;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_cmd_split.vhd | 2 | 22474 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((2*C_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31 downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103 downto 96) & command (71 downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149 downto 118);
vsize_data <= s_axis_cmd_tdata (117 downto 95);
vsize_data_int <= s_axis_cmd_tdata (117 downto 95) - '1';
stride_data <= s_axis_cmd_tdata (94 downto 72);
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63 downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
| mit |
UVVM/UVVM_All | uvvm_vvc_framework/src_target_dependent/td_vvc_framework_common_methods_pkg.vhd | 1 | 63648 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- Note: This package will be compiled into every single VVC library.
-- As the type t_vvc_target_record is already compiled into every single VVC library,
-- the type definition will be unique for every library, and thus result in a unique
-- procedure signature for every VVC. Hence the shared variable shared_vvc_cmd will
-- refer to only the shared variable defined in the given library.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all; -- shared_vvc_response, t_vvc_result
use work.td_target_support_pkg.all;
package td_vvc_framework_common_methods_pkg is
--======================================================================
-- Common Methods
--======================================================================
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- await_any_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Waits for the first of multiple VVCs to finish :
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- Overload with wanted_idx
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Disables the specified msg_id for the VVC
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- See description above
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Enables the specified msg_id for the VVC
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- See description above
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Flushes the command queue of the specified VVC
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- See description above
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- fetch_result
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Fetches result from a VVC
-- - Requires that result is available (i.e. already executed in respective VVC)
-- - Logs with ID ID_UVVM_CMD_RESULT
-- The 'result' parameter is of type t_vvc_result to
-- support that the BFM returns something other than a std_logic_vector.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- -- - This version does not use vvc_channel.
-- -- - Fetches result from a VVC
-- -- - Requires that result is available (i.e. already executed in respective VVC)
-- -- - Logs with ID ID_UVVM_CMD_RESULT
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for 'delay' clock cycles
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for a given time
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- terminate_current_command
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- Overload without VVC channel
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-------------------------------------------
-- terminate_all_commands
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor, and
-- flushes the command queue
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- Overload without VVC channel
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
);
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) return natural;
end package td_vvc_framework_common_methods_pkg;
package body td_vvc_framework_common_methods_pkg is
--=========================================================================================
-- Methods
--=========================================================================================
-- NOTE: ALL VVCs using this td_vvc_framework_common_methods_pkg package MUST have the following declared in their local transaction_pkg.
-- - The enumerated t_operation (e.g. AWAIT_COMPLETION, ENABLE_LOG_MSG, etc.)
-- Any VVC based on an older version of td_vvc_framework_common_methods_pkg must - if new operators have been introduced in td_vvc_framework_common_methods_pkg either
-- a) include the new operator(s) in its t_operation, or
-- b) change the use-reference to an older common_methods package.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
await_completion(vvc_target, vvc_instance_idx, vvc_channel, -1, timeout, msg, scope, parent_msg_id_panel);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, -1, timeout, msg, scope, parent_msg_id_panel);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
constant proc_call_short : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
variable v_vvc_logged : std_logic_vector(0 to C_MAX_TB_VVC_NUM-1) := (others => '0');
variable v_vvcs_completed : natural := 0;
variable v_local_cmd_idx : integer;
variable v_timestamp : time;
variable v_done : boolean := false;
variable v_first_wait : boolean := true;
variable v_proc_call : line;
variable v_vvc_idx_in_activity_register : t_integer_array(0 to C_MAX_TB_VVC_NUM) := (others => -1);
variable v_num_vvc_instances : natural range 0 to C_MAX_TB_VVC_NUM := 0;
variable v_vvc_instance_idx : integer := vvc_instance_idx;
variable v_vvc_channel : t_channel := vvc_channel;
begin
-- Wait for a few delta cycles to account for any potential extra delays in new or user VVCs.
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
-- Only log wanted_idx when it's given as a parameter
if wanted_idx = -1 then
v_proc_call := new string'(proc_call_short);
else
v_proc_call := new string'(proc_call);
end if;
-- Use the correct msg_id_panel when called from an HVVC
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
-- Get the corresponding index from the vvc activity register
if v_vvc_instance_idx = -1 then
v_vvc_instance_idx := ALL_INSTANCES;
end if;
if v_vvc_channel = NA then
v_vvc_channel := ALL_CHANNELS;
end if;
get_vvc_index_in_activity_register(vvc_target,
vvc_instance_idx,
vvc_channel,
v_vvc_idx_in_activity_register,
v_num_vvc_instances);
-- If the VVC is registered use the new mechanism
if v_num_vvc_instances > 0 then
-- Checking if await selected (with a specified wanted_idx) is supported by this VVC
if wanted_idx /= -1 and not shared_vvc_activity_register.priv_get_vvc_await_selected_supported(v_vvc_idx_in_activity_register(0)) then
alert(TB_ERROR, v_proc_call.all & " await_completion with a specified wanted_idx is not supported by " &
shared_vvc_activity_register.priv_get_vvc_name(v_vvc_idx_in_activity_register(0)) & ". " &
add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope);
end if;
-- Increment shared_cmd_idx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
-- Store it in a local variable since new commands might be executed from another sequencer.
await_semaphore_in_delta_cycles(protected_semaphore);
shared_cmd_idx := shared_cmd_idx + 1;
v_local_cmd_idx := shared_cmd_idx;
release_semaphore(protected_semaphore);
log(ID_AWAIT_COMPLETION, v_proc_call.all & ": " & add_msg_delimiter(msg) & "." & format_command_idx(v_local_cmd_idx), scope, v_msg_id_panel);
v_timestamp := now;
while not(v_done) loop
for i in 0 to v_num_vvc_instances-1 loop
-- Wait for all of the VVC's instances and channels to complete (INACTIVE status)
if wanted_idx = -1 then
if shared_vvc_activity_register.priv_get_vvc_activity(v_vvc_idx_in_activity_register(i)) = INACTIVE then
if not(v_vvc_logged(i)) then
log(ID_AWAIT_COMPLETION_END, v_proc_call.all & "=> " & shared_vvc_activity_register.priv_get_vvc_info(v_vvc_idx_in_activity_register(i)) &
" finished. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, v_msg_id_panel);
v_vvc_logged(i) := '1';
v_vvcs_completed := v_vvcs_completed + 1;
end if;
if v_vvcs_completed = v_num_vvc_instances then
v_done := true;
end if;
end if;
-- Wait for all of the VVC's instances and channels to complete (cmd_idx completed)
else
if shared_vvc_activity_register.priv_get_vvc_last_cmd_idx_executed(v_vvc_idx_in_activity_register(i)) >= wanted_idx then
if not(v_vvc_logged(i)) then
log(ID_AWAIT_COMPLETION_END, v_proc_call.all & "=> " & shared_vvc_activity_register.priv_get_vvc_info(v_vvc_idx_in_activity_register(i)) &
" finished. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, v_msg_id_panel);
v_vvc_logged(i) := '1';
v_vvcs_completed := v_vvcs_completed + 1;
end if;
if v_vvcs_completed = v_num_vvc_instances then
v_done := true;
end if;
end if;
end if;
end loop;
if not(v_done) then
if v_first_wait then
log(ID_AWAIT_COMPLETION_WAIT, v_proc_call.all & " - Pending completion. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, v_msg_id_panel);
v_first_wait := false;
end if;
-- Wait for vvc activity trigger pulse
wait on global_trigger_vvc_activity_register for timeout;
-- Check if there was a timeout
if now >= v_timestamp + timeout then
alert(TB_ERROR, v_proc_call.all & "=> Timeout. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope);
v_done := true;
end if;
end if;
end loop;
-- If the VVC is not registered use the old mechanism
else
log(ID_OLD_AWAIT_COMPLETION, vvc_target.vvc_name & " is not supporting the VVC activity register, using old await_completion() method.", scope, v_msg_id_panel);
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, v_proc_call.all, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.timeout := timeout;
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
send_command_to_vvc(vvc_target, timeout, scope, v_msg_id_panel);
end if;
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, timeout, msg, scope, parent_msg_id_panel);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0; -- Useful when being called by multiple sequencers
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, vvc_channel, -1, lastness, timeout, msg, awaiting_completion_idx, scope, parent_msg_id_panel);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, -1, lastness, timeout, msg, awaiting_completion_idx, scope, parent_msg_id_panel);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0; -- Useful when being called by multiple sequencers
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
constant proc_call_short : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
variable v_proc_call : line;
begin
-- Only log wanted_idx when it's given as a parameter
if wanted_idx = -1 then
v_proc_call := new string'(proc_call_short);
else
v_proc_call := new string'(proc_call);
end if;
log(ID_OLD_AWAIT_COMPLETION, "Procedure is not supporting the VVC activity register, using old await_any_completion() method.", scope, shared_msg_id_panel);
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, v_proc_call.all, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
if lastness = LAST then
-- LAST
shared_vvc_cmd.gen_boolean := true;
else
-- NOT_LAST : Timeout must be handled in interpreter_await_any_completion
-- becuase the command is always acknowledged immediately by the VVC to allow the sequencer to continue
shared_vvc_cmd.gen_boolean := false;
end if;
send_command_to_vvc(vvc_target, timeout, scope, v_msg_id_panel);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0; -- Useful when being called by multiple sequencers
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, lastness, timeout, msg, awaiting_completion_idx, scope, parent_msg_id_panel);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, DISABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(vvc_target, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
disable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness, scope, parent_msg_id_panel);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, ENABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(vvc_target, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
enable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness, scope, parent_msg_id_panel);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FLUSH_COMMAND_QUEUE);
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(vvc_target, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, NA, msg, scope, parent_msg_id_panel);
end procedure;
-- Requires that result is available (i.e. already executed in respective VVC)
-- The four next procedures are overloads for when 'result' is of type work.vvc_cmd_pkg.t_vvc_result
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
await_semaphore_in_delta_cycles(protected_response_semaphore);
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FETCH_RESULT);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(vvc_target, std.env.resolution_limit, scope, v_msg_id_panel);
-- Post process
result := shared_vvc_response.result;
fetch_is_accepted := shared_vvc_response.fetch_is_accepted;
if caller_name = "base_procedure" then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(shared_vvc_response.fetch_is_accepted) & ", Result=>" & to_string(result) & format_command_idx(shared_cmd_idx), scope, v_msg_id_panel); -- Get and ack the new command
end if;
release_semaphore(protected_response_semaphore);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
variable v_fetch_is_accepted : boolean;
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
fetch_result(vvc_target, vvc_instance_idx, vvc_channel, wanted_idx, result, v_fetch_is_accepted, msg, alert_level, proc_name & "_with_check_of_ok", scope, parent_msg_id_panel);
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
if v_fetch_is_accepted then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(v_fetch_is_accepted) & ", Result=>" & to_string(result) & format_command_idx(shared_cmd_idx), scope, v_msg_id_panel); -- Get and ack the new command
else
alert(alert_level, "fetch_result(" & to_string(wanted_idx) & "): " & add_msg_delimiter(msg) & "." &
" Failed. Trying to fetch result from not yet executed command or from command with no result stored. " & format_command_idx(shared_cmd_idx), scope);
end if;
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, fetch_is_accepted, msg, alert_level, "base_procedure", scope, parent_msg_id_panel);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, msg, alert_level, scope, parent_msg_id_panel);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.gen_integer_array(0) := delay;
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(vvc_target, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg, scope, parent_msg_id_panel);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.delay := delay;
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(vvc_target, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg, scope, parent_msg_id_panel);
end procedure;
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, TERMINATE_CURRENT_COMMAND);
--shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; --UVVM: temporary fix for HVVC, uncomment in v3.0
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(vvc_target, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Overload without VVC channel
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant vvc_channel : t_channel := NA;
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx) -- First part common for all
& ")";
begin
terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg, scope, parent_msg_id_panel);
end procedure;
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, vvc_channel, msg, scope, parent_msg_id_panel);
terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg, scope, parent_msg_id_panel);
end procedure;
-- Overload without VVC channel
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: temporary fix for HVVC, replace for C_UNUSED_MSG_ID_PANEL in v3.0
) is
constant vvc_channel : t_channel := NA;
begin
terminate_all_commands(vvc_target, vvc_instance_idx, vvc_channel, msg, scope, parent_msg_id_panel);
end procedure;
---- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) return natural is
variable v_cmd_idx : integer := -1;
begin
v_cmd_idx := shared_vvc_last_received_cmd_idx(vvc_channel, vvc_instance_idx);
check_value(v_cmd_idx /= -1, tb_error, "Channel " & to_string(vvc_channel) & " not supported on VVC " & vvc_target.vvc_name, scope, ID_NEVER);
if v_cmd_idx /= -1 then
return v_cmd_idx;
else
-- return 0 in case of failure
return 0;
end if;
end function;
end package body td_vvc_framework_common_methods_pkg;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_addr_cntl.vhd | 5 | 41873 | ----------------------------------------------------------------------------
-- axi_sg_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_sg Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1;
Use axi_sg_v4_1.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_sg_addr_cntl;
architecture implementation of axi_sg_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
-- GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
--
-- begin
--
-- -- Format the input FIFO data word
--
-- sig_aq_fifo_data_in <= mstr2addr_cache &
-- mstr2addr_user &
-- mstr2addr_calc_error &
-- mstr2addr_cmd_cmplt &
-- mstr2addr_burst &
-- mstr2addr_size &
-- mstr2addr_len &
-- mstr2addr_addr &
-- mstr2addr_tag ;
--
--
--
-- -- Rip fields from FIFO output data word
-- sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 7)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 4)
-- );
--
-- sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 3)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)
-- );
--
--
-- sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)-1);
--
--
-- sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH)-1);
--
--
-- sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH) ;
--
-- sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH) ;
--
-- sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH)-1
-- downto
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_ADDR_QUAL_FIFO
-- --
-- -- Description:
-- -- Instance for the Address/Qualifier FIFO
-- --
-- ------------------------------------------------------------
-- I_ADDR_QUAL_FIFO : entity axi_sg_v4_1.axi_sg_fifo
-- generic map (
--
-- C_DWIDTH => ADDR_QUAL_WIDTH ,
-- C_DEPTH => C_ADDR_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => mmap_reset ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
-- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
-- fifo_wr_tdata => sig_aq_fifo_data_in ,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
-- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
-- fifo_rd_tdata => sig_aq_fifo_data_out ,
-- fifo_rd_empty => sig_cmd_fifo_empty
--
-- );
--
--
--
-- end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd | 6 | 88906 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the width of the alignment control inputs
-- Should be log2(C_DWIDTH)
);
port (
-- Clock and Reset Input ----------------------------------------------
--
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------------------------------------
-- Alignment Control (Independent from Stream Input timing) ----------
--
dre_align_ready : Out std_logic; --
dre_align_valid : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Flush Control (Aligned to input Stream timing) --------------------
--
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Stream Input Channel ----------------------------------------------
--
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Stream Output Channel ---------------------------------------------
--
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_s2mm_dre;
architecture implementation of axi_datamover_s2mm_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
Signal sig_cntl_accept : std_logic := '0';
Signal sig_dre_halted : std_logic := '0';
begin --(architecture implementation)
-- Misc port assignments
dre_align_ready <= sig_dre_halted or
sig_flush_db2_complete ;
dre_in_tready <= sig_input_accept ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
-- Internal logic
sig_cntl_accept <= dre_align_valid and
(sig_dre_halted or
sig_flush_db2_complete);
sig_pipeline_halt <= sig_dre_halted or
(sig_dre_tvalid_i and
not(dre_out_tready));
sig_output_xfer <= sig_dre_tvalid_i and
dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt);
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
not(sig_pipeline_halt) and
not(sig_input_flush_stall);
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or
sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
------------------------------------------------------------------------------------
-- DRE Halted logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_HALTED_FLOP
--
-- Process Description:
-- Implements a flop for the Halted state flag. All DRE
-- operation is halted until a new alignment control is
-- loaded. The DRE automatically goes into halted state
-- at reset and at completion of a flush operation.
--
-------------------------------------------------------------
IMP_DRE_HALTED_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
(sig_flush_db2_complete = '1' and
dre_align_valid = '0'))then
sig_dre_halted <= '1'; -- default to halted state
elsif (sig_cntl_accept = '1') then
sig_dre_halted <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_DRE_HALTED_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Input Register for the flush command
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
Signal s_case_i_64 : Integer range 0 to 7 := 0;
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
Signal s_case_i_32 : Integer range 0 to 3 := 0;
signal sig_cntl_state_32 : std_logic_vector(3 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(3 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
Signal s_case_i_16 : Integer range 0 to 1 := 0;
signal sig_cntl_state_16 : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic := '0';
Signal sig_shift_case_reg : std_logic := '0';
Signal sig_final_mux_sel : std_logic_vector(1 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| mit |
UVVM/UVVM_All | bitvis_vip_uart/src/uart_bfm_pkg.vhd | 1 | 28282 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: This BFM is only intended as a simplified UART BFM to be used as a test
-- vehicle for presenting UVVM functionality.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library std;
use std.textio.all;
--=================================================================================================
package uart_bfm_pkg is
--===============================================================================================
-- Types and constants for UART BFMs
--===============================================================================================
constant C_SCOPE : string := "UART BFM";
constant C_DATA_MAX_LENGTH : natural := 8;
constant C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR : string := "; ";
type uart_expect_received_data_array is array (natural range<>) of std_logic_vector(C_DATA_MAX_LENGTH-1 downto 0);
type t_bfm_error_injection is record
parity_bit_error : boolean;
stop_bit_error : boolean;
end record t_bfm_error_injection;
constant C_BFM_ERROR_INJECTION_INACTIVE : t_bfm_error_injection := (
parity_bit_error => false,
stop_bit_error => false
);
type t_uart_bfm_config is record
bit_time : time; -- The time it takes to transfer one bit
num_data_bits : natural range 7 to 8; -- Number of data bits to send per transmission
idle_state : std_logic; -- Bit value when line is idle
num_stop_bits : t_stop_bits; -- Number of stop-bits to use per transmission {STOP_BITS_ONE, STOP_BITS_ONE_AND_HALF, STOP_BITS_TWO}
parity : t_parity; -- Transmission parity bit {PARITY_NONE, PARITY_ODD, PARITY_EVEN}
timeout : time; -- The maximum time to pass before the expected data must be received. Exceeding this limit results in an alert with severity ‘alert_level’.
timeout_severity : t_alert_level; -- The above timeout will have this severity
num_bytes_to_log_before_expected_data : natural; -- Maximum number of bytes to save ahead of the expected data in the receive buffer. The bytes in the receive buffer will be logged.
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the UART BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the UART BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the UART BFM
id_for_bfm_poll_summary : t_msg_id; -- The message ID used for logging polling summary in the UART BFM
error_injection : t_bfm_error_injection;
end record;
constant C_UART_BFM_CONFIG_DEFAULT : t_uart_bfm_config := (
bit_time => -1 ns,
num_data_bits => 8,
idle_state => '1',
num_stop_bits => STOP_BITS_ONE,
parity => PARITY_ODD,
timeout => 0 ns, -- will default never time out
timeout_severity => error,
num_bytes_to_log_before_expected_data => 10,
match_strictness => MATCH_EXACT,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL,
id_for_bfm_poll_summary => ID_BFM_POLL_SUMMARY,
error_injection => C_BFM_ERROR_INJECTION_INACTIVE
);
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
------------------------------------------
-- uart_transmit
------------------------------------------
-- - This procedure transmits data 'data_value' to the UART DUT
-- - The TX configuration can be set in the config parameter
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- uart_receive
------------------------------------------
-- - This procedure reads data from the UART DUT and returns it in 'data_value'
-- - The RX configuration can be set in the config parameter
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- uart_expect
------------------------------------------
-- - This procedure reads data from the UART DUT and compares it to the data in
-- 'data_exp'.
-- - If the read data is inconsistent with the 'data_exp' data, a new read will
-- be performed, and the new read data will be compared with 'data_exp'.
-- This process will continue untill one of the following conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_receptions'
-- c) The time spent reading is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_receptions' is set to 0, it will be interpreted as no limitation on number of reads
-- - The RX configuration can be set in the config parameter
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- odd_parity
------------------------------------------
-- - This function checks if the data parity is odd or even
-- - If the number of '1' in the 'data' input is odd, '1' will be returned
-- - If the number of '1' in the 'data' input is even, '0' will be returned
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic;
end package uart_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body uart_bfm_pkg is
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic is
begin
return xnor(data);
end odd_parity;
---------------------------------------------------------------------------------
-- uart_transmit
---------------------------------------------------------------------------------
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_transmit";
constant proc_call : string := proc_name & "(" & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
alias stop_bit_error is config.error_injection.stop_bit_error;
alias parity_bit_error is config.error_injection.parity_bit_error;
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- check if tx line was idle when trying to transmit data
check_value(tx, config.idle_state, FAILURE, proc_call & " Bus was active when trying to send data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
tx <= not config.idle_state;
wait for config.bit_time;
for j in data_value'low to data_value'high loop
tx <= data_value(j);
wait for config.bit_time;
end loop;
-- Set parity bit
if (config.parity = PARITY_ODD) then
tx <= odd_parity(data_value);
elsif(config.parity = PARITY_EVEN) then
tx <= not(odd_parity(data_value));
end if;
-- Invert parity bit if error injection is requested
if parity_bit_error = true then
if (config.parity = PARITY_ODD) then
tx <= not(odd_parity(data_value));
elsif(config.parity = PARITY_EVEN) then
tx <= odd_parity(data_value);
end if;
end if;
if (config.parity /= PARITY_NONE) then
wait for config.bit_time;
end if;
-- Set stop bits
if stop_bit_error = false then
tx <= config.idle_state;
else
-- Invert stop bit if error injection is requested
tx <= not(config.idle_state);
--Will return to idle/normal stop bit after 1 bit time
tx <= transport config.idle_state after config.bit_time;
end if;
wait for config.bit_time;
if (config.num_stop_bits = STOP_BITS_ONE_AND_HALF) then
wait for config.bit_time/2;
elsif(config.num_stop_bits = STOP_BITS_TWO) then
wait for config.bit_time;
end if;
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
---------------------------------------------------------------------------------
-- uart_receive
---------------------------------------------------------------------------------
-- Perform a receive operation
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant start_time : time := now;
-- local_proc_* used if uart_receive is called directly from sequencer or VVC
constant local_proc_name : string := "uart_receive";
constant local_proc_call : string := local_proc_name & "()";
-- Helper variables
variable v_transfer_time : time;
variable v_proc_call : line; -- Current proc_call, external or internal
variable v_remaining_time : time; -- temp variable to calculate the remaining time before timeout
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_terminated : boolean := false;
variable v_timeout : boolean := false;
begin
-- check whether config.bit_time was set properly
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
data_value := (data_value'range => 'X');
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- If timeout enabled, check that timeout is longer than transfer time
if config.timeout /= 0 ns then
v_transfer_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_transfer_time := v_transfer_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
check_value(v_transfer_time < config.timeout, TB_ERROR, "Length of timeout is shorter than or equal length of transfer time.", C_SCOPE, ID_NEVER, msg_id_panel);
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'uart_receive...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing uart_receive...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name & ". ");
end if;
-- check if bus is in idle state
check_value(rx, config.idle_state, FAILURE, v_proc_call.all & "Bus was active when trying to receive data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait until the start bit is sent on the bus, configured timeout occures or procedure get terminate signal
if config.timeout = 0 ns then
wait until (rx = not config.idle_state) or (terminate_loop = '1');
else
wait until (rx = not config.idle_state) or (terminate_loop = '1') for config.timeout;
end if;
if terminate_loop = '1' then
if ext_proc_call = "" then
log(ID_TERMINATE_CMD, v_proc_call.all & "=> terminated." & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- termination handled in calling procedure
end if;
v_terminated := true;
end if;
-- if configured timeout, check if there is enough time remaining to receive the byte
if config.timeout /= 0 ns and not v_terminated then
v_remaining_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_remaining_time := v_remaining_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if now + v_remaining_time > start_time + config.timeout then
-- wait until timeout
wait for ((start_time + config.timeout) - now);
if ext_proc_call = "" then
alert(config.timeout_severity, v_proc_call.all & "=> timeout. " & add_msg_delimiter(msg),scope);
else
-- timeout handled in upper module
end if;
v_timeout := true;
end if;
end if;
if not v_terminated and not v_timeout then
-- enter the middle of the bit period
wait for config.bit_time/2;
check_value(rx , not config.idle_state, FAILURE, v_proc_call.all & " Start bit was not stable during receiving. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait for data bit
wait for config.bit_time;
-- sample the data bits
for i in 0 to config.num_data_bits-1 loop
v_data_value(i) := rx;
-- wait for middle of the next bit
wait for config.bit_time;
end loop;
-- check parity, if enabled
if config.parity = PARITY_ODD then
if rx /= odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
elsif config.parity = PARITY_EVEN then
if rx /= not odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
end if;
-- check the stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect stop bit received. " & add_msg_delimiter(msg),scope);
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
wait for config.bit_time/2 + config.bit_time/4; -- middle of the last half. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second half stop bit received. " & add_msg_delimiter(msg),scope);
end if;
elsif config.num_stop_bits = STOP_BITS_TWO then
wait for config.bit_time; -- middle of the last bit. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second stop bit received. " & add_msg_delimiter(msg),scope);
end if;
end if;
-- return the received data
data_value := v_data_value;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. uart_expect)
end if;
end if;
DEALLOCATE(v_proc_call);
end procedure;
----------------------------------------------------------------------------------------
-- uart_expect
----------------------------------------------------------------------------------------
-- Perform a receive operation, then compare the received value to the expected value.
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1; -- 0 = any occurrence before timeout
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_expect";
constant proc_call : string := proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
constant start_time : time := now;
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_num_of_occurrences : natural := 0;
variable v_check_ok : boolean;
variable v_num_of_occurrences_ok : boolean;
variable v_timeout_ok : boolean;
variable v_config : t_uart_bfm_config := config;
variable v_received_data_fifo : uart_expect_received_data_array(0 to v_config.num_bytes_to_log_before_expected_data-1) := (others => (others =>'0'));
variable v_received_data_fifo_write_idx : natural := 0;
variable v_received_output_line : line;
variable v_internal_timeout : time;
variable v_alert_radix : t_radix;
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- if timeout = -1 function was called without parameter
if timeout = -1 ns then
v_internal_timeout := config.timeout;
else
v_internal_timeout := timeout;
end if;
assert (v_internal_timeout >= 0 ns) report "configured negative timeout(not allowed). " & add_msg_delimiter(msg) severity failure;
-- Check for v_internal_timeout = 0 and max_receptions = 0. This combination can result in an infinite loop.
if v_internal_timeout = 0 ns and max_receptions = 0 then
alert(ERROR, proc_name & " called with timeout=0 and max_receptions = 0. This combination can result in an infinite loop. " & add_msg_delimiter(msg),scope);
end if;
if v_internal_timeout = 0 ns then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences. " & msg, scope, msg_id_panel);
elsif max_receptions = 0 then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
else
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences and " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
end if;
-- Initial status of check variables
v_check_ok := false;
v_timeout_ok := true;
if max_receptions < 1 then
v_num_of_occurrences_ok := true;
else
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Setup of v_config with correct timeout
v_config.timeout := v_internal_timeout;
-- Check operation
while not v_check_ok and v_timeout_ok and v_num_of_occurrences_ok and (terminate_loop = '0') loop
-- Receive and check data
uart_receive(v_data_value, msg, rx, terminate_loop, v_config, scope, msg_id_panel, proc_call);
for i in 0 to v_config.num_data_bits-1 loop
-- Allow don't care in expected value and use match strictness from config for comparison
if data_exp(i) = '-' or check_value(v_data_value(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
-- Place the received data in the received data buffer for debugging
-- If the FIFO is not full, fill it up
if v_received_data_fifo_write_idx < v_config.num_bytes_to_log_before_expected_data then
v_received_data_fifo(v_received_data_fifo_write_idx)(v_data_value'length-1 downto 0) := v_data_value;
v_received_data_fifo_write_idx := v_received_data_fifo_write_idx + 1;
else
-- If the FIFO is full, left shift all input and append new data
for i in 1 to v_config.num_bytes_to_log_before_expected_data-1 loop
v_received_data_fifo(i-1) := v_received_data_fifo(i);
end loop;
v_received_data_fifo(v_received_data_fifo_write_idx-1)(v_data_value'length-1 downto 0) := v_data_value;
end if;
-- Evaluate number of occurrences, if limited by user
if max_receptions > 0 then
v_num_of_occurrences := v_num_of_occurrences + 1;
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Evaluate timeout if specified by user
if v_internal_timeout = 0 ns then
v_timeout_ok := true;
else
v_timeout_ok := now < start_time + v_internal_timeout;
end if;
end loop;
-- Concatenate the string FIFO into a single string with given separators
for i in 0 to v_received_data_fifo_write_idx-1 loop
write(v_received_output_line, to_string(v_received_data_fifo(i), HEX, SKIP_LEADING_0, INCL_RADIX));
if i /= v_received_data_fifo_write_idx-1 then
write(v_received_output_line, C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR);
end if;
end loop;
if max_receptions > 1 then
-- Print the received string of bytes
log(v_config.id_for_bfm_poll_summary, "Last "& to_string(v_received_data_fifo_write_idx) & " received data bytes while waiting for expected data: " & v_received_output_line.all, scope, msg_id_panel);
end if;
if v_check_ok then
log(v_config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & " after " & to_string(v_num_of_occurrences) & " occurrences and " & to_string((now - start_time),ns) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
elsif not v_timeout_ok then
alert(config.timeout_severity, proc_call & "=> Failed due to timeout. Did not get expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " before time " & to_string(v_internal_timeout,ns) & ". " & add_msg_delimiter(msg), scope);
elsif not v_num_of_occurrences_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_data_value, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
if max_receptions = 1 then
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences, received value " & to_string(v_data_value, v_alert_radix, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope);
else
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences. " & add_msg_delimiter(msg), scope);
end if;
else
alert(warning, proc_call & "=> Failed. Terminate loop received. " & add_msg_delimiter(msg), scope);
end if;
DEALLOCATE(v_received_output_line);
end procedure;
end package body uart_bfm_pkg;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_scc.vhd | 13 | 42217 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0.vhd | 2 | 8791 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ncUawuo3vR1ZycZF8xtqqfVI6gCrdI+PWd72xdzgvbKVjiUqedCWSUEBFuuQDLCwTlT4hYrqtcoA
k+jkF6hUqA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
N3KVU8m7dp9m/o5klJahn6JrAp4dPvJ5px8Qjfdd/9teg+MgeqRSyR4a+nedbYovR1iG1M+OV4GZ
eedyUHeQwlftb33WHTgiSQcQOeDYQHOhB1q+SjuhN26SLFWK3YFERu3kL1tM5w3W0nuFqj+bXHZu
R4gQdtVWH/+OjyCytQw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZuxsHcVs7eB3t+mMECRU+c4tWaV00xKC1y8JMSw6ZK4lGIrGd9iKbAKZ3Blwh1vsVCQb3NTC7N3r
Y605Rnu1VKPlFpM556/vIzoPVRgcSvlo0qBj3oTSzlA5eJk5FVF3mP4v0RD6iY8xceU38ESPNbz9
tslYUbhOJVSsY7yCjCM7p+456bByCG6ed5+0nGONoXPAT0zF3Hxdnq8qgQDMjEIvOsaFSADZUSxL
WwjD6WPmcry72t5+zgCtiIUOoGhbFWqTndKP66O5YJAWE6dVlP4zMLQZZAfmdfQyazOsgs1uciSH
+eAOcN/r5BkNmFBVWZOF8biq4mt3PmniNwcfbg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ygy9fvZbqToh8lhxP+oGEoqQi72mLbOonZqXDBQOfdz3oQWE3Hi1Zc2hfB1uR17TPoqAq2eJIm6k
q8c0om7asQ06vgODSHayDyQ+hyxq53TnIlLVx1AtJPfm0kI21kep00Mfc/Dwi7Qyt/ia2tlS/tQw
4OktcMlj77AyGCR8zdc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mcqNli4YixoMqmYwzxOZ0byTQYAQvCZuCaZ7iJ4keY79GxqKVx5edvY5HqwqCRXfHCDzwy4qGKcN
pXmE+CGNG2mMTGEfU6W2QQ+HDW5dsb4d7quBuFh6+SnA7XZEst6UjKRr26YyBGTL5qgiRLyYbkFW
QKRK7TmdgdCAj37TPbTPR6zjrQ3PTlWUwzVToIPxndDd6Jgk0ZyBHqXveC/6PEihQuzGKgS5GKHX
85sYZQakcEpa7RtFdztUyxh1/Do/cjYhmERWgZJD9wSCPweFJCsvo6MP2JripEEkasaBYRqfxMPN
DPHGfcHemBvMggmA1I4jVeD0GpW65Lo9IxE2YQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4768)
`protect data_block
SzsPkdK/1I7crNTpc3RI4SlFdfDTvHkI9YdUtuGjuvthNHkbB0O41/ot4CgBke7A2quFEZYstPKr
6MuV/JZ5j+1RMNw8eLlIz1UbBFygHXbeTyAoBP6UXh48TAe+3D5L+/auSgirevMCE8g2JjLbmB7Q
fcBHvrbSIcOt13ahrGX4FmrDGpF4rrtZYU+hW1vMQvNSOlpoI3Ek9LPv7Le609r03/Gk/Je8wBdE
DKIMSylF5uIM8oH+tlC3CLmMydxc/g98hchIrm7YEdVgq4o8k0KHsGCsirVkD/UEDKmjo8pN8r00
ysj2yz8AqWFkqjbqVhHycznA6w9TQAmauXtFvmWRowVoqS59IyWpCuMMqX0BHYtgEaxrtk6RGm1j
PSGPlNzwVcpqST9V4SaWO8s+MMwem1/hsjxeNx5fngKytc4QrbFMm+U1JdDCLicUJ8NYAoMjruic
i7knXm6kbIu9h1hYkNjgx1p/3T4E6yKRw3GkAPm3NFTYdL4AqmZItKzN/zE4inC/qlcRbKmsCqgq
+42cBP+c6Bcs2nCke9IXUYLCAeQJoCOWyLuJ6FIFUpS1zBEV1l6Zz+xjmjqNffnUQUWHNDEIw3Sp
gwEE3vZK0bqnxP3g1rCAxzwukXO0aXFhEBsrESh1KNy4jAbeJVanMxx4OYoTS9FiJv/ENksYgQAP
3dIDn7GLTkZ95mDiu4a6Ajwa8lkKumB1uUjAwg3jOVRJhjYdPhxMurOzbRo06c8j8dLKXCtf+cQ2
FuPYfzuaXBIzck6ahWRIY2fdZx+5mvDNEqAQ3BhvhaYovQhAonaWKbZ34OGn/Y45df903ceqJs7x
um3cFuEUjWWIQUgLOKmQ/YH5QYPAGhz06c9MOwCDS0pZCHWQcKvcenrxCyF1MQksQ51U6TVvOt3H
mpxnyZPr0giKF/VDSbH8B6TK41nx0LmGyXoj4JhGWsJ360hiz7oLpeLgAfSCT7ClLVoV2Lrc3yjA
G34SeEqZDeiTVEdKtFmpkRcfXQjaKs+4byZi9r4bfjeb9RHaleS15hv0WE0AWggANpmdTeUgpm/H
0yLqNNryCBrWBP3/1WPRHZPiEgUNl5J/Lsg7QSNImaVNk4nuHK+Od3NecXE1SmZT+JYhRmPt+PaF
AXhHcMzZuV28TykQj/XXYGStDvbdU5VtTjHxFlBNjaa4reEzmzhh9FT77UvxxQxeiVTsTOstP788
JMSSvaCFcfBUnt2IQ4WAQff0DUEJgzUlT9BR4o8mzW6IuOX20QFtKGLRtO4BR76gQSOTrC1cQQW/
XOfqIgud2uZS0j/WN8fIRjgwP/jzzbjfekt3puw2V1wTit79d+jSsyu6c5KNBf5GH0mRXH9UCnsU
6yeuNZKkVLIcT8upizM39lpvJhN9NpkNKQdmCdP3MBw0fQjlfEPBiu0rPAnD+0cMRMobOkUmS1Er
bB81HzXhZFhGYHCrCIGJZegMeWEfOgv2eHQB9ID00lS+4xWa3oiKliCbvb6yPsr7K/YQDlmLj6Gl
p8CRspNnjSRAsYWaNy9YfNgorzR+bC1ymwF2H4f4p/PTeY/w/7IK5FEXv/bHlt/32v26nHRrf2n/
zZiDpYI3LDyAbZMV9QUvRpcDDpnk8r8O7CiQ0yJt3+EPXXtWnUELsh/bx6iRLeC6WIog7MN6mS+o
Jxrbs4fKJe6WLr/1x9LJRPvnWf7n5A9l6UPi35IKauOgc1bCT4QJ9Dm9arEfQbWicVCmVf1c5mX1
FvJAb6ceL+6ngf70zBMaUmE1kWUk8mP44s7Y6VZyCdmx3Cl1V8gtETy9/81bePHp+2vQTSCXUPfh
jscD1TCxxICI238mWBtoIrPs8SvmikOPRBQzVg7IPS5aOAzA8TEXFMCXdicQqNdAch+W1HMW/E5m
YwH05SDI9pq+Z+gkZQqVR85Jl15eSIFeEQRHe57LqkMogX/461jeW4yhXPL/U3zfYQFocfiLUOuD
of7RIZItTp6rgqpjSYlnnCqVJrOR0t+UlgvCEEk9ccl+X61uTtGbCaQzOXjCGw/vATgcWh0HtRrW
UHoxDCT6u4jRgWmOrv7+VEF4bfs1SbwShVRyrhHFDFMbaqQlqcoCkApAGB85/h2PnPqwETH0wOTp
bY6P6NDRqQbCj/HvxHBel+WGkLewhWfZR7hCf69lf3KUOkj5EUTHEC1abwW5WMGrEtcnz75KWv02
LabCUwardxDJ3Thj9sgRamy8NEDyyTmUOCeevRDRVekHc2aA0gRbhD+udJwRcPnGBqYt/pS6RR8l
hG19MSO8ig9RyED+GyWb5Bfq09MwZDiDyKCH0n1rtK3MsAV1pCEovLBm2ujJZzRCmPpCZfuM6EL9
bwb3DnQxK0VP9lxs1e9epLgkRiskWYLTO/eLuVMTrGqHlwD7z3Xf0Xc9dwZhhP2+SIQOJOCGar0p
8eKPlrcGzFoOfq2WyEMMLUPWwJwIoM4wnTONW32+tdrAKfgyu1e6tK2csp4EP/ygw54P/64kGzUH
SFjHw3dT8YEEXnWWmN1Mo7XvMbGzaU0l+pJOh+r6upYR1c4w2EF+V5LSddKRtb5aCVX8H4ZcrviK
zymaC7IOJ5cIaN8U16P3lPIYcOlBSNSUlHCXNO5Q3EEwM6cO/5xphJh9yBq0HAqsibpOre+uTVok
LxZc/6s+8+ncKKBhkWwzPfEh2Ru1lEZRuASOBWF7kc5H3rZbjmMnBi391fYn10jd2n40xgj7GY+6
0yXoMPFbKycSJwOa8noGkvcTwwCNoUq9vjr94/6wPwEYqE0FjzAFObBk1z80kg53QPrwO56n2iHb
bKSvrkJ7M2KPRZXQYceVwfeie743Q1FBwYKWO5IZkiR5fAZ6pHSmB3VNhvbH2nMZlVMTrAhqXeh0
cdt7T7n3aYGjfbwEvBhx6Tm2jUZpIoi4uu8okotH/LdhOotG8GoB6JJSZCy5oZM7ueBwqdoqV4kE
fDOfaNvXkVeyrLAMwfzf5Dtq5CXrBnakfMRKpn3tDhNXlJKqXwmi/wdgmg1iO3ooNd1mBYBFkIzc
W82EOSq2V5ZTtxZLhHMWYyepHi/bf+9Vy0C3mxuXZAteOBW96vdk4q7CukhYNOi0UQxObn5QsSCM
EGBpULRAC4fqoP3oOuKN/HsoI4l22rteK8Vks7WiijF+fiTUWWvH3FLGfiOqY3ZyA6Y8KYSpZCu5
l9pBS6xKV0m9d3cqM8Ln8OTyG4jijWGekoRTnOROMWMYHnv0SUc8i921m4yRIj1ECFUDLTIj1Bdz
0QdbTNitqUtAv2aXoZr75aeuvbgrdthkG11zl0Yu9rBl8wZkCQZjws7s09oYJ/ibQAj1HgzgM0qw
rHct/PkPVb5LY+49mvYMqNXQIo0ijmxmtYUzcDNN6JrJkEGYI52i3c+4zZWMAn53P/qtvumvJ57j
feMQJc1ftZ/rUn6VHn2uE30W7UiYLX2ZutsIAS3Fa1JK3AmdjWZJtYik2PHuAhJLEVg3v8493LSH
IQihS9Zy9VCO3z4vd7lceax1Gjkv1Lo3jab9MITC/TJeGe69XqRBPb7XjInlBu7FvC/ci12dXGDm
PtPirOrzn1amGr19/CTcx65Kxw0SOpW4GUgsRdN2gd5To1Ho8tGiE2JqhcPtFE83MkUzAiOyuOEK
uerzKaSVrbAoYKPPVG6xFxJjk0puxqVEmlTafxs7ZjHvdWf7g5QLvft/awnVz4G7NdkO3LDJ41nr
xN2si6RXiKQ4j75yJ3Nn26jNWiIJQMkHSNqVlyb8NXdwvEDK2e0BoaFSXX+3h50C/ZXuPA406XBK
3WdJ4W8XaCWAiDnrycPzKwFFOo3GgrkYh+eLZtTRTvs3VpmfU+9XfrWeazDe++DLQfZm7xoiY/4i
zDo7DQKh2o/djhd0UcEFjQCBuseRfRARZUzuRNyvxXeN7Z23LFS3OQR2efGhEK3OxjTEpBNMb/sj
KcMnnRkZfAOCriU1GHtfjt/MDNCBXvsc+MGexF8wXA9sPvHRE/ygEZ11V3AsXAnDjq3N9JoBLlfW
N0nCuv5hgLU2eeKWl51lYDLb141fqyTeoZK4n9Y5068i5iTugyutyg2/xqW/Q9NmaP+N1QdP4nBc
zgUWlcgYko88mvq9Uyg1sI6tz1Ln0k7q8F+gtjwPzgR5VA40TayZ2BKNB5FKSIijZA+9K4Vsgfvg
vGqQgXVEoGWcTPrvbmOOkZSfMj4tgpNaXbF51KPLfH//PMhK6VgBVSWOFxNTOjRwXC4x8zD9UYYT
sylCN0oZS5TUiQ3JnnlLKa5+fPyC5EVZFgO5RPdPZ5UhJkEvPbrGtsTNBKghWgLWPGmDl1OLqZx+
g+SN3GrW4POHYlIyMIjmGoOGQ8vDJ7WcEbElmvfqXUpWLa0XdV2ndYE/k7gA7o9q9tdQkCPwzTu8
3vXnH186ZBLw2rBspzje+tNWt13xye+fo/mKxP6jpk7SbctGtaaCuZ9xfZ6UzuEueEXJ3IeRywoS
CK6ilIBbuwGL8BWBBBkwnDo+RC0ENL+7qXrwSzMyrrKS9iPHaG3RFC5869cAA4IF2IYNRAC/fmSA
TEen26NbvAFn6iPk8oHq0SauJJ6qSdK24XczHhe2Z7sO4SCWQMgdRhituuleK/kA3d+8BB6tEh9S
P5+kv+vh08bWEzXYUwRT4CILLva12hzDZmqGKM7DDOoW2nVNZ5uVFOCZro9VkLrFSW+7tiDCcfhR
FYWuGBErrlPd88TsVW3/VthYcixuTJ+Da4Nzi/YkPCjgYE/0JBhnzLLm/XEaEj4T2aUdnlzxt1MT
OyojtsS9AvyKCENTf/BbJ7487EuSsiXt2kjSQbRfUoaR6BJTH07LV/tljgmerJrAGx/pEznd0WOm
Wd1IAZR7Vb3NzjqLOdYOa3vvNoaFRpiEi/jx2SClO4rER8oeFWyoFVIdox1VW7rcM6pGfVkP3buU
riu627i7TNpYySca+q6jJZ/CiTXgQ4jHaBQDdIHpDi25kaPL7WUH/zmgMEiL/8NqZIC2SVytncsN
E92EERDjqdD+l/M/kusV/CKkoUWFQyL3sVLdkrFHq+JtAlRFZbqifh/7ogv0pYB+igyuKYY1e3fQ
0vUcCqw7WWQ7ddkROIvevCQ1P7JvfVXNhRSLl82N7xQYqcxekRXs6HllJThZfUiIQGPVvOkOpvZO
pwyAlFDmF5sq5ScrIrMqIRqf+p3yjS9mTeLonlTC1NuXLcgLVj1ncI86sFnSaw5gYvov1uO3IuUg
/d1PNg2cpKvBTb78VP0Ez/z+AnhkpMTWJekkFU9SU7Y4D25ID1CfkS9K+WkQAtveyhQaWcUXae8V
8VPMlG59RxiD5wGPDE3oZDqRoICa7ygJC0vzM9/2XLKprDc5dVxTVEOqGraM2hLCWep50vNZCv63
IMooVyubohxpD1N7ATy5jABldkrFL5hGH5mnjgSLMZ/Ea/7wOsoIyDHrJnbqsMAuO6Fe8U0byK6K
FyddyPN0QSuXVrm8oLFZCOU/0pXlkvHvANx/MzSaGOj+/5mtfTbuSYB68pyJevseyCNDKd3939k5
6/mNJOm3GGhQIlT8sMldxlBjo3OmMbgsBWhfB27LgXi6aFClULENSLmCLWyBMa3UTPtRsFJwLZKT
kRtVk454OqAmLW8PenhlUJsNdsmO3jFR3QAukXgzK+xoADUE+vXd81z0rgzxI/Y3MXS4ELlYMga8
7B5wnd4zGeXFOLMWg/VhPYOUws76Zbg02nodUyo8JGMjeo2dc0IAtGK1AdrwP8xXchVeMFLvY4Yj
6VxmhtxiGJw27H8exS7EbtUzpP8KjiJmePKorZEuMSOmuKa1FqB8mOL6PqA/IO3VANQGZM+AkTA2
i8QsBmVRr0FbZyQsitzhyO1c/GqPyBUBKPbg4jtxLzEJlcdv7E3IR3/x7dlmdbu20+H+Iab5mVo8
Qg2JfT8P6mPhPMLN9FwW0rzN0kK9hknU+kxsorpBcz1+r8hUIuHDK+c9X5/2H1sNd7PXgJEk36Js
DhIyEkab+96cM2/w5F3zfg8ZWt/OsTOsbZBWFqA2I1tH2CXw6/H9lR08WAjToLu9fiCSJyJ7Az6D
1TNnRsOK7cjVA+4HGxw9yw9pFs1AsV4Mna2F3av7e/mKsuFLQnuFdEN2yLIPhs2BnUWfzcxA7FaW
WvbCFtHLMuAwN0179Td8VScY+m6euXi0KQAes4YMdp2mbtr8wxdqzNh2UXPDfcU2pArGxokjywaT
Mv/5tiHNbuzV6pYOtme5Cz1SapOozbODOcjwZ1n6i/GfVr3ZrtV0hIBZXiXnKlv5mK7NvyW8GiSX
t7tOeRpJg8Mtyt2gW/7pxg2J+Rr+ZSK+XwXhwfYbcMfpZsQihw==
`protect end_protected
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/dcc1fbbe/hdl/xbip_dsp48_addsub_v3_0.vhd | 2 | 10258 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QYO4bC/BpWm+DaF8UOmQDOcAsbC+d/JMY5sEWsuW/VAJkhlLLCRRf2xj4mrnj7+ujH/C+7m3q5Zs
xzDm1At4AA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EAsx2FyM21UM9qDHbPXzMh2eIz57llWutyxXjqztKcjjdTHAbzFDJJS5CPdBS1lrQJ1r06THDYeO
GIekzNeZRNi0lRWvM3FBDIM7X4sFJlQHq+pR2abGJ8GPEp9gNqXZ5PP6XBfsWqx35TdFklwYtvFa
xdi/Ix1xf1piHjhyHYc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
d5kki2wUhqWmb3MsbBBrMxSI9FO+9SOBUjynp6O1iaq3hfGEQWGUhSqRvn98pbYjT6fCAaDJxhsl
RKGZrR+stNRuC9Dp/ogEJp52uY+4pfvj0pv33xHI98o2jys88DdirpOiEDgKbDE3ZMYX/Csaxrf3
G5FD3I+2lXGXnSQfxOcQ2qNGS006x4oQuL67n1YXv/OqWXGhtNpKpRnvOtF+cvrEWIPH5g+efRzg
aJytpnG6HgJDLl3pMgrZUyeKP19TA3q9mVoDsofNDxPQHiVzkNFnN8tnnA7UcpziNuimX5P3clH4
zYwZOjVmz7EuWFXGiW1eRCVdOJ8f0HGmbsAqVQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
mwiFaKBDXPtzvtmpoM0UUiJPfcSKgcKD1m08YQT3IOchMOL3j9+ISUQt3fW/ARdaiXpZBXR7Vdkr
MEZ6gFHAp/pWscKf6s2646QPNif4QB3D7g97saxcawZZFOpW+P4Ueea6gCAo8X5YkZlyGH+ZdzLH
uDreYL/JP+RbWEsT8Vw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
CgrJkU1GIqOLFE7DBL9jkpVmyfsGQ83rWL33M/TvtINaYmtwiHngb7oR78CEXsWldXLw/RruR30N
dogRR+szYc45aPcxFc6hslv0SF+W+VYisQ2eCPD69ISmcJBwfagbtyJm2D232eiNhqUtMcB7ccC0
3Lwov3FndXMeKNFZnhZPvJMEd0k8uwCu5GteXUwYiTZZ03dHbC+sN3XKdvmg9fOw9LtVfzEGRAHp
NouQU4BzylDB5eRRGHAViLZZsfcZvQmOB5oyyF0DkU1roYTVUV1zbmhUXMShK0SaZ6rR+fRJxB54
DwPGwCjQQWXcl8GYcFLObMua1VfrD/fsI50Sow==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5856)
`protect data_block
72H4+l8g/RQOD2U4ROiblpfv1EU1NAX67TNpRdBTZBP7J6eNEdEVm33V49gCITcbCVqRhq3eADpw
R5eWTqvIteoA9lCyLVl34lg+S3fEueu4/I9RXMVnzPfV2bQhGrw0LBP39235UOiLGhdgM2l7Fh20
pulUb0A4aVio4/seI3DAm/f3zkmvS4BGvcClDTwI+SDfPQ07Q02SZq3N8UuZfw8bOXcN5oMm6zgX
F3FzltvV3njq884bWNqcyNhp21FG9MfgGJU+XYhrwyKnDjvSu/vHN/kbNp0V9lMHDBX2/KUc85tp
apNBSKDCNNYnQKHUDJwoHw1awfNfWxBjlOEEdD0wKoYgAI2FyEydNeQ0aC+c2As5ItYS8zwN2M7a
tlNj8JUDK1EFabkk7foQEZ8/xKJ6srChhD+gaP6tuMwtuLqZ6Bz2oql99W+pW3GEigCAvYxT2s8i
rqY9tMeHb5MQEaj44xrk/fCDrzYf5tnXtboLG2ifhjW5BYp1G01V+X3Bqp4BlG5KlCQXiM/PHw1K
SVAGMwsqRUUn0sWsIVW7CCOo3DhPXek5oUFGTGOxGtmT38smJgj6SghdpnxvsfbYp7biJW3eC6tS
6Uhe5K3d9GwNr8lwjRsTjUsuO9eH3X4S3szztrOSCW0fb7YTAWtJha1qwgzpqPRzxDEZqBJuezf1
VIwZyyj0e3TSN7LEwg+EufqlobnK0BV32e7A1me5n/q4TqKacJIBjXh0uioJeN7WH7F1/Ft1v3gC
9Zkc6JKGzxAxxpGUuP6xa5Oy5dKk7HH0mpg4534NS4f537pB0Y7yWmLEicg+yCvdNTGeBoewvjML
pOTQQPr0LgyKdwzp5aOLIgOCb+DikDQSzPt1JZPBL0fM19B91mqsgSlGVAObcLMmkSfZlhLAlnCJ
bV7a6hRsBcewVk+5KNRTmRr1oooSnPVMIKCTwBpvKA3uos9Rhum9wLdrD9UoOuinHldN58yhEDFS
p8ELLKMWXQLTktQzcM3PvewftynGkRQ3Fbfo0bG0w1Z3dkCwiTn39QfJBQis41h1R76Ne1zNSpJ1
hVDLyeOGhk5J7T4bImQBu7RS7bCBvi/k+E2+1OibP2yJ4oZzQIUDxtyxhFk1a7QOfuxBbftKxAXL
7emHCexC27mm4anWCMY/ozTFysQcpY1tYVxxJH97fQnffiYEtdqAdwgULTL6Do9Rcpb35QNysLH+
SYsdp5p6GIfJ89H9TkzGE9ImQZ162zoilij2CPKTTma+4/rPwLnwR+jwLmcX+aFeFvuC/k0DwmBy
gOHr1uO4mJb95LrMvT/V1de5AI1TYZ7oOzIuFCtm6oZKtmvIWW2AFebwMnHHYl76kYQMB9OSt58n
DOH48eQyKTAM4EJE0wzLmUspknZIydSjbqLzAjJwLCCRKDvQP9wvP8KCauEWRHFdrLP7RaIEq6Yj
xsoyGqyQLhCPtVCotzLwuF5KleulYu6LZ6CNsVrf4FXobaJm6RvRTvd8YEtawLW5ow9hX4nehfaM
FeDz51/HDih1+sUxyrIpcPaZRZcaVOZ8GFdI37TFAV+RCNyYhFOM3cg0DlOxSaRWnDxFJO3bSGv1
OwfrkgVdcStpbdn1bXpRQ6jfu+apUvQhza/fvNfLgcTTVgbV/9I47yTgSVLZ5U3k86J4tbk4qAnn
sg3xwJhhaXifN+14qt7iqmCbDuCTnjK9NJN95Vx4omimxC0gmUVLh2DWeJfN7em9KfYaVv1KYBy4
NojQXlDXoOVSjlqWdtSaHbXP9DQzI4NqnAQpFMnmKLNKZG/v/ZLvrBVWcCCyzOk88lbNXm6lbn9M
DczLVWjnGomNYYDkyCVZFi/gqzMSN0EOzn6ik/RzmG8wp7zANHoMmI0a0C2CUjNUr7fuJXtzhEBx
pg/rVBl25JbVTEcMCRufUKpiGLfL5Y1dHDijKDSbIOz+wZSea3IbKcTo9lteh8gQPsmRwDC1qVPB
Rs+cMgPO31aoGhM20mD4jqocufGpFaDktYhcFWenRPGOZgKL1LjVIQ3JEX9Hk9fIUUrxHGNMCJ6s
UchD3DfGniayo7DFwiMbcFlG2rRMCduJrv7ZGTBs3+zc+nJ20MNUsk2YD/Gnj4tXM5sQg8WyHtPK
gAWLyohiC49HtBJK4tSy8WH2YdDS6IJPt1hb4z14cvlxfUdlSrjaeRcJuYFBEQQhca3aiS0fuES7
Pi1jFgK2oksRYbPQPFDbySNOhdFhXukzWOOWDhTeAL2sEpcvp7GEkPDZfB5J30C5liXFkl46FWSa
Dhha/HqqFKirCp8eA8pufJbXxvk26dfFBWEq/pLCjI66BUYZMEyVo2iW0kD5UVFudFjb4vti45Nu
nlVSZ2MNDGsC5nFs+8m0llE3eZhMZdXkvfCPHUTaHxl5yUIhL1m0gSOt5AvNNgM/8AmR95uwskFw
n0Z+kFXM8LGwG56Z7SmeI9xhqAAVgRcKDmsXSiCqFKCNVUyXu+WPLIOnlz2IK35lqaz9eZ8g0jWn
Wsq/X0ukj+D5EIyeRQUw+cXdzqxbOntPpnrKXyIGj1gI/j9F/Dh9jLz++Yz7JArphjPP8iZmUl4N
ApXECnb32aScnL4MUibFUXt98L1UKK639noqBLnBCaSWAAysCBop62z/nLpJzUMhxqElqRhCgfdq
elktxCmAtb0rGkMqmmp/2/Qv21/zW7+y2HqO/eOERQtryreTosoHCccwqzv7cUiA5I5ln4D418CM
gtwO4VYkOqWvdfuDrfYGfKCPnZV1ZgXGVIbcGbgFzJpYYLEOLPdR4gndUY2doC4ZQ1WGe/dUcekS
OoDo1RKjbmdzzK8AX5Rze91ty3ClWw4Ff3LpvYqUZzH1hfeouCijpc3DU1iu11uQqRBt8OafscaW
n0gD9257LTCdxwgy58RiUarFEuRqdjO1RHXfrDmpWuFbOKp07Aya2DhhFL8hwkeVZn9sPZkb4+Py
pjg4Xr8ylb9CnHGlS30TdxLl9EpX5Xm8fEQ0JL6db+/c+TjG9rWwvRyNAzrspkIq0LiVXBF+d84/
7z4qUicWY6i6J6FA4jTe41iMpfBZrFhf/ssw751SaE0/ue0F2894ibPkCFDlHefvlvjCN+cmsJcY
hxbEXYjsNLVhnqVSvQUY3nLodWgUtHJ90ehQbUu/oey5JFa71QaT41mqR99wFzPuYG1MUhWF72Lj
RTbTnBE8IVUcKMfJ2tSP/6bPFGLIwu5q+KScqchIJKTfDKhNSwSe+pIu6Z2WeV1Qf8Qfc0PYtwS9
k0Pta1uQnDd12TW7gEU1XsF3wf2iuWXHeyKYRCYeVNYe0uLPWM1q0HF3szbjIlQ4D5TJWJZ/f0Tu
PqCAOABJNXGDQY+HO0TzX6p9IbopJLgZqvjHYy3T85MQgGKU3WYiIx4AnIZbXRRPPH5kV0PxEVSy
kcsPhnwH0lWONe0H64kZESYwC+CCFmytnX5uEGoSzNDbuIg8+Grp7X/EaJ2efhi/uswhRvnyp5PW
29c4RwS9lXsIDomyJlTjICuF96dbzGKQouxe0CID5nxj6nSPxPoQxKNiPcZZ1nwrL4+rvlf+2ReO
YkWlCu6WXUQU7V0dNb30C22dK4UGIFWTpIjspdwbd5f+wPTyg2/J05zYen/Mghae91kYj4iPDENH
5TZA8N6GDeqc+g0p7GxqIahQhH+pW7e1/f0WAN2Un3dRswAhp354Q5x+Vnh7Py3VIAiXlo/p1B09
1quK3D3Yep3M8tqfHNgRvosAXpkK6PzrTCI0JJUw/ncaabLnLlR/l9VDBV5wFdU6XmIgLRE0kQm3
mLFcTHYxa7NuQGnPphCPe73KJEx110u8LL7XwRBET2e6xxWONg+9ot6S1pVa/PIssmkCBtlqbwVa
gcQqgyX/p/30X7u1TnjABWJTN14mlJWyJoD/TDoUEENHhL51rUC0irYIdm9Bsn6M+jn7oMpd1W6U
WKPlPd4yyR4VfeHTYElc1hqrc83JOMLG4LcPnfTqkq7KxmDTLYpTbGRO0UjPd2diQof5wLaZP931
7txlmlPA6PmHiDoEyKc6fwT74RPWSIajM5Ky0n+wsQBg9/NnCspytgp4Oki+MC2iCRokzp9bkJ+q
KPK4KDyd50s4k8u4SdXLkQxdQjVhCAnoS4crlhIalFLECdlbI3Kx5oz3L2RUK1VCU5rP+uxR5+F/
YnqKezlABZNyMoWmeG/2JWWGmEJD1GZP3Zt7BK3vxV3noHl0dm+y1CZS7sMlA6dM8Yezv5tTVAgC
rkAmTZNsiVMQfYBHsEJZwqBUzN6/ON6ZFCwnllTEvEkTr2+qmAAGKQNWF3HYzeiRtkeGqqBP6vmd
AT39LDHuvVG9X7xkfBnRvW/7c9FytPQrNvSdhrFVC1uR5LncnGwIJb1OI2zI342vzcf+N/HlITtS
PCd0ES7avjSwNIhXCrZySa3/H87k4GwP+BlbYVM32lmW1svdoIco10AOJBTdvTE2b4/nkHQnfA0T
aWBvdz5RHZ0B1fAPhbs4Vh0G53+wJO9EMKI5P5FfSO1cM5ghD3naXiVzTsHv1f6rvogu2YwRuIGR
HB65pnvW+dvm6a8BXgA0ACMpOncR6tVW0RvHgrKKu2G8t3ii3tez33Ma8lhCUQbJfeCWkAq8izQ/
df68DOgmJRkoueW1zUEQ+a3+UMgXZ5YrDTYRGTSIZLoD1HA7yTLh5vNG3w11yLy5aMwfuhc6BdGU
wyCcLJlpzQdq38q7CrguXbZZ0UFWIAA7iw7nQDfVxRb3G3TYxJYDh0qns+GxIUHkx511GETTpryg
eWJVGbZcUlCQ3iX5wdsr8Z7eGPEO22WODlUDZTPlDCJgoUre/tSa59+Y0T2GFKCOg8zurMs+IOyc
+j7AaLuDfoo7XRqshZiE7U2POOOQDvPrbSNxUt9S/Aw462FF57rzXAl20KyXwiknKQsvyzRmFmz9
LXxxhGFRfU4un2lHxVyAA1ROo1fUmgj2yoC8P1LYT23avqdgvIpczmrrLQEPA7Q5vjDJaiEgWPJ8
mVzl9jltJQHclvckZWiGJSdZk+AzjP9Ielme8kXkNy77Z9IvHhgBWuSMEc2I0oxYBdFGD0ryOU2l
m9Vrri3k/Ijj1Iy6h+Cpr5VqAYb8CqGW9zRwRsGOkWe1jbO22+IEsQDUJKrz5XF8VFOUfAFoFJb8
ZOGRY9RUoBnGCReaewRk0aIOHd26xBYKWxJRWmtFmbU2vL+UEXlCZcyuZ3NencwRffMzzKjZOJRe
HV3vSOnkEWQsp5ul1JMZono1Znzu7G+AaubQKhol4Y6SHOZTXqC8ByZyO8APmhP6Nf1kyxAaGQuS
TX7JTyu4UX8cAF1xyZpZPLIGQ4IC+PL1oVwitSQbPHqkFmYfW3bKkfBPA59xeJQmhQrXbqrsG4Wr
vmkgV0OdGb/hCu1br9wFoRjdt0CYxms6PrPaAOJyX9jngKqvAKDGfq8Zmup7oPGDvbcLnOAJZYOC
3MqljWG08Vx9fkIALY0m6hhAc+gjpiSKtMFzMYkevvYZrUA5XDVczN9/fqBaa48C25rVNWkgwMEA
UXNICU3rDrHW75+MCxUNraSrwFCZxjsfzxtHkxkMEqkZQiOJaDwzQtIkyCTOr2cGOkJNAy/qRIBv
eRph/hh5lc98xNVPlW/fdJBLhMBbEEPg8gZt87RhkDrZmAHHUQ9CjScnr/k6CSYJJmAWXwI8NOB/
p9lfucMfUBAbbhQlh2o0yH6TiEuIf0/mT0TfutxuofLSTtZgcDm/AMQV3Gl4EYai+t7D1kwo3LDh
Ur6F7+Au0gFQIc6EQzIPg5mg0x+o0w/Pq+QCbYbUe7NrulL/6hH+/31j7aAQ9K7+bvNrkyTKniDF
LFDjFI+r77UjHztHe+OE40nAM/cJ9sCPu6XYeFcmJYfEuQqnXdt19aQnUqmHQZF+vvaMuEbrMuT3
wq47J9EnCp2vBteV3VP6F6VveqLRlBMt4ab/BEpWNMEhYdov77Qn6dug2ZOwS9EKIdwxMYWdJeM5
Hd19+PCC+OtMlM2m3kplWTPHjhkoiHc9UT8m0kFf9/0QnkFwuZSpdd8o4NLWfuMpTqbJ+IDdLXoE
4uyUC6G795Bx+qzoKBq2i+gtQKKcTU790RDI/l6WL7O70vUOvKOmsQ17b5onqt45cHMQzjfQdlit
d0sjtQKiy0RB/jV3xxs8Trtmt0lM86I7lN8mA33W+66OOB5QvwW+5Omna/JI13x26hSnWE4nJ7OI
43AOCsUpyuUYcv/x6JtGsPjEU9bgIakpYX2uWtMVv7apQLxeUfTaGkvF9yRjiN1DXocB0cBs2ToR
xBc7iMhRGiF6IA5h18AwmxCYIlhum/NoCeiVQ5KHv28YBhQyGq8W2JD9tZAbcKCj9gUBlUT3JTWO
D2hkIJG70Rl0tuv8AvYDaJ3p0GBSdE1i7aABamdy97cNCI8qWKb7bcWs3BeKKjFmyRzYzxUFxjEU
/QYV9V1CUMQxyElUlvHuShbKo25i6HRE06ycS+AfunVpdnsZhKlsFogcRfKX9ElKAjV3fNQtgOxL
TF/isbOKikuMb5DHUuI5FZfZaLHHV6vxfT0hmhCAf/HR33g1qHR8G71w82RpO2dDxp/HU1p0wktH
1L9KSSS/XvwZqypNd/EOB2ydiDT3Ys9htvoxCtQ8T3P94oS/ncId6BFG8rBrPO067P3rMsrXhmhk
5ko1p/XHijKQyqmKIZ3WF/xRTxKEXHePVTyQC/2giqiS1bETm2StkThqSw+WFfl+AiYrbwCmGrnU
H7gWrTP7+85vAuPhvYyx0CvgSRk1VaVOfadBd+nUTD3ikFiVCOrUV+BEAW4MAVZY58C0CVypI7Me
5R4ceW8SazHhs5IjSRIV6bne0EO7xERN5VqJb4rCq47IKeeW7kK0mmegj+03nolEyL5cf7u/KyKW
An5xZU01KGcvRPJ/ls7IVGMMUjx5yj/1flvVLN7fqTNFnJAtnr+UFIYQURkrfArnXzLJeDmHPFhC
V34rrKSs1AVPxRGg1g/q4crRIM9Sm98AoIZB3LH36el87tRnlHESCwTihvQ1jABBd/4cdLUfxoNB
BvbMmiYWinAdPtIlgmxCZzYNX2RmS/635TSyj9HkPTNGcs7H13jM8RQgkh2NdXL587mIOrjMtS58
mr6dTS0d7zzTZupV7vVvKs+G3xZETE108sXV4VnqXAheabIoqq6tOpbNDISd6pdHGj11t+bUdexG
V8aZYnCXJ7T3gXQ5Y6IxOADLWXFLO/P11+nzK+3fHVQobFKT+V7DZdJKGOFVeTvCfP0A2FF/u783
M8UFLXXc5UYcZALs7T0eMEtMoCce+TwHskKS2mwjtE7CS8TsckJzgJt+TW7EjZwN/4dOhETQEsxn
dZaH1rRVsmtZhU1Eq9QxpygQwEejz7mdpnEI6ZtxEmkigYYh1ZxullUPy7tj4bltU8zD78qicgsE
H5+o22BRRMMSsogQM46lFwesA1XSVWHD/N9Usas14edRhbsKD4F/IRIneG+SjKqZR9jAQOw/Os83
JfC+wA4qDPQHU6rRjleyl4KU6/8QlIB+F7eex2PwVM5oPTa0+2YWGrFa1ESh69Uu316NsPZtyvjx
9w41PAlz8HPkRg3KA3L82mCKxqVFyXnfWWU1prxQK0IlC80ml5l0v7DhflNyGNIctOG0g7APJk5t
PYcXQ1Bx/bt06Bvg/jFhN77ouizNB5a/irDllpiNpUNJVqikpokBkFjGjNOLFC/iuy6mCZ5EUD+C
KSvDdRlVfxd+2WyAtON4OvKlMV3SPgwOwChz09nBwpGP3z1xPFNrxh7T
`protect end_protected
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd | 3 | 39575 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_q_mngr.vhd
-- Description: This entity is the descriptor update queue manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Control **-- --
--***********************************-- --
ch1_updt_curdesc_wren : out std_logic ; --
ch1_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_active : in std_logic ; --
ch1_updt_queue_empty : out std_logic ; --
ch1_updt_ioc : out std_logic ; --
ch1_updt_ioc_irq_set : in std_logic ; --
--
ch1_dma_interr : out std_logic ; --
ch1_dma_slverr : out std_logic ; --
ch1_dma_decerr : out std_logic ; --
ch1_dma_interr_set : in std_logic ; --
ch1_dma_slverr_set : in std_logic ; --
ch1_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Control **-- --
--***********************************-- --
ch2_updt_active : in std_logic ; --
-- ch2_updt_curdesc_wren : out std_logic ; --
-- ch2_updt_curdesc : out std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_queue_empty : out std_logic ; --
ch2_updt_ioc : out std_logic ; --
ch2_updt_ioc_irq_set : in std_logic ; --
--
ch2_dma_interr : out std_logic ; --
ch2_dma_slverr : out std_logic ; --
ch2_dma_decerr : out std_logic ; --
ch2_dma_interr_set : in std_logic ; --
ch2_dma_slverr_set : in std_logic ; --
ch2_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Update Interface In **-- --
--***********************************-- --
s_axis_ch1_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Update Interface In **-- --
--***********************************-- --
s_axis_ch2_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--***************************************-- --
--** Update Interface to AXI DataMover **-- --
--***************************************-- --
-- S2MM Stream Out To DataMover --
s_axis_s2mm_tdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_tlast : out std_logic ; --
s_axis_s2mm_tvalid : out std_logic ; --
s_axis_s2mm_tready : in std_logic --
);
end axi_sg_updt_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch1_updt_tlast : std_logic := '0';
signal m_axis_ch1_updt_tvalid : std_logic := '0';
signal m_axis_ch1_updt_tready : std_logic := '0';
signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch2_updt_tlast : std_logic := '0';
signal m_axis_ch2_updt_tvalid : std_logic := '0';
signal m_axis_ch2_updt_tready : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** CHANNEL 1 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 1 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
-------------------------------------------------------------------------------
I_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_INCLUDE_MM2S => C_INCLUDE_CH1 ,
C_INCLUDE_S2MM => C_INCLUDE_CH2 ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch1_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
-- updt2_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt2_curdesc => ch2_updt_curdesc ,
updt2_active => ch2_updt_active ,
updt2_queue_empty => ch2_updt_queue_empty ,
updt2_ioc => ch2_updt_ioc ,
updt2_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma2_interr => ch2_dma_interr ,
dma2_slverr => ch2_dma_slverr ,
dma2_decerr => ch2_dma_decerr ,
dma2_interr_set => ch2_dma_interr_set ,
dma2_slverr_set => ch2_dma_slverr_set ,
dma2_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Update Pointer Stream
s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready ,
-- m_axis2_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis2_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis2_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_QUEUE;
--*****************************************************************************
--** CHANNEL 1 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
begin
I_NO_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
updt2_active => ch2_updt_active ,
updt2_queue_empty => ch2_updt_queue_empty ,
updt2_ioc => ch2_updt_ioc ,
updt2_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma2_interr => ch2_dma_interr ,
dma2_slverr => ch2_dma_slverr ,
dma2_decerr => ch2_dma_decerr ,
dma2_interr_set => ch2_dma_interr_set ,
dma2_slverr_set => ch2_dma_slverr_set ,
dma2_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Update Pointer Stream
s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready ,
-- m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch1_updt_tready ,
-- S2MM Stream Out To DataMover
-- m_axis2_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis2_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis2_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_NO_QUEUE;
-- Channel 1 NOT included therefore tie ch1 outputs off
--GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate
--begin
-- ch1_updt_curdesc_wren <= '0';
-- ch1_updt_curdesc <= (others => '0');
-- ch1_updt_queue_empty <= '1';
-- ch1_updt_ioc <= '0';
-- ch1_dma_interr <= '0';
-- ch1_dma_slverr <= '0';
-- ch1_dma_decerr <= '0';
-- m_axis_ch1_updt_tdata <= (others => '0');
-- m_axis_ch1_updt_tlast <= '0';
-- m_axis_ch1_updt_tvalid <= '0';
-- s_axis_ch1_updtptr_tready <= '0';
-- s_axis_ch1_updtsts_tready <= '0';
--end generate GEN_NO_CH1_UPDATE_Q_IF;
--*****************************************************************************
--** CHANNEL 2 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 2 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
--GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate
--
--begin
--
-- --*************************************************************************
-- --** CHANNEL 2 - DESCRIPTOR QUEUE **
-- --*************************************************************************
-- -- If Descriptor Update queueing enabled then instantiate Queue Logic
-- GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
-- begin
-- ---------------------------------------------------------------------------
-- I_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue
-- generic map(
-- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
-- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
-- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
-- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
-- C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
-- C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- ---------------------------------------------------------------
-- -- AXI Scatter Gather Interface
-- ---------------------------------------------------------------
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- s_axis_updt_aclk => s_axis_ch2_updt_aclk ,
--
-- --********************************--
-- --** Control and Status **--
-- --********************************--
-- updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt_curdesc => ch2_updt_curdesc ,
-- updt_active => ch2_updt_active ,
-- updt_queue_empty => ch2_updt_queue_empty ,
-- updt_ioc => ch2_updt_ioc ,
-- updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
--
-- dma_interr => ch2_dma_interr ,
-- dma_slverr => ch2_dma_slverr ,
-- dma_decerr => ch2_dma_decerr ,
-- dma_interr_set => ch2_dma_interr_set ,
-- dma_slverr_set => ch2_dma_slverr_set ,
-- dma_decerr_set => ch2_dma_decerr_set ,
--
-- --********************************--
-- --** Update Interfaces In **--
-- --********************************--
-- -- Update Pointer Stream
-- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
-- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
-- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
-- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
--
-- -- Update Status Stream
-- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
-- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
-- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
-- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--
-- --********************************--
-- --** Update Interfaces Out **--
-- --********************************--
-- -- S2MM Stream Out To DataMover
-- m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch2_updt_tready
-- );
--
-- end generate GEN_CH2_QUEUE;
--
--
-- --*****************************************************************************
-- --** CHANNEL 2 - NO DESCRIPTOR QUEUE **
-- --*****************************************************************************
--
-- -- No update queue enabled, therefore map internal stream logic
-- -- directly to channel port.
-- GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
-- I_NO_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue
-- generic map(
-- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
-- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
-- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
-- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
-- )
-- port map(
-- ---------------------------------------------------------------
-- -- AXI Scatter Gather Interface
-- ---------------------------------------------------------------
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- --********************************--
-- --** Control and Status **--
-- --********************************--
-- updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt_curdesc => ch2_updt_curdesc ,
-- updt_active => ch2_updt_active ,
-- updt_queue_empty => ch2_updt_queue_empty ,
-- updt_ioc => ch2_updt_ioc ,
-- updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
--
-- dma_interr => ch2_dma_interr ,
-- dma_slverr => ch2_dma_slverr ,
-- dma_decerr => ch2_dma_decerr ,
-- dma_interr_set => ch2_dma_interr_set ,
-- dma_slverr_set => ch2_dma_slverr_set ,
-- dma_decerr_set => ch2_dma_decerr_set ,
--
-- --********************************--
-- --** Update Interfaces In **--
-- --********************************--
-- -- Update Pointer Stream
-- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
-- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
-- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
-- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
--
-- -- Update Status Stream
-- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
-- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
-- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
-- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--
-- --********************************--
-- --** Update Interfaces Out **--
-- --********************************--
-- -- S2MM Stream Out To DataMover
-- m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch2_updt_tready
-- );
--
-- end generate GEN_CH2_NO_QUEUE;
--
--end generate GEN_CH2_UPDATE_Q_IF;
--
---- Channel 2 NOT included therefore tie ch2 outputs off
--GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate
--begin
-- ch2_updt_curdesc_wren <= '0';
-- ch2_updt_curdesc <= (others => '0');
-- ch2_updt_queue_empty <= '1';
--
-- ch2_updt_ioc <= '0';
-- ch2_dma_interr <= '0';
-- ch2_dma_slverr <= '0';
-- ch2_dma_decerr <= '0';
--
-- m_axis_ch2_updt_tdata <= (others => '0');
-- m_axis_ch2_updt_tlast <= '0';
-- m_axis_ch2_updt_tvalid <= '0';
--
-- s_axis_ch2_updtptr_tready <= '0';
-- s_axis_ch2_updtsts_tready <= '0';
--
--end generate GEN_NO_CH2_UPDATE_Q_IF;
-------------------------------------------------------------------------------
-- MUX For DataMover
-------------------------------------------------------------------------------
--TO_DATAMVR_MUX : process(ch1_updt_active,
-- ch2_updt_active,
-- m_axis_ch1_updt_tdata,
-- m_axis_ch1_updt_tlast,
-- m_axis_ch1_updt_tvalid,
-- m_axis_ch2_updt_tdata,
-- m_axis_ch2_updt_tlast,
-- m_axis_ch2_updt_tvalid)
-- begin
-- if(ch1_updt_active = '1')then
-- s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata;
-- s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast;
-- s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid;
-- elsif(ch2_updt_active = '1')then
-- s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata;
-- s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast;
-- s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid;
-- else
-- s_axis_s2mm_tdata <= (others => '0');
-- s_axis_s2mm_tlast <= '0';
-- s_axis_s2mm_tvalid <= '0';
-- end if;
-- end process TO_DATAMVR_MUX;
--
--m_axis_ch1_updt_tready <= s_axis_s2mm_tready;
--m_axis_ch2_updt_tready <= s_axis_s2mm_tready;
--
end implementation;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_register.vhd | 2 | 48618 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 6;
constant BUFF_LENGTH_INDEX : integer := 10; -- Buffer Length Reg
constant SGCTL_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal diff_thresh_xor : std_logic_vector (7 downto 0);
signal sig_cur_updated : std_logic;
signal tmp11 : std_logic;
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
buffer_address <= buffer_address_i ;
buffer_length <= buffer_length_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
--diff_thresh_xor <= dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) xor
-- axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT);
--different_thresh <= '0' when diff_thresh_xor = "00000000"
-- else '1';
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Bit 3 for Key hole operation
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1')then
curdesc_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc
((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
-- elsif(bytes_received_wren = '1')then
-- buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| mit |
UVVM/UVVM_All | bitvis_vip_spi/src/spi_bfm_pkg.vhd | 1 | 72549 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package spi_bfm_pkg is
--===============================================================================================
-- Types and constants for SPI BFMs
--===============================================================================================
constant C_SCOPE : string := "SPI BFM";
type t_spi_if is record
ss_n : std_logic; -- master to slave
sclk : std_logic; -- master to slave
mosi : std_logic; -- master to slave
miso : std_logic; -- slave to master
end record;
-- Configuration record to be assigned in the test harness.
type t_spi_bfm_config is record
CPOL : std_logic; -- sclk polarity, i.e. the base value of the clock.
-- If CPOL is '0', the clock will be set to '0' when inactive, i.e., ordinary positive polarity.
CPHA : std_logic; -- sclk phase, i.e. when data is sampled and transmitted w.r.t. sclk.
-- If '0', sampling occurs on the first sclk edge and data is transmitted on the sclk active to idle state.
-- If '1', data is sampled on the second sclk edge and transmitted on sclk idle to active state.
spi_bit_time : time; -- Used in master for dictating sclk period
ss_n_to_sclk : time; -- Time from SS active until SCLK active
sclk_to_ss_n : time; -- Last SCLK until SS off
inter_word_delay : time; -- Minimum time between words, from ss_n inactive to ss_n active
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the SPI BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the SPI BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the SPI BFM
end record;
constant C_SPI_BFM_CONFIG_DEFAULT : t_spi_bfm_config := (
CPOL => '0',
CPHA => '0',
spi_bit_time => -1 ns, -- Make sure we notice if we forget to set bit time.
ss_n_to_sclk => 20 ns,
sclk_to_ss_n => 20 ns,
inter_word_delay => 0 ns,
match_strictness => MATCH_EXACT,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_spi_if_signals
------------------------------------------
-- - This function returns an SPI interface with initialized signals.
-- - master_mode = true:
-- - ss_n initialized to 'H'
-- - if config.CPOL = '1', sclk initialized to 'H',
-- otherwise sclk initialized to 'L'
-- - miso and mosi initialized to 'Z'
-- - master_mode = false:
-- - all signals initialized to 'Z'
function init_spi_if_signals (
constant config : in t_spi_bfm_config;
constant master_mode : in boolean := true
) return t_spi_if;
------------------------------------------
-- spi_master_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI slave DUT
-- and receives 'rx_data' from the SPI slave DUT.
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- spi_master_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI slave DUT
-- and receives 'rx_data' from the SPI slave DUT.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
-- Multi-word
procedure spi_master_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- spi_master_transmit_and_check
------------------------------------------
-- This procedure ...
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_transmit
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_receive
------------------------------------------
-- This procedure receives data 'rx_data' from the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_receive(
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_receive(
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_check
------------------------------------------
-- This procedure receives an SPI transaction, and compares the read data
-- to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_check(
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_check(
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI master DUT
-- and receives 'rx_data' from the SPI master DUT.
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- spi_slave_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI master DUT
-- and receives 'rx_data' from the SPI master DUT.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
-- Multi-word
procedure spi_slave_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- spi_slave_transmit_and_check
------------------------------------------
-- This procedure ...
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_transmit
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit (
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_transmit (
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_receive
------------------------------------------
-- This procedure receives data 'rx_data' from the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_receive (
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_receive (
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_check
------------------------------------------
-- This procedure receives an SPI transaction, and compares the read data
-- to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_check (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_check (
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
end package spi_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body spi_bfm_pkg is
---------------------------------------------------------------------------------
-- initialize spi to dut signals
---------------------------------------------------------------------------------
function init_spi_if_signals (
constant config : in t_spi_bfm_config;
constant master_mode : in boolean := true
) return t_spi_if is
variable result : t_spi_if;
begin
if master_mode then
result.ss_n := 'H';
if (config.CPOL) then
result.sclk := 'H';
else
result.sclk := 'L';
end if;
else
result.ss_n := 'Z';
result.sclk := 'Z';
end if;
result.mosi := 'Z';
result.miso := 'Z';
return result;
end function;
---------------------------------------------------------------------------------
-- spi_master_transmit_and_receive
--
-- alert if size of tx_data or rx_data doesn't
-- match with how long ss_n is kept low
---------------------------------------------------------------------------------
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant local_proc_name : string := "spi_master_transmit_and_receive";
constant local_proc_call : string := local_proc_name;
constant C_ACCESS_SIZE : integer := tx_data'length;
-- Helper variables
variable v_access_done : boolean := false;
variable v_tx_count : integer := 0;
variable v_tx_data : std_logic_vector(tx_data'length-1 downto 0) := tx_data;
variable v_rx_data : std_logic_vector(rx_data'length-1 downto 0) := (others => 'X');
variable v_rx_count : integer := 1;
variable v_proc_call : line;
variable v_multi_word_transfer_in_progress : boolean := false;
begin
-- check whether config.spi_bit_time was set
check_value(config.spi_bit_time /= -1 ns, TB_ERROR, "SPI Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'spi_master_transmit_and_receive...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing spi_master_transmit_and_receive...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- Detect if we have an ongoing multi-word transfer
if ss_n = '0' then
v_multi_word_transfer_in_progress := true;
end if;
sclk <= config.CPOL;
ss_n <= '0';
wait for 0 ns; -- wait a delta cycle
if ss_n = '0' then
-- set MOSI together with SS_N when CPHA=0
if not config.CPHA then
mosi <= v_tx_data(C_ACCESS_SIZE- v_tx_count - 1);
v_tx_count := v_tx_count + 1;
end if;
-- Decide delay before initial SCLK edge
if not v_multi_word_transfer_in_progress then
wait for config.ss_n_to_sclk;
else
wait for config.spi_bit_time/2;
end if;
sclk <= not config.CPOL;
-- serially shift out v_tx_data to mosi
-- serially shift in v_rx_data from miso
while ss_n = '0' and not v_access_done loop
if not config.CPHA then
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
mosi <= v_tx_data(C_ACCESS_SIZE-v_tx_count-1);
else -- config.CPHA
mosi <= v_tx_data(C_ACCESS_SIZE-v_tx_count-1);
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
end if;
if v_tx_count < C_ACCESS_SIZE-1 then -- Not done
v_rx_count := v_rx_count + 1;
v_tx_count := v_tx_count + 1;
wait for config.spi_bit_time/2;
sclk <= not config.CPOL;
else -- Final bit
if not config.CPHA then
v_rx_count := v_rx_count + 1;
-- Sample Last bit on the second to last edge of SCLK (CPOL=0: last rising. CPOL=1: last falling)
wait for config.spi_bit_time/2;
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
sclk <= not config.CPOL;
end if;
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
v_access_done := true;
end if;
end loop;
-- Clock the last bit
if not config.CPHA then
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
end if;
-- Determine if single- or multi-word transfer
if action_when_transfer_is_done = RELEASE_LINE_AFTER_TRANSFER then
wait for config.sclk_to_ss_n;
mosi <= 'Z';
ss_n <= '1';
wait for config.inter_word_delay;
else -- action_when_transfer_is_done = HOLD_LINE_AFTER_TRANSFER
ss_n <= '0';
end if;
wait for 0 ns; -- delta cycle
if (v_tx_count /= C_ACCESS_SIZE-1) or (v_rx_count /= C_ACCESS_SIZE) then
alert(note, " v_tx_count /= C_ACCESS_SIZE-1 or v_rx_count /= C_ACCESS_SIZE then");
alert(note, to_string(v_tx_count) & " /= " & to_string(C_ACCESS_SIZE-1) & " or" &to_string(v_rx_count) & " /= " & to_string(C_ACCESS_SIZE));
alert(note, local_proc_name & " ss_n not kept low for v_tx_data size duration");
else
rx_data := v_rx_data;
end if;
else
alert(error, local_proc_name & " ss_n not low when expected.");
end if;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> Transmitted: " & to_string(v_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". Received: " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. spi_master_transmit_and_check)
end if;
DEALLOCATE(v_proc_call);
end procedure;
-- Single-word
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
begin
spi_master_transmit_and_receive(tx_data, rx_data, msg,
spi_if.sclk, spi_if.ss_n, spi_if.mosi, spi_if.miso,
action_when_transfer_is_done, scope, msg_id_panel, config, ext_proc_call);
end procedure;
-- Multi-word
procedure spi_master_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
-- Check length of tx_data and rx_data
if tx_data'length /= rx_data'length then
alert(error, ext_proc_call & " tx_data and rx_data have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit_and_receive(tx_data(idx), rx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config, ext_proc_call);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_transmit_and_check
---------------------------------------------------------------------------------
procedure spi_master_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit_and_check";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean := true;
variable v_alert_radix : t_radix;
begin
spi_master_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
for i in data_exp'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if data_exp(i) = '-' or check_value(v_rx_data(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, local_proc_call & "=> Failed. Was " & to_string(v_rx_data, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_master_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit_and_check";
constant local_proc_call : string := local_proc_name;
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
-- Check length of tx_data and data_exp
if tx_data'length /= data_exp'length then
alert(error, local_proc_call & " tx_data and data_exp have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit_and_check(tx_data(idx), data_exp(idx), msg, spi_if, alert_level, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_transmit
---------------------------------------------------------------------------------
procedure spi_master_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_rx_data : std_logic_vector(tx_data'length - 1 downto 0);
begin
spi_master_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_master_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit(tx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_receive
---------------------------------------------------------------------------------
procedure spi_master_receive(
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_receive";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_tx_data : std_logic_vector(rx_data'length - 1 downto 0) := (others => '0');
begin
spi_master_transmit_and_receive(v_tx_data, rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_master_receive(
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (rx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < rx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < rx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_receive(rx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_check
---------------------------------------------------------------------------------
procedure spi_master_check(
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_check";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_tx_data : std_logic_vector(data_exp'length - 1 downto 0) := (others => '0');
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean := true;
variable v_alert_radix : t_radix;
begin
spi_master_transmit_and_receive(v_tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
for i in data_exp'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if data_exp(i) = '-' or check_value(v_rx_data(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, local_proc_call & "=> Failed. Was " & to_string(v_rx_data, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_master_check(
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (data_exp'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < data_exp'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < data_exp'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_check(data_exp(idx), msg, spi_if, alert_level, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_slave_transmit_and_receive
--
---------------------------------------------------------------------------------
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
-- Local_proc_name/call used if called from sequencer or VVC
constant local_proc_name : string := "spi_slave_transmit_and_receive";
constant local_proc_call : string := local_proc_name;
constant C_ACCESS_SIZE : integer := rx_data'length;
-- Helper variables
variable v_rx_data : std_logic_vector(rx_data'range) := (others => 'X');
variable bfm_tx_data : std_logic_vector(tx_data'length-1 downto 0) := tx_data;
variable v_access_done : boolean := false;
variable v_tx_count : integer := 0;
variable v_rx_count : integer := 1;
variable v_proc_call : line;
begin
-- check whether config.spi_bit_time was set
check_value(config.spi_bit_time /= -1 ns, TB_ERROR, "SPI Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'spi_slave_transmit_and_receive...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing spi_slave_transmit_and_receive...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- Await for master to drive SS_N and SCLK
if (ss_n /= '0') then -- master not acvtive
wait until (ss_n = '0');
elsif (ss_n = '0') then -- master active
case when_to_start_transfer is
when START_TRANSFER_ON_NEXT_SS =>
if (ss_n = '0') and (ss_n'last_active > 0 ns) then
wait until (ss_n = '0') and (ss_n'last_active <= 0 ns);
end if;
when others => -- START_TRANSFER_IMMEDIATE
null;
end case;
end if;
if ss_n = '0' then
-- set MISO together with SS_N when CPHA=0
if not config.CPHA then
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
v_tx_count := v_tx_count + 1;
end if;
-- Await first clock edge
if sclk = config.CPOL then
wait until sclk = not(config.CPOL);
end if;
-- Receive bits
while (ss_n = '0') and not(v_access_done) loop
if not config.CPHA then
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
wait until sclk'event and sclk = config.CPOL;
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
else -- config.CPHA
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
wait until sclk'event and sclk = config.CPOL;
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
end if;
if (v_tx_count < (C_ACCESS_SIZE-1)) and (v_rx_count < C_ACCESS_SIZE) then
wait until sclk'event and sclk = not(config.CPOL);
v_tx_count := v_tx_count + 1;
v_rx_count := v_rx_count + 1;
else
if not config.CPHA then
wait until sclk'event and sclk = not(config.CPOL);
end if;
v_access_done := true;
end if;
end loop;
end if;
-- Sample last bit
if not config.CPHA then
v_rx_count := v_rx_count + 1;
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
wait until sclk'event and sclk = config.CPOL;
end if;
if (v_tx_count < C_ACCESS_SIZE-1) then
alert(error, v_proc_call.all & " ss_n not kept active for tx_data size duration " & add_msg_delimiter(msg), scope);
elsif (v_rx_count < C_ACCESS_SIZE) then
alert(error, v_proc_call.all & " ss_n not kept active for rx_data size duration " & add_msg_delimiter(msg), scope);
else
rx_data := v_rx_data;
end if;
-- Await for master to finish
wait until (mosi = 'Z')
for config.ss_n_to_sclk;
miso <= 'Z';
if ext_proc_call = "" then
log(config.id_for_bfm, local_proc_call & "=> " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " rx completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
log(config.id_for_bfm, local_proc_call & "=> " & to_string(bfm_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " tx completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. spi_master_transmit_and_check)
end if;
DEALLOCATE(v_proc_call);
end procedure;
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
begin
spi_slave_transmit_and_receive(tx_data, rx_data, msg,
spi_if.sclk, spi_if.ss_n, spi_if.mosi, spi_if.miso,
when_to_start_transfer, scope, msg_id_panel, config, ext_proc_call);
end procedure;
-- Multi-word
procedure spi_slave_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
begin
-- Check length of tx_data and rx_data
if tx_data'length /= rx_data'length then
alert(error, ext_proc_call & "tx_data and rx_data have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
spi_slave_transmit_and_receive(tx_data(idx), rx_data(idx), msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, ext_proc_call);
end loop;
end procedure;
------------------------------------------
-- spi_slave_transmit_and_check
------------------------------------------
procedure spi_slave_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit_and_check";
constant local_proc_call : string := local_proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean := true;
variable v_alert_radix : t_radix;
begin
spi_slave_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
for i in data_exp'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if data_exp(i) = '-' or check_value(v_rx_data(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, local_proc_call & "=> Failed. Was " & to_string(v_rx_data, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end;
-- Multi-word
procedure spi_slave_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant loc_proc_call : string := "spi_slave_transmit_and_check"; -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
begin
-- Check length of tx_data and rx_data
if tx_data'length /= data_exp'length then
alert(error, loc_proc_call & " tx_data and data_exp have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
-- call single-word procedure - will handle error checking
spi_slave_transmit_and_check(tx_data(idx), data_exp(idx), msg, spi_if, alert_level, when_to_start_transfer, scope, msg_id_panel, config);
end loop;
end;
---------------------------------------------------------------------------------
-- spi_slave_transmit
---------------------------------------------------------------------------------
procedure spi_slave_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit";
constant local_proc_call : string := local_proc_name & "(" & to_string(tx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(tx_data'length-1 downto 0); -- := (others => '0');
begin
spi_slave_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_slave_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit";
constant local_proc_call : string := local_proc_name & "(" & to_string(tx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_tx_data : t_slv_array(tx_data'length-1 downto 0)(tx_data(0)'length-1 downto 0) := (others => (others => '0'));
begin
-- call multi-word procedure
spi_slave_transmit_and_receive(tx_data, v_tx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end procedure;
---------------------------------------------------------------------------------
-- spi_slave_receive
---------------------------------------------------------------------------------
procedure spi_slave_receive (
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_receive";
constant local_proc_call : string := local_proc_name & "(" & to_string(rx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_tx_data : std_logic_vector(rx_data'length-1 downto 0) := (others => '0');
begin
spi_slave_transmit_and_receive(v_tx_data, rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end;
-- Multi-word
procedure spi_slave_receive (
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_receive";
constant local_proc_call : string := local_proc_name & "(" & to_string(rx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : t_slv_array(rx_data'length-1 downto 0)(rx_data(0)'length-1 downto 0) := (others => (others => '0'));
begin
-- call multi-word procedure
spi_slave_transmit_and_receive(v_rx_data, rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end;
---------------------------------------------------------------------------------
-- spi_slave_check
---------------------------------------------------------------------------------
procedure spi_slave_check (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_check";
constant local_proc_call : string := local_proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0) := (others => 'X');
variable v_tx_data : std_logic_vector(data_exp'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean := true;
variable v_alert_radix : t_radix;
begin
spi_slave_transmit_and_receive(v_tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
for i in data_exp'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if data_exp(i) = '-' or check_value(v_rx_data(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, local_proc_call & "=> Failed. Was " & to_string(v_rx_data, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_slave_check (
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
begin
for idx in 0 to (data_exp'length-1) loop
-- call singl-word procedure - will handle error check
spi_slave_check(data_exp(idx), msg, spi_if, alert_level, when_to_start_transfer, scope, msg_id_panel, config);
end loop;
end procedure;
end package body spi_bfm_pkg;
| mit |
UVVM/UVVM_All | bitvis_vip_ethernet/src/ethernet_tx_vvc.vhd | 1 | 20078 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_hvvc_to_vvc_bridge;
use work.support_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.transaction_pkg.all;
--==========================================================================================
entity ethernet_tx_vvc is
generic(
GC_INSTANCE_IDX : natural;
GC_CHANNEL : t_channel;
GC_PHY_INTERFACE : t_interface;
GC_PHY_VVC_INSTANCE_IDX : natural;
GC_PHY_MAX_ACCESS_TIME : time := 1 us;
GC_DUT_IF_FIELD_CONFIG : t_dut_if_field_config_direction_array := C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY_DEFAULT;
GC_ETHERNET_PROTOCOL_CONFIG : t_ethernet_protocol_config := C_ETHERNET_PROTOCOL_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
end entity ethernet_tx_vvc;
--==========================================================================================
--==========================================================================================
architecture behave of ethernet_tx_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, GC_CHANNEL);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
signal hvvc_to_bridge : t_hvvc_to_bridge(data_words(0 to C_MAX_PACKET_LENGTH-1)(7 downto 0));
signal bridge_to_hvvc : t_bridge_to_hvvc(data_words(0 to C_MAX_PACKET_LENGTH-1)(7 downto 0));
-- Instantiation of the element dedicated executor
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_ethernet_vvc_config(GC_CHANNEL, GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_ethernet_vvc_status(GC_CHANNEL, GC_INSTANCE_IDX);
-- Transaction info
alias vvc_transaction_info_trigger : std_logic is global_ethernet_vvc_transaction_trigger(GC_CHANNEL, GC_INSTANCE_IDX);
alias vvc_transaction_info : t_transaction_group is shared_ethernet_vvc_transaction_info(GC_CHANNEL, GC_INSTANCE_IDX);
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
begin
--==========================================================================================
-- HVVC-to-VVC Bridge
-- Choose the correct architecture with the generic GC_PHY_INTERFACE
--==========================================================================================
gen_hvvc_bridge : if GC_PHY_INTERFACE = GMII generate
i_hvvc_to_vvc_bridge : entity bitvis_vip_hvvc_to_vvc_bridge.hvvc_to_vvc_bridge(GMII)
generic map(
GC_INSTANCE_IDX => GC_PHY_VVC_INSTANCE_IDX,
GC_DUT_IF_FIELD_CONFIG => GC_DUT_IF_FIELD_CONFIG,
GC_MAX_NUM_WORDS => C_MAX_PACKET_LENGTH,
GC_PHY_MAX_ACCESS_TIME => GC_PHY_MAX_ACCESS_TIME,
GC_SCOPE => C_SCOPE
)
port map(
hvvc_to_bridge => hvvc_to_bridge,
bridge_to_hvvc => bridge_to_hvvc
);
elsif GC_PHY_INTERFACE = SBI generate
i_hvvc_to_vvc_bridge : entity bitvis_vip_hvvc_to_vvc_bridge.hvvc_to_vvc_bridge(SBI)
generic map(
GC_INSTANCE_IDX => GC_PHY_VVC_INSTANCE_IDX,
GC_DUT_IF_FIELD_CONFIG => GC_DUT_IF_FIELD_CONFIG,
GC_MAX_NUM_WORDS => C_MAX_PACKET_LENGTH,
GC_PHY_MAX_ACCESS_TIME => GC_PHY_MAX_ACCESS_TIME,
GC_SCOPE => C_SCOPE
)
port map(
hvvc_to_bridge => hvvc_to_bridge,
bridge_to_hvvc => bridge_to_hvvc
);
else generate
alert(TB_FAILURE, "Unsupported interface");
end generate gen_hvvc_bridge;
--==========================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--==========================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_ETHERNET_PROTOCOL_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--==========================================================================================
--==========================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--==========================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(GC_CHANNEL, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc(name => C_VVC_NAME,
channel => GC_CHANNEL,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- Update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(GC_CHANNEL, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the executor if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
-- Await completion of all commands in the cmd_executor executor
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd, executor_is_busy);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--==========================================================================================
--==========================================================================================
-- Command executor
-- - Fetch and execute the commands
--==========================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = TRANSMIT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when TRANSMIT =>
-- Set vvc_transaction_info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the vvc_methods_pkg.
priv_ethernet_transmit_to_bridge(interpacket_gap_time => vvc_config.bfm_config.interpacket_gap_time,
vvc_cmd => v_cmd,
hvvc_to_bridge => hvvc_to_bridge,
dut_if_field_config => GC_DUT_IF_FIELD_CONFIG(TRANSMIT),
bridge_to_hvvc => bridge_to_hvvc,
vvc_transaction_info => vvc_transaction_info,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
--<USER_INPUT> Uncomment if BFM has clock_period config
-- check_value(vvc_config.bfm_config.clock_period > -1 ns, TB_ERROR, "Check that clock_period is configured when using insert_delay().",
-- C_SCOPE, ID_NEVER, v_msg_id_panel);
-- wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Set VVC Transaction Info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--==========================================================================================
--==========================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--==========================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--==========================================================================================
end behave; | mit |
UVVM/UVVM_All | bitvis_vip_uart/src/vvc_methods_pkg.vhd | 1 | 27860 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
use work.uart_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.monitor_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
constant C_VVC_NAME : string := "UART_VVC";
constant C_EXECUTOR_RESULT_ARRAY_DEPTH : natural := 3;
signal UART_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is UART_VVCT;
alias t_bfm_config is t_uart_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_UART_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_error_injection is record
parity_bit_error_prob : real;
stop_bit_error_prob : real;
end record t_vvc_error_injection;
constant C_VVC_ERROR_INJECTION_INACTIVE : t_vvc_error_injection := (
parity_bit_error_prob => -1.0,
stop_bit_error_prob => -1.0
);
type t_bit_rate_checker is record
enable : boolean;
min_period : time;
alert_level: t_alert_level;
end record;
constant C_BIT_RATE_CHECKER_DEFAULT : t_bit_rate_checker := (
enable => FALSE,
min_period => -1 ns,
alert_level=> WARNING
);
type t_vvc_config is record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_uart_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
error_injection : t_vvc_error_injection;
bit_rate_checker : t_bit_rate_checker;
parent_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
end record;
type t_vvc_config_array is array (t_channel range <>, natural range <>) of t_vvc_config;
constant C_UART_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_UART_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, -- from adaptation package
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_UART_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT,
error_injection => C_VVC_ERROR_INJECTION_INACTIVE,
bit_rate_checker => C_BIT_RATE_CHECKER_DEFAULT,
parent_msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (t_channel range <>, natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information to include in the wave view during simulation
type t_transaction_info is record
operation : t_operation;
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (t_channel range <>, natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
data => (others => '0'),
msg => (others => ' ')
);
shared variable shared_uart_vvc_config : t_vvc_config_array(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => C_UART_VVC_CONFIG_DEFAULT));
shared variable shared_uart_vvc_status : t_vvc_status_array(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => C_VVC_STATUS_DEFAULT));
shared variable shared_uart_transaction_info : t_transaction_info_array(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => C_TRANSACTION_INFO_DEFAULT));
-- Scoreboard
package uart_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg
generic map (t_element => std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0),
element_match => std_match,
to_string_element => to_string);
use uart_sb_pkg.all;
shared variable UART_VVC_SB : uart_sb_pkg.t_generic_sb;
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
procedure uart_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure uart_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant num_words : in natural;
constant randomisation : in t_randomisation;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure uart_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data_routing : in t_data_routing;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure uart_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure uart_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data : in std_logic_vector;
constant msg : in string;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT);
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record);
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME);
--==============================================================================
-- Error Injection methods
--==============================================================================
procedure determine_error_injection(
constant probability : in real;
variable bfm_configured_error_injection_setting : inout boolean;
variable has_raised_warning_if_vvc_bfm_conflict : inout boolean;
constant scope : in string
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
procedure uart_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx, channel) -- First part common for all
& ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, channel, proc_call, msg, QUEUED, TRANSMIT);
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure uart_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant num_words : in natural;
constant randomisation : in t_randomisation;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx, channel) -- First part common for all
& ", RANDOM)";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, channel, proc_call, msg, QUEUED, TRANSMIT);
-- Randomisation specific
shared_vvc_cmd.randomisation := randomisation;
shared_vvc_cmd.num_words := num_words;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure uart_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data_routing : in t_data_routing;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx, channel) -- First part common for all
& ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, channel, proc_call, msg, QUEUED, RECEIVE);
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure uart_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
uart_receive(VVCT, vvc_instance_idx, channel, NA, msg, alert_level, scope, parent_msg_id_panel);
end procedure;
procedure uart_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data : in std_logic_vector;
constant msg : in string;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx, channel) -- First part common for all
& ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, channel, proc_call, msg, QUEUED, EXPECT);
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.max_receptions := max_receptions;
if timeout = -1 ns then
shared_vvc_cmd.timeout := shared_uart_vvc_config(RX, vvc_instance_idx).bfm_config.timeout;
else
shared_vvc_cmd.timeout := timeout;
end if;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT) is
begin
case vvc_cmd.operation is
when TRANSMIT | RECEIVE | EXPECT =>
vvc_transaction_info_group.bt.operation := vvc_cmd.operation;
vvc_transaction_info_group.bt.data(vvc_cmd.data'length-1 downto 0) := vvc_cmd.data;
vvc_transaction_info_group.bt.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.bt.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.bt.transaction_status := IN_PROGRESS;
vvc_transaction_info_group.bt.error_info.parity_bit_error := false;
vvc_transaction_info_group.bt.error_info.stop_bit_error := false;
if vvc_cmd.operation = TRANSMIT then
vvc_transaction_info_group.bt.error_info.parity_bit_error := vvc_config.bfm_config.error_injection.parity_bit_error;
vvc_transaction_info_group.bt.error_info.stop_bit_error := vvc_config.bfm_config.error_injection.stop_bit_error;
end if;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
when others =>
alert(TB_ERROR, "VVC operation not recognized");
end case;
wait for 0 ns;
end procedure set_global_vvc_transaction_info;
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record) is
begin
case vvc_cmd.operation is
when TRANSMIT | RECEIVE | EXPECT =>
vvc_transaction_info_group.bt := C_BASE_TRANSACTION_SET_DEFAULT;
when others =>
null;
end case;
wait for 0 ns;
end procedure reset_vvc_transaction_info;
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME) is
variable v_activity : t_activity := activity;
begin
-- Update vvc_status after a command has finished (during same delta cycle the activity register is updated)
if activity = INACTIVE then
vvc_status.previous_cmd_idx := last_cmd_idx_executed;
vvc_status.current_cmd_idx := 0;
end if;
if v_activity = INACTIVE and not(command_queue_is_empty) then
v_activity := ACTIVE;
end if;
shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register,
activity => v_activity,
last_cmd_idx_executed => last_cmd_idx_executed);
if global_trigger_vvc_activity_register /= 'L' then
wait until global_trigger_vvc_activity_register = 'L';
end if;
gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER);
end procedure;
--==============================================================================
-- Error Injection methods
--==============================================================================
procedure determine_error_injection(
constant probability : in real;
variable bfm_configured_error_injection_setting : inout boolean;
variable has_raised_warning_if_vvc_bfm_conflict : inout boolean;
constant scope : in string
) is
begin
if probability /= -1.0 then
check_value_in_range(probability, 0.0, 1.0, tb_error, "Verify probability value within range 0.0 - 1.0.", scope, ID_NEVER);
-- Raise a TB_WARNING only once if there is a conflict between VVC and BFM setting
if not(has_raised_warning_if_vvc_bfm_conflict) and bfm_configured_error_injection_setting and probability < 1.0 then
alert(TB_WARNING, "VVC error injection probability will override BFM configuration.", scope);
has_raised_warning_if_vvc_bfm_conflict := true;
end if;
bfm_configured_error_injection_setting := (random(0.0, 1.0) <= probability);
end if;
end procedure determine_error_injection;
end package body vvc_methods_pkg;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_strb_gen2.vhd | 18 | 101757 | -------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
| mit |
UVVM/UVVM_All | bitvis_vip_avalon_mm/src/avalon_mm_vvc.vhd | 1 | 38023 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.C_SB_CONFIG_DEFAULT;
use work.avalon_mm_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
entity avalon_mm_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8; -- Avalon MM address bus
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32; -- Avalon MM data bus
GC_INSTANCE_IDX : natural := 1; -- Instance index for this AVALON_MM_VVCT instance
GC_AVALON_MM_CONFIG : t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
avalon_mm_vvc_master_if : inout t_avalon_mm_if := init_avalon_mm_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (avalon_mm_vvc_master_if.address'length = GC_ADDR_WIDTH) report "avalon_mm_vvc_master_if.address'length /= GC_ADDR_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.writedata'length = GC_DATA_WIDTH) report "avalon_mm_vvc_master_if.writedata'length /= GC_DATA_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.readdata'length = GC_DATA_WIDTH) report "avalon_mm_vvc_master_if.readdata'length /= GC_DATA_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.byte_enable'length = GC_DATA_WIDTH/8) report "avalon_mm_vvc_master_if.byte_enable'length /= GC_DATA_WIDTH/8" severity failure;
end entity avalon_mm_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of avalon_mm_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal vvc_is_active : boolean := false;
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal read_response_is_busy : boolean := false;
signal response_queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal last_read_response_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of element dedicated Queues
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable command_response_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_avalon_mm_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_avalon_mm_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_avalon_mm_transaction_info(GC_INSTANCE_IDX);
-- Transaction info
alias vvc_transaction_info_trigger : std_logic is global_avalon_mm_vvc_transaction_trigger(GC_INSTANCE_IDX);
alias vvc_transaction_info : t_transaction_group is shared_avalon_mm_vvc_transaction_info(GC_INSTANCE_IDX);
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
-- Propagation delayed interface signal used when reading data from the slave in the read_response process.
signal avalon_mm_vvc_master_if_pd : t_avalon_mm_if(address(GC_ADDR_WIDTH-1 downto 0),
byte_enable((GC_DATA_WIDTH/8)-1 downto 0),
writedata(GC_DATA_WIDTH-1 downto 0),
readdata(GC_DATA_WIDTH-1 downto 0)) := avalon_mm_vvc_master_if;
--UVVM: temporary fix for HVVC, remove function below in v3.0
function get_msg_id_panel(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config
) return t_msg_id_panel is
begin
-- If the parent_msg_id_panel is set then use it,
-- otherwise use the VVCs msg_id_panel from its config.
if command.msg(1 to 5) = "HVVC:" then
return vvc_config.parent_msg_id_panel;
else
return vvc_config.msg_id_panel;
end if;
end function;
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AVALON_MM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
variable v_temp_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc( name => C_VVC_NAME,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
--UVVM: temporary fix for HVVC, remove two lines below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
v_temp_msg_id_panel := vvc_config.msg_id_panel;
vvc_config.msg_id_panel := v_msg_id_panel;
end if;
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
-- Await completion of all commands in the cmd_executor queue
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed,ID_IMMEDIATE_CMD_WAIT,ID_NEVER);
-- Await completion of all commands in the read_response queue
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_response_queue, vvc_config, read_response_is_busy, C_VVC_LABELS, last_read_response_idx_executed, ID_NEVER, ID_IMMEDIATE_CMD);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
--UVVM: temporary fix for HVVC, remove line below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
vvc_config.msg_id_panel := v_temp_msg_id_panel;
end if;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands.
-- - Note that the read response is handled in the read_response process.
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_msg_id_panel : t_msg_id_panel;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_byte_ena : std_logic_vector((GC_DATA_WIDTH/8)-1 downto 0) := (others => '0');
variable v_cmd_queues_are_empty : boolean;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Setup Avalon MM scoreboard
AVALON_MM_VVC_SB.set_scope("AVALON_MM_VVC_SB");
AVALON_MM_VVC_SB.enable(GC_INSTANCE_IDX, "AVALON_MM VVC SB Enabled");
AVALON_MM_VVC_SB.config(GC_INSTANCE_IDX, C_SB_CONFIG_DEFAULT);
AVALON_MM_VVC_SB.enable_log_msg(GC_INSTANCE_IDX, ID_DATA);
loop
-- update vvc activity
v_cmd_queues_are_empty := (command_queue.is_empty(VOID) and command_response_queue.is_empty(VOID));
if not(read_response_is_busy) and v_cmd_queues_are_empty then
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, v_cmd_queues_are_empty, C_SCOPE);
end if;
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity
v_cmd_queues_are_empty := (command_queue.is_empty(VOID) and command_response_queue.is_empty(VOID));
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, v_cmd_queues_are_empty, C_SCOPE);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for insert_bfm_delay
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK or v_cmd.operation = RESET then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
msg_id_panel => v_msg_id_panel,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_write() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "avalon_mm_write() called with to wide data. " & v_cmd.msg);
if (v_cmd.byte_enable = (0 to v_cmd.byte_enable'length-1 => '1')) then
v_normalised_byte_ena := (others => '1');
else
v_normalised_byte_ena := normalize_and_check(v_cmd.byte_enable, v_normalised_byte_ena, ALLOW_WIDER_NARROWER, "v_cmd.byte_enable", "v_normalised_byte_ena", "avalon_mm_write() called with to wide byte_enable. " & v_cmd.msg);
end if;
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
transaction_info.byte_enable((GC_DATA_WIDTH/8) - 1 downto 0) := v_cmd.byte_enable((GC_DATA_WIDTH/8) - 1 downto 0);
-- Call the corresponding procedure in the BFM package.
avalon_mm_write(addr_value => v_normalised_addr,
data_value => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
byte_enable => v_cmd.byte_enable((GC_DATA_WIDTH/8)-1 downto 0),
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
when READ =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_read() called with to wide address. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
if vvc_config.use_read_pipeline then
-- Stall until response command queue is no longer full
while command_response_queue.get_count(VOID) > vvc_config.num_pipeline_stages loop
wait for vvc_config.bfm_config.clock_period;
end loop;
avalon_mm_read_request( addr_value => v_normalised_addr,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, command_response_queue, vvc_status, response_queue_is_increasing);
else
avalon_mm_read( addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
AVALON_MM_VVC_SB.check_received(GC_INSTANCE_IDX, pad_avalon_mm_sb(v_read_data(GC_DATA_WIDTH-1 downto 0)));
else
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data );
end if;
end if;
when CHECK =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_check() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "avalon_mm_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
if vvc_config.use_read_pipeline then
-- Wait until response command queue is no longer full
while command_response_queue.get_count(VOID) > vvc_config.num_pipeline_stages loop
wait for vvc_config.bfm_config.clock_period;
end loop;
avalon_mm_read_request( addr_value => v_normalised_addr,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config,
ext_proc_call => "avalon_mm_check(A:" & to_string(v_normalised_addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(v_normalised_data, HEX, AS_IS, INCL_RADIX) & ")"
);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, command_response_queue, vvc_status, response_queue_is_increasing);
else
avalon_mm_check(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
end if;
when RESET =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
avalon_mm_reset(clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
num_rst_cycles => v_cmd.gen_integer_array(0),
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
when LOCK =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
avalon_mm_lock( avalon_mm_if => avalon_mm_vvc_master_if,
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
when UNLOCK =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
avalon_mm_unlock( avalon_mm_if => avalon_mm_vvc_master_if,
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
check_value(vvc_config.bfm_config.clock_period > -1 ns, TB_ERROR, "Check that clock_period is configured when using insert_delay().",
C_SCOPE, ID_NEVER, v_msg_id_panel);
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
-- Set VVC Transaction Info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Add a delta cycle to the read response interface signals to avoid reading wrong data.
--===============================================================================================
avalon_mm_vvc_master_if_pd <= transport avalon_mm_vvc_master_if after std.env.resolution_limit;
--===============================================================================================
-- Read response command execution.
-- - READ (and CHECK) data received from the slave after the command executor has issued an
-- read request (or check).
-- - Note the use of propagation delayed avalon_mm_vv_master_if signal
--===============================================================================================
read_response : process
variable v_cmd : t_vvc_cmd_record;
variable v_msg_id_panel : t_msg_id_panel;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
-- check if command_queue and command_response_queue is empty
variable v_cmd_queues_are_empty : boolean;
begin
-- Set the command response queue up to the same settings as the command queue
command_response_queue.set_scope(C_SCOPE & ":RQ");
command_response_queue.set_queue_count_max(vvc_config.cmd_queue_count_max);
command_response_queue.set_queue_count_threshold(vvc_config.cmd_queue_count_threshold);
command_response_queue.set_queue_count_threshold_severity(vvc_config.cmd_queue_count_threshold_severity);
-- Wait until VVC is registered in vvc activity register in the interpreter
wait until entry_num_in_vvc_activity_register >= 0;
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- update vvc activity
v_cmd_queues_are_empty := command_queue.is_empty(VOID) and command_response_queue.is_empty(VOID);
if not(executor_is_busy) and v_cmd_queues_are_empty then
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, v_cmd_queues_are_empty, C_SCOPE);
end if;
-- Fetch commands
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_response_queue, vvc_config, vvc_status, response_queue_is_increasing, read_response_is_busy, C_VVC_LABELS);
---- response executor follows executor, thus VVC activity is already set to ACTIVE
--v_cmd_queues_are_empty := (command_queue.is_empty(VOID) and command_response_queue.is_empty(VOID));
--update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, v_cmd_queues_are_empty, C_SCOPE);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "Function called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "Function called with to wide data. " & v_cmd.msg);
case v_cmd.operation is
when READ =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Initiate read response
avalon_mm_read_response(addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if_pd,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
AVALON_MM_VVC_SB.check_received(GC_INSTANCE_IDX, pad_avalon_mm_sb(v_read_data(GC_DATA_WIDTH-1 downto 0)));
else
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
end if;
when CHECK =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Initiate check response
avalon_mm_check_response( addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if_pd,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
last_read_response_idx_executed <= v_cmd.cmd_idx;
-- Set vvc transaction info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_slice.vhd | 19 | 4781 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_noqueue.vhd | 3 | 30514 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
| mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_pc_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 24 | 19921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
XWrzYjpTpUuus//3Yqipm0uESgOiNKQ8VQh6ZdiO7zAhk4piHKnqwa/2EKkH2x6OH6UJ3gXKq5/H
re5lJuG43w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I/mVU8dDhiD84VpApZ3BHEAFwc8ScdU1t9VBFtvay6KT8PQqngzpdxcgzAY0oIKkn+v6vjos+Vid
wD+8ZToTkz2FZXJPO3eRQevGvf5hRJLnUIO2/ZJWF1oujViMdIgwOogfnidehakdpP9Dgg9TjQgp
v0EFW47TFj3bwlWawDY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
enarOZZRqLSdokx00l/yrdbwVHZE+iAGChN3X8+ai4tHQi6+FKLUSim9B5GEcPwYS2mLkPj8A9rQ
5+AJ1kr2tDdusvxAzB/shFvbBXROK4gidDLQeNupO6hIO7r5vzS3kcAOkJO2aDc55fp7hixh/JA0
B5ocr008Ek+2uBgUbygMG2FCfD0pFWjISb/tg1djhmIcAFZG9kmWWc0s+zoo/kTSUd4KkXr/QOkH
ic6q2IKhR1zbYLDZIyB9OwtYBKnmV3gKLNz4lRCqnLkfHbIMkYgdIsFcnEpJiDoMsvseR01+aCP6
GWfqzKUs5VqB3KCuOzf8E3dscBl39FrAil+mPQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NInC2wOqMP8qjRIT3rC43wHF+spQmp4lMdNpY71XGeTlX0lnj6wSc7IAQCUvEwCsoD8M4lwDIyQW
CEJUES1QCK6RSSvTwvVQeBA4AxEIpaskNQxhoCUW/G4HQJtkJNx3CEIEt169GwQJQGnHhDLxfGpS
u+cWPD37eOsIEPKPYDo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
n/eBV2B/I1aWzlinjPqs0AiVgEgxpVbGxbjLwPCaCuUjlRKvVii71Q//M8LWbnOjtRJh3iBV/FEx
4T5nzpDhXZdqlODnIgqEMa5jCYIjAB6EeS4jPxVGSA7iEqNBDhWlHG3rpa4eNPN3yBK1pHMbI7UP
Hji9wZRyEtGGFw5B11hN9vtAkMO2LkpNTGpgjYHkEwC52hYlYduDhCuZ3vjF8T70md/6IndKHOYN
1iPNKTgSWMqyyRqam9ZwHLVb8pZEd1PWRleL/jtaee1nkct5RizJO5isCLalUXAmpwA5DzxRzVfm
6HIYn0aBOwtEePgf/knEux3ax3FfU2Xf9P4+rw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
VRl2IPSegGte2EEkvGTfMdA8J/7ljZkIqUO655TVXkaKszIQdAParUVE/q4nfRMUKm8EQmcEPW8r
Em7z7lcUd9yUjANQPGTUlEBraIe4wJwQOyyvvylIpotL3I6OpYXxNoSwtwFPJr04onHOlmvOGH1H
lzHTjBNJ9HKfj1Z4UGEA6/bDw7WC2Lw4Y5BhXLMY8u+1BZRV5DIW5OR41B5zr54DwrDuRpaQnY93
6AtfPSLcONqz+21Snh0NhQ7ycxPZ6Hz/af8HP7wS2lNHkOiLb6otttKwpt0M4WwwnGrB4iGZfsrA
YkbLwxaeo8WMaV5KVcg+tE51mTwMhIrd8ZTkGJ2TmlDobpXMZqeYogqIAY9s8qV+6zROdyUySyM+
YC0XDfCjgnirKkBajDHxdDGw5xGFpi8zPovHD1lDbyPDHE9RSDClGG1CIFOyQ5AZL4VM2LbaA6qK
CkSwhLy7jEqPrmMhyGNg3i8OKfVblnA0pazoX9TaXfqZPIlSCBoQyjTSIMq3YOwTNFQt2Knh3bA7
z1C/Xkp+Krd6zVrropiFDGxkMybRQTB/Q8niI/5ztwZsH/9V3MHV2QcbkAd54y1GMItBwxKz8wcF
Q47VJWqErHkdfDDEobskd06MEpmw4cmN7pQSrsFNMM9z7yXDASul1+DLnXM9CbjbX6zc4tSUiXiN
yNVXCrN1mtbwbRX+UsLxhpHnuKIa5h4sOvX3YHqV8de0g6T2VwmROHWvPWkyo+kCfYbXHNbAzeSE
crA45b1bQ5OIksefv0jsIUhsa/ZOPHay0MuhxznN4d6LshQCznhNTr7LgeteOR62qvyE1gxOL3Qt
ptfsXMJSZpPVXUeP4qKKwSZDXfc+V6ALd1RY3tiSxRjlx37HT6D6LzavjeUsR82AIvLd3avFWIkf
Qu6hAwPdTxHtNNv5FEIxWJ5q331h3DjyCcwrlbERIl6/6cm7xFbgo0ddO2145sZUxTRnGvZ0Ii1s
jLDMz7pWA9G35BZ7xi8stvYSlQ2w91jR+XLkbeY7Wlc4yVGnLhi1gzT1RBbRzuM9c/3LO10YUrp0
Uz+xQN1vGIIWDVkT13Jfkef0otPz5xR3sdXQaTGSWJhAwC9nlwhckQXuPcK96tbl0rs9yxoqpH9I
eAKsFuc/JbndWuVgBer6IQoPu3/KJSa+cwnsIYt5xNrH1MKY2WJj4G8IMYFl+2RcxnkIp2GkoOeU
OFFncKFkLjdLnc17S3d8o+LjHy7rvCMuoBAB2gE5mrJvIsUOSUo2oqh4P2JvLABjRJ3EPXaLgFUK
pmYuN5rrlYWYbbmhLZqW040Lew1OWg6hEu8FFg4qLR47vpgtLYjUfbvQpqt+0l3DG12xqpJMcdwj
0tvpNS93RNQfDkytXPBG2hZQa6Mw5y8TxTcp+BpwJtedtQPbW214FcAT6fkDLANKG7NNXFCRlv/8
Nl2/1Mhq8u78MIifW2iz3ZrqXITdoZdtJT8DqfD+chLy0jjiw/vinXUBSl3u31O1ECd2WjVH9joM
hlvjU4cnx5CxuZpJ2b0Uo75DmJGhJXQST3drzo40KlVfOwkIiY2vkLr7U3GNiBCfRKgWjdzFd8aC
7rS+3H9LeY3SCwD8spPBTK94BRI/43iYFkblg+bWDGJxJOHjjocgGI6okosepRxbketf/xC3nsI9
QKX9vu3URW618M9KMbpADmufcgmddEudcSbbEtmQY+pt0FbPGTNNkr89mvww2HXj5HyU7z5R1T41
ln5a3KYRh93pia2/vpc0OstNSq8As63nRBeHabbzM766IIyFm4qanaH9k9uFz9ROaRIKOQKoUBhQ
nk/qGbspmWPmLpzbnlqIIMISU6e3DBsUkKmirKssj2NjIWr6BCf3zhI7HVLe7jQXmu8cwvZynb28
b4FWvLt5UdX0mIZS3NBVZYQ/p/8uIL+rJGq5HM6DtDh4ShTAbUsAz8fnZqlzqzyec0pxmY8e7mOA
hLV4YbScR9mCZF3qck5+6s6bdutZ+tQ/uacKwxYniorwGmhEHY8XLY1hCfAQHg2CtIHDWU7sRFtk
ghqbrEA8z0J5Sn9MXZgnNcnhm3/fSKgheU95Rp36ymss2RIjT8/Zz22drQViSzQlVtIV+TzQk6J3
6CrlLhH6iIJNFE3hb46lvPD7OzyWAbtlL7rZJ+5KWJhfsDkk77j6O/Geu6AE90MuTSvwNhUeTcUi
OEGeKS8WW/Duc09rT+wNBBT4Zsk30ll9/EJZpQbgP+r/2WYQlgn08YnhOQIOssuwS3DpsLqCLnRO
u6tyuZh0wfwVAmfwBbpc3M/hcQbOSq43zUUuZaFah0WPuBywBYYw7Gta6sM9KMP+UD8g89pbqfxd
6vCBNG4uKWH/4ZcXBdUT78/guPCu5gDikrY/SFL1KiFzE9uk9S3gzDZDzCY9+YRjWC2cs3PvSKR/
hDs+tQ0wt++h/DASmcoOfMcsaPG72aX7ZCIxr1RNASa5lreZo+6L00SIvF4u1ke+TD7NHfILliMJ
H2GCS1HGnd962HGibUBfLTPwiNLqwgUTPqvEE5DpeRTW67gqlYZyYiC+p0T5PgyZb4iYRGb/fCFr
lgcghTJLpk/FpicS1xP84Mqy5bxlO1OcqT/78Bqjf0a5IBhlEpshg51u8K2W+d4b56aioXlIT78U
iP+UcHTSzyVOHmflh6NgS+3nFrlHS4n53rSKBRvxONtjrY+PM8wUVlQjrxU/9EJbCJIaSQ7tuFA1
xHn9u+XrjtKoxGSl+X+GjQ+jVYMihxW+C53HN3NNZrfE6ItRbqofvtc4IyoqeyPskotyKNQcdMWE
27NLl9eKWPoL2DzqzgTnmqj7gdmnKV1iifm4e6OsiBzJNMzpX+ByU9zmHNu6KLFrrjhYWgMXP0T0
5URhaTRcD+XLR/27WzDbwO+SuOsbUBbfg4Pw+KS56SFaVsrj2HwSIyn9dXjebXf9FMry/toEOliK
2MTBanOAkSXIqvprL8rsUQp9GQekcaAT9YVfMalS479qPvgyp+i+q984A2wSpHBF9o4zYXMDQuAA
RagQC3j7cZcHANj19Hxb4lY9takJFWlXiqau4EeR0o0GmquBahSZeh3o3ob1z1L0aD0qk95y6HrL
9Iksxz/E19hlU+Vyylk9y5LPJdGY7brWPomZ/9zqFe+iZK/0Kb/QQ/zxL67QOyysWOJDGLU6mU8A
ibNNAS6x1yCgLE/ABXeM3LsUbKerPVQzzpGomus7MoD47GpjamjCDpvdPuaN9w8VPFEAmFkdM3jg
eu9e082hZQYRepLgQX7uWJb3BwxidNzgNUq1SmJU2FydC7seeyFFHkNCpJOtgGcU3SfiCDpjFwdo
xd0gFgzfVHylY4nUU9kMvtUoeNcZGgvjF9ke5lg8Nkd0Sv6/TbPNkQ+FQ3Kqw6533FLL7K6kBxTi
4DfiwNnojVh7/YmuSVmqGYj0QFRaHbjlpIEs561b2FxitX8cyYgoyA6NTZfhItntIJBIqGt00DhM
OclUr4X7RE/+ImNkF6fcbX+TqihvIAga6y7ndep9SJ/CeMRZ0IY2t9Uk5lolmRN5DxqS9oT+g2ns
XUs8Zf5JqAdPQoqB0t4K+MbgWIEZ8Tw4+HGqMLg2FiCZtNNfmk3wBVP/geklvUHBnKQNKkWsXnwz
1Zcx5SVqOAqAL7QJOaTkcKmtBA1/yQ529TIc88PW7isurljI2Fs2riSBic9FgPskFWGCe4pFxejo
KYxsy4MM+1nVuZTvm8znXHoatPLJZmZip9ZPn+uatyWwm6POihEjyztcMMfK8Zq3Be9GdBFdjPF4
MamDXb9h5riN4zf5XV3OotgUhq9nTn2IJOBpD716SH5UJuEV1GHj98vo2VSLi6HQ9c5EO5a2IW42
mCA+RzL7SrtqSll2Yy+2j7MdY3LC2ze86LU86I3E26zl+Ii+zRNRDKvjQbYI6Xpg2EAM2C0Ls9x9
1V6zl/64J5yBERYYmyOcxk46TStZwJGaD0AbZ+PxerDaffa0sOEI5h1NUX4ohwBwhcNvnfENSAMS
ZRdXuiKOJ6Lj3i5DJWyP8WE9FEDV5FJSbgNmzPvQu2gc1jOQQV+dJKx5v9HMGhU3cfeeryblEHx6
BCMNV4+5pgP1VfpF5sZADOkL1divXnJGZSzjRxH1lxY91zOMgy6I/qVVPpMymBGgPMzpwrE26fzG
iWeXwbb0jnSfqTCTxV9tWC3DLTt9BmXx4c/Qh9lXrRCvyEdQvy9PK8ldgYM+ctIHg5WKe1s84Kuz
JsbrgIE3cgkG1T+R0Cc8wXeaZnWp9lp7zlXfYYpqyphNUXHPNWEq6vwt+ZlMrjXpGgWvlAPRwhnG
wxukv38xxMXdpj6Jf0bH8MInOWAynsVd+wfLeJ9v+fNzP0u+wn6298mhLlkaSp1WUnNgfGdiQSsc
WXUVNlKM1pLhWchXtF58zmP+AT9BucSSNULA6Ua9ZRr7E7sAjXdoSvfyf0LHm1+BuWs+V3CJw0H1
gMpenOkqLS0rButb1czQx0C7KVgf6PM++Cg65OLX1wxHEEzsNccVZiBMnnoD4ucGQ6i/uTbyQNF1
sEY11080DdKczfwTP/HiAvds7mU9JuKNGSRPqigw3qV687IOhk0BHoIJjB4EFP7xUC8hZSq3SRjb
emyoaqG1XZcFjGQtzhv4Ip8eqWvNMoolm44fyChnHXNCJEDbfyTFrtqznkNwkifseKbEGnRC4PST
lxbrmGlKwUJPx57E646sIMEVOyy6BFZPayGq+s3rGZ9GU0RaC0DeVpYtdgEmoRbmnRHQzsxP8Mmz
LqfiS+UCL/FPjHjWJfiZrRB210fdhNfApkqTVrUxHUcifllX99fBgCvXroJRsUJj6G4VHHGxq9fI
E0xp6Yz1C4/4GjQL9DTxx0cSv7aDMbsLdurZkUV5yNRkXxHPx4CRwb1iHAxPB7gulSDTJSbj+1+h
UvTIppziuu0SWkfrFmJeSw8C6sf0q5c6W9HGE0LUE1UJUuzWuM1kUas2QRSWGVcVDQbPBfJqJ6gn
E/fIvFqBC8W/IOe6aHfeAn4sF+9dEOwRZJgyHSW/XObSuaWEm/aZaKrSI3zzqkE6JOhkGD7CMWy5
TmsF/0CcyxoqAD2ONiD7HkSw9DfRb1NCAqvMkyk3+q5z1V0wb8KVi5reK+lojqxaq/FdAMMMZuMv
tLO4jLOtNsOIG2tQQgWJClF3R1KeMnYpJYZrLgMxuOTUM2NwiMbSkgMyLvPaLz8HGN6ufZIPUsVk
6ATbwfqgpIen1iSi8fkkFJwQgvr1Paphto+oWZMaGLaDctyMBye1Gj/qCNL3tYjp4lADtXj7B8jG
lRo61W3JhVC/FLfT+6YfGk7XryhMHXnHHD54bVj7Fgq5GPHUjI8PFcw2AHIVOcBwzYlA0FogmZZ5
ZSLknehLuAz4snoxaKL6RK4i+04mNwd/Keb32XB3UHSuHAE0JPBOQNSo8i5fT72QVND9w2OCa2JF
jE32Yw6PRSOICCS0vtJfsIOozcG+OiS8VsTfNK9sI4tyRVyCseske4J4128oanpQukjAhEA1F+5X
r7AH80ON7y16oXsEvuLWvX/7LJ4H6vf+YdQDpC/+s6G0hGsupRAROF990ls6EZ+6gPHX9DHinqcg
oBgKvGI6CDHwv50CZ0XW9M8cx4leTVsyQv/oEQYpooonl1JNlYLGn59GzBStcKh4V1O+c8weJP1d
3Z1pKaPO86GP4e2vqpVJjr/eRbk+u2I71cq/ZZWoBlm9oQACNK88bToEn80671/2P7Q+gagB5Flc
vHXxSx8PMfetdFw36vPx6bDniURH0dzI29qZMc2z0yS80RYOW0r7Xm+oIP5we0p5xSFkwK7SMV45
wAPnFmoniptNTIujzMSd8c/zEmgfyeswiaIHps7YkNj8WLLUxwpjis4ErFX0ODucQzCvETwDb2OB
OHqHcVyXcxnFWuEEacb5kPqGbXH29T9z53EgmDsba4hyPXdkbN9b3r1d1IeVe4pF1pYQvDz9awn9
kTVi2WRtUp3fXYTqH0iazcZ9BhEkVxyL/Rck+q2rhzWapXCQ6WGJsmUI73JpzOky9SDmNf1wZ5kF
QkzRJQAebbnT4yKUdvmnPcNYr1bqcKwUdMeE9gGsr67ovEwwkF8AkXXsp06o9qeSiSMuuvz45f0r
1jORJRegAP+dLmmVTqO1hoWZBnHElKbNPC/XpLXwX0r8E3lsRxfFRp7eH9HrHAzVI+RRZMCmbdAc
jHWf0oVZIiyRbmYEhun6e9N/fsx77uMbyCDJMIz/teN2uX3ulCTZ9SC6iJnme7LIKLu0p02BNM7+
uq4n+zklwVdZLZLhBi2KPaKSHedsIwxPVZ/SyUP9WQUpqvy9M+JArUx0HGKan785gkjz9sqteus6
x/9Cqj1imntEUHGqLrK7SMb/ZnAeLS8bisoV1QarJjmoDEUcY7DKsUdZIKLfV76+pSKU+7lRtLGa
FsdL/2Pc13oXBCA+BSdEHE9AJoHYH6TEnSJaMb7eNCyet71GmH/1m1TPSm1sN2bZIj1N/S2qS+CG
GhsOc6X/x/ELNcmGeqU3bm6Zv6erkucWq+dYFRTqcfEZpyh7lCxgWdjYpPb5VSpfLzMEOORI4t4V
xEO/Vr3XT6MEzKfQumSU2KFas8n7u1ryd7kI4JoTKbv10b0pXxi5TIAstkGGjKxzhtBrhQ0is4tP
LomjRGQKFTxDAwODuL9wjJCfXw+4DE9+ApAC7wBircaGc1JkMKY3wBK0REQWAPHVDvY1XUWrpIgG
n+JlP+sa/AoCHbTT6e476q0ZjIolMGy4/gP+CjNcUrcO532/CyeeHVZ8QU1cAv8i+9+u/kcNgsls
M2vscffFZV5Y8F10Hl212BAVK2pTomHV9WmP8EaECHZGWD4SUbltPPL3WONZJyqbnuHJcv9Ob7ds
RDfR6W3tfAYPlNDDSowGkfZrRzy9IB30D7wVJdCg7L+gX7HB7bZw/rz8OdXKJkFmm3gPrgIu7Tfd
TTvEoMCc6YJo7CNZOtDK6CJrisk1FJvt0hFsYEBdLuKUeZ+bgCgE5sfkO7SL3dHQFZf7uWpxkgqH
dAY4Wc4InXZUx7DYsDft4mTSrxHgG5TgrH4okuvjszFlO5eHNeY8+sy+VeIfTAv5XpdllszbYUmQ
f/YXNX/lHYAG7mV9mlGge0pILr4tnXyu7UTaIL2p06yZO1mpIzUZOzCrNXyX22Qr4PaXXFkXiN0O
ETm0m0oa43QuoZ+ORo9I3KBH8A0ujoVlrf9w9hPXTBGm8huXgSXhiS1QTqHtZ6IXHWpOYqabcAiQ
nceAKNe6PntsXBU6O0AE3xGwQOPbiFLLnoFHb3rtWzwhzJU7veTr3AndSIK11mLfSDFA3QftDoKD
WC/zKOBmIxlSwxQNTnNXDOoLabMMMFVEjf1bCHM56Dl0wloUr+W4cPcNDtIndQMsb2vnkZhi3fCa
8JWWVDSGYB8L3QTKp2DVGmDPLs6sS80G4COLk7t47cmopd++9ab52GRE2r7KtsEyRhALxtlxJkzg
WViNdegbXHmRaxPVYGiDBdlwjUQUPZ1LR7s2wpBlsyuC/BIal5sxuBeJzxQkSjLcRTOo9RDiNFiF
vgVV6WwESLFPOOZiy4OMyIbRB9eydIqOe9wE7vsCikjiszddf2izwUseXoN9t5uF+nvhZeP/9Vbk
z3f1YyFeC5viBGwR3Sf10CqUUqe5cOIfX94NdEfc/OZ6rKpl+egNLecFRwF6+/MU9tIBpJSV9bb/
X86hP4ZS16Grf5MZuRwAOz2eJ8Pquy+063nGIw5fC8XWZQmuKKeShiED+OMtuq0P4MnPahsjIkc9
Bl9Tk8OEXjBbeWYTA1hBMEbdD045DQQoDoUWysqHGK7DSjYEKNFiizp9GOX2V+Ip4K1WM7auM5c4
Vvq85N8u9plPTSfZcJCTrlJ0KEPqT7nQ+YTE6fOX62AibGwIfi6T3qfP78nUpAQcnQ+PtgWkwhp0
EbSgmghk1+vfTitCJoMH/GQJLkyjvf31LqTnpj4IAbgIGfYQFtccwBnvGajOtRQloKP7bZwVn2UD
iIPcFPfUFOtdFi43kFG8iiLiURBfWS5P/MINDvBAJKVGfnXvXQHQ1hsZCwexXVUfkxFPIrSQP9ZN
fc8bLF3mb1nFgSZ9DVOCXThNnON+N5dD8xa7aFmNu5WdkrgaskZrc4ee6pHjIbUlbMtqhmlnIESA
UwHNMJnhOZibyYQQI6e4R0twwJglrOmXoPwWndxeyPwQRJdbI09emtew5fSTQAo2LYcrqWvo0muu
3hnrSS2xh169gPt+ZpmW7A7OsSwcvwHQq0mte2kujBuPIG5adFXxq+PoB8dZGQF1exbFYQaUPgaF
n/FhA+mdFTHW3MVyHZzMUu80RGKZRoiRGSVW9mX7I0Zb8X15wgaSTUn5yaU5MA9wOYiA+oeSyLJm
rlYvwUgcPg/luUW+afbwHTNMn+77kWfT0Wn/IM8TCDgx21ANl7BVS27bs9Iwrv6nuhrmSf2IGGKW
x+3IIDcdpNRhv0oWSAg+hUwfDzP16laqOMyp0IDQGox7/RAn9QCXyhugvbvy3Jy1r380A7g0OmU/
+0NA0SD0OpWMvkx2nk2W5EjOYCAAOO5TkPhIC5BupRHMB6OAIM4vgiDQ3yGzT7GrKS7Mdy2tjXTx
KZhBzXczl2Oo0AokJ4/UgaRmVgHC8XtNPqI7blLKA3Ki8kiQwP98KjcdFza31Y2VWMjnF/LtfOem
57thfx/3i7hqM25m3ksajNPk0J6UBWgUzDcnQtlRLvydnsd3esPVYv4OgcHFc1t8Vu/VIQPbOEhw
eam7xvGFgF62aH+pbukccRhqcmWzfBbUPoMUtoy56yLXpQSnPyO0HH9WckBF5nrBYVQT3EYlEoFX
XOlXenK2ZnL/gYbQGYPK2oGHHyamxeFhDlLwKK5EppUO4PObiiZSsvfmQ5YQYyT0DmbiWaXMSoE/
CnOjkhGNBhDnSnEM5DT/f+jQVQGi3SH+evbCtay+ORoNOYEooggEZqxH+FZqPvBn2d7pwvB5IxyK
Awe1s94CLUplUnQth8MPbil0uPYHFFIZZrVHobvW2XarZqz87qZXNdS9Us9JbPasvc6DHY+39p/B
BVma8ECQbQvwiK65WyR/uiwjgKMrOM1AnC+iU6hPLBIielT8t+ohjBb4hPc77uIM296Np8c7oz++
HUosl04XkKAmk5zFLmlKyy9i4mr0e2K9jZeTnz55G4UjJPf715XQ2OO/dxQE3GEJOctc3DNrjsRl
IPDNjNfh+1gzQzj93PJRbmXVWZbGtfgiHzG2nwbjSSPqOT66JGHxAqUsuko0SOvriTZ+0psINce5
RkdHW/5Gg+ar29tCzAZicolWxxt1F6fidGE9Q+Gyg2dHsgIumxqfv3P0upibb0OZQrMvRbJwKyKe
OzkZmD117v17tV5VvmJYLpnv2rVnyLsqNGEUT+hiHL2UZirc8D8CxEKDNDZd60iO3Y1AHFl4fjbl
K607BtKaZvzfQrhNnbhv3lO5+4X/+N458bOEFU/G1ceS73Ouxwhd352ZjR8DzWTqva8g627dDQ1R
AXDTEO8bUiNHSiRe9W0KGueDpTbhnS9D1kU8awMYGQSfAh9wQOuyH9eKuR6eG6a81IYvZj8ARF/k
JbzbSL9h5lL3EEFzt4sJhiwJjOEB6XTTBgRe8wZe4xKqE3o2aAu4ymqhjL+YmUgQpYwnuMXupBUg
lJxbgX6Y3r7tSVjGlszZ+72QsArXRI4CDExCndB9FAIzz8MCepVV1aIIfArdA6geKJmT9We8B5bW
xzfj9GULWPdYU018Nyry/6rb3XS8taH6TQq/qTtSQbW0gh9BTa90S7pSfxOybMit3IwKAfAsiozm
2hk6K0uT5yR7j+w2VwN13+WqwVbTz06BCLwrJxQP/waciLz3O4nrsYMKMkoFNZFA9FoZUVMOI0Wm
zStyHUG7U4QCLSrJ+20Yecbx8g+YFAIN4bwbKuIMcLiugdSpPEUlNkfjz6J/1YA+JBHtWnzIap2z
Ov8B4OOlo6yl23qDaYzBY2STLnGKZG5IPsQXoLQoAQ+seDXji/w1hGcNWdp40MGukKo/FJ/QisWv
fobKge9ErFeuekaGIx0MQSRkVpS94peUJ+sJQkNAzyz5XyxFh5D908Hq7iYGqtRBBJmmmbr4ATO3
ulUiYRBnclYMeMV2SnzClxwn0sOSP10G4FgRIIym6P+Zs42oBTlNvWXbLDh5aeaCqRuNvV2xCMVs
7vOO2LyBPS1ape/BmiA+B28a29hqiBEAYn7cdK4PeTpFvIt2G+HpkLQW9WxbMuXsrO+r65hm2LJc
eDWSiwj+B9weR9Q0B4FnStUjDrQHK5Pj/0f9OmlpWBE61M3qNCC2f6nLaYVc9uQhVObi994PXw+G
F8kGFZQW0K8c7S8Mqx8R5xJv5cjyKo9yxZ6Hd6MdJsHKeE6fMne4K/3pfV7+M8jd2qgpjLrwxCpP
L/Sxvm+M0zoI/WnvSIScIBOL9brYG41yvtrDyeio+7kciJMBZAxQO5r0P3XiqiApWF4MgHokPCGG
XSKXjh0gT0R4nqLW2cBSAhXUsH86qmcm8V2nr39IwI7ZnGdwBEHkqH8Uaz0SGM1o/UXteswD6N0+
JRGw/5ympFyqTWPDl71lazpvc7oAfuugcFJQOy5ulXmIfPPmdLT2kb38eSpBv+Kai5eGtajB67d2
p2g2DE3asntzqODzuq9lNuBawpCireCsl6lOgb8PbskJ/0NsSjg/DF5j2GYwvzggm7kSS3XTj9x/
HLbfL9KAKB27+uaL+sXqJB8BiEblk1xiHQuso0Ld2HBU/3A3CJEQfqGXDMCjUt+kI19nXqAEN8CM
u07dWsBG3ZmpcL7bUi4GtxoMHjD6lZhRLwme/x5Ls9/K6m53aAMeVjN3Sgh0iR/hhc/iglh3LuAp
OHoqV5LI6AIgy1q70tw6KjaVaSMxZMQK5MM+gudymqYZjA4nQxBvsnDc+ULg3ZhvlYxTx7ZoDZyx
5K3U35EjNOPzg0077mQdkl6RflnLOYRi70VrUfLNL5ES7VREKnfv2EFq4pZfMAeggODH6ESNrF4b
LNo8CT0ve0sO/XRZon/ZdtN5BYYze386tgMFa6qLo/Ul0TG1UqAIT9jbdIUOF+ITH1OCmSbwY9Na
r+fRXt/oHae2Q8snbIzxWbDyrYkpDYkrTCDxVCWZVWED5dnzVRsFefda4LHpuKtINH5Fs3i6T00S
aFvMPW/6BxyGTCtklz/Aq8AtI3J2+uTD5FG2CMPdG1XcNwWH4WQz/pSr3DwK/jqDvv51r2tvGTSg
hoebs5QRK6LRelHrRGbJL4Rnqosjt+dROuOFJFhudwwMfAbyuh6adQAuNpfs3EFFRr/U25RJkGkU
5y3TdMpnIWsLgOehcr/r7p/0Vyfxsc6haAigQFDT9ocHJzCN6Mhu2bOhJrt4AeiiZVOVpZiWgatv
ayuLgF6ZKLNin2BOVCgzHQSmg4XCOGI34H/zMot4Qbl/fcno9TqDA4N+71CDxBp4rQsB4bqmAgAE
GeGh4dW3wJ/T8jFmxjjcazp0mjP87iTJ/ghPGiKJ9GfjsQIrfDiZiowfL8e1kkJFtSEepLky2Pz7
Vg6eCq29gwWzw2t9nS0IuzE0Xj7chhLv5yhG/kvJfRpJh3spXtqzIMeEOe1HCT/OPTStOIawjtN4
tAmEQulX/QR4YiGPN2HLcUQ7B1zJ5O3xataT7wtkRBLQsoxiE/bkP74qEuzopVTpj8suixsEiZ2J
+kANey7dxKqclQ5rIW01cFk1O6uNfOSuf5oE+r5hqODXgxvu09RjIhPT3IS2Ucfcrq2AUA1LvyI1
YuUzLSSUCdAD3vcstgRMrTfqCuLHesZfbZhvjzRFFtBhpSK8kkkUp7PW0F2FWwG9qkr0lB8HexEZ
DjoV5YY8N2gMxTWZHlCr/XVaNRyBxvo2re9em/eXiZViZHWmQHLa35KLuEshXjYErQK8bckcW5HD
NZIvKWcFtz2SaDuVPpoqqumdT7YgpKeTfUORBZagSiBRS7SOUu4xwIl/M8bS47lwuTm7/tXOEWB4
CLMnpwDCI71Wq4K73ccwkValTGlYQ9rh1yd1k9J+MJ1ykgG6bZ2rmRPG4HK4HDfWDEu/k4HWDpeT
sIvldIxwDysqMEh//eHfcNrsx7+/YsZeK2vpV3R4BdyTWsS0sjg8LUoQ0/c8M+23a5E7vnYaaTyp
8aEzSjy0oi4C995LGwnEbZ3FUi0k+pXma96lvH2RTUKfK74/kmaWc+MRnA8DJLWvjy71PeGtkOxT
rl952TgGO2aQ0bzBLujPfr05zzgA7j7FbPmbZs8DJstTiyvitlFj5V7rtM3A2DKGeO3UfW72Pd0i
QNIzp/2Un0++sjiKg85Z9qXJLjAJ8UT7JEREP4mp65QdD1TTYeL5BrDXn0UaKe1i0kNA3IftoqPI
2xqkasHzhc6aRU77DSQ25Pf7Xz3uzrs9TYKu1RG6PVtBS20OYPo0BhBRYrg10kTmQsiGXMfe8oGz
R3sIZEzN1qdQmcvF8hV8W08e4RlqV8riD5WTcWF6u+w6qdLlfqPqm2FvUEPPtMTKXPYwS5wAA8O9
toETOlyrxit5M6qqvkKQlwuk9Rsga/An47cg0wW8Zt9yyK/ruRqxXjVbahSfuQoYNxYNDC7zAUsd
pQJ7kjYJlGCBb9WhzydEjeQ1mbg1pnru0UUt7BPmr1xZw5YTuVuOTyzzKRtIZa5fzOC7V+333PP5
ROidLqScom2KcMXYym4JjbjDPpy8tZ1N2qzd39z/YWI0JDQ6nH0FroULZywBZRjtUH3Ctpgqb/9l
AupEf/qbnJbgnBlqEhv9sB4WxiRzGdmURpdy3OInLdFLeDtflYDken/2il8GQZngDFK+X4V2Sg1A
odYwJZKl3I3od+iJW4AB7eB51omFnU6c5naVP5qfYrO35nj6VIaXDF266iScFj39YblsvK01UuLU
QyAxVvTVl86lAWGClgc6UjPrRX1Et5FsrCs4v4GYdUcsol/OZNm3xItC3qCs4jR8rq+FOL9UObYy
C6iLoTUdf8L9xHCJUChIoORbXd+sl3jEGiiJJRWCVle1Bjag2sBcgSlymXj66QlDFy94ODSA01m+
c3O+uTtg3u37qqeH3ABV9vfHlH0Ekic4F0fiyGW9a7Dm2YgRsRI1cDtDABOSs1xPH0dIaeIu66kY
bI2mGQwh/wT+0cnoVt67/ToiNyZdmdVyNmQHG1cOSRQW/n+zXI0T1pELK5fLya77GwiFrJORgasl
5XSHY3CAO7zKtzrCWIz/U27KvUfB/GcHqTAI+ISKQXnx4EKHR6JK/CsfWJm4ZIbqGK4tS3237o0g
W+tjy1SBnaWAWbTPbbWyCU0mtPs35fEtwo8K9L8AyfvKwc0mLAPwGbM8S+8WdCKtgSO60J3viIxe
YZ37yLAO704UcinTumoCuZbdyzwbJuQqQykvTK1r89FT5Lm1G3EPlXoQutEz1Hn0x946SVlP1+Ww
ycXwjDbSiThqlRBTWKtSZtyfiHK7aVsIdyXJj+Gqd2jQDtuuLR7I1mFIqF7vcKt5E2uJia1M0dNf
2Ck0LSxtU864VBjiQXpD5Z0eM0dZRD0vbIFgTeK2kVHclVODCD96xxj6SZjkcopHwhUAapPoule1
foJ85Op2VOmji/54aNULFY6Mp65eCiC7Ni+Z96VjUoq6qVY3tZviW+DYeOnQSQzlqrJrqex2iBjj
3YnMaQBKRzt0Lx0Fr8E1KLgDOCTt/VPoDWWFY6RNEigyGHxaaWxKUd+HLcG/SH50nAuzPfx5a8f3
vgAZYhVMUe8tKb1tb7qcbP9YcbOgxkBOUdPcxJDyjX0xclBB6EVBcOncuMUnLcDl98FtpnpJzg+Q
I6JpY8pdHAAZ+aC/d7aoxFWiA/arTPgpBtMBRH5kZrt7h5/EAp8Ixodn96B8mGYUqmHAhF38W+/Z
TPLcdVj/GQMjWuQqEhq7EjVcGykjn56kT8iLE/ccxr1E5lyd1NcZQ6C2V7bOVLzbe3CciYRWcRcL
uY3cfNxR56IvyBXqFZ4Dib1xNrf9W6dx0A9xrCAvqdyTIdL1fNaMQo17NR3wxnUdCvzSoV14VFSa
jv4k+Hl6HdqvcPRbCy0TgjxNpER3+Ir5hZSgpqQypoZxn8jo3Qd8F5qeQdrpleMdIEanYCc1vwKb
dTzkNEUcEYXZ8K4N/7zxqf2sWNq2mxKL9ha6rAmEOJcCypmz45RR+s1yCo3793z2XADA5WAxy/Xq
Th7hrBh/O/dtlydzsEUYDWTcrr+KJo2IGvYuSyIvBdTywi3s00CcyHJGafwrxu7F9EV96iAYSh0n
NgQ7QM4KT5TjZAaMYnKD07PcMtu1dZ/Nnhbib1PmHjmrc3Ksrh/smzgoMDPYkvmAoFxJwMzZYukG
wKswohybtFzeQ9LH7GzJMbqdwkAJRj08nW5SzhC5z6GCX7oVIiqyRVf74s1mYpMsCjHW9iOWA6e1
Esu5yPgNvHbbS9AnG/2sRg3Ka1L/JGIoWrHWTK2Xh1O7tHRYs2rAjr2IRBzti7CB29wxSmMsS2NG
TR/UqjL3CJypI5uhSOQcEg3BsWigcTYso1+NBPcSbq/QRPvwhYhn757LjMpdu5385RwGwaHKmpIY
GMs3Hl2aYCutz0T2NCWq/r9nXmRJr4CrcrOak18vQwX2TFduaeCv0wTasMDCpExLJbuLcPNYX6ih
BcOQdQ9MN83s5dFzumN080xzNS5PawwcrGKdISaLmM8wpglRd3bFZTKHpuA4UnY3716yU8f70iZt
pL38JyJRxfM7dzwCF8ZDc4Vt+3Cd9jhgUkofno3hoaM/SVM80PAQzexQOnUuJB6nqNCOBPRUft4w
Ip8me90aDI6Bup56CcdC5z0+lPdPr2dlhDUFAck2GccLy/x4qBPRI4oX7oJM1ksxIkB7nEf3ezDv
iWHEH5210WU5tudLN6HmIthJOEwYetXnI4WAqRWMmSfw3p22p03yQP5W1gnLahaBl1fIP38E3mOa
27fSWR1TK5iGUOYB/8eZW7CFhwYqi/H+nxKQJuxSkXE/uUTyL7UYIb3a+uL3D7j+Ej4ljgrHon0L
MILg+Xo9InZjXJ5QY8koWmXGb9T+IhJRDZ0SXOcdh4zyu1KrqVaexJgrhIK4IkJobRcCglZdGq87
TbqbkgF9qlXYYi8tPoXW9F7/s3I+RlVzy02hDNCQe4szIDjDJ4kgxTPY+U3ZgXY6ijPgCPk0mnBL
XRKifGuuSG59JX8rutdmGUVFHXuH9i9eygydyjQ4LYwbl05R0Ff+RM4STE9dv9MCE7C2yQBfCy2h
OCQh62VLzCLeNjO63ROak9u4cEbbZxiu66LxslTrHaPUpOLhcba1sO5BtT7L/SVXBvnfHgBubY25
04vE7bhqaCsNFXitjTMzEVsI1Rv8VLnmykogkQzcRN4iYQZmvGKoEXcumA+eZJkzsGlSd3eLfgEK
JHXDgCy54/ih7sAmjiTvrHMrwhmlydgiJvkmoBKFpTn0PTr2r3aXW7A8Xyy+V5jOg6TR1nt3dmQd
U57wnWKsyedK/SZOJttUhlxzezP8F6I/5UbyPD7Z96JlkR+eIxJ2rQTdvApiv2e436PSJAGuDQG/
Yc+AXgqWm/ZiBt6OWUCWchTmZ6Zbs41xNlpLJflRCzgMKC6osLQXn48vI/2CScFleAdvV1p0rCsP
CQp/1jaGH/bdcmSndQQ6HZ09m4sMa8S+kEwfRQye89H3Fmu3eBusClef3rINi3sV8+JF4u6uLGMh
LArbiB7nDGPDebo1DfL5g6MVrZPtB7kJoVTCMiBgifKSqp+V0CtHnMhJQdte7yDMc5SuvzeAO8hx
/A584p9sdg2Rv8vVFeFfnDffun4PPueocM8EY1dy8627gSuUgBhDXdmpYx4uWOdCDXCxgRLFTdfQ
YJCph64yu12ho33d5v8HLJDlbI6r70aXrPTIn4u6XZkqFZs7qv+NlT49IFGFjZF+n/QOeQM1Gk0v
rfUTbcdZgLjD4Jk1+G/M6stIXT2d6HZRiUtqdGQPfnUWSOALyGCi6jNsswEYJzfGKFz/F36WVjpL
06f6vkjNX6Zbe9D3VU1VphZtp8md0jm/s1iBhUEn9leeExFMoYClIRCQIXaSVgjquCx+xkyAsDqa
oRt6bJOxCO5qkXvO7m+RDhYvu6s6hyDKX+cCsmwBa0BXbQ9qteT+k9ga2h/+P8KojHK+0JhP8qCP
IY4HEa5It2jipiFQF4brAgE89U411qsQaPkbBoAEZkrwXHik0YcpZy/677mkNxwYCtYdIj4+2F4g
t2rrz82kEBKQc8XJUDasxBdGijE+yjbEGDvihbLRki6pAuFQu98O8DUU/JPoKxpsaLBZqizcCywr
z2j8jcTAXcnEbt4ypE72eafJV73Xi7Yu1uZ6vXk+/1Gakmxa+eKdYOTizaqV0WSGlOYY7QHhG0Gn
7Kw1pgYqq/but5RJZQoQ4qQX637q3NDPcB+Hrj7x3HH7Yk7z5vsLpcp4GIhZ6DUGWSKdUthU0iTr
3Ese0WgFBlM754fuYPtcGRBEG4RUjdmyxBQPFTZeZiw5qr9uUpLeWTOa9ljcBRELJlyGnSOTqJjI
rpPLBCGYNQ7uSpvjY+1uyxt0JnPVUrEyMF5zy39C/FPw51iL/pVuIzzLaPFmVtFAys+K53bukIeT
Jli1lA0/wD3cXo/QCapmoIneAqQBtO4KwG28AVRE0HtWhnggT20kgIR96ugJ5XeMD/Jb9GY2esKD
deNcABh0aX0i5PM2J4Qkh1cIYd3IWGsrRp6b7SvMvH8ZOThTdz4q7sER7udWjBfMlEV90hoZ96ED
TQLc23sybCJ5Nq4Yuma1MuyNqhjVkP0SZ6p6G1rb6BynyOTNpu9/pCSBjXeOYcATQM5Mm/AOe5zB
cVj2cT7a0WtPqgmrYOnGJbYOPuNWrm8qv/RMLUuIUFEFComEVIpvcR8r3oEGAG5y/5mTjtsg9OnE
cmcPv7vTCua2mpYOMdJHjyqBFbcGXbkzJEIBhQdELw+vNMkfQL1+1XuU8ukDLC0YC7hKzQ6K1sHs
9oAlvbbT/C1bemuB0gwCyEGQT1rC4LWXCbKV9VixagvQtkPQcxqlxwVrym27McWBvWpG5h0083bV
HItUFs8jQPB/Dse7z3kXUuSPQAw3GDtje/m5+Ana8J+kVq8o65KocIb9aM0lPc1TiOmdvQnHX1cc
yF8CAoeHphhU88KXwYHGcYbLPSLycKzgA2LXCGgadzoVc47Bql161l3mPwGVb4WHtHcoaCVoGv21
ZloTK9KTfsT7LhhY
`protect end_protected
| mit |
UVVM/UVVM_All | bitvis_vip_spec_cov/src/local_adaptations_pkg.vhd | 1 | 3401 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package local_adaptations_pkg is
-- Max length of line read from CSV file, used in csv_file_reader_pkg.vhd
constant C_CSV_FILE_MAX_LINE_LENGTH : positive := 256;
-- Delimiter when reading and writing CSV files.
constant C_CSV_DELIMITER : character := ',';
-------------------------------------------------------------------------------
-- VIP configuration record
-------------------------------------------------------------------------------
type t_spec_cov_config is record
missing_req_label_severity : t_alert_level; -- Alert level used when the tick_off_req_cov() procedure does not find the specified
-- requirement label in the requirement list.
csv_delimiter : character; -- Character used as delimiter in the CSV files. Default is ",".
max_requirements : natural; -- Maximum number of requirements in the req_map file used in initialize_req_cov().
max_testcases_per_req : natural; -- Max number of testcases allowed per requirement.
csv_max_line_length : positive; -- Max length of each line in any CSV file.
end record;
constant C_SPEC_COV_CONFIG_DEFAULT : t_spec_cov_config := (
missing_req_label_severity => TB_WARNING,
csv_delimiter => C_CSV_DELIMITER,
max_requirements => 1000,
max_testcases_per_req => 20,
csv_max_line_length => C_CSV_FILE_MAX_LINE_LENGTH
);
-- Shared variable for configuring the Spec Cov VIP from the testbench sequencer.
shared variable shared_spec_cov_config : t_spec_cov_config := C_SPEC_COV_CONFIG_DEFAULT;
end package local_adaptations_pkg;
package body local_adaptations_pkg is
end package body local_adaptations_pkg; | mit |
mpvanveldhuizen/16-bit-risc | vhdl/add16.vhd | 4 | 453 | library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_COMP : add4 port map(X((i*4)+3 downto i*4),Y((i*4)+3 downto i*4),C(i),Z((i*4)+3 downto i*4),C(i+1));
end generate adx;
end Logic; | mit |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_cntrl_strm.vhd | 1 | 21804 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library lib_fifo_v1_0_5;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_10.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1_10.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_10.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| mit |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_afifo_autord.vhd | 5 | 17241 | -------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_EN_SAFETY_CKT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF,
C_USE_EMBEDDED_REG => 0 -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
-- ored_ack_ff_reset <= fifo_read_enable or
-- AFIFO_Ainit_Rd_clk or
-- AFIFO_Clr_Rd_Data_Valid;
--
-- sig_rddata_valid <= hold_ff_q or
-- sig_wrfifo_rdack;
--
ored_ack_ff_reset <= '1'
when (fifo_read_enable = '1' or
AFIFO_Ainit_Rd_clk = '1' or
AFIFO_Clr_Rd_Data_Valid = '1')
Else '0';
sig_rddata_valid <= '1'
when (hold_ff_q = '1' or
sig_wrfifo_rdack = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| mit |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_rst_processing_system7_0_50M_0/synth/dma_loopback_rst_processing_system7_0_50M_0.vhd | 1 | 6793 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY dma_loopback_rst_processing_system7_0_50M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END dma_loopback_rst_processing_system7_0_50M_0;
ARCHITECTURE dma_loopback_rst_processing_system7_0_50M_0_arch OF dma_loopback_rst_processing_system7_0_50M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dma_loopback_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dma_loopback_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dma_loopback_rst_processing_system7_0_50M_0_arch : ARCHITECTURE IS "dma_loopback_rst_processing_system7_0_50M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dma_loopback_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "dma_loopback_rst_processing_system7_0_50M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END dma_loopback_rst_processing_system7_0_50M_0_arch;
| mit |
qeedquan/fpga | de2-115/nios_lights/lights/lights_inst.vhd | 1 | 717 | component lights is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
switches_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
leds_export : out std_logic_vector(7 downto 0) -- export
);
end component lights;
u0 : component lights
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
switches_export => CONNECTED_TO_switches_export, -- switches.export
leds_export => CONNECTED_TO_leds_export -- leds.export
);
| mit |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_reset.vhd | 12 | 26430 | -------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_reset.vhd
--
-- Description:
-- This file implements the DataMover Reset module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_datamover_reset is
generic (
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0
-- 0 = Use Synchronous Command/Statys User Interface
-- 1 = Use Asynchronous Command/Statys User Interface
);
port (
-- Primary Clock and Reset Inputs -----------------
--
primary_aclk : in std_logic; --
primary_aresetn : in std_logic; --
---------------------------------------------------
-- Async operation clock and reset from User ------
-- Used for Command/Status User interface --
-- synchronization when C_STSCMD_IS_ASYNC = 1 --
--
secondary_awclk : in std_logic; --
secondary_aresetn : in std_logic; --
---------------------------------------------------
-- Halt request input control -------------------------------
halt_req : in std_logic; --
-- Active high soft shutdown request (can be a pulse) --
--
-- Halt Complete status flag --
halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------------------
--
flush_stop_request : Out std_logic; --
-- Active high soft stop request to modules --
--
data_cntlr_stopped : in std_logic; --
-- Active high flag indicating the data controller is flushed and stopped --
--
addr_cntlr_stopped : in std_logic; --
-- Active high flag indicating the address controller is flushed and stopped --
--
aux1_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 1 module --
-- Tie high if unused --
--
aux2_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 2 module --
-- Tie high if unused --
------------------------------------------------------------------------------------
-- HW Reset outputs to reset groups -------------------------------------
--
cmd_stat_rst_user : Out std_logic; --
-- The reset to the Command/Status Module User interface side --
--
cmd_stat_rst_int : Out std_logic; --
-- The reset to the Command/Status Module internal interface side --
--
mmap_rst : Out std_logic; --
-- The reset to the Memory Map interface side --
--
stream_rst : Out std_logic --
-- The reset to the Stream interface side --
--------------------------------------------------------------------------
);
end entity axi_datamover_reset;
architecture implementation of axi_datamover_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
constant MTBF_STAGES : integer := 4;
-- ATTRIBUTE async_reg : STRING;
-- Signals
signal sig_cmd_stat_rst_user_n : std_logic := '0';
signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0';
signal sig_cmd_stat_rst_int_reg_n : std_logic := '0';
signal sig_mmap_rst_reg_n : std_logic := '0';
signal sig_stream_rst_reg_n : std_logic := '0';
signal sig_syncd_sec_rst : std_logic := '0';
-- soft shutdown support
signal sig_internal_reset : std_logic := '0';
signal sig_s_h_halt_reg : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
-- additional CDC synchronization signals
signal sig_sec_neg_edge_plus_delay : std_logic := '0';
signal sig_secondary_aresetn_reg : std_logic := '0';
signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0';
signal sig_prim2sec_rst_reg2_n : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true";
begin --(architecture implementation)
-- Assign outputs
cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n);
cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
mmap_rst <= not(sig_mmap_rst_reg_n) or
sig_syncd_sec_rst;
stream_rst <= not(sig_stream_rst_reg_n) or
sig_syncd_sec_rst;
-- Internal logic Implmentation
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Synchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_syncd_sec_rst <= '0';
sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from);
end generate GEN_SYNC_CMDSTAT_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Asynchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
-- ATTRIBUTE async_reg : STRING;
signal sig_sec_reset_in_reg_n : std_logic := '0';
signal sig_secondary_aresetn_reg_tmp : std_logic := '0';
-- Secondary reset pulse stretcher
signal sig_secondary_dly1 : std_logic := '0';
signal sig_secondary_dly2 : std_logic := '0';
signal sig_neg_edge_detect : std_logic := '0';
signal sig_sec2prim_reset : std_logic := '0';
signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0';
signal sig_sec2prim_reset_reg2 : std_logic := '0';
signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0';
signal sig_sec2prim_rst_syncro2 : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true";
begin
-- Generate the reset in the primary clock domain. Use the longer
-- of the pulse stretched reset or the actual reset.
sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or
sig_sec2prim_rst_syncro2;
-- Check for falling edge of secondary_aresetn input
sig_neg_edge_detect <= '1'
when (sig_sec_reset_in_reg_n = '1' and
secondary_aresetn = '0')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSE_STRETCH_FLOPS
--
-- Process Description:
-- This process implements a 3 clock wide pulse whenever the
-- secondary reset is asserted
--
-------------------------------------------------------------
IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
If (sig_secondary_dly2 = '1') Then
sig_secondary_dly1 <= '0' ;
sig_secondary_dly2 <= '0' ;
Elsif (sig_neg_edge_detect = '1') Then
sig_secondary_dly1 <= '1';
else
sig_secondary_dly2 <= sig_secondary_dly1 ;
End if;
end if;
end process IMP_PUSE_STRETCH_FLOPS;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_NEG_EDGE
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- negative edge detection,
--
-------------------------------------------------------------
SYNC_NEG_EDGE : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or
sig_secondary_dly1 or
sig_secondary_dly2;
end if;
end process SYNC_NEG_EDGE;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO
--
-- Process Description:
-- This process registers the secondary reset input to
-- the primary clock domain.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_sec_neg_edge_plus_delay,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_reset_reg2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ;
--
-- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig;
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SEC_RST
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- secondary reset input,
--
-------------------------------------------------------------
REG_SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_secondary_aresetn_reg <= secondary_aresetn;
end if;
end process REG_SEC_RST;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO_2
--
-- Process Description:
-- Second stage (destination) synchronizers for the secondary
-- reset CDC to the primary clock.
--
-------------------------------------------------------------
sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg);
SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_secondary_aresetn_reg_tmp,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_rst_syncro2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn);
-- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg);
-- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig;
--
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO_2;
-- Generate the Command and Status side reset
sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and
sig_prim2sec_rst_reg2_n;
-- CDC sig_cmd_stat_rst_user_reg_n_cdc_from;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RESET_ASYNC
--
-- Process Description:
-- This process registers the secondary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_RESET_ASYNC : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_reset_in_reg_n <= secondary_aresetn;
end if;
end process REG_RESET_ASYNC;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_PRIM2SEC_RST
--
-- Process Description:
-- Second (destination clock) stage synchronizers for CDC of
-- primary reset input,
--
-------------------------------------------------------------
SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => secondary_awclk,
scndry_resetn => '0',
scndry_out => sig_prim2sec_rst_reg2_n,
scndry_vect_out => open
);
-- SYNC_PRIM2SEC_RST : process (secondary_awclk)
-- begin
-- if (secondary_awclk'event and secondary_awclk = '1') then
--
-- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from;
-- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to;
--
-- end if;
-- end process SYNC_PRIM2SEC_RST;
--
end generate GEN_ASYNC_CMDSTAT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_PRIM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_PRIM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn;
end if;
end process REG_CMDSTAT_PRIM_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_INT_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status internal interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_INT_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_int_reg_n <= primary_aresetn;
end if;
end process REG_CMDSTAT_INT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_MMAP_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Memory Map interface reset.
--
-------------------------------------------------------------
REG_MMAP_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_rst_reg_n <= primary_aresetn;
end if;
end process REG_MMAP_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STREAM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Stream interface reset.
--
-------------------------------------------------------------
REG_STREAM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_stream_rst_reg_n <= primary_aresetn;
end if;
end process REG_STREAM_RESET;
-- Soft Shutdown logic ------------------------------------------------------
sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
flush_stop_request <= sig_s_h_halt_reg;
halt_cmplt <= sig_halt_cmplt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_HALT_REQ
--
-- Process Description:
-- Implements a sample and hold flop for the halt request
-- input. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
REG_HALT_REQ : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_s_h_halt_reg <= '0';
elsif (halt_req = '1') then
sig_s_h_halt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process REG_HALT_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT
--
-- Process Description:
-- Implements a the flop for the halt complete status
-- output. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_halt_cmplt <= '0';
elsif (data_cntlr_stopped = '1' and
addr_cntlr_stopped = '1' and
aux1_stopped = '1' and
aux2_stopped = '1') then
sig_halt_cmplt <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT;
end implementation;
| mit |
AlexMitakos/DES-in-VHDL | testbenches/test_left_shift_by_1.vhdl | 1 | 470 | library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_left_shift_by_1 is
end test_left_shift_by_1;
architecture behavior of test_left_shift_by_1 is
signal data_in: std_logic_vector(0 to 27);
signal data_out: std_logic_vector(0 to 27);
begin
uut: entity left_shift_by_1 port map (data_in, data_out);
testprocess: process is
begin
data_in<="0111111111111111111111111110";
wait for 10 ns;
end process testprocess;
end architecture behavior;
| mit |
AlexMitakos/DES-in-VHDL | vhdl/right_shift_by_2.vhdl | 1 | 1197 | library ieee;
use ieee.std_logic_1164.all;
--From the beginning there was a thought thar using right_shift_by_1 twice would add overhead to the algorithm. So we created a new function to perform right shift by 2 bits.
entity right_shift_by_2 is
port( data_in: in std_logic_vector(0 to 27);
data_out: out std_logic_vector(0 to 27));
end right_shift_by_2;
architecture behavior of right_shift_by_2 is
begin
data_out(0)<=data_in(26);
data_out(1)<=data_in(27);
data_out(2)<=data_in(0);
data_out(3)<=data_in(1);
data_out(4)<=data_in(2);
data_out(5)<=data_in(3);
data_out(6)<=data_in(4);
data_out(7)<=data_in(5);
data_out(8)<=data_in(6);
data_out(9)<=data_in(7);
data_out(10)<=data_in(8);
data_out(11)<=data_in(9);
data_out(12)<=data_in(10);
data_out(13)<=data_in(11);
data_out(14)<=data_in(12);
data_out(15)<=data_in(13);
data_out(16)<=data_in(14);
data_out(17)<=data_in(15);
data_out(18)<=data_in(16);
data_out(19)<=data_in(17);
data_out(20)<=data_in(18);
data_out(21)<=data_in(19);
data_out(22)<=data_in(20);
data_out(23)<=data_in(21);
data_out(24)<=data_in(22);
data_out(25)<=data_in(23);
data_out(26)<=data_in(24);
data_out(27)<=data_in(25);
end behavior;
| mit |
Given-Jiang/Binarization | tb_Binarization/altera_lnsim/altera_generic_pll_functions/_primary.vhd | 5 | 116 | library verilog;
use verilog.vl_types.all;
entity altera_generic_pll_functions is
end altera_generic_pll_functions;
| mit |
Given-Jiang/Binarization | tb_Binarization/hdl/alt_dspbuilder_delay_GNVTJPHWYT.vhd | 9 | 1102 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNVTJPHWYT is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "01111111";
width : positive := 8);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNVTJPHWYT is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 8,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "01111111")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit |
Given-Jiang/Binarization | tb_Binarization/hdl/alt_dspbuilder_testbench_salt_GNDBMPYDND.vhd | 20 | 1717 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNDBMPYDND is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 1) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= '0';
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic(s(1));
end if ;
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Binarization | tb_Binarization/db/alt_dspbuilder_testbench_clock_GNCGUFKHRR.vhd | 15 | 2707 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; | mit |
KaskMartin/Digiloogika_ALU | ALU/toplevel.vhdl | 1 | 2278 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU is --do not change entity, it must match testbench component
Port ( a , b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
op : in STD_LOGIC_VECTOR (1 downto 0); --2 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end ALU;
architecture toplevel of ALU is
--the component for first function is created
component func1 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for second function is created
component func2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for third function is created
component func3 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for forth function is created
component func4 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for mux is created
component mux is
Port (m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F2_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F3_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F4_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
m_o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
signal F1_out, F2_out, F3_out, F4_out : STD_LOGIC_VECTOR (3 downto 0):="0000";
begin --beginning of the architecture
--components are port mapped according to workinstructions: http://priit.ati.ttu.ee/?page_id=2320
F1 : func1 port map (a => a,
b => b ,
o => F1_out);
F2 : func2 port map (a => a,
o => F2_out);
F3 : func3 port map (a => a,
b => b ,
o => F3_out);
F4 : func4 port map (a => a,
b => b,
o => F4_out);
MUX_tl : mux port map (m_op => op,
F1_in => F1_out,
F2_in => F2_out,
F3_in => F3_out,
F4_in => F4_out,
m_o => o);
end toplevel; | mit |
KaskMartin/Digiloogika_ALU | ALU_FPGA/func_2.vhdl | 2 | 441 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Fun2 = rol A (ringnihe vasakule)
entity func2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end func2;
architecture design of func2 is
signal a_sign, o_sign: signed(3 downto 0);
begin
a_sign <= signed(a);
o_sign <= rotate_left(a_sign, 1);
o <= std_logic_vector(o_sign);
end design; | mit |
APastorG/APG | permutation/permutation_pkg.vhd | 1 | 12673 |
library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
package permutation_pkg is
function permutation_checks(
input_length : integer;
input_indexes : integer_v;
output_indexes : integer_v)
return boolean;
function is_pp_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean;
function is_sp_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean;
function is_ss_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean;
function contiguous_ps_latency(
optimal_perm : integer_vv;
parallel_dimensions : positive;
i : natural;
left : boolean)
return natural;
function calculate_indexes(
i : integer;
P : natural;
K : natural;
offset : natural)
return natural;
function generate_perm_file_name(
parallel_dimensions : positive;
input_indexes : integer_v;
output_indexes : integer_v)
return string;
end package;
package body permutation_pkg is
function permutation_checks(
input_length : integer;
input_indexes : integer_v;
output_indexes : integer_v)
return boolean is
variable dimensions : integer := output_indexes'length;
variable par_dimensions : real := log2(real(input_length));
variable par_dimensions_int : integer := integer(par_dimensions);
begin
--The number of inputs is not a power of 2
assert (integer(par_dimensions) mod 1) = 0
report "(1) " &
"ERROR in module permutation: The number of inputs(" &
image(input_length) & ") must be a power of 2 " & image(par_dimensions mod 1.0)
severity error;
--The generic OUTPUT_INDEXES and the number of inputs do not agree, as the value of dimensions
--is smaller than the parallel dimensions
assert dimensions >= par_dimensions_int
report "(2) " &
"ERROR in module permutation: For the length of the assigned output indexes (" &
image(dimensions) & ") the number of inputs (" & image(input_length) & ") " &
"cannot be greater than (" & image(integer(2.0**dimensions)) & ")"
severity error;
--The generics INPUT_INDEXES and OUTPUT_INDEXES don't have the same size
assert output_indexes'length >= input_indexes'length
report "(3) " &
"ERROR in module permutation: The sizes of the parameters INPUT_INDEXES(" &
image(integer'(input_indexes'length)) & ") and OUTPUT_INDEXES(" &
image(integer'(output_indexes'length)) &
") must be equal."
severity error;
--The input_indexes vector doesn't contain all the indexes from 0 to dimensions-1
ext_loop_in: for i in 0 to dimensions - 1 loop
for j in 0 to dimensions - 1 loop
if input_indexes(j) = i then
next ext_loop_in;
end if;
end loop;
assert false
report "(4) " &
"ERROR in module permutation: The values of INPUT_INDEXES must contain the " &
"values from 0 to " & image(dimensions-1) & " but " & image(i) & " is missing"
severity error;
end loop;
--The output_indexes vector doesn't contain all the indexes from 0 to dimensions-1
ext_loop_out: for i in 0 to dimensions - 1 loop
for j in 0 to dimensions - 1 loop
if output_indexes(j) = i then
next ext_loop_out;
end if;
end loop;
assert false
report "(5) " &
"ERROR in module permutation: The values of OUTPUT_INDEXES must contain the " &
"values from 0 to " & image(dimensions-1) & " but " & image(i) & " is missing"
severity error;
end loop;
return true;
end function;
function is_parallel(
index : natural;
parallel_dimensions : natural)
return boolean is
begin
return index < parallel_dimensions;
end function;
function is_pp_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean is
begin
assert elem_bit_exchange'length = 2
report "ERROR in module permutation: function is_pp called with parameter " &
"elem_bit_exchange of illegal length (" & image(integer'(elem_bit_exchange'length)) &")."
severity error;
return is_parallel(elem_bit_exchange(1), parallel_dimensions)
and
is_parallel(elem_bit_exchange(2), parallel_dimensions);
end function;
function is_sp_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean is
begin
assert elem_bit_exchange'length = 2
report "ERROR in module permutation: function is_sp called with parameter " &
"elem_bit_exchange of illegal length (" & image(integer'(elem_bit_exchange'length)) &")."
severity error;
return is_parallel(elem_bit_exchange(1), parallel_dimensions)
xor
is_parallel(elem_bit_exchange(2), parallel_dimensions);
end function;
function is_ss_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean is
begin
assert elem_bit_exchange'length = 2
report "ERROR in module permutation: function is_ss called with parameter " &
"elem_bit_exchange of illegal length (" & image(integer'(elem_bit_exchange'length)) &")."
severity error;
return not(is_parallel(elem_bit_exchange(1), parallel_dimensions)
or
is_parallel(elem_bit_exchange(2), parallel_dimensions));
end function;
function contiguous_ps_latency(
optimal_perm : integer_vv;
parallel_dimensions : positive;
i : natural;
left : boolean)
return natural is
begin
if left and i > 1 then
if is_sp_perm(optimal_perm(i-1), parallel_dimensions) then --previous elementary bit exchange is serial-parallel
if minimum(optimal_perm(i-1)) = minimum(optimal_perm(i)) then --they share the lowest dimension(the parallel one)
return (2**maximum(optimal_perm(i-1)))/(2**parallel_dimensions); --return latency of previous ps permutation block
end if;
end if;
elsif (not left) and (i < optimal_perm'length) then
if is_sp_perm(optimal_perm(i+1), parallel_dimensions) then --next elementary bit exchange is serial-parallel
if minimum(optimal_perm(i+1)) = minimum(optimal_perm(i)) then --they share the lowest dimension(the parallel one)
return (2**maximum(optimal_perm(i+1)))/(2**parallel_dimensions); --return latency of next ps permutation block
end if;
end if;
end if;
return 0;
end function;
function calculate_indexes(
i : integer;
P : natural;
K : natural;
offset : natural)
return natural is
variable aux : std_ulogic_vector(P-1 downto 0);
begin
aux := std_ulogic_vector(to_unsigned(abs(i), P));
aux := aux sll 1;
if K > 0 then
aux(K-1 downto 0) := aux(K downto 1);
end if;
aux(K) := '1' when offset = 1 else
'0';
return to_integer(unsigned(aux));
end function;
--designed for at most 99 indexes
function calculate_file_name_length(
parallel_dimensions : positive;
input_indexes : integer_v;
output_indexes : integer_v)
return positive is
constant number_of_indexes : positive := input_indexes'length;
constant one_digit_indexes : natural := minimum(10, number_of_indexes);
constant two_digit_indexes : natural := ite(number_of_indexes > 10,
number_of_indexes-10,
0);
variable is_input_in_order : boolean := true;
variable is_output_in_order : boolean := true;
variable result : natural := 0;
begin
if parallel_dimensions > 9 then --"10_"
result := result + 3;
elsif parallel_dimensions > 0 then --"9_"
result := result + 2;
end if;
floop1:
for i in 0 to number_of_indexes-1 loop
if input_indexes(i) /= number_of_indexes-1-i then
is_input_in_order := false;
exit floop1;
end if;
end loop;
floop2:
for i in 0 to number_of_indexes-1 loop
if output_indexes(i) /= number_of_indexes-1-i then
is_output_in_order := false;
exit floop2;
end if;
end loop;
if is_input_in_order then
result := result + 2; --"00"
else
result := result + one_digit_indexes; --"1"
result := result + 2*two_digit_indexes; --"a1" (11)
end if;
result := result + 1; --"_"
if is_output_in_order then
result := result + 2; --"00"
else
result := result + one_digit_indexes; --"1"
result := result + 2*two_digit_indexes; --"a1" (11)
end if;
result := result + 4; --".txt"
return result;
end function;
--string used as this function should be static to work when called in synthesis and thus cannot
--contain line data types(which would more flexible as the size wouldn't need to be predefined)
--designed for at most 99 indexes
function generate_perm_file_name(
parallel_dimensions : positive;
input_indexes : integer_v;
output_indexes : integer_v)
return string is
constant letters : string(1 to 9) := "abcdefghi";
constant file_name_length : positive := calculate_file_name_length(parallel_dimensions,
input_indexes,
output_indexes);
variable is_input_in_order : boolean := true;
variable is_output_in_order : boolean := true;
variable counter : natural := 1;
variable result : string(1 to file_name_length);
begin
if parallel_dimensions > 9 then
result(counter to counter+1) := image(parallel_dimensions);
counter := counter + 2;
elsif parallel_dimensions > 0 then
result(counter to counter) := image(parallel_dimensions);
counter := counter + 1;
end if;
result(counter to counter) := "_";
counter := counter + 1;
floop1:
for i in 0 to input_indexes'length-1 loop
if input_indexes(i) /= input_indexes'length-1-i then
is_input_in_order := false;
exit floop1;
end if;
end loop;
floop2:
for i in 0 to output_indexes'length-1 loop
if output_indexes(i) /= output_indexes'length-1-i then
is_output_in_order := false;
exit floop2;
end if;
end loop;
if is_input_in_order then
result(counter to counter+1) := "00";
counter := counter + 2;
else
for i in 0 to input_indexes'length-1 loop
if input_indexes(i)>9 then
result(counter) := letters(integer(real(input_indexes(i))/10.0));
counter := counter + 1;
end if;
result(counter) := integer'image(input_indexes(i) rem 10)(1);
counter := counter + 1;
end loop;
end if;
result(counter) := '_';
counter := counter + 1;
if is_output_in_order then
result(counter to counter+1) := "00";
counter := counter + 2;
else
for i in 0 to output_indexes'length-1 loop
if output_indexes(i)>9 then
result(counter) := letters(integer(real(output_indexes(i))/10.0));
counter := counter + 1;
end if;
result(counter) := integer'image(output_indexes(i) rem 10)(1);
counter := counter + 1;
end loop;
end if;
result(counter to counter + 3) := string'(".txt");
return result;
end function;
end package body; | mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prj.srcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 20 | 94635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
HCSQmAapELPf1sBJFgFNhgvq73K3W3UGtfFvL7obu/9NizRz26mkfd9wNe21bmirivGTwKeZvyMe
zWixxZrSiw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Tk1PatICqGOpQtQ8oJOeHvG+wSfV6MFfzUR+1NxNiA3D1oXGbbc3gTGsYeri9x35CpLHrY3uJIMS
sskF5MZiJ7RqK1c31dmN3ubJJ35zyIvetaYotC1izf5s6ofYhL5l9laNqVTgpIBd3otGkPj7WK42
86gYynjSjGGc+HBZhcI=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cfZeSAapGTxUQEvxn2/r1T9bFdYrx2rPwOioTJgVQ4OPGb3rFvHX8Vp6MPky6sR+Tep2gIB6VvvP
GJ5ngtwI0kzcD8i/Z7LqBs3I0qgI2LxV9deOeTUvqf7Xj+AX3Me28gLMVyg5BeW6O/GYGZS6IF77
zIAQ05cyjTCdzU0eisQ=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hByo2GW7W1vrbUqX0oTwbTccL13floF1xp6jmWwfhWqfIXbs0v8cD3nYTIv0ZYmWoiTKFmNd2sTo
hSJnPp7TVyR1qJV4cGM5eHyJP0Oa0E9FIgOeJbf6amWtoLToYMeyuyPFP2PGgWxiTnTHvCRNxcee
r2qILz+Dre3Cv9w+px2Ly7XdRgYJ3RzxQTc6eb9jPdogRLqbWIApE3aukiI+xrAOOeOWDGbHkIGi
PEbEc9hjcMTJGsiBrr+650bIjmaHov/vU5mT7BxlWt0FfFp2aUWxkbKxh2AZTOD4yzu/CnaGjY+s
amPG0D13N2mmb+HM77btNBJwICYwyT0dib12KQ==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XVZe1Iq1b4q0pJb7G1HiRPHToYeBo0kSF6/+epE/iNiHS4dXLRGITekimnvUz5jWC64VQVuw116b
q9OWkuBBNOouYj7wEAh1ufsn0z3zlkIMYNtGWNIdhLZl1p4j0bK/HvisFljWeFoyO80WNu3avx8g
sKSpXqMlJW2EaFNf4NWfq7c3muHUQgSgG3nk/5vO0zESapsSTn6WmN5PuuhhAVEm+UpYjnn1vaMi
FCcQWMu6hrIFKlyiWWFj7aF9efNcYZ1vxJhIL9jhKm6ritRw5ekFlEM5BpA3Fo6rdQML5P0ZB1qr
YAvM3UTGIvL4FyuNcsavn2EM7H5R9TD3b5jlGQ==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FKZGFNGDGgbVQmf36A3vvlEeMnTnMkVMn0xyNtGAe/C4BYiio0GGVng56CCV/s2VwIm86yFp5jG6
OufL8mHaK4lz/4lq9NjXNCGWuIw3b9dPcaLXw7iwVjULo0X5P00dXSClAogIRSQDMhMifhijdjna
Eb/DWk+oktBkXYiz4Up9+USfCbQs1TybctiLJiIo5ZY7v/TiA8q6C+PcOae1te0q3hmRyJ/Sfsaq
/hJvDUrmS+CocnCEQuXxO1mKRTFHdj/f+yRZWld2jM0s+jXW1EGw+L492pzX7W7U768NObMW4fwA
Uc/SSjGIhOpg9nMGC+XCI+RN5rkAFDfhx6kGMA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
pKjKQ9yxMXDRjXEKg0nt75KpMqHxlcPp1+s85YeqrqVYl5pOJxW3Ga00rDbgkABHmOgn6PchGFbr
eaMVQeoFcCFKZXGvQMCnbXtlMJyzWT1noQFNtrE+AJhueb7CDiGwNxQo71UTANf5zxjyWwEeyvKn
MejF1pqbzRicYPoG/RkgM4kXZpRtOQK6N3awoZDOaFd2JJht2HuHOsn7htPff65dGss/n/I+kEKg
zQywfr2Q0fE/9l8JlKONQyYLC4RLl79gg5ICll0Wh73DJJn8EOydDJM/C3O87B1ufNTtci9cOP3Y
y7/Pvf79xm2dNy+IQ2WJUKNbBFZKAojd9gZXqmIz86Nuz1ekBneOCvIFgDbGMitx1cfC36q2wN8Y
pdnTEZ3qUvOUbeNJXGRoqFH3HOiT3b/FCJTUl8RCibnoldrcJ1jyyOMejk+QnkLRokqzsf8JsDR+
3upEDwZaaoVZT+mx49LVN3SCU2P9JgpqYXWDN9cKn1WO/Ix+dyaHmIm1+8AVRYPawvT/5pH8j+UB
BXRU6dji4Rcqr+7BqtEyhaQohWD6dCxfeByuUqmw+1gZM0utAEvKve9Czd8NvsEdEZZ0nJi1SMOi
gPWEzJoLfVPxox2oE/w+ZlTMxjHeB8mss1yD3Ga/0isCaU1fL5JzbJCUlDyiClzEVw8UJ4JgxBBS
NpujZ6aD8hOUyCO+MSKCmgO8no9ApVkolw/wpWj3gxRGYWr8qo+rnM5OD2XPp9fyS8666McMkoOy
0J6g8PY2htn49jSDLA9FScLHI1/ZN+hEmBWgqzn/tO9ioukUSFkXeClAXe/TCQBFm0NKoOa9GKr6
36BFj6WUW938GpT+YBkO+1PFwb8E/lQXsVpJRN8BpRbhijmZTauxQZbliAp0V2IbgF21M/koso4A
YERKT/z0Iv4ACibGixFE/WRryLG/ydrMP7mnejssE/2PUkZKGgCnFcrXHMI8cfODV1394q2EiRBs
lj44hbCwxNxtbVqGUI0r0WBYD5b6fihc7E+NoqH+8aeHjzoPsV5lZFBAV+eFAv19vIWicWtjxDpQ
cRt8goRM0QdZeVJ57/wtZq8/s4BTTfZbKHBHyr2FXl+siWAjZ1dq7NQc6YFeG3aguuMPFgzPYZML
ZPLhr9v6Eboxt3AGDwEaOyahdfzGLaaKaDoWrcLQL7u0lvNIaYTkNFPyXftDNNkud1Vj4Qd/n3hM
so8IueVC8H5/Mhf36L2pPVudcgDXtKCJOBDRFVclYGeVgo0atY2njyjISbjQz487kLhQVpy5B7fM
t71kDHKY4i1apkwyvJ04qXopedhmKm/2bhMuDGBtC1ZrQGOnMu/58YHNe8epmMASQlFnG1eesLkr
FCPPTn5bvXIrSjvd4SM/wusBtyXjaCHiuwGX2XYsUSIa0qe8n1YRxa2wz7/EPjHu2Fmqu1tXYW7t
LNZJN95KOF1mEF3Rq56vrjBOVt/6kSkmF5FR+tmvBgxBW93SV9LGGGbZXWq03njtwuhVOr4IhDvF
m7LssCudhF34JDN1BmRaJmEosp1kv6FmXmgvX2MEl+iGrMoQcbKp2QgIkAQNfL6PnBw/cdivaUik
WnnYQTcIG0jcuTt4lqU5N3zInOcCXHQzOmUKrHIwK3vxFsfKXn+f3XZ9ea7Ik9yEjngtDk233Vlf
fdcmP5WrSoR1WIO6dVPt4Zm9kCWoml825wTcybg97jAXVS4+NgByCYgvO2TPeL1myE/EoTxZxxuH
aydQ+xb06DPcSDzgvSlirFvkpbgV8kQrVJYIEneO/g9QIfX5b5z97Hl/yWy1k17Ffg+lwJ9pTg4e
zcFWenRSqpRSrAzpxhC3pXwyKp3jouJcbeTKtYxXtfCpjAyW1wRuPdOSPk8PSvmji0kumE1LHYQ+
N5CIkfq1loNJkK+Cj4L5uyHso8tby9qYCswq3bJgDPmnpINxlfn+fH8SPpjU0FRGDjtLXxEArLkN
Q/HU/v9pxs0bOe/9k30fEnvzfeJ5QfLUwEO77+d6mI3K5eSeipUxmBFCrwcD323Xh5zeFtNdOuPO
MGDyK22SoK8HuIpfW4E8EaFvMe7VzAmWS1rTXRqLLNCk65mj/fVYKM4zSHyTEZI7HVvaC50nWk3c
yquE0/jNGIFYhoCtGntCDaoRDijKjiQcCkBDkeM6oKDILduVwKHUVQFfdTlUvSMDAjQpTUNokhDF
sGjI2jl/tcsmpCafxShAB0EtCibNOJxTGB3/y8uXQBPBxN96MUwOE+yrgyQBjw2NxSH2MzUUaBEf
u2TWSA67OTtDtqat3q6Luv1RmcHlU5InEhc3szm5YMYOjUSfuXDHJpFdG01J63I35qnc/aHNbRYu
B0UR/l5lvIzKcNnjwYo8Ph1vwvIKR/9f/tMX4OSiFHBVCZA5o3gnFIHwxKGbaTJ8TZ90eufYLAcc
sv9ko7JTUBNDhzrIOwHKecIDM8iBPzfwGEgFnL7y5QrIquN+ykFYNWZ1NHwbn+rNLCcXJypf645V
5y7Gihp037SGrx594zxycilov4qEGiDBrQifMcUsmQFYBRYz//eHif3IKHwqpZU59i5thYo/1PBK
ZcHrIocdywqMHuy/y11v0tDdw1+usAfs9bfG+mEDspRGEx6HXhbDnKKsj1VuzSsFDfyLyJpCoU7e
e61ryJqAQv4HuAPGEtFNPjSW8vVywFrM173l+HemYRkI7WTpA6nyCMjK1ul0LPtwWtVVhRK4wSI+
2d0tVxfSzhJooPnnB0Fh9tlsJjj8sSd6JnFb52+8BAiw+a+PTEPN0wdtkzruvZiqhBk1CAMdBuUj
Lvg/6qdk5okrN7F+XBqUB4eNhIJ/22Hhpot8BeVfyZ883SC9DOSp9HHSu0YqOx4638WM96eGaViI
+AcatS3CyIphx/TXbgtSXYIB+ZxRe3kM3DwHF57qQ7EmwyyCghBfTrqnJ5kb3d8kIdjbcr2aXQTm
Gw+u8ex0IG9Cp4A9jFcAP52iG+bjFWoTuSN+HNZEAqTFDrdf8uv+bZV1EYwb/v9gAmzuCXeDKB1r
58PIts6+9/LwJ4+B1Yosfw45Vr8teU4B+3G185KhWCBMbhG4ybmTMNucODo/yzzt6amgKfnypQnB
GY4H2JftVRmPVsRNYM4msSyP1DHazEubuVfVwLwYvNOTLHybCuOw9VEnupuHOP9cSgg7IVDcmb0q
xW4IsCeYDyzEDFFqkYyRGAPdQtRJtVJWRZfA3/Z/R+D34wLbxRFnBzDV2MUrKgaA+M1n9oQsiZzD
Phqh9Mco617HFF0K4WH9N44mjzuaPxMNPT4dnKLne4ByuR+dB/MIxXOGmyQDSwGAcC/oZThXJk76
47dWcKcdsh4XUl6jGQc2KonTvckShrR2PhLH/H/riSN4py1+sL/+v+Zqu1RqAzbUYxfX3nsMXIgT
mWMrqjLg/y2LUvkGBHCZa9G7t0tBvJjKuHWi8Yzx8dNigEooSpzHEskKUhwUmAkPhAilf7ihZ/lZ
jCOSVuboa7AVigtNr857e2mBQ/No+Jb8GdN29ueSGv7nOOyIqgNNmOedpdL0BsZqtGmSH/6OCmjZ
kae4Ar/FoHyIauu0d5sRJEXuSE7UTCX8cAbH3P89kWknc7xpI/ZIdcVSiW8TODqBmuA+4WJuJsA2
KYJRqvGI358hhKqZ2/siqU6mu+7t/yikS78+SD/4CbDT3eakNsURhMg249yWl/OPiaG4T3wOpLQ0
CYDWUpSYET0yfBVTH491raK5MED9KceuQHNZuHbb6FlNpenTYzMT4Ms7ZbkMqNtLyVNicCO7xDe/
X1klZx96BcAlU+eyvDtZ1doCbIszVWJWXXL1BT4AbsikNMq3PNiuaIFVZvXgNBaHSPaOsUEXXJhF
wjBSmGczETL5GaaQ+5w0+RxEI+sOFhkLI8Ve/AYznbvq5RCDlMTlt+ZQG4mMe4S4mTMXPWXw1X1d
sHPl983C2/TAC9gY7gip1da3Gno3lElnslxNl+uCCuq6aiKywbs+wVOkls0BtNEAyW/4b3uPmObf
swh0fjQZt/cOuV2J2hcIEf722au/qvs/6PJlobPMOA3LjPTZKfohBTK5HouG/6Taici+bGIzV2Yx
aorWAn+JCEPWIrLvrK/GJaf+hxA8IExZP6iazNzATlltFr3ArztELM5vlJos0iewpu9YeDBSAG7S
bTAgBRmWvXe6XV60VzbgtLwZKzMgS4gl5NgZMvklN5WBhRcU/Z6MVborEXOrw/nc0YtHN/n9/lH1
9Q57iP7FvqFSC9LJDA8HhvR3KPQfi2vEvgjcuKS2xliareEi1I2tqDgeTVR3ihqt8IrSl+6MpT3z
kc28FcEQETkACVNmTySB/Bekr9xqrpdq3De+csUUyqu6DBPSy4Qm0CWSeWCE/WOXuHXro1wwdSFC
O8ntXyfiG3lK+PAi442OCVV1edO6jwaEEue+7uQKzX0GaV76rSb7rH18iQe00ZmbdvrYOddz3Ezs
ByzWFYy3COG4DnTQ/lrQn6QE4aUfCSYf45BGrBOE5wF6rnN+4UahtaiXcup3NGcdh1hfL22X2sfx
0R3MSFjZH5xrZ7VYDwGhOYhg+ymsPEsyMCCGhc4ZW6Z5Eg++wM9SR6ZgwJ0N6oggVj9mEC3sop94
Iuh6Xqnno7djtbE8SB0JPZgaZVRdYpr3sDqUt3zGeOwdPgyxBfAAlhzy95XcZPVNC1M5du8b/OSX
BDChn2ZIOeCeneQmSjM1XQv96oDAuVqaEqxzgeZVMWcXiEkaWzCC++U2KpqsNNu1E4NO2u2TX1Oi
mZLMameX/Si0x924QdyxSeClJAGv3FFkxQ0IyCWT978WDgRfLBzLyq2tlhUZb2paDOtre+vskV41
YQns2ui9Bz/3VeoyHr51gwDMILImaroTvgEc19QD2jYBQrzSE6SycoEyKVrYxep5BD2mLhTpYnhf
y+c8Qhw1rc6BL2awNaQ5CZ8I+k6I4j+dK31vHOI79WhEYrE4ShIvW0anOUJSItVUUPH9TCU9nf2j
FNnVDNGcL975XSaWgGuw1CXw/xbqHyL4NjG2UaWqMVBXbn30pJhUP5FrkY6iN5iLK7cVRSyAI+JV
H5KSt4zjy5OZTb26uIohuAldgzIsFInXdLM7wVbqp/3vVVznVE895fDxkonI35r0SJjIiWLry9ie
ZMXZGDb6H8WjAb44+anN80Yd3bbnUTTYRIx+t2Mfo0wOcz63xVnOSU7jBHe4boTEtx2ADGrYw+3W
dxyb1FYtSLlUPsn/7zTUyGeI4NqYITaURZ0raQdRA6pOnW788aaIonbUflGtKEWWyPwBUlakirzY
H2GFQqup+A1ipkJNyXdrcWpyc5NQ+Sc9Y5rn9cMl43Y0nC6rVpdkv/9Lxgn468ZPUmeNWit1AuNz
K/nczm+sxNc2qe2WRihNnOOhmjL36LF+lZ4rS6iIC6zlT7ZddeXGzEivDMZ2uv8EDuWFA4DviNst
zvrN6ZtLvtxXz5DNDwDZ20teoxW+vypjctVN+ir1i1jxKX+wqma5OL7SSNfHpw4x9FLx0WpWIaZD
zpF0VdiSMDvn2l279G0w7N0zDdsV7bIUgYJdSklLhrjMRFPjSxmwuQ6xXlc2C08cf/eyjy3j2rSt
YqL8Twf/wGavXhPHTedowweI8B4Pu9XU44ZXvDkDptMMGRJ7nhjMlbYB0n5PDSTLqFJgOr9UiZAM
2yLQcqJyKUkYAK4BWM6E/X2VGmJgFsbjjGrD+gOSWt2iaqiM8pd1WuXyaAuh4Y/mBifY1xiOQBv7
b5xDyJJi9+1yXcwdeXAywWtPnqJ+j2gvkU1t9X/0VABgQdbLvrjqLcFPKIPlPZRLJrFb7X4/ZR3m
XqNyD6EYgt113MZuKcm1p5dmIOSKaAXVXDIvrdZ67/z27fNkpoD7wQ1O/B3uY4u7tquSKLkeFctJ
hBzOyPd+7ljwuKs1dWTISeRKjXQMLdRBf6KIxmX/SWgZEliGJxQnUgq5WWy/oQ15XJGGn/QchknJ
3vtG7wH8PmeC9msr2cMptR8bLjv4HCZz6EuMZDURq765rO32By21iDrJIA4LwlbHajqeZXpH28A0
ZyVVBbMKH5UMr8ZqLbnxuzmTe7NznG/EYJTPUrj9A+D1+SjVswOP81i/EgdHQ9BJJ1lLo5LnX4Aw
c1u6f6hFKTC7+Wq9ghB46KLxAkPUj+ow3VyKfYt83hllRh3bO18Xo2EJ6ySeYaWUl1GfOR02bJyb
QCYQ/EURwoT2TmOuqFwpxMn2hn1cSK77zQ6YfO4bTcF6km69Fj3pLdSxZK+AOkjTfBR0pHDBhdfJ
MFrbTWcxrlFdnA+0QuGiVMWwOBGKyzKp3VABtvir36h/QWyS2ivKwxVKvIUqroNqNK+Gvt9UISuE
Sfy5iOxhdIW14HlfBjYMijbmW0eNk4d56I64GF9vXtrIQR+E6ddyz8OVj8XtneZtRq7m6SYpuRhG
YpCjRPs5GYhctrCpG60lzTjYZzxnz2GZBM2Tf8PDzjewlHVgH5z1z66H0br05Gno4J2USreOTrfA
a7zvtJ25k4P5pDLYPl6ilxizQkArCquFwEfP2YueGtcPXJ1UvvM8W0hLrllXKRGa2IUNvi10845y
hXk0ZMOWwHpDIECmlIyxD8S+MTIW/MEMsttLv6+drImm5oR9w7dhFb6UYzfiTm6knBeejmxw3YJO
q4h901lLu5/JHqbXmsXve9vuJRtKmTK54J53hfTjujHwKxlD3dj2u7qWM/CSFJscouER3JgaCuGo
VeS1t+D1MNrfIPZbBtrU6nASdP1wVg9RBRqQQhmCUZqlW0SGmoMY663c4jcnDLZEVAodIJlIvF2x
y0VB7thcpUrPO2k6gOYLkJbDKIin0LhCLtF/ar3OrpUM4zgnAkEZQNUXiM9bsbpuOppgZ9vO0ilV
Ear+W6zD719XAs72QVUTlPJBacMKwWcY/31EVhFo2eji1mobF0FOHPN1vzi1qum/xHb/ujquWwcb
crzoSnfKN+4FFItEKviCZLUiTZelCQd6s5WaWM9l/vuL+n2IbP1pao5OLySYIXxu+lX/H2FEb9o2
Dg2scP8hT6cvJ6ZjR4C6GyhrmGV8N9KwOzP2bdgAv5ukLfkJCqI+cQ8t1vZHfAFk3viibW7hd9Gp
WScrGH7UUJuiLLwHnYy2jlBE6QTnpEmItoxb2aVmM1pRAMYqoi1oxcwJawNFcEBuA17jpT/bLJ65
Ms8SKd7ktaokXv9co+Ln1wy9HI/j6/AJk5+gzGe1tYMB5yECj5UjDS/PB8BH15Qff2vpZOCBXeg3
94QbC5NNPiZWDoK1jE35Or7+L+w/ekN2W1aBEHpBM74eDuOISOtOpZkD0XJy+ZV0wLHHLW2Bbn63
6B0g+hgSGtTU6An6xJrGLQaQI5Ba9HxG6HmnnydmSCa+4jJUBiRLjtBJ7YjVND/8Js6giUmZBO59
E+hFbFG0OEDXpmoX/3N7rtt656FUNe3GjnSAZDJzeBQDxKBzqrXtUIj/llSpxuKBKJolutTrQUxf
bTq4wPIrXEU1EVuRydYfKJ5UIRUj+6UUh1d5dqMqXyKEoNzSDqhGjee37Rjlgls65IvvkHyZFxLI
qNF9Gm5jFJy/+0xZOqSnigMTTRzxmGPBGx19gGmow86+SffDalVjerXK6/IFIiixQrMEFgRYB3ZX
RIV4JeerH2B0NBynTExt1OAIMIHwoEVnBs93JCfaas9/cRmSpPXrBaCmIL6gGj1PypVUOv+duz+g
4fVOxAesOsBj9xCZkkSfEfMgLAfZkNZpQSgWfxaYx+S6niYLTpbHzq1X3fyq/kMN32kXgpNcr73Z
Jb4PREyoUGnwdw+MUCEH1yfljEQIELknKqDneRttTC7chrEX4/QPj8cS5WkvJ8mLtrwQwytWEYnD
xnQv02TOO9kY0dTWo38K1WS7iyyFZEN/s4miNIzbdIEq8Yi+FmZJmf0zVRQeDkfMctsGUwVJtTUR
67j6LVs1eMfQjCvNatXfK0RCwBhHOea0n33ytYBAd65xuDzWdxgJKUxn8bzvY+xhAbWEh2BTUKs5
Y9PZYxWrryBmnSqFvlbCyGqOtQmecW7O4wkoK/iZnQZv3dOBud9I/+H+fcXBIfG5QD1MXX4J3TNA
3V90JsgSp9inrYIKarqfS38rEufJledPUnhWSzN93tM+eUO83/2g+6K92XHxMzedfLeISmab6lXt
PqtuPUDx2u2GSvNlRiTJbK59We02PzHZdmNVM5q/OG+UkGHSfjmG/kMqyW3I2VxDsr2V+6952viB
38xVRec7lry87xFv6hnIVC3sREFbx39/ybKugHNmrbD40hszT6k09AF+kSM7EkHWbdaNGZPOZ3tr
N1hGxHVOYrim4NHZ+1gzIMWS5Cst1biaQOpsDqgiJCsEW/XD8dsbZivxqi4k7ZQ5a7/xMAu6cVZC
SSmeSu6vBqhiZub4EWVoW4zDe5ldr6GjNs8HrEhMq7r0Ktg0rnvVAWf+ZjNw2yeWhJW9NrFBr0PN
xOJlI34+g7OB2zghYDCgKvRS1bnrSTepU7qLnIn8dfY7zYsntosk3awWsetPvi7/p93on02qxNA9
aHKEwEu8wOT3YO4kFxNM/lTO522jAFYFQfwBzt+jStHAue8y14Wzja7RKenuNZ4xBJQk/j10f4rC
Tfu7y2PaoejtlqhlCny2xLVf/+y9wpKn8ZdRoh8J+HbIHZxHMqRo92DTT1di1vJVvMWm9AaJ03n5
A2COM3632lt4VLPoptnXeLR89zmmHja7Sc9MGl7t1BlMqExv22de0WBdog3UaIEPI04iDzpSh2XO
fBOGn7AHQ4v+VB8QXo3jCjChp1qv0g88OGgzGXYmaudgrFGw5Z+TBtF/pwE0LVOwe9qdtAG0sNUJ
5raItYiqThQLm6p0A4Ds2bm8Y25A94QJuFzmL0+YiGzcOkpaxfnrsonFFLM6KYfSNU6nmynzlMA5
jDmXbor5vFMBznR7J3aVHMNXfizNbMB4BUYv0TMIhBNVLo4u6vCKs2midF+VzaJxDPHpWQ/1rTCa
Se/yVo+j/Z0dX11yiI19AbbyJ0RTgfmW/pU3G4VNkJKEgZ+9Z8T3fvJXicytr9qmBanrL5OWJ8Av
OUYzqqRS2wrAr0BMgSdpguPiuoC6wMD1U6AOG11apQjLZioI0PZdVTRUa/qraayI9c/WJ+c0kaNc
Dni42ZQ9A5+1jhjFITSgp6SNxASP6JyHs/JxZqoI5PU0bC3ydEAZ+82ehqRpaUX+llTTnWCulJRo
gVytN4LoxdhPbSXHtF1k6fuXT/JXHnoC1usZ/XU5faTvS9XErGHJA/ul9ybhyjs0S1jPhw5rSGQi
FG6Q6LeWmcTZkt91K8rAOILE0tXU7GljzmtR8rsr6uEF1gA1exiHSP4XtheqPDyYfs8OnzvyzrvS
5C/0Wc2tvGblUTwJPhhVTFbG7CqTmZkJSMFX+dFTL53QRKCPhlVhpr81hTQ80uWF+yEkRmko7UX1
Xt0gZ9f4Dxu2CX036bIC/7u1iM1JOXP5goKB7dVf51//6r/42i473RPkVzHSI1ED1PUHGdoDMBhF
sqbHK9ao//guFu6blKPyT4QM8J7L9C2OlQh4nJf6W7CCUXjvfcmX1uLKRTVND60eV8gpS/C/0lWB
gyaOk6ROSYC6ftyvar3ze45tc217EUpliVuJ5TSGSPtkAU0TXNOXqvI5rohmYlwo5zwK8aQn52mh
kJdWsKrFdCU5v830SnNH0R9kROVgJ0XQF6cJNvwcqgaQwZ/BQBTviTmI2mUbPSq4e7RSB+b7LnnH
0Do7OSir5dMPvJU2rjrPWT5xttMEkf6VMC4jr46zIpWnuRvbKbDMGSDVebTnoBQMYIn/jTBLbF46
Bm+icW7jXjJEMtkpgfNxoLhY5s9G9uxz4fe1Tt5jOOQ0SRm7w0rcu41xntt/BWuOQJjPtdRNcT/X
XkpDRW+40FVT/psAIiiLck6v9SJ3PRSY4QYQWPmeNwBGU66l7AKOK7tueKoydR/l/N8kNNpClEBh
YGkMMAcLXHSDrjq9g2c0pTpXdATyDXFb26suMp0X3Pg2w8WP4Q4q/38xyhr+elgXTYDiwHVSDcxt
hgDFUnyVDNUiMZmg/MdDL1V/3mCCqFvXEMvQUhwgDrRr+s6JJdINK4fgI53SdanJkvUVDatw9rHI
ecq4g+HGtXul/kiLQQ8LpxikLJluRQCJhSfEUP0nisV2yUQBmVoyfgNJVh0gIoa3/79r10au51Ke
lRSobovBmufrxgNUV4GWImk8N3NFhqDNAWdk6vuWjcm4aH2GSaLgqP13XUY2L2u+TFs7rvjr5WNf
exoBqC20G98oiPbwy1zqMJK1JPZlOyP2CT02lHJ3VEiA/JXqVnLLFM6EN4Eluj4wG6+/K7PrGuH+
u0Af5Atg9PEJsG/PhCb5+O6C91OfoltLX32YpPWya3JCOw4bQHxpiV//18pw3Vor5ibvSlWH+TC6
ztKU0Gc+LnYvOCba8zUwcXTKZZWnUP9lJPMrj6yRocK+PWm8L6vABcNNG0x3I4ePWXItUL0zmHxK
27z9egBJbI7okuKCi1w7UD5OoOspHMvaa43IiB3OEijZIdVteYRh/g/sa0HoHt8lHmT9LIGJ4QW9
//bcnX9cwaTm9CAg1NyJ0yTSHc+2hwu1HSKYeHNOtOEVm8z7hO2zo+7+TB7Ry/5FSLUFvbjZ00OD
zk4PffQ5/2/1bF/0QpFvfU3iprjHbx+FavxtOE6OC8Ev/hcPbbmfeCbnTBhzuyoLaXqBagg62rpL
J/hLH1pBURF3pbLgHrJ6Q/gwLvNnkicpmb766VlodFUdtaEabb9BKwfNtXBVm7sJOHRcn5oQUpMT
I8ojVT055kNQ01QFJqCC/0Fbm4rSWXA1mWQD3BAybFAG3wabCISuHVwI2onm91ukkVB9O8GSAmnf
bar5hfh7eAeW174nbCsryEXeFnBqHEMZNkHN0ze6TX2QCrrEk0hub8RrzVIWqvKEAfYVI9XrXU5L
8joXPARMEIDMmT8uxIgOVAwamMafAojUzOHruyBdjcypO6I3LMedNipEXEreQvaaK1pXpoGCJy52
6T9dGHEQpkGu0m5c481WKOtP2OgkDBJLqk0hhPnpojF7q7lUXp9OPwPk6ztISO+rLOmQ77gWIH72
Fc6CMMX7TftvhMN0nFDBAZpe/r5FWpv8D05iPxQg7P/gE8/u0DcKmsy6eD/1r4fg7QtDh0FuTDCG
nx9Q3SXHlBOS0if5dmaJUzdTWoQd7X3EJSOVhN0dU+WYT5iZ+kCRmfQOQbuPj62m6lcjdqxvS4ob
QahsfkP1bwb1Z4lMqDs7yMXva01N9xV5y85Zvc+A8LwACVQ9eoZ79qVqeWJcIzHCXKs+2p/+kFNg
xLAwUAMVFDz9oKTG1xa65dxL3N/33D8+spXCGaZ8mKCZvQ0tPTr7f0mQqWREM1t/HGPU4bZ3o6hn
4e2Y1ImKjk4gARTbLGGeGxTgNm0NEcfXPj4wyRptdYVNEf/gyHdHSquGf2LWyyF/D3bQIbIB7kCo
xJ3mXLDdbNcD78Kwq08y5ur/JyxHaLvnr+ysrZG5DCro87viFW8g5e8OUKl4xmaDzNeMS0PzWTL9
N8ODVCtUpnkNd+qrkQx+shLtxfRRFvFK+nTAbO80Li66KDS4PVeg9Endo89kvwv1S+xlEO1W+4cT
pwHR5QaJJqiTWjGQz9qCVdgtqFLwaQWmytfRqSH5BGEEVqcsrhVApz3fK3MLvy5f7qDawnkPTAB7
n81cnJCAafYpvcIBsLxI6Jg0fUCVbnVG3FI7zfQt4RPZBdlIXGxxId2g7UFfAw0djqGuqxVgV1pB
9SuhdFyYx9GChMe3ejAgXb/dWcpcnDV7ONw2Tpss/7qtB3KXMKSl3df9nlSnkbTmoKlrZOQnlemT
5SI2nTXRvv9QyPnPN9DHq8By8ZLekcc8i0eJcA3ujDRSAO2p4XqEYQU6qQOmu9vDTnlhDqngAsLe
9jSKCmBls5JBxzEJGF5ZhOH4omlTW91pxAK01tYRg7MGOvxZFoCiRck75W+CsMAZzvHqgJNRAMZk
fQHPJBXczRMRP2kki57jc3Bh0IFuyIwntR8JEenVKndk+mXgr4k2Whmkw4aj0M/d+aTdO5wgHrQQ
IigsPHGUfQTTlQtzlo3ydH2C7AYSbs7Jn175dqO30WGFuFAWYXmzTrTHi3YDhGvvhLokZG40cDdg
ICgdhifWopWJ81wPCrHhPDbzzuusXvoL7nabNnLJmIE07Lc5kmWECkHJ6GDx7XzXhySmAZIviHg8
ws87eh5smpsNzYZC6NiO4bfodipaWfZFXAGbb0SyRGSoJ/AMCoT7RcnKkGPBQgO66G23ne6NaPye
u4uj0F58B+OBv5gWu5YSRlQnzvOMUdmVDP5q6nxxf9V4bLslUYR+OePEqYAdDGD3oU0gs0J7fQ8P
MBZKcciZbcsRf3uJSIMTImFnxp+t4ofWAFfDEoPJDUVJjsQ6TDfJ9WQhmpTSaU47MQqTWb90lLQu
NrTkBF625GkCbq9+jvhDHurzeFf3LnuDgu/bdkSrW7Fz+N5yY37plh9t9DgXVTuZFW3Nmt97IP4e
w8zG6SH8iKyfqdJCmM7PUTwNnmBXGEXH8MEgBW81Zk5MjpS5mApy57Dq4Wq/bQTLjRWkV0qn0C9b
FwG61oB/rHLGiCQho+gg7Td8N19Mq7B2Hz2JX335Wy0e5e8bE+QToaCe2UeecPWwPA2kmU2P9pcQ
QNzhYaAepLeU58HXjRU730CbwSyXPOU8NtpDNOrY2gY9ExcJeTgNOQU2R9NClQ19m4HFjYlNnc8y
Mh15XI0HHQWgTScd2NmuiMwEXryl8iL+P1pQwu3OtKiDRrWZOfkwzYss/Rt4ms+ESfY7lwWqIt07
gYNwec90LOpdLVfWj/s8Z1RmUF1IvbWEXabVYD9c3406BztNU1QX6jlV4EEebApYlF+p0jyA/wfV
hGnhWc764IdPr+rMrsIXnXaM6c8hlNRM1JGIxc9eKKYDXYxMCToSs3QnZMcZxkhAPPBohf06UN6n
CvACoQXlr3OspedOtOgemHuSN0kcQjTW1FAqArOn1KGuhSd62sKLiCOQo3OTWuI9IzXddM70yl7B
UyMHD548G4VkEj/3GgHwfDhp2bnZwVi3NxszQZ2wS9gf+Rn1uxNETFrG4kb5Mww2EiXs2ofWWTw9
xm2kxSQZvnbsF7KJ/dxLf/Lkdf7SCx5rCk58OP9eiWchHCQaY0qHXA8v6Uq/UPt3mgCcD7SLvNwD
IhdFiFUeagEAVvW/28uXR9UdCEopHwOtzBO0AG8RpgL0uZtlAxfDg5Rx/QQz8MdwQtjX/2e6yK3P
axdrxYEZs4sWekf3D7xT7PL9kRYHIbeWVtztHla/NH7/MQoh7to3SB4MeeWbx7A3HdNLFhm0DOXO
nlf3gL+4Hux3ekf8mCNx7KL3KqOhYopOH1iJSSaGf5Yz0hCwo/vDRxzfy6o5POoCn6vG5ZPPsnND
hUwBIVSSeHwS7yJb62fixRtQkZJXALzh3QBbVnj8ul3uVfnIAgXGlyCY1J15ccedLuDrdp+Na6OM
FOmeYSEwepHICf6MxbC6bSqDfwNmHPr0RFGhFq/xs/zfCDZKg9/+6fl26T2VPWz4sZWVDIQEwTGE
cMI+UUs2QU0l0/WrzdjN6yEmUEQLd9woVOw7pZC78/3GGXh+yEfL1nEskHRXSLgzst+XK0CgfF6K
o89GEQwkpCjAimh4caKiBzlmDGD0B0+5YNcMu68YmZ5NEoqlwh9nwGIRHAcnUPaWHvFmwYRDvz6U
S6q0YNCRDvhdBoZeP3twwQDUOQ7GhRA3BL+WSMSo2KpMl4W1pkkDIx4sXyPsUHHUbHMqXVbR2/yb
Puw+bNXJcwOyGMu/LOdNIDqWrkC1PokGQY7L6VILQMCUBmv6FxqYj6gdnIEC9RATW3m1NPxPoTv6
nctz1b8rQoW/F/9koBhrzHSekK6rQKZYIf5UAiV86rHHsqDRP3Dcqp88FyKlSoay65jHinTszgYR
XM8PnqvZqB7ULJVJfV2R2LDv/L6AsYFb1bGaosk3wyTaeEBfD+z2PlI9280WDDjFzENDEeURhho6
uc6L0DSRRxFLML7538ssXmkg98aml2rr9fsP0rAKGzA2TlwOuBUmZG/fhgX3zGfyrJPl8SNb8lBL
u450Gwh7GP6zV/qwGkuwHEBbcUCIqM0FlhNxnqGyeF1vXiAsERmCpdt4uoC/clBYvoHGjWOsvq5E
+p8UwlZJTmrSmy9wGB31Olnhi4AuJHbtSMUm787fHN0La2XgPxKPxpskj8sfpJurNvqPqi/Mmt1Q
5Hwm7LL0aKzL8ybhE5iOOHDfecG9PZJ98CyRG7IjNKpprKB8fD+2H80xyHa2QQSUE17Vs0wyV5h9
0gV9+w+8lGZjqbaNZ6Dnq1oZ9HZ7UCMnjrZwNbr0Xx9AbLmv22OwwXBDAnHkmAehkHZ2cfR+zQvS
5A3e+57c0Jf4alX4TLr4HZjYsobs+KaaIAerFp/RxfOm1R9KmG2g5PQqOZ1Ap1WajpBhGhrDDCxz
4eZjfsBBDBiv3rD8HgDe8e0c60qH/MCuqtWhsy9q74+pVt7vX3rdFm5AYsCjjCaAMApcNYRAjd64
ttcft1PbCzmgUj9eFH1H63n01VD9FG2GgJxG9uAXxbfUXNihcnIPSMS1yFM8jRb6FIJa1mwLOnx7
iRZ9gIMl+woTf1PzTUvafTb/bgx8TXH9SOaynkXmHJh+7xAx6vJ4Gz39sqvFJM/J//I8UduuvBIX
xguxAmoAOOwKZOqo9ch18+zGCYOcuWkD8r37xHTxq2iVENniq9uSU9pthdltROuKPC0bCX5qp3EM
U3BTsLxEN6tc0lNDDrK1cWCOERP4AGF1z/fu9amVhmJlJ82MRvzmudrih6eaATUtRahJfnQhD7lX
ovHkUFGdpy6Y9/IbgJE7yIvGClTo+JgfrfCOilGyz1lWiXP7bP971q/2qdLHiAYnUkHDI/G2X1t9
b3oi6fsbmNa2niiWlgqAWcW+d81Z1sQaKZaDLIfySp4YSTwqaAUx0NMD4tst2WMZ0HsMg87vbYjI
64+5UBGf8wiUzRByL8KwudEMWV/D1FvwVXTJFXcy65J2G/IpLrOkshh59hObSfLeNnuZBSYgB8/d
xktRZYD6b3bkE5ymo7I8AyFTwRydukRi0Tx3rk+UuOyopPmGzYROb7/8g8IhN9ASTuwy03GBarSa
KhGLeU+qlJCGBa0EuuxzSdTNcCEqAW7h9GDUc39nedA3lNrikQjlj+KamNcBTSXL3QOn49F44d6x
EvQc59tye5Mija/spJG4KEUDWCmfjua7TLK1CMO6Btf2r/ZPGq7O/TAiZ9/2YIDR00xa6lIeFUK2
EyOyDlyvMCIfJ+epNqNva4aqw5xVxwcjWcJGrYtacC7T/WqHkdmDu9hZvLh44OkfadEd9Dmf25Pu
DwHQ6ZfT5CrWNnWpTfoFDZtlgI/Mww7HURTBe1OkflTEwhehPvc4rVb8oO9NadoBAyLerp+8sqQ2
UwU289qriXhp6uH+69JR7Eodpa5L9OUCqqMTPcYJgBGGarsL1HseB/ja086Peypgo4JUXwwEYtIg
suaxJRojn+3/PZOoEnvfDf2S2CYevfivhEUg3jtGK64bsQMrIvXvWZgYQ2VrBlhKLKuvz3rI4yWJ
fcpaa5yP1w3XVOqOku3GMqETOU+wmhTFgvExczqoOSFbudrv2wS4GHK3R0qKPfyn14pNc8xf2FdF
WiEESw8wQapQOgcZmUTV4TL5+rJgv5tMZbbFQDE+IFZwwKQdLZsmiD4PktxpPeHTyE+c9zFfr9Qr
RvNne9wsVDHMz7RKIAJGdkLkTE7w69kEYsQyJAkl1ojZKxng8G64ctASiiT7UKLbUf0a8UmwAWe0
GcaIhHh4sNaayCqriIyLjtwcDHFhCW1T99O8v7g7+aLlMnDy1SkmhhIBajTdHaSr2kAxMs1+8AI8
2BsCP7r4xudMwCfC35b6AICzNZdXX665kJJQYA2IR/bnNqZmJMKbP4rJTGyBjAQm1DhA8ltUZxHb
ZSBKQ863mMwzPC7qjEQs/9se/6P5f9NxPptKqgYe2gY4fZOUnQnN5zU6VeD7ThFnFw/Q0VMQpj3r
0t5/K0BKshZvh2VGKGTcaq916/wPcRsdRCIVJ6u6yRe0EcslkJb5+FnThp+WIV4Vj7/Ckl7pNII2
totpnO/vl6pQf5TxkD+amoFmPNVwXOCCNI4fH9iK+6ewOELnm2gIBJmDmf1gopdCeTSCB7ajy7hj
pBqA41ZKXPkgGr/QgkRLzmiykkP4KUjW/dlEXY5/rKB60DxiA9shtrxLd4o3UsjjFxcCUJejwr4S
d9cWO/y98M9T8IXbiz0BQzzJ1ZHpLuY+IyhP+PEHvrfPbn5l8LHN5FpNHb4kZvF/pHvJBdIFBGXa
39ycQWvc/seAvxMuh1qZXeQwsHL4C+DqeIbuRNcwgwAZcKiR0QdYhDUiUsHxMS0uIiYmOgXvfH7C
igYFYzd1dv2mDPgUct4OI+aC8zBu8YJxMt/tPNoX6/x+bg0m7LC+jfp1Qp2c+TC04eYUm8Rj+ZJd
LOksj1x07toj4BeVp9KPBk/XYZAOG5evYETLoAOwakF6KKK0u+QAUt5IO8/rIOTeKIH4poTPOK+S
jvz3e99BP1NSp0Cs9d8saUdZtEDWq//HM2N/DU2IQUHA5ftrkY8mZ774RASDV7yZ51yknrJuSdSY
9A27HDdyFOr1EYNat+N8UEkXe1QYLkP4H2hSucmUAtZ7qPwNJS+F9k/rRHpGu/26fjjZZ/PLuEM7
HZ8MlRj7zgi7Ck0qrPiXQ/f+ukNkJcMkZ7tc9Sjy1psmFGpMmSFD8ZLZGOUtgjmLVUTfIMq1xu5G
eL7s4vMIGrHCXMryxDdqpmmRgS+Bu+KVNuTaD+1ou0ya62nhT5adSYET/zm78hP6NJMGCOSmYv0z
Xm6lcLafGS7QdJNVU1x7j9tpezUxRitT6BpVSzrfYFv0EiiGx7L2jWlpUJJC9vPVXMO1FphcIBcM
kS16ppGSKikktxZkRAZlHIYRHifoino18gFABR8Yh166VD6N8F35L/ABQugwlcU9dqCiSqoyWntn
KpyeH5TlD+IrXTFH2jhxIFQiSh4zeNEX4O0zFwmBX0SeEhMS/hSqe7A1+JDKHs9a5k9Tqn2BbUnw
8sgMBCgXu522VnTpyUf+K2GCBG1L4FvS81gChdqBh90iksdXx3CsqtQZCcKQ0vv0xnGKax4fbMkV
kun3lC74v8Fhdkb/LC+fmsvb/POosPWH+YjjqxfyPt0mJb4dT8WU2nnT1Cu1Rama7w/i7ZVsI7Pr
Ucv4gzCg+k4+hIMtMSGy8SSsFynzc0TBIxm5v4H0wg4znkhsuc6WnOWePgOS/HNkFsc2umx5dJkY
1tieSG7L/SKoxwhzdnYfBDZ1FOfOgA+N+IS8zkYV1BSluXtbh6vpsCwLify8/mWtFzFh7X1dhUHF
gW3Zs25byqt5NVY9xTOhK7Q2VFmKayCN2N4H3NneNcme6et/zk5MTyzHxA4S4vf83TU/nbMUyhP5
1/hhmX3/NhYDd6sEb/UwWS4lTLn13OlbPKAaB10cC/WfnSbX1SYXm8Qg1ZwXW/ni23SJGV5KZYrZ
SzSdicm+WMN92cKE67l6TVkyZNyao0vHPl7nov/bgXv0FmiCGYhzB5RlU9dewyZFOAyGDjB/U41P
SzxMaRpc/Ux6SOYvE+gyScsLRZiXucCLXFIy9JPjJMJ5FtlNE2RbOf4Fqp6YxtGMNy839U7UTqnc
p4lR3O4j4lCqvWI7bJ0les/RVlQJ1O2npWXrqJPatk6G+ifrcnMayXXRYemHMR9MWUTOw6G2vp5K
wgzOBeg0y41kfzFXjNEXVEC+cwI4Ku+wv2uv2HcOHBEgs1Phl6C4KIgkynL9FlyZjiFqxsbu3cFv
pr5/rdS7toMfMTK0icdUwwIlV3SQAAUjqSqnUs+WnpuiIDkPnCqeY11HOOEVc+uXYbHwnquzn0La
z3BkCSalgNS+sNouqBZf5y2PY8cp0JlCF950Me/7tbfXVyS4nNA+2190N4XayEcJmGIo6Vki4TCl
b+u220tksOyLjNMTtOFt+kJeCquVGa7UUXFfCkrWDNlVa/KjTtzSp7NRer2Z+ADL5B3WLRD9xkBj
zVu9nogoIY2UXN3g1ho4PsYvMfWqPmFN//RCys++gGUzNv4b7OQMSHspfI0Ufe7Xegm7U0e4m3em
c2x1fOnO0coBx5md0pgr2qaA5dAhugJryrH5pgiq9/E3xfiZ75sjhQ1LiGrvy5mv1OIdZruzirBD
y8woxPJlSZztMy9U0Gno/+qzw5vQLdserPxzZRwv0Ivcdbv6oxc6REA2Uv+RjD9LwZVGM8vo7Tlr
e9i0Ew5l/QqkS2/O75s6M6/c3gS1ofsqJ3cz8VzdOaGVZambzEHK7mG8PStaa0GJ6/JSoqTWw+ps
WGXJh8OLF6BGOT2JpfYMHF5m0Tm9Hp3A5eVIpBc2w6lXSn7jX1mDFv847e/qRyKLNB70ff2kowvi
rNXZ8Hsa36ZxFIG5MLQ9HU6aFyDCljhbf3ye21i7WwrcrtAaqud25HSt/dooTLHhb/VaVNqOczv8
drZkcsGb5f8cG3h0D06bikqvjV19mEoJVJ7em/KtlOJfuJ+sKaHP7BDfXVBff4uYTTz0yQ9led9l
OY7WA0jxH+/VeTGTkFbZacQ56jojmlJsP/+Vyo29Iu+ynxGxkDqx8GjAIz2E+D78WSMmWBAn2OZT
vGFpLrbU4ym2Unb2LGz1jZDm70lFEUVAIOAAovPW+XFP8jrdW7ydtPTBkOZRoMCHh95rC6Vte5mO
XIwAvfmY4evQXUTdgYJvAofwzQbE8DQAmwLVMahwdJQbACj4nUNwMVClEd+YAdNRrXTZ3NkbGRYF
meceQIFkz1H8yOp9nH6utvAKtMjIHxn4Qs/hw531v5hiUqcjPvVyo0zgrUY/wrjHWfSw+4CwRsc1
qHaGuExGyqhTRkEKJWSEz0d3iM10ZlrJlJUjUkopJTEQZgdjenDBuoTKLU34thK/e07szzaQtwhs
7B/U0mLO69K+EFawlcVEqUeSumHy6shGL0RyjYlthr8enG0f7xE3oPeIBrhieR5DbXspFSzhEKel
xggj7tBXA7jgYAtLGD+rNUJZOyep/lTFLyaFHiEIoprkLqGM5j/veH5b3ieMTAC+ESGfVl7ot0ig
navVzHGhNMKRnGgiYMulNwiZ4x1QJ3/In+CqC5AgCXLVW6NlF17CLcue2kR7cPAN9ym37ReXUcvD
ibRB/iuIiXd73z+h9DqFaQXx6yyRjv4R/B1f8BPCpdt4R1IPjTMW+qfjtrmopNRnle1hYHulb1Sm
78PiZdT9rGTDgBguVyZGCbnIF7DAICIMbcQzjYpKNY+yM4vkKnrJNYRuzFV3Pj1ay3fK0MR33GKF
I4OJn2Y5wAUECJ0bmxA9azX1qjox/PRxfdERu5CzTk5xOAwTZYqiJ9oSowbCAqUGv21gKr9N0C4u
uL9/gyPVFw1VH9gOrhKWRW0bHAdM+6IUpwAeCZuq/nW15ygBWcFymrE5+KzNtYgAYO9RMVQXitDF
MXmgshpR4scT9pszLvoewy2F+bfs367Og9Qz3lSIibF4yMZSTfkAUbKGNpKu+cGp69qhvlmA7sYv
lQLZe9ugmdhGTCdCwzX/u38/Vo3VliGjrX6+bvffTLIUMKjooTurSPnz9UFXdIdu16pkAQ5+41nx
C4b/qH4rwfo+wAgd97jaWLQ1tzy/PbkHHehuNdeoOdoLCORzCiXpr+TMfemu/JP5N5P0lR5Ui2ma
Mko64yDHlGMayJrU2d39vv/mU1EpRjw+YGGeUtED56Uot1T3JmBkDj+TeEzvIjN94IvuxKx0DHBN
0NGI2JzZuL37sv0oo9tnbNuxYGTLkajJdcpxjoYG2Ze7PnuZO0wlhq9ay0m47qJ0MbzemdI0EEkQ
4Rgslbd7rNlHyZFIX6Gkm2tCEZpUs9O/e8hnYH+LEFpf8D4hPfVisSjQdRp9I+mx6+6Uj4PuNtr5
m0CwCpEwSQG+aUDx1GfADPFEyXt1Kl/3v9uSKndNOwgmjOHsoyb7ZbIOLJWmHvCU1SCxcrqAhMiX
4/7sa9jvMw3gSl83ETSMGdU1mLW3Hi5smN6VaKzXovFoauL31jkfe7uCVoCWiCFSfva/rLrvo6UA
WoNN0LDM3rkwvDr7wzuhJ5kgH9md+mWlH4oDnXaJ2WOq9ZNFIrlYn+v3kVGdmgO8uoIUnZwmwwgZ
dGJQVmk49W9oonHx506uxNjYyL7UgoxQcfj9+H1dgasLasixlwypIbY9HSHZwlxQBjSTsTczM5Ix
ajmYL8Nm04KYnfLTZO9IlYUbKka10XvTf53vHAFFwQ2lz9yjqja4AmPYCbDGlrvqc8BPl1rqORmY
lLKLVz+xX219QrNgb6KuyOfD5CxjLMJhFqPms+CE9qN19xJAHdb0lrGan8qqj1PtkX1EC5EnmsxF
HxrM4zYSod8f63i/0qEby70Bj2GJt2p8hneNGLHDNga4qd7ImpvWclS24dGndCELU7Z9xXlyz/ri
kijQO9NUreuancaL8h07EA4zbq4TYHIhw7FpDLtXj/NXx4cUzABeaBygWthIfK3isyYe6yfMnWW5
nIDhLMo4KJ/vEw+zg99BTLNt68Jl6RVVLLt6uXGqwFqPIIsm1uAVnRRo9CbVLh9aSGqktR6QlZel
KjWaXNptYF3AxO7W61YPq10wC+zidEum4pOnZoL/Z4nF/7o8Z+fZCeNVbaKq79RKdZfGcHybc8Hs
J+B3FIiPLFvLT+fMgSL4KBaSQvU/dwQ4X8cE7+9DxUw2eHjsaMB+QhYJz+hvnLG1GQuEV5tGCpFd
mFeg5nWz+YdY9EYfHvy3aJ17HIjCnQr4oLdtgPvlPj1iOw9kYskYlOImNFQIFPAgpKZIy7gCsgLT
Fbz3liOtYaM4l1IOa5l8QvfvlxBGLNXmBG3bm5cDdlGIIK5gks2ZfbP6lUMvNjyjuNZCPQm+s8YF
XP4V6w5jWeI3+sise1Gq8C9jyYlZfY1GKJp36Az7fyBgEvea96HQlYKNo8UvkLfplt1lHp5w/Dl/
CjWxX/H1XaDfsTpwaXLb44m33kzs2POrmtB74rjIwaY1Ct7vpLpd6voboHWvuE252ERfCVCrNJN0
XgmvEz4nhk+7Ac5K8AUyowWsAmXh8Z+znrFIRSSG+UDQjSXg9CgbUAm3f7KNudJknILdIiyaXLEC
n3viGaD5jXOBNXQOyrtK9OtyXwqvs+VzbakPuziYGEahwP2ot5I9YoG9+YzGl4KA7mbYW5CiRDfM
WFbz1988wAZrD2IRTkUKeEUCFumfMagneyk/ca6ebt9PQ54hQ++aeIZX4n1AQM59wpxGpOe8VjYR
mgWYZFkeLHOSCEjG2p1TkW6vgfjqIFs40/bc54mcSYiwSswmimdP4+vdft+AlQt/Zh8CM1egHXhk
icN/JH/c80Q7Z0RHouiIaFmJpCN3ydjrueyYQ/BkZ2eQ1VWyUGrM0l/iOtrqC+km7kugtgTb3xj6
saE+5XSgR4EqvlecQuP3XlkcRx1KtUfvwzHL5jXKvnu/BTPdlAh/XnoBAU27LuHKDwHl2HYFNtcF
UT1eoP2hCenYho2E/jSAUGqKYRhbPLEZbED1zalqjzajwTeUCvS+kEF5NknXmBTjVkl2OrbLYwiO
bW8+8QiEu7ISB058A69QxzXT/QuisZ16q8XfXpMYyiDV+fKBM2WCUIkkvKkCblkFH4drY0D8B24S
YS0d5Cx5WzaDH55XKbfMEWUpHRKcsO13bVNbNNJO/jq55iqM9AHjCx1V8uFCfPt/7UjFCwmTFh2s
fRFeyEmCsUauhBDbYe7ONq5lYbePfcNt2jFwN7t4TzxbzVkGTkgbi3yDI1vyHAupbN7r/VM2odiw
crVd4LynhhEi36NbO/Q2AAr+wLaOImE7JKl7aQT8LcASODU9ge9f75kc9U9SRqMuUvjbX4K3cB8t
bKPzTEejtHmgVf7L27UpZPAwyqmVABtCiAYW4lAbM1hZm7KL76b+8WwU1GAX2zJJ2d3Khybf7LYO
RM2Yob0QEizkfI2TxlkLdeIytCr8L6U5aoFBCApH2sVP7kY61fdsf9B5nyHdInJ4wjL9AU5iGUC/
4UrTNIH9alO0kOYQhPrv2jEy9ySb+mmQAW1M3hxlT86SRc/mOOw97cb1cnuMFFG9zsgc9EX8YZbZ
79EF/m8YyCfWP4AW54LnOCZx4f45LvpDWjryy7/twrGUvAgqVnWvsQLQja4azMFYJ/oY63Wv58rN
O7l0t0/wfgx6k8OpR2K8ZLhVy25lUe8eXFQSiaASlGiqSIcb/F4PHVE7nnQTJ81c42AFEqSkTWhf
X9ewTx2YhxTozwUWp3hSYKrpy0jAc7ceN68yE5NhhVvg43rJbTzEmOPaoXbsr9N7z/W4Vl8DQlhH
ezrdaTCTqg2hhPwIBuzEuxMHi58jSTe5FtZ13W6tt+IwdDFZ1+f2VirLHj7ySo4JULeTkFhehY7s
cPjgQwMr5T0d8L4l9msEmb4Wg6ec3Xq/cgSbveOHmGx1l0lXwlWIHjSQ7P52NI3DYfJVEGZJf9yF
3BlDiF5qax1V+qJfMpHMdu+nrS19+OzcmGVbybptUG93hj55CRFvfWX9f8PIBfkn/mHzBy9h69CW
8Q+DEDwUJSG1PFdXVR/E0slxogMFfFZVUbspHmV4yz/JNskh+dcihxEMVu00WRG0eFRm0RPqmGKF
0LY+iyjoy8KsulRps8K8XG14y8qFTgAW7CHbh1vHLyg5m0tSJsgEaUCnE/OUHnmuPrr0uRd5GMm0
E+uNF9jlkIhfGw/bX+5vqUhJZ9DnhARPTqG0DYGumpiqHy6IEj2OA+sgsFgtbMFNKPJ9405YAZrD
Ib3Vz4gUtq3WQzS2QBA9Drd8FAiGznKht+8Jg7puUwHOkNYo4rMZTRVTLayFB2dX0O7iZA9QVJXX
HolFcwI1ylQ3Vcb8lUv6XCQB+PHvAhSjiHVxxTVBI9Z47/AY2c+W+bquLn0rsZrBbzg9R9gpX7pt
8nUxROwm+O703UdTdhTx6dcU++IunHH4WhQ6711zbkEpzu/wBwOSK8CKbShBpJZ+iAHFzIHZtC+S
CJmjrtmAEhlfRYCEp6YA5LBxpobqS99AV5/573IDTiANZBrd+1VG8Vlj9WR6bSajr2xAiH1cY6cp
GZg9CqQln8KZrk21J4hr1pP7rXNU6IVLJqp0FNDFPCWZint0l8EshGTgeA9az+1Q0oUYyhsCIPsu
QqKx89vxTFibHxiRiXR9Mjsn2/MiYqpeK2cvu5H7E1gteBnsLD+OcGYKp3licaUmZLfNpZ5EuvZo
16nkW7vsiBiWgg/RjWyKDoRSkO7SFHQWXGV7o+Z5TchokWBxC122DO5RyC9TcxEVUci9tglPh/3a
yl7dlWcIFucolWWGmwdkXIqqf54disLNqiPsmYKpT0OAaQf8lrZpPgKq1SZM/dbdU7qBZ+WdIDXt
6Sz8yxX8U9xw0g6yY9K7Yodbk/mU/6kAxe/dm2q1/wS52cKZYv73jGpq8bbV1OLI0ihDWhpBNtHw
hKqLmoG4tHJ09BEhZ7mgYWVsvA3Gc5W/az4iDOQNHpl1o87uGfWQ5vXBppzig00HzZHhXsnI0zWb
KNDdC10HCj8MNSm961PcoRcryDkkI+eKZ9yC4JcR8qQ2jcHzpuQp5wNlDLr4Fafva9ukGyE9ccSo
b8p+gS2uohgRI6CGniAR1Q2vFMBkxM356Id1ILyEJGFnCUfu+A6QsHjtCZzHn3MaGFUvU1wJHc+B
nq1QMbG5PhTgA92dCzqcFxmkhZV/MK+B+xtoyvHH3OcaJ3QcTCKlCcu2EWtdKHvqatGCN2zdmwa8
q6Buu9iZj97ZgeHHbczJ72wjhahERJKkzbL//3stBrNN/C+oLNea7jUxjHPwwVMQ3BF9ziPZSFTO
CpqY0agLKCWJycYYsUfSov78UEV5/f1mSjAOM21M16mfFAdoiVhXBXKxHA9y7MN1s1Yds9NyOmol
y5mHjB+zWj0XJ7KXG8hf9pjUos/nb+m8JcogW0wdc6lDJVh5w39i4LrJkOaloTtAwWoZdJ+cwM/n
bpEBZ623cS+xcIuELOAU0NTxkG5mhlI+ulGx1uTpBrNqbEpx0a17hmtF91kbEPW9qCNY7v9h5A/Z
s/IedrBB9fgszbu4JOK7iNqm0N/+6ednMQObZjyG0wCMgQ+A1h7avxr/6Xs+4/1KLVGLWkuMR1Jr
8D2lIcBEXji7NsXC/qhhuYKWJo+RtKW4VxTmIUZDDwlz2PeJ9L5XoPLmRltkYmVSKd+9fZenjLRq
idc8k9f6IvKyy8wBAuCpooIgx8LVD63F3nu7TNwgBsQ3x6UckAunHgqzeLjulrmbbbDCdHbo7/Kr
tSflx72kwKnORBEQIkpDocJgiagHqVpkjQCWEAiT2iQxU6H6Ns8TJZtZtSn7LzjqXdPAKPzbLqrf
szVL11fSiR3eNdUiDOKOC8FLltSlVSZjxJUTQtJSjJgdt30tcMKJN4wCavhoRyTTQvFrSKqvJuka
mcVyHV+yY1swybg4X+ZBgaMZBaO0MuRWCkuM/nK34/blI2/wPL9naWbKweW3A4lp08XukrWlYbZQ
uI02GwiKemYWsEvaSo5I26qiKpHdDetEiaJjabKGiw6PbLrNRWA6yyLnDTkw0n5ncrONFKIfF1/5
9KB/7DGrLJBME/QoHEOvsyTIjymKZ6kLrHeP2kiFASS98nvWMK5bGOQR5m8C6rPIHeZjVJdgVd8L
17M9t7wGcSkjXMQkPd9RjsVOU784mNBa6sFiOYYIN8LhNhSdfNlI4rLK/r8hOPd5S6x6vYdIzp2Q
HBCQFhcqDJdzCPKidCr2wgAdTUii9S0Wy1vkk++RaYNNBMTjo/JcqanVP80zvJJt4yvm6gZPEd9s
2OBCMGiOZGdep+FL8iVa6kHcKs/K8fhvrnJM4m7RCglM8kMtuu8UmRDK8qt5VRXcbTyJNZ696bKa
pE/BpZRc5uHMo7bTbmqvWXI99qapMxN/+1qkzMn6s5GW0+blIn8boa8AphnUKfVvRiEvFn1lceQN
vO9jSqCBbjjOj5QGNC2HHDticoTly7w3AugniyYXvjwnGF0z7eDyIDcrhFaRsK2FG8/P/KdLNIFV
oNR2yFaFzOJSD/5zAbewMyPoviUqY7T7IKMHKbxGvn5k0zoItf0+2tfqFeTmQyVVr5erOc4iFDRs
4eur5ZjXlzA+UwIkLWpmRtW45/QNO041tNwbPQj8j1cuxGiHMRJhuSlXawHmFhiQemFursPtlsbH
3JJWRv7cC3Sl22e4K6044MGRWoSCy8BEv0FrQFkZouCjxhCPzbuqdl7QrsZHXDTYzQevq/O7GVA8
kb/q6j41unZU4Rkbe/rsIgI1JlCFN3ek8QizWXWIvbD59CnPSYbZfZFU0NsDDLDnlk+pBvZizMy5
oGRjyWDfFh8QeTqCQvepx072IKuRfog0g9VrjXfLfqbyqUfmHpx1jnDwWxMdMVZ2PuxTI/y7dyQ4
gzWoohOXWRjRoIvYEDu5xjfkDbkkfHjaLXhWlOk8IylLJetH6/zQ2Y7pbBwJ65EIfiqNTSFsYXeW
YfXjWzW3UuAg0fUCeJ/rXUjvJRyjxLqapLOOmakTZjR4Erq5VYZEl5t2ECwsfVwKwr9eysrjSVmx
NL5sY7tsX/Dns4hlh5NhdViMdg3U3sG0deLgEqnDdTUrBdae+WBYLXIU8LXrU6xuqS2Q9jYwgMG4
JBNVft1CEsfmLRahrYQ2z0qydyHyobQ3px0gVtvPogQjfJsw3/3rs9E8MYe+QH/lFnMI+ajMGqTK
YwEMmt8gfFir9TAG9eKGXRuDG/dlu66kgdRpddxN37iIsdOv0jue1lXIgmMcPiI9utyqGZAZrdAK
gr49gAdRy6KjO15pcvGu5zwWtJX/XDbnTEhbC1Z0EddrNGvAfl4fekyCNdm6mSrPsSyN7ZC0tA/3
qJOrpLIk8BUL02HE7gJNBONp5oo+ed2WF4avIDYYz6ZEcVnCBQZ0ingI0oT7dT1A06E4hcPEDahI
WwXZGdwk6Ds0ezbPOVodaeWuVoyJONjaBRYBCXX00Vhqq5NDMsPkSS84/btqMBwj/oxGRDRnjbKN
f2uX/FjnYs5t1yB5x4AX6HDfnjkI5ddhNHQNrb3qimf6amKpMhGK/Di/qU1At4fdjJQcFc1z71Tv
uP/yezNytE07C/ExOKaq5HxYyQrRJr4dDmD+WIkqeUwVATit27zVI1ftdFZMl0/osIhD7M5h7EFO
3itxBzqakf4Ne4BmxANV1lWLvbN7O//afTIChFr7+PqBG0DhlEZGJ/RB0QHoGeqWFMVEftu8V/EK
ZBhwvnhdWZnZSmSakk11pILF9j/8X8jZl44xDb32hbt9/nwZi46TnUXx+0wtjYM1+pKWKB11L+HG
qSULbWO5J4H5Ht9bsMucl5zvz9DDXIl2TxdQmgTKFQ0cjsJDrPe+MO7EaarZSvKba8zV2YeC3hyQ
NAZmno1ZjOQalXAfo4JPP8ZHF9v6PvqASoTAMMWK+wbRLpgGtzn37KwpCQEvkz1UnV6vf2xASNpZ
HQ9x82lWjYYUsVUAapa7S8d96FwekNtuJb/av00P0gLIPMCUsH0KdR9zkGP/M/vM4Csr8YoBj8V4
gfasN6NZ1WFkvbgsGMd1LJ9STsPX5+WYbQuEY+ZwYSLCtU2KMTzbD5VpmLYlIYYeMDqM99CnrFun
VB13v0moatrSVENxxhNkUzuFdI4Ymt5um21tYSNWObFOjs5kuv7m/9Tc3ZiJqN19d+PaGt8n4TfF
ynD0CPqTgUjUFtUfzBiZUnGO7zt6/g64zUy4shZFuQ7VA9dEz5l8ukVVfwAFhPLCkQKahnr2mkq4
Nf2c98Dc2j+YqlbYKHUwFC/ODJTlK8z/N+uTlie5V1miMvm5FBO7+qlMZGuIRHLjvn34hVHTzBG2
Em+h+RX4Wm8HV6bClxKfjI6XgnyIItPZ5DxzShQgCE01G5x9mjhtfQeLt8M+ah8eYFdm13aNx4rt
SCo+X/99peCOrBauJufA9oelR/oRtMBx0S9MJqTbR3Cn5deaSJBGNRIsCAt52O5DZ3caHa0JakBK
+lJ1YZeGXtT1iLKJmyF8eczLvd7iidgyXJJZ/XRJIJI582XLjyu3ZFj4nm66oKL7qrua6njS7an7
hukK64dF+30RQa/mxdQGx8VQRnA1zKU0xM4d+gJY4l+ySQlrZle73rRK0JaoAxZwGhd7sVAJF4Gl
Y24YZgDGjmwaiK8leJk5sA+4/mmqC6tygp19nE0cvX/JT+xDkmiERufVfI/p5S9vxbski5XoGAiQ
zleqOynobVP9YzK6KVd4HfQv6bEctLBKPAYWQimtJJkcT7Lqe8EUGwBqvPNQBzYq/CutRcj7aFK0
lmOivjR/VpNYc1Nd4GeCaDGvLUBg6BJ4D36a9PXmM5jnRAjqKVwb4N0MPW9lzhnx0f5o7uVH+/uc
B7WHCeG+8DZ7QLVG97slBj5sHq/qce+7rGvNBlckmY26Os7kJ1DYwgEoQYG6H347LvEh+jcSxpSt
QegPkZgmYMIAeOr/7X2T/lbL5gxbEK/blgXyPLqc7YDWQYNTydySUHDcfjc5er05IbGgpMUFrci5
/uPIMawGby7jID7IA/cN4F5NrhjTOb5FQ0CUpT35BM6ZbriLWKjv0yJQSTkXZ8DCaj/qwV4iXaHC
M2i8fAayGVPj/+cL2+gLQuurEGwEeJwN0EVJIdbx0NJVOext1P6T6lHsa8FMYHt8jmzXnfr8zrdK
2SDSR4RhyGe40WJ2fALtJ0hgQLy6672vDFr4QmRJwE3JDIf/ssz3pse1A2DHw7/AJ+FZ0SWA1RlZ
Prl6FA6BypJtTwj5mxfwPID/Ggdih+CkB0PyjbgEgc0zndVthD+ZEFIE26PV54IUXr2axsOgTc8U
kyPtb62zeTa5JDAQqF2kI1spL5H2EEE5uIwLbZ5DCeCrPlgYOxjUhfsci+9X/Y4P4BpeZnYmXMtx
OefRBT+XY+8bGzCMu9K1rB3HizM01ZR3T3r1azJk8w34HQ7gVFkoxF0ZKvyel8QlNPtCOFnb8vLT
hpn0TdsP23eRvWLIV7GCxGGrr77I+3J1rdWAsPt7F6TKIJMnxcn4xKxHcEcWA7HUc9Jkrl0q+BTu
JsD+5oulvu4nsvFjx09M+rtm/k4VxRr+Jhg4ePELo6kLAZHkXZdEFDre6C11QFqaYWPTWv8BxS/n
CIJpt2KWpccdJtX2UwRxUfcGkkk/+StQtKZHf33kp2YRkkYVFuxqWjmm04lQPPHm7m6FbgwfZaus
QT6GdsrLPKNTpnv4rPZfMWPNW2cLjLqjTW55WlxtkEInvw1vMxFJvb8DC+2qNknAMUgiSgGW1S2Q
CO/OjJhg+cA7lP8P0VaxPb2ohDt6mnvC9wc6gPP8PQm7BuKp3lVc8IsQHKAzvYulLKjNKWwKGSqM
vAlY5F0oQw5J/ls7GC2IxaLsBxMcTIB+BrSZ4HPfIXFkkVZIb69JRgGPjr9ZCR+SdxRLkKRT19jq
76MKSm1J9BrpjLpJUl+RqCUvdaaX2sdiVBWPVfVGl4Mpm7vQ8rBY+EJkAnjwADdA9qWC3y7UJBcQ
oU6sUynK003lzE39G7SDd7xG9lBkM9b3asRgCP6PtSAUzt8Ou9EKHfC0cGbyze5gnbUH/+5zU/ih
dW4McJfHUfnKx2ZLbGIAalVhnP3AM6GeUjBl3AWh4GdhdGHzGdTG3rjavI5ujj5JN5VrOIwkih5Z
Z1NKrIOGV0nRmtaArYq7iFhnj2Rd8iiGGQXoToC+FL+mB+MTpu1l9+Nx4pMBgdVtqpZnk+fTRJ/F
/ZNeOffMJ2jpc+Q4aYN8LYRhBP2CPajYm+7fw34EacmCz8X/w5qiTvp1WuUvWsl1THYiNJy1fwko
uQoIgU63o2P5OOrb+bxlhbugaFIVUPyv0HwrcQ7TvPRlduSmr4DKTmKZqzXFHvCLCOX+h5/iRYHm
seQFWCTEZl9eKqMmslP4doZGybW70WFmi0VuUYFOvefIwi+RrmGToW2QPFbC7wcCr5qo4NeV9MCt
gkG8qTOiBvRAMI2agSPGSO3qbPj7FkQEOjW3fEi9moALGzATAPLpc3pwDyNih3rgQeTktrhxjDXd
GEiRTo5HTo2LWol8E+jISay/W7cmyQu6jsife0spdZxx3i40f+pu2aoUuB7jGO1kMshU0lQk7nFw
KjEOIpbuKvdcvnH5ae9eKyoXTpvLPwDzIQNM00oZho073ze5wgZMgmnpHiCuyOR9OMxz5QB1VlXW
wWLkITuiKLputLoWEPObwEm9MMePUKnMTI5L1wo86s1WOMc11OfKVHDKA1zTx2DF635/+G9+Kr50
jEoCfGL7fctCLDg5wcXsY6k//5tLXfr7+AjWBoHtMZwXZ3pX81yecVyKFLGpv7S3y1AJWRm8kLYy
tTHTseAImi5Rhu+7p70VcyzhKz3zsxWNdm6sOjYNy/hBNWwFwNJT1fyAJU7ztf+4cBcrymzJnhPi
V10vGPrGsqcDvMwBO0cW9TwNAM/Vks4pyTXRFKWvj66llvroWes67L54zeO6pHmdpvnRdbzdkV4a
FbNMQ6W9he7eT1SxW4UjNgB/mQi76Tf02oN/Do/iYhBj0DlNbSQ89iu5CFZ8ZTwpa2VtKo0MTpcj
uy96bpt+Aejstx/FfsrLQqGyHW+m9t5Qg207BC934xAgysbibSyPj2D77SOvUFTN+GYGQ46po3hO
JQZugaWuqCIQYqIwbG/mqgQuA9gV3g0LQLui9GNUyH/J5K2eUaqdKC40U14+0VO8acBztLMsq7Bc
AQA1TvIQUfheL+rWPeaN6XE2/01YJaeH692KL978RycALzzG2svIgASsVXX8PUhbEdtxc+O3m85C
IoAyFjG91xknLopZ2/0tlrVjRNeD6acul+0Lvk3FaamEETKy8e4sc1govDD3v6sVrwc1ud6apPEj
fqWdl2sr/kmMgWip1b4vFz0zDhe8Ljc8YniCGlCFNZyGds+a1siJVbrPpIXxPDmMGFkY30/lJ4HR
hAdYd6/BltC/A4I5kU0Sw/gm1GGrCoIbk7b7f4DVqCVD/iiB6C6TeklhXjtFBzttxvJj4eT8lmDt
6uVix6eOr5fdzWGcJ/UBiXv7sVxXGDIqI6m/wJ5c0g5/sKiGW7Y88BjF9nbYtLfLoe7QFyt51mI7
XkLM88lIW8/LS/PIIK8AqwQh2HtbPfU7Bx52mEoE2abq0HK5ZD8MYiqQWMTdTisE3ZZ96Y2OthL6
NnLvf3tc5o2cFkbbjTnkRBeRO4G3QlbZ2RhOYqx6x7viTcIjhH3Xw33KZuc37y89OcQ8msGNn6Rw
YpbXHtJoLDKAjt4VXpJVja5VO6exEf9Gg+pY01ghgjQqSd0GnEhGXZDWHA4wqMYEIlHMQcclaQCt
zG5yHiCrrsllDT3Q+fKtLTEhzvp5woFJPNdm3oWQ/MyDvhaYcYLjIvf7jfwBEW5qifJD6CVUAy+d
UXlrAsMGVdaEWuuTwognX1GQEXCj/w8OORsBoaRUAm8QFpd074qXjUSkXVAUYbFTgJhgKbmcV3zI
8dOEl6gZJoCWF8QDBUnDAg2LkT+rPYEHWJ+I7Ix639KOmiGDEER9Jlkkom+NnynsJudUTmRWbHOU
zN+26M1kZC1JYjaWJm9Qyne5oVjLp2y7dZPWlZSBH8qD75YagqLBEV780wvSXiSxyrmo9oW6mKCo
QkeFEf80uXcXMNejX4CdmmIBDcEY5FN1VPMCx2GQVcn5/INvt5J8iR7Dd6nUuhHyMdQIf9tXHqiw
22RvW6KsmPRo5mK0AhWwb9PMohLsJEAZuLXFprsh7AD/jn5MURODW2Mo2KX1NNG/XhBn1Bapen5H
sp3fCt/rNSeGZn8lXHID5iM8TsVKH+lN5y5B49sx9ELBV7bYRcVdasgycPF6t9suSp83CS01XMTz
cGpmve9IfdKN9XfpcFag84VQlw1W3o+PWEGUBxmoK3kOhI8iom8NL79tLQoZTZr0byXoN03wXMfQ
dZpeRb4S3DLdQ/6A5DqZu6SpmX4FsYAy0r5kjihGj07mcZO9NB7+yOY8CyAAmOgbNm+iQijkbqKp
xjvDha8SIsJ8SvVY5rp/WUcTz4YLJWWwoxYwPTUv5YYBpq7Pazt230pdFeEbK2wi1uRIzHiI1H6h
lhvXtRo/YrDCs6g5saOq3xgKzTMuGWV+WejB8SzppFMq+xDqT9C6g82CCxaNLwG87dpOesWsEF2P
Era3i4pcyi/A8CwuIzHgphbCke5wI1rnQVtEEiorgOdMrlqNaDVX6xaNL/N8GVz8V60nv9yoMKnG
bP4gjPFHzoQpEiB2duJ5yUZnTY5RUFdDy+Pp64aYqDq8DJuaQntjgseauK1V86KVsMjRmCGPUiB+
AEHumLPaHeuHuZviwgkxk2J6VBfSVZ0ro5JUUMNNPrqiu9HIi3xYbnQcFbb4ODbMQaPDo2ewBS7/
003Rv+SIebzkrjUaIrjN469FJtlkeIhD1pqWtf+1rdl9uAX3DmDdVAtizZMhAuIBnh861Rxra6qv
vx7Mo1JAB/2wvuTByQrvv7p3sLc0Qarn3ywflSLTTwf0uYOarRNgrUz22UHhZxlZpIq6ArXX8iyy
Xtc0tkjEfTIIFsms7UH2s57jFVpGlIMvDjD8YvfyKcw2cCOB2rQT91fhefCMS/3RjIVEbWYlU6Wb
USpU4Pp/DPEw0GAVtizGEnzc5DK8ahmlBDUJTABjFS6eX/2RkeSMZJdY7AqHCsZVYnZRTebI/zwy
fFCDzr6AHNuoAu+TZHV6Ut8yaK8PcGgKyAl/1L2moiYl7UfJF3kIWHaMw8qpIzduzgkM7o2m6g+W
hVOVfjoxPKxlo4FTebP7IVQNxtuJJk0R82nSeflPlAzrymbJh+n7ojjOKAZ6UkpehSA4CtsOziLj
+qEUfsBFzbcXCgJbgprJu+WU6URNnvZY7ZBOvaEMjQKHkUzJfkTxKxvlDlE/gcoCU6ysF2sUL47z
eyt7yTzZ/WQKEjk8DebPz+io+tSmchVeTeKzTNflYUVMPDgg+WRvGv43PLOu+1WGofrZ5eJlTpXJ
1pQVPudFu+Q3vekU7xFwMpHGwi+Qul9hR/sKTWUsNXbbXxrpl7Agwl3af4FRL2a87r/Sj099YJGI
GUX/65trfo889eQmqnueUcvxuoxRBJRKbn7b0cR0yTxwwkhB29EiBAxsc5TXB/suJsGXY051OF/U
HKEgzo6m8z951Rjod1mw37BVfgumwr0hs0LYib0/zTysvveUU2Rre13+2lzxAzGdX7UwvkDIVeSk
o3zoHqdLqjd5KMab7I7UX9RCREdwsTI7c16z0nFvhNrcyCOxrlWywL6OS4ChJvhwiCFBd96Eo/Re
43YkBQFVevwYdvkX+fq5h/jZbqHROZF/vihz/K0af807RUeiJyJbht/wVBsKLYczA+BCLiU0qmkA
SLXpbwNHCF32WdSwvaoFVa/Ca43nU43kPK1e+fnwWaMjeSybz/TYE08vH0oV4Ky+n3fsyUSatDsU
+pNxDIkLbAdDH9nXMkp/vL3K5smyawajivt+oEa/ibq8cElk2/RLaLp2Fa7eOoI4+AYMLmI7ZiUP
ofaR3IHLofPGO09/lPJZHq/9zkDqC45LAqdL263uuntU6tkocPF1uHabq6hOZ7XfZURgbuBKjGkD
+5c0OdTbKOGYr1fzNSKgkG8L5xfg6Nd6C3CBC6x1f9+OxD+Vn1EUhIhFVCZ6eBQE+vytmyLSw2Ki
w+r55pO5XaEahg4CabOwNkVw981YouQg7bQLDIYLULGa0I0ABk4SZq0J9DwwpXBU1o1zTtqzZJri
GmtL179D2sGgJPokZoLF8oQzjes/ZH1n6lDIaTsPSt3A8RnSgmeBMbUdEZpCWJAqqSjblJald2+O
4XH6+mgjsAy3ZPKG7UPWPiDZVI2FGtTKTaUyPvsSxiu20b7QD9m+8MeDvXFiC/QWFXdqYOX5PwjD
800PNPLdRUdQyOENPTIQOyiSSqYfbOEDXR48kiQGFpZCTyG6pUp25Rd9VNppw6MrpyCgHfUYFRYk
lDkJa3XCPufJUXvo4c7L1fbHQtVk75U9PqIVk0AHfs6TX9/K+XAKxwRBHZ1l+tMN8qgnuR3I7Pd4
8P3QW/nX0EaY0MiXhzNTJskX7wKPFRpuk6Gx9kbuhFw5H5wMyR5xSGWdllLJoGIJSXOT3xqu2Kdb
iI0h6Tc/ZFnx7LYa7J94bRwLabHLGKc4O7rKEiOrgUvasMDIClmZWMPAZIBvQlgBuPw1MByUZxZd
eXsHjjq7WqU6FTp4FbX+J+B2RiQXfOMZrM0DI/s/zTTfl3W+mZXUvrhMq+ZucwT6VpZVlv22ifXJ
9h8tw0VQ9Ema9NyIVLypSS68xxST+A745IlGoywp/MYhrZ9Ianv9jjlcIeqhqzRmXsnJBbB5oZ+y
U1sv/cAtrn69fjm/EKc9XR6gkUsx6kIrJYFqLkZ3ZtVjuN2U89Yd+S/6uMLdhzH/DU71/+6cNI3X
G5+940PTA0d+qkRUv96MzMQQv8AdK80d2/ZZB+keN4vYDltd0N4rbHZXP8194zLnbpmWV2ohxkED
giytgS9kvWbDej9NVS8HKxeQ7ruVqfkClEEKSK2vjKr8UwA4NhlcBMEZW8/39iJPxOQW7fCMWehc
t+54MoP/YeRhGQhtADxZO9+1o9aCegMnVrh63JL4n5Go2JIiE1aI9gx7Efv7MjtNjT7bs/svyLkp
xqRvXSRKY6vGm13sFR2Iw8euMTijr19H64exLxcxoYpNCAO1Ljbx81QN1+XMadeADYsn+0ACi+UA
70YU4vaEDzBmQ0xcfjimtzZi0o4JLbKv+pmYBDS8rfJmZe3vOlPJp6VkZ7oZfZ2lJMkYfpsgGFPQ
K09AeCEBbgm6kKkhD8BeXsDryB3teP4QdIhxBW238jYZqnQxQFn5RrvUxnjD8qSYPbvSPUdh96Pa
IL4fePDYVwNtd9O7ZRWep9acngcxLlpnL7ocea7Ne1nRCYa7bHTQgHqVSPBZYzDAV9nEziVe/Ztq
1vmhqgdTGi1UQuiUpzol2pIWnyJHa6imx6GaKXRUsueiCHpDddmiD+mFWN4G2s4KkUoQr1MSfA1y
5RYPpihkcN6fMzjvlCAhQDRXfFUgTdqSDIKChrIM4Lc3WIDYKLZLAvon5lF+M1hIyT7hw25fvH2X
8p0DsirwsvwiU/CowNboHPT78QbwoCyxgwz6h7aMkapTUhJJTlff1y4uia6RHa3G2CIBbeT9G071
TpLlG6hcEvVas1BmOu+OnZZLuVGMXkPt+hUpmIlKJyvU7WZWu4r38fYCzjdwEHWSb04MMOw+vjAS
vymo5+y997Athx7I/9VUem3eqioP44gWliXFkAjdpo764CT/FaX06GeonFPTwUVfehzlGPaANu7B
GomqmaLVh3gIuWfs9Oq8hdOO6kYMks/46On8YCWcmw3rCHipKy89l/fCiHzU3HvAQjjvYMKLc4Rq
ZrGd402yppJJ1dF+FLjaazprFkAfCVTwHjuzxVpS+xPVbXvDWV5m3IJ1LENrKCHzPP+92Qfuk5W2
fgizi8D/Miqqw3mEFwqdRx0H/2VgYXI04JXjN5zQB6J+K49YDiQoh7yJHTElswZ0ZcU6tbPACeUE
flFP8qp4EEShrRg6VnBX7AQQj6BTLdsbocCw6EDkDNgsZsxZPf51uYQDWQOcfI6VwgpOu+rk5njf
TTMwXUuXoYHt/bp3uP/9G2cUAD/bDUpz+mc+HMyKfvgpj/7Sl+lvlug0+mVXMHN4JdP3m+Z1X1BN
gQz9UZpHs1Ue7G6Nc9My8VxvapVKhjYXyZ27BrzUaS5jMz07Oqv0K+HUjhjWRFgvdKtnrdwYDcHc
WjTa+HzQ36CjaYwDT3uu8I/p87xQ8LcBCtqX56wwxMPdfD/Meu7Y/pLncU0F5rkJ9lbpA9xvDutV
XEZWRgMVQ2HLFrZA3/HI8A3dPUooQz5zV/LP3HCHkMijIjIBBPKUk73c1dt4VlDmDFqdAj3p9a1r
BM2b7X40Acv2zL31XZIc4SkF74Mb9KK1CUVI9Mk8INydMA+BGQV0uCzjcdErjqcb7astn7suDmXf
w/QX0u2dUmA5Tu1nflheY4qvbw/mg+GmY8gZBkqEzxpmum8xnc/mm/l6M6HcPiTQXCyz/wF5LHla
biTCJWcc4+/BTZGrm+cNBe5cL+s5ayx+Uv8zOv3l35Yes+7Qs4Hv9LP2vLn1hH67116QUsN4MQ1i
wvMtI43H4WIFebEeqawHZYUfgcZp0uQsY0GOJu3mFRSWYx4QGVNnZfdMgRWM0PyBf6oGucrwZ5Fa
Z0BKIbyXYIWBfiCCvIMIfJTVr0gI3cjcC3jI6i6ip9ZdVrO7B/6ILbQp9DHX8NqxYbrZe7bLbrXk
A2aM3yse7pMUOZieoaj3ZUQio1l+lKZIkOc0s76q96FWUhNpxKzXX5KVKGk25R+mVPRJwTTE7u/B
BUvV6GhZ6rzXiUhVF1AIu3oWt4DP4hFL6rmzYwittLEX1JjUxodQ3MMFrt36WK4EQImTeeEUbFpt
mGvBOxsQncn5zBJDhlUUz+t8iexlzp2qNOAea5GVI3WoM0fPRZuTrpNWIQrYY3HmuDhMI2RYDbN2
c9eppX+riiXOJI+rrhaXAEdA2/gvjAHdiVaQOCqgLC6EK9X/SiCTb4VVIbj9c4Tzf1t8j8Etr7gz
4S64x/dKLd1b1g+qpmUdpFZaD24aOTwkva/ZOlKW6AmsH+S/Ct6zqoR52yW2sagCshhvzYVqXHh4
idxYRjAN5MGqaCFIc9H8OmnIpOGddV3uEXh8v1eDq/ovtreNpp+363N1nAE1U18MEUUhnVPyEncZ
qFC4v1UoIorxfJsGFyVh/mA20x4DsXpgGFnWB1t/qoj1v+KeU0eo9v2qZZpUf7l7DjYYhvRsCkjq
4B7hbUabAys1LIF4hEagoIcrKs3HGk5Li2ZKjOwM1WvGrkbdf6yMi8P7gIEVD9E+imWtHi2T7qHO
JPKHUywWJ+T9C9T8KB+tZdBVQPyT9UvJBjmUSdMe1G9XJnW5k6o5+pGY7jBf3Ss/Yf+ZBB8Oq5p7
01IRZ3c7+1hTN0aJzaCc9Tl7FzvqTa48rz0K2CZgdlLjl7gUfxDGfhEZnhpygtJK4XkWtiYpMMrx
oZQcx59JchEI51GqEA6CAC6BXMCLQkuUn1ogOe5mk8LpNhwKboquzdyffyUNxj/sxJq2vOVrvMO+
KcSa6GLYfDFHB5mtaP99eKom0gJgElSV48SxxNcCuM9LNsunV1LKGZA9yLLOhRbHwVjPbz0D8d2k
v6amCLjLbejVFBh26QSN/zIgVgfkNiFImkPevbEsDL71bB+Zuh2YWkfbaaNyDpAYYwQXDq3kCkdG
esogsndQQXxgLjLlGg0csPX71c/zI3/QO3Vu0gIGsoaCIM53b2MlkmLJ5h3x0wzRjls2Ljnx9FHB
k+YK8niGY/M/9LI6jj8VNQArAb5oJt5evviR9PSi+mCraSr8/FoUWj1FDerscaPVCt/rcQPlbbNh
TRQJRQ58C2oEEDq+7CB54m4Sb5FHsY1rWOE+8oGpcdT12CuMa3r8ngg17LniU5iL2WkJPDSlbrnv
+wfvMWChuS62/Hn3ib+KUV93kTAmclEIHvgBr6VtCLxbUji7huHsmWzdpY2xY56xcaF6FfZe7Ac3
wzt7UFXmkdAS60PmnewDDRZsxrw6dwZIMx9HoONGc0MAxfJyaz7zKYKDM9828OaHgH7+9sJe/eTU
xcI/bwE4Ozu45u5eH5Sz/lNHu+JiVBGP1zKb41+1tMmPP3jvPjfyjL25+wDY6C/e/6pTfBplIOll
8vji2HNDhWvLMNVGAGe6t6f69Q3hwrLtVxFry5l86nVQUBQfflMh3hiaEAxP9pTUZbbMZ/6FIvf6
B8WDVvayiCvJBPQ5viLtG6NAoDlhchVOOAnwJNRnyvhmX6TTHZEfAo6WoxL+BiGizEChySoNxtKV
LIxWznIMbhFllZAHLc97JIn38KRqGj4GTKG27S2bHT/5n/0vznl9F/IZBmKt/5m8xbimxSoyRFAS
T2wVAxAhpMJhJvOTnAfwIqQBlR4gkOhFtUQ+7hz79dl6R9AAXkI5Q+qQ3m+/LBlqEeqSCFb2uG94
IykfYnXhWx1pHc/ve/HsyiTxlgYGkMOvVq541EgrHdf215JneA92rWttDoKoPy+UsntfKhmh0cjT
wYNe/K/iS8cz6Y6FHUj2rpDCyBg1vk/yBvEhsPSCAGzt5dnCwJL3bGwawWZnGrWSXnX/aKzIkaGv
rlce8dz5ElkYSaIjzXH6xGB2iogA1KssfvQi3GJUoG5NC8YNlY1h04wAvV+sZBWymUWvqvjYXDCl
PVo5BNFqobFgLD51xY3H1FKm0hCyhi1hP2rFHXitzareeD8+dPHxIry93vj20nMrZcCcbkClB5Su
jfmsUJQYQhOioi5FGmqc1RBhaoU4EOJWY1m5PSXjrzCERoCGLSfl0TWwSrsuy5wagbPMV+znUuUu
7Zs2yVrGBMY0HddM+/FU9oUjf8tgyas5LA89IcmV3y6b58Y+/WLFcu/h7FxGygw14ELHGRcGF9kI
syRtXg8Hcyq7kiIrY5Kb7GJjA9XyqJOWMxYpizJLYmOjUdzLTMdZMEHA3uIJgB7ZsuiMXbi2jBIF
nBZEAqLziDw18CAiZnu5iBHjoCZe2P823faX1QsMgs7N+goOeTKEyclcQTbyV8Epxr7UTFx3UerQ
kg0/BI6Xtp3ievFR6ifr4OIPXnAqlEYy9LB1vE2d9dJa8PbLDDqOoXr3HyoUfrlkWkEqS0TcmPAU
ZgSbn8MDM8DAc5qHYUs7/Q+9lofwJKLDdFuDxDcR7tYrnsaamiVDYpIES29/jA5ZDzY/9w+7aks0
VJ9dWecHmSpNV8FWYILMZ5WubThBl8Jx7q/c3kmmdj5Z0CDFPw5+ZJtqItjVxHyfC3FE43AragEQ
InrovjI3MI4gnUmTuIsD5eUhJKDf1h8JY8CFeMHQ8h8jyK38EoQ+j7nQ2UrEP0VdHBJ9WH25gyvK
JPoMhSVlkecYhSI1iewyreij+6A9+mk4LB4CCtLai1xrp/rMON58Qq4MSJAoM/Wf2cDR/7UwVMpT
ROZgkCjUsPl76or2YSWgcrMzss/OTljXQn6dQgDdevdEN3uytQi7c7vor9etyKFa+X7VQh4ZlWhu
q0s5OMgCOC+oiOQA2QaDA7YzIE978fLS0whl72pshs2+nD3VKDDLqukXwBSu1qNL4NSnsXTkPkT4
yrSfsYgS6+tmKnRC1OK1NkIav3s9xkEsNycDa/nzkFw5iMmaj+/YoI6wXBi5PCWbogMlS4czLr6k
vzYRX+3sBrK/If7SMG5vk41fFqWOsq1ZoH5Gt3R4xTckJkeS/pBXfkdwvKjKYFNM9bZaBAN2XQGW
pQfL2jh1xfJ4SldT8k7ofGfO9xl46YAgVsaL1jKVFIPyGJ2nxc6xmCuiTje8+vrGmwwD5Kd5B9Nj
w6XTSrWxHh4c/0DIqxcloDih0AvIc4c8x1XlWcJmXNZg5UMb/o/5bviFASFkxOsmSHVL1c/n42ge
FpKWTDrof+LHatH+dgi4vMXq8Kimdpf0yEA4mGigeD8Q3BLf8cEjDuPvBsShdmRlF71NnSWg4rJP
CGQZ+C+ibSvRIqwR4zDd6+y+1asfCqV9KH5UJpEBMPsikUM3kk9kQ3Hw+LlkYwIERYWejdncNesv
iaEYPPqHUTcHG49oo2x0S9ZRPt8RABZsL5mKpxWISWvJz7gDbhAlmvOWISI9WiXLgo4gUYmxRezQ
tCQ7FTUilZ1w68hZQfuEdqsmSKHFG4ze10hm4ktQf9NEbR8qUOLg7tRHXH4m/4dOFnHQTpZ5+6Zu
GRg77kEMDtODKM3eMbzrC6CLcnSyf25kUUNgHVTSof8i+rEi4+H5denssaAJFZ04UG2z5egtYAgv
Eo3Hjwdcj3Y/9FheMVMbtvZxgcV4LOXDRh6lNfR3axUrUI4dz/y2x0NpBxHx81vxh4daE32hZ9o9
ZLnOjOHuewzB+gFdrAbqktxgFtua5f77//Vp4j+1ggvZLPKddOJa9fgRJyuNbgbdwpCiQXpZ9onX
MrsHS/GxpnBUqiaVDir1NV7MWbJ2uLftTaJmtH4kOewaKQ4sygamnl9MUDIGvrUrKsBGbPjG/oKH
0uPnE+HFlb57TTj+N6LYXSC9W2IkD70WzB/EqLRPkM5K5YLlvknWrmUyk9SigfPjoX4M4pDKXNhO
GKB+PSMg+s12LG4/pjAaSTKQT/J67MOnhHqxZgzmwmRCXr4IkmONwXBNKEXpNxtVXRVpzDxay9yK
/3Diuf1nlPqNSg9Y/UvwmInwH50ai7wK06W4DTteMAlHG1zCXgvFAJJO6/g/Ls4cs/2ftN1BAL+S
Oc3gJzAfQ2CPi5EA15PzmH5EQNxKgC2S7Usj0tkvGLP0Ey57XJJ7bjiyEDdevb0s4E6cnV80tUav
szIde8Lv/OxMfhBnpJJ4DE8H0iwW5uZjEC9EQidelG2PDs90/Ic4u9plivZnoq5TQe88VVMCM7EX
1O6wbCa7UqJHW0BStkjZCvUesaNFuF+VaIklhMuKk8NL8YmQ20ha4wne24ficw9bu0cyxhIXvgX0
o9oFOUCbG3koI8rm4w7gO9Hn/o6zTCB5SU0L0vXyUCf5OCBRQYzjlRMGXj7yNyXgOECqN94VN4VB
9uxWtJdDDI1wJE0yuSIKdsl/HDu3nyXU5yEhpG56S/UTOuU24ZJ+Tk5HACK7tsWDEFD71jvb+ArJ
YHxFDXoUihMVGTP1A1JygDgLmgvi4xDq5yG+gDPnrahV8rdCpFOo1BV3gjwe6Zn+BBXAFHc2dgGI
YN+NYYKwBg5JUuBdbHbfc/DxJW/i1yBJ+CUIJDKvDg/jywB7SQpRrNQYVJ6MndK56ax/LNgLp4cN
ZH0ppxDbpGXsE3qdJpUiZ1dHCJsiOh7kSNl1SstedfrryVajRtJIN2yMXTgKMfl0ecB1y7dFB2OS
3OUkl5flJtp6k4IE8Um5gMD6WYMXP2zYNBegwWONpP8qhmHTenArbwUNGIA6Oh0ltmYbocFhvvmw
/z1SXxXzMmTykE6spqt4M7oK1yFKEr08qIQNYYVPpQ/JfojkKZ+fqQSMWN9bMWAG63iJrN6t00n1
G2UbSz24H1NYPxIQhUwPftCYWOJOYuSWkLvFxcHT5OBUEi1NtzFu+/UlZdC7eHSn/J184ptv6eh7
pC6AWKueR21SMavbcF5ExtrTBqVBGR4ue3NJWobcEd/OgM6G3GnzhyqiKWWbfuJAt6b9qC6dj8JD
W8/jgDmgkvKnRwRQsDf6mXRpSVOFcggFGJ9Uw4N4x+c72aYvgSwEAmE0ysCMuaOrQzgqFcvGstAs
VpGpIRN3gdSkTwMcuq+xWLDUuof6r5a30IX22JfF+TfregCguoPaydu0fhFD3Q5gHROSIVDlrH/A
qtW+mZxv2HxmRkjsNQRRuMigscU5sacptdLqIcMJqQOVXCmvWxJhGo5P2yLrmMIiiZj+AJd+d1Cc
3dSqSIBPe1h4FGHMOG5ymxrqWMuMBZMxPhr5A1/YeaDiSD+ZE5F15wRrjp1dVAduVLH38duO5SbR
ehYZgP0BDblGNEG7AsJ/hMYKVMuuJVmU/8tSp5yuTReUtjBOXvM4vNIIk1D9Tz2wxtGGgPsDrzsw
FJCMnJCBpqH4SJOYKGPMvXFJNkOrHINAJPJs6Ga+RFOYDVHu8HIMELQABpD35AxHqL8WV3DzMRQg
dVgTjDXkexXLuUxo9NkileWwlIoe+rDMjbijgM93Ii9+XPOpPTUsojFMVImuOsUi8b/YOYnmHN1W
/eWFyatkqnzLyfdrYcR/mVpdpMVXHWatVrm0cTm7gjiJnPiMLeDtT5dMOjRl6eN83kuiX8dCJkX6
0UMR/yzFoMN8IkptUEbEtN20KpiPY43h3pbd/ojOH26vInvAz5gvT4iHGdXV/KPGdpFLkxXD/pOT
iWIl33i7zCjoQ4mD1O9uw0lGHDmS2PVEjhhbLgOBFj8nQbh3PjKaP+b98rSBiHTbCTSA7qux1/lr
dN2ntOvYa9lfD8ZG5iCqJBcE9f1VX1DyzX9gEvgl1vZLytHbdQECmKVNd6OL9lbA9h7tcFhRsu0n
xe7IWF1jjhj6EeAP9e/h1tI4hOnJ6HhTthLLkcT10rIW0h3zSKXbTzstg6nVOuPX+fhoC+2hIeK1
t7MjavroLffhdSeADcMKXXR9RvL5K9GIjxH7I6nWn+T9gNi5SIGx+NIgYSbWcq39ywMswCgC1Tbh
1rwyDTGRRPIPcSEDAkJmIqHdCQ7AQ9DVLUj0+XNJe9Y8vqgE3h5X1du0iyFQIjqPs2i8NhBTBEwv
eZwle9aBA4Oz3GsJHEeFzJHTc+OcDcKqUfdy1e+Axc+ypAB/Z0JTKQoFyoIA6dJTC3oBbsRDG8e0
Cww54hQ+6/ALmnZIUbJePcmGTb/aP/Vz3TBWOIrdK6vUpQ2nU5gfbvmS/dZqXNzaLY5zoc9WRNr8
jaHtm6WxDO/k7wChBTWfuLSCaLvnsXcrM6jEu9wCHnk1668MeMBF2XY8dVC6/OB21SuCHatdT9Wg
sUd8LVgbm+U/Zebphi7rRz15ntxeCAxtLegQyRjFY2ALQGmN1WIX9C04BPTGzyCSX4BPxN5N0p8X
hunnnVkBBBZqoO11E69Z+kM+UXGzaXiQQ059b/R0/zThf718M9YibbZsdkmFxUEDQcheuxub2FV9
C32qKoOI+rVFaLC5HymZX2zrWU2cO9Z5QqUABlTYUE70jhvKCYEIBBFjE3fkGk6aNIRNZJ+yn8eF
2XmxpGKSOm0z+H9ZRiSVSVGS+LKIvHYI6dflxZ56VbcnxIJgAbGVXVdci7sDZXABYz+rbLqujs8D
CWn3JvAAMWCs+KSJHquMmbRAKJyXQzIh0d5XuYcli69UaDPvb5h2HkAXRJ/KfZriVovXRO/CZdHp
oa6qpL5NJzFFxzCTRF7T50nlcyM79r17Tz1vFcxmzJ9QdcF07spknoncEkpv++uv2k6eHR6OqXt3
si937LwMm9QQ/1VYCRMe6Mep7Gsohy2qpPW1RnfjVEQR1zYlqM8b0v5X4PEp6XtGpPcCI6lhwLNI
Xkrzm5ymudcjA8LXytuvGXrC/ACiRRRbMk8NHXbL5OEWsk3nOGrvS1y0H7sX2nf5Lib+PTED4JYZ
7UhPHaWpEYnzyUNhrkr7R+8ltzT8Jcen0vfgxjQsOA5KsJVikzT5AQ84ys3h5t17TJli8VQo402W
jvw/dBedyx/l8bBGohNBJb8EBYPOzRugmG6z/LVrrt8f0wfzdgjm02E90JvgEjBr/cqCWwSI/yZl
HEvHdatU2240/zIw4agTydkOHPsCUfe/TF82DCtbGBe7fhuf9f39s6tTO1WLcZODixSx44K9IFBX
Vx9WqJg3Ow2/mN086hyLoN2968yTWhPZN6gWz0r6Awr225U5+lds2cJgcRTE0EawdaiQti6NxVQj
+eRIk+sopRDN/KrrmR1NLBCzznh40chOil4zbeUB6Sn2Rmhrc45ry48+woJbGFwfBvlnxjVzFI7f
ah5lzyblowHwEMBDDh6ie5P+GToLED+r32WGhseef6sz9Ust01hnHWocoCk9bMpcmqmQxM3iT+2J
x+rSxHyZTFsbB80Dn7cJo8MdySlEPkBYQMPCUuLuPWvOz00qTD7GIeJ/N9xsVeIYey5ykuyTf7X3
B3pFebPzyPEQjPpvBq9IVBdKD2mqo2MqBE5sZRfdSsjelEj6JVfJY5dfeFEWrMi2dYZ8EolSCeMH
5h54lD+ulBfEQfmBDC35sOLMLzgg3rtEm596nyX9xQJgcSmUJWdgZ6xDl9PGHTLQtWOh4xsM87/K
OyA4uktqDmtUISGEDDtSw3vv6mPdg3YBJCpS2lnA3jVnFa4EI0cVkCGAb/p3nHIA7swYrAmEAotq
pKIx/feiYEgy08at1WNFxs+GsevWdUajtj6wf/Pqm800PrY663bJqISzh0/21fBfGp7Ymveg8a0P
N4cfvIg48LBjLRwBofmOwCxgxo3WJLlEd+DPjDIDqeVq98C82ttSu7478BhcJQCdLaef1naBQChF
KNVB9IGP8c+N7jIz5q9x57NzZCcq32Sdpmi01Vxp4E7YpXPylJxgpxU3ZNYCnxqIc2k8ipUKSXGL
Ei8QX6WhmUCHRqnz/ZemvTstomX6k43U3TkinfDwIRpoedeH8ONU8MqUkNzy11ewdFIMqNPJ4dtP
ffJrKhBI1/9i8k8+6qKmHAo4MeMlH1epiLsW5UYXJisqOw95TCr+kscVtU8aaCJ/ySsiDqbhX+l8
EaCwUGhwz1T/VSQtwzKDUAlQHje2ZwCQrSZqUNzKEtUhaim/OoE+bsdqfMO0wychvfTi1/iQTHzu
sOv0tN4IhqM3RPpxMHf+iVWe3AiwZHdwu9EZd2qMRGgy60w9BySud6ZYmpB5DOvkzItLUEIf3Qm+
kQcwYh3LIxTaoC8QipO9NSs8fGz62uvCq1Q76ilifhuX65AGwzsZBs908aairgACl+410S2bwsWo
YQTJ/Kp5cUdPm3v19Jgs1OLYM7d11F9aiXONG90Q8Dvrc3ffYfUEVdjL3zqhApgiYLNjwQDDvvqb
KoJhFbb82nBuqY3s3P2i8PbiSN8fbX65b/GPSP2phfDj6Y5+sJmIBtp15Oj8Vhusg3cYtcj/596h
cyvYe+0WtX5pauoP+TWaqTlBSrZiAHZh1A/Sc4VoXA5goY7ZuS79kK2M1FTQW8OBjTYWBL+sfCk+
N7gXA0w3RnozTiUNaT+f3SQcCdHBG8YO9bCE0xT84JvOXgE1J7Ny7QGUbXq/ba/fV/14DK9BINe+
5MJZa6GL2eTDsjeBsRcu32WCeLPFAPJIUQlMWj76JtW3tZ3huygGq08A/0f5DS2cdYB+XoRbdC0X
Hxq1q07hPHfyZmIkCUH7HXf0Pyxm+7VHixFDLPgodcVoZ7bdsWJBU+w0a8DZaB7rWCJAMlH8rj+L
yz2UI8mgydUz0EeA76Sc67pc5GcT/gBV3jmju2oKBLucLnDNK7muXKcCmfboB6xdiu0xxvNpPbHn
eb7uhclsg9vKO7cKTUnuJMXrYUGM75+tY65ebNWqus6HzBLc6xPZ6ILawujz3oKa6SmOjsMP2/oS
6MPFDDwrZ6nXufR02MdORugN8K9MruUEZx6OGXOD0I2/2Kb/cEyp5uj1T04dBrtZrXDaTehB1ztc
Nulx/e8YwUp+GI0O8l2+vFCXzmR2Hw/PWMKFsEq4yQtg30olf0vXumpyOGuUQWWbq6mccYaVvna4
cUgan7yhyqnHEg7tQ2sasAwfxS/hOpGN6HDBnl4Hi4x376iNMH0CmcUarcEOBVhuveyJURttrrLq
9v+E4MT23Dc42//3VZb/npSSbxTtVo9KngZ3EZmSrYKP0U/GZWOpaqO40Nq7SUYS8a2uKhc4kkcG
TWwa55EpMSRC1xHX1uTGqARgRpJFNWR9FYN1zaAxIc70z0YEaGNIJ79+eEziSDLvsErtiJzxK4/1
ZWTe0bvfEyx1mZy9XVbS5Cc5kHk/8/edjILY4Wa55EnDG7oF2X0Yrc8JbHA4DixlKAdbebbzpha8
McGqdkuy39LEunGHTiY0zZKhcppiu/Qi30st/S5G9W3wy0iOWuthVSSJtXPOYzluq22BH9E7Th9G
IAgqI6hzLouyti86+VGhE1kImV9kSP/VRHSuL1la3HTfSZn8/F93Ql4F8RzgYzD9OALlKoa/Ykqj
Zxz6h0SBg+xmmR5XMTuZohuVJcG3mK3f5RZM2/1YI9tN8LAqIrRwjO1/QJ/9AEeAzOh7vOzReWkP
E3xbYkNq0l6t5vNkAzE+cb+IFBWCIUKaBDxnRzmWgYh35zPuf98ABi5tYQSSnB1jWYTOAgV6nTkL
wctlLvYYQ3JSfutAXydtSDx+C7EY48Zz+nmZpTVbcBvwuubbL9jogDfOjnrtMYsNq6nckMnhC2P1
lScJl95vEilqM9Fh4cUi9XeCNi1YMw8aGJhr94/TItJtHtGzm2O/lqHxC2GKI1v1KCy9aalIjzrh
9I5TQIifJdxiNmnQW28AYYR1suZkPxU4+W1AJuUJpyMZUTsZWwL8IRAOh7JiKCDBxVREM8rreLU8
K9sAsdEjnPnroLNxxuWgGwDSJb9yh0E+2RJSql/kxG3+KN8obcFKp71+1WRpxDNBwz/xBSIDb9Hm
5u6RMvJuNzSwbV/ckj7x+KCzrt9r2pdopvD0fjObQHUXSCUUMTtgBKwzM8N1Os8qZ5HKNMeOtfny
/lcjr5OXMT4vNWz3R/M4m7GfwCJ8KSFlTvauY9SI1fXa9tNj2HJgu6HckIdW4ekDh7OMvoFCZt1W
41ys2agfc4XkkMXfqe4eWyTw1dmpp2wQUEuR5HKgkiCxJiZSa5xNaDZ6p+vuZzkJiIga3yNOK6To
kiUlyqz9KkxBnZkTIYyLlBIhY0p8ohGMQVyGYn0z6E/rq8fzej2lJeaOcMHXmU1p0FsLsPn/MtX2
zcwWwZJFyV9fJIng5ZydHnyKQWbuRl7A6IimjzGToou7qk7a/KGLrE66t4fl3bXzMZ1/cA0zpaCo
neqm8RK1SiFLfdKHwwRbb6sLypgUzGdI1ANqFqFUzVhhTFjEIpPnaS8GS45gTCWnrBjalUq78yyE
9lB8wv2QC6LLzxxIexTPRbTkrjnrKc/FJsFv8L3COEk8XfsZOyhQGLtjZP9d4yVe34g4uXzzb7PY
Otqyb5Sy26csFNJ6VlRIxTWIw95LPCEiJADzUBHwxai3RXzLgXIo5EkknI9v14p0aJw8XxM9+h4a
zsHL93eEHhGxyYaF3MoV8K7vacrsdFhUuh+91+1GdHbkl16ARf/kQ56IA7jNxxXmLKU3e6zFy++Y
+552sBUrWjGLdKpMtPx08KMXWtqjBt4xE+gtRchRDc3EtOEjg3LnEx9yhN6z0JcPIjfJ9TDFPvy9
FThsetirDsGpOTzYjMS5l4VBa4EX+aUixMA2Co/44HwAqc16IJC+kzQcBI1aud1uXdx/tYYT85JI
2C6BxtFXzOfIO87vhuOI5wx0wHIB4rlnnZ5ue2sobtiTg8qEXDx5Mec8Iatm0LjCEY+gDP6X4gFO
oPGcJC9kqtoCJmsqwpGHC03nhIietX3xLzqRCdihMroesNE0q/iK74kuFX8pXGNJzYP6mT/30wEP
fIjln/1cVrEggxRBRAxaYFl6+tiv7e0Uant2WJXyHOUUxJmIiG10WOdkQAsT4Cq0FPM8kgu+RT6U
SHNrUs/THYo/ASz7xDAode6HwLuRpz2F8vnrROkoDlBgyrDgTcnKZRGB9Cl0eiA9XgvZCdUttVv/
cgQsyc0OYxBNKQPIy5K7ed0YTtDsZpdfqrH2CKCv5jumwIrE4nNkKF/c/X/6anVAcfLOZvpL0UsE
HMcY+tD0rO+syxmbOwovf8hXGbZrf9NCbsaFTkocy9jn9q8NFuPxnE/QpMwDoHgYNNOzaoIlMc1C
+W5PpS+msKrZcjVZMKfrIhm81FvC/Qx9InYZPfweOaY7CWu1FLH767du4wG2vtarOgId0Ou6iryV
3L+GiaQLxORdqDCW0hlDjsG/3hIsJTab90Y+JzSpUe6qnz+QRfFnXOL6nxqmvhKzuUmuhNaR0K3K
4wj5fmN3TeATuspVVg3+7KfIcOR4eHXs5fw1mIROpv61UTcYz3SVI6rJAN7SIhk+yihZVCxC4TCn
XbYNTDUqcRHg1Ip6Xmd/rF+eQz+f+h52wfB0tyhemcTMywXchmsqUIjpr5mHqYlxibxNQ0Qi2He6
6u1O5Z4JmKHsTEv5ebEU81M+vkNFUfkHxDZcaNMzNf/8RvkHv8DPbEgpfkJ0qOxGVz5SSMeS4XfM
GfRK5lIoZdbj/5JWmt17iocWjB93uoRXL/KzM+DOUj4OBYkfFEFBVedgUnPDXBQ+WGlBJvO5OtFd
fKStmrvFLJgjwzY91X48yN3N0YFHSNaxaouv1T5C6wtmq2aICXX0qj80RU4/nwIT/dMu4VFMTh+s
U4gwH1tQ5ZJSBxjUgNCYTPuu7o2vhe8Out1WNA6v3obfnZ9h+ZBh2ZhO4dtR0VkqsH+Sl10c44cP
jHjoMSVuSLtjJOnYiUx++GSYw/+ty8KbXoe+yjzp5r7Nr0319eQ0bjrmpIAh7SzCmqAxKTQOb5jS
fO8ca44y0kBB/ha7IEwH+HWbuDUJDmbWfhOlJmoJKUOZA9cvz5Jf0Enr6qk/ECiDWKCr9gRJQ+S4
lz4HSeJSBUPnMyRTBEu1cm1G5OWQyW42jQOrXxE7d1fxAePlC+/wYaWDa5AAkUbU5Qa4mrybGn86
Ip6ZpyOarN0gAWYL88Zm2zYJmaQf2X3h39eUts/rB9Z7eG4jKOt8tBaawymaknklaQckQ0TRMmEU
8u6nOz8NcvknAetWwJmMVJH+WSPol0WF8tegqMHLCHsiLM8ry1TGEwQjU+RxsJWHY/LTZUmxoZnz
1PcegznxeiKTSpdxBe1yBleED2Jb5uzi4ggFSEuUUdPoJuuzH37Wu3GrA7m+AlovJNcvgHUoF7Tx
25vt/TDPJ3QCQ3z86h2fk6CaAi7OjSX5UqXhbNzMHafjOZjhdBwBrWsP2DVDcINjJ/OBBzuYXCTz
UwqfbSlId4zz6wkGoaRbqGXSCMEzUbPkpFkmkbt9DtJ9TwUYEbzrTUfXgBSJVjUWye6CyJo8MQW6
XkRGbt1jqm+Rh2yodBQH1/JEx95bUtU08EABEdzyN+NHWIHqEtPi9vPyGWJtsTg8/7g+vyFFbXtc
zmdncc+FJumtLmunn+QNXS2iFuNe3LBvoifm21jblfiLZArs51ggE9Z2mP+fHM0Jh3IzuNsbT7+Q
UoYM5HO2uIvIrgw0YOZ6KOUSSbCLxVxL6h3YrJnLMxGmqjSdhSt0UV4gHonxS2SP28E9pd0hx454
cckUM/MOd0A9MLsHq4lnpQclbGE9gpiCUuJR6daV81P2XNrTz1WF+s2omGAzXDBZTijQlxWzOUlU
A6OIx/moPGz0UIYJ1JwydK7PrKxCgLqix1ADssuWSBA0sFG3DAXQi1NVlVxwo2G6vyhTNlult4qo
gurBu0qBRWfnLwFTYiilHdWRt8OVX4ldeRatbTyeTrWZY1SI9LE9ajcicOi8fvWXCgd2u2fCpyrP
YgyQjBaAOk2br1LlSnMFo6v7CBBjKDfROhSpOlgMqHWSD7yomg/aotDYcLTNfja01VH/cJ83pgmF
SMF9cN7MOee502v7iTTh1djq+MDxjJu7hYW3DWZMu/EFGHHDkdIdgVMmzcsyXO4uVzGYmpgqC+ti
EwFLgjK38AImEu0UYrORFOxQTMRfMZQSbgwPlmsWGfD7raaXM8xpcRSCuaE1ZAhdrX6GO/Ktw84E
osDNVh1J5UnezLaBAXxrYn2K6Y9kSkosls/hy6wqKgPb9k86rRYjnZNNxL0VfnRK5CV6s2MW+BhG
/ETkCMrAEfyOwlRXgElTyzjvI1ZVE3eEPFC+xdKfa4TOz33Bogeljv65DzjcHAQMchqSWXAU0ao9
CXjsS3pbA6wiXWlj4Px6BXEdbyGG5QNz9ba7EMGDQJhPLeVGQWhG6D1cZr7Cbc5d5ORxX9jc8FAk
4Vvu/BuMk+Qjt4ofNZ5WdryjTyM9SKg5F698dH3V9nLTWFqtkrFBNCfODMODkQ23JleBBAiJCm5h
paIBxVuGlx+DMwAL6Ay/dmTgS2Wc21V5CLJBqC5xVLI6d8JxJMK+G5fsmO6OkyXXYq5E+qLMDOgC
1N/AVhTXtF4txVvfrhlOmRppzgIM2Do0VRAUfAIv6NYnyaaZJOElM5jnBQpL2mwFCspX/7PjVUOe
iqeoBM7WalrS87hu95PgLpaBK+5MTl7hOCH0OdmybMuGVwl6pkQrS2j82b/0WfqmVbRoHkLUQNtT
PKilzsBHr/Uqi1olzDsl5e/JxtwgZpb6Ar9LHQDQsfrxAd8WceiReH5jalnsziLWXHTmggTmfkRm
wdXEJPIqd8n1LIjRIDkIGffB/9Q4O4jqsNLwwcWH/jIjC2Ozt7HYUvnVEDKHcUTEmzqdnTxlwbYF
qcS0WuEhVGQUZ7pRaapvZ+uYQeVjKO6IEWL2H608/Cn+05pEVgIlHQxFOqkfdHtPceNMpygvx/Sb
uFVvFgpkMYFi/2WfnqJPIidZ/qPq+lxTo03oGeV874EEYjYGTLYCSqdLH8x7FfGynEKZaRBkgk9I
k0sf6dxtzHambo0nZnOwnazkCkrpAAYAlp4hiZWEVUsBn8rVqkCAX2oNN/jKWX91ym4nhepLLIO0
AWIgjCgmNRtK8RSuFqs5FD3rpfb1BPL2hnxl4dPiAIzwYVOY4DhVnTO4X47V+1u6EvX/ZmpNooqc
iN2rMuSQpDxzk6cvcT/1zpLmcKS6wZx1BDCmA5FWRC1dKXrmAQBsbqhp4ezVdTti0NxjXqWQ6UUN
XQxWTYkqmcIl8YYjUL6ltxCWl0JQ4yfPa8L4bNEIvoXjZMIR5bDa5hgV3bfFWLOxGOHQe7g3A+U4
wOqrtP7Gum+i2fXkXFxQmWMVAV0yy3Oz9N7+R9rgtDNLrOiZUlQIbq0SyyJsiPS6RwD9fN7niOHs
cA0zmK8OfVdWjx27/99LY6GAxMhyFynA1WPWYVjeVwgm4gFlnidt1EOJB+v6QU8J7zpO5aKtzp/l
QMe+MjXLVCJ5VL3sOshbUZRRFF0/DEVXZzYHAlxxamx+tAB/b9HXMW26EQxaaZKBPpKhiMLaGPno
dELNT/N98Iz2G3DH6746KQSLPA7GUz3h3NRaMoXFjhqErVZYa1Bjf+kJvK6LIYkWEnmrmDM8Nm1F
Oiz/sOiowL9kmwzYRx+Fr0hOLBx65CimLWvhJQHXHkNimeCRNqAfgnEQ2bvU1zTvx8hPS5Poj2HL
w0NweVIKxnN1jF5+IgtutBTZH5oLmzPS3yyVDK8/kyu5fPwOuhsWVjxtOnbImKjeSUhx8Op0p7kp
sdFthI54zIXvy+5X5GMRNT7Qw79ty+r19p70wD3iWSIftY2nyBzXKQIfTWirTipHLolG60plH5fR
9eoOvOLlki5yOQPp+izCk9eee96jM9DguFNdCQPhiavy3T3zjnjmYI0hVhzSqg0xE1XKsmLVye1g
6tzR5Wnz+iahruHsv/C9wTLiYFBjDksxOnkSNvykYBHCC0KiXAx+t1MJ/Ev5NWPIxpjpV/s/hQIo
zzaYip2eYye/KIsTmVdGnQCL8fHzyOulLbWhi/3Oxf+6t7ptNZXwTakS+eWhw8svEQ8f96vQ4y5t
evn3nVi8wVGcUqUNj6PCZ3vMHLiH83ZLOsQBH1sYdqb02GF8fnSG9VljJMgNp1ZYevGMao7yDo9Q
ccG1+PlVrloCVTwnQVPpgEpq7BoR2PZJQDzb2O6eIWaMWWA9Xx6fKcR4DsOqxkwKs+ReUwI6O/fs
ijPyHtnh+Bp3t4UE+m/QBI7nU6F7/SrsrH+uBAt4P9z1+xHkngssVloCDOHj16AqZ3IHecVrETGG
cP3U7FhkBynxrMtj1vc9S/iolVSX5z/fOg2dp4ZZpET1gzqTHOM7N5XCAmLdGpjl0F11W2AdfTjt
Cral/lwuZ7SNsPFMlCc5FkRkvFM0Tkihfeu2BnHp0iYlpUAZSFUKty3TBpWd3o6PxLCOgs/uwShj
ZNFqdFQ7HDl9wV3o8P8aUT+FNos0+BMEjjW1okFdaRDHoaaLNQJ/ofS5hPMkEVP3ILv1tB5lF0MD
mfTA/cwfnMxE8TD8z2f4HWVzySYiNButrnzUbIkxgVJnTLpqCLDsJLnMkM0zwk1Cw38ZOHMo45Q/
YlbvZ8M4nXsB54mOzQkIg7qCsQeqmjn1f2ANFIisM65oz9vpjRnAXWksX4dyFw+Oq55NxPwX9BZR
QiGHtATOalQfdgUKBQZ9lB8qHHnLrNXsdLdEcyUGF/ocDFGojWq3NEZIyaQcsr+utuJiv2f5hta8
EeIpZPopmeFv/34DMEiwA17Sll3lXc2tDOVdk54wlvUlqyr6TbRqhtLFlZ8BBkP5FxaDzjEIvTm2
5kMxs7Mt2ceOU1Ah47lGmDheBg6lvu8GJte+0vXYYo5eOz0dSr7/6XvN70gRYFTNaDwJf8UrMoz4
Q6sxX6bECoS3GHJ6CkqMC9c46tITTVu5YCaOJhHNS2zYWGbAesRJpUF7Hq9PiwtrNVuF6+wjV9ji
udXhCOZP7kWPoYX/hwlayivec2NIudjYc1hgo/wYWF2xvxjBMF+iOs+AgKAeYpnkMLCgUmKMHF8/
rBYebAdQxtq0rTzves5N0f2HYiS3JzZoXYAPoU3JYHk4opFtBAV/dxA0OVYxgNNvyZqmTXr581b/
Qj7KTDElST+F5fgsVIeKTKnKSb5xjUJ+T/xKYgiJAFbKlF64+uu9I8nXaX4ePd+ObOrTDaLKkKJ3
keWVTyfi65cHihSR6IwePrgrBe1dmNuiLAnpTGOcrdQdUodhEjF6VePvp9mrY2keTjnFsoOIg/17
qNmI6x6o22E4VyBfFzlWm9m2fThsgfAsf3iexY3S0Y5cONVydBSWQp05zKV+3KV5vy0dPVs+ojCn
HTu7dOk19qn4HMK/x5GEMgMTENfxuCo+rNe35JX2M+DIS5SF7E6J2mrO69pmijw9Y0BqTw4FVX46
KpjuIu2mgspxtOKLw57wp61KoXWqT2+PtIuscBxap4TjOIk1tDuJsfMdyVuznfiy2QDrPTCbiMyd
mYUlkcW1DGeyNpHrnbF87i1EFPVEUU0p658ABcjcmXb4pNNylzUh0ZkOcFAtDNnBjioh+DLUu7IU
OKGoQpZvdZ6WYtsxW6/HmbCzBbKzSVPD5RfxttzhIqr683Lo1/UZ3TzEpc5mAsPgb5KYxPlKKsE9
DfMNDb/QJZohj0ICJYVjPAXw1xe/IGEuiuX8uf8Cg1xgONw7kh1MHC9gYu7WrHnUi7OlmG80yA/a
y3w9fSx7wPHHQTlLvh9zuFTXVuzIEWnfKD/CgjxdH85Gtnw838rDSTGRNJNL9piQueX210FQfSXP
4B7ZgkzzTV7fXDF96ya3NnMn99PPY4+mw3ie9M97MTh1QfbQrncb/UioG3YnEmgfPI9imF1Phq7E
u3vyGEOlU+t3rmQU2g3AVoIebKwA7zNwo3w3yLLG3osNGDtJDe7yrlQXU0uC+36QQvbvEu6qX+b2
toogGDKsYfO7SScLt2LQ+8oKfrujWHhiIv24EFeZm7aCj8ffhCZxMm2awOeYO9N8GVDAXPuMu6Nj
ZOokAHxyHgYMnEj98pOTSQQemgW638pCt094D9aQXxdozCv6HRfu6C8pkca92Ho1hVZRhc7rhpmg
/m/VvP+RoPP8wfjJgs+kK+o9Gs08OnBvl/pQDkwZx1BsY+aohDHSNUMl82IDNaXugmsvbz4LsPU3
tmgZ77Kl9m4ilIV/+JdiaiWGKzXHaCww3SP90dZHsYag5m2GsH45+WwBAlChrT6cgdAg0MMMJwOJ
vC5zOrGTXyoHHUSUvxap5iTMsjurRK+gG7fTKdn8+aWhoPIW+vdG/E5gEC/LREFiqVfspSTUKIaU
4DX6zXU8zlFp2IPXTaSOArQ3rwKR7yrrDEUAQP9ysyYkF4E7GB8Ou7tAdJfv1u93LsW7EI4IMDm2
5rfWVveaN2TD5hhqdLuj11E3oLCAA6QISGys3j7YenuydcP74zHHpniJqd/3O3DKbNuPXcYowK6F
qp7VV6ruQSJpBcnRn/6eGiNG/GQaWEdzoC6+4oge3+pvz6vau3lNYBpXcKJBj1gIRHf6iz2xin+i
eswW7CqLELv1/Png7C94gcF6s9Lqg5yZm0Or34+hzwgJaxwslemPikgUlTjl3HC514fno8WyTtbZ
WfDMNtzCdg4+wcNfe2eLMI9h0NyQUsottYm8WSAtZjUx5iCUvuLxD/12dR6QCmZeQ9XWU5TGRp9M
2APMcI8OQqAIXBUEqfGslddfH6pAHlA0hV9DYblD5RJXpjtyfieoQVXk+m5HjvywHXBK9xXSNjXr
JuVJ5h0CmMwbXLyoM8Ge3ZPGIGJRX4PJCXksvNz1E30YQYLiOwQ0kBi31ffE2VW1FP2iDVxTIysn
/DZhhEdR84QX5owj736iE3GP6yxR4p04sAKDDn0T5aeGkWp6COkbFWijgu4I9VBFKztal8NRifjC
KP2VTTSxijS6+/bltExS7QRMDcp5d7oTJ45sQ0Up691BB2XY7UK1zuwn9VhFLKFmmb03PoN+4EK0
sSQ8WW/yyPsYsa51xmJbjbHKKwr4dVGT2+oINfTy3NC0gEayQlJi+vgCaID4fJrQ2QPm8GIbZK6g
NowVApn/ZEPETFsfYmU94Y2SmwxjTW2YclH33weTyVyC9UGToEi9/B/pHQOFOKd7GIt7x9LSXq7K
3kqVeYrgnHcwunS6u1Z6ZFEIN8RXX4HQ+UfFFDNBHKI9H+UygkFsDbgstCcdfJG/VkUy3MMsVC52
0LtmreWohgN28FCKPEUWYyxshmrN/BwT05NGL6+QG3Ryi6vLWt38VsXmKkfyz48AD+JCH7kbfZc5
FvWiCjUPOSo+bWDLyOEtmafkrXv0K1Bo9yBOYRqAQ8Byo2ZqRHc1oiPvyKnxtnv8nXJd22tueDfR
odgQivuRWEbrGii1kWHb8tmp1g9rUsMRGuRNJ48tGARRnC3DrQUG/jPV7426km7w2NssLmwz9RBL
FYp3CV2Phq+VpSFsly9AO+G9daOHpyVsl4dh2LKkdg60aNkprPuWRBzqrO+aD/AdNGTCyrTqS1Yk
DoS2665hNAUhKanraFvoD7ZvQ9ErWOfIV1QLZiRbED9RfPDzxdpHSl2qQwepCbhFkQTHz3JIUtV6
1vMvpFUM8DVy/hjukrm0/06fIHY/wpQ1fgBQLOYRXiQMU03X28bD54xfIWu3zTTd19SXNUyqTpdU
ML8NZgub/QUoqkM0ot1j/NsRUvoWx93cpzZI4Hw+fsladP4So517f5utHahNT9yLbN7S29WPsKpi
LIfEr3WmrKB6Bat4913C/OKtAvcX0MIRCuGXvpywCRP45Qzqs9df1y9EEQzpz6tIRJz53eVSzfo3
kA9aXF2yeV92A1DBSCz+welPk+UOLm2Vnohabs0qN/2KJeUfjLIXPSlMx7/JXHFf9IrSzpBWs3o5
GUMncm8m4qlRRORdHrpDXCn1Imfp+oedjeYoSrR8ryHOb1HF2IctzvLMMvHqDX1fieY/BEKgGtT/
SCc9zKMGCbJwgrpAluFhIQoohwsBKvW4LxFUodWx6sCjYkp8rXqi+HouIOObtZoyJrdwxPVYq/Gu
Psk1ThAI1ditjkk5QpKkSZlT4rYM+wULVeUBrvzQE3WeNbjdvXbgSLsdpDbdSpdHXvk+BMqztCCz
SkC9XYIBXlYA7vuYMNePY7FVlrf2WOpR2AnJ6rm9h9qKTkluUZrgqdClw8pxeMZJUR1EUN0BV5m+
7/IDMH+YiPgfB8VtTm3rm4mlHotMQpj0u/gkg71V1/3LMJpsfvOKxcHche33K+PDd6acEgjZ+07M
Y7xJTaLWL+W7h4FXifNeg4VveePmUqHsODbS8C4HC0hmr8nPz+t6g99j10JKL3EhQ43KUMbzv6LX
djqGvPdPygmRHAAoKJ7cyBDDIO7UTbwdg7Qk6EIqNlwBtoIgCw90FtgtTcAnzfeHSo0Y5lXXATDA
/+czEiVz4DTXJkodQaQ/szjZwDvFga6hk3403q5cGfFvVCVGdTIx9Tw2x7epXfAn44iHluWK2Ynt
zj+W56IyIWXKoBsFAl+FDtwl4IIVnuxjWC0Mz4lK5ZiV4wYhLLfAU2AcP+z2MT60JHjAblld4FI0
aQkrFJguo83KkFADHtuFYwLJNxfX6dCSfCsieWXW5TxbRLmz2GXcpdhKAcGxjP8O/wnnAin5K3j3
VgvOHYX3QUwklQoJGlGbcePLlbJkAbubVB0IzH3jV7NXA/J4GsdIwuwBJYAr9rkywUnJlLPJu3vq
+1Drybt5bzO2s67Dq1pi2XsD8JwNPxSureLnreo7EpOkzTdzbgTtp0YiQp7b64vLvg/gFPRKxPnq
3nsDrJiN9G89KswIS9a7KFOFWe6X6ZhfvLariKSvPdupYPHXwgT/FNwj4vVvEtq0WUjJe6/fVazp
up0AukcPFM1fDs8aGJSbzdttdhnZSJKE9LnUvwLmq9aIYjojm5/3sKs1+F8ExueacxjjGB+42bZw
NEOzgD1HYzJ8nrLRPbOsJo2mfOHQL6nDw3j1emjVM3oVuz4L6HlkQXrUZzhK83/1fm6BsViykGMT
dcRcc4EVffkzGpd5/HczZ4A1DIuwhnv2OXJ/SNWab9z0RCMuDxWeU/fhuiG2zKi9su2ov2HBbI4T
YoMuE79QbHoLlh/gjvW12C9MZgLbtNr/3vQoKvNFuYNmpUr8k5bRS2HPjmG9LMNlgfqYWw/qMnwv
Wf0sFI6pCm80t9D6GJeddTDvC6+fbOWvH9a+ai6Yy4OG/Ymp9ng27XCK2byk8f4LQ51VXQD//xYv
Rt2mhxw1unuoKpkkjj8LM8rPj6tl5TY28589JddhoiujhhSBgrKVMQYn5RC3Kl/rTDYhXtG5Fyqx
3wLcZu2r9JtLpTSJ1wiC9OgcGLlt7/7dhDueiUNk7fwlgYRHrCAP8y4G6011VehoDhwsxVYBmhEC
+S5x3wGU2jcojCg3iYhHud9SOuCMjdFOanrjwNhFta51wAj81mt+8OnlBtBVwYuS9FL7mbU0Ztka
OCPhKyPwTv/wwwSRu+pYSqFzK1T/MIgBuaRZBiWokA5E7AZ4bIx6ijFeawceKweRM/dXYGEGvJid
IQPsMZ3Jmr1/2e6NHCeDV+T6aSTHa9VMZ6x4tq/H+Yx3FTgeNQ/oShmKGwQzXRGNwxJRKmVgVbpt
wxXpoMiT1TBTIG7EFKW3agTVImbOMHBfFCVMfpjNgUm37TApbz4YzpAnAQQxHx6rXdOgBugApfgP
RaJRIyVelQ/0UXHTfcn0GACZGvrX0sfUT1VB7vUHSiUnZy4+vRfis8nwAOsiVIZYyL8c3Fk2VPc3
Yqe4Cm2zd6yvuXiCFQLk4SAawOgFLMeJKnUPTOtAYN0CqrckY4d7Eu7gnx92kOxi3emF9a6JOUNJ
H8Jm5892P9xh9M0DwNoKZSO2ysPAXMm5MW8A1WXx55OBEYYFFhabXDbVT4xvLxDh/NeLFVxmyGPr
fcwUtQOqYkv7DmuKD/o5+2CV2qCHwrdPmQ3I8G2+60AZ6klQEmt6r9QpzQEhIETr3my55jNfAj+5
kt2KtYfdUJGfwx6KMDjMDr7oM0yHw6kDgqeDQLMgXdwEL0btDVv5VDuO4pMZw48BXYGP4vh+ti+G
tg8k//JE9wJiVh2rMkgY5mBka8hk5dNj4dCMtmKqEOcWtVifeKQ9izyQ2jsQoJzfqMQlnRxzGc1H
3Vv0NmQnqj+j6lFOyERK+aUSvh6cQc0WBZwgyCF+kLILzsA0rBz9RhgYTujauJ6cL0REjf0RU8oQ
vlQqywqiJYeIK/aPQZ7vXzG2iWBCc15BniVqGJfimIMePq5KgZiORMyTRqzTr4O+2dk6rLCfYJkF
CQMBvTJZMOJ3nmOmAd0PRxA8NCtg/LJNyfkcQXK73eiNFmisnL/1L1Zx0z850EXaRbbXKbrO5I1z
gGJmCmfdBE8U386b1zxCSp7O6LosKG4BQt/FDaRZXPe9nV+aYrYlMub0SJiHjpt/jklj2G1eWFsv
MDCOyYvhzTQhmHdv05g0KR1JvylkoVTeiQ95E5S3MUIgzr44cYzJ/JiYcQLyVmJgTxvj9RT5Uzgi
Lxzfo0OvbKbjgPvAHF55nxdxWyiKFPjoOMB6pqKKMoH3p5zulkV3Tf2aH0wteS9XBZQYt0lsNE36
SIgK5ylH4q08zJRgRSxbreRAlVhagJR2UFmqIH0GSAacasEV2TzvlhNfhNmMy2hi5GoPPKc3KooG
H8C5WLFNiXQutN100W0B81SCl66nxQ969suyb3WFdtXWSCdnobgxKxrlCqJ1lR2+s1Rvm4iab0z3
/S05SebeaIagvLjoCNttZ2DW2A4EATH7i/IqSnb+g49UzHM0D3FL0LpTbxZzWrmR8TJrQHhrxkXS
YzOIeIY6ye3jpNBSQxuh00F17JzaC7P6Lkf5yR30KRyGWE2dY9KDM/ITlWaH7XA9V1uHrKGOzEmN
Fgbd7wNnBXJwUVv6q+lgR/iX9eMBOrgAcb3LUqB1Myf7Vs9yWVbxWZo3zV++A3UpAGliICRTQaU3
hzygoawON0T3+knrhAVSdfHFYFUQm22ejE6F0ub9u3kwcHjtrnqayhSCJjursnfTfCc5YdtyJKKh
4Sx3vqPhR0/xxYOj83C0fV2aNBUFJUU9/FqpPqZPbus3qc+c14hzI+Xnt4ikCtuSm4FgoyezWa4i
nfK76QPuG1OinNdmiYI3fX5JuB4b6KU5Xqkd7FgupcGHUe981/Uuiv1Z6vDLA/BiX7+91Iv1ILsu
vyLMOvnbJL8U2MXueKilkT4OTPtf7dGd44QGyK50QIh4qZnaqKofcMDv6p8AvyyD/oPs9hPpupUL
Dzvgtyb/vW0CO4RrSwpjqo3N8XAPVxhQpdqCBnOLrJW+L7/Si8vbBWiPMSdOUV1rX5mkgKdRmW0X
bTFWfYhDBPQ58Zty/FGOQYhmLZJWIy2SHVKCAhHcHrL/8ZC+9k8CvfJ8VAao1lVp/BVxwBEfxWrX
3r2AHlPjTl0atSTMM6GvUcIkOaiKl2dCDZLe4x88khRDIfiG6yjiboH9+ZFB7ceLBdx+s2c9ZaxH
pCxcvu5xzcLh6SH87WVNRLeA5YBvRIt56VKaxneYUeZK/Ku+/nDqsrb7uxYXatt/YwnJZgOzit7c
cwtRK7g/FXNXvS2uQTKUsltq6GDIDi20jSCRQKOCCbYtMzGeWMRKSUN6uvyrXMQ4ZRFHSANPBms3
qz9Ay/eCFeYCfmcolhzkFisYH5d9t8uoObpmsbmCo8WDqdGKVkSz5dlvUpZLdP9srhwNCzgWyxAK
I1czYcznNST/hh9MgAkM+an7PzBScvPsV3DWpgP7Zrd3PA+WSHh00Z2uTG/ApooJsCRoRghxJnOF
IV6F07hdH6DuFMsCOChiYjFmzl39RXCTfDOoQ7w5sQ6ltmBYZVtDZ7Cn1PAAf8Y8mDOGPC2LgC5F
7M27ecM7kujRShICYgscPpfdf875CFDWAhvNyX+JvNqkNmB3JQegeV4RtBH3mccrnE+xz0Ca7hXA
SbavSsNkYwKXHjVGFJgdnriodXYmCohBe5WUuEwYeBPbvIP0sLzxfikFRAATdUQ9pv6ZZNHSk8ww
icpPXlLDrUKMGkevjYP6+NsLk78KnfIXGtzrYYCbyEj5WZhP68jwCSggQI+MGHOyxz+YSy/+DUjf
oy7l/TNhpYUsIbWdpNBUj3c5mDGA82gIE6EHG6fIw0QjQCMpr6GbJkw+rHpWmVhpXx5W9qIahPxw
kw8MdBhZ721aBF0cTagId06NIkOeh5T+HQY10wIV6yd0SvJSLnvhO5sANY3fJApmf9uP20C9PnF6
x5NrPSi2/Ou8oQ3L6s4k2nngS8pslz7L3LIw0bvPVD5+83K0Icn3aQLvAcqcCT+0RWBnF3Gz706U
KZC+fzKsbqCENfaxzr9LpM64X6apHmzDkzXjo187Hp6EEgVLidwp8BIARLB59E1Z4n4Xly5OnjL9
IHO+AmReV7hJAl8JwFyokq1quQS81N1J4BqXPigE18RjXUdvVwyLr7AUinvntrT89Nkdp3eH0yLn
dgyJ0ncabZediH5QbxSEkNkae90k2pbEK85vYX48/jX7WWDp5+/dznbXNSwFNqDZU/dIQfzaiNYc
v65r+EQmJ5guiHWDKcXu+b9swGHey+D/CJ9Y/IAbQwooJwPmlBhPN5kSu8gz6hDAPlwE/ZDASuE9
0Fv+MVehhcUZwP8/svofseLFMYS3ZlSDZ/JeCmV/hXNLxEUygrT5DsWc+DDlMZtNlsOX3AoRPUpG
IzkYOFq9xcPu0pxXoEshceWpaalaGro3AzIeMkutYCGqMD5K5TZ43GI8a47fa2znHlpYx9e5VrmW
4jvdf/hTIrKPbEYkp5nyWdV8+owtDMD7XLs5dtfM616zDf0xjxOivTo5HAyqu8QL8ggbPy/HeWvn
4MrLmtvGD3SFc4Lt/K/NT5MP/ePB+i1qa3oJptou+rAL3udWnKBoUMMo9Oti5x/TuvzzbhbSYGxQ
4MZKsboed0WgiEAouHgAPadPqA6QEq840fABLI4ZcA5fA82iDwevUZmoC6XX9WLm1zt7jN70GTtS
z2XXtqmJ1xapM6sb3/h8cRiDRM6Hy1mAvzZFA0IFLjYLnz+EZuw6fNX2o+ohYGHGQCGbuhVZsLab
mxcDw4v+EbqmJXysgBHqI++fwrMqN767aLgx/QJuZHk9mGDFLzBoPWm6wam/D+e4thyXMWSikknz
x7sNvkU4+7Fh8auVuLd8q5II2jaCcbSxM0nZw9lJp59qZv67LJyUT6jvGHw+brDXNz/BX9RCmA/q
dyU5/wUbEfz2TKA7BuM+nayyxcLiCWvYe9D+fdCo9e1KqRR36MyuxBWHzIlk9jhPMPnd0iYkQfgG
bD0KI52FU0P9HSjUYZUNl2rxY87O6dnIxlCqVyX8iX2Z7D0G+TpFx/rWZU0xYjf40ZjS79a1H1fj
/7D6dRb5qO47hZaB6Cn1pP837BaoKDY2x5F9D1QQFSysphoSCZVCBZBS6JtSo+QdYKXEizzVL2uC
wR1SFEF/OMnqhJBylWaIp57024OXmNDhMGOIzgpD20ojBxnFUJHIHUQaR/xImO7m4MH+gX8lV07w
T56Woho55aNblo2PUO+YgcZHXa3qIf+CfD+h0DXG22nPtTVMZjpzkimpvWaYl7T06YsfYdxTqPl9
8aqrtgqjZfoILwQL4xNjR1QjZYr+KM0YuxGGljSraFfjPV9ATRUvA3JGGYy3g6DOewFbGkEA8fic
8In8MKG8HF6vXGttPP1tr/0iJgsLNfUXDygLqPG4LI43hBfYSRg1HcvTh6Ja6WHBYYxhhlMo2bjx
3BEdJbQpDbBH90pkg8LbuHJGQGXhyHiEVNuUOQgZKPBxATfPWNJm0kXMHtaNKwojC40+okB5DmSd
YvFb+pxNMZXsSXnvoHYQcjFVoiXhSj2Bf2tZDWiqpP3PvDqgh5z20ptbwV9kg5sqoO63wja1LauZ
OHBUvRcVtCgxrG2I1t6zyaWyKprzPwed9nhM7iL8xGmLwzmWm7aRJ8h0BUpwI7dxnwCx6nYXHT7l
IGJFxtqWpBCCKGMbOa7/79d2xsRkao9Wer5Rb8TtUuPOJE6EaOqwPKKAC6yfEiHqwJQ355eID980
f3n/pkqJySV4nljXScbDPEFjWX4FGujOr4sWV502hiFIGgvIEd2v/bzBJkOp2lmtdGzzzNMt3vwX
EIX/yWty1SR7dj5+A9sEZrd8k0RNBNERhLeqoLYQmy2l3dHgxCWXUXI0wuHVaGAZw91s3Dv5a15i
FCnGQVDA/ugET3G7u/JqAdbdPuNTVpP/3nlBzaXbqAfPqNKmL/I5x+S5gA5o3o+Aa8GScMgf+rfz
Hirb32nydou75RCWjJXo6jiyYL9muqvwYGAAzxbF9yIC++jb2QvVJsnG52K1Wi8Y0x+vGc+fmafB
KumJLW2JPeJtUk/g4yo1RGeXYZorpcHdgOSk6ho6KuA4EbTB85UWYLmdoKYIeUCSR8tucde5EHnn
yfEZOtPe9jl5KQzfhn7mK4bybTYUeIAvJ3MwY9AwXoJ91z1Go+TJnqAh47bHRBhspTi33ylzs6wW
wMWBMtxHM6KYhtg9dZR6CL0FlNz6WSpQ+lh2dMeUQuK65jRgvipj/iUHZlbfSgXLlq6Ca/GY+3B2
0TypKWqysbtsmav0FgkjamqjwGlQNQdYhNTu9pG97NI57bqpkFw4y+Dg40TRwf5I10JCnmkRryg1
o15QyiGCkEtpkB6wBBr7ZatW2HNyITi2PYE8Ufxc4/p1LqLyBvV85ihFPNPfGxsEnj2Ll/VKe5/S
saLQHngBBvRLCYV3p8zx9Agu171FQT3tJgM3RyK7HmIdLIb4qc7tH/dgkJRibdL3VvzkicOdGuGX
CMfwUeatkxIjY4qMIaOGyLUQ8gxE2UA9l1Sk11dFbBu7lU9XHFEJqvvh2Bo5ja1KEPWO+om59gtz
OjxuXoVswGYo/fFKJNYLN/tipo8QyoiSYu5VTAsRqPo38QNTb/hNj73RjUxBZDtJ66bqqiA/0Jd5
siFauv2UoXJd8NlFVbCeJnD0GYYZfFU4xMwfPQtCmVfK3GEWxT72LjtJaUY++bAZfklIjt1cY0hv
BqYZXThgCz2W1+PeANca2piFLp+0cL67n4gpSBgv0MOMEUsZnTyAXe4XWLka6KYbTh2UiXUmf43X
WVc2zrFlWpqzZURD1Zy3cx8NCrjcPKe/dS68/u8w7WGvm58SJjjn/JNrj0klnfNeUPuD7u09l0gK
8+CNLX10jxENNq5UJgiHZznN3dfRDOIXMgnsL2gIMm16kRi+kiLqvReRx8H5MAZ33/mZCnA3T5Cn
cbkOWVw4KOZOS1MGuUARjKOaXgr0Qfy0uu9+dcSrcjieH52+53fyVZkygaJf3FIdfwBU4CyuvGG2
y0ftp5sys6nggtlbw5mhBFR6PhSWx9GJdvgOZetvmmdRjWwy7/blIB4ua43C70/YIoHi3haV7ZJn
ubAjA4tTssWHzpgqDDqoOi0bAshBi7qEBzcZP6RnfDvjk4z1GFyq7lps2CbbkCrfF0cN6POovjh9
yB3ylVWCbhxOS8HTmn2tpHEY9I5dTGnTOVp0GpDd1VgD4xE0l9QdjuxbP+V/C/0LLajpISRR/1kM
RyRLe2oO0raqFOC0b7vV/lP27iR+JJ3JX7ei66dnreyuvAeUeadYuxmsok1WT28t6inOOo8v+usJ
E42vW5uI0FOthoQik73JuKFpb+I7cISgnN7oY7eEhqI6ASqhVhiSnEfahYeOYwWrJEOUje64XOTR
fjuLKuzVW8iUC9wjZq3DwyoQU+r+LJvqw+RrerElFunwCEYvMaAJlSi5jaJVobZVwHA3Q105Cd0x
mcjnrF9k/ISmz2jGCgVZ7iQxCmGsHm7jdtDdTGuZFeop6fnkGIdIMCVJ5e3dFf9yXATezX8841GB
64aJ468jto0qyE6Z4CzDXN8/lj05VeiTf1ZchrKyzHRdg70nB4M6Cml+OItVtlBXicNFjQ6f0pV4
rgHHZBj/4Vdnd+cDinv3XnYzgL80hkwpjU304NSsF/BzKDGu0JlJU3YaiXPwwa7v5Ctt7CT8aiDD
W122MQCKj+neC4eyoKu3LJ7Yh4uZtlLtsRL3wli7DoKy4gu7MN+O0wT4WNWrV9bUdFsfjfwhP1UF
jDwEHbtUww3OyTt7fTUn7MuVGejXbKcN7qFUALbqv+/IYwlnLRCYJQaE2URdhlf/PrPJHO7lpiP6
/KJL974EZCegr5JebPlrOdsfJXmY9d/oCAeo55A/uYQOh4EMoueXhaD/JGInN8BNl3Yuz6oBu4wj
KKG79a3tTY3l0lxcDwCH99oyQ7fREyKkH/kpWyitoN6mhByNaGN0l3gXAkwq0aFE/eAFnEryCpMg
Tx0TLLPdotZ+MaGJu8MfNX0ZnogcwHjscqavzKd7ekfGuW8199CyoQcu04xF0ITAKfiO6kWP/+cc
LgOuMAJqZ7i3yh7yYRdGwzvDfX08SkCL3ucquYZOXA/5I+dMz4gbHNhMW+doqFhGOY924qYFIDXD
bSyD5LjQqghc8q1/S7SK/zbAqxbrh4/+7hve0tL1Hj+JBDsakD6+s5Hp1zzYS4EX5hW0psPFm0fa
r2G53AoAYKTffRGMYIyAZVXVZpZe5uhkMQeusPeaeGJleyhmsEVI2C5DzDNHatZz44wFWofnVau6
bbVfyJzJNh7fxRWsA8kXekPC/xJ6QqaVv/XrAYuEuu5z4qv0kdiB3kWQjBa8/0QRoWDGUshFuoQM
PEWJJLTnW/WWQ7Znk7zsdppxymtF4Ip7mJKtpt6xJFTd3WMTSAnRWVevnHiF2Dr4wAdq3QvaynSP
VL6PewAuR3qzmYUWYU+0vFjAM8kBFsqst84y/pS9tzxc7ELvzWlCyqhJqgd1Z8QsrtrBWIrCdOmB
aBlnUSpNTRrqsd0CL9jw7qBSd3D+esu9PImdqgHCsziti9RUkD/J9zN0e/s60g9srLjV/e8i96SW
qL/vP/kyBB/9RPbkrB7K344u8697ynPPfx+IOQj5/td6yj3IZYe6JrpYMtSldaGHwZNMEVEtEYPB
HkObIohc49Y4seIXXFhkvjM3FHmq26+Z/DpcOiwI2nKh4R900XkRZOgFmQYOX/23woRGwfQkMor8
v65R40hSgG4rodBhc1WzS3TPSFKIM5F70XbGHdJNgxXUE5g/1oIWdPqz5OIY+FwhYWSzpQUkuFjr
Lago9bF6/PdPGK2cAZUV3z8HOXzl9kiNIWMxZjObbEGA9yG+Mib/DzQaC/gPE9qbrUkJPHQxd452
BWLEuIt8L6j9dhw0zABnI3SaqOIc2gLjgPVTkuEscheMGiRSfLBlwdlbwab9TTXYPX3gup7MZJk3
G7iz3I1/EcNOoZfjeiQBuBchKL1nOSM2OygKwEshny/Lw2tbVmtQCb6FKCjV6AovjZrtHMwSkMVL
JZXvh/+OG3IN4caNh0IiP9ImXvpu0N72YismJeYhXyZEGTKIUENM3mSYetuT9z2nZ0kkwbrU7bPk
ARTuZcRasbbQfpIJYAFfwuqltU5ReHpuENn760/gvxs4ZdVZ7tUmblJbuDR5VrLaGwbe4zoNzK5P
ftFYMpa0ucg6XrumDJ1ugHsOy5R/jnJ5NCWnhrDqkKs6OqwYgv3TgfDi4K2iwAHrDXv1BWW3U1la
kQUEXNE9px/VFHp9IArw9sivD9AwyJb9Jrjm4MUP0Ugv54mThCr+c3s0TLAlOmK7aJSRu7qfUlN2
zyyLu1WuyLX5y9N2PmA/iBdftaCAtogfJR4hoTRyUdsEovpQAK4LCfvDu0KICgCGfWt1o7mriX40
uqb8BixwZ9bpLiKVUHpGMkVVPLRzQ7rew/3KlaDonLZln6vJCtRL6maYyj0SDuIYk0pgnBw74OAj
Ifxc49YmAJO41HVF5lJoass7JeeWUcz1+szW/6rG2TRAO/4mmgiD9bMLLx7ugE8Kgkur20AHcYn8
RvJudUJS5CJftoH6suyd1gg31a8jEN/YGm4zzggxoMRawwqnjDszNMy3YCH+sLYsrNxcb/IUk97G
tHF3Tk5ChCDd4jqreA4Jf9fPhpHJ7gj4bM8tvMzMcFsXdcLU16c2h97fu8Aj/4ODvWfnpnBdhcv5
X9NZYmZGTWhIs0sgCnU7kwddu0tXq+v7gBAA8EAMw2HJvyLBLsjBdiA1NLOY+OoHuVZ81PjTxypp
j/1Prnz8dwBNkqvKhzligNSFEvN9FH1Xz+PxVfS6omuD0scNkchVcJnP9Yqn+ZdDoQ6GZze0BW6x
qrwHGeQQ2tSrX2ARMNV+qJUOUhEdH2GOwBjOAwADBYaxfrSnSpajGmDoNj5+LavqN1EQ7PQLlXxO
i7i7uTC3DPC2607/nHRTcda6HvC8hiPpLgDcThQqsuVsbfk7E/woj7I0Q+7R1M1sEJDE/L2adMgC
vKA5tgCuITHxDlKy9pdU2ZWds7hIc6LP6OVZwCFWyMRyvyesWaj0cY/OpImBpJCoiPoaKDRgrDwF
IMJV/yM6enkopaNrCgUcaJ96Y2q6kevvQwSoCkbhslL1nTrFEksywSu3JGiFABpKg8emZ7Hvp2b/
coA86ADgFpjJhCfbe92FUwbqoEj1x23NboZFEnzL4UpThq9OnT5Re9eRhWR2/J8vqVAsTL1iqnHT
wujgIDIlU4A2TgjJRukWrZwRVmkMrj/VflZAtCXUpdN+jDsiSqDCXwgnlMHAjMjPuBE5vtBZMoVy
nQTJ5Dlc/90NOWQXLdhwKRPVRAlX3Fgkhob+yKLZdL91qnqwOI13WpzTDA1aft+1UGqEaUtOisYq
z1H+wrhvwjzxtgLz8I9G43b1eJmrWcrU7Iap2SUNeOZsaygB+PhbYqXFkkjIrb/J73ihCuW6y5ks
61vZ8MR5ZgFh4447EbC7bIlBCnsaGs2njtZNizfeODRbdgoWYqz7cnRGsemQXkhcwN/J1ypyTNBg
+Z9uAkWpmqFXb8QRP2+UPlsIgbHiEFqZDM91cDyaSeiBycWTAuuKW8TIieOyr0wMpuO6bP3oB0uN
4xoFcDg1IfOfZbQ6arvNkVBlxqlcJHMDXlwRlsZ+b9YxVh8EsA4Htrwwtv+4FS6pPlZvb248mvAc
TYlZUfpY2x980NBlDv5MI5Wa1PFFnxFARn1V/CvkTHnGlitKp2HIg9WUhU8uKlLiXiooYfFnpCW4
nCCJNBk41gSVTiu+aTD1QfN8fYBo3R1JY/IxwtuLlivRF2qpZpGMD6A2ypBrQ3QU1H4pZiscWjo4
eFIqkHVLJwKrP1nVZQV7KOuzwYzCDk/nv6z95OpmsrAubi5ZhcCBVGgWIpYYn7PO5hjq1wMBHJ6O
ATPmmmzqP9S6S2emuo7CpxlnnsQCYHQTsZQP5HDdXjJApWRRdvwGlS3ZQyFT3arayySR6i1rV5fi
P/1ttDiIaDQ5sQp2/TE8IoWjVW2E8VxsMJJIsBk4pPOlJzwtGRVPRTer1irymKDewO7JIzOvQXHt
K2lVH45LBVBgmm6goerBwAp76X6SWLSoR8F48ed9ejGZZY0anDKukIRPS8aWvxsO5pr9soezaO6l
cQ/aKzYRd1mRZWVp1m1huewY2M/Bth/QIiGGb/Fw4YBngVwb3me/0pTLWBD4Tqh36k92TVTSZ/6W
yFotcnSuwac2PLAJFu5tGa7wUxdxPlgnWvE8LjMM1mpg5IhGeLOGg14FswxjP8UuLEQcO+ZPdlAJ
a9YfCm2sW8OhwSBS3FSKXjCso9+YRCVmNPNACCtL3HWRRKQPR8J9MwqhzJ7vi5iyvk3CaGe5yKZ5
v8oKNZJTXaY/ZsFSBUj28HKr52jPziVqOSk8OK5Z5L8uaYfbgJjf9iRhrE4i6XOCGO9e5AjHRmbe
GV8CwBRj1qiWMz0W9NjQZ5mZ46TRWvcr6WXPiCgFpYfv1Cj+SCXFgxldBEZOyRoBO6mqvJEBvig0
N+jHxbSEoVgxF3qvqxKgpd0H9hNZO5i+h3xsRkZnNLy+DTuoojcv55TiTZW7YwByC+8mj14dfQZn
Q4kjEXiX1JBQonoP3vPQ1WxYon6rdBJayjJJh8lKUIaBSBLmSnO0Ar+xB8NDvWzdrwHnarA450Iy
Bkp5hE7KN/fCgDG/rRL+S1NX36ldqdFONKDnAVvbezFvetZC3ras79Aha9GxurdypMeLZhrBwUIL
qm0ZWPg1Q4c0dFOtHTJgC2hEBImQXfZnMduk5zACNdVDESZ8cNvn9QHV+LQSxT/W41ixVxxn7Uwd
Ej0zQO7Iq5AduvjHY4qJVa907tkVTertP71TqJMIDiJneNPqF7qFgekb4edDNPr4Zg0j3YedrKfe
h39TYu1L3awrhb08nVPBKv+sn0EUbG6KviOJEJAnI0V/qCLRffL3INk6nv5YQxXaSe6QQa8zKATc
66w12SLnFKkYP4rfD/BSLleixgrWPFvhmobRPrs1q3ggOjvGZ15gJ7b+4LI79kXwGYdbw6Qyl7vX
YtQwVXRC1RMlvgO1nQvnwbmWVz4DChKuKkACB+hxhlWDd3B0PeEngDxculCcU7gAIJyFw5e2zWHE
a0icU45+Q0MUDcs6gXkAdr5ieiCnkvSNfZxFV1N/CF2gLoDN3eM44XZqNnA0ZNaqY9w19wB+A0Tp
2RhtvoR3wpupgxPo/T36u7Ol5Tc+JChO5GllNqkMLttFySuYjp6ge4cFh618tb9t4jIHmfHOXQKH
ej7Lx0NoAdFZUdZvDjYHm6VnKz7rpY6GPprMnHEeVsNxE7aFyGErnVfulcCNJ7ggI3Ubs+n3j1Pg
SY/9aSi73aJ4kIiyO5DjzJ4rSAHNNmA+mtusv/kS09jR1iCydbdq+diexK0MS4LBOYahR0voesp5
En8x5RUhlP0JjD4Itgigvu++WWEhOqPvgXtLSl/cd6B/6GNaTZK1mufNSFTHwL87Zm00HD9P/xqO
7a2YAva8zOPehI9mTcobbluFxUezeCjrIwXSYBmePLhwDfa0HBDBV9VivwiXwj4AjUC+D5q2i0j6
IGKAJFQAdtYtDfdsfP6lGsqbV69/hGCJt8SUfOMrkfCPmT2YTYL0tCnYRSyPHMsd0hh1ctQ0KsJc
DfBRqTAbNYECl3GU0yj6plUTYuvUV6/mxTuZyA+jcRktuY8GuKKCBzA07JEIjcw+7deuYtNt9+hJ
w+eXfhLbrtXooQ65PdJfWPE7yKeCEq3tky/Ovyw6+qUH8xlOEH9hYS7AgwJhskKMdRfoB5tpJ6rG
6wP3NSZV3TD3RNqn7RM4zxVQ7u5lrgT4ZsyjdU9tSTgzfo2+os9wahL4FTPqR4orPULGM/3tk6Ti
iR4n9E3q17WGW8qOy/7QwnbqkmGBgDfA85peesK/BvyiMBZvOw0G66Pm5NRC6Vyw9S4fVguiVx5h
tzYqtN4Oy9wDeSz+FVHjkMERtqk5vhyhxEB1J5pWOD8mXefVSnsJPY6uddlDRjSoJ6gU270dwyC4
mnwDsf7uVgTnVFbT1UvmyKlfSr/v2Tb5gQPkj9IXJdMcohlmq/+HZjucCzlrIa/k1KRgtvyiQbGu
n+AvM0w91fUhMGfrjZwYdCJFZmr6XbpnY1Qk9nxzO6p1qN7PeqJwbKRleMVsRuv2HZyntY8vkm7T
qXUrnDicyv820iqcDED9KSwBNyA70tsSYSJEOU7IAA1z52Xw85cHqQsXlSjamxcn89+W3Y4rHUtp
MomAZgQrjg49z7qsI4BmEaYSxLSzaSL+nvqmAjQ33NQBejq2/sQJ5fHuwg+5TLf0O4S0RrMUUJq6
LpN1MNHk3zOHdnEz48Oel8gMDPT4suTYwOr7aRVMlFVytp78wsDwhPPxnHc3Ik3+qgPItgCfwWER
8gFeJDxB8rraNgnqNQQ+T+Ae9HvK8IUd6CZ0wwfn3W8jyKnrceS7f2F2udIASB8txZdMFjkflYbb
wN838uwVB4eBP5RN4VopPUYHI63cPTTauzDRVFFrNm2UKpGMVqNtXCg90ycyzOsYnz8s/Qo1Xbr4
/p1PzPjw48oqk7sCBYg0EoS4uZRLECHKkQcHRh9amCqWx06aVMYL+B7X+qRoXChk+RaOafqZqitv
UZ0lUfRd3eL9HP/lfjFN0XN5uvzhLEXYX7zBRyIMRqvKezD1UWmeYcAPmh7Ozal07L7LGFuRb505
JjRn8eph60o0WSoVDCoFUSXDwlRiK3zaUhKXUqTJksmS61UT6J/ldsza5PsZ8cL64jmdJxxSLYWR
1POmlH3GBqdnbN5wtX+Zn6/bwRWWhvOJCwjxaJ4nCbjib35nEhhbpAr3gyKEKFGDVw5hBx2xF4bm
wAr1AhqVGG/0Hdw4t+69MvzaBH6In9EWf67zmj9QoHywbt3iHUQMTiKKAw6/Aw2VXMB5eiB1SdIl
p1xemp1V4okZJ3jkX/9Pt0Iv7jnejafcghkUvRsYYmj47+uVyAWaYmql4VWpnZwK/PFvyaQbpOjS
pMl4tgpsaj4QZuWfLPPzORzLKIJKQEaf3J431xPVDYr1Ts5UmsNhm8HXjfUGiLLBQM60eQ17xBOw
hffny++ZvIUOZ1Q1GBFtGj70ASyTria/s/NPZuC9twu3CerLjNvO6fGtvH4lnIs6haplfOR9FPGU
wL0l9BLVGgDK8do+M/Kn0d5grEu/wK7KJliGWJHTq0R56EjPCa9p8ssaB4TXY1qoX7GdMEct6Cl1
IEL1mroxG3dkNJSwUfbVYD1buvCBrMCVtQH+wjjkAkQUOJHlZVy5HIkVhuEYN2zVkrZWprpUNy3d
/6LpwxWj2xIJUCPbSxQKC/9DAaQS16nN6AgtZG/rayBhIxbtFDZoUW3ot8EVnF0/TLVHIHcRcV95
59VRrHuYeusQrBjEk+lk1kT/7rPx5mjD5nsd00ilSJmYS/J0Tcm3cEVEQ20gRJ2d9EbDmv8q9T1a
gM+RN7cenTHYQYJY962qm2ON07Xo68S+h6pEeugZi4yKTRQvuxJw4HNC26rZpdWkP3N6QsP63Qp6
6qS4/+QefIr1AKUqbQD0e5tLnrdW2z6/Y++/K9RY7FWjYWMCKEKln81ZvFc0k76p6dKaE9CEPqIs
XDv+L59vmA6s+BK9YdB/n8PNDp700WeqigPVOGa+cPHB/Zu5c1a/CuqJ8uqmfXcniR8Ahr176K73
tzaTRmsb1sB2J2PDL8HPDfEOd17qZubZsGIQUX0mil33tAwzya3ycQgIYT+icxnTT9of3MVaiuvj
fJ6eKaAYVE36rFn/N4mpeFiT2xvPCSj5UjAptBe8mI/3sATBH0WB+wUN/EkAbpsHpqKRJ3KSDkys
T72dS9Y7fKI2EJQ3Y9rdsSqPXeSTWUq4YuF1MLqa1GYIaOvN7MSaa5+QBdJO4brP5FP6d+k3KIR+
lOJv1ntHcU+bt3D3TR5JFrl4GR3nlN5cI/AD4ghNt96OUwdgHbMHy7FOLQpYH+qRgqvfgRpuTY7O
59adpojrEvf6eVob746QBZjl9UBmFqYy4uGPKZ51WD4t9aqTGYIYwBPmLb3QBeE/BijXJBk3RHiB
EIk41PDaVM6TnnIqiLTv4cANRWRr/9Bmeon+QkAnMx3YT/CultsySAvrLZu+CaRABot6qIA8f6PB
YGfa4itII4JZdbc3A3zC8Uhy7Owq2uecIvX7EbtXLamWwwyJt7/bcfEGi2a96JC5C9U2jp4JYC6r
n1LNUBFXaSTgUUyqLUyeYKA5O/UCjy7yosNVMEbEdXGRbn5H+F5O5njMTc81jRJKrLiepazEe7YP
axJ5ay60DiUvA9BN637kw7uavuXs/Z+maqCmX31RS0nKYY4I6nlWtDdIpPszL/YKjmprMw1EsLye
pcAL18/dLmN8l4uW1a6ovsFDNFzHJECqWr8Cdb3jn3w7kVqfBNgpxLOLwWhxepygO2K9AHRfk7ci
Kp5BfGkppdaU1tEfOwUd+dLYcN0xY5OXbqFhFQf4ALOA7zSiE4vd9jvZAb7EVxRnwR1yArnA1MZo
DXx0HTI2keAv64nhIzmJZmPQEWuPAbmePKfdBeRrnzTisOvGiUNkl0dYNfUouVKOqgY95JcWgZXm
MTudaqG5sqJqLnO22+LWLrUncxAOddbP8llI96QlOwvhLeNotGChfVG4DXACNjHTL86l2xyj9O6L
w8+05tfDiNSjbJH2FAQwblCfnJJcrYSlLpgFyLzAG8auGOHx8YjLWQpUAjDN0YSeZXI9LoUrrc4L
sfP1By5N4aN7vV1Jz5xx0Kv0mh2TG5jGf1XXv9siOv5zBqn8z32Ejx4MiNehqiwvEWWvkL4C4n9Z
K2oKBHQ4R/ScDJqOVUTzBSPkqG2HXLq7Qdw4+UAFRCXbnZc2QuXjcusicvLzGXxHJ2hdNpw+H/0N
8YXz3FfbCeKqecbEjgnKtGUssqixcSAqCPfFGtqPaVt4ZKhqCqNgNVBUL5QDJ1sXeU2wOdioyDWM
OWq4dmgEItkDVrRd2N4ZdTHauvknNqzhR82GEamk1jToxwiW0guKlaD2Z2Cwffg2uGJ6npchWDf+
TbDxJmbGT1D8zur6+rz3K2nfqfqzxJAQC5hY4jDwjeED13aDkJBleheYy/jiuP4Uq7ZCTh/Ic9MU
ay8yQ0BR4aNr6NUafFk4dTxa4oQCh7ARnvhfr4mR9xiV9akch7UDztbY7faPvhK2SjnWTwXtRHDO
DZWQaBwSQc6RKpAmEEtbB/wAIlz/ZgPmysoo2JAQ360TDKJBJKoTMojTgqw5Ux2VGE/iUWg2MZYr
zCQQYSogfdGZLvySPoSo6idlClnqF7u09gp425ceI2nOWvR5j1fmi3nv/+rU1GIMo9r0VxhS8D7r
Zp0j3E0TeGc8qy8L3FyjXtBMjHeEfN7s+yA8vd5yv1F1BcbyxIbBtQLqzt/4o4ouXKG9F8r7vn50
F54PTfEzJ1ZzLRrkaj5+HD2fmZykup7fRUBqdRpsAVikMLe3hKeHNgSo//a8BQWsCiQJbIcQ5s+u
5aNN2D8r/wBNR45Um2E3wYLWIylHOmi0Q9MIwkRugO9tRBAhpD9Bimh4iPjQa957bOtL/GyuCUgQ
2/COqQcvzy/UzMo42pzOwJ4P9BSX8839t4blOMkE191Umr4Hl19NrFYRIvZhftiQ2NSOY4t5GxDP
e8iLsMg7d7zCZLGDMOO5ziH7OwCag1bUeWViqDeRBKmvzV9AN8FWsZhOdwe2LtylhzZXmMmQjmXJ
Ygu6Gz5tICCutk3Y/e139kS5L6t19EFrgjJrQFCcQQW1J4T4oKP5tEqqUeEjfx4Ir0/jY0ATSMz4
0wUZbyvcbazRZX+g0/cYE+0FWg+mYrmeG1Ogf0CJZ2xDdlZEqEhIISf/X1ruWhp/50N3FP+tBgjG
dsBW8ffvUDdZqA7/xg9ktw+MTOalstHvTBJqyhOm4+Wvdw0tYh3m4MD4yiCdVeM9RxTzkJK2KDBT
V1kYFqcx5XPvgOmcQQPrKCdpuPKbGMFZsDv/LNYgA6bZe22/u8idYOiWJGsaoZCkYx2oaIJqCeSd
UB1P3YRSLxsGXFwOWhtSTMvfKKwc03lOIJ/GfDGcGM8VrnuUBL6ezN/TeTq8UAfVDZOZ0c1jlzjS
FtYoiklqMKulDwUDpEfwLWlrraCijGYOG4dEBt+HoKASQi5169Mn0aUoRVlbUie5D5azacKBzVaf
too7vuIA8dNXFvcjO6zU6zuckQv6qqmfbGZ00Zu7ZkMlJBxV6UKEw6ZyRprW045W0tCrM/T0pFQ8
gkVtex0eTPsay+IymtkdF5bR1EYbKJjkqe8B2UkHG7iqKKI+ZOu9NUoOkm2IkT8XnG/QhRgta3ab
DoBbonz7g+F/kZOJRyQ+r6HVyhMNVBX8BvXwcFxDAwAXWA7xayu232wH9jhhjDpEOSAGo90PahFS
RhosVc27p1nkSxTQUewe+AVunPnlOFD3LLkngbIlo4Rrhzdc7svWj6OLcWz5WpUIhMXaxu7qujZW
9yKf621zozCOkqC99bxugnDiZt8wqg5Xw2QzDXeu12uWTywJTSHo0maGvmaEAeuSj0si7GPEONh4
PrL9Spxq/wOvmbUPdJFcS6EEDOdW1zCXem06T+WUlq0MEkJxUGby0tL8W20awfR2ejywbIuyNqHB
EBPn9j1suIW2D22i2Q56U0+UIzaV3K6HCco1LCcTgRmR7lFnETCRTtl1zDGMsBSX50IJxXMKTFeW
Bczh20M64wHhYIWOvNkKb2ey506YpHrnbbFAQSj7OlzCpx7DTyouDCzVVSpuPE5IT/R92dix1YAt
ahFdEfy9CA7GQROUh7I1oxelqZSN/VpaKkvg1sYd6ZliqebsgpjPv8h92bZI6+J6NLTg+ScE72e1
OybUtDlHWTsfXOsOy65maU2/ZN1SHIehWna8bW9pUzYaSA0Ye5//E5k4ZI9qf00JWvzm8HpY8S1m
y9gENHdW3/FBs0e2MxOGqVJIaACTcgHor11GxTbaxuUXpXrmS8iQQRv7xaqO0lCeW20/2hGIBEEo
wijcgVeav51OLWwxiA/8Eja2vbBPyw6vnodEPptbdcXWeQEb1Lj4bZI5QP3RxU5Sc/IxuSo/e3pp
Vsx5uApv/VIbbzLOyiBIuCn4R5aio73Fb07D1PtIY60XeX1L/hGWX0ASngfQrkz6yQntXkQaoIff
qTs8AnsaAZ5XAdvQ3eyVSzE1CCuqaHmGAzswICq9KfnShu2qE+fh5Q7UEG5zmuUDQ+a2kXFYqDMl
WCldZ9NvgBbW2eyNtIlTA7eKJlIbRMF0pMW2ck4bmK1IHNjnGRoMqFVUcI+++5g+3A4FZbbB67wM
vwMsqeOfLoVnLrA0kzIqckCwO7HB+aAVaower74LNdE2UWn1MGWjXtwiotanLcCQmC3BfwCozs+Y
qzCQnc0nl+EHcN9V8IgQ2HYN7sDajbs4nqrPiP+YveaYxLfLwAwkW6a9yvfleGAhzPlfHAoyume3
UmAhtsGoCpHAbYa+HRJhmAmQadYKCNyCW4XP1W3rWvDy6vVtEZgjr2uGGL/Na8xW+9buo+h2vgM+
u+8sdhlutuT5Xa0XkZ6OSSc8fsubYktbuRp5yVxgBGnFy00Crg/wbyuRKeFMAvKG/rM8JqLDHoOB
PGkgcYpDI1U82jMWNYHRuD6+kStzR7E1LAM4lcF6jVKFPpS6hOJL8cMTgXJMq5P9Dq93GhgMrVmx
iXRFsU6JWKt57ipjMY8caRjaCsIkwKP1iuVKrDIPv7gALxK5hNpCDCsOwz60Iel3UNL9JJlJxkNt
V5/yzUJe860mYrFEMswT0sAC59zyBpbV11+xqFKyBWo4idfaM5R2RUJxSmAl/frPzcUEGJtHSbtB
CyGBdqPGabs7a+ADxmfqi7t6HIOhpforPFUXm9cqdx/A7wbcHvD4+Xy1Cjcpr2tVETScXFgBIYOX
TyE10uzztgJ6Ub5MWKfwbhj3ct0L2rhY3Mq+N1fYDO08CsHSb7WbrOY7o4q8HR6WXPc3Ag53vM6G
75lMeh5keR3DCwWQtjVDrUAyxI9qH1N+yNzmz96JhNFcvxKIayVolkSgvgZBGV69p0oYXT5vKkx/
AQqFJf2X02Vu8qmk5pYnMvdJ67blyvQSkxgpHLDuvp6Od6CMCQS34Utre+IJJW40Lb6VGUeBCUaa
Tc/4fXLQ0Xhf6wzMU2Th5S5Fdg0ioszvUqkiGyGAqWP4siLfkBuJveCBqi58KFVo8jy8lKS/e8gQ
fegU4mV9FI68hX8Yk4uCnwLlGes+VvQmBlesMpIReIFu1fTkmo8tgECRr00AQ1FSRaUKXQXQWD/u
LjLabvE4fCo3nQMTHsZ4VXJmX+q3mizmGOpe4SW8xkTw7+IKj+zPkJ+CunHBBhxhM+8OcZy+TJUK
viOqkVGK9VXr/FzNqIKE9cCgJK8xu+KYco3oglpURHdmS48h2Z74YBDMGfka9ZuowwxS0sUp+9b5
OBGJ7rJ1XB9ImgKR3sAgeGcGEAhmGHadMU5wVRZCM+KvPnlzQ7p84b0wLaMnC+nUaD5Yt0XNUVJH
jjRj2ktFgvg7pVSnhuJnCqHeWKSWg3+N44y8ep84Uiqxt34rzB3kzQ7apItcYKOeO+jVD7T1E2aE
Ran+4KNc86ai5TU04CHc9WBz4GxYlsnO6kGlQUI9OXjkrI3fu8iKNSRYVezYuIReDexUynlH8I90
Kpt+6NbDZzxIMwEYJKx6kQEJkRRJdC8IlWMTDRjJb0VyQ0hgZRS17hU1HBwFP8WHZoavYDIMclG3
/wDhbQ78JwzedXkDsLB8kevFuUKE9yrFz5Brg+Xdi3vtvU0ZC8ew/kiRpbzGMcfULHE4XoHk4Szc
/9Z3pbzzabIFi4Ildgv5AVl0kjoys1jzjz1CkLzRadMZtvadynoV2DwM5dbg/PesQWbHTizzwNu8
JwDKUizLb2LT+UhVIu51obTQQGafRIY8EvtpwPCLNqNgViO1WPBSdKY1sCs29go2MGUTLhwUBAVX
rRWJewadIj58otIUy5FM6Eoqa0ZuVvHDajFrWPr2M2FgqFaYvw55KoOFtu9Dbw5ZLhZO54Ncu66D
SkOMCtle7vUXe5p5THI+ri92cP6xyzlRU2LtRPMWwsO7ZuTIf+oCXTSxdAmsXRl7HHqnmwlLjrh7
5ZwOE3tKieaoAQTo0FGldhwuRED73nn4lzRnylBVTTKypWxS1O1b5vXYB5nvxnWoHcfEoSKHcd1E
wlkmLazieueuyI7H9QgfvcrgXFSZRFtwQeFHZW2PAzyiEOaOeD8MjtLD/Y8Prq9ogI9pbWS5wTlT
7yhADexbAiTEkWVBce6I1Makbm+IyrLZDU5LodrcjWVvk6VTSaYGMWTbEs8Bv63ORex0WGrDop2c
JLYSBGD/kBoAecfB5b5/33XVMsBe/hDRoBT9u0uEwNPvmHm+21K502LYCG65DB7Yopy+C/8sqYUT
c1a1O8WXjnpMlS1Y8YmmbJWKHXv08IXOUBLWjdvKexPQl2rAVSwdICO2kJHD5DotOfEibebxE0KK
Z+YlaHsaP5p3vEcOoYAVW7+xwGXgjwPAIXd1206zfU7jHQ1hKIBRRplcJhGqqQ6PupiH59bb40ba
k2N3SBj0G21RqGZZ9IJju3v2s+batp7uDIAUBW+mgQlAgokMAxkfxKc3C5uCW/d0F3RX4wk7oglO
cnY8pbgoxwyCZJT9x0fPwXiDNkjUorZmnLI2OfvhI76Wng2B2IcsBGxdjzKTy2hzF1nztGioAcW1
MUHYwbtBLiUONkFsQ0buG/YZxV2Va7uj5t9DlAuKvWtxTjFtP86u+mDUY7WfiZTSGrl/76FkQNU4
pGSyQwAvCiT+MRo1wb0ZGw24Q5PBKdgmTUUdjJas1UPt04y45KIo1N587TmC3D+G4tWa4/Ih0xNl
B3vlPajfbgtJTIwyjgBvQtlm+S1/KY2TiA9IQWUMvH7MobcIoQ6GrvD8HgTdJg6Tw8+ZQT0njnQj
C6BVNDdSLODhXIvxemg9Kg2x5O/7ksbH4iWFUUyj/ukHm5Ol4JQQYZVKGVTUYQ0Cjv4OMBansWWQ
nakcO3bnAidJKSEN/A6eyNe1wy+ksKFeUorAJVRERN9e5Rl3Hc79x90c1Mij1lbXKeuZkiFKD0bM
QtNkKFvWW4WgHbVYHUYEtywCFRbkiGnlwtIViod2temRnUmE7/dsgnicmWrDOcjgDXQzWIvWWsWM
Yh0tt7OiPqyUFPnNqtCNXO31zXJmuWCoDhXXr88rGjCZDOllyS0SHKhP8tUlOW1u0XvgP/VCY15/
rKDHKuIZTij3GhPUISndjgvva+zIEZaFeAOvbVia4JNVYb56wz876emwQ59zN9Bx4TQxGX+BVbJQ
PymUTD7o1/OXgQ1EGM7TAZ0gZStGQ7xlPwGqlDEm87xJ1/LhvUIwtMP5PSM+afdXlcpzJCP1M6rh
Jim1AWz57SSa8ngrduCEC3Z/zpo+cgzIIGpreNpo5/+oa7K3ZLEuL+T1JJqWaq03ighVwQGovDPf
tuWX0jqFuPwse1a8VyR/HFOLtvxIbnnmAabNpV3kD/kF0t43Ryb8qbbm8jPpzNiddC9fNRWT6Gsn
iEc/aArNdII0qzRQGSYNI394BQ9HpP071hUIa8X8ENtX7Z1k9pr+5WQ6mECjuJ6W8mjeolNBQjki
wGzolLyDUJtkWJgq1L0VnoSKEQI9mND/e01yZYEFkWTMV0STzoeafCtrCLNmO91y6sSQ5noFLNqM
GiINKjdMaKy9fxKi63KPIEA6cVnewMPJwpJ3PsKlXMGFvjSfSotJ37Xy+jFA5xlwuCW5oTjVWQtj
X49WDrTehzFqFNBKiUMkl9iM5DC9RknnQx41iWscT72vMMS/j2rjq9Ys48jPb1dA55O8FTGQFpW5
gYgABXQB2usITM0K7uYfPZ96p4AQJD4XFCAzFohLiruq+5xCia4YOjeOnE5z8/US5rWqvH4W1GFy
gke/SNWwgaws+XyAXwJPUND+9DHRW9Cr0GrUcJj9itY2j8wl9nZGeJ4qLbxpEJH+Nt0FbCg37hcJ
9kq6LQOimdI4Y+DdsAEkJQ4FX0WhdD5p7pHOqvNIAR+CPg+DSNTjLgeRVgNUTtQYlDEX/2ivwJUY
CekPbqq+zkk+5hgJxPjDsZ6mkRUNes9GoXEAwS1kALBiLb0IGO90xF0A3/a/acXJ0V0qwfWJlphm
sOAINvUbt1mg4M+D2XUGU2SwbPHSdhHX/vYmXXAy3Mvepe0FTVbaRJn1Y8JOAcxpZ3Xrci6WaOCp
AGGybpfzD9Ejo2CllIqwOSdtcA7w1/OpOWeeEPUV02r1P5VccCxH9zubNjL4+ZHWEyNOpgDzjFy9
vW7F1NNprDFl6sWWTdWsOmImx39rf5cJ4WJgSJ9iT+/GVQLr112J3mWyTqinp6Ka0u+6zUKCSq2y
eFUmTkhZ2seylJM1HOlWtaxtoCtPjBo8h+ampND17mkpyGJqU0XpLKMWNz1xeV1qm3LNiW1FfLex
oXrksZIvUlLjfo6jEC30144TuiTifKpLuPPVuNiazIXAgwWgfwZLTHEcbF7mYuyr0iC0yzOiKT4Q
DnHCEf9JVM9gT3a8fKXxVjMin3ASxmWQf2TziRvDpjtF4aDmAB1RBEhS6V1fRCxH9ij1vl/aSO/W
MkAQPyyqg1/I11jOb0IvBD57RN+EmMngtU2H9ckAv4hfrglO1aq8N5HhbvOvxC0WJ5U0B1/4EL40
1GQbU/kN/jaz3z4alw9w+10YZknP/Y2bceFJ6mJVsZDlNGWTkjSb1VAVgHzhQVOyoyEszfsAZtvw
LNKJtRbN/ZcIxoQFBnKu9gL0C0s9PMuOBGRr9g10tj4b1y289K5ZQsdqO2i8Q3lFMfui6hTHtBni
YkFL+xAiJFEzUq3IX70j/ivfnPo75tfiNnpaBet9guvyv98ocQ55Nap7mQ2cpWiKELaNrCTUSMam
aICD/VkEb1gQey+zKeH088yKrL57CsHaS45coS7l5Z6JAzAQCzczMbO9ihoT2dDPvg2MNLbOuaZZ
P/jh9TnhZCmVycEtvmEn81Z9aPWSBcBr9sE8h8oUzMFeNOtdTlLyfc0A8xrdfpeIVOX5JbBBba8e
31XwWKVYUK7l3Ewpf87xuhPtTYB82gMxseTZpqFx4+X5gqeMWbKYcSIoz0z60ihOLlqhEca4UeHG
MLv4TwfANdjhOpGvzQPQdJXIG4RQ8rSUmTic0b48KknELmOn7apdt1TzTKdBJOjIOPWNyL7zg3c+
jwzEjwANKW4LPEDIKm6rHjMg+9BQb+/q4+1CJAtfp8d4h9eHN7ccS5Fd7Mk7fwuKTSPeI1WdswWU
xyy/C6uznTpn55/C0UriHBQwu8slGqDsIjOGLEZgI9n5JJvQc6cxrb91viPqP3wuLda7wfAtQFnB
n1d/4eQ1V6vE6Owvo64JKwL8yhTnBadcNf/IbH7tC0+MUP7mnRoCBl9LFzEo7LEB/GVQ/v3Zum2U
thiD23rRdI+XxlqkS/HTdXU1zE/EQIfHkMHbL5jCWfL1W1+PLHbWgvJE7L8qR4L/5RYcCnXqr/zX
5oGOHLnfoqm7qIBG6Nk198X3DJMvDOiz8o0c6y5LxwNYOq9Dda3FlY6lzmZpn618QQa/zJfT+gpG
u6AIgeW/sk7UVkhbJC6PO+rrmhrzPmPP9tGi/NeC7qWJxkjgG2JQ82xo56UGMljf+ld/yB+CVsAs
LMzuqsuvSGlAeXpwxA9lqm9r4i5B1MGKgM1mV575guMfX5lEr2yAuSdq7K/96HYoJy17h24cjwIk
UvN5qjgRLBVh2dDjziM7+yK6VOlgPJfpFEtCYQsGZk2ETXyiy5TPeln7NnFRNp/R3vGzOh1cHqlp
kqUKzmV1pFsmPumLftoR22/cLGBFYHWGuK1blSKY7sJLNhjQb1fzEubjkSgCey2Xh1A7z82SpRs7
Q6kpW9JuCy51lvA91pJVtCSZ7jskUZ9/DMlluEzgYjKqWOT6wbJZKwYnFdkAVWqkSBsF/fh1RZpu
y/krVGu2VdLHhbbPFl8HhVvhhBN5NiOg+gFGQxxEPZRcTt85Ch4COvkRAdsKcLLqpvd86ocjCGdE
kO2cKGUH5pFL+NxT+2Aq0HJkboA57D1T7zFf6wqXWorz+klJAlOuvd8hkesooLxPSHKTQ/NsOzxY
sGaZofzSmoo8ePrnhXkrH7mfTrmQaTW22MUEwhMUIm7CHFNHYMcW3uf04owh7nWXlK+IxvQN96y0
MeCoEkKBZs6/4iVpkiBxTnpD8T3N26LR8tHybHg78Ia3D4eE3wAdh80lFUUEVV9CX97NIQApK/Gd
PgU1TD+kZCi9+Tv29fkIF2MHdAAd8/n+6lMMnJNoLv2t1bjBJoD8yMkguvssW8zjVthPh8hz7qDk
PMbR2l2UCbH+rV/ikk7m8qAWOxIE+ZBf0Ik34WmompKanOo4QNDVBschCIgQja/8oIZ6jTsYF8R5
tLgXozlDg5SNyceFw7uanGcewN/84WS4bXAHz6v7ne+9OFihZsl7wyMwqCDKLXr6Ij8z9kIhMl9L
Ob4Fsfq2Qbnho1tuGo0Zah7nTahhiWZVXQId+2p/85D6A86+UpoJpXnukeSuq9oGAwZ0A59XU5iC
2kPADtBRAZ0vm9k9LU9LKdabSYxpInLlnI9q7daP805LhHgP3RBVM9SSUVcd6Izah2FQn4Wtuowl
KTTg8xD5/z31BBvfqXDLz0sSqG4uvqEsiTZwf07C8QmLS0N18/dy+VXExh11fb4Ogae2KddRJLu2
OJfmWYIu2aDz8HHXdis2eqCGcVZf83P70hTbw++jWR1tx221+wLnhB67u1tIoGruoGJr2Cb1sDX4
xK3Kel7RKIjFKEBUsAfuZ4LRAZewjDFp+ftGMaU0VmwocHxrf+tCKszT95Vqq2yP8I+uegW43lPB
GiZg+0sG9TDJ/Mc67LIHVtOyxsDRJptdrU5Awx2Vu+BMplaM9ai73B0defaZMjBSnMT6RvaIwQp9
5Gs18qlsAcGF5yB0NAKdgc/H0ldlUPnVBMZyS6n/hyG8RKNf++Neg2EgcC6MaoTG01WLLmiQAClV
DSfPlNJFwtP9H1K9ohSPAcpx02zX2dut8GpFK2l3sK+J7r2XEQYdsGBk9CeVFRvHzJakuxMU/q1J
7EaBed9cWnoku3jxCPKghX3evlVHFsCy0dp9ICYEkgBViSFdqHgnd0vxhJAkPNg25NzaD2+WzRO9
3Aa8vaeaiFPZlcjC2Y4L2Obc7es1ibT7QoYo3eOnUlQdR/Am+Uuj6Hb5l3C9G7Ldeu7ozMPirw0B
ULjto5PDoSB2JuN/fWC38a5xkLivPmDPlsxjrf6bhKlbp7loGUbL1yr4R3CNHQulBd8zrSP65UcU
wI/5H/nQM07Q5Y38qLI6yB2WpxRPtcXsfh4GAFCcaPsWI5t9lKM7p47iyHmhkmTxE+Ncpm7bWu45
dIfnI5XrEkDQG2p0Se+hRf/rzD9Zi8/dPtWHSaUN9T9i8p1ZTiZdfS4EjULXGrFbajKByKemhTUc
GhCKh1VxGPhUeBv1iSbhWWbXSe8b0SOmr0qZe1NDIQ3deZM6Cb22Yy4ywVhqAtHU4CyJdV4lHy5Q
4PNZJwwpGfaeZ9SJUTgjzIAtmELBAj7MMavFig49Z5kiDAVGPYh2rSEvtOAUrbnvlI7gTpJ+7cWG
q7Hg66sHwf4XTL7nEIheur1w+CyOIKtTIN35pSkGgR4Xnlvy/LghADFCXfm6vHGQC95CiW7VBZ3q
/sCDkutwtXD5d10OUJLfGJR15t5gCt1D0SySppA0F53ChnYj14maH7uTcvjoBPpXaYn7AJN0ytQQ
fKxH1fJi9Raxb8FgzIsWVD7v1oqwUGLa8uJSFeCPBZ/p6j8nObxyauOY5g31nU+LRzxyYzIIQPbr
WFoFPao7NLNjWdVgg7uWjVVlPUxd0IsY1A0n+b3yjZWTq68qJ8NFNQ7uj1VKozELUK5ltp+cAVXQ
MUuGIZyFopk4b24NnZ9pEUzLW7fP5HULQBLClN5bH2Mmkqv+Kh/krm8optlKy4HpLbFsqTdIROAV
+M5L1LBG1yrzirJkYJFNUOaVZRH2Qt0Fsu09p0DIfR9TtU2XNX9hcNtyWrM7cNAqI83+hJPLW6qE
mHVGJZdnb+QTQClqZEWS71pCVP9wPlA0jSl/4+fGHx/2zAOaH+CebG1RS9tyarNaRCNgXa95P83G
YNghaQbhwNerN69l67x6WUDJMKjVmXZYdM3HZSLqYqo05Y2VDZmn+yB6P+NOkOIc711CgVVOXVZD
hysLHElfqOjIcnykyGBIVWyihd/V1fRlE9zHrHvuQuRGJGnbUa2GThyFvqBVyW+O5+wCgizf1grw
+5zzsk8tLWaCXJGVR92Vl/Q2peEUR9msIO42+krmr/eIzXYhmsZMkbduCDqTKKSxpx7hKzsVYUaD
QYUmPXT4NCbdUhPb2jgtET0BjRetWjU5+GWaKxsVJxyvx2GT92JRm1NCVTYjUF/+92X4Ev67hLvN
9Fr+iVKN4Pe+UZlqcczsnVaTvP1yTT3I/LsjDavwFO3ZKwqv/4ckJqLJDnNldwaqPTzQE5ehcasH
jc8QPp4qQpsXmFOLTaB58D9Kx+02vuRX219s/bCxXSV8UAsyWTtn5JKBShfq9JVV5bhI9qTkii/y
sxcCvGPe6TYD9FlO5YZNQLy02wESNk0zBQGruvEMxfN+n29Q+7KnmOPvXTKV3cH6zdLVtiQh2R01
wyxch27D5iLmdIv7PoQaNJkkvMNI5B2XFBbspFoQBWwPwQiU2OzLJY3AaO7YjETvUIbpGpBPAWjG
ShqhMuSC4/GOEb+TKVlJxjpi9yQGjTo/ghYUHUHd2D352xz3ztMb+OaOqVdpHZyrBIK0Vg2jPFpE
JSCVPeK5YmaqOxAtdWjvlWajZSh7wrOncxKs1rwvDPUBw5qBA66zkEcsQL6ZYlj7hEcoXfFj9WFR
5Dy8cFWk6vzR91VVz9olbIrAQcTwVvIb+/EL4OYcM21+7rexvvHzarmt9FuXXhaztCGk00k5qk8f
qgUl9zVJVFqqtUymwA8M/JtU4CHbFQotVY2NhGkLAXiZ3xtzOO9nmYYYdlFbZtCOs/PzUubwO8Ip
3NTkCugLbGmf40HQ0Z+N6nMhtsGUVMqwcfMX0J87kJWlfPAm2gIyCrQiM8jH+5O9aygkVNXe3qMb
Rhc1ErmEra1C+adR53Ta1iV65xE+I88ZfaGGhX8nSxco+ZWAo6lP+HAvwZBuzTmJMWHw3I3cNT9i
hy+Grh2K7/jfO7TMmb0lCw1ht10BEKy9+kWh3TYi4rIROGrAHsiidiPgGhTg6vZGlCj6cel1WlbD
mD44bX6aZg9wT/IsbmQ42mGf5vQYhausHrL7rQUE5wBweGltFaYlcWER3dNhboVD440Ft3Udpr0u
ZgxHJESmVCCacfJhzvTtr4p4qvds/pkAsGiP9vogt2uh7gKlvzmjZaU9S2qPTWsx6iYw65cypjVX
HS340Mc7PyHBwl+pOk92MIOP4dxusSCskr4Arl8lPqAP9AhJgSaAoHmfNXXwCsL4BDauChPmJeP0
x22LIEefIByPrLgp6Bn/vIHYCxbKAZ4n56gGcxXBANtBV0Y67XuEy9VWQipBiTw1dscoCRXpUj1R
eGx/V11jtWUET5ZlNWmt5axFV8bBsHa+LcEt9GL7mEWitC+79Tv6xeCYE+EjmfTaWlaUhXkRjujB
FFcp+hvVqCXOADc5A3jMb03wjuwu9hH9WutsceOTpovH3Ee9VHgL6et4aAS7qkvyaMYgNXfv6ZPF
MBWeLiy3kWHLzdNuMFUViVjTeuxhzMKEIw6sbeRfeF3PUulq8PF0vRW8Pes8jQEKYKHROm765E6O
Fnf1sQRt1VGl9rTRwAy62yF0SsmwvSdAi1Sr2qVTn9IZhooCwxu0st1XhYNOd8sUJlVNYDWX51Ty
Q9OAPpgNVj2u/YDsQ+KAyA/aePx7IY/nWWjqeAShOJ/5k+f3Xii7gNHiGPxt6aL0VE989n5Uw5we
0uZ9o5byRtHGeJUQ/b9i6+okwS+iumD+ahbrEYa4UHFe26Tb64Cnl5a1Bfk4Xd1TqQAxpOmk7IBC
U9AHF5rH1tAvL6vuBwdce0qV8LBaCvfWHHsUaozw/zRNI61CwAv0eQ3YMi9777LIdIC42D+jm34c
0Xmh61MdQwYDwYKjm5m5njLYMY8eSk1qi7w71uUQ3nV3HNQbCYCBlMzpF7lyizdHCymvfXFO6VvO
hFaEGo8RSNrtYelYOxokY8obdqlDcHp68GobM/1lV3WQ9YVRacKo3TxVSMjb169mOg+AQ+FpXwQM
ylDM5XJVl+ZPtlJRM4lDiS6NUe4yBi3PB1+iesnjoJDWh7zFdT2fhJH8vYfcQ2nPBJTt17ulsITg
kEyq6SmS1mlTK7t1nFqUo0dKZm19tBTUYanib2zHP+xP2ctpWD/4e0n5XtrGNlyAHvvsCylfGyEV
dO2FQl/Yy5tB4hbOM6/l6nFQeF4PUv1bh6eflog2DSjL2nGvsv2tkfzW5yfGuqsX/CNLP3jQi3/p
4dfe4MTUv1b1VChGUmDQvTAb+6kE4S7pLLItoyZQ1v0uyXTbmSyzlMMuLS0bNbHCsTdJ6ugrDL0Z
/pIdTj6wsIx9mAMTY5BUFnnmI6LqPkWdDoeyU9tWq8y2v+t8/TBJ4+tU1/FYlpAk1aJYKxMgIIwt
JTkf2oPD2W53VVUY7qbhZe9ULCr4xWgEFGqYdxesybSuTZqzadDzCYyJjKQPTPa1lyoJqhYgLVgs
CygIVoGROVAMSOSNDZMR3JN0NHf16vhV4yFwGrf/6g/QDNxUXXnC+JiRojvRiOMrq6rTb9r4zDCr
j4Vs46G0SWsTxxr5HiES6/jGjh5ybTPUsKDpZ6Jp9aR172pWxJ1f9YyHEglLawlpF3v9NG9te+nx
mygBKXRnY9gmZAkiD1EUuVg5xmdWft/B08q2++V/C/uKMY0S6cFUiwfB5ibP/9TYS2kje0nZtZLH
CzUUromroTD+euEA173uUhArtmrbjkXiK8A5gKVRvOuy35G0SHgyCZHGaDa317J7zsOHaONXnz9T
4Ly6C1BSA8BR2bC0gaDTi/fmG9prTuAZHNQ5vXP93DSoxNhxN3p4mCAXbfjtlnAzqNShlENT/aKd
Gxy0Xk4panI188qEAn9a9LD2VeTsEAPsETdY0Fa55Inoye8K4+ExNjUflMiuy/lIda9A14y5pMmb
xz9rAyR+Y+lQfbYQlzCWQxjVTo0YnpSAWlp3XcTRzClG0Fk03OUfKFVkkaBHLiBOXUW6SaUyMXsc
WB7wbozYm5N64Vh3JIo0A89sFDaEvyA3v7CPAwulQzeF0laWGi6qDxY4Mt5HVXxin+ji3tNnxzH9
vwTqOvFjd0pT2F7I/Xp3IlYEUQz3YT1qnKcht58AsDeTIliBH/JGMFOMwVZeXXb1JeMsjO8Ob0Z4
rJvfxyE9UVEJwMVrNK5UqAselDbr8H3HF0K5icQtSDrm9a2ymxBCv0vWOVdercUMI7MNtd9YIWhV
LKyKIfoKcYIjwNSJu/SWSoccbTUeQ7/dmRqCXhTmKWZyQdG2gjqkHcJF/5hvLWjndV6DFN4DUrM7
2pZLSAn94klwbt+fGt5ZAuYNncAX6jy5rNSH68flI/os+jiORxeesbgIezXKNDTGjHXSc7+cOMf6
lvzMoGM3vBwUjNqIJ1gs6rmb9HnC6tHZwDAfeSJAIcq2viucmpd4mv9cSDnYSxsY6XsRiVrAyLRN
fYa533/KKVJ1f1ejQWOG2Ik6aKR8G+RKpetprQLW5i0XvgF+NEW3pv3KORPv/n0OjrR8xm6AU6Ho
a9MABqwVsXTfQsh998Wx9sYDhTjq9MxBu/diJquVf9AhePFTYjw2/O+UnBvlcHQPU/8Xsf4rW/3d
27uF6oDwOnZMhCJ2rwB9awViLTeRq/OmAW4IDLnZ19u3r0mUvt/xCm8asoYouMPPh4lV5z8X5qC1
5BjOkL7gXPQsB5EEZoifTnh8nmJaRITekhjp9yWvNTSQiH5aVVxiF+MAiKIMJg82AkC9U8LzBv68
4WRbGTHKcxh3dTp1eWSUBvRwVCWMlWIY5kglM5Z3TYW7N2TjRFWz9dmbjhonMnt9XCGMHsc8euxT
GVa6yVkn4bB5aQa+cQqNxdDVYaNJGFJmYo3L/RCrWQDe4gATAZWzxovOOc7l8J3ag7CJ8UlW7Qz/
85NDCLEzgbrreSgTZ1rI1bwkvPLPyeV9ziDOraCJkZNOuPNsrwfMh6MrNncZV0VF79VeJJlsV2AA
yUOr1wrgkCfgK03HmGO/+Jzt7zqmEUGqHG24iSfobkBagvznhDERUZcYHjSPgBJRVgW0E+nO7rWs
87JFJXK81CSzPknsPJZpoDfvdCqlzFYecHnT6X1tmiI6RlosfVzqC81N0iPlVQqbYgO/WCv0iVuV
3zzR6fbUWMhqOG/nAZh4Jp74+/1UJKvbB4RIz+IkP1hiNjcMw8uNxXaG1RRhEKZ1Gmb/xD7tiSne
bsuRZ+NuSzf7OuEekENrZZhRvCcFWztBjK6z/nzkZmB87BKfDXFSctG7RTPOajIUhWWlqTRjST7g
SHmpRZ6fV/ZmjPlu+0lcaiLWlEnXsJo0pYpZ9UBSigxbCNhwek5ILvDkPyS/i0y7dAbOI1ZW61RX
4AEI9OnzulQLLG8JQ73ED02UFZ0M7sZQG96m8R7JpSzFKVV1RBnjXgAk4OVsMR3w04BLA9nouE+u
+4gMhYxBh6AUSj49fwpH7Nqvowt4HaJTYQs3zzCj4s6KyYV+jyIrWJnqWveIMJ1qXpq4P11fXHhy
dCFDcNKy/GLsW5Ag6DZPa+SjzbJB1RxrU5eJcLH2io6vctQsuTwuHBnGZ8EvJHUSD8Ed1TPyHXr2
yXD6nAkc6CcbBLb67BvajYoRwnOPeAZ9jcuSoOvQ7nTz75g24tZUW3P5UsgO6t6rCJ5J5TIzjTSP
sYmPGstD76/T1DOwTBxzHf/kCNe1eNiEf4u8BHerWAJi+oUfbljSTaC4zCxnca1ehBiVsA2pdnuZ
vFtcrTxwrdDiqZribtm5N+8T95YsEs1zr8XKba92mD0/dapcqcodcjmy94UDeUv5vqIwV+EmsGRR
xmzPU6FXCIm/EdKABX34hY7h2sgEDeL+Htp7jHuPxfehDLCnCucnnFcg9ZB+R+jHhWLm75mvcC9c
c+VSxkWt7U1JraVJQUPEMxg9U9LjMgYOyzDYM6BS3CxdB7JDHzM2GkhalRHNCRJ8eUjyJ7y3MBiF
WofleVFLvQ/zHVQB8yNvUJHLNR1YS/v3RtANcQUpi6t0aqpciyL2RzP4hcG9yMr+JaSPmNRloMZi
lNXf4xgjRwB8d41/0B/ooZv39bwmXgV9jmRfgp0tS+qRqEhA7OHYVOci5YPZ4psqF7Sm6CbT1ooG
xjI5LXOW0e8ZkqOmJdp9zB6PKOgzzrVw7TCbrzBN8MBH5lOLFTD/FfjbpqkVTQMrU/KbA7XeNCLJ
6vRbnCSUIUSr6rG71apG3iQ5nBzmqwV9udyoqvG0XpshuBqyHnvMzBe1VTjGe7QEg9JTTVEwE7e1
fRabOhsuV+LsXCa4UnLbpkv6L+JtFTI0rjf6GhtycSaD582LM+pgTdDvLnbLB/u5y2qqkFaE5kw3
eNH5OVVETiMG4gSVJr2tN9eyM9CKIEzvh6pvzD6E3p02DpdhQjxU9T9Jns+XXni2QwmCUqohwBCH
SvmlsGp+6KfgGhBCRLs5/4RgWPAeORDcqVFU/qVuU4kX/YfY59wQDGRYgABcJMFmLJ0g2DHjjxbX
56Mgfg5qGfoapKPPdfSAf9q/CN3xhzM6KpfN9SH91fJeJttYlkLwTJuP8N9ziMahkcqitTOBQ7Ke
1qPpMIi0fDlimNdEWg8UP9ua02aMIChJlJKDb07lVtxpa/hxMCnoKSMKMT+ldGUL33B2QnpnNiOW
1PnFM/xNDy42t9981cypoP+aWjoH69FpKenqGRh2GigD1IrrmbgkLPj8BT8NAvE974MUNcylHzYv
CweHZdzEs8LRjsLIC0FEj/HFfeBMKrZK4do7tBKUtbuCeoq62RWclX5D2/TuVqNQ5fuAD+t8qyY3
09C/FJUfEpnhnXMDivgMQx2n2/0xPXZ0SQT8TRtLk7syuQ4H+LvQv+95TiMLPePJpblC4gmcsbOS
MF+JDlgYImA+svBVRsMfXFknOQXbAENLE/AA2ftJ8CkWSeRWF6eOJaUyy4kZUAJNzl4KsnY6Dbka
QCh13/s2U4lQisQjCJLAtkZEbauaZQ4zK5WM9FdUXqu7AIOkEAmeWIKpky8SHQ+h0uHSK1sUOf5o
5eIjU4W6RcZ2s9ermyfvlTOANJ1IbSkD0pRMkqFelTcRwz5hnLhoJOgHmrBbukgYB4G6i7t7mqau
c6omsz5VSxFErzZ0TmME46XcN+kxvGC+tijLSR4jKcyNf5e81wQeA2CGCyZDJUpSxnIBg9Q7glZI
zmXGiqbxSoDOT6BqkPXrD/RcoEyd/Rl3+eZwVXCscgkTSLP6iU1Ei0ekgd0A8jr7jqbe8az/ZGKX
bAul317R4Tu/90NgsMj4o//9z78bX8TDYcBjGrSCi1NU/6q4EVdbe5SN/tshQaQfkml/jy3/lEOt
x+UtlDzQWqG7BoTbXxLbqwARH5Jf1Q+LMhDDO6bHFqWPF4TWNKs/5Bt/rND4e0KiC/XUeI4jPqgS
QOdV7ueOb54mtlMNfL1NpP6H5misM02aGXzLyte2INCbYKBGdk5JSFtmNdOOwIhRXzAwQciXd644
5Wo9MdgCIJfJVDQs75X19uytzFRbktzXhbL/o1v4KZuVn1Qpg+A/dAeuqNYEc3mItKilUJj3iYX5
3Px3IBfHS1TpuueMD4lf0Qxixv0fVK/mJb8oNXBrfEmEPMFVdgUllfLfEWCvXIDB8DlOaWDcNAdv
2nhoVEIITqKT1OPS9NZR57iO+mMiNsCPE3pFRewdjc7GPnr97Qv4LTBvyqaLV85fFs9GmWOVTaMW
WzXtZv7KvBF04nkJ2HHUIkNZ/sQh7z7F2jQ9EQBCrXx8MK+QdIwiG/nVlm2i/ylwA7wfChg3YDyJ
eWIgDS8R+fdUR+03k6ayBL+Dq2VJ8hf2TA+Xdv0e2Zj+/6YVxsdU2eiRMu2Nr+WQTzO5Uazs4nXv
3iOaNJM77vE1AA/MfDeE8E9ViUtMXRIwqpS5ZvcCW9ugi+3V9xFp2Q4qqSwPKe6KZeZfbK21cv7m
hL5bQpOkgbi7jMCCDvgFGHo9T6jvZlp+pOI0AwSQOopvrz2zPD7+iZWPz+ksrDydCB5c7OFJpEln
472V7BRcuyH3yZBp1yVfAR2gpbHZuHmDtwPk0mdA0pFhXwQgoXDjZyHoybMfi86KPNtywdpDslK7
rCJREChQOC27aKYqLVhj9D3RSCQsu/1oYziscJGa2P3ap2hLrTBdXvausj6jajYOv16XxksHwiEU
+1zkh/Z6qeebDKYCALguWYC2B3rqLdq6gA+jk8WYCUjEKnqiwcFv8ZNmuEte0gkqq1G9y5RRLgtr
RFOn8tQb/kUYRXgTEOyJW2IE+wuOgP4vBiRbZT+OmjLfaDdmae9l8eKX+H+v8KdTkroQPb3VKtqv
bbWyc+gWI2XfIc+Yvlva5GwytUSCEHC/bxHW1unZLxsT4wSxmBL53m88BGxcukfUIBr8W2PfLnnV
6NMX3i50LpPBCmKivyfLFPPV9GJOYe2ei3rzhVk1jpDZepU0lUGvAOlmL3T4E1vdBPZ34ySMIRa6
l/N7FpFolEV45QoPHOuO8B1JPF7cjotFdLLwyDTZUO3y25a5yuyu79nkIzuxHZvbYN81r4Lhm86g
0nGd9iKJGpj6Ha4OlZPMw/3jmINZCFLOTaYUohEHwCvnfP7XH7CbbRuTW9mNri9rhJtmJHuIzD92
hw/owhx97zTQ4NpY3qx0Jt0jSDhh9a5Vty/t+wpHd4HOdo/A25QSHiQ0S7mnqv40uJa1u+eSWMeR
22P3i9QCQmvO4nEppXKX2UfZaQ9rLPz/Kqg/5ZYDeF3yijSB5LBQ3oIGEeKWKGqMTouxn6LDUEJW
KHiKerBaGQmFqOJaaJeCdnneAjvi50cX6hobjFLVueCXAuRDqqqygmqGm1Hn9/miMGszJZW/53z3
FZX9Fnj+3I7QYrR3wXfX794Mxde9dN3aveYayB31m6ddASlRmvxjfJdLDagoEgLOQ9OjY3dAZxPU
VUx5VtWQnfCd32PzgRDz16E5lzQiCRbW1td/oEtT6teDL2aOtx/D76dLoBh8rL7i37ZFfwN4sIJA
g9dgDm4tMhTsT9mmw0utuKM/hW1tLO3Olw4refqHfaidu3XG+bmKsyiMkV2Bw0lN5TU2T1IPsQTv
h+KFN7sDQBoIUe19yJffOiuEkAcCQH6Gf8Q0jCipJq2AcfbgNb4fopyKlqFf1eeBFSYPPgY4SOTT
d4bVCOneV5PUrT8XT0Y2qSxMh2q7PI/SUWBReec2nKKlWgRD0EK8K6ggzJi2hjP2BSngI6fKCGyk
EMtFWKYx/MnFyfA7LRtQvsKzDz3ICBmfBuSBNAPO+aLQKTBmOnXTu0dA4BG62Vuk4NPlB6uZfJ3w
ZF+B607pfuf+TuWUtafoQ96eMDBPZxnzGIiSATjGamXsZkeojMSqUdMoWUJX3YpQnlOTBuqzrMXs
KCiru7Xqd4XO4LRbP32dqtDVzOH+oLMDGgfWz9DO58tQl0mgJj4Tm3QYOKTfJYMcgeoydgUB/aQv
hZ7reiL+0CkGpputER7203UvKAy8RPu7QeylxZtvEflbfyUNbruTAN9gPFBKoyzvgUQpE1Ou6r4j
wuI3jVfO2y7+2Nd2kESrGbBKamHeTqlM3JdzPZxHIorlILKWjGC2OWUKAeWnTpDXoC868sFIqYfz
NDQT7KNjTSOKS6qrmAbBLqJxXCSxRskCm9uH82UYGMfGofy6EeKAO9X3zoRGPgZrDrjpQRND+Vz/
mE+/nIzAAfRYkatVVrpPpvvZ/0Wce4HX4YaHvB0+dluPu8popkdp2YiFwi/+l7dQ2opmfMTHca2d
WY8VDntFEcDbpoiup6HWjw11jWmpIPu5ly+2YuEQLwbkKgv5Xidbgeghn+Xsta1RL+hgDegaopg9
EoPiu5JSFnT0AWf3V2fcS9x/CDIYvxaUlQUoXF2yZmwUgH1Hwipcw71E4yqo1wcL5X0xxebQdtSC
1kFa5N1gmDP8uKeK3UqZc5NBiU3uGbmP1RM2kwq4BfBVwgmB//JE6nIYE4HMGKbq49LpY77sDy5i
Sc1c2u9Pf6LMntFw78EcM+v+NPy9/N8uyFIr1rrfYltrpWd/CHpS1vAox1Oea6cdDLBj0e7y7kBz
jYU9Fhrlbt5G32+myCjAKs7mkIkem8bhp9enOvcpBPTq
`protect end_protected
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prj.srcs/sources_1/ip/sin_taylor_series_ap_ddiv_29_no_dsp_64/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 20 | 94635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
HCSQmAapELPf1sBJFgFNhgvq73K3W3UGtfFvL7obu/9NizRz26mkfd9wNe21bmirivGTwKeZvyMe
zWixxZrSiw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Tk1PatICqGOpQtQ8oJOeHvG+wSfV6MFfzUR+1NxNiA3D1oXGbbc3gTGsYeri9x35CpLHrY3uJIMS
sskF5MZiJ7RqK1c31dmN3ubJJ35zyIvetaYotC1izf5s6ofYhL5l9laNqVTgpIBd3otGkPj7WK42
86gYynjSjGGc+HBZhcI=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cfZeSAapGTxUQEvxn2/r1T9bFdYrx2rPwOioTJgVQ4OPGb3rFvHX8Vp6MPky6sR+Tep2gIB6VvvP
GJ5ngtwI0kzcD8i/Z7LqBs3I0qgI2LxV9deOeTUvqf7Xj+AX3Me28gLMVyg5BeW6O/GYGZS6IF77
zIAQ05cyjTCdzU0eisQ=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hByo2GW7W1vrbUqX0oTwbTccL13floF1xp6jmWwfhWqfIXbs0v8cD3nYTIv0ZYmWoiTKFmNd2sTo
hSJnPp7TVyR1qJV4cGM5eHyJP0Oa0E9FIgOeJbf6amWtoLToYMeyuyPFP2PGgWxiTnTHvCRNxcee
r2qILz+Dre3Cv9w+px2Ly7XdRgYJ3RzxQTc6eb9jPdogRLqbWIApE3aukiI+xrAOOeOWDGbHkIGi
PEbEc9hjcMTJGsiBrr+650bIjmaHov/vU5mT7BxlWt0FfFp2aUWxkbKxh2AZTOD4yzu/CnaGjY+s
amPG0D13N2mmb+HM77btNBJwICYwyT0dib12KQ==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XVZe1Iq1b4q0pJb7G1HiRPHToYeBo0kSF6/+epE/iNiHS4dXLRGITekimnvUz5jWC64VQVuw116b
q9OWkuBBNOouYj7wEAh1ufsn0z3zlkIMYNtGWNIdhLZl1p4j0bK/HvisFljWeFoyO80WNu3avx8g
sKSpXqMlJW2EaFNf4NWfq7c3muHUQgSgG3nk/5vO0zESapsSTn6WmN5PuuhhAVEm+UpYjnn1vaMi
FCcQWMu6hrIFKlyiWWFj7aF9efNcYZ1vxJhIL9jhKm6ritRw5ekFlEM5BpA3Fo6rdQML5P0ZB1qr
YAvM3UTGIvL4FyuNcsavn2EM7H5R9TD3b5jlGQ==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FKZGFNGDGgbVQmf36A3vvlEeMnTnMkVMn0xyNtGAe/C4BYiio0GGVng56CCV/s2VwIm86yFp5jG6
OufL8mHaK4lz/4lq9NjXNCGWuIw3b9dPcaLXw7iwVjULo0X5P00dXSClAogIRSQDMhMifhijdjna
Eb/DWk+oktBkXYiz4Up9+USfCbQs1TybctiLJiIo5ZY7v/TiA8q6C+PcOae1te0q3hmRyJ/Sfsaq
/hJvDUrmS+CocnCEQuXxO1mKRTFHdj/f+yRZWld2jM0s+jXW1EGw+L492pzX7W7U768NObMW4fwA
Uc/SSjGIhOpg9nMGC+XCI+RN5rkAFDfhx6kGMA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
pKjKQ9yxMXDRjXEKg0nt75KpMqHxlcPp1+s85YeqrqVYl5pOJxW3Ga00rDbgkABHmOgn6PchGFbr
eaMVQeoFcCFKZXGvQMCnbXtlMJyzWT1noQFNtrE+AJhueb7CDiGwNxQo71UTANf5zxjyWwEeyvKn
MejF1pqbzRicYPoG/RkgM4kXZpRtOQK6N3awoZDOaFd2JJht2HuHOsn7htPff65dGss/n/I+kEKg
zQywfr2Q0fE/9l8JlKONQyYLC4RLl79gg5ICll0Wh73DJJn8EOydDJM/C3O87B1ufNTtci9cOP3Y
y7/Pvf79xm2dNy+IQ2WJUKNbBFZKAojd9gZXqmIz86Nuz1ekBneOCvIFgDbGMitx1cfC36q2wN8Y
pdnTEZ3qUvOUbeNJXGRoqFH3HOiT3b/FCJTUl8RCibnoldrcJ1jyyOMejk+QnkLRokqzsf8JsDR+
3upEDwZaaoVZT+mx49LVN3SCU2P9JgpqYXWDN9cKn1WO/Ix+dyaHmIm1+8AVRYPawvT/5pH8j+UB
BXRU6dji4Rcqr+7BqtEyhaQohWD6dCxfeByuUqmw+1gZM0utAEvKve9Czd8NvsEdEZZ0nJi1SMOi
gPWEzJoLfVPxox2oE/w+ZlTMxjHeB8mss1yD3Ga/0isCaU1fL5JzbJCUlDyiClzEVw8UJ4JgxBBS
NpujZ6aD8hOUyCO+MSKCmgO8no9ApVkolw/wpWj3gxRGYWr8qo+rnM5OD2XPp9fyS8666McMkoOy
0J6g8PY2htn49jSDLA9FScLHI1/ZN+hEmBWgqzn/tO9ioukUSFkXeClAXe/TCQBFm0NKoOa9GKr6
36BFj6WUW938GpT+YBkO+1PFwb8E/lQXsVpJRN8BpRbhijmZTauxQZbliAp0V2IbgF21M/koso4A
YERKT/z0Iv4ACibGixFE/WRryLG/ydrMP7mnejssE/2PUkZKGgCnFcrXHMI8cfODV1394q2EiRBs
lj44hbCwxNxtbVqGUI0r0WBYD5b6fihc7E+NoqH+8aeHjzoPsV5lZFBAV+eFAv19vIWicWtjxDpQ
cRt8goRM0QdZeVJ57/wtZq8/s4BTTfZbKHBHyr2FXl+siWAjZ1dq7NQc6YFeG3aguuMPFgzPYZML
ZPLhr9v6Eboxt3AGDwEaOyahdfzGLaaKaDoWrcLQL7u0lvNIaYTkNFPyXftDNNkud1Vj4Qd/n3hM
so8IueVC8H5/Mhf36L2pPVudcgDXtKCJOBDRFVclYGeVgo0atY2njyjISbjQz487kLhQVpy5B7fM
t71kDHKY4i1apkwyvJ04qXopedhmKm/2bhMuDGBtC1ZrQGOnMu/58YHNe8epmMASQlFnG1eesLkr
FCPPTn5bvXIrSjvd4SM/wusBtyXjaCHiuwGX2XYsUSIa0qe8n1YRxa2wz7/EPjHu2Fmqu1tXYW7t
LNZJN95KOF1mEF3Rq56vrjBOVt/6kSkmF5FR+tmvBgxBW93SV9LGGGbZXWq03njtwuhVOr4IhDvF
m7LssCudhF34JDN1BmRaJmEosp1kv6FmXmgvX2MEl+iGrMoQcbKp2QgIkAQNfL6PnBw/cdivaUik
WnnYQTcIG0jcuTt4lqU5N3zInOcCXHQzOmUKrHIwK3vxFsfKXn+f3XZ9ea7Ik9yEjngtDk233Vlf
fdcmP5WrSoR1WIO6dVPt4Zm9kCWoml825wTcybg97jAXVS4+NgByCYgvO2TPeL1myE/EoTxZxxuH
aydQ+xb06DPcSDzgvSlirFvkpbgV8kQrVJYIEneO/g9QIfX5b5z97Hl/yWy1k17Ffg+lwJ9pTg4e
zcFWenRSqpRSrAzpxhC3pXwyKp3jouJcbeTKtYxXtfCpjAyW1wRuPdOSPk8PSvmji0kumE1LHYQ+
N5CIkfq1loNJkK+Cj4L5uyHso8tby9qYCswq3bJgDPmnpINxlfn+fH8SPpjU0FRGDjtLXxEArLkN
Q/HU/v9pxs0bOe/9k30fEnvzfeJ5QfLUwEO77+d6mI3K5eSeipUxmBFCrwcD323Xh5zeFtNdOuPO
MGDyK22SoK8HuIpfW4E8EaFvMe7VzAmWS1rTXRqLLNCk65mj/fVYKM4zSHyTEZI7HVvaC50nWk3c
yquE0/jNGIFYhoCtGntCDaoRDijKjiQcCkBDkeM6oKDILduVwKHUVQFfdTlUvSMDAjQpTUNokhDF
sGjI2jl/tcsmpCafxShAB0EtCibNOJxTGB3/y8uXQBPBxN96MUwOE+yrgyQBjw2NxSH2MzUUaBEf
u2TWSA67OTtDtqat3q6Luv1RmcHlU5InEhc3szm5YMYOjUSfuXDHJpFdG01J63I35qnc/aHNbRYu
B0UR/l5lvIzKcNnjwYo8Ph1vwvIKR/9f/tMX4OSiFHBVCZA5o3gnFIHwxKGbaTJ8TZ90eufYLAcc
sv9ko7JTUBNDhzrIOwHKecIDM8iBPzfwGEgFnL7y5QrIquN+ykFYNWZ1NHwbn+rNLCcXJypf645V
5y7Gihp037SGrx594zxycilov4qEGiDBrQifMcUsmQFYBRYz//eHif3IKHwqpZU59i5thYo/1PBK
ZcHrIocdywqMHuy/y11v0tDdw1+usAfs9bfG+mEDspRGEx6HXhbDnKKsj1VuzSsFDfyLyJpCoU7e
e61ryJqAQv4HuAPGEtFNPjSW8vVywFrM173l+HemYRkI7WTpA6nyCMjK1ul0LPtwWtVVhRK4wSI+
2d0tVxfSzhJooPnnB0Fh9tlsJjj8sSd6JnFb52+8BAiw+a+PTEPN0wdtkzruvZiqhBk1CAMdBuUj
Lvg/6qdk5okrN7F+XBqUB4eNhIJ/22Hhpot8BeVfyZ883SC9DOSp9HHSu0YqOx4638WM96eGaViI
+AcatS3CyIphx/TXbgtSXYIB+ZxRe3kM3DwHF57qQ7EmwyyCghBfTrqnJ5kb3d8kIdjbcr2aXQTm
Gw+u8ex0IG9Cp4A9jFcAP52iG+bjFWoTuSN+HNZEAqTFDrdf8uv+bZV1EYwb/v9gAmzuCXeDKB1r
58PIts6+9/LwJ4+B1Yosfw45Vr8teU4B+3G185KhWCBMbhG4ybmTMNucODo/yzzt6amgKfnypQnB
GY4H2JftVRmPVsRNYM4msSyP1DHazEubuVfVwLwYvNOTLHybCuOw9VEnupuHOP9cSgg7IVDcmb0q
xW4IsCeYDyzEDFFqkYyRGAPdQtRJtVJWRZfA3/Z/R+D34wLbxRFnBzDV2MUrKgaA+M1n9oQsiZzD
Phqh9Mco617HFF0K4WH9N44mjzuaPxMNPT4dnKLne4ByuR+dB/MIxXOGmyQDSwGAcC/oZThXJk76
47dWcKcdsh4XUl6jGQc2KonTvckShrR2PhLH/H/riSN4py1+sL/+v+Zqu1RqAzbUYxfX3nsMXIgT
mWMrqjLg/y2LUvkGBHCZa9G7t0tBvJjKuHWi8Yzx8dNigEooSpzHEskKUhwUmAkPhAilf7ihZ/lZ
jCOSVuboa7AVigtNr857e2mBQ/No+Jb8GdN29ueSGv7nOOyIqgNNmOedpdL0BsZqtGmSH/6OCmjZ
kae4Ar/FoHyIauu0d5sRJEXuSE7UTCX8cAbH3P89kWknc7xpI/ZIdcVSiW8TODqBmuA+4WJuJsA2
KYJRqvGI358hhKqZ2/siqU6mu+7t/yikS78+SD/4CbDT3eakNsURhMg249yWl/OPiaG4T3wOpLQ0
CYDWUpSYET0yfBVTH491raK5MED9KceuQHNZuHbb6FlNpenTYzMT4Ms7ZbkMqNtLyVNicCO7xDe/
X1klZx96BcAlU+eyvDtZ1doCbIszVWJWXXL1BT4AbsikNMq3PNiuaIFVZvXgNBaHSPaOsUEXXJhF
wjBSmGczETL5GaaQ+5w0+RxEI+sOFhkLI8Ve/AYznbvq5RCDlMTlt+ZQG4mMe4S4mTMXPWXw1X1d
sHPl983C2/TAC9gY7gip1da3Gno3lElnslxNl+uCCuq6aiKywbs+wVOkls0BtNEAyW/4b3uPmObf
swh0fjQZt/cOuV2J2hcIEf722au/qvs/6PJlobPMOA3LjPTZKfohBTK5HouG/6Taici+bGIzV2Yx
aorWAn+JCEPWIrLvrK/GJaf+hxA8IExZP6iazNzATlltFr3ArztELM5vlJos0iewpu9YeDBSAG7S
bTAgBRmWvXe6XV60VzbgtLwZKzMgS4gl5NgZMvklN5WBhRcU/Z6MVborEXOrw/nc0YtHN/n9/lH1
9Q57iP7FvqFSC9LJDA8HhvR3KPQfi2vEvgjcuKS2xliareEi1I2tqDgeTVR3ihqt8IrSl+6MpT3z
kc28FcEQETkACVNmTySB/Bekr9xqrpdq3De+csUUyqu6DBPSy4Qm0CWSeWCE/WOXuHXro1wwdSFC
O8ntXyfiG3lK+PAi442OCVV1edO6jwaEEue+7uQKzX0GaV76rSb7rH18iQe00ZmbdvrYOddz3Ezs
ByzWFYy3COG4DnTQ/lrQn6QE4aUfCSYf45BGrBOE5wF6rnN+4UahtaiXcup3NGcdh1hfL22X2sfx
0R3MSFjZH5xrZ7VYDwGhOYhg+ymsPEsyMCCGhc4ZW6Z5Eg++wM9SR6ZgwJ0N6oggVj9mEC3sop94
Iuh6Xqnno7djtbE8SB0JPZgaZVRdYpr3sDqUt3zGeOwdPgyxBfAAlhzy95XcZPVNC1M5du8b/OSX
BDChn2ZIOeCeneQmSjM1XQv96oDAuVqaEqxzgeZVMWcXiEkaWzCC++U2KpqsNNu1E4NO2u2TX1Oi
mZLMameX/Si0x924QdyxSeClJAGv3FFkxQ0IyCWT978WDgRfLBzLyq2tlhUZb2paDOtre+vskV41
YQns2ui9Bz/3VeoyHr51gwDMILImaroTvgEc19QD2jYBQrzSE6SycoEyKVrYxep5BD2mLhTpYnhf
y+c8Qhw1rc6BL2awNaQ5CZ8I+k6I4j+dK31vHOI79WhEYrE4ShIvW0anOUJSItVUUPH9TCU9nf2j
FNnVDNGcL975XSaWgGuw1CXw/xbqHyL4NjG2UaWqMVBXbn30pJhUP5FrkY6iN5iLK7cVRSyAI+JV
H5KSt4zjy5OZTb26uIohuAldgzIsFInXdLM7wVbqp/3vVVznVE895fDxkonI35r0SJjIiWLry9ie
ZMXZGDb6H8WjAb44+anN80Yd3bbnUTTYRIx+t2Mfo0wOcz63xVnOSU7jBHe4boTEtx2ADGrYw+3W
dxyb1FYtSLlUPsn/7zTUyGeI4NqYITaURZ0raQdRA6pOnW788aaIonbUflGtKEWWyPwBUlakirzY
H2GFQqup+A1ipkJNyXdrcWpyc5NQ+Sc9Y5rn9cMl43Y0nC6rVpdkv/9Lxgn468ZPUmeNWit1AuNz
K/nczm+sxNc2qe2WRihNnOOhmjL36LF+lZ4rS6iIC6zlT7ZddeXGzEivDMZ2uv8EDuWFA4DviNst
zvrN6ZtLvtxXz5DNDwDZ20teoxW+vypjctVN+ir1i1jxKX+wqma5OL7SSNfHpw4x9FLx0WpWIaZD
zpF0VdiSMDvn2l279G0w7N0zDdsV7bIUgYJdSklLhrjMRFPjSxmwuQ6xXlc2C08cf/eyjy3j2rSt
YqL8Twf/wGavXhPHTedowweI8B4Pu9XU44ZXvDkDptMMGRJ7nhjMlbYB0n5PDSTLqFJgOr9UiZAM
2yLQcqJyKUkYAK4BWM6E/X2VGmJgFsbjjGrD+gOSWt2iaqiM8pd1WuXyaAuh4Y/mBifY1xiOQBv7
b5xDyJJi9+1yXcwdeXAywWtPnqJ+j2gvkU1t9X/0VABgQdbLvrjqLcFPKIPlPZRLJrFb7X4/ZR3m
XqNyD6EYgt113MZuKcm1p5dmIOSKaAXVXDIvrdZ67/z27fNkpoD7wQ1O/B3uY4u7tquSKLkeFctJ
hBzOyPd+7ljwuKs1dWTISeRKjXQMLdRBf6KIxmX/SWgZEliGJxQnUgq5WWy/oQ15XJGGn/QchknJ
3vtG7wH8PmeC9msr2cMptR8bLjv4HCZz6EuMZDURq765rO32By21iDrJIA4LwlbHajqeZXpH28A0
ZyVVBbMKH5UMr8ZqLbnxuzmTe7NznG/EYJTPUrj9A+D1+SjVswOP81i/EgdHQ9BJJ1lLo5LnX4Aw
c1u6f6hFKTC7+Wq9ghB46KLxAkPUj+ow3VyKfYt83hllRh3bO18Xo2EJ6ySeYaWUl1GfOR02bJyb
QCYQ/EURwoT2TmOuqFwpxMn2hn1cSK77zQ6YfO4bTcF6km69Fj3pLdSxZK+AOkjTfBR0pHDBhdfJ
MFrbTWcxrlFdnA+0QuGiVMWwOBGKyzKp3VABtvir36h/QWyS2ivKwxVKvIUqroNqNK+Gvt9UISuE
Sfy5iOxhdIW14HlfBjYMijbmW0eNk4d56I64GF9vXtrIQR+E6ddyz8OVj8XtneZtRq7m6SYpuRhG
YpCjRPs5GYhctrCpG60lzTjYZzxnz2GZBM2Tf8PDzjewlHVgH5z1z66H0br05Gno4J2USreOTrfA
a7zvtJ25k4P5pDLYPl6ilxizQkArCquFwEfP2YueGtcPXJ1UvvM8W0hLrllXKRGa2IUNvi10845y
hXk0ZMOWwHpDIECmlIyxD8S+MTIW/MEMsttLv6+drImm5oR9w7dhFb6UYzfiTm6knBeejmxw3YJO
q4h901lLu5/JHqbXmsXve9vuJRtKmTK54J53hfTjujHwKxlD3dj2u7qWM/CSFJscouER3JgaCuGo
VeS1t+D1MNrfIPZbBtrU6nASdP1wVg9RBRqQQhmCUZqlW0SGmoMY663c4jcnDLZEVAodIJlIvF2x
y0VB7thcpUrPO2k6gOYLkJbDKIin0LhCLtF/ar3OrpUM4zgnAkEZQNUXiM9bsbpuOppgZ9vO0ilV
Ear+W6zD719XAs72QVUTlPJBacMKwWcY/31EVhFo2eji1mobF0FOHPN1vzi1qum/xHb/ujquWwcb
crzoSnfKN+4FFItEKviCZLUiTZelCQd6s5WaWM9l/vuL+n2IbP1pao5OLySYIXxu+lX/H2FEb9o2
Dg2scP8hT6cvJ6ZjR4C6GyhrmGV8N9KwOzP2bdgAv5ukLfkJCqI+cQ8t1vZHfAFk3viibW7hd9Gp
WScrGH7UUJuiLLwHnYy2jlBE6QTnpEmItoxb2aVmM1pRAMYqoi1oxcwJawNFcEBuA17jpT/bLJ65
Ms8SKd7ktaokXv9co+Ln1wy9HI/j6/AJk5+gzGe1tYMB5yECj5UjDS/PB8BH15Qff2vpZOCBXeg3
94QbC5NNPiZWDoK1jE35Or7+L+w/ekN2W1aBEHpBM74eDuOISOtOpZkD0XJy+ZV0wLHHLW2Bbn63
6B0g+hgSGtTU6An6xJrGLQaQI5Ba9HxG6HmnnydmSCa+4jJUBiRLjtBJ7YjVND/8Js6giUmZBO59
E+hFbFG0OEDXpmoX/3N7rtt656FUNe3GjnSAZDJzeBQDxKBzqrXtUIj/llSpxuKBKJolutTrQUxf
bTq4wPIrXEU1EVuRydYfKJ5UIRUj+6UUh1d5dqMqXyKEoNzSDqhGjee37Rjlgls65IvvkHyZFxLI
qNF9Gm5jFJy/+0xZOqSnigMTTRzxmGPBGx19gGmow86+SffDalVjerXK6/IFIiixQrMEFgRYB3ZX
RIV4JeerH2B0NBynTExt1OAIMIHwoEVnBs93JCfaas9/cRmSpPXrBaCmIL6gGj1PypVUOv+duz+g
4fVOxAesOsBj9xCZkkSfEfMgLAfZkNZpQSgWfxaYx+S6niYLTpbHzq1X3fyq/kMN32kXgpNcr73Z
Jb4PREyoUGnwdw+MUCEH1yfljEQIELknKqDneRttTC7chrEX4/QPj8cS5WkvJ8mLtrwQwytWEYnD
xnQv02TOO9kY0dTWo38K1WS7iyyFZEN/s4miNIzbdIEq8Yi+FmZJmf0zVRQeDkfMctsGUwVJtTUR
67j6LVs1eMfQjCvNatXfK0RCwBhHOea0n33ytYBAd65xuDzWdxgJKUxn8bzvY+xhAbWEh2BTUKs5
Y9PZYxWrryBmnSqFvlbCyGqOtQmecW7O4wkoK/iZnQZv3dOBud9I/+H+fcXBIfG5QD1MXX4J3TNA
3V90JsgSp9inrYIKarqfS38rEufJledPUnhWSzN93tM+eUO83/2g+6K92XHxMzedfLeISmab6lXt
PqtuPUDx2u2GSvNlRiTJbK59We02PzHZdmNVM5q/OG+UkGHSfjmG/kMqyW3I2VxDsr2V+6952viB
38xVRec7lry87xFv6hnIVC3sREFbx39/ybKugHNmrbD40hszT6k09AF+kSM7EkHWbdaNGZPOZ3tr
N1hGxHVOYrim4NHZ+1gzIMWS5Cst1biaQOpsDqgiJCsEW/XD8dsbZivxqi4k7ZQ5a7/xMAu6cVZC
SSmeSu6vBqhiZub4EWVoW4zDe5ldr6GjNs8HrEhMq7r0Ktg0rnvVAWf+ZjNw2yeWhJW9NrFBr0PN
xOJlI34+g7OB2zghYDCgKvRS1bnrSTepU7qLnIn8dfY7zYsntosk3awWsetPvi7/p93on02qxNA9
aHKEwEu8wOT3YO4kFxNM/lTO522jAFYFQfwBzt+jStHAue8y14Wzja7RKenuNZ4xBJQk/j10f4rC
Tfu7y2PaoejtlqhlCny2xLVf/+y9wpKn8ZdRoh8J+HbIHZxHMqRo92DTT1di1vJVvMWm9AaJ03n5
A2COM3632lt4VLPoptnXeLR89zmmHja7Sc9MGl7t1BlMqExv22de0WBdog3UaIEPI04iDzpSh2XO
fBOGn7AHQ4v+VB8QXo3jCjChp1qv0g88OGgzGXYmaudgrFGw5Z+TBtF/pwE0LVOwe9qdtAG0sNUJ
5raItYiqThQLm6p0A4Ds2bm8Y25A94QJuFzmL0+YiGzcOkpaxfnrsonFFLM6KYfSNU6nmynzlMA5
jDmXbor5vFMBznR7J3aVHMNXfizNbMB4BUYv0TMIhBNVLo4u6vCKs2midF+VzaJxDPHpWQ/1rTCa
Se/yVo+j/Z0dX11yiI19AbbyJ0RTgfmW/pU3G4VNkJKEgZ+9Z8T3fvJXicytr9qmBanrL5OWJ8Av
OUYzqqRS2wrAr0BMgSdpguPiuoC6wMD1U6AOG11apQjLZioI0PZdVTRUa/qraayI9c/WJ+c0kaNc
Dni42ZQ9A5+1jhjFITSgp6SNxASP6JyHs/JxZqoI5PU0bC3ydEAZ+82ehqRpaUX+llTTnWCulJRo
gVytN4LoxdhPbSXHtF1k6fuXT/JXHnoC1usZ/XU5faTvS9XErGHJA/ul9ybhyjs0S1jPhw5rSGQi
FG6Q6LeWmcTZkt91K8rAOILE0tXU7GljzmtR8rsr6uEF1gA1exiHSP4XtheqPDyYfs8OnzvyzrvS
5C/0Wc2tvGblUTwJPhhVTFbG7CqTmZkJSMFX+dFTL53QRKCPhlVhpr81hTQ80uWF+yEkRmko7UX1
Xt0gZ9f4Dxu2CX036bIC/7u1iM1JOXP5goKB7dVf51//6r/42i473RPkVzHSI1ED1PUHGdoDMBhF
sqbHK9ao//guFu6blKPyT4QM8J7L9C2OlQh4nJf6W7CCUXjvfcmX1uLKRTVND60eV8gpS/C/0lWB
gyaOk6ROSYC6ftyvar3ze45tc217EUpliVuJ5TSGSPtkAU0TXNOXqvI5rohmYlwo5zwK8aQn52mh
kJdWsKrFdCU5v830SnNH0R9kROVgJ0XQF6cJNvwcqgaQwZ/BQBTviTmI2mUbPSq4e7RSB+b7LnnH
0Do7OSir5dMPvJU2rjrPWT5xttMEkf6VMC4jr46zIpWnuRvbKbDMGSDVebTnoBQMYIn/jTBLbF46
Bm+icW7jXjJEMtkpgfNxoLhY5s9G9uxz4fe1Tt5jOOQ0SRm7w0rcu41xntt/BWuOQJjPtdRNcT/X
XkpDRW+40FVT/psAIiiLck6v9SJ3PRSY4QYQWPmeNwBGU66l7AKOK7tueKoydR/l/N8kNNpClEBh
YGkMMAcLXHSDrjq9g2c0pTpXdATyDXFb26suMp0X3Pg2w8WP4Q4q/38xyhr+elgXTYDiwHVSDcxt
hgDFUnyVDNUiMZmg/MdDL1V/3mCCqFvXEMvQUhwgDrRr+s6JJdINK4fgI53SdanJkvUVDatw9rHI
ecq4g+HGtXul/kiLQQ8LpxikLJluRQCJhSfEUP0nisV2yUQBmVoyfgNJVh0gIoa3/79r10au51Ke
lRSobovBmufrxgNUV4GWImk8N3NFhqDNAWdk6vuWjcm4aH2GSaLgqP13XUY2L2u+TFs7rvjr5WNf
exoBqC20G98oiPbwy1zqMJK1JPZlOyP2CT02lHJ3VEiA/JXqVnLLFM6EN4Eluj4wG6+/K7PrGuH+
u0Af5Atg9PEJsG/PhCb5+O6C91OfoltLX32YpPWya3JCOw4bQHxpiV//18pw3Vor5ibvSlWH+TC6
ztKU0Gc+LnYvOCba8zUwcXTKZZWnUP9lJPMrj6yRocK+PWm8L6vABcNNG0x3I4ePWXItUL0zmHxK
27z9egBJbI7okuKCi1w7UD5OoOspHMvaa43IiB3OEijZIdVteYRh/g/sa0HoHt8lHmT9LIGJ4QW9
//bcnX9cwaTm9CAg1NyJ0yTSHc+2hwu1HSKYeHNOtOEVm8z7hO2zo+7+TB7Ry/5FSLUFvbjZ00OD
zk4PffQ5/2/1bF/0QpFvfU3iprjHbx+FavxtOE6OC8Ev/hcPbbmfeCbnTBhzuyoLaXqBagg62rpL
J/hLH1pBURF3pbLgHrJ6Q/gwLvNnkicpmb766VlodFUdtaEabb9BKwfNtXBVm7sJOHRcn5oQUpMT
I8ojVT055kNQ01QFJqCC/0Fbm4rSWXA1mWQD3BAybFAG3wabCISuHVwI2onm91ukkVB9O8GSAmnf
bar5hfh7eAeW174nbCsryEXeFnBqHEMZNkHN0ze6TX2QCrrEk0hub8RrzVIWqvKEAfYVI9XrXU5L
8joXPARMEIDMmT8uxIgOVAwamMafAojUzOHruyBdjcypO6I3LMedNipEXEreQvaaK1pXpoGCJy52
6T9dGHEQpkGu0m5c481WKOtP2OgkDBJLqk0hhPnpojF7q7lUXp9OPwPk6ztISO+rLOmQ77gWIH72
Fc6CMMX7TftvhMN0nFDBAZpe/r5FWpv8D05iPxQg7P/gE8/u0DcKmsy6eD/1r4fg7QtDh0FuTDCG
nx9Q3SXHlBOS0if5dmaJUzdTWoQd7X3EJSOVhN0dU+WYT5iZ+kCRmfQOQbuPj62m6lcjdqxvS4ob
QahsfkP1bwb1Z4lMqDs7yMXva01N9xV5y85Zvc+A8LwACVQ9eoZ79qVqeWJcIzHCXKs+2p/+kFNg
xLAwUAMVFDz9oKTG1xa65dxL3N/33D8+spXCGaZ8mKCZvQ0tPTr7f0mQqWREM1t/HGPU4bZ3o6hn
4e2Y1ImKjk4gARTbLGGeGxTgNm0NEcfXPj4wyRptdYVNEf/gyHdHSquGf2LWyyF/D3bQIbIB7kCo
xJ3mXLDdbNcD78Kwq08y5ur/JyxHaLvnr+ysrZG5DCro87viFW8g5e8OUKl4xmaDzNeMS0PzWTL9
N8ODVCtUpnkNd+qrkQx+shLtxfRRFvFK+nTAbO80Li66KDS4PVeg9Endo89kvwv1S+xlEO1W+4cT
pwHR5QaJJqiTWjGQz9qCVdgtqFLwaQWmytfRqSH5BGEEVqcsrhVApz3fK3MLvy5f7qDawnkPTAB7
n81cnJCAafYpvcIBsLxI6Jg0fUCVbnVG3FI7zfQt4RPZBdlIXGxxId2g7UFfAw0djqGuqxVgV1pB
9SuhdFyYx9GChMe3ejAgXb/dWcpcnDV7ONw2Tpss/7qtB3KXMKSl3df9nlSnkbTmoKlrZOQnlemT
5SI2nTXRvv9QyPnPN9DHq8By8ZLekcc8i0eJcA3ujDRSAO2p4XqEYQU6qQOmu9vDTnlhDqngAsLe
9jSKCmBls5JBxzEJGF5ZhOH4omlTW91pxAK01tYRg7MGOvxZFoCiRck75W+CsMAZzvHqgJNRAMZk
fQHPJBXczRMRP2kki57jc3Bh0IFuyIwntR8JEenVKndk+mXgr4k2Whmkw4aj0M/d+aTdO5wgHrQQ
IigsPHGUfQTTlQtzlo3ydH2C7AYSbs7Jn175dqO30WGFuFAWYXmzTrTHi3YDhGvvhLokZG40cDdg
ICgdhifWopWJ81wPCrHhPDbzzuusXvoL7nabNnLJmIE07Lc5kmWECkHJ6GDx7XzXhySmAZIviHg8
ws87eh5smpsNzYZC6NiO4bfodipaWfZFXAGbb0SyRGSoJ/AMCoT7RcnKkGPBQgO66G23ne6NaPye
u4uj0F58B+OBv5gWu5YSRlQnzvOMUdmVDP5q6nxxf9V4bLslUYR+OePEqYAdDGD3oU0gs0J7fQ8P
MBZKcciZbcsRf3uJSIMTImFnxp+t4ofWAFfDEoPJDUVJjsQ6TDfJ9WQhmpTSaU47MQqTWb90lLQu
NrTkBF625GkCbq9+jvhDHurzeFf3LnuDgu/bdkSrW7Fz+N5yY37plh9t9DgXVTuZFW3Nmt97IP4e
w8zG6SH8iKyfqdJCmM7PUTwNnmBXGEXH8MEgBW81Zk5MjpS5mApy57Dq4Wq/bQTLjRWkV0qn0C9b
FwG61oB/rHLGiCQho+gg7Td8N19Mq7B2Hz2JX335Wy0e5e8bE+QToaCe2UeecPWwPA2kmU2P9pcQ
QNzhYaAepLeU58HXjRU730CbwSyXPOU8NtpDNOrY2gY9ExcJeTgNOQU2R9NClQ19m4HFjYlNnc8y
Mh15XI0HHQWgTScd2NmuiMwEXryl8iL+P1pQwu3OtKiDRrWZOfkwzYss/Rt4ms+ESfY7lwWqIt07
gYNwec90LOpdLVfWj/s8Z1RmUF1IvbWEXabVYD9c3406BztNU1QX6jlV4EEebApYlF+p0jyA/wfV
hGnhWc764IdPr+rMrsIXnXaM6c8hlNRM1JGIxc9eKKYDXYxMCToSs3QnZMcZxkhAPPBohf06UN6n
CvACoQXlr3OspedOtOgemHuSN0kcQjTW1FAqArOn1KGuhSd62sKLiCOQo3OTWuI9IzXddM70yl7B
UyMHD548G4VkEj/3GgHwfDhp2bnZwVi3NxszQZ2wS9gf+Rn1uxNETFrG4kb5Mww2EiXs2ofWWTw9
xm2kxSQZvnbsF7KJ/dxLf/Lkdf7SCx5rCk58OP9eiWchHCQaY0qHXA8v6Uq/UPt3mgCcD7SLvNwD
IhdFiFUeagEAVvW/28uXR9UdCEopHwOtzBO0AG8RpgL0uZtlAxfDg5Rx/QQz8MdwQtjX/2e6yK3P
axdrxYEZs4sWekf3D7xT7PL9kRYHIbeWVtztHla/NH7/MQoh7to3SB4MeeWbx7A3HdNLFhm0DOXO
nlf3gL+4Hux3ekf8mCNx7KL3KqOhYopOH1iJSSaGf5Yz0hCwo/vDRxzfy6o5POoCn6vG5ZPPsnND
hUwBIVSSeHwS7yJb62fixRtQkZJXALzh3QBbVnj8ul3uVfnIAgXGlyCY1J15ccedLuDrdp+Na6OM
FOmeYSEwepHICf6MxbC6bSqDfwNmHPr0RFGhFq/xs/zfCDZKg9/+6fl26T2VPWz4sZWVDIQEwTGE
cMI+UUs2QU0l0/WrzdjN6yEmUEQLd9woVOw7pZC78/3GGXh+yEfL1nEskHRXSLgzst+XK0CgfF6K
o89GEQwkpCjAimh4caKiBzlmDGD0B0+5YNcMu68YmZ5NEoqlwh9nwGIRHAcnUPaWHvFmwYRDvz6U
S6q0YNCRDvhdBoZeP3twwQDUOQ7GhRA3BL+WSMSo2KpMl4W1pkkDIx4sXyPsUHHUbHMqXVbR2/yb
Puw+bNXJcwOyGMu/LOdNIDqWrkC1PokGQY7L6VILQMCUBmv6FxqYj6gdnIEC9RATW3m1NPxPoTv6
nctz1b8rQoW/F/9koBhrzHSekK6rQKZYIf5UAiV86rHHsqDRP3Dcqp88FyKlSoay65jHinTszgYR
XM8PnqvZqB7ULJVJfV2R2LDv/L6AsYFb1bGaosk3wyTaeEBfD+z2PlI9280WDDjFzENDEeURhho6
uc6L0DSRRxFLML7538ssXmkg98aml2rr9fsP0rAKGzA2TlwOuBUmZG/fhgX3zGfyrJPl8SNb8lBL
u450Gwh7GP6zV/qwGkuwHEBbcUCIqM0FlhNxnqGyeF1vXiAsERmCpdt4uoC/clBYvoHGjWOsvq5E
+p8UwlZJTmrSmy9wGB31Olnhi4AuJHbtSMUm787fHN0La2XgPxKPxpskj8sfpJurNvqPqi/Mmt1Q
5Hwm7LL0aKzL8ybhE5iOOHDfecG9PZJ98CyRG7IjNKpprKB8fD+2H80xyHa2QQSUE17Vs0wyV5h9
0gV9+w+8lGZjqbaNZ6Dnq1oZ9HZ7UCMnjrZwNbr0Xx9AbLmv22OwwXBDAnHkmAehkHZ2cfR+zQvS
5A3e+57c0Jf4alX4TLr4HZjYsobs+KaaIAerFp/RxfOm1R9KmG2g5PQqOZ1Ap1WajpBhGhrDDCxz
4eZjfsBBDBiv3rD8HgDe8e0c60qH/MCuqtWhsy9q74+pVt7vX3rdFm5AYsCjjCaAMApcNYRAjd64
ttcft1PbCzmgUj9eFH1H63n01VD9FG2GgJxG9uAXxbfUXNihcnIPSMS1yFM8jRb6FIJa1mwLOnx7
iRZ9gIMl+woTf1PzTUvafTb/bgx8TXH9SOaynkXmHJh+7xAx6vJ4Gz39sqvFJM/J//I8UduuvBIX
xguxAmoAOOwKZOqo9ch18+zGCYOcuWkD8r37xHTxq2iVENniq9uSU9pthdltROuKPC0bCX5qp3EM
U3BTsLxEN6tc0lNDDrK1cWCOERP4AGF1z/fu9amVhmJlJ82MRvzmudrih6eaATUtRahJfnQhD7lX
ovHkUFGdpy6Y9/IbgJE7yIvGClTo+JgfrfCOilGyz1lWiXP7bP971q/2qdLHiAYnUkHDI/G2X1t9
b3oi6fsbmNa2niiWlgqAWcW+d81Z1sQaKZaDLIfySp4YSTwqaAUx0NMD4tst2WMZ0HsMg87vbYjI
64+5UBGf8wiUzRByL8KwudEMWV/D1FvwVXTJFXcy65J2G/IpLrOkshh59hObSfLeNnuZBSYgB8/d
xktRZYD6b3bkE5ymo7I8AyFTwRydukRi0Tx3rk+UuOyopPmGzYROb7/8g8IhN9ASTuwy03GBarSa
KhGLeU+qlJCGBa0EuuxzSdTNcCEqAW7h9GDUc39nedA3lNrikQjlj+KamNcBTSXL3QOn49F44d6x
EvQc59tye5Mija/spJG4KEUDWCmfjua7TLK1CMO6Btf2r/ZPGq7O/TAiZ9/2YIDR00xa6lIeFUK2
EyOyDlyvMCIfJ+epNqNva4aqw5xVxwcjWcJGrYtacC7T/WqHkdmDu9hZvLh44OkfadEd9Dmf25Pu
DwHQ6ZfT5CrWNnWpTfoFDZtlgI/Mww7HURTBe1OkflTEwhehPvc4rVb8oO9NadoBAyLerp+8sqQ2
UwU289qriXhp6uH+69JR7Eodpa5L9OUCqqMTPcYJgBGGarsL1HseB/ja086Peypgo4JUXwwEYtIg
suaxJRojn+3/PZOoEnvfDf2S2CYevfivhEUg3jtGK64bsQMrIvXvWZgYQ2VrBlhKLKuvz3rI4yWJ
fcpaa5yP1w3XVOqOku3GMqETOU+wmhTFgvExczqoOSFbudrv2wS4GHK3R0qKPfyn14pNc8xf2FdF
WiEESw8wQapQOgcZmUTV4TL5+rJgv5tMZbbFQDE+IFZwwKQdLZsmiD4PktxpPeHTyE+c9zFfr9Qr
RvNne9wsVDHMz7RKIAJGdkLkTE7w69kEYsQyJAkl1ojZKxng8G64ctASiiT7UKLbUf0a8UmwAWe0
GcaIhHh4sNaayCqriIyLjtwcDHFhCW1T99O8v7g7+aLlMnDy1SkmhhIBajTdHaSr2kAxMs1+8AI8
2BsCP7r4xudMwCfC35b6AICzNZdXX665kJJQYA2IR/bnNqZmJMKbP4rJTGyBjAQm1DhA8ltUZxHb
ZSBKQ863mMwzPC7qjEQs/9se/6P5f9NxPptKqgYe2gY4fZOUnQnN5zU6VeD7ThFnFw/Q0VMQpj3r
0t5/K0BKshZvh2VGKGTcaq916/wPcRsdRCIVJ6u6yRe0EcslkJb5+FnThp+WIV4Vj7/Ckl7pNII2
totpnO/vl6pQf5TxkD+amoFmPNVwXOCCNI4fH9iK+6ewOELnm2gIBJmDmf1gopdCeTSCB7ajy7hj
pBqA41ZKXPkgGr/QgkRLzmiykkP4KUjW/dlEXY5/rKB60DxiA9shtrxLd4o3UsjjFxcCUJejwr4S
d9cWO/y98M9T8IXbiz0BQzzJ1ZHpLuY+IyhP+PEHvrfPbn5l8LHN5FpNHb4kZvF/pHvJBdIFBGXa
39ycQWvc/seAvxMuh1qZXeQwsHL4C+DqeIbuRNcwgwAZcKiR0QdYhDUiUsHxMS0uIiYmOgXvfH7C
igYFYzd1dv2mDPgUct4OI+aC8zBu8YJxMt/tPNoX6/x+bg0m7LC+jfp1Qp2c+TC04eYUm8Rj+ZJd
LOksj1x07toj4BeVp9KPBk/XYZAOG5evYETLoAOwakF6KKK0u+QAUt5IO8/rIOTeKIH4poTPOK+S
jvz3e99BP1NSp0Cs9d8saUdZtEDWq//HM2N/DU2IQUHA5ftrkY8mZ774RASDV7yZ51yknrJuSdSY
9A27HDdyFOr1EYNat+N8UEkXe1QYLkP4H2hSucmUAtZ7qPwNJS+F9k/rRHpGu/26fjjZZ/PLuEM7
HZ8MlRj7zgi7Ck0qrPiXQ/f+ukNkJcMkZ7tc9Sjy1psmFGpMmSFD8ZLZGOUtgjmLVUTfIMq1xu5G
eL7s4vMIGrHCXMryxDdqpmmRgS+Bu+KVNuTaD+1ou0ya62nhT5adSYET/zm78hP6NJMGCOSmYv0z
Xm6lcLafGS7QdJNVU1x7j9tpezUxRitT6BpVSzrfYFv0EiiGx7L2jWlpUJJC9vPVXMO1FphcIBcM
kS16ppGSKikktxZkRAZlHIYRHifoino18gFABR8Yh166VD6N8F35L/ABQugwlcU9dqCiSqoyWntn
KpyeH5TlD+IrXTFH2jhxIFQiSh4zeNEX4O0zFwmBX0SeEhMS/hSqe7A1+JDKHs9a5k9Tqn2BbUnw
8sgMBCgXu522VnTpyUf+K2GCBG1L4FvS81gChdqBh90iksdXx3CsqtQZCcKQ0vv0xnGKax4fbMkV
kun3lC74v8Fhdkb/LC+fmsvb/POosPWH+YjjqxfyPt0mJb4dT8WU2nnT1Cu1Rama7w/i7ZVsI7Pr
Ucv4gzCg+k4+hIMtMSGy8SSsFynzc0TBIxm5v4H0wg4znkhsuc6WnOWePgOS/HNkFsc2umx5dJkY
1tieSG7L/SKoxwhzdnYfBDZ1FOfOgA+N+IS8zkYV1BSluXtbh6vpsCwLify8/mWtFzFh7X1dhUHF
gW3Zs25byqt5NVY9xTOhK7Q2VFmKayCN2N4H3NneNcme6et/zk5MTyzHxA4S4vf83TU/nbMUyhP5
1/hhmX3/NhYDd6sEb/UwWS4lTLn13OlbPKAaB10cC/WfnSbX1SYXm8Qg1ZwXW/ni23SJGV5KZYrZ
SzSdicm+WMN92cKE67l6TVkyZNyao0vHPl7nov/bgXv0FmiCGYhzB5RlU9dewyZFOAyGDjB/U41P
SzxMaRpc/Ux6SOYvE+gyScsLRZiXucCLXFIy9JPjJMJ5FtlNE2RbOf4Fqp6YxtGMNy839U7UTqnc
p4lR3O4j4lCqvWI7bJ0les/RVlQJ1O2npWXrqJPatk6G+ifrcnMayXXRYemHMR9MWUTOw6G2vp5K
wgzOBeg0y41kfzFXjNEXVEC+cwI4Ku+wv2uv2HcOHBEgs1Phl6C4KIgkynL9FlyZjiFqxsbu3cFv
pr5/rdS7toMfMTK0icdUwwIlV3SQAAUjqSqnUs+WnpuiIDkPnCqeY11HOOEVc+uXYbHwnquzn0La
z3BkCSalgNS+sNouqBZf5y2PY8cp0JlCF950Me/7tbfXVyS4nNA+2190N4XayEcJmGIo6Vki4TCl
b+u220tksOyLjNMTtOFt+kJeCquVGa7UUXFfCkrWDNlVa/KjTtzSp7NRer2Z+ADL5B3WLRD9xkBj
zVu9nogoIY2UXN3g1ho4PsYvMfWqPmFN//RCys++gGUzNv4b7OQMSHspfI0Ufe7Xegm7U0e4m3em
c2x1fOnO0coBx5md0pgr2qaA5dAhugJryrH5pgiq9/E3xfiZ75sjhQ1LiGrvy5mv1OIdZruzirBD
y8woxPJlSZztMy9U0Gno/+qzw5vQLdserPxzZRwv0Ivcdbv6oxc6REA2Uv+RjD9LwZVGM8vo7Tlr
e9i0Ew5l/QqkS2/O75s6M6/c3gS1ofsqJ3cz8VzdOaGVZambzEHK7mG8PStaa0GJ6/JSoqTWw+ps
WGXJh8OLF6BGOT2JpfYMHF5m0Tm9Hp3A5eVIpBc2w6lXSn7jX1mDFv847e/qRyKLNB70ff2kowvi
rNXZ8Hsa36ZxFIG5MLQ9HU6aFyDCljhbf3ye21i7WwrcrtAaqud25HSt/dooTLHhb/VaVNqOczv8
drZkcsGb5f8cG3h0D06bikqvjV19mEoJVJ7em/KtlOJfuJ+sKaHP7BDfXVBff4uYTTz0yQ9led9l
OY7WA0jxH+/VeTGTkFbZacQ56jojmlJsP/+Vyo29Iu+ynxGxkDqx8GjAIz2E+D78WSMmWBAn2OZT
vGFpLrbU4ym2Unb2LGz1jZDm70lFEUVAIOAAovPW+XFP8jrdW7ydtPTBkOZRoMCHh95rC6Vte5mO
XIwAvfmY4evQXUTdgYJvAofwzQbE8DQAmwLVMahwdJQbACj4nUNwMVClEd+YAdNRrXTZ3NkbGRYF
meceQIFkz1H8yOp9nH6utvAKtMjIHxn4Qs/hw531v5hiUqcjPvVyo0zgrUY/wrjHWfSw+4CwRsc1
qHaGuExGyqhTRkEKJWSEz0d3iM10ZlrJlJUjUkopJTEQZgdjenDBuoTKLU34thK/e07szzaQtwhs
7B/U0mLO69K+EFawlcVEqUeSumHy6shGL0RyjYlthr8enG0f7xE3oPeIBrhieR5DbXspFSzhEKel
xggj7tBXA7jgYAtLGD+rNUJZOyep/lTFLyaFHiEIoprkLqGM5j/veH5b3ieMTAC+ESGfVl7ot0ig
navVzHGhNMKRnGgiYMulNwiZ4x1QJ3/In+CqC5AgCXLVW6NlF17CLcue2kR7cPAN9ym37ReXUcvD
ibRB/iuIiXd73z+h9DqFaQXx6yyRjv4R/B1f8BPCpdt4R1IPjTMW+qfjtrmopNRnle1hYHulb1Sm
78PiZdT9rGTDgBguVyZGCbnIF7DAICIMbcQzjYpKNY+yM4vkKnrJNYRuzFV3Pj1ay3fK0MR33GKF
I4OJn2Y5wAUECJ0bmxA9azX1qjox/PRxfdERu5CzTk5xOAwTZYqiJ9oSowbCAqUGv21gKr9N0C4u
uL9/gyPVFw1VH9gOrhKWRW0bHAdM+6IUpwAeCZuq/nW15ygBWcFymrE5+KzNtYgAYO9RMVQXitDF
MXmgshpR4scT9pszLvoewy2F+bfs367Og9Qz3lSIibF4yMZSTfkAUbKGNpKu+cGp69qhvlmA7sYv
lQLZe9ugmdhGTCdCwzX/u38/Vo3VliGjrX6+bvffTLIUMKjooTurSPnz9UFXdIdu16pkAQ5+41nx
C4b/qH4rwfo+wAgd97jaWLQ1tzy/PbkHHehuNdeoOdoLCORzCiXpr+TMfemu/JP5N5P0lR5Ui2ma
Mko64yDHlGMayJrU2d39vv/mU1EpRjw+YGGeUtED56Uot1T3JmBkDj+TeEzvIjN94IvuxKx0DHBN
0NGI2JzZuL37sv0oo9tnbNuxYGTLkajJdcpxjoYG2Ze7PnuZO0wlhq9ay0m47qJ0MbzemdI0EEkQ
4Rgslbd7rNlHyZFIX6Gkm2tCEZpUs9O/e8hnYH+LEFpf8D4hPfVisSjQdRp9I+mx6+6Uj4PuNtr5
m0CwCpEwSQG+aUDx1GfADPFEyXt1Kl/3v9uSKndNOwgmjOHsoyb7ZbIOLJWmHvCU1SCxcrqAhMiX
4/7sa9jvMw3gSl83ETSMGdU1mLW3Hi5smN6VaKzXovFoauL31jkfe7uCVoCWiCFSfva/rLrvo6UA
WoNN0LDM3rkwvDr7wzuhJ5kgH9md+mWlH4oDnXaJ2WOq9ZNFIrlYn+v3kVGdmgO8uoIUnZwmwwgZ
dGJQVmk49W9oonHx506uxNjYyL7UgoxQcfj9+H1dgasLasixlwypIbY9HSHZwlxQBjSTsTczM5Ix
ajmYL8Nm04KYnfLTZO9IlYUbKka10XvTf53vHAFFwQ2lz9yjqja4AmPYCbDGlrvqc8BPl1rqORmY
lLKLVz+xX219QrNgb6KuyOfD5CxjLMJhFqPms+CE9qN19xJAHdb0lrGan8qqj1PtkX1EC5EnmsxF
HxrM4zYSod8f63i/0qEby70Bj2GJt2p8hneNGLHDNga4qd7ImpvWclS24dGndCELU7Z9xXlyz/ri
kijQO9NUreuancaL8h07EA4zbq4TYHIhw7FpDLtXj/NXx4cUzABeaBygWthIfK3isyYe6yfMnWW5
nIDhLMo4KJ/vEw+zg99BTLNt68Jl6RVVLLt6uXGqwFqPIIsm1uAVnRRo9CbVLh9aSGqktR6QlZel
KjWaXNptYF3AxO7W61YPq10wC+zidEum4pOnZoL/Z4nF/7o8Z+fZCeNVbaKq79RKdZfGcHybc8Hs
J+B3FIiPLFvLT+fMgSL4KBaSQvU/dwQ4X8cE7+9DxUw2eHjsaMB+QhYJz+hvnLG1GQuEV5tGCpFd
mFeg5nWz+YdY9EYfHvy3aJ17HIjCnQr4oLdtgPvlPj1iOw9kYskYlOImNFQIFPAgpKZIy7gCsgLT
Fbz3liOtYaM4l1IOa5l8QvfvlxBGLNXmBG3bm5cDdlGIIK5gks2ZfbP6lUMvNjyjuNZCPQm+s8YF
XP4V6w5jWeI3+sise1Gq8C9jyYlZfY1GKJp36Az7fyBgEvea96HQlYKNo8UvkLfplt1lHp5w/Dl/
CjWxX/H1XaDfsTpwaXLb44m33kzs2POrmtB74rjIwaY1Ct7vpLpd6voboHWvuE252ERfCVCrNJN0
XgmvEz4nhk+7Ac5K8AUyowWsAmXh8Z+znrFIRSSG+UDQjSXg9CgbUAm3f7KNudJknILdIiyaXLEC
n3viGaD5jXOBNXQOyrtK9OtyXwqvs+VzbakPuziYGEahwP2ot5I9YoG9+YzGl4KA7mbYW5CiRDfM
WFbz1988wAZrD2IRTkUKeEUCFumfMagneyk/ca6ebt9PQ54hQ++aeIZX4n1AQM59wpxGpOe8VjYR
mgWYZFkeLHOSCEjG2p1TkW6vgfjqIFs40/bc54mcSYiwSswmimdP4+vdft+AlQt/Zh8CM1egHXhk
icN/JH/c80Q7Z0RHouiIaFmJpCN3ydjrueyYQ/BkZ2eQ1VWyUGrM0l/iOtrqC+km7kugtgTb3xj6
saE+5XSgR4EqvlecQuP3XlkcRx1KtUfvwzHL5jXKvnu/BTPdlAh/XnoBAU27LuHKDwHl2HYFNtcF
UT1eoP2hCenYho2E/jSAUGqKYRhbPLEZbED1zalqjzajwTeUCvS+kEF5NknXmBTjVkl2OrbLYwiO
bW8+8QiEu7ISB058A69QxzXT/QuisZ16q8XfXpMYyiDV+fKBM2WCUIkkvKkCblkFH4drY0D8B24S
YS0d5Cx5WzaDH55XKbfMEWUpHRKcsO13bVNbNNJO/jq55iqM9AHjCx1V8uFCfPt/7UjFCwmTFh2s
fRFeyEmCsUauhBDbYe7ONq5lYbePfcNt2jFwN7t4TzxbzVkGTkgbi3yDI1vyHAupbN7r/VM2odiw
crVd4LynhhEi36NbO/Q2AAr+wLaOImE7JKl7aQT8LcASODU9ge9f75kc9U9SRqMuUvjbX4K3cB8t
bKPzTEejtHmgVf7L27UpZPAwyqmVABtCiAYW4lAbM1hZm7KL76b+8WwU1GAX2zJJ2d3Khybf7LYO
RM2Yob0QEizkfI2TxlkLdeIytCr8L6U5aoFBCApH2sVP7kY61fdsf9B5nyHdInJ4wjL9AU5iGUC/
4UrTNIH9alO0kOYQhPrv2jEy9ySb+mmQAW1M3hxlT86SRc/mOOw97cb1cnuMFFG9zsgc9EX8YZbZ
79EF/m8YyCfWP4AW54LnOCZx4f45LvpDWjryy7/twrGUvAgqVnWvsQLQja4azMFYJ/oY63Wv58rN
O7l0t0/wfgx6k8OpR2K8ZLhVy25lUe8eXFQSiaASlGiqSIcb/F4PHVE7nnQTJ81c42AFEqSkTWhf
X9ewTx2YhxTozwUWp3hSYKrpy0jAc7ceN68yE5NhhVvg43rJbTzEmOPaoXbsr9N7z/W4Vl8DQlhH
ezrdaTCTqg2hhPwIBuzEuxMHi58jSTe5FtZ13W6tt+IwdDFZ1+f2VirLHj7ySo4JULeTkFhehY7s
cPjgQwMr5T0d8L4l9msEmb4Wg6ec3Xq/cgSbveOHmGx1l0lXwlWIHjSQ7P52NI3DYfJVEGZJf9yF
3BlDiF5qax1V+qJfMpHMdu+nrS19+OzcmGVbybptUG93hj55CRFvfWX9f8PIBfkn/mHzBy9h69CW
8Q+DEDwUJSG1PFdXVR/E0slxogMFfFZVUbspHmV4yz/JNskh+dcihxEMVu00WRG0eFRm0RPqmGKF
0LY+iyjoy8KsulRps8K8XG14y8qFTgAW7CHbh1vHLyg5m0tSJsgEaUCnE/OUHnmuPrr0uRd5GMm0
E+uNF9jlkIhfGw/bX+5vqUhJZ9DnhARPTqG0DYGumpiqHy6IEj2OA+sgsFgtbMFNKPJ9405YAZrD
Ib3Vz4gUtq3WQzS2QBA9Drd8FAiGznKht+8Jg7puUwHOkNYo4rMZTRVTLayFB2dX0O7iZA9QVJXX
HolFcwI1ylQ3Vcb8lUv6XCQB+PHvAhSjiHVxxTVBI9Z47/AY2c+W+bquLn0rsZrBbzg9R9gpX7pt
8nUxROwm+O703UdTdhTx6dcU++IunHH4WhQ6711zbkEpzu/wBwOSK8CKbShBpJZ+iAHFzIHZtC+S
CJmjrtmAEhlfRYCEp6YA5LBxpobqS99AV5/573IDTiANZBrd+1VG8Vlj9WR6bSajr2xAiH1cY6cp
GZg9CqQln8KZrk21J4hr1pP7rXNU6IVLJqp0FNDFPCWZint0l8EshGTgeA9az+1Q0oUYyhsCIPsu
QqKx89vxTFibHxiRiXR9Mjsn2/MiYqpeK2cvu5H7E1gteBnsLD+OcGYKp3licaUmZLfNpZ5EuvZo
16nkW7vsiBiWgg/RjWyKDoRSkO7SFHQWXGV7o+Z5TchokWBxC122DO5RyC9TcxEVUci9tglPh/3a
yl7dlWcIFucolWWGmwdkXIqqf54disLNqiPsmYKpT0OAaQf8lrZpPgKq1SZM/dbdU7qBZ+WdIDXt
6Sz8yxX8U9xw0g6yY9K7Yodbk/mU/6kAxe/dm2q1/wS52cKZYv73jGpq8bbV1OLI0ihDWhpBNtHw
hKqLmoG4tHJ09BEhZ7mgYWVsvA3Gc5W/az4iDOQNHpl1o87uGfWQ5vXBppzig00HzZHhXsnI0zWb
KNDdC10HCj8MNSm961PcoRcryDkkI+eKZ9yC4JcR8qQ2jcHzpuQp5wNlDLr4Fafva9ukGyE9ccSo
b8p+gS2uohgRI6CGniAR1Q2vFMBkxM356Id1ILyEJGFnCUfu+A6QsHjtCZzHn3MaGFUvU1wJHc+B
nq1QMbG5PhTgA92dCzqcFxmkhZV/MK+B+xtoyvHH3OcaJ3QcTCKlCcu2EWtdKHvqatGCN2zdmwa8
q6Buu9iZj97ZgeHHbczJ72wjhahERJKkzbL//3stBrNN/C+oLNea7jUxjHPwwVMQ3BF9ziPZSFTO
CpqY0agLKCWJycYYsUfSov78UEV5/f1mSjAOM21M16mfFAdoiVhXBXKxHA9y7MN1s1Yds9NyOmol
y5mHjB+zWj0XJ7KXG8hf9pjUos/nb+m8JcogW0wdc6lDJVh5w39i4LrJkOaloTtAwWoZdJ+cwM/n
bpEBZ623cS+xcIuELOAU0NTxkG5mhlI+ulGx1uTpBrNqbEpx0a17hmtF91kbEPW9qCNY7v9h5A/Z
s/IedrBB9fgszbu4JOK7iNqm0N/+6ednMQObZjyG0wCMgQ+A1h7avxr/6Xs+4/1KLVGLWkuMR1Jr
8D2lIcBEXji7NsXC/qhhuYKWJo+RtKW4VxTmIUZDDwlz2PeJ9L5XoPLmRltkYmVSKd+9fZenjLRq
idc8k9f6IvKyy8wBAuCpooIgx8LVD63F3nu7TNwgBsQ3x6UckAunHgqzeLjulrmbbbDCdHbo7/Kr
tSflx72kwKnORBEQIkpDocJgiagHqVpkjQCWEAiT2iQxU6H6Ns8TJZtZtSn7LzjqXdPAKPzbLqrf
szVL11fSiR3eNdUiDOKOC8FLltSlVSZjxJUTQtJSjJgdt30tcMKJN4wCavhoRyTTQvFrSKqvJuka
mcVyHV+yY1swybg4X+ZBgaMZBaO0MuRWCkuM/nK34/blI2/wPL9naWbKweW3A4lp08XukrWlYbZQ
uI02GwiKemYWsEvaSo5I26qiKpHdDetEiaJjabKGiw6PbLrNRWA6yyLnDTkw0n5ncrONFKIfF1/5
9KB/7DGrLJBME/QoHEOvsyTIjymKZ6kLrHeP2kiFASS98nvWMK5bGOQR5m8C6rPIHeZjVJdgVd8L
17M9t7wGcSkjXMQkPd9RjsVOU784mNBa6sFiOYYIN8LhNhSdfNlI4rLK/r8hOPd5S6x6vYdIzp2Q
HBCQFhcqDJdzCPKidCr2wgAdTUii9S0Wy1vkk++RaYNNBMTjo/JcqanVP80zvJJt4yvm6gZPEd9s
2OBCMGiOZGdep+FL8iVa6kHcKs/K8fhvrnJM4m7RCglM8kMtuu8UmRDK8qt5VRXcbTyJNZ696bKa
pE/BpZRc5uHMo7bTbmqvWXI99qapMxN/+1qkzMn6s5GW0+blIn8boa8AphnUKfVvRiEvFn1lceQN
vO9jSqCBbjjOj5QGNC2HHDticoTly7w3AugniyYXvjwnGF0z7eDyIDcrhFaRsK2FG8/P/KdLNIFV
oNR2yFaFzOJSD/5zAbewMyPoviUqY7T7IKMHKbxGvn5k0zoItf0+2tfqFeTmQyVVr5erOc4iFDRs
4eur5ZjXlzA+UwIkLWpmRtW45/QNO041tNwbPQj8j1cuxGiHMRJhuSlXawHmFhiQemFursPtlsbH
3JJWRv7cC3Sl22e4K6044MGRWoSCy8BEv0FrQFkZouCjxhCPzbuqdl7QrsZHXDTYzQevq/O7GVA8
kb/q6j41unZU4Rkbe/rsIgI1JlCFN3ek8QizWXWIvbD59CnPSYbZfZFU0NsDDLDnlk+pBvZizMy5
oGRjyWDfFh8QeTqCQvepx072IKuRfog0g9VrjXfLfqbyqUfmHpx1jnDwWxMdMVZ2PuxTI/y7dyQ4
gzWoohOXWRjRoIvYEDu5xjfkDbkkfHjaLXhWlOk8IylLJetH6/zQ2Y7pbBwJ65EIfiqNTSFsYXeW
YfXjWzW3UuAg0fUCeJ/rXUjvJRyjxLqapLOOmakTZjR4Erq5VYZEl5t2ECwsfVwKwr9eysrjSVmx
NL5sY7tsX/Dns4hlh5NhdViMdg3U3sG0deLgEqnDdTUrBdae+WBYLXIU8LXrU6xuqS2Q9jYwgMG4
JBNVft1CEsfmLRahrYQ2z0qydyHyobQ3px0gVtvPogQjfJsw3/3rs9E8MYe+QH/lFnMI+ajMGqTK
YwEMmt8gfFir9TAG9eKGXRuDG/dlu66kgdRpddxN37iIsdOv0jue1lXIgmMcPiI9utyqGZAZrdAK
gr49gAdRy6KjO15pcvGu5zwWtJX/XDbnTEhbC1Z0EddrNGvAfl4fekyCNdm6mSrPsSyN7ZC0tA/3
qJOrpLIk8BUL02HE7gJNBONp5oo+ed2WF4avIDYYz6ZEcVnCBQZ0ingI0oT7dT1A06E4hcPEDahI
WwXZGdwk6Ds0ezbPOVodaeWuVoyJONjaBRYBCXX00Vhqq5NDMsPkSS84/btqMBwj/oxGRDRnjbKN
f2uX/FjnYs5t1yB5x4AX6HDfnjkI5ddhNHQNrb3qimf6amKpMhGK/Di/qU1At4fdjJQcFc1z71Tv
uP/yezNytE07C/ExOKaq5HxYyQrRJr4dDmD+WIkqeUwVATit27zVI1ftdFZMl0/osIhD7M5h7EFO
3itxBzqakf4Ne4BmxANV1lWLvbN7O//afTIChFr7+PqBG0DhlEZGJ/RB0QHoGeqWFMVEftu8V/EK
ZBhwvnhdWZnZSmSakk11pILF9j/8X8jZl44xDb32hbt9/nwZi46TnUXx+0wtjYM1+pKWKB11L+HG
qSULbWO5J4H5Ht9bsMucl5zvz9DDXIl2TxdQmgTKFQ0cjsJDrPe+MO7EaarZSvKba8zV2YeC3hyQ
NAZmno1ZjOQalXAfo4JPP8ZHF9v6PvqASoTAMMWK+wbRLpgGtzn37KwpCQEvkz1UnV6vf2xASNpZ
HQ9x82lWjYYUsVUAapa7S8d96FwekNtuJb/av00P0gLIPMCUsH0KdR9zkGP/M/vM4Csr8YoBj8V4
gfasN6NZ1WFkvbgsGMd1LJ9STsPX5+WYbQuEY+ZwYSLCtU2KMTzbD5VpmLYlIYYeMDqM99CnrFun
VB13v0moatrSVENxxhNkUzuFdI4Ymt5um21tYSNWObFOjs5kuv7m/9Tc3ZiJqN19d+PaGt8n4TfF
ynD0CPqTgUjUFtUfzBiZUnGO7zt6/g64zUy4shZFuQ7VA9dEz5l8ukVVfwAFhPLCkQKahnr2mkq4
Nf2c98Dc2j+YqlbYKHUwFC/ODJTlK8z/N+uTlie5V1miMvm5FBO7+qlMZGuIRHLjvn34hVHTzBG2
Em+h+RX4Wm8HV6bClxKfjI6XgnyIItPZ5DxzShQgCE01G5x9mjhtfQeLt8M+ah8eYFdm13aNx4rt
SCo+X/99peCOrBauJufA9oelR/oRtMBx0S9MJqTbR3Cn5deaSJBGNRIsCAt52O5DZ3caHa0JakBK
+lJ1YZeGXtT1iLKJmyF8eczLvd7iidgyXJJZ/XRJIJI582XLjyu3ZFj4nm66oKL7qrua6njS7an7
hukK64dF+30RQa/mxdQGx8VQRnA1zKU0xM4d+gJY4l+ySQlrZle73rRK0JaoAxZwGhd7sVAJF4Gl
Y24YZgDGjmwaiK8leJk5sA+4/mmqC6tygp19nE0cvX/JT+xDkmiERufVfI/p5S9vxbski5XoGAiQ
zleqOynobVP9YzK6KVd4HfQv6bEctLBKPAYWQimtJJkcT7Lqe8EUGwBqvPNQBzYq/CutRcj7aFK0
lmOivjR/VpNYc1Nd4GeCaDGvLUBg6BJ4D36a9PXmM5jnRAjqKVwb4N0MPW9lzhnx0f5o7uVH+/uc
B7WHCeG+8DZ7QLVG97slBj5sHq/qce+7rGvNBlckmY26Os7kJ1DYwgEoQYG6H347LvEh+jcSxpSt
QegPkZgmYMIAeOr/7X2T/lbL5gxbEK/blgXyPLqc7YDWQYNTydySUHDcfjc5er05IbGgpMUFrci5
/uPIMawGby7jID7IA/cN4F5NrhjTOb5FQ0CUpT35BM6ZbriLWKjv0yJQSTkXZ8DCaj/qwV4iXaHC
M2i8fAayGVPj/+cL2+gLQuurEGwEeJwN0EVJIdbx0NJVOext1P6T6lHsa8FMYHt8jmzXnfr8zrdK
2SDSR4RhyGe40WJ2fALtJ0hgQLy6672vDFr4QmRJwE3JDIf/ssz3pse1A2DHw7/AJ+FZ0SWA1RlZ
Prl6FA6BypJtTwj5mxfwPID/Ggdih+CkB0PyjbgEgc0zndVthD+ZEFIE26PV54IUXr2axsOgTc8U
kyPtb62zeTa5JDAQqF2kI1spL5H2EEE5uIwLbZ5DCeCrPlgYOxjUhfsci+9X/Y4P4BpeZnYmXMtx
OefRBT+XY+8bGzCMu9K1rB3HizM01ZR3T3r1azJk8w34HQ7gVFkoxF0ZKvyel8QlNPtCOFnb8vLT
hpn0TdsP23eRvWLIV7GCxGGrr77I+3J1rdWAsPt7F6TKIJMnxcn4xKxHcEcWA7HUc9Jkrl0q+BTu
JsD+5oulvu4nsvFjx09M+rtm/k4VxRr+Jhg4ePELo6kLAZHkXZdEFDre6C11QFqaYWPTWv8BxS/n
CIJpt2KWpccdJtX2UwRxUfcGkkk/+StQtKZHf33kp2YRkkYVFuxqWjmm04lQPPHm7m6FbgwfZaus
QT6GdsrLPKNTpnv4rPZfMWPNW2cLjLqjTW55WlxtkEInvw1vMxFJvb8DC+2qNknAMUgiSgGW1S2Q
CO/OjJhg+cA7lP8P0VaxPb2ohDt6mnvC9wc6gPP8PQm7BuKp3lVc8IsQHKAzvYulLKjNKWwKGSqM
vAlY5F0oQw5J/ls7GC2IxaLsBxMcTIB+BrSZ4HPfIXFkkVZIb69JRgGPjr9ZCR+SdxRLkKRT19jq
76MKSm1J9BrpjLpJUl+RqCUvdaaX2sdiVBWPVfVGl4Mpm7vQ8rBY+EJkAnjwADdA9qWC3y7UJBcQ
oU6sUynK003lzE39G7SDd7xG9lBkM9b3asRgCP6PtSAUzt8Ou9EKHfC0cGbyze5gnbUH/+5zU/ih
dW4McJfHUfnKx2ZLbGIAalVhnP3AM6GeUjBl3AWh4GdhdGHzGdTG3rjavI5ujj5JN5VrOIwkih5Z
Z1NKrIOGV0nRmtaArYq7iFhnj2Rd8iiGGQXoToC+FL+mB+MTpu1l9+Nx4pMBgdVtqpZnk+fTRJ/F
/ZNeOffMJ2jpc+Q4aYN8LYRhBP2CPajYm+7fw34EacmCz8X/w5qiTvp1WuUvWsl1THYiNJy1fwko
uQoIgU63o2P5OOrb+bxlhbugaFIVUPyv0HwrcQ7TvPRlduSmr4DKTmKZqzXFHvCLCOX+h5/iRYHm
seQFWCTEZl9eKqMmslP4doZGybW70WFmi0VuUYFOvefIwi+RrmGToW2QPFbC7wcCr5qo4NeV9MCt
gkG8qTOiBvRAMI2agSPGSO3qbPj7FkQEOjW3fEi9moALGzATAPLpc3pwDyNih3rgQeTktrhxjDXd
GEiRTo5HTo2LWol8E+jISay/W7cmyQu6jsife0spdZxx3i40f+pu2aoUuB7jGO1kMshU0lQk7nFw
KjEOIpbuKvdcvnH5ae9eKyoXTpvLPwDzIQNM00oZho073ze5wgZMgmnpHiCuyOR9OMxz5QB1VlXW
wWLkITuiKLputLoWEPObwEm9MMePUKnMTI5L1wo86s1WOMc11OfKVHDKA1zTx2DF635/+G9+Kr50
jEoCfGL7fctCLDg5wcXsY6k//5tLXfr7+AjWBoHtMZwXZ3pX81yecVyKFLGpv7S3y1AJWRm8kLYy
tTHTseAImi5Rhu+7p70VcyzhKz3zsxWNdm6sOjYNy/hBNWwFwNJT1fyAJU7ztf+4cBcrymzJnhPi
V10vGPrGsqcDvMwBO0cW9TwNAM/Vks4pyTXRFKWvj66llvroWes67L54zeO6pHmdpvnRdbzdkV4a
FbNMQ6W9he7eT1SxW4UjNgB/mQi76Tf02oN/Do/iYhBj0DlNbSQ89iu5CFZ8ZTwpa2VtKo0MTpcj
uy96bpt+Aejstx/FfsrLQqGyHW+m9t5Qg207BC934xAgysbibSyPj2D77SOvUFTN+GYGQ46po3hO
JQZugaWuqCIQYqIwbG/mqgQuA9gV3g0LQLui9GNUyH/J5K2eUaqdKC40U14+0VO8acBztLMsq7Bc
AQA1TvIQUfheL+rWPeaN6XE2/01YJaeH692KL978RycALzzG2svIgASsVXX8PUhbEdtxc+O3m85C
IoAyFjG91xknLopZ2/0tlrVjRNeD6acul+0Lvk3FaamEETKy8e4sc1govDD3v6sVrwc1ud6apPEj
fqWdl2sr/kmMgWip1b4vFz0zDhe8Ljc8YniCGlCFNZyGds+a1siJVbrPpIXxPDmMGFkY30/lJ4HR
hAdYd6/BltC/A4I5kU0Sw/gm1GGrCoIbk7b7f4DVqCVD/iiB6C6TeklhXjtFBzttxvJj4eT8lmDt
6uVix6eOr5fdzWGcJ/UBiXv7sVxXGDIqI6m/wJ5c0g5/sKiGW7Y88BjF9nbYtLfLoe7QFyt51mI7
XkLM88lIW8/LS/PIIK8AqwQh2HtbPfU7Bx52mEoE2abq0HK5ZD8MYiqQWMTdTisE3ZZ96Y2OthL6
NnLvf3tc5o2cFkbbjTnkRBeRO4G3QlbZ2RhOYqx6x7viTcIjhH3Xw33KZuc37y89OcQ8msGNn6Rw
YpbXHtJoLDKAjt4VXpJVja5VO6exEf9Gg+pY01ghgjQqSd0GnEhGXZDWHA4wqMYEIlHMQcclaQCt
zG5yHiCrrsllDT3Q+fKtLTEhzvp5woFJPNdm3oWQ/MyDvhaYcYLjIvf7jfwBEW5qifJD6CVUAy+d
UXlrAsMGVdaEWuuTwognX1GQEXCj/w8OORsBoaRUAm8QFpd074qXjUSkXVAUYbFTgJhgKbmcV3zI
8dOEl6gZJoCWF8QDBUnDAg2LkT+rPYEHWJ+I7Ix639KOmiGDEER9Jlkkom+NnynsJudUTmRWbHOU
zN+26M1kZC1JYjaWJm9Qyne5oVjLp2y7dZPWlZSBH8qD75YagqLBEV780wvSXiSxyrmo9oW6mKCo
QkeFEf80uXcXMNejX4CdmmIBDcEY5FN1VPMCx2GQVcn5/INvt5J8iR7Dd6nUuhHyMdQIf9tXHqiw
22RvW6KsmPRo5mK0AhWwb9PMohLsJEAZuLXFprsh7AD/jn5MURODW2Mo2KX1NNG/XhBn1Bapen5H
sp3fCt/rNSeGZn8lXHID5iM8TsVKH+lN5y5B49sx9ELBV7bYRcVdasgycPF6t9suSp83CS01XMTz
cGpmve9IfdKN9XfpcFag84VQlw1W3o+PWEGUBxmoK3kOhI8iom8NL79tLQoZTZr0byXoN03wXMfQ
dZpeRb4S3DLdQ/6A5DqZu6SpmX4FsYAy0r5kjihGj07mcZO9NB7+yOY8CyAAmOgbNm+iQijkbqKp
xjvDha8SIsJ8SvVY5rp/WUcTz4YLJWWwoxYwPTUv5YYBpq7Pazt230pdFeEbK2wi1uRIzHiI1H6h
lhvXtRo/YrDCs6g5saOq3xgKzTMuGWV+WejB8SzppFMq+xDqT9C6g82CCxaNLwG87dpOesWsEF2P
Era3i4pcyi/A8CwuIzHgphbCke5wI1rnQVtEEiorgOdMrlqNaDVX6xaNL/N8GVz8V60nv9yoMKnG
bP4gjPFHzoQpEiB2duJ5yUZnTY5RUFdDy+Pp64aYqDq8DJuaQntjgseauK1V86KVsMjRmCGPUiB+
AEHumLPaHeuHuZviwgkxk2J6VBfSVZ0ro5JUUMNNPrqiu9HIi3xYbnQcFbb4ODbMQaPDo2ewBS7/
003Rv+SIebzkrjUaIrjN469FJtlkeIhD1pqWtf+1rdl9uAX3DmDdVAtizZMhAuIBnh861Rxra6qv
vx7Mo1JAB/2wvuTByQrvv7p3sLc0Qarn3ywflSLTTwf0uYOarRNgrUz22UHhZxlZpIq6ArXX8iyy
Xtc0tkjEfTIIFsms7UH2s57jFVpGlIMvDjD8YvfyKcw2cCOB2rQT91fhefCMS/3RjIVEbWYlU6Wb
USpU4Pp/DPEw0GAVtizGEnzc5DK8ahmlBDUJTABjFS6eX/2RkeSMZJdY7AqHCsZVYnZRTebI/zwy
fFCDzr6AHNuoAu+TZHV6Ut8yaK8PcGgKyAl/1L2moiYl7UfJF3kIWHaMw8qpIzduzgkM7o2m6g+W
hVOVfjoxPKxlo4FTebP7IVQNxtuJJk0R82nSeflPlAzrymbJh+n7ojjOKAZ6UkpehSA4CtsOziLj
+qEUfsBFzbcXCgJbgprJu+WU6URNnvZY7ZBOvaEMjQKHkUzJfkTxKxvlDlE/gcoCU6ysF2sUL47z
eyt7yTzZ/WQKEjk8DebPz+io+tSmchVeTeKzTNflYUVMPDgg+WRvGv43PLOu+1WGofrZ5eJlTpXJ
1pQVPudFu+Q3vekU7xFwMpHGwi+Qul9hR/sKTWUsNXbbXxrpl7Agwl3af4FRL2a87r/Sj099YJGI
GUX/65trfo889eQmqnueUcvxuoxRBJRKbn7b0cR0yTxwwkhB29EiBAxsc5TXB/suJsGXY051OF/U
HKEgzo6m8z951Rjod1mw37BVfgumwr0hs0LYib0/zTysvveUU2Rre13+2lzxAzGdX7UwvkDIVeSk
o3zoHqdLqjd5KMab7I7UX9RCREdwsTI7c16z0nFvhNrcyCOxrlWywL6OS4ChJvhwiCFBd96Eo/Re
43YkBQFVevwYdvkX+fq5h/jZbqHROZF/vihz/K0af807RUeiJyJbht/wVBsKLYczA+BCLiU0qmkA
SLXpbwNHCF32WdSwvaoFVa/Ca43nU43kPK1e+fnwWaMjeSybz/TYE08vH0oV4Ky+n3fsyUSatDsU
+pNxDIkLbAdDH9nXMkp/vL3K5smyawajivt+oEa/ibq8cElk2/RLaLp2Fa7eOoI4+AYMLmI7ZiUP
ofaR3IHLofPGO09/lPJZHq/9zkDqC45LAqdL263uuntU6tkocPF1uHabq6hOZ7XfZURgbuBKjGkD
+5c0OdTbKOGYr1fzNSKgkG8L5xfg6Nd6C3CBC6x1f9+OxD+Vn1EUhIhFVCZ6eBQE+vytmyLSw2Ki
w+r55pO5XaEahg4CabOwNkVw981YouQg7bQLDIYLULGa0I0ABk4SZq0J9DwwpXBU1o1zTtqzZJri
GmtL179D2sGgJPokZoLF8oQzjes/ZH1n6lDIaTsPSt3A8RnSgmeBMbUdEZpCWJAqqSjblJald2+O
4XH6+mgjsAy3ZPKG7UPWPiDZVI2FGtTKTaUyPvsSxiu20b7QD9m+8MeDvXFiC/QWFXdqYOX5PwjD
800PNPLdRUdQyOENPTIQOyiSSqYfbOEDXR48kiQGFpZCTyG6pUp25Rd9VNppw6MrpyCgHfUYFRYk
lDkJa3XCPufJUXvo4c7L1fbHQtVk75U9PqIVk0AHfs6TX9/K+XAKxwRBHZ1l+tMN8qgnuR3I7Pd4
8P3QW/nX0EaY0MiXhzNTJskX7wKPFRpuk6Gx9kbuhFw5H5wMyR5xSGWdllLJoGIJSXOT3xqu2Kdb
iI0h6Tc/ZFnx7LYa7J94bRwLabHLGKc4O7rKEiOrgUvasMDIClmZWMPAZIBvQlgBuPw1MByUZxZd
eXsHjjq7WqU6FTp4FbX+J+B2RiQXfOMZrM0DI/s/zTTfl3W+mZXUvrhMq+ZucwT6VpZVlv22ifXJ
9h8tw0VQ9Ema9NyIVLypSS68xxST+A745IlGoywp/MYhrZ9Ianv9jjlcIeqhqzRmXsnJBbB5oZ+y
U1sv/cAtrn69fjm/EKc9XR6gkUsx6kIrJYFqLkZ3ZtVjuN2U89Yd+S/6uMLdhzH/DU71/+6cNI3X
G5+940PTA0d+qkRUv96MzMQQv8AdK80d2/ZZB+keN4vYDltd0N4rbHZXP8194zLnbpmWV2ohxkED
giytgS9kvWbDej9NVS8HKxeQ7ruVqfkClEEKSK2vjKr8UwA4NhlcBMEZW8/39iJPxOQW7fCMWehc
t+54MoP/YeRhGQhtADxZO9+1o9aCegMnVrh63JL4n5Go2JIiE1aI9gx7Efv7MjtNjT7bs/svyLkp
xqRvXSRKY6vGm13sFR2Iw8euMTijr19H64exLxcxoYpNCAO1Ljbx81QN1+XMadeADYsn+0ACi+UA
70YU4vaEDzBmQ0xcfjimtzZi0o4JLbKv+pmYBDS8rfJmZe3vOlPJp6VkZ7oZfZ2lJMkYfpsgGFPQ
K09AeCEBbgm6kKkhD8BeXsDryB3teP4QdIhxBW238jYZqnQxQFn5RrvUxnjD8qSYPbvSPUdh96Pa
IL4fePDYVwNtd9O7ZRWep9acngcxLlpnL7ocea7Ne1nRCYa7bHTQgHqVSPBZYzDAV9nEziVe/Ztq
1vmhqgdTGi1UQuiUpzol2pIWnyJHa6imx6GaKXRUsueiCHpDddmiD+mFWN4G2s4KkUoQr1MSfA1y
5RYPpihkcN6fMzjvlCAhQDRXfFUgTdqSDIKChrIM4Lc3WIDYKLZLAvon5lF+M1hIyT7hw25fvH2X
8p0DsirwsvwiU/CowNboHPT78QbwoCyxgwz6h7aMkapTUhJJTlff1y4uia6RHa3G2CIBbeT9G071
TpLlG6hcEvVas1BmOu+OnZZLuVGMXkPt+hUpmIlKJyvU7WZWu4r38fYCzjdwEHWSb04MMOw+vjAS
vymo5+y997Athx7I/9VUem3eqioP44gWliXFkAjdpo764CT/FaX06GeonFPTwUVfehzlGPaANu7B
GomqmaLVh3gIuWfs9Oq8hdOO6kYMks/46On8YCWcmw3rCHipKy89l/fCiHzU3HvAQjjvYMKLc4Rq
ZrGd402yppJJ1dF+FLjaazprFkAfCVTwHjuzxVpS+xPVbXvDWV5m3IJ1LENrKCHzPP+92Qfuk5W2
fgizi8D/Miqqw3mEFwqdRx0H/2VgYXI04JXjN5zQB6J+K49YDiQoh7yJHTElswZ0ZcU6tbPACeUE
flFP8qp4EEShrRg6VnBX7AQQj6BTLdsbocCw6EDkDNgsZsxZPf51uYQDWQOcfI6VwgpOu+rk5njf
TTMwXUuXoYHt/bp3uP/9G2cUAD/bDUpz+mc+HMyKfvgpj/7Sl+lvlug0+mVXMHN4JdP3m+Z1X1BN
gQz9UZpHs1Ue7G6Nc9My8VxvapVKhjYXyZ27BrzUaS5jMz07Oqv0K+HUjhjWRFgvdKtnrdwYDcHc
WjTa+HzQ36CjaYwDT3uu8I/p87xQ8LcBCtqX56wwxMPdfD/Meu7Y/pLncU0F5rkJ9lbpA9xvDutV
XEZWRgMVQ2HLFrZA3/HI8A3dPUooQz5zV/LP3HCHkMijIjIBBPKUk73c1dt4VlDmDFqdAj3p9a1r
BM2b7X40Acv2zL31XZIc4SkF74Mb9KK1CUVI9Mk8INydMA+BGQV0uCzjcdErjqcb7astn7suDmXf
w/QX0u2dUmA5Tu1nflheY4qvbw/mg+GmY8gZBkqEzxpmum8xnc/mm/l6M6HcPiTQXCyz/wF5LHla
biTCJWcc4+/BTZGrm+cNBe5cL+s5ayx+Uv8zOv3l35Yes+7Qs4Hv9LP2vLn1hH67116QUsN4MQ1i
wvMtI43H4WIFebEeqawHZYUfgcZp0uQsY0GOJu3mFRSWYx4QGVNnZfdMgRWM0PyBf6oGucrwZ5Fa
Z0BKIbyXYIWBfiCCvIMIfJTVr0gI3cjcC3jI6i6ip9ZdVrO7B/6ILbQp9DHX8NqxYbrZe7bLbrXk
A2aM3yse7pMUOZieoaj3ZUQio1l+lKZIkOc0s76q96FWUhNpxKzXX5KVKGk25R+mVPRJwTTE7u/B
BUvV6GhZ6rzXiUhVF1AIu3oWt4DP4hFL6rmzYwittLEX1JjUxodQ3MMFrt36WK4EQImTeeEUbFpt
mGvBOxsQncn5zBJDhlUUz+t8iexlzp2qNOAea5GVI3WoM0fPRZuTrpNWIQrYY3HmuDhMI2RYDbN2
c9eppX+riiXOJI+rrhaXAEdA2/gvjAHdiVaQOCqgLC6EK9X/SiCTb4VVIbj9c4Tzf1t8j8Etr7gz
4S64x/dKLd1b1g+qpmUdpFZaD24aOTwkva/ZOlKW6AmsH+S/Ct6zqoR52yW2sagCshhvzYVqXHh4
idxYRjAN5MGqaCFIc9H8OmnIpOGddV3uEXh8v1eDq/ovtreNpp+363N1nAE1U18MEUUhnVPyEncZ
qFC4v1UoIorxfJsGFyVh/mA20x4DsXpgGFnWB1t/qoj1v+KeU0eo9v2qZZpUf7l7DjYYhvRsCkjq
4B7hbUabAys1LIF4hEagoIcrKs3HGk5Li2ZKjOwM1WvGrkbdf6yMi8P7gIEVD9E+imWtHi2T7qHO
JPKHUywWJ+T9C9T8KB+tZdBVQPyT9UvJBjmUSdMe1G9XJnW5k6o5+pGY7jBf3Ss/Yf+ZBB8Oq5p7
01IRZ3c7+1hTN0aJzaCc9Tl7FzvqTa48rz0K2CZgdlLjl7gUfxDGfhEZnhpygtJK4XkWtiYpMMrx
oZQcx59JchEI51GqEA6CAC6BXMCLQkuUn1ogOe5mk8LpNhwKboquzdyffyUNxj/sxJq2vOVrvMO+
KcSa6GLYfDFHB5mtaP99eKom0gJgElSV48SxxNcCuM9LNsunV1LKGZA9yLLOhRbHwVjPbz0D8d2k
v6amCLjLbejVFBh26QSN/zIgVgfkNiFImkPevbEsDL71bB+Zuh2YWkfbaaNyDpAYYwQXDq3kCkdG
esogsndQQXxgLjLlGg0csPX71c/zI3/QO3Vu0gIGsoaCIM53b2MlkmLJ5h3x0wzRjls2Ljnx9FHB
k+YK8niGY/M/9LI6jj8VNQArAb5oJt5evviR9PSi+mCraSr8/FoUWj1FDerscaPVCt/rcQPlbbNh
TRQJRQ58C2oEEDq+7CB54m4Sb5FHsY1rWOE+8oGpcdT12CuMa3r8ngg17LniU5iL2WkJPDSlbrnv
+wfvMWChuS62/Hn3ib+KUV93kTAmclEIHvgBr6VtCLxbUji7huHsmWzdpY2xY56xcaF6FfZe7Ac3
wzt7UFXmkdAS60PmnewDDRZsxrw6dwZIMx9HoONGc0MAxfJyaz7zKYKDM9828OaHgH7+9sJe/eTU
xcI/bwE4Ozu45u5eH5Sz/lNHu+JiVBGP1zKb41+1tMmPP3jvPjfyjL25+wDY6C/e/6pTfBplIOll
8vji2HNDhWvLMNVGAGe6t6f69Q3hwrLtVxFry5l86nVQUBQfflMh3hiaEAxP9pTUZbbMZ/6FIvf6
B8WDVvayiCvJBPQ5viLtG6NAoDlhchVOOAnwJNRnyvhmX6TTHZEfAo6WoxL+BiGizEChySoNxtKV
LIxWznIMbhFllZAHLc97JIn38KRqGj4GTKG27S2bHT/5n/0vznl9F/IZBmKt/5m8xbimxSoyRFAS
T2wVAxAhpMJhJvOTnAfwIqQBlR4gkOhFtUQ+7hz79dl6R9AAXkI5Q+qQ3m+/LBlqEeqSCFb2uG94
IykfYnXhWx1pHc/ve/HsyiTxlgYGkMOvVq541EgrHdf215JneA92rWttDoKoPy+UsntfKhmh0cjT
wYNe/K/iS8cz6Y6FHUj2rpDCyBg1vk/yBvEhsPSCAGzt5dnCwJL3bGwawWZnGrWSXnX/aKzIkaGv
rlce8dz5ElkYSaIjzXH6xGB2iogA1KssfvQi3GJUoG5NC8YNlY1h04wAvV+sZBWymUWvqvjYXDCl
PVo5BNFqobFgLD51xY3H1FKm0hCyhi1hP2rFHXitzareeD8+dPHxIry93vj20nMrZcCcbkClB5Su
jfmsUJQYQhOioi5FGmqc1RBhaoU4EOJWY1m5PSXjrzCERoCGLSfl0TWwSrsuy5wagbPMV+znUuUu
7Zs2yVrGBMY0HddM+/FU9oUjf8tgyas5LA89IcmV3y6b58Y+/WLFcu/h7FxGygw14ELHGRcGF9kI
syRtXg8Hcyq7kiIrY5Kb7GJjA9XyqJOWMxYpizJLYmOjUdzLTMdZMEHA3uIJgB7ZsuiMXbi2jBIF
nBZEAqLziDw18CAiZnu5iBHjoCZe2P823faX1QsMgs7N+goOeTKEyclcQTbyV8Epxr7UTFx3UerQ
kg0/BI6Xtp3ievFR6ifr4OIPXnAqlEYy9LB1vE2d9dJa8PbLDDqOoXr3HyoUfrlkWkEqS0TcmPAU
ZgSbn8MDM8DAc5qHYUs7/Q+9lofwJKLDdFuDxDcR7tYrnsaamiVDYpIES29/jA5ZDzY/9w+7aks0
VJ9dWecHmSpNV8FWYILMZ5WubThBl8Jx7q/c3kmmdj5Z0CDFPw5+ZJtqItjVxHyfC3FE43AragEQ
InrovjI3MI4gnUmTuIsD5eUhJKDf1h8JY8CFeMHQ8h8jyK38EoQ+j7nQ2UrEP0VdHBJ9WH25gyvK
JPoMhSVlkecYhSI1iewyreij+6A9+mk4LB4CCtLai1xrp/rMON58Qq4MSJAoM/Wf2cDR/7UwVMpT
ROZgkCjUsPl76or2YSWgcrMzss/OTljXQn6dQgDdevdEN3uytQi7c7vor9etyKFa+X7VQh4ZlWhu
q0s5OMgCOC+oiOQA2QaDA7YzIE978fLS0whl72pshs2+nD3VKDDLqukXwBSu1qNL4NSnsXTkPkT4
yrSfsYgS6+tmKnRC1OK1NkIav3s9xkEsNycDa/nzkFw5iMmaj+/YoI6wXBi5PCWbogMlS4czLr6k
vzYRX+3sBrK/If7SMG5vk41fFqWOsq1ZoH5Gt3R4xTckJkeS/pBXfkdwvKjKYFNM9bZaBAN2XQGW
pQfL2jh1xfJ4SldT8k7ofGfO9xl46YAgVsaL1jKVFIPyGJ2nxc6xmCuiTje8+vrGmwwD5Kd5B9Nj
w6XTSrWxHh4c/0DIqxcloDih0AvIc4c8x1XlWcJmXNZg5UMb/o/5bviFASFkxOsmSHVL1c/n42ge
FpKWTDrof+LHatH+dgi4vMXq8Kimdpf0yEA4mGigeD8Q3BLf8cEjDuPvBsShdmRlF71NnSWg4rJP
CGQZ+C+ibSvRIqwR4zDd6+y+1asfCqV9KH5UJpEBMPsikUM3kk9kQ3Hw+LlkYwIERYWejdncNesv
iaEYPPqHUTcHG49oo2x0S9ZRPt8RABZsL5mKpxWISWvJz7gDbhAlmvOWISI9WiXLgo4gUYmxRezQ
tCQ7FTUilZ1w68hZQfuEdqsmSKHFG4ze10hm4ktQf9NEbR8qUOLg7tRHXH4m/4dOFnHQTpZ5+6Zu
GRg77kEMDtODKM3eMbzrC6CLcnSyf25kUUNgHVTSof8i+rEi4+H5denssaAJFZ04UG2z5egtYAgv
Eo3Hjwdcj3Y/9FheMVMbtvZxgcV4LOXDRh6lNfR3axUrUI4dz/y2x0NpBxHx81vxh4daE32hZ9o9
ZLnOjOHuewzB+gFdrAbqktxgFtua5f77//Vp4j+1ggvZLPKddOJa9fgRJyuNbgbdwpCiQXpZ9onX
MrsHS/GxpnBUqiaVDir1NV7MWbJ2uLftTaJmtH4kOewaKQ4sygamnl9MUDIGvrUrKsBGbPjG/oKH
0uPnE+HFlb57TTj+N6LYXSC9W2IkD70WzB/EqLRPkM5K5YLlvknWrmUyk9SigfPjoX4M4pDKXNhO
GKB+PSMg+s12LG4/pjAaSTKQT/J67MOnhHqxZgzmwmRCXr4IkmONwXBNKEXpNxtVXRVpzDxay9yK
/3Diuf1nlPqNSg9Y/UvwmInwH50ai7wK06W4DTteMAlHG1zCXgvFAJJO6/g/Ls4cs/2ftN1BAL+S
Oc3gJzAfQ2CPi5EA15PzmH5EQNxKgC2S7Usj0tkvGLP0Ey57XJJ7bjiyEDdevb0s4E6cnV80tUav
szIde8Lv/OxMfhBnpJJ4DE8H0iwW5uZjEC9EQidelG2PDs90/Ic4u9plivZnoq5TQe88VVMCM7EX
1O6wbCa7UqJHW0BStkjZCvUesaNFuF+VaIklhMuKk8NL8YmQ20ha4wne24ficw9bu0cyxhIXvgX0
o9oFOUCbG3koI8rm4w7gO9Hn/o6zTCB5SU0L0vXyUCf5OCBRQYzjlRMGXj7yNyXgOECqN94VN4VB
9uxWtJdDDI1wJE0yuSIKdsl/HDu3nyXU5yEhpG56S/UTOuU24ZJ+Tk5HACK7tsWDEFD71jvb+ArJ
YHxFDXoUihMVGTP1A1JygDgLmgvi4xDq5yG+gDPnrahV8rdCpFOo1BV3gjwe6Zn+BBXAFHc2dgGI
YN+NYYKwBg5JUuBdbHbfc/DxJW/i1yBJ+CUIJDKvDg/jywB7SQpRrNQYVJ6MndK56ax/LNgLp4cN
ZH0ppxDbpGXsE3qdJpUiZ1dHCJsiOh7kSNl1SstedfrryVajRtJIN2yMXTgKMfl0ecB1y7dFB2OS
3OUkl5flJtp6k4IE8Um5gMD6WYMXP2zYNBegwWONpP8qhmHTenArbwUNGIA6Oh0ltmYbocFhvvmw
/z1SXxXzMmTykE6spqt4M7oK1yFKEr08qIQNYYVPpQ/JfojkKZ+fqQSMWN9bMWAG63iJrN6t00n1
G2UbSz24H1NYPxIQhUwPftCYWOJOYuSWkLvFxcHT5OBUEi1NtzFu+/UlZdC7eHSn/J184ptv6eh7
pC6AWKueR21SMavbcF5ExtrTBqVBGR4ue3NJWobcEd/OgM6G3GnzhyqiKWWbfuJAt6b9qC6dj8JD
W8/jgDmgkvKnRwRQsDf6mXRpSVOFcggFGJ9Uw4N4x+c72aYvgSwEAmE0ysCMuaOrQzgqFcvGstAs
VpGpIRN3gdSkTwMcuq+xWLDUuof6r5a30IX22JfF+TfregCguoPaydu0fhFD3Q5gHROSIVDlrH/A
qtW+mZxv2HxmRkjsNQRRuMigscU5sacptdLqIcMJqQOVXCmvWxJhGo5P2yLrmMIiiZj+AJd+d1Cc
3dSqSIBPe1h4FGHMOG5ymxrqWMuMBZMxPhr5A1/YeaDiSD+ZE5F15wRrjp1dVAduVLH38duO5SbR
ehYZgP0BDblGNEG7AsJ/hMYKVMuuJVmU/8tSp5yuTReUtjBOXvM4vNIIk1D9Tz2wxtGGgPsDrzsw
FJCMnJCBpqH4SJOYKGPMvXFJNkOrHINAJPJs6Ga+RFOYDVHu8HIMELQABpD35AxHqL8WV3DzMRQg
dVgTjDXkexXLuUxo9NkileWwlIoe+rDMjbijgM93Ii9+XPOpPTUsojFMVImuOsUi8b/YOYnmHN1W
/eWFyatkqnzLyfdrYcR/mVpdpMVXHWatVrm0cTm7gjiJnPiMLeDtT5dMOjRl6eN83kuiX8dCJkX6
0UMR/yzFoMN8IkptUEbEtN20KpiPY43h3pbd/ojOH26vInvAz5gvT4iHGdXV/KPGdpFLkxXD/pOT
iWIl33i7zCjoQ4mD1O9uw0lGHDmS2PVEjhhbLgOBFj8nQbh3PjKaP+b98rSBiHTbCTSA7qux1/lr
dN2ntOvYa9lfD8ZG5iCqJBcE9f1VX1DyzX9gEvgl1vZLytHbdQECmKVNd6OL9lbA9h7tcFhRsu0n
xe7IWF1jjhj6EeAP9e/h1tI4hOnJ6HhTthLLkcT10rIW0h3zSKXbTzstg6nVOuPX+fhoC+2hIeK1
t7MjavroLffhdSeADcMKXXR9RvL5K9GIjxH7I6nWn+T9gNi5SIGx+NIgYSbWcq39ywMswCgC1Tbh
1rwyDTGRRPIPcSEDAkJmIqHdCQ7AQ9DVLUj0+XNJe9Y8vqgE3h5X1du0iyFQIjqPs2i8NhBTBEwv
eZwle9aBA4Oz3GsJHEeFzJHTc+OcDcKqUfdy1e+Axc+ypAB/Z0JTKQoFyoIA6dJTC3oBbsRDG8e0
Cww54hQ+6/ALmnZIUbJePcmGTb/aP/Vz3TBWOIrdK6vUpQ2nU5gfbvmS/dZqXNzaLY5zoc9WRNr8
jaHtm6WxDO/k7wChBTWfuLSCaLvnsXcrM6jEu9wCHnk1668MeMBF2XY8dVC6/OB21SuCHatdT9Wg
sUd8LVgbm+U/Zebphi7rRz15ntxeCAxtLegQyRjFY2ALQGmN1WIX9C04BPTGzyCSX4BPxN5N0p8X
hunnnVkBBBZqoO11E69Z+kM+UXGzaXiQQ059b/R0/zThf718M9YibbZsdkmFxUEDQcheuxub2FV9
C32qKoOI+rVFaLC5HymZX2zrWU2cO9Z5QqUABlTYUE70jhvKCYEIBBFjE3fkGk6aNIRNZJ+yn8eF
2XmxpGKSOm0z+H9ZRiSVSVGS+LKIvHYI6dflxZ56VbcnxIJgAbGVXVdci7sDZXABYz+rbLqujs8D
CWn3JvAAMWCs+KSJHquMmbRAKJyXQzIh0d5XuYcli69UaDPvb5h2HkAXRJ/KfZriVovXRO/CZdHp
oa6qpL5NJzFFxzCTRF7T50nlcyM79r17Tz1vFcxmzJ9QdcF07spknoncEkpv++uv2k6eHR6OqXt3
si937LwMm9QQ/1VYCRMe6Mep7Gsohy2qpPW1RnfjVEQR1zYlqM8b0v5X4PEp6XtGpPcCI6lhwLNI
Xkrzm5ymudcjA8LXytuvGXrC/ACiRRRbMk8NHXbL5OEWsk3nOGrvS1y0H7sX2nf5Lib+PTED4JYZ
7UhPHaWpEYnzyUNhrkr7R+8ltzT8Jcen0vfgxjQsOA5KsJVikzT5AQ84ys3h5t17TJli8VQo402W
jvw/dBedyx/l8bBGohNBJb8EBYPOzRugmG6z/LVrrt8f0wfzdgjm02E90JvgEjBr/cqCWwSI/yZl
HEvHdatU2240/zIw4agTydkOHPsCUfe/TF82DCtbGBe7fhuf9f39s6tTO1WLcZODixSx44K9IFBX
Vx9WqJg3Ow2/mN086hyLoN2968yTWhPZN6gWz0r6Awr225U5+lds2cJgcRTE0EawdaiQti6NxVQj
+eRIk+sopRDN/KrrmR1NLBCzznh40chOil4zbeUB6Sn2Rmhrc45ry48+woJbGFwfBvlnxjVzFI7f
ah5lzyblowHwEMBDDh6ie5P+GToLED+r32WGhseef6sz9Ust01hnHWocoCk9bMpcmqmQxM3iT+2J
x+rSxHyZTFsbB80Dn7cJo8MdySlEPkBYQMPCUuLuPWvOz00qTD7GIeJ/N9xsVeIYey5ykuyTf7X3
B3pFebPzyPEQjPpvBq9IVBdKD2mqo2MqBE5sZRfdSsjelEj6JVfJY5dfeFEWrMi2dYZ8EolSCeMH
5h54lD+ulBfEQfmBDC35sOLMLzgg3rtEm596nyX9xQJgcSmUJWdgZ6xDl9PGHTLQtWOh4xsM87/K
OyA4uktqDmtUISGEDDtSw3vv6mPdg3YBJCpS2lnA3jVnFa4EI0cVkCGAb/p3nHIA7swYrAmEAotq
pKIx/feiYEgy08at1WNFxs+GsevWdUajtj6wf/Pqm800PrY663bJqISzh0/21fBfGp7Ymveg8a0P
N4cfvIg48LBjLRwBofmOwCxgxo3WJLlEd+DPjDIDqeVq98C82ttSu7478BhcJQCdLaef1naBQChF
KNVB9IGP8c+N7jIz5q9x57NzZCcq32Sdpmi01Vxp4E7YpXPylJxgpxU3ZNYCnxqIc2k8ipUKSXGL
Ei8QX6WhmUCHRqnz/ZemvTstomX6k43U3TkinfDwIRpoedeH8ONU8MqUkNzy11ewdFIMqNPJ4dtP
ffJrKhBI1/9i8k8+6qKmHAo4MeMlH1epiLsW5UYXJisqOw95TCr+kscVtU8aaCJ/ySsiDqbhX+l8
EaCwUGhwz1T/VSQtwzKDUAlQHje2ZwCQrSZqUNzKEtUhaim/OoE+bsdqfMO0wychvfTi1/iQTHzu
sOv0tN4IhqM3RPpxMHf+iVWe3AiwZHdwu9EZd2qMRGgy60w9BySud6ZYmpB5DOvkzItLUEIf3Qm+
kQcwYh3LIxTaoC8QipO9NSs8fGz62uvCq1Q76ilifhuX65AGwzsZBs908aairgACl+410S2bwsWo
YQTJ/Kp5cUdPm3v19Jgs1OLYM7d11F9aiXONG90Q8Dvrc3ffYfUEVdjL3zqhApgiYLNjwQDDvvqb
KoJhFbb82nBuqY3s3P2i8PbiSN8fbX65b/GPSP2phfDj6Y5+sJmIBtp15Oj8Vhusg3cYtcj/596h
cyvYe+0WtX5pauoP+TWaqTlBSrZiAHZh1A/Sc4VoXA5goY7ZuS79kK2M1FTQW8OBjTYWBL+sfCk+
N7gXA0w3RnozTiUNaT+f3SQcCdHBG8YO9bCE0xT84JvOXgE1J7Ny7QGUbXq/ba/fV/14DK9BINe+
5MJZa6GL2eTDsjeBsRcu32WCeLPFAPJIUQlMWj76JtW3tZ3huygGq08A/0f5DS2cdYB+XoRbdC0X
Hxq1q07hPHfyZmIkCUH7HXf0Pyxm+7VHixFDLPgodcVoZ7bdsWJBU+w0a8DZaB7rWCJAMlH8rj+L
yz2UI8mgydUz0EeA76Sc67pc5GcT/gBV3jmju2oKBLucLnDNK7muXKcCmfboB6xdiu0xxvNpPbHn
eb7uhclsg9vKO7cKTUnuJMXrYUGM75+tY65ebNWqus6HzBLc6xPZ6ILawujz3oKa6SmOjsMP2/oS
6MPFDDwrZ6nXufR02MdORugN8K9MruUEZx6OGXOD0I2/2Kb/cEyp5uj1T04dBrtZrXDaTehB1ztc
Nulx/e8YwUp+GI0O8l2+vFCXzmR2Hw/PWMKFsEq4yQtg30olf0vXumpyOGuUQWWbq6mccYaVvna4
cUgan7yhyqnHEg7tQ2sasAwfxS/hOpGN6HDBnl4Hi4x376iNMH0CmcUarcEOBVhuveyJURttrrLq
9v+E4MT23Dc42//3VZb/npSSbxTtVo9KngZ3EZmSrYKP0U/GZWOpaqO40Nq7SUYS8a2uKhc4kkcG
TWwa55EpMSRC1xHX1uTGqARgRpJFNWR9FYN1zaAxIc70z0YEaGNIJ79+eEziSDLvsErtiJzxK4/1
ZWTe0bvfEyx1mZy9XVbS5Cc5kHk/8/edjILY4Wa55EnDG7oF2X0Yrc8JbHA4DixlKAdbebbzpha8
McGqdkuy39LEunGHTiY0zZKhcppiu/Qi30st/S5G9W3wy0iOWuthVSSJtXPOYzluq22BH9E7Th9G
IAgqI6hzLouyti86+VGhE1kImV9kSP/VRHSuL1la3HTfSZn8/F93Ql4F8RzgYzD9OALlKoa/Ykqj
Zxz6h0SBg+xmmR5XMTuZohuVJcG3mK3f5RZM2/1YI9tN8LAqIrRwjO1/QJ/9AEeAzOh7vOzReWkP
E3xbYkNq0l6t5vNkAzE+cb+IFBWCIUKaBDxnRzmWgYh35zPuf98ABi5tYQSSnB1jWYTOAgV6nTkL
wctlLvYYQ3JSfutAXydtSDx+C7EY48Zz+nmZpTVbcBvwuubbL9jogDfOjnrtMYsNq6nckMnhC2P1
lScJl95vEilqM9Fh4cUi9XeCNi1YMw8aGJhr94/TItJtHtGzm2O/lqHxC2GKI1v1KCy9aalIjzrh
9I5TQIifJdxiNmnQW28AYYR1suZkPxU4+W1AJuUJpyMZUTsZWwL8IRAOh7JiKCDBxVREM8rreLU8
K9sAsdEjnPnroLNxxuWgGwDSJb9yh0E+2RJSql/kxG3+KN8obcFKp71+1WRpxDNBwz/xBSIDb9Hm
5u6RMvJuNzSwbV/ckj7x+KCzrt9r2pdopvD0fjObQHUXSCUUMTtgBKwzM8N1Os8qZ5HKNMeOtfny
/lcjr5OXMT4vNWz3R/M4m7GfwCJ8KSFlTvauY9SI1fXa9tNj2HJgu6HckIdW4ekDh7OMvoFCZt1W
41ys2agfc4XkkMXfqe4eWyTw1dmpp2wQUEuR5HKgkiCxJiZSa5xNaDZ6p+vuZzkJiIga3yNOK6To
kiUlyqz9KkxBnZkTIYyLlBIhY0p8ohGMQVyGYn0z6E/rq8fzej2lJeaOcMHXmU1p0FsLsPn/MtX2
zcwWwZJFyV9fJIng5ZydHnyKQWbuRl7A6IimjzGToou7qk7a/KGLrE66t4fl3bXzMZ1/cA0zpaCo
neqm8RK1SiFLfdKHwwRbb6sLypgUzGdI1ANqFqFUzVhhTFjEIpPnaS8GS45gTCWnrBjalUq78yyE
9lB8wv2QC6LLzxxIexTPRbTkrjnrKc/FJsFv8L3COEk8XfsZOyhQGLtjZP9d4yVe34g4uXzzb7PY
Otqyb5Sy26csFNJ6VlRIxTWIw95LPCEiJADzUBHwxai3RXzLgXIo5EkknI9v14p0aJw8XxM9+h4a
zsHL93eEHhGxyYaF3MoV8K7vacrsdFhUuh+91+1GdHbkl16ARf/kQ56IA7jNxxXmLKU3e6zFy++Y
+552sBUrWjGLdKpMtPx08KMXWtqjBt4xE+gtRchRDc3EtOEjg3LnEx9yhN6z0JcPIjfJ9TDFPvy9
FThsetirDsGpOTzYjMS5l4VBa4EX+aUixMA2Co/44HwAqc16IJC+kzQcBI1aud1uXdx/tYYT85JI
2C6BxtFXzOfIO87vhuOI5wx0wHIB4rlnnZ5ue2sobtiTg8qEXDx5Mec8Iatm0LjCEY+gDP6X4gFO
oPGcJC9kqtoCJmsqwpGHC03nhIietX3xLzqRCdihMroesNE0q/iK74kuFX8pXGNJzYP6mT/30wEP
fIjln/1cVrEggxRBRAxaYFl6+tiv7e0Uant2WJXyHOUUxJmIiG10WOdkQAsT4Cq0FPM8kgu+RT6U
SHNrUs/THYo/ASz7xDAode6HwLuRpz2F8vnrROkoDlBgyrDgTcnKZRGB9Cl0eiA9XgvZCdUttVv/
cgQsyc0OYxBNKQPIy5K7ed0YTtDsZpdfqrH2CKCv5jumwIrE4nNkKF/c/X/6anVAcfLOZvpL0UsE
HMcY+tD0rO+syxmbOwovf8hXGbZrf9NCbsaFTkocy9jn9q8NFuPxnE/QpMwDoHgYNNOzaoIlMc1C
+W5PpS+msKrZcjVZMKfrIhm81FvC/Qx9InYZPfweOaY7CWu1FLH767du4wG2vtarOgId0Ou6iryV
3L+GiaQLxORdqDCW0hlDjsG/3hIsJTab90Y+JzSpUe6qnz+QRfFnXOL6nxqmvhKzuUmuhNaR0K3K
4wj5fmN3TeATuspVVg3+7KfIcOR4eHXs5fw1mIROpv61UTcYz3SVI6rJAN7SIhk+yihZVCxC4TCn
XbYNTDUqcRHg1Ip6Xmd/rF+eQz+f+h52wfB0tyhemcTMywXchmsqUIjpr5mHqYlxibxNQ0Qi2He6
6u1O5Z4JmKHsTEv5ebEU81M+vkNFUfkHxDZcaNMzNf/8RvkHv8DPbEgpfkJ0qOxGVz5SSMeS4XfM
GfRK5lIoZdbj/5JWmt17iocWjB93uoRXL/KzM+DOUj4OBYkfFEFBVedgUnPDXBQ+WGlBJvO5OtFd
fKStmrvFLJgjwzY91X48yN3N0YFHSNaxaouv1T5C6wtmq2aICXX0qj80RU4/nwIT/dMu4VFMTh+s
U4gwH1tQ5ZJSBxjUgNCYTPuu7o2vhe8Out1WNA6v3obfnZ9h+ZBh2ZhO4dtR0VkqsH+Sl10c44cP
jHjoMSVuSLtjJOnYiUx++GSYw/+ty8KbXoe+yjzp5r7Nr0319eQ0bjrmpIAh7SzCmqAxKTQOb5jS
fO8ca44y0kBB/ha7IEwH+HWbuDUJDmbWfhOlJmoJKUOZA9cvz5Jf0Enr6qk/ECiDWKCr9gRJQ+S4
lz4HSeJSBUPnMyRTBEu1cm1G5OWQyW42jQOrXxE7d1fxAePlC+/wYaWDa5AAkUbU5Qa4mrybGn86
Ip6ZpyOarN0gAWYL88Zm2zYJmaQf2X3h39eUts/rB9Z7eG4jKOt8tBaawymaknklaQckQ0TRMmEU
8u6nOz8NcvknAetWwJmMVJH+WSPol0WF8tegqMHLCHsiLM8ry1TGEwQjU+RxsJWHY/LTZUmxoZnz
1PcegznxeiKTSpdxBe1yBleED2Jb5uzi4ggFSEuUUdPoJuuzH37Wu3GrA7m+AlovJNcvgHUoF7Tx
25vt/TDPJ3QCQ3z86h2fk6CaAi7OjSX5UqXhbNzMHafjOZjhdBwBrWsP2DVDcINjJ/OBBzuYXCTz
UwqfbSlId4zz6wkGoaRbqGXSCMEzUbPkpFkmkbt9DtJ9TwUYEbzrTUfXgBSJVjUWye6CyJo8MQW6
XkRGbt1jqm+Rh2yodBQH1/JEx95bUtU08EABEdzyN+NHWIHqEtPi9vPyGWJtsTg8/7g+vyFFbXtc
zmdncc+FJumtLmunn+QNXS2iFuNe3LBvoifm21jblfiLZArs51ggE9Z2mP+fHM0Jh3IzuNsbT7+Q
UoYM5HO2uIvIrgw0YOZ6KOUSSbCLxVxL6h3YrJnLMxGmqjSdhSt0UV4gHonxS2SP28E9pd0hx454
cckUM/MOd0A9MLsHq4lnpQclbGE9gpiCUuJR6daV81P2XNrTz1WF+s2omGAzXDBZTijQlxWzOUlU
A6OIx/moPGz0UIYJ1JwydK7PrKxCgLqix1ADssuWSBA0sFG3DAXQi1NVlVxwo2G6vyhTNlult4qo
gurBu0qBRWfnLwFTYiilHdWRt8OVX4ldeRatbTyeTrWZY1SI9LE9ajcicOi8fvWXCgd2u2fCpyrP
YgyQjBaAOk2br1LlSnMFo6v7CBBjKDfROhSpOlgMqHWSD7yomg/aotDYcLTNfja01VH/cJ83pgmF
SMF9cN7MOee502v7iTTh1djq+MDxjJu7hYW3DWZMu/EFGHHDkdIdgVMmzcsyXO4uVzGYmpgqC+ti
EwFLgjK38AImEu0UYrORFOxQTMRfMZQSbgwPlmsWGfD7raaXM8xpcRSCuaE1ZAhdrX6GO/Ktw84E
osDNVh1J5UnezLaBAXxrYn2K6Y9kSkosls/hy6wqKgPb9k86rRYjnZNNxL0VfnRK5CV6s2MW+BhG
/ETkCMrAEfyOwlRXgElTyzjvI1ZVE3eEPFC+xdKfa4TOz33Bogeljv65DzjcHAQMchqSWXAU0ao9
CXjsS3pbA6wiXWlj4Px6BXEdbyGG5QNz9ba7EMGDQJhPLeVGQWhG6D1cZr7Cbc5d5ORxX9jc8FAk
4Vvu/BuMk+Qjt4ofNZ5WdryjTyM9SKg5F698dH3V9nLTWFqtkrFBNCfODMODkQ23JleBBAiJCm5h
paIBxVuGlx+DMwAL6Ay/dmTgS2Wc21V5CLJBqC5xVLI6d8JxJMK+G5fsmO6OkyXXYq5E+qLMDOgC
1N/AVhTXtF4txVvfrhlOmRppzgIM2Do0VRAUfAIv6NYnyaaZJOElM5jnBQpL2mwFCspX/7PjVUOe
iqeoBM7WalrS87hu95PgLpaBK+5MTl7hOCH0OdmybMuGVwl6pkQrS2j82b/0WfqmVbRoHkLUQNtT
PKilzsBHr/Uqi1olzDsl5e/JxtwgZpb6Ar9LHQDQsfrxAd8WceiReH5jalnsziLWXHTmggTmfkRm
wdXEJPIqd8n1LIjRIDkIGffB/9Q4O4jqsNLwwcWH/jIjC2Ozt7HYUvnVEDKHcUTEmzqdnTxlwbYF
qcS0WuEhVGQUZ7pRaapvZ+uYQeVjKO6IEWL2H608/Cn+05pEVgIlHQxFOqkfdHtPceNMpygvx/Sb
uFVvFgpkMYFi/2WfnqJPIidZ/qPq+lxTo03oGeV874EEYjYGTLYCSqdLH8x7FfGynEKZaRBkgk9I
k0sf6dxtzHambo0nZnOwnazkCkrpAAYAlp4hiZWEVUsBn8rVqkCAX2oNN/jKWX91ym4nhepLLIO0
AWIgjCgmNRtK8RSuFqs5FD3rpfb1BPL2hnxl4dPiAIzwYVOY4DhVnTO4X47V+1u6EvX/ZmpNooqc
iN2rMuSQpDxzk6cvcT/1zpLmcKS6wZx1BDCmA5FWRC1dKXrmAQBsbqhp4ezVdTti0NxjXqWQ6UUN
XQxWTYkqmcIl8YYjUL6ltxCWl0JQ4yfPa8L4bNEIvoXjZMIR5bDa5hgV3bfFWLOxGOHQe7g3A+U4
wOqrtP7Gum+i2fXkXFxQmWMVAV0yy3Oz9N7+R9rgtDNLrOiZUlQIbq0SyyJsiPS6RwD9fN7niOHs
cA0zmK8OfVdWjx27/99LY6GAxMhyFynA1WPWYVjeVwgm4gFlnidt1EOJB+v6QU8J7zpO5aKtzp/l
QMe+MjXLVCJ5VL3sOshbUZRRFF0/DEVXZzYHAlxxamx+tAB/b9HXMW26EQxaaZKBPpKhiMLaGPno
dELNT/N98Iz2G3DH6746KQSLPA7GUz3h3NRaMoXFjhqErVZYa1Bjf+kJvK6LIYkWEnmrmDM8Nm1F
Oiz/sOiowL9kmwzYRx+Fr0hOLBx65CimLWvhJQHXHkNimeCRNqAfgnEQ2bvU1zTvx8hPS5Poj2HL
w0NweVIKxnN1jF5+IgtutBTZH5oLmzPS3yyVDK8/kyu5fPwOuhsWVjxtOnbImKjeSUhx8Op0p7kp
sdFthI54zIXvy+5X5GMRNT7Qw79ty+r19p70wD3iWSIftY2nyBzXKQIfTWirTipHLolG60plH5fR
9eoOvOLlki5yOQPp+izCk9eee96jM9DguFNdCQPhiavy3T3zjnjmYI0hVhzSqg0xE1XKsmLVye1g
6tzR5Wnz+iahruHsv/C9wTLiYFBjDksxOnkSNvykYBHCC0KiXAx+t1MJ/Ev5NWPIxpjpV/s/hQIo
zzaYip2eYye/KIsTmVdGnQCL8fHzyOulLbWhi/3Oxf+6t7ptNZXwTakS+eWhw8svEQ8f96vQ4y5t
evn3nVi8wVGcUqUNj6PCZ3vMHLiH83ZLOsQBH1sYdqb02GF8fnSG9VljJMgNp1ZYevGMao7yDo9Q
ccG1+PlVrloCVTwnQVPpgEpq7BoR2PZJQDzb2O6eIWaMWWA9Xx6fKcR4DsOqxkwKs+ReUwI6O/fs
ijPyHtnh+Bp3t4UE+m/QBI7nU6F7/SrsrH+uBAt4P9z1+xHkngssVloCDOHj16AqZ3IHecVrETGG
cP3U7FhkBynxrMtj1vc9S/iolVSX5z/fOg2dp4ZZpET1gzqTHOM7N5XCAmLdGpjl0F11W2AdfTjt
Cral/lwuZ7SNsPFMlCc5FkRkvFM0Tkihfeu2BnHp0iYlpUAZSFUKty3TBpWd3o6PxLCOgs/uwShj
ZNFqdFQ7HDl9wV3o8P8aUT+FNos0+BMEjjW1okFdaRDHoaaLNQJ/ofS5hPMkEVP3ILv1tB5lF0MD
mfTA/cwfnMxE8TD8z2f4HWVzySYiNButrnzUbIkxgVJnTLpqCLDsJLnMkM0zwk1Cw38ZOHMo45Q/
YlbvZ8M4nXsB54mOzQkIg7qCsQeqmjn1f2ANFIisM65oz9vpjRnAXWksX4dyFw+Oq55NxPwX9BZR
QiGHtATOalQfdgUKBQZ9lB8qHHnLrNXsdLdEcyUGF/ocDFGojWq3NEZIyaQcsr+utuJiv2f5hta8
EeIpZPopmeFv/34DMEiwA17Sll3lXc2tDOVdk54wlvUlqyr6TbRqhtLFlZ8BBkP5FxaDzjEIvTm2
5kMxs7Mt2ceOU1Ah47lGmDheBg6lvu8GJte+0vXYYo5eOz0dSr7/6XvN70gRYFTNaDwJf8UrMoz4
Q6sxX6bECoS3GHJ6CkqMC9c46tITTVu5YCaOJhHNS2zYWGbAesRJpUF7Hq9PiwtrNVuF6+wjV9ji
udXhCOZP7kWPoYX/hwlayivec2NIudjYc1hgo/wYWF2xvxjBMF+iOs+AgKAeYpnkMLCgUmKMHF8/
rBYebAdQxtq0rTzves5N0f2HYiS3JzZoXYAPoU3JYHk4opFtBAV/dxA0OVYxgNNvyZqmTXr581b/
Qj7KTDElST+F5fgsVIeKTKnKSb5xjUJ+T/xKYgiJAFbKlF64+uu9I8nXaX4ePd+ObOrTDaLKkKJ3
keWVTyfi65cHihSR6IwePrgrBe1dmNuiLAnpTGOcrdQdUodhEjF6VePvp9mrY2keTjnFsoOIg/17
qNmI6x6o22E4VyBfFzlWm9m2fThsgfAsf3iexY3S0Y5cONVydBSWQp05zKV+3KV5vy0dPVs+ojCn
HTu7dOk19qn4HMK/x5GEMgMTENfxuCo+rNe35JX2M+DIS5SF7E6J2mrO69pmijw9Y0BqTw4FVX46
KpjuIu2mgspxtOKLw57wp61KoXWqT2+PtIuscBxap4TjOIk1tDuJsfMdyVuznfiy2QDrPTCbiMyd
mYUlkcW1DGeyNpHrnbF87i1EFPVEUU0p658ABcjcmXb4pNNylzUh0ZkOcFAtDNnBjioh+DLUu7IU
OKGoQpZvdZ6WYtsxW6/HmbCzBbKzSVPD5RfxttzhIqr683Lo1/UZ3TzEpc5mAsPgb5KYxPlKKsE9
DfMNDb/QJZohj0ICJYVjPAXw1xe/IGEuiuX8uf8Cg1xgONw7kh1MHC9gYu7WrHnUi7OlmG80yA/a
y3w9fSx7wPHHQTlLvh9zuFTXVuzIEWnfKD/CgjxdH85Gtnw838rDSTGRNJNL9piQueX210FQfSXP
4B7ZgkzzTV7fXDF96ya3NnMn99PPY4+mw3ie9M97MTh1QfbQrncb/UioG3YnEmgfPI9imF1Phq7E
u3vyGEOlU+t3rmQU2g3AVoIebKwA7zNwo3w3yLLG3osNGDtJDe7yrlQXU0uC+36QQvbvEu6qX+b2
toogGDKsYfO7SScLt2LQ+8oKfrujWHhiIv24EFeZm7aCj8ffhCZxMm2awOeYO9N8GVDAXPuMu6Nj
ZOokAHxyHgYMnEj98pOTSQQemgW638pCt094D9aQXxdozCv6HRfu6C8pkca92Ho1hVZRhc7rhpmg
/m/VvP+RoPP8wfjJgs+kK+o9Gs08OnBvl/pQDkwZx1BsY+aohDHSNUMl82IDNaXugmsvbz4LsPU3
tmgZ77Kl9m4ilIV/+JdiaiWGKzXHaCww3SP90dZHsYag5m2GsH45+WwBAlChrT6cgdAg0MMMJwOJ
vC5zOrGTXyoHHUSUvxap5iTMsjurRK+gG7fTKdn8+aWhoPIW+vdG/E5gEC/LREFiqVfspSTUKIaU
4DX6zXU8zlFp2IPXTaSOArQ3rwKR7yrrDEUAQP9ysyYkF4E7GB8Ou7tAdJfv1u93LsW7EI4IMDm2
5rfWVveaN2TD5hhqdLuj11E3oLCAA6QISGys3j7YenuydcP74zHHpniJqd/3O3DKbNuPXcYowK6F
qp7VV6ruQSJpBcnRn/6eGiNG/GQaWEdzoC6+4oge3+pvz6vau3lNYBpXcKJBj1gIRHf6iz2xin+i
eswW7CqLELv1/Png7C94gcF6s9Lqg5yZm0Or34+hzwgJaxwslemPikgUlTjl3HC514fno8WyTtbZ
WfDMNtzCdg4+wcNfe2eLMI9h0NyQUsottYm8WSAtZjUx5iCUvuLxD/12dR6QCmZeQ9XWU5TGRp9M
2APMcI8OQqAIXBUEqfGslddfH6pAHlA0hV9DYblD5RJXpjtyfieoQVXk+m5HjvywHXBK9xXSNjXr
JuVJ5h0CmMwbXLyoM8Ge3ZPGIGJRX4PJCXksvNz1E30YQYLiOwQ0kBi31ffE2VW1FP2iDVxTIysn
/DZhhEdR84QX5owj736iE3GP6yxR4p04sAKDDn0T5aeGkWp6COkbFWijgu4I9VBFKztal8NRifjC
KP2VTTSxijS6+/bltExS7QRMDcp5d7oTJ45sQ0Up691BB2XY7UK1zuwn9VhFLKFmmb03PoN+4EK0
sSQ8WW/yyPsYsa51xmJbjbHKKwr4dVGT2+oINfTy3NC0gEayQlJi+vgCaID4fJrQ2QPm8GIbZK6g
NowVApn/ZEPETFsfYmU94Y2SmwxjTW2YclH33weTyVyC9UGToEi9/B/pHQOFOKd7GIt7x9LSXq7K
3kqVeYrgnHcwunS6u1Z6ZFEIN8RXX4HQ+UfFFDNBHKI9H+UygkFsDbgstCcdfJG/VkUy3MMsVC52
0LtmreWohgN28FCKPEUWYyxshmrN/BwT05NGL6+QG3Ryi6vLWt38VsXmKkfyz48AD+JCH7kbfZc5
FvWiCjUPOSo+bWDLyOEtmafkrXv0K1Bo9yBOYRqAQ8Byo2ZqRHc1oiPvyKnxtnv8nXJd22tueDfR
odgQivuRWEbrGii1kWHb8tmp1g9rUsMRGuRNJ48tGARRnC3DrQUG/jPV7426km7w2NssLmwz9RBL
FYp3CV2Phq+VpSFsly9AO+G9daOHpyVsl4dh2LKkdg60aNkprPuWRBzqrO+aD/AdNGTCyrTqS1Yk
DoS2665hNAUhKanraFvoD7ZvQ9ErWOfIV1QLZiRbED9RfPDzxdpHSl2qQwepCbhFkQTHz3JIUtV6
1vMvpFUM8DVy/hjukrm0/06fIHY/wpQ1fgBQLOYRXiQMU03X28bD54xfIWu3zTTd19SXNUyqTpdU
ML8NZgub/QUoqkM0ot1j/NsRUvoWx93cpzZI4Hw+fsladP4So517f5utHahNT9yLbN7S29WPsKpi
LIfEr3WmrKB6Bat4913C/OKtAvcX0MIRCuGXvpywCRP45Qzqs9df1y9EEQzpz6tIRJz53eVSzfo3
kA9aXF2yeV92A1DBSCz+welPk+UOLm2Vnohabs0qN/2KJeUfjLIXPSlMx7/JXHFf9IrSzpBWs3o5
GUMncm8m4qlRRORdHrpDXCn1Imfp+oedjeYoSrR8ryHOb1HF2IctzvLMMvHqDX1fieY/BEKgGtT/
SCc9zKMGCbJwgrpAluFhIQoohwsBKvW4LxFUodWx6sCjYkp8rXqi+HouIOObtZoyJrdwxPVYq/Gu
Psk1ThAI1ditjkk5QpKkSZlT4rYM+wULVeUBrvzQE3WeNbjdvXbgSLsdpDbdSpdHXvk+BMqztCCz
SkC9XYIBXlYA7vuYMNePY7FVlrf2WOpR2AnJ6rm9h9qKTkluUZrgqdClw8pxeMZJUR1EUN0BV5m+
7/IDMH+YiPgfB8VtTm3rm4mlHotMQpj0u/gkg71V1/3LMJpsfvOKxcHche33K+PDd6acEgjZ+07M
Y7xJTaLWL+W7h4FXifNeg4VveePmUqHsODbS8C4HC0hmr8nPz+t6g99j10JKL3EhQ43KUMbzv6LX
djqGvPdPygmRHAAoKJ7cyBDDIO7UTbwdg7Qk6EIqNlwBtoIgCw90FtgtTcAnzfeHSo0Y5lXXATDA
/+czEiVz4DTXJkodQaQ/szjZwDvFga6hk3403q5cGfFvVCVGdTIx9Tw2x7epXfAn44iHluWK2Ynt
zj+W56IyIWXKoBsFAl+FDtwl4IIVnuxjWC0Mz4lK5ZiV4wYhLLfAU2AcP+z2MT60JHjAblld4FI0
aQkrFJguo83KkFADHtuFYwLJNxfX6dCSfCsieWXW5TxbRLmz2GXcpdhKAcGxjP8O/wnnAin5K3j3
VgvOHYX3QUwklQoJGlGbcePLlbJkAbubVB0IzH3jV7NXA/J4GsdIwuwBJYAr9rkywUnJlLPJu3vq
+1Drybt5bzO2s67Dq1pi2XsD8JwNPxSureLnreo7EpOkzTdzbgTtp0YiQp7b64vLvg/gFPRKxPnq
3nsDrJiN9G89KswIS9a7KFOFWe6X6ZhfvLariKSvPdupYPHXwgT/FNwj4vVvEtq0WUjJe6/fVazp
up0AukcPFM1fDs8aGJSbzdttdhnZSJKE9LnUvwLmq9aIYjojm5/3sKs1+F8ExueacxjjGB+42bZw
NEOzgD1HYzJ8nrLRPbOsJo2mfOHQL6nDw3j1emjVM3oVuz4L6HlkQXrUZzhK83/1fm6BsViykGMT
dcRcc4EVffkzGpd5/HczZ4A1DIuwhnv2OXJ/SNWab9z0RCMuDxWeU/fhuiG2zKi9su2ov2HBbI4T
YoMuE79QbHoLlh/gjvW12C9MZgLbtNr/3vQoKvNFuYNmpUr8k5bRS2HPjmG9LMNlgfqYWw/qMnwv
Wf0sFI6pCm80t9D6GJeddTDvC6+fbOWvH9a+ai6Yy4OG/Ymp9ng27XCK2byk8f4LQ51VXQD//xYv
Rt2mhxw1unuoKpkkjj8LM8rPj6tl5TY28589JddhoiujhhSBgrKVMQYn5RC3Kl/rTDYhXtG5Fyqx
3wLcZu2r9JtLpTSJ1wiC9OgcGLlt7/7dhDueiUNk7fwlgYRHrCAP8y4G6011VehoDhwsxVYBmhEC
+S5x3wGU2jcojCg3iYhHud9SOuCMjdFOanrjwNhFta51wAj81mt+8OnlBtBVwYuS9FL7mbU0Ztka
OCPhKyPwTv/wwwSRu+pYSqFzK1T/MIgBuaRZBiWokA5E7AZ4bIx6ijFeawceKweRM/dXYGEGvJid
IQPsMZ3Jmr1/2e6NHCeDV+T6aSTHa9VMZ6x4tq/H+Yx3FTgeNQ/oShmKGwQzXRGNwxJRKmVgVbpt
wxXpoMiT1TBTIG7EFKW3agTVImbOMHBfFCVMfpjNgUm37TApbz4YzpAnAQQxHx6rXdOgBugApfgP
RaJRIyVelQ/0UXHTfcn0GACZGvrX0sfUT1VB7vUHSiUnZy4+vRfis8nwAOsiVIZYyL8c3Fk2VPc3
Yqe4Cm2zd6yvuXiCFQLk4SAawOgFLMeJKnUPTOtAYN0CqrckY4d7Eu7gnx92kOxi3emF9a6JOUNJ
H8Jm5892P9xh9M0DwNoKZSO2ysPAXMm5MW8A1WXx55OBEYYFFhabXDbVT4xvLxDh/NeLFVxmyGPr
fcwUtQOqYkv7DmuKD/o5+2CV2qCHwrdPmQ3I8G2+60AZ6klQEmt6r9QpzQEhIETr3my55jNfAj+5
kt2KtYfdUJGfwx6KMDjMDr7oM0yHw6kDgqeDQLMgXdwEL0btDVv5VDuO4pMZw48BXYGP4vh+ti+G
tg8k//JE9wJiVh2rMkgY5mBka8hk5dNj4dCMtmKqEOcWtVifeKQ9izyQ2jsQoJzfqMQlnRxzGc1H
3Vv0NmQnqj+j6lFOyERK+aUSvh6cQc0WBZwgyCF+kLILzsA0rBz9RhgYTujauJ6cL0REjf0RU8oQ
vlQqywqiJYeIK/aPQZ7vXzG2iWBCc15BniVqGJfimIMePq5KgZiORMyTRqzTr4O+2dk6rLCfYJkF
CQMBvTJZMOJ3nmOmAd0PRxA8NCtg/LJNyfkcQXK73eiNFmisnL/1L1Zx0z850EXaRbbXKbrO5I1z
gGJmCmfdBE8U386b1zxCSp7O6LosKG4BQt/FDaRZXPe9nV+aYrYlMub0SJiHjpt/jklj2G1eWFsv
MDCOyYvhzTQhmHdv05g0KR1JvylkoVTeiQ95E5S3MUIgzr44cYzJ/JiYcQLyVmJgTxvj9RT5Uzgi
Lxzfo0OvbKbjgPvAHF55nxdxWyiKFPjoOMB6pqKKMoH3p5zulkV3Tf2aH0wteS9XBZQYt0lsNE36
SIgK5ylH4q08zJRgRSxbreRAlVhagJR2UFmqIH0GSAacasEV2TzvlhNfhNmMy2hi5GoPPKc3KooG
H8C5WLFNiXQutN100W0B81SCl66nxQ969suyb3WFdtXWSCdnobgxKxrlCqJ1lR2+s1Rvm4iab0z3
/S05SebeaIagvLjoCNttZ2DW2A4EATH7i/IqSnb+g49UzHM0D3FL0LpTbxZzWrmR8TJrQHhrxkXS
YzOIeIY6ye3jpNBSQxuh00F17JzaC7P6Lkf5yR30KRyGWE2dY9KDM/ITlWaH7XA9V1uHrKGOzEmN
Fgbd7wNnBXJwUVv6q+lgR/iX9eMBOrgAcb3LUqB1Myf7Vs9yWVbxWZo3zV++A3UpAGliICRTQaU3
hzygoawON0T3+knrhAVSdfHFYFUQm22ejE6F0ub9u3kwcHjtrnqayhSCJjursnfTfCc5YdtyJKKh
4Sx3vqPhR0/xxYOj83C0fV2aNBUFJUU9/FqpPqZPbus3qc+c14hzI+Xnt4ikCtuSm4FgoyezWa4i
nfK76QPuG1OinNdmiYI3fX5JuB4b6KU5Xqkd7FgupcGHUe981/Uuiv1Z6vDLA/BiX7+91Iv1ILsu
vyLMOvnbJL8U2MXueKilkT4OTPtf7dGd44QGyK50QIh4qZnaqKofcMDv6p8AvyyD/oPs9hPpupUL
Dzvgtyb/vW0CO4RrSwpjqo3N8XAPVxhQpdqCBnOLrJW+L7/Si8vbBWiPMSdOUV1rX5mkgKdRmW0X
bTFWfYhDBPQ58Zty/FGOQYhmLZJWIy2SHVKCAhHcHrL/8ZC+9k8CvfJ8VAao1lVp/BVxwBEfxWrX
3r2AHlPjTl0atSTMM6GvUcIkOaiKl2dCDZLe4x88khRDIfiG6yjiboH9+ZFB7ceLBdx+s2c9ZaxH
pCxcvu5xzcLh6SH87WVNRLeA5YBvRIt56VKaxneYUeZK/Ku+/nDqsrb7uxYXatt/YwnJZgOzit7c
cwtRK7g/FXNXvS2uQTKUsltq6GDIDi20jSCRQKOCCbYtMzGeWMRKSUN6uvyrXMQ4ZRFHSANPBms3
qz9Ay/eCFeYCfmcolhzkFisYH5d9t8uoObpmsbmCo8WDqdGKVkSz5dlvUpZLdP9srhwNCzgWyxAK
I1czYcznNST/hh9MgAkM+an7PzBScvPsV3DWpgP7Zrd3PA+WSHh00Z2uTG/ApooJsCRoRghxJnOF
IV6F07hdH6DuFMsCOChiYjFmzl39RXCTfDOoQ7w5sQ6ltmBYZVtDZ7Cn1PAAf8Y8mDOGPC2LgC5F
7M27ecM7kujRShICYgscPpfdf875CFDWAhvNyX+JvNqkNmB3JQegeV4RtBH3mccrnE+xz0Ca7hXA
SbavSsNkYwKXHjVGFJgdnriodXYmCohBe5WUuEwYeBPbvIP0sLzxfikFRAATdUQ9pv6ZZNHSk8ww
icpPXlLDrUKMGkevjYP6+NsLk78KnfIXGtzrYYCbyEj5WZhP68jwCSggQI+MGHOyxz+YSy/+DUjf
oy7l/TNhpYUsIbWdpNBUj3c5mDGA82gIE6EHG6fIw0QjQCMpr6GbJkw+rHpWmVhpXx5W9qIahPxw
kw8MdBhZ721aBF0cTagId06NIkOeh5T+HQY10wIV6yd0SvJSLnvhO5sANY3fJApmf9uP20C9PnF6
x5NrPSi2/Ou8oQ3L6s4k2nngS8pslz7L3LIw0bvPVD5+83K0Icn3aQLvAcqcCT+0RWBnF3Gz706U
KZC+fzKsbqCENfaxzr9LpM64X6apHmzDkzXjo187Hp6EEgVLidwp8BIARLB59E1Z4n4Xly5OnjL9
IHO+AmReV7hJAl8JwFyokq1quQS81N1J4BqXPigE18RjXUdvVwyLr7AUinvntrT89Nkdp3eH0yLn
dgyJ0ncabZediH5QbxSEkNkae90k2pbEK85vYX48/jX7WWDp5+/dznbXNSwFNqDZU/dIQfzaiNYc
v65r+EQmJ5guiHWDKcXu+b9swGHey+D/CJ9Y/IAbQwooJwPmlBhPN5kSu8gz6hDAPlwE/ZDASuE9
0Fv+MVehhcUZwP8/svofseLFMYS3ZlSDZ/JeCmV/hXNLxEUygrT5DsWc+DDlMZtNlsOX3AoRPUpG
IzkYOFq9xcPu0pxXoEshceWpaalaGro3AzIeMkutYCGqMD5K5TZ43GI8a47fa2znHlpYx9e5VrmW
4jvdf/hTIrKPbEYkp5nyWdV8+owtDMD7XLs5dtfM616zDf0xjxOivTo5HAyqu8QL8ggbPy/HeWvn
4MrLmtvGD3SFc4Lt/K/NT5MP/ePB+i1qa3oJptou+rAL3udWnKBoUMMo9Oti5x/TuvzzbhbSYGxQ
4MZKsboed0WgiEAouHgAPadPqA6QEq840fABLI4ZcA5fA82iDwevUZmoC6XX9WLm1zt7jN70GTtS
z2XXtqmJ1xapM6sb3/h8cRiDRM6Hy1mAvzZFA0IFLjYLnz+EZuw6fNX2o+ohYGHGQCGbuhVZsLab
mxcDw4v+EbqmJXysgBHqI++fwrMqN767aLgx/QJuZHk9mGDFLzBoPWm6wam/D+e4thyXMWSikknz
x7sNvkU4+7Fh8auVuLd8q5II2jaCcbSxM0nZw9lJp59qZv67LJyUT6jvGHw+brDXNz/BX9RCmA/q
dyU5/wUbEfz2TKA7BuM+nayyxcLiCWvYe9D+fdCo9e1KqRR36MyuxBWHzIlk9jhPMPnd0iYkQfgG
bD0KI52FU0P9HSjUYZUNl2rxY87O6dnIxlCqVyX8iX2Z7D0G+TpFx/rWZU0xYjf40ZjS79a1H1fj
/7D6dRb5qO47hZaB6Cn1pP837BaoKDY2x5F9D1QQFSysphoSCZVCBZBS6JtSo+QdYKXEizzVL2uC
wR1SFEF/OMnqhJBylWaIp57024OXmNDhMGOIzgpD20ojBxnFUJHIHUQaR/xImO7m4MH+gX8lV07w
T56Woho55aNblo2PUO+YgcZHXa3qIf+CfD+h0DXG22nPtTVMZjpzkimpvWaYl7T06YsfYdxTqPl9
8aqrtgqjZfoILwQL4xNjR1QjZYr+KM0YuxGGljSraFfjPV9ATRUvA3JGGYy3g6DOewFbGkEA8fic
8In8MKG8HF6vXGttPP1tr/0iJgsLNfUXDygLqPG4LI43hBfYSRg1HcvTh6Ja6WHBYYxhhlMo2bjx
3BEdJbQpDbBH90pkg8LbuHJGQGXhyHiEVNuUOQgZKPBxATfPWNJm0kXMHtaNKwojC40+okB5DmSd
YvFb+pxNMZXsSXnvoHYQcjFVoiXhSj2Bf2tZDWiqpP3PvDqgh5z20ptbwV9kg5sqoO63wja1LauZ
OHBUvRcVtCgxrG2I1t6zyaWyKprzPwed9nhM7iL8xGmLwzmWm7aRJ8h0BUpwI7dxnwCx6nYXHT7l
IGJFxtqWpBCCKGMbOa7/79d2xsRkao9Wer5Rb8TtUuPOJE6EaOqwPKKAC6yfEiHqwJQ355eID980
f3n/pkqJySV4nljXScbDPEFjWX4FGujOr4sWV502hiFIGgvIEd2v/bzBJkOp2lmtdGzzzNMt3vwX
EIX/yWty1SR7dj5+A9sEZrd8k0RNBNERhLeqoLYQmy2l3dHgxCWXUXI0wuHVaGAZw91s3Dv5a15i
FCnGQVDA/ugET3G7u/JqAdbdPuNTVpP/3nlBzaXbqAfPqNKmL/I5x+S5gA5o3o+Aa8GScMgf+rfz
Hirb32nydou75RCWjJXo6jiyYL9muqvwYGAAzxbF9yIC++jb2QvVJsnG52K1Wi8Y0x+vGc+fmafB
KumJLW2JPeJtUk/g4yo1RGeXYZorpcHdgOSk6ho6KuA4EbTB85UWYLmdoKYIeUCSR8tucde5EHnn
yfEZOtPe9jl5KQzfhn7mK4bybTYUeIAvJ3MwY9AwXoJ91z1Go+TJnqAh47bHRBhspTi33ylzs6wW
wMWBMtxHM6KYhtg9dZR6CL0FlNz6WSpQ+lh2dMeUQuK65jRgvipj/iUHZlbfSgXLlq6Ca/GY+3B2
0TypKWqysbtsmav0FgkjamqjwGlQNQdYhNTu9pG97NI57bqpkFw4y+Dg40TRwf5I10JCnmkRryg1
o15QyiGCkEtpkB6wBBr7ZatW2HNyITi2PYE8Ufxc4/p1LqLyBvV85ihFPNPfGxsEnj2Ll/VKe5/S
saLQHngBBvRLCYV3p8zx9Agu171FQT3tJgM3RyK7HmIdLIb4qc7tH/dgkJRibdL3VvzkicOdGuGX
CMfwUeatkxIjY4qMIaOGyLUQ8gxE2UA9l1Sk11dFbBu7lU9XHFEJqvvh2Bo5ja1KEPWO+om59gtz
OjxuXoVswGYo/fFKJNYLN/tipo8QyoiSYu5VTAsRqPo38QNTb/hNj73RjUxBZDtJ66bqqiA/0Jd5
siFauv2UoXJd8NlFVbCeJnD0GYYZfFU4xMwfPQtCmVfK3GEWxT72LjtJaUY++bAZfklIjt1cY0hv
BqYZXThgCz2W1+PeANca2piFLp+0cL67n4gpSBgv0MOMEUsZnTyAXe4XWLka6KYbTh2UiXUmf43X
WVc2zrFlWpqzZURD1Zy3cx8NCrjcPKe/dS68/u8w7WGvm58SJjjn/JNrj0klnfNeUPuD7u09l0gK
8+CNLX10jxENNq5UJgiHZznN3dfRDOIXMgnsL2gIMm16kRi+kiLqvReRx8H5MAZ33/mZCnA3T5Cn
cbkOWVw4KOZOS1MGuUARjKOaXgr0Qfy0uu9+dcSrcjieH52+53fyVZkygaJf3FIdfwBU4CyuvGG2
y0ftp5sys6nggtlbw5mhBFR6PhSWx9GJdvgOZetvmmdRjWwy7/blIB4ua43C70/YIoHi3haV7ZJn
ubAjA4tTssWHzpgqDDqoOi0bAshBi7qEBzcZP6RnfDvjk4z1GFyq7lps2CbbkCrfF0cN6POovjh9
yB3ylVWCbhxOS8HTmn2tpHEY9I5dTGnTOVp0GpDd1VgD4xE0l9QdjuxbP+V/C/0LLajpISRR/1kM
RyRLe2oO0raqFOC0b7vV/lP27iR+JJ3JX7ei66dnreyuvAeUeadYuxmsok1WT28t6inOOo8v+usJ
E42vW5uI0FOthoQik73JuKFpb+I7cISgnN7oY7eEhqI6ASqhVhiSnEfahYeOYwWrJEOUje64XOTR
fjuLKuzVW8iUC9wjZq3DwyoQU+r+LJvqw+RrerElFunwCEYvMaAJlSi5jaJVobZVwHA3Q105Cd0x
mcjnrF9k/ISmz2jGCgVZ7iQxCmGsHm7jdtDdTGuZFeop6fnkGIdIMCVJ5e3dFf9yXATezX8841GB
64aJ468jto0qyE6Z4CzDXN8/lj05VeiTf1ZchrKyzHRdg70nB4M6Cml+OItVtlBXicNFjQ6f0pV4
rgHHZBj/4Vdnd+cDinv3XnYzgL80hkwpjU304NSsF/BzKDGu0JlJU3YaiXPwwa7v5Ctt7CT8aiDD
W122MQCKj+neC4eyoKu3LJ7Yh4uZtlLtsRL3wli7DoKy4gu7MN+O0wT4WNWrV9bUdFsfjfwhP1UF
jDwEHbtUww3OyTt7fTUn7MuVGejXbKcN7qFUALbqv+/IYwlnLRCYJQaE2URdhlf/PrPJHO7lpiP6
/KJL974EZCegr5JebPlrOdsfJXmY9d/oCAeo55A/uYQOh4EMoueXhaD/JGInN8BNl3Yuz6oBu4wj
KKG79a3tTY3l0lxcDwCH99oyQ7fREyKkH/kpWyitoN6mhByNaGN0l3gXAkwq0aFE/eAFnEryCpMg
Tx0TLLPdotZ+MaGJu8MfNX0ZnogcwHjscqavzKd7ekfGuW8199CyoQcu04xF0ITAKfiO6kWP/+cc
LgOuMAJqZ7i3yh7yYRdGwzvDfX08SkCL3ucquYZOXA/5I+dMz4gbHNhMW+doqFhGOY924qYFIDXD
bSyD5LjQqghc8q1/S7SK/zbAqxbrh4/+7hve0tL1Hj+JBDsakD6+s5Hp1zzYS4EX5hW0psPFm0fa
r2G53AoAYKTffRGMYIyAZVXVZpZe5uhkMQeusPeaeGJleyhmsEVI2C5DzDNHatZz44wFWofnVau6
bbVfyJzJNh7fxRWsA8kXekPC/xJ6QqaVv/XrAYuEuu5z4qv0kdiB3kWQjBa8/0QRoWDGUshFuoQM
PEWJJLTnW/WWQ7Znk7zsdppxymtF4Ip7mJKtpt6xJFTd3WMTSAnRWVevnHiF2Dr4wAdq3QvaynSP
VL6PewAuR3qzmYUWYU+0vFjAM8kBFsqst84y/pS9tzxc7ELvzWlCyqhJqgd1Z8QsrtrBWIrCdOmB
aBlnUSpNTRrqsd0CL9jw7qBSd3D+esu9PImdqgHCsziti9RUkD/J9zN0e/s60g9srLjV/e8i96SW
qL/vP/kyBB/9RPbkrB7K344u8697ynPPfx+IOQj5/td6yj3IZYe6JrpYMtSldaGHwZNMEVEtEYPB
HkObIohc49Y4seIXXFhkvjM3FHmq26+Z/DpcOiwI2nKh4R900XkRZOgFmQYOX/23woRGwfQkMor8
v65R40hSgG4rodBhc1WzS3TPSFKIM5F70XbGHdJNgxXUE5g/1oIWdPqz5OIY+FwhYWSzpQUkuFjr
Lago9bF6/PdPGK2cAZUV3z8HOXzl9kiNIWMxZjObbEGA9yG+Mib/DzQaC/gPE9qbrUkJPHQxd452
BWLEuIt8L6j9dhw0zABnI3SaqOIc2gLjgPVTkuEscheMGiRSfLBlwdlbwab9TTXYPX3gup7MZJk3
G7iz3I1/EcNOoZfjeiQBuBchKL1nOSM2OygKwEshny/Lw2tbVmtQCb6FKCjV6AovjZrtHMwSkMVL
JZXvh/+OG3IN4caNh0IiP9ImXvpu0N72YismJeYhXyZEGTKIUENM3mSYetuT9z2nZ0kkwbrU7bPk
ARTuZcRasbbQfpIJYAFfwuqltU5ReHpuENn760/gvxs4ZdVZ7tUmblJbuDR5VrLaGwbe4zoNzK5P
ftFYMpa0ucg6XrumDJ1ugHsOy5R/jnJ5NCWnhrDqkKs6OqwYgv3TgfDi4K2iwAHrDXv1BWW3U1la
kQUEXNE9px/VFHp9IArw9sivD9AwyJb9Jrjm4MUP0Ugv54mThCr+c3s0TLAlOmK7aJSRu7qfUlN2
zyyLu1WuyLX5y9N2PmA/iBdftaCAtogfJR4hoTRyUdsEovpQAK4LCfvDu0KICgCGfWt1o7mriX40
uqb8BixwZ9bpLiKVUHpGMkVVPLRzQ7rew/3KlaDonLZln6vJCtRL6maYyj0SDuIYk0pgnBw74OAj
Ifxc49YmAJO41HVF5lJoass7JeeWUcz1+szW/6rG2TRAO/4mmgiD9bMLLx7ugE8Kgkur20AHcYn8
RvJudUJS5CJftoH6suyd1gg31a8jEN/YGm4zzggxoMRawwqnjDszNMy3YCH+sLYsrNxcb/IUk97G
tHF3Tk5ChCDd4jqreA4Jf9fPhpHJ7gj4bM8tvMzMcFsXdcLU16c2h97fu8Aj/4ODvWfnpnBdhcv5
X9NZYmZGTWhIs0sgCnU7kwddu0tXq+v7gBAA8EAMw2HJvyLBLsjBdiA1NLOY+OoHuVZ81PjTxypp
j/1Prnz8dwBNkqvKhzligNSFEvN9FH1Xz+PxVfS6omuD0scNkchVcJnP9Yqn+ZdDoQ6GZze0BW6x
qrwHGeQQ2tSrX2ARMNV+qJUOUhEdH2GOwBjOAwADBYaxfrSnSpajGmDoNj5+LavqN1EQ7PQLlXxO
i7i7uTC3DPC2607/nHRTcda6HvC8hiPpLgDcThQqsuVsbfk7E/woj7I0Q+7R1M1sEJDE/L2adMgC
vKA5tgCuITHxDlKy9pdU2ZWds7hIc6LP6OVZwCFWyMRyvyesWaj0cY/OpImBpJCoiPoaKDRgrDwF
IMJV/yM6enkopaNrCgUcaJ96Y2q6kevvQwSoCkbhslL1nTrFEksywSu3JGiFABpKg8emZ7Hvp2b/
coA86ADgFpjJhCfbe92FUwbqoEj1x23NboZFEnzL4UpThq9OnT5Re9eRhWR2/J8vqVAsTL1iqnHT
wujgIDIlU4A2TgjJRukWrZwRVmkMrj/VflZAtCXUpdN+jDsiSqDCXwgnlMHAjMjPuBE5vtBZMoVy
nQTJ5Dlc/90NOWQXLdhwKRPVRAlX3Fgkhob+yKLZdL91qnqwOI13WpzTDA1aft+1UGqEaUtOisYq
z1H+wrhvwjzxtgLz8I9G43b1eJmrWcrU7Iap2SUNeOZsaygB+PhbYqXFkkjIrb/J73ihCuW6y5ks
61vZ8MR5ZgFh4447EbC7bIlBCnsaGs2njtZNizfeODRbdgoWYqz7cnRGsemQXkhcwN/J1ypyTNBg
+Z9uAkWpmqFXb8QRP2+UPlsIgbHiEFqZDM91cDyaSeiBycWTAuuKW8TIieOyr0wMpuO6bP3oB0uN
4xoFcDg1IfOfZbQ6arvNkVBlxqlcJHMDXlwRlsZ+b9YxVh8EsA4Htrwwtv+4FS6pPlZvb248mvAc
TYlZUfpY2x980NBlDv5MI5Wa1PFFnxFARn1V/CvkTHnGlitKp2HIg9WUhU8uKlLiXiooYfFnpCW4
nCCJNBk41gSVTiu+aTD1QfN8fYBo3R1JY/IxwtuLlivRF2qpZpGMD6A2ypBrQ3QU1H4pZiscWjo4
eFIqkHVLJwKrP1nVZQV7KOuzwYzCDk/nv6z95OpmsrAubi5ZhcCBVGgWIpYYn7PO5hjq1wMBHJ6O
ATPmmmzqP9S6S2emuo7CpxlnnsQCYHQTsZQP5HDdXjJApWRRdvwGlS3ZQyFT3arayySR6i1rV5fi
P/1ttDiIaDQ5sQp2/TE8IoWjVW2E8VxsMJJIsBk4pPOlJzwtGRVPRTer1irymKDewO7JIzOvQXHt
K2lVH45LBVBgmm6goerBwAp76X6SWLSoR8F48ed9ejGZZY0anDKukIRPS8aWvxsO5pr9soezaO6l
cQ/aKzYRd1mRZWVp1m1huewY2M/Bth/QIiGGb/Fw4YBngVwb3me/0pTLWBD4Tqh36k92TVTSZ/6W
yFotcnSuwac2PLAJFu5tGa7wUxdxPlgnWvE8LjMM1mpg5IhGeLOGg14FswxjP8UuLEQcO+ZPdlAJ
a9YfCm2sW8OhwSBS3FSKXjCso9+YRCVmNPNACCtL3HWRRKQPR8J9MwqhzJ7vi5iyvk3CaGe5yKZ5
v8oKNZJTXaY/ZsFSBUj28HKr52jPziVqOSk8OK5Z5L8uaYfbgJjf9iRhrE4i6XOCGO9e5AjHRmbe
GV8CwBRj1qiWMz0W9NjQZ5mZ46TRWvcr6WXPiCgFpYfv1Cj+SCXFgxldBEZOyRoBO6mqvJEBvig0
N+jHxbSEoVgxF3qvqxKgpd0H9hNZO5i+h3xsRkZnNLy+DTuoojcv55TiTZW7YwByC+8mj14dfQZn
Q4kjEXiX1JBQonoP3vPQ1WxYon6rdBJayjJJh8lKUIaBSBLmSnO0Ar+xB8NDvWzdrwHnarA450Iy
Bkp5hE7KN/fCgDG/rRL+S1NX36ldqdFONKDnAVvbezFvetZC3ras79Aha9GxurdypMeLZhrBwUIL
qm0ZWPg1Q4c0dFOtHTJgC2hEBImQXfZnMduk5zACNdVDESZ8cNvn9QHV+LQSxT/W41ixVxxn7Uwd
Ej0zQO7Iq5AduvjHY4qJVa907tkVTertP71TqJMIDiJneNPqF7qFgekb4edDNPr4Zg0j3YedrKfe
h39TYu1L3awrhb08nVPBKv+sn0EUbG6KviOJEJAnI0V/qCLRffL3INk6nv5YQxXaSe6QQa8zKATc
66w12SLnFKkYP4rfD/BSLleixgrWPFvhmobRPrs1q3ggOjvGZ15gJ7b+4LI79kXwGYdbw6Qyl7vX
YtQwVXRC1RMlvgO1nQvnwbmWVz4DChKuKkACB+hxhlWDd3B0PeEngDxculCcU7gAIJyFw5e2zWHE
a0icU45+Q0MUDcs6gXkAdr5ieiCnkvSNfZxFV1N/CF2gLoDN3eM44XZqNnA0ZNaqY9w19wB+A0Tp
2RhtvoR3wpupgxPo/T36u7Ol5Tc+JChO5GllNqkMLttFySuYjp6ge4cFh618tb9t4jIHmfHOXQKH
ej7Lx0NoAdFZUdZvDjYHm6VnKz7rpY6GPprMnHEeVsNxE7aFyGErnVfulcCNJ7ggI3Ubs+n3j1Pg
SY/9aSi73aJ4kIiyO5DjzJ4rSAHNNmA+mtusv/kS09jR1iCydbdq+diexK0MS4LBOYahR0voesp5
En8x5RUhlP0JjD4Itgigvu++WWEhOqPvgXtLSl/cd6B/6GNaTZK1mufNSFTHwL87Zm00HD9P/xqO
7a2YAva8zOPehI9mTcobbluFxUezeCjrIwXSYBmePLhwDfa0HBDBV9VivwiXwj4AjUC+D5q2i0j6
IGKAJFQAdtYtDfdsfP6lGsqbV69/hGCJt8SUfOMrkfCPmT2YTYL0tCnYRSyPHMsd0hh1ctQ0KsJc
DfBRqTAbNYECl3GU0yj6plUTYuvUV6/mxTuZyA+jcRktuY8GuKKCBzA07JEIjcw+7deuYtNt9+hJ
w+eXfhLbrtXooQ65PdJfWPE7yKeCEq3tky/Ovyw6+qUH8xlOEH9hYS7AgwJhskKMdRfoB5tpJ6rG
6wP3NSZV3TD3RNqn7RM4zxVQ7u5lrgT4ZsyjdU9tSTgzfo2+os9wahL4FTPqR4orPULGM/3tk6Ti
iR4n9E3q17WGW8qOy/7QwnbqkmGBgDfA85peesK/BvyiMBZvOw0G66Pm5NRC6Vyw9S4fVguiVx5h
tzYqtN4Oy9wDeSz+FVHjkMERtqk5vhyhxEB1J5pWOD8mXefVSnsJPY6uddlDRjSoJ6gU270dwyC4
mnwDsf7uVgTnVFbT1UvmyKlfSr/v2Tb5gQPkj9IXJdMcohlmq/+HZjucCzlrIa/k1KRgtvyiQbGu
n+AvM0w91fUhMGfrjZwYdCJFZmr6XbpnY1Qk9nxzO6p1qN7PeqJwbKRleMVsRuv2HZyntY8vkm7T
qXUrnDicyv820iqcDED9KSwBNyA70tsSYSJEOU7IAA1z52Xw85cHqQsXlSjamxcn89+W3Y4rHUtp
MomAZgQrjg49z7qsI4BmEaYSxLSzaSL+nvqmAjQ33NQBejq2/sQJ5fHuwg+5TLf0O4S0RrMUUJq6
LpN1MNHk3zOHdnEz48Oel8gMDPT4suTYwOr7aRVMlFVytp78wsDwhPPxnHc3Ik3+qgPItgCfwWER
8gFeJDxB8rraNgnqNQQ+T+Ae9HvK8IUd6CZ0wwfn3W8jyKnrceS7f2F2udIASB8txZdMFjkflYbb
wN838uwVB4eBP5RN4VopPUYHI63cPTTauzDRVFFrNm2UKpGMVqNtXCg90ycyzOsYnz8s/Qo1Xbr4
/p1PzPjw48oqk7sCBYg0EoS4uZRLECHKkQcHRh9amCqWx06aVMYL+B7X+qRoXChk+RaOafqZqitv
UZ0lUfRd3eL9HP/lfjFN0XN5uvzhLEXYX7zBRyIMRqvKezD1UWmeYcAPmh7Ozal07L7LGFuRb505
JjRn8eph60o0WSoVDCoFUSXDwlRiK3zaUhKXUqTJksmS61UT6J/ldsza5PsZ8cL64jmdJxxSLYWR
1POmlH3GBqdnbN5wtX+Zn6/bwRWWhvOJCwjxaJ4nCbjib35nEhhbpAr3gyKEKFGDVw5hBx2xF4bm
wAr1AhqVGG/0Hdw4t+69MvzaBH6In9EWf67zmj9QoHywbt3iHUQMTiKKAw6/Aw2VXMB5eiB1SdIl
p1xemp1V4okZJ3jkX/9Pt0Iv7jnejafcghkUvRsYYmj47+uVyAWaYmql4VWpnZwK/PFvyaQbpOjS
pMl4tgpsaj4QZuWfLPPzORzLKIJKQEaf3J431xPVDYr1Ts5UmsNhm8HXjfUGiLLBQM60eQ17xBOw
hffny++ZvIUOZ1Q1GBFtGj70ASyTria/s/NPZuC9twu3CerLjNvO6fGtvH4lnIs6haplfOR9FPGU
wL0l9BLVGgDK8do+M/Kn0d5grEu/wK7KJliGWJHTq0R56EjPCa9p8ssaB4TXY1qoX7GdMEct6Cl1
IEL1mroxG3dkNJSwUfbVYD1buvCBrMCVtQH+wjjkAkQUOJHlZVy5HIkVhuEYN2zVkrZWprpUNy3d
/6LpwxWj2xIJUCPbSxQKC/9DAaQS16nN6AgtZG/rayBhIxbtFDZoUW3ot8EVnF0/TLVHIHcRcV95
59VRrHuYeusQrBjEk+lk1kT/7rPx5mjD5nsd00ilSJmYS/J0Tcm3cEVEQ20gRJ2d9EbDmv8q9T1a
gM+RN7cenTHYQYJY962qm2ON07Xo68S+h6pEeugZi4yKTRQvuxJw4HNC26rZpdWkP3N6QsP63Qp6
6qS4/+QefIr1AKUqbQD0e5tLnrdW2z6/Y++/K9RY7FWjYWMCKEKln81ZvFc0k76p6dKaE9CEPqIs
XDv+L59vmA6s+BK9YdB/n8PNDp700WeqigPVOGa+cPHB/Zu5c1a/CuqJ8uqmfXcniR8Ahr176K73
tzaTRmsb1sB2J2PDL8HPDfEOd17qZubZsGIQUX0mil33tAwzya3ycQgIYT+icxnTT9of3MVaiuvj
fJ6eKaAYVE36rFn/N4mpeFiT2xvPCSj5UjAptBe8mI/3sATBH0WB+wUN/EkAbpsHpqKRJ3KSDkys
T72dS9Y7fKI2EJQ3Y9rdsSqPXeSTWUq4YuF1MLqa1GYIaOvN7MSaa5+QBdJO4brP5FP6d+k3KIR+
lOJv1ntHcU+bt3D3TR5JFrl4GR3nlN5cI/AD4ghNt96OUwdgHbMHy7FOLQpYH+qRgqvfgRpuTY7O
59adpojrEvf6eVob746QBZjl9UBmFqYy4uGPKZ51WD4t9aqTGYIYwBPmLb3QBeE/BijXJBk3RHiB
EIk41PDaVM6TnnIqiLTv4cANRWRr/9Bmeon+QkAnMx3YT/CultsySAvrLZu+CaRABot6qIA8f6PB
YGfa4itII4JZdbc3A3zC8Uhy7Owq2uecIvX7EbtXLamWwwyJt7/bcfEGi2a96JC5C9U2jp4JYC6r
n1LNUBFXaSTgUUyqLUyeYKA5O/UCjy7yosNVMEbEdXGRbn5H+F5O5njMTc81jRJKrLiepazEe7YP
axJ5ay60DiUvA9BN637kw7uavuXs/Z+maqCmX31RS0nKYY4I6nlWtDdIpPszL/YKjmprMw1EsLye
pcAL18/dLmN8l4uW1a6ovsFDNFzHJECqWr8Cdb3jn3w7kVqfBNgpxLOLwWhxepygO2K9AHRfk7ci
Kp5BfGkppdaU1tEfOwUd+dLYcN0xY5OXbqFhFQf4ALOA7zSiE4vd9jvZAb7EVxRnwR1yArnA1MZo
DXx0HTI2keAv64nhIzmJZmPQEWuPAbmePKfdBeRrnzTisOvGiUNkl0dYNfUouVKOqgY95JcWgZXm
MTudaqG5sqJqLnO22+LWLrUncxAOddbP8llI96QlOwvhLeNotGChfVG4DXACNjHTL86l2xyj9O6L
w8+05tfDiNSjbJH2FAQwblCfnJJcrYSlLpgFyLzAG8auGOHx8YjLWQpUAjDN0YSeZXI9LoUrrc4L
sfP1By5N4aN7vV1Jz5xx0Kv0mh2TG5jGf1XXv9siOv5zBqn8z32Ejx4MiNehqiwvEWWvkL4C4n9Z
K2oKBHQ4R/ScDJqOVUTzBSPkqG2HXLq7Qdw4+UAFRCXbnZc2QuXjcusicvLzGXxHJ2hdNpw+H/0N
8YXz3FfbCeKqecbEjgnKtGUssqixcSAqCPfFGtqPaVt4ZKhqCqNgNVBUL5QDJ1sXeU2wOdioyDWM
OWq4dmgEItkDVrRd2N4ZdTHauvknNqzhR82GEamk1jToxwiW0guKlaD2Z2Cwffg2uGJ6npchWDf+
TbDxJmbGT1D8zur6+rz3K2nfqfqzxJAQC5hY4jDwjeED13aDkJBleheYy/jiuP4Uq7ZCTh/Ic9MU
ay8yQ0BR4aNr6NUafFk4dTxa4oQCh7ARnvhfr4mR9xiV9akch7UDztbY7faPvhK2SjnWTwXtRHDO
DZWQaBwSQc6RKpAmEEtbB/wAIlz/ZgPmysoo2JAQ360TDKJBJKoTMojTgqw5Ux2VGE/iUWg2MZYr
zCQQYSogfdGZLvySPoSo6idlClnqF7u09gp425ceI2nOWvR5j1fmi3nv/+rU1GIMo9r0VxhS8D7r
Zp0j3E0TeGc8qy8L3FyjXtBMjHeEfN7s+yA8vd5yv1F1BcbyxIbBtQLqzt/4o4ouXKG9F8r7vn50
F54PTfEzJ1ZzLRrkaj5+HD2fmZykup7fRUBqdRpsAVikMLe3hKeHNgSo//a8BQWsCiQJbIcQ5s+u
5aNN2D8r/wBNR45Um2E3wYLWIylHOmi0Q9MIwkRugO9tRBAhpD9Bimh4iPjQa957bOtL/GyuCUgQ
2/COqQcvzy/UzMo42pzOwJ4P9BSX8839t4blOMkE191Umr4Hl19NrFYRIvZhftiQ2NSOY4t5GxDP
e8iLsMg7d7zCZLGDMOO5ziH7OwCag1bUeWViqDeRBKmvzV9AN8FWsZhOdwe2LtylhzZXmMmQjmXJ
Ygu6Gz5tICCutk3Y/e139kS5L6t19EFrgjJrQFCcQQW1J4T4oKP5tEqqUeEjfx4Ir0/jY0ATSMz4
0wUZbyvcbazRZX+g0/cYE+0FWg+mYrmeG1Ogf0CJZ2xDdlZEqEhIISf/X1ruWhp/50N3FP+tBgjG
dsBW8ffvUDdZqA7/xg9ktw+MTOalstHvTBJqyhOm4+Wvdw0tYh3m4MD4yiCdVeM9RxTzkJK2KDBT
V1kYFqcx5XPvgOmcQQPrKCdpuPKbGMFZsDv/LNYgA6bZe22/u8idYOiWJGsaoZCkYx2oaIJqCeSd
UB1P3YRSLxsGXFwOWhtSTMvfKKwc03lOIJ/GfDGcGM8VrnuUBL6ezN/TeTq8UAfVDZOZ0c1jlzjS
FtYoiklqMKulDwUDpEfwLWlrraCijGYOG4dEBt+HoKASQi5169Mn0aUoRVlbUie5D5azacKBzVaf
too7vuIA8dNXFvcjO6zU6zuckQv6qqmfbGZ00Zu7ZkMlJBxV6UKEw6ZyRprW045W0tCrM/T0pFQ8
gkVtex0eTPsay+IymtkdF5bR1EYbKJjkqe8B2UkHG7iqKKI+ZOu9NUoOkm2IkT8XnG/QhRgta3ab
DoBbonz7g+F/kZOJRyQ+r6HVyhMNVBX8BvXwcFxDAwAXWA7xayu232wH9jhhjDpEOSAGo90PahFS
RhosVc27p1nkSxTQUewe+AVunPnlOFD3LLkngbIlo4Rrhzdc7svWj6OLcWz5WpUIhMXaxu7qujZW
9yKf621zozCOkqC99bxugnDiZt8wqg5Xw2QzDXeu12uWTywJTSHo0maGvmaEAeuSj0si7GPEONh4
PrL9Spxq/wOvmbUPdJFcS6EEDOdW1zCXem06T+WUlq0MEkJxUGby0tL8W20awfR2ejywbIuyNqHB
EBPn9j1suIW2D22i2Q56U0+UIzaV3K6HCco1LCcTgRmR7lFnETCRTtl1zDGMsBSX50IJxXMKTFeW
Bczh20M64wHhYIWOvNkKb2ey506YpHrnbbFAQSj7OlzCpx7DTyouDCzVVSpuPE5IT/R92dix1YAt
ahFdEfy9CA7GQROUh7I1oxelqZSN/VpaKkvg1sYd6ZliqebsgpjPv8h92bZI6+J6NLTg+ScE72e1
OybUtDlHWTsfXOsOy65maU2/ZN1SHIehWna8bW9pUzYaSA0Ye5//E5k4ZI9qf00JWvzm8HpY8S1m
y9gENHdW3/FBs0e2MxOGqVJIaACTcgHor11GxTbaxuUXpXrmS8iQQRv7xaqO0lCeW20/2hGIBEEo
wijcgVeav51OLWwxiA/8Eja2vbBPyw6vnodEPptbdcXWeQEb1Lj4bZI5QP3RxU5Sc/IxuSo/e3pp
Vsx5uApv/VIbbzLOyiBIuCn4R5aio73Fb07D1PtIY60XeX1L/hGWX0ASngfQrkz6yQntXkQaoIff
qTs8AnsaAZ5XAdvQ3eyVSzE1CCuqaHmGAzswICq9KfnShu2qE+fh5Q7UEG5zmuUDQ+a2kXFYqDMl
WCldZ9NvgBbW2eyNtIlTA7eKJlIbRMF0pMW2ck4bmK1IHNjnGRoMqFVUcI+++5g+3A4FZbbB67wM
vwMsqeOfLoVnLrA0kzIqckCwO7HB+aAVaower74LNdE2UWn1MGWjXtwiotanLcCQmC3BfwCozs+Y
qzCQnc0nl+EHcN9V8IgQ2HYN7sDajbs4nqrPiP+YveaYxLfLwAwkW6a9yvfleGAhzPlfHAoyume3
UmAhtsGoCpHAbYa+HRJhmAmQadYKCNyCW4XP1W3rWvDy6vVtEZgjr2uGGL/Na8xW+9buo+h2vgM+
u+8sdhlutuT5Xa0XkZ6OSSc8fsubYktbuRp5yVxgBGnFy00Crg/wbyuRKeFMAvKG/rM8JqLDHoOB
PGkgcYpDI1U82jMWNYHRuD6+kStzR7E1LAM4lcF6jVKFPpS6hOJL8cMTgXJMq5P9Dq93GhgMrVmx
iXRFsU6JWKt57ipjMY8caRjaCsIkwKP1iuVKrDIPv7gALxK5hNpCDCsOwz60Iel3UNL9JJlJxkNt
V5/yzUJe860mYrFEMswT0sAC59zyBpbV11+xqFKyBWo4idfaM5R2RUJxSmAl/frPzcUEGJtHSbtB
CyGBdqPGabs7a+ADxmfqi7t6HIOhpforPFUXm9cqdx/A7wbcHvD4+Xy1Cjcpr2tVETScXFgBIYOX
TyE10uzztgJ6Ub5MWKfwbhj3ct0L2rhY3Mq+N1fYDO08CsHSb7WbrOY7o4q8HR6WXPc3Ag53vM6G
75lMeh5keR3DCwWQtjVDrUAyxI9qH1N+yNzmz96JhNFcvxKIayVolkSgvgZBGV69p0oYXT5vKkx/
AQqFJf2X02Vu8qmk5pYnMvdJ67blyvQSkxgpHLDuvp6Od6CMCQS34Utre+IJJW40Lb6VGUeBCUaa
Tc/4fXLQ0Xhf6wzMU2Th5S5Fdg0ioszvUqkiGyGAqWP4siLfkBuJveCBqi58KFVo8jy8lKS/e8gQ
fegU4mV9FI68hX8Yk4uCnwLlGes+VvQmBlesMpIReIFu1fTkmo8tgECRr00AQ1FSRaUKXQXQWD/u
LjLabvE4fCo3nQMTHsZ4VXJmX+q3mizmGOpe4SW8xkTw7+IKj+zPkJ+CunHBBhxhM+8OcZy+TJUK
viOqkVGK9VXr/FzNqIKE9cCgJK8xu+KYco3oglpURHdmS48h2Z74YBDMGfka9ZuowwxS0sUp+9b5
OBGJ7rJ1XB9ImgKR3sAgeGcGEAhmGHadMU5wVRZCM+KvPnlzQ7p84b0wLaMnC+nUaD5Yt0XNUVJH
jjRj2ktFgvg7pVSnhuJnCqHeWKSWg3+N44y8ep84Uiqxt34rzB3kzQ7apItcYKOeO+jVD7T1E2aE
Ran+4KNc86ai5TU04CHc9WBz4GxYlsnO6kGlQUI9OXjkrI3fu8iKNSRYVezYuIReDexUynlH8I90
Kpt+6NbDZzxIMwEYJKx6kQEJkRRJdC8IlWMTDRjJb0VyQ0hgZRS17hU1HBwFP8WHZoavYDIMclG3
/wDhbQ78JwzedXkDsLB8kevFuUKE9yrFz5Brg+Xdi3vtvU0ZC8ew/kiRpbzGMcfULHE4XoHk4Szc
/9Z3pbzzabIFi4Ildgv5AVl0kjoys1jzjz1CkLzRadMZtvadynoV2DwM5dbg/PesQWbHTizzwNu8
JwDKUizLb2LT+UhVIu51obTQQGafRIY8EvtpwPCLNqNgViO1WPBSdKY1sCs29go2MGUTLhwUBAVX
rRWJewadIj58otIUy5FM6Eoqa0ZuVvHDajFrWPr2M2FgqFaYvw55KoOFtu9Dbw5ZLhZO54Ncu66D
SkOMCtle7vUXe5p5THI+ri92cP6xyzlRU2LtRPMWwsO7ZuTIf+oCXTSxdAmsXRl7HHqnmwlLjrh7
5ZwOE3tKieaoAQTo0FGldhwuRED73nn4lzRnylBVTTKypWxS1O1b5vXYB5nvxnWoHcfEoSKHcd1E
wlkmLazieueuyI7H9QgfvcrgXFSZRFtwQeFHZW2PAzyiEOaOeD8MjtLD/Y8Prq9ogI9pbWS5wTlT
7yhADexbAiTEkWVBce6I1Makbm+IyrLZDU5LodrcjWVvk6VTSaYGMWTbEs8Bv63ORex0WGrDop2c
JLYSBGD/kBoAecfB5b5/33XVMsBe/hDRoBT9u0uEwNPvmHm+21K502LYCG65DB7Yopy+C/8sqYUT
c1a1O8WXjnpMlS1Y8YmmbJWKHXv08IXOUBLWjdvKexPQl2rAVSwdICO2kJHD5DotOfEibebxE0KK
Z+YlaHsaP5p3vEcOoYAVW7+xwGXgjwPAIXd1206zfU7jHQ1hKIBRRplcJhGqqQ6PupiH59bb40ba
k2N3SBj0G21RqGZZ9IJju3v2s+batp7uDIAUBW+mgQlAgokMAxkfxKc3C5uCW/d0F3RX4wk7oglO
cnY8pbgoxwyCZJT9x0fPwXiDNkjUorZmnLI2OfvhI76Wng2B2IcsBGxdjzKTy2hzF1nztGioAcW1
MUHYwbtBLiUONkFsQ0buG/YZxV2Va7uj5t9DlAuKvWtxTjFtP86u+mDUY7WfiZTSGrl/76FkQNU4
pGSyQwAvCiT+MRo1wb0ZGw24Q5PBKdgmTUUdjJas1UPt04y45KIo1N587TmC3D+G4tWa4/Ih0xNl
B3vlPajfbgtJTIwyjgBvQtlm+S1/KY2TiA9IQWUMvH7MobcIoQ6GrvD8HgTdJg6Tw8+ZQT0njnQj
C6BVNDdSLODhXIvxemg9Kg2x5O/7ksbH4iWFUUyj/ukHm5Ol4JQQYZVKGVTUYQ0Cjv4OMBansWWQ
nakcO3bnAidJKSEN/A6eyNe1wy+ksKFeUorAJVRERN9e5Rl3Hc79x90c1Mij1lbXKeuZkiFKD0bM
QtNkKFvWW4WgHbVYHUYEtywCFRbkiGnlwtIViod2temRnUmE7/dsgnicmWrDOcjgDXQzWIvWWsWM
Yh0tt7OiPqyUFPnNqtCNXO31zXJmuWCoDhXXr88rGjCZDOllyS0SHKhP8tUlOW1u0XvgP/VCY15/
rKDHKuIZTij3GhPUISndjgvva+zIEZaFeAOvbVia4JNVYb56wz876emwQ59zN9Bx4TQxGX+BVbJQ
PymUTD7o1/OXgQ1EGM7TAZ0gZStGQ7xlPwGqlDEm87xJ1/LhvUIwtMP5PSM+afdXlcpzJCP1M6rh
Jim1AWz57SSa8ngrduCEC3Z/zpo+cgzIIGpreNpo5/+oa7K3ZLEuL+T1JJqWaq03ighVwQGovDPf
tuWX0jqFuPwse1a8VyR/HFOLtvxIbnnmAabNpV3kD/kF0t43Ryb8qbbm8jPpzNiddC9fNRWT6Gsn
iEc/aArNdII0qzRQGSYNI394BQ9HpP071hUIa8X8ENtX7Z1k9pr+5WQ6mECjuJ6W8mjeolNBQjki
wGzolLyDUJtkWJgq1L0VnoSKEQI9mND/e01yZYEFkWTMV0STzoeafCtrCLNmO91y6sSQ5noFLNqM
GiINKjdMaKy9fxKi63KPIEA6cVnewMPJwpJ3PsKlXMGFvjSfSotJ37Xy+jFA5xlwuCW5oTjVWQtj
X49WDrTehzFqFNBKiUMkl9iM5DC9RknnQx41iWscT72vMMS/j2rjq9Ys48jPb1dA55O8FTGQFpW5
gYgABXQB2usITM0K7uYfPZ96p4AQJD4XFCAzFohLiruq+5xCia4YOjeOnE5z8/US5rWqvH4W1GFy
gke/SNWwgaws+XyAXwJPUND+9DHRW9Cr0GrUcJj9itY2j8wl9nZGeJ4qLbxpEJH+Nt0FbCg37hcJ
9kq6LQOimdI4Y+DdsAEkJQ4FX0WhdD5p7pHOqvNIAR+CPg+DSNTjLgeRVgNUTtQYlDEX/2ivwJUY
CekPbqq+zkk+5hgJxPjDsZ6mkRUNes9GoXEAwS1kALBiLb0IGO90xF0A3/a/acXJ0V0qwfWJlphm
sOAINvUbt1mg4M+D2XUGU2SwbPHSdhHX/vYmXXAy3Mvepe0FTVbaRJn1Y8JOAcxpZ3Xrci6WaOCp
AGGybpfzD9Ejo2CllIqwOSdtcA7w1/OpOWeeEPUV02r1P5VccCxH9zubNjL4+ZHWEyNOpgDzjFy9
vW7F1NNprDFl6sWWTdWsOmImx39rf5cJ4WJgSJ9iT+/GVQLr112J3mWyTqinp6Ka0u+6zUKCSq2y
eFUmTkhZ2seylJM1HOlWtaxtoCtPjBo8h+ampND17mkpyGJqU0XpLKMWNz1xeV1qm3LNiW1FfLex
oXrksZIvUlLjfo6jEC30144TuiTifKpLuPPVuNiazIXAgwWgfwZLTHEcbF7mYuyr0iC0yzOiKT4Q
DnHCEf9JVM9gT3a8fKXxVjMin3ASxmWQf2TziRvDpjtF4aDmAB1RBEhS6V1fRCxH9ij1vl/aSO/W
MkAQPyyqg1/I11jOb0IvBD57RN+EmMngtU2H9ckAv4hfrglO1aq8N5HhbvOvxC0WJ5U0B1/4EL40
1GQbU/kN/jaz3z4alw9w+10YZknP/Y2bceFJ6mJVsZDlNGWTkjSb1VAVgHzhQVOyoyEszfsAZtvw
LNKJtRbN/ZcIxoQFBnKu9gL0C0s9PMuOBGRr9g10tj4b1y289K5ZQsdqO2i8Q3lFMfui6hTHtBni
YkFL+xAiJFEzUq3IX70j/ivfnPo75tfiNnpaBet9guvyv98ocQ55Nap7mQ2cpWiKELaNrCTUSMam
aICD/VkEb1gQey+zKeH088yKrL57CsHaS45coS7l5Z6JAzAQCzczMbO9ihoT2dDPvg2MNLbOuaZZ
P/jh9TnhZCmVycEtvmEn81Z9aPWSBcBr9sE8h8oUzMFeNOtdTlLyfc0A8xrdfpeIVOX5JbBBba8e
31XwWKVYUK7l3Ewpf87xuhPtTYB82gMxseTZpqFx4+X5gqeMWbKYcSIoz0z60ihOLlqhEca4UeHG
MLv4TwfANdjhOpGvzQPQdJXIG4RQ8rSUmTic0b48KknELmOn7apdt1TzTKdBJOjIOPWNyL7zg3c+
jwzEjwANKW4LPEDIKm6rHjMg+9BQb+/q4+1CJAtfp8d4h9eHN7ccS5Fd7Mk7fwuKTSPeI1WdswWU
xyy/C6uznTpn55/C0UriHBQwu8slGqDsIjOGLEZgI9n5JJvQc6cxrb91viPqP3wuLda7wfAtQFnB
n1d/4eQ1V6vE6Owvo64JKwL8yhTnBadcNf/IbH7tC0+MUP7mnRoCBl9LFzEo7LEB/GVQ/v3Zum2U
thiD23rRdI+XxlqkS/HTdXU1zE/EQIfHkMHbL5jCWfL1W1+PLHbWgvJE7L8qR4L/5RYcCnXqr/zX
5oGOHLnfoqm7qIBG6Nk198X3DJMvDOiz8o0c6y5LxwNYOq9Dda3FlY6lzmZpn618QQa/zJfT+gpG
u6AIgeW/sk7UVkhbJC6PO+rrmhrzPmPP9tGi/NeC7qWJxkjgG2JQ82xo56UGMljf+ld/yB+CVsAs
LMzuqsuvSGlAeXpwxA9lqm9r4i5B1MGKgM1mV575guMfX5lEr2yAuSdq7K/96HYoJy17h24cjwIk
UvN5qjgRLBVh2dDjziM7+yK6VOlgPJfpFEtCYQsGZk2ETXyiy5TPeln7NnFRNp/R3vGzOh1cHqlp
kqUKzmV1pFsmPumLftoR22/cLGBFYHWGuK1blSKY7sJLNhjQb1fzEubjkSgCey2Xh1A7z82SpRs7
Q6kpW9JuCy51lvA91pJVtCSZ7jskUZ9/DMlluEzgYjKqWOT6wbJZKwYnFdkAVWqkSBsF/fh1RZpu
y/krVGu2VdLHhbbPFl8HhVvhhBN5NiOg+gFGQxxEPZRcTt85Ch4COvkRAdsKcLLqpvd86ocjCGdE
kO2cKGUH5pFL+NxT+2Aq0HJkboA57D1T7zFf6wqXWorz+klJAlOuvd8hkesooLxPSHKTQ/NsOzxY
sGaZofzSmoo8ePrnhXkrH7mfTrmQaTW22MUEwhMUIm7CHFNHYMcW3uf04owh7nWXlK+IxvQN96y0
MeCoEkKBZs6/4iVpkiBxTnpD8T3N26LR8tHybHg78Ia3D4eE3wAdh80lFUUEVV9CX97NIQApK/Gd
PgU1TD+kZCi9+Tv29fkIF2MHdAAd8/n+6lMMnJNoLv2t1bjBJoD8yMkguvssW8zjVthPh8hz7qDk
PMbR2l2UCbH+rV/ikk7m8qAWOxIE+ZBf0Ik34WmompKanOo4QNDVBschCIgQja/8oIZ6jTsYF8R5
tLgXozlDg5SNyceFw7uanGcewN/84WS4bXAHz6v7ne+9OFihZsl7wyMwqCDKLXr6Ij8z9kIhMl9L
Ob4Fsfq2Qbnho1tuGo0Zah7nTahhiWZVXQId+2p/85D6A86+UpoJpXnukeSuq9oGAwZ0A59XU5iC
2kPADtBRAZ0vm9k9LU9LKdabSYxpInLlnI9q7daP805LhHgP3RBVM9SSUVcd6Izah2FQn4Wtuowl
KTTg8xD5/z31BBvfqXDLz0sSqG4uvqEsiTZwf07C8QmLS0N18/dy+VXExh11fb4Ogae2KddRJLu2
OJfmWYIu2aDz8HHXdis2eqCGcVZf83P70hTbw++jWR1tx221+wLnhB67u1tIoGruoGJr2Cb1sDX4
xK3Kel7RKIjFKEBUsAfuZ4LRAZewjDFp+ftGMaU0VmwocHxrf+tCKszT95Vqq2yP8I+uegW43lPB
GiZg+0sG9TDJ/Mc67LIHVtOyxsDRJptdrU5Awx2Vu+BMplaM9ai73B0defaZMjBSnMT6RvaIwQp9
5Gs18qlsAcGF5yB0NAKdgc/H0ldlUPnVBMZyS6n/hyG8RKNf++Neg2EgcC6MaoTG01WLLmiQAClV
DSfPlNJFwtP9H1K9ohSPAcpx02zX2dut8GpFK2l3sK+J7r2XEQYdsGBk9CeVFRvHzJakuxMU/q1J
7EaBed9cWnoku3jxCPKghX3evlVHFsCy0dp9ICYEkgBViSFdqHgnd0vxhJAkPNg25NzaD2+WzRO9
3Aa8vaeaiFPZlcjC2Y4L2Obc7es1ibT7QoYo3eOnUlQdR/Am+Uuj6Hb5l3C9G7Ldeu7ozMPirw0B
ULjto5PDoSB2JuN/fWC38a5xkLivPmDPlsxjrf6bhKlbp7loGUbL1yr4R3CNHQulBd8zrSP65UcU
wI/5H/nQM07Q5Y38qLI6yB2WpxRPtcXsfh4GAFCcaPsWI5t9lKM7p47iyHmhkmTxE+Ncpm7bWu45
dIfnI5XrEkDQG2p0Se+hRf/rzD9Zi8/dPtWHSaUN9T9i8p1ZTiZdfS4EjULXGrFbajKByKemhTUc
GhCKh1VxGPhUeBv1iSbhWWbXSe8b0SOmr0qZe1NDIQ3deZM6Cb22Yy4ywVhqAtHU4CyJdV4lHy5Q
4PNZJwwpGfaeZ9SJUTgjzIAtmELBAj7MMavFig49Z5kiDAVGPYh2rSEvtOAUrbnvlI7gTpJ+7cWG
q7Hg66sHwf4XTL7nEIheur1w+CyOIKtTIN35pSkGgR4Xnlvy/LghADFCXfm6vHGQC95CiW7VBZ3q
/sCDkutwtXD5d10OUJLfGJR15t5gCt1D0SySppA0F53ChnYj14maH7uTcvjoBPpXaYn7AJN0ytQQ
fKxH1fJi9Raxb8FgzIsWVD7v1oqwUGLa8uJSFeCPBZ/p6j8nObxyauOY5g31nU+LRzxyYzIIQPbr
WFoFPao7NLNjWdVgg7uWjVVlPUxd0IsY1A0n+b3yjZWTq68qJ8NFNQ7uj1VKozELUK5ltp+cAVXQ
MUuGIZyFopk4b24NnZ9pEUzLW7fP5HULQBLClN5bH2Mmkqv+Kh/krm8optlKy4HpLbFsqTdIROAV
+M5L1LBG1yrzirJkYJFNUOaVZRH2Qt0Fsu09p0DIfR9TtU2XNX9hcNtyWrM7cNAqI83+hJPLW6qE
mHVGJZdnb+QTQClqZEWS71pCVP9wPlA0jSl/4+fGHx/2zAOaH+CebG1RS9tyarNaRCNgXa95P83G
YNghaQbhwNerN69l67x6WUDJMKjVmXZYdM3HZSLqYqo05Y2VDZmn+yB6P+NOkOIc711CgVVOXVZD
hysLHElfqOjIcnykyGBIVWyihd/V1fRlE9zHrHvuQuRGJGnbUa2GThyFvqBVyW+O5+wCgizf1grw
+5zzsk8tLWaCXJGVR92Vl/Q2peEUR9msIO42+krmr/eIzXYhmsZMkbduCDqTKKSxpx7hKzsVYUaD
QYUmPXT4NCbdUhPb2jgtET0BjRetWjU5+GWaKxsVJxyvx2GT92JRm1NCVTYjUF/+92X4Ev67hLvN
9Fr+iVKN4Pe+UZlqcczsnVaTvP1yTT3I/LsjDavwFO3ZKwqv/4ckJqLJDnNldwaqPTzQE5ehcasH
jc8QPp4qQpsXmFOLTaB58D9Kx+02vuRX219s/bCxXSV8UAsyWTtn5JKBShfq9JVV5bhI9qTkii/y
sxcCvGPe6TYD9FlO5YZNQLy02wESNk0zBQGruvEMxfN+n29Q+7KnmOPvXTKV3cH6zdLVtiQh2R01
wyxch27D5iLmdIv7PoQaNJkkvMNI5B2XFBbspFoQBWwPwQiU2OzLJY3AaO7YjETvUIbpGpBPAWjG
ShqhMuSC4/GOEb+TKVlJxjpi9yQGjTo/ghYUHUHd2D352xz3ztMb+OaOqVdpHZyrBIK0Vg2jPFpE
JSCVPeK5YmaqOxAtdWjvlWajZSh7wrOncxKs1rwvDPUBw5qBA66zkEcsQL6ZYlj7hEcoXfFj9WFR
5Dy8cFWk6vzR91VVz9olbIrAQcTwVvIb+/EL4OYcM21+7rexvvHzarmt9FuXXhaztCGk00k5qk8f
qgUl9zVJVFqqtUymwA8M/JtU4CHbFQotVY2NhGkLAXiZ3xtzOO9nmYYYdlFbZtCOs/PzUubwO8Ip
3NTkCugLbGmf40HQ0Z+N6nMhtsGUVMqwcfMX0J87kJWlfPAm2gIyCrQiM8jH+5O9aygkVNXe3qMb
Rhc1ErmEra1C+adR53Ta1iV65xE+I88ZfaGGhX8nSxco+ZWAo6lP+HAvwZBuzTmJMWHw3I3cNT9i
hy+Grh2K7/jfO7TMmb0lCw1ht10BEKy9+kWh3TYi4rIROGrAHsiidiPgGhTg6vZGlCj6cel1WlbD
mD44bX6aZg9wT/IsbmQ42mGf5vQYhausHrL7rQUE5wBweGltFaYlcWER3dNhboVD440Ft3Udpr0u
ZgxHJESmVCCacfJhzvTtr4p4qvds/pkAsGiP9vogt2uh7gKlvzmjZaU9S2qPTWsx6iYw65cypjVX
HS340Mc7PyHBwl+pOk92MIOP4dxusSCskr4Arl8lPqAP9AhJgSaAoHmfNXXwCsL4BDauChPmJeP0
x22LIEefIByPrLgp6Bn/vIHYCxbKAZ4n56gGcxXBANtBV0Y67XuEy9VWQipBiTw1dscoCRXpUj1R
eGx/V11jtWUET5ZlNWmt5axFV8bBsHa+LcEt9GL7mEWitC+79Tv6xeCYE+EjmfTaWlaUhXkRjujB
FFcp+hvVqCXOADc5A3jMb03wjuwu9hH9WutsceOTpovH3Ee9VHgL6et4aAS7qkvyaMYgNXfv6ZPF
MBWeLiy3kWHLzdNuMFUViVjTeuxhzMKEIw6sbeRfeF3PUulq8PF0vRW8Pes8jQEKYKHROm765E6O
Fnf1sQRt1VGl9rTRwAy62yF0SsmwvSdAi1Sr2qVTn9IZhooCwxu0st1XhYNOd8sUJlVNYDWX51Ty
Q9OAPpgNVj2u/YDsQ+KAyA/aePx7IY/nWWjqeAShOJ/5k+f3Xii7gNHiGPxt6aL0VE989n5Uw5we
0uZ9o5byRtHGeJUQ/b9i6+okwS+iumD+ahbrEYa4UHFe26Tb64Cnl5a1Bfk4Xd1TqQAxpOmk7IBC
U9AHF5rH1tAvL6vuBwdce0qV8LBaCvfWHHsUaozw/zRNI61CwAv0eQ3YMi9777LIdIC42D+jm34c
0Xmh61MdQwYDwYKjm5m5njLYMY8eSk1qi7w71uUQ3nV3HNQbCYCBlMzpF7lyizdHCymvfXFO6VvO
hFaEGo8RSNrtYelYOxokY8obdqlDcHp68GobM/1lV3WQ9YVRacKo3TxVSMjb169mOg+AQ+FpXwQM
ylDM5XJVl+ZPtlJRM4lDiS6NUe4yBi3PB1+iesnjoJDWh7zFdT2fhJH8vYfcQ2nPBJTt17ulsITg
kEyq6SmS1mlTK7t1nFqUo0dKZm19tBTUYanib2zHP+xP2ctpWD/4e0n5XtrGNlyAHvvsCylfGyEV
dO2FQl/Yy5tB4hbOM6/l6nFQeF4PUv1bh6eflog2DSjL2nGvsv2tkfzW5yfGuqsX/CNLP3jQi3/p
4dfe4MTUv1b1VChGUmDQvTAb+6kE4S7pLLItoyZQ1v0uyXTbmSyzlMMuLS0bNbHCsTdJ6ugrDL0Z
/pIdTj6wsIx9mAMTY5BUFnnmI6LqPkWdDoeyU9tWq8y2v+t8/TBJ4+tU1/FYlpAk1aJYKxMgIIwt
JTkf2oPD2W53VVUY7qbhZe9ULCr4xWgEFGqYdxesybSuTZqzadDzCYyJjKQPTPa1lyoJqhYgLVgs
CygIVoGROVAMSOSNDZMR3JN0NHf16vhV4yFwGrf/6g/QDNxUXXnC+JiRojvRiOMrq6rTb9r4zDCr
j4Vs46G0SWsTxxr5HiES6/jGjh5ybTPUsKDpZ6Jp9aR172pWxJ1f9YyHEglLawlpF3v9NG9te+nx
mygBKXRnY9gmZAkiD1EUuVg5xmdWft/B08q2++V/C/uKMY0S6cFUiwfB5ibP/9TYS2kje0nZtZLH
CzUUromroTD+euEA173uUhArtmrbjkXiK8A5gKVRvOuy35G0SHgyCZHGaDa317J7zsOHaONXnz9T
4Ly6C1BSA8BR2bC0gaDTi/fmG9prTuAZHNQ5vXP93DSoxNhxN3p4mCAXbfjtlnAzqNShlENT/aKd
Gxy0Xk4panI188qEAn9a9LD2VeTsEAPsETdY0Fa55Inoye8K4+ExNjUflMiuy/lIda9A14y5pMmb
xz9rAyR+Y+lQfbYQlzCWQxjVTo0YnpSAWlp3XcTRzClG0Fk03OUfKFVkkaBHLiBOXUW6SaUyMXsc
WB7wbozYm5N64Vh3JIo0A89sFDaEvyA3v7CPAwulQzeF0laWGi6qDxY4Mt5HVXxin+ji3tNnxzH9
vwTqOvFjd0pT2F7I/Xp3IlYEUQz3YT1qnKcht58AsDeTIliBH/JGMFOMwVZeXXb1JeMsjO8Ob0Z4
rJvfxyE9UVEJwMVrNK5UqAselDbr8H3HF0K5icQtSDrm9a2ymxBCv0vWOVdercUMI7MNtd9YIWhV
LKyKIfoKcYIjwNSJu/SWSoccbTUeQ7/dmRqCXhTmKWZyQdG2gjqkHcJF/5hvLWjndV6DFN4DUrM7
2pZLSAn94klwbt+fGt5ZAuYNncAX6jy5rNSH68flI/os+jiORxeesbgIezXKNDTGjHXSc7+cOMf6
lvzMoGM3vBwUjNqIJ1gs6rmb9HnC6tHZwDAfeSJAIcq2viucmpd4mv9cSDnYSxsY6XsRiVrAyLRN
fYa533/KKVJ1f1ejQWOG2Ik6aKR8G+RKpetprQLW5i0XvgF+NEW3pv3KORPv/n0OjrR8xm6AU6Ho
a9MABqwVsXTfQsh998Wx9sYDhTjq9MxBu/diJquVf9AhePFTYjw2/O+UnBvlcHQPU/8Xsf4rW/3d
27uF6oDwOnZMhCJ2rwB9awViLTeRq/OmAW4IDLnZ19u3r0mUvt/xCm8asoYouMPPh4lV5z8X5qC1
5BjOkL7gXPQsB5EEZoifTnh8nmJaRITekhjp9yWvNTSQiH5aVVxiF+MAiKIMJg82AkC9U8LzBv68
4WRbGTHKcxh3dTp1eWSUBvRwVCWMlWIY5kglM5Z3TYW7N2TjRFWz9dmbjhonMnt9XCGMHsc8euxT
GVa6yVkn4bB5aQa+cQqNxdDVYaNJGFJmYo3L/RCrWQDe4gATAZWzxovOOc7l8J3ag7CJ8UlW7Qz/
85NDCLEzgbrreSgTZ1rI1bwkvPLPyeV9ziDOraCJkZNOuPNsrwfMh6MrNncZV0VF79VeJJlsV2AA
yUOr1wrgkCfgK03HmGO/+Jzt7zqmEUGqHG24iSfobkBagvznhDERUZcYHjSPgBJRVgW0E+nO7rWs
87JFJXK81CSzPknsPJZpoDfvdCqlzFYecHnT6X1tmiI6RlosfVzqC81N0iPlVQqbYgO/WCv0iVuV
3zzR6fbUWMhqOG/nAZh4Jp74+/1UJKvbB4RIz+IkP1hiNjcMw8uNxXaG1RRhEKZ1Gmb/xD7tiSne
bsuRZ+NuSzf7OuEekENrZZhRvCcFWztBjK6z/nzkZmB87BKfDXFSctG7RTPOajIUhWWlqTRjST7g
SHmpRZ6fV/ZmjPlu+0lcaiLWlEnXsJo0pYpZ9UBSigxbCNhwek5ILvDkPyS/i0y7dAbOI1ZW61RX
4AEI9OnzulQLLG8JQ73ED02UFZ0M7sZQG96m8R7JpSzFKVV1RBnjXgAk4OVsMR3w04BLA9nouE+u
+4gMhYxBh6AUSj49fwpH7Nqvowt4HaJTYQs3zzCj4s6KyYV+jyIrWJnqWveIMJ1qXpq4P11fXHhy
dCFDcNKy/GLsW5Ag6DZPa+SjzbJB1RxrU5eJcLH2io6vctQsuTwuHBnGZ8EvJHUSD8Ed1TPyHXr2
yXD6nAkc6CcbBLb67BvajYoRwnOPeAZ9jcuSoOvQ7nTz75g24tZUW3P5UsgO6t6rCJ5J5TIzjTSP
sYmPGstD76/T1DOwTBxzHf/kCNe1eNiEf4u8BHerWAJi+oUfbljSTaC4zCxnca1ehBiVsA2pdnuZ
vFtcrTxwrdDiqZribtm5N+8T95YsEs1zr8XKba92mD0/dapcqcodcjmy94UDeUv5vqIwV+EmsGRR
xmzPU6FXCIm/EdKABX34hY7h2sgEDeL+Htp7jHuPxfehDLCnCucnnFcg9ZB+R+jHhWLm75mvcC9c
c+VSxkWt7U1JraVJQUPEMxg9U9LjMgYOyzDYM6BS3CxdB7JDHzM2GkhalRHNCRJ8eUjyJ7y3MBiF
WofleVFLvQ/zHVQB8yNvUJHLNR1YS/v3RtANcQUpi6t0aqpciyL2RzP4hcG9yMr+JaSPmNRloMZi
lNXf4xgjRwB8d41/0B/ooZv39bwmXgV9jmRfgp0tS+qRqEhA7OHYVOci5YPZ4psqF7Sm6CbT1ooG
xjI5LXOW0e8ZkqOmJdp9zB6PKOgzzrVw7TCbrzBN8MBH5lOLFTD/FfjbpqkVTQMrU/KbA7XeNCLJ
6vRbnCSUIUSr6rG71apG3iQ5nBzmqwV9udyoqvG0XpshuBqyHnvMzBe1VTjGe7QEg9JTTVEwE7e1
fRabOhsuV+LsXCa4UnLbpkv6L+JtFTI0rjf6GhtycSaD582LM+pgTdDvLnbLB/u5y2qqkFaE5kw3
eNH5OVVETiMG4gSVJr2tN9eyM9CKIEzvh6pvzD6E3p02DpdhQjxU9T9Jns+XXni2QwmCUqohwBCH
SvmlsGp+6KfgGhBCRLs5/4RgWPAeORDcqVFU/qVuU4kX/YfY59wQDGRYgABcJMFmLJ0g2DHjjxbX
56Mgfg5qGfoapKPPdfSAf9q/CN3xhzM6KpfN9SH91fJeJttYlkLwTJuP8N9ziMahkcqitTOBQ7Ke
1qPpMIi0fDlimNdEWg8UP9ua02aMIChJlJKDb07lVtxpa/hxMCnoKSMKMT+ldGUL33B2QnpnNiOW
1PnFM/xNDy42t9981cypoP+aWjoH69FpKenqGRh2GigD1IrrmbgkLPj8BT8NAvE974MUNcylHzYv
CweHZdzEs8LRjsLIC0FEj/HFfeBMKrZK4do7tBKUtbuCeoq62RWclX5D2/TuVqNQ5fuAD+t8qyY3
09C/FJUfEpnhnXMDivgMQx2n2/0xPXZ0SQT8TRtLk7syuQ4H+LvQv+95TiMLPePJpblC4gmcsbOS
MF+JDlgYImA+svBVRsMfXFknOQXbAENLE/AA2ftJ8CkWSeRWF6eOJaUyy4kZUAJNzl4KsnY6Dbka
QCh13/s2U4lQisQjCJLAtkZEbauaZQ4zK5WM9FdUXqu7AIOkEAmeWIKpky8SHQ+h0uHSK1sUOf5o
5eIjU4W6RcZ2s9ermyfvlTOANJ1IbSkD0pRMkqFelTcRwz5hnLhoJOgHmrBbukgYB4G6i7t7mqau
c6omsz5VSxFErzZ0TmME46XcN+kxvGC+tijLSR4jKcyNf5e81wQeA2CGCyZDJUpSxnIBg9Q7glZI
zmXGiqbxSoDOT6BqkPXrD/RcoEyd/Rl3+eZwVXCscgkTSLP6iU1Ei0ekgd0A8jr7jqbe8az/ZGKX
bAul317R4Tu/90NgsMj4o//9z78bX8TDYcBjGrSCi1NU/6q4EVdbe5SN/tshQaQfkml/jy3/lEOt
x+UtlDzQWqG7BoTbXxLbqwARH5Jf1Q+LMhDDO6bHFqWPF4TWNKs/5Bt/rND4e0KiC/XUeI4jPqgS
QOdV7ueOb54mtlMNfL1NpP6H5misM02aGXzLyte2INCbYKBGdk5JSFtmNdOOwIhRXzAwQciXd644
5Wo9MdgCIJfJVDQs75X19uytzFRbktzXhbL/o1v4KZuVn1Qpg+A/dAeuqNYEc3mItKilUJj3iYX5
3Px3IBfHS1TpuueMD4lf0Qxixv0fVK/mJb8oNXBrfEmEPMFVdgUllfLfEWCvXIDB8DlOaWDcNAdv
2nhoVEIITqKT1OPS9NZR57iO+mMiNsCPE3pFRewdjc7GPnr97Qv4LTBvyqaLV85fFs9GmWOVTaMW
WzXtZv7KvBF04nkJ2HHUIkNZ/sQh7z7F2jQ9EQBCrXx8MK+QdIwiG/nVlm2i/ylwA7wfChg3YDyJ
eWIgDS8R+fdUR+03k6ayBL+Dq2VJ8hf2TA+Xdv0e2Zj+/6YVxsdU2eiRMu2Nr+WQTzO5Uazs4nXv
3iOaNJM77vE1AA/MfDeE8E9ViUtMXRIwqpS5ZvcCW9ugi+3V9xFp2Q4qqSwPKe6KZeZfbK21cv7m
hL5bQpOkgbi7jMCCDvgFGHo9T6jvZlp+pOI0AwSQOopvrz2zPD7+iZWPz+ksrDydCB5c7OFJpEln
472V7BRcuyH3yZBp1yVfAR2gpbHZuHmDtwPk0mdA0pFhXwQgoXDjZyHoybMfi86KPNtywdpDslK7
rCJREChQOC27aKYqLVhj9D3RSCQsu/1oYziscJGa2P3ap2hLrTBdXvausj6jajYOv16XxksHwiEU
+1zkh/Z6qeebDKYCALguWYC2B3rqLdq6gA+jk8WYCUjEKnqiwcFv8ZNmuEte0gkqq1G9y5RRLgtr
RFOn8tQb/kUYRXgTEOyJW2IE+wuOgP4vBiRbZT+OmjLfaDdmae9l8eKX+H+v8KdTkroQPb3VKtqv
bbWyc+gWI2XfIc+Yvlva5GwytUSCEHC/bxHW1unZLxsT4wSxmBL53m88BGxcukfUIBr8W2PfLnnV
6NMX3i50LpPBCmKivyfLFPPV9GJOYe2ei3rzhVk1jpDZepU0lUGvAOlmL3T4E1vdBPZ34ySMIRa6
l/N7FpFolEV45QoPHOuO8B1JPF7cjotFdLLwyDTZUO3y25a5yuyu79nkIzuxHZvbYN81r4Lhm86g
0nGd9iKJGpj6Ha4OlZPMw/3jmINZCFLOTaYUohEHwCvnfP7XH7CbbRuTW9mNri9rhJtmJHuIzD92
hw/owhx97zTQ4NpY3qx0Jt0jSDhh9a5Vty/t+wpHd4HOdo/A25QSHiQ0S7mnqv40uJa1u+eSWMeR
22P3i9QCQmvO4nEppXKX2UfZaQ9rLPz/Kqg/5ZYDeF3yijSB5LBQ3oIGEeKWKGqMTouxn6LDUEJW
KHiKerBaGQmFqOJaaJeCdnneAjvi50cX6hobjFLVueCXAuRDqqqygmqGm1Hn9/miMGszJZW/53z3
FZX9Fnj+3I7QYrR3wXfX794Mxde9dN3aveYayB31m6ddASlRmvxjfJdLDagoEgLOQ9OjY3dAZxPU
VUx5VtWQnfCd32PzgRDz16E5lzQiCRbW1td/oEtT6teDL2aOtx/D76dLoBh8rL7i37ZFfwN4sIJA
g9dgDm4tMhTsT9mmw0utuKM/hW1tLO3Olw4refqHfaidu3XG+bmKsyiMkV2Bw0lN5TU2T1IPsQTv
h+KFN7sDQBoIUe19yJffOiuEkAcCQH6Gf8Q0jCipJq2AcfbgNb4fopyKlqFf1eeBFSYPPgY4SOTT
d4bVCOneV5PUrT8XT0Y2qSxMh2q7PI/SUWBReec2nKKlWgRD0EK8K6ggzJi2hjP2BSngI6fKCGyk
EMtFWKYx/MnFyfA7LRtQvsKzDz3ICBmfBuSBNAPO+aLQKTBmOnXTu0dA4BG62Vuk4NPlB6uZfJ3w
ZF+B607pfuf+TuWUtafoQ96eMDBPZxnzGIiSATjGamXsZkeojMSqUdMoWUJX3YpQnlOTBuqzrMXs
KCiru7Xqd4XO4LRbP32dqtDVzOH+oLMDGgfWz9DO58tQl0mgJj4Tm3QYOKTfJYMcgeoydgUB/aQv
hZ7reiL+0CkGpputER7203UvKAy8RPu7QeylxZtvEflbfyUNbruTAN9gPFBKoyzvgUQpE1Ou6r4j
wuI3jVfO2y7+2Nd2kESrGbBKamHeTqlM3JdzPZxHIorlILKWjGC2OWUKAeWnTpDXoC868sFIqYfz
NDQT7KNjTSOKS6qrmAbBLqJxXCSxRskCm9uH82UYGMfGofy6EeKAO9X3zoRGPgZrDrjpQRND+Vz/
mE+/nIzAAfRYkatVVrpPpvvZ/0Wce4HX4YaHvB0+dluPu8popkdp2YiFwi/+l7dQ2opmfMTHca2d
WY8VDntFEcDbpoiup6HWjw11jWmpIPu5ly+2YuEQLwbkKgv5Xidbgeghn+Xsta1RL+hgDegaopg9
EoPiu5JSFnT0AWf3V2fcS9x/CDIYvxaUlQUoXF2yZmwUgH1Hwipcw71E4yqo1wcL5X0xxebQdtSC
1kFa5N1gmDP8uKeK3UqZc5NBiU3uGbmP1RM2kwq4BfBVwgmB//JE6nIYE4HMGKbq49LpY77sDy5i
Sc1c2u9Pf6LMntFw78EcM+v+NPy9/N8uyFIr1rrfYltrpWd/CHpS1vAox1Oea6cdDLBj0e7y7kBz
jYU9Fhrlbt5G32+myCjAKs7mkIkem8bhp9enOvcpBPTq
`protect end_protected
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dsub_3_full_dsp_64/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 20 | 94635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
HCSQmAapELPf1sBJFgFNhgvq73K3W3UGtfFvL7obu/9NizRz26mkfd9wNe21bmirivGTwKeZvyMe
zWixxZrSiw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Tk1PatICqGOpQtQ8oJOeHvG+wSfV6MFfzUR+1NxNiA3D1oXGbbc3gTGsYeri9x35CpLHrY3uJIMS
sskF5MZiJ7RqK1c31dmN3ubJJ35zyIvetaYotC1izf5s6ofYhL5l9laNqVTgpIBd3otGkPj7WK42
86gYynjSjGGc+HBZhcI=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cfZeSAapGTxUQEvxn2/r1T9bFdYrx2rPwOioTJgVQ4OPGb3rFvHX8Vp6MPky6sR+Tep2gIB6VvvP
GJ5ngtwI0kzcD8i/Z7LqBs3I0qgI2LxV9deOeTUvqf7Xj+AX3Me28gLMVyg5BeW6O/GYGZS6IF77
zIAQ05cyjTCdzU0eisQ=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hByo2GW7W1vrbUqX0oTwbTccL13floF1xp6jmWwfhWqfIXbs0v8cD3nYTIv0ZYmWoiTKFmNd2sTo
hSJnPp7TVyR1qJV4cGM5eHyJP0Oa0E9FIgOeJbf6amWtoLToYMeyuyPFP2PGgWxiTnTHvCRNxcee
r2qILz+Dre3Cv9w+px2Ly7XdRgYJ3RzxQTc6eb9jPdogRLqbWIApE3aukiI+xrAOOeOWDGbHkIGi
PEbEc9hjcMTJGsiBrr+650bIjmaHov/vU5mT7BxlWt0FfFp2aUWxkbKxh2AZTOD4yzu/CnaGjY+s
amPG0D13N2mmb+HM77btNBJwICYwyT0dib12KQ==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XVZe1Iq1b4q0pJb7G1HiRPHToYeBo0kSF6/+epE/iNiHS4dXLRGITekimnvUz5jWC64VQVuw116b
q9OWkuBBNOouYj7wEAh1ufsn0z3zlkIMYNtGWNIdhLZl1p4j0bK/HvisFljWeFoyO80WNu3avx8g
sKSpXqMlJW2EaFNf4NWfq7c3muHUQgSgG3nk/5vO0zESapsSTn6WmN5PuuhhAVEm+UpYjnn1vaMi
FCcQWMu6hrIFKlyiWWFj7aF9efNcYZ1vxJhIL9jhKm6ritRw5ekFlEM5BpA3Fo6rdQML5P0ZB1qr
YAvM3UTGIvL4FyuNcsavn2EM7H5R9TD3b5jlGQ==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FKZGFNGDGgbVQmf36A3vvlEeMnTnMkVMn0xyNtGAe/C4BYiio0GGVng56CCV/s2VwIm86yFp5jG6
OufL8mHaK4lz/4lq9NjXNCGWuIw3b9dPcaLXw7iwVjULo0X5P00dXSClAogIRSQDMhMifhijdjna
Eb/DWk+oktBkXYiz4Up9+USfCbQs1TybctiLJiIo5ZY7v/TiA8q6C+PcOae1te0q3hmRyJ/Sfsaq
/hJvDUrmS+CocnCEQuXxO1mKRTFHdj/f+yRZWld2jM0s+jXW1EGw+L492pzX7W7U768NObMW4fwA
Uc/SSjGIhOpg9nMGC+XCI+RN5rkAFDfhx6kGMA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
pKjKQ9yxMXDRjXEKg0nt75KpMqHxlcPp1+s85YeqrqVYl5pOJxW3Ga00rDbgkABHmOgn6PchGFbr
eaMVQeoFcCFKZXGvQMCnbXtlMJyzWT1noQFNtrE+AJhueb7CDiGwNxQo71UTANf5zxjyWwEeyvKn
MejF1pqbzRicYPoG/RkgM4kXZpRtOQK6N3awoZDOaFd2JJht2HuHOsn7htPff65dGss/n/I+kEKg
zQywfr2Q0fE/9l8JlKONQyYLC4RLl79gg5ICll0Wh73DJJn8EOydDJM/C3O87B1ufNTtci9cOP3Y
y7/Pvf79xm2dNy+IQ2WJUKNbBFZKAojd9gZXqmIz86Nuz1ekBneOCvIFgDbGMitx1cfC36q2wN8Y
pdnTEZ3qUvOUbeNJXGRoqFH3HOiT3b/FCJTUl8RCibnoldrcJ1jyyOMejk+QnkLRokqzsf8JsDR+
3upEDwZaaoVZT+mx49LVN3SCU2P9JgpqYXWDN9cKn1WO/Ix+dyaHmIm1+8AVRYPawvT/5pH8j+UB
BXRU6dji4Rcqr+7BqtEyhaQohWD6dCxfeByuUqmw+1gZM0utAEvKve9Czd8NvsEdEZZ0nJi1SMOi
gPWEzJoLfVPxox2oE/w+ZlTMxjHeB8mss1yD3Ga/0isCaU1fL5JzbJCUlDyiClzEVw8UJ4JgxBBS
NpujZ6aD8hOUyCO+MSKCmgO8no9ApVkolw/wpWj3gxRGYWr8qo+rnM5OD2XPp9fyS8666McMkoOy
0J6g8PY2htn49jSDLA9FScLHI1/ZN+hEmBWgqzn/tO9ioukUSFkXeClAXe/TCQBFm0NKoOa9GKr6
36BFj6WUW938GpT+YBkO+1PFwb8E/lQXsVpJRN8BpRbhijmZTauxQZbliAp0V2IbgF21M/koso4A
YERKT/z0Iv4ACibGixFE/WRryLG/ydrMP7mnejssE/2PUkZKGgCnFcrXHMI8cfODV1394q2EiRBs
lj44hbCwxNxtbVqGUI0r0WBYD5b6fihc7E+NoqH+8aeHjzoPsV5lZFBAV+eFAv19vIWicWtjxDpQ
cRt8goRM0QdZeVJ57/wtZq8/s4BTTfZbKHBHyr2FXl+siWAjZ1dq7NQc6YFeG3aguuMPFgzPYZML
ZPLhr9v6Eboxt3AGDwEaOyahdfzGLaaKaDoWrcLQL7u0lvNIaYTkNFPyXftDNNkud1Vj4Qd/n3hM
so8IueVC8H5/Mhf36L2pPVudcgDXtKCJOBDRFVclYGeVgo0atY2njyjISbjQz487kLhQVpy5B7fM
t71kDHKY4i1apkwyvJ04qXopedhmKm/2bhMuDGBtC1ZrQGOnMu/58YHNe8epmMASQlFnG1eesLkr
FCPPTn5bvXIrSjvd4SM/wusBtyXjaCHiuwGX2XYsUSIa0qe8n1YRxa2wz7/EPjHu2Fmqu1tXYW7t
LNZJN95KOF1mEF3Rq56vrjBOVt/6kSkmF5FR+tmvBgxBW93SV9LGGGbZXWq03njtwuhVOr4IhDvF
m7LssCudhF34JDN1BmRaJmEosp1kv6FmXmgvX2MEl+iGrMoQcbKp2QgIkAQNfL6PnBw/cdivaUik
WnnYQTcIG0jcuTt4lqU5N3zInOcCXHQzOmUKrHIwK3vxFsfKXn+f3XZ9ea7Ik9yEjngtDk233Vlf
fdcmP5WrSoR1WIO6dVPt4Zm9kCWoml825wTcybg97jAXVS4+NgByCYgvO2TPeL1myE/EoTxZxxuH
aydQ+xb06DPcSDzgvSlirFvkpbgV8kQrVJYIEneO/g9QIfX5b5z97Hl/yWy1k17Ffg+lwJ9pTg4e
zcFWenRSqpRSrAzpxhC3pXwyKp3jouJcbeTKtYxXtfCpjAyW1wRuPdOSPk8PSvmji0kumE1LHYQ+
N5CIkfq1loNJkK+Cj4L5uyHso8tby9qYCswq3bJgDPmnpINxlfn+fH8SPpjU0FRGDjtLXxEArLkN
Q/HU/v9pxs0bOe/9k30fEnvzfeJ5QfLUwEO77+d6mI3K5eSeipUxmBFCrwcD323Xh5zeFtNdOuPO
MGDyK22SoK8HuIpfW4E8EaFvMe7VzAmWS1rTXRqLLNCk65mj/fVYKM4zSHyTEZI7HVvaC50nWk3c
yquE0/jNGIFYhoCtGntCDaoRDijKjiQcCkBDkeM6oKDILduVwKHUVQFfdTlUvSMDAjQpTUNokhDF
sGjI2jl/tcsmpCafxShAB0EtCibNOJxTGB3/y8uXQBPBxN96MUwOE+yrgyQBjw2NxSH2MzUUaBEf
u2TWSA67OTtDtqat3q6Luv1RmcHlU5InEhc3szm5YMYOjUSfuXDHJpFdG01J63I35qnc/aHNbRYu
B0UR/l5lvIzKcNnjwYo8Ph1vwvIKR/9f/tMX4OSiFHBVCZA5o3gnFIHwxKGbaTJ8TZ90eufYLAcc
sv9ko7JTUBNDhzrIOwHKecIDM8iBPzfwGEgFnL7y5QrIquN+ykFYNWZ1NHwbn+rNLCcXJypf645V
5y7Gihp037SGrx594zxycilov4qEGiDBrQifMcUsmQFYBRYz//eHif3IKHwqpZU59i5thYo/1PBK
ZcHrIocdywqMHuy/y11v0tDdw1+usAfs9bfG+mEDspRGEx6HXhbDnKKsj1VuzSsFDfyLyJpCoU7e
e61ryJqAQv4HuAPGEtFNPjSW8vVywFrM173l+HemYRkI7WTpA6nyCMjK1ul0LPtwWtVVhRK4wSI+
2d0tVxfSzhJooPnnB0Fh9tlsJjj8sSd6JnFb52+8BAiw+a+PTEPN0wdtkzruvZiqhBk1CAMdBuUj
Lvg/6qdk5okrN7F+XBqUB4eNhIJ/22Hhpot8BeVfyZ883SC9DOSp9HHSu0YqOx4638WM96eGaViI
+AcatS3CyIphx/TXbgtSXYIB+ZxRe3kM3DwHF57qQ7EmwyyCghBfTrqnJ5kb3d8kIdjbcr2aXQTm
Gw+u8ex0IG9Cp4A9jFcAP52iG+bjFWoTuSN+HNZEAqTFDrdf8uv+bZV1EYwb/v9gAmzuCXeDKB1r
58PIts6+9/LwJ4+B1Yosfw45Vr8teU4B+3G185KhWCBMbhG4ybmTMNucODo/yzzt6amgKfnypQnB
GY4H2JftVRmPVsRNYM4msSyP1DHazEubuVfVwLwYvNOTLHybCuOw9VEnupuHOP9cSgg7IVDcmb0q
xW4IsCeYDyzEDFFqkYyRGAPdQtRJtVJWRZfA3/Z/R+D34wLbxRFnBzDV2MUrKgaA+M1n9oQsiZzD
Phqh9Mco617HFF0K4WH9N44mjzuaPxMNPT4dnKLne4ByuR+dB/MIxXOGmyQDSwGAcC/oZThXJk76
47dWcKcdsh4XUl6jGQc2KonTvckShrR2PhLH/H/riSN4py1+sL/+v+Zqu1RqAzbUYxfX3nsMXIgT
mWMrqjLg/y2LUvkGBHCZa9G7t0tBvJjKuHWi8Yzx8dNigEooSpzHEskKUhwUmAkPhAilf7ihZ/lZ
jCOSVuboa7AVigtNr857e2mBQ/No+Jb8GdN29ueSGv7nOOyIqgNNmOedpdL0BsZqtGmSH/6OCmjZ
kae4Ar/FoHyIauu0d5sRJEXuSE7UTCX8cAbH3P89kWknc7xpI/ZIdcVSiW8TODqBmuA+4WJuJsA2
KYJRqvGI358hhKqZ2/siqU6mu+7t/yikS78+SD/4CbDT3eakNsURhMg249yWl/OPiaG4T3wOpLQ0
CYDWUpSYET0yfBVTH491raK5MED9KceuQHNZuHbb6FlNpenTYzMT4Ms7ZbkMqNtLyVNicCO7xDe/
X1klZx96BcAlU+eyvDtZ1doCbIszVWJWXXL1BT4AbsikNMq3PNiuaIFVZvXgNBaHSPaOsUEXXJhF
wjBSmGczETL5GaaQ+5w0+RxEI+sOFhkLI8Ve/AYznbvq5RCDlMTlt+ZQG4mMe4S4mTMXPWXw1X1d
sHPl983C2/TAC9gY7gip1da3Gno3lElnslxNl+uCCuq6aiKywbs+wVOkls0BtNEAyW/4b3uPmObf
swh0fjQZt/cOuV2J2hcIEf722au/qvs/6PJlobPMOA3LjPTZKfohBTK5HouG/6Taici+bGIzV2Yx
aorWAn+JCEPWIrLvrK/GJaf+hxA8IExZP6iazNzATlltFr3ArztELM5vlJos0iewpu9YeDBSAG7S
bTAgBRmWvXe6XV60VzbgtLwZKzMgS4gl5NgZMvklN5WBhRcU/Z6MVborEXOrw/nc0YtHN/n9/lH1
9Q57iP7FvqFSC9LJDA8HhvR3KPQfi2vEvgjcuKS2xliareEi1I2tqDgeTVR3ihqt8IrSl+6MpT3z
kc28FcEQETkACVNmTySB/Bekr9xqrpdq3De+csUUyqu6DBPSy4Qm0CWSeWCE/WOXuHXro1wwdSFC
O8ntXyfiG3lK+PAi442OCVV1edO6jwaEEue+7uQKzX0GaV76rSb7rH18iQe00ZmbdvrYOddz3Ezs
ByzWFYy3COG4DnTQ/lrQn6QE4aUfCSYf45BGrBOE5wF6rnN+4UahtaiXcup3NGcdh1hfL22X2sfx
0R3MSFjZH5xrZ7VYDwGhOYhg+ymsPEsyMCCGhc4ZW6Z5Eg++wM9SR6ZgwJ0N6oggVj9mEC3sop94
Iuh6Xqnno7djtbE8SB0JPZgaZVRdYpr3sDqUt3zGeOwdPgyxBfAAlhzy95XcZPVNC1M5du8b/OSX
BDChn2ZIOeCeneQmSjM1XQv96oDAuVqaEqxzgeZVMWcXiEkaWzCC++U2KpqsNNu1E4NO2u2TX1Oi
mZLMameX/Si0x924QdyxSeClJAGv3FFkxQ0IyCWT978WDgRfLBzLyq2tlhUZb2paDOtre+vskV41
YQns2ui9Bz/3VeoyHr51gwDMILImaroTvgEc19QD2jYBQrzSE6SycoEyKVrYxep5BD2mLhTpYnhf
y+c8Qhw1rc6BL2awNaQ5CZ8I+k6I4j+dK31vHOI79WhEYrE4ShIvW0anOUJSItVUUPH9TCU9nf2j
FNnVDNGcL975XSaWgGuw1CXw/xbqHyL4NjG2UaWqMVBXbn30pJhUP5FrkY6iN5iLK7cVRSyAI+JV
H5KSt4zjy5OZTb26uIohuAldgzIsFInXdLM7wVbqp/3vVVznVE895fDxkonI35r0SJjIiWLry9ie
ZMXZGDb6H8WjAb44+anN80Yd3bbnUTTYRIx+t2Mfo0wOcz63xVnOSU7jBHe4boTEtx2ADGrYw+3W
dxyb1FYtSLlUPsn/7zTUyGeI4NqYITaURZ0raQdRA6pOnW788aaIonbUflGtKEWWyPwBUlakirzY
H2GFQqup+A1ipkJNyXdrcWpyc5NQ+Sc9Y5rn9cMl43Y0nC6rVpdkv/9Lxgn468ZPUmeNWit1AuNz
K/nczm+sxNc2qe2WRihNnOOhmjL36LF+lZ4rS6iIC6zlT7ZddeXGzEivDMZ2uv8EDuWFA4DviNst
zvrN6ZtLvtxXz5DNDwDZ20teoxW+vypjctVN+ir1i1jxKX+wqma5OL7SSNfHpw4x9FLx0WpWIaZD
zpF0VdiSMDvn2l279G0w7N0zDdsV7bIUgYJdSklLhrjMRFPjSxmwuQ6xXlc2C08cf/eyjy3j2rSt
YqL8Twf/wGavXhPHTedowweI8B4Pu9XU44ZXvDkDptMMGRJ7nhjMlbYB0n5PDSTLqFJgOr9UiZAM
2yLQcqJyKUkYAK4BWM6E/X2VGmJgFsbjjGrD+gOSWt2iaqiM8pd1WuXyaAuh4Y/mBifY1xiOQBv7
b5xDyJJi9+1yXcwdeXAywWtPnqJ+j2gvkU1t9X/0VABgQdbLvrjqLcFPKIPlPZRLJrFb7X4/ZR3m
XqNyD6EYgt113MZuKcm1p5dmIOSKaAXVXDIvrdZ67/z27fNkpoD7wQ1O/B3uY4u7tquSKLkeFctJ
hBzOyPd+7ljwuKs1dWTISeRKjXQMLdRBf6KIxmX/SWgZEliGJxQnUgq5WWy/oQ15XJGGn/QchknJ
3vtG7wH8PmeC9msr2cMptR8bLjv4HCZz6EuMZDURq765rO32By21iDrJIA4LwlbHajqeZXpH28A0
ZyVVBbMKH5UMr8ZqLbnxuzmTe7NznG/EYJTPUrj9A+D1+SjVswOP81i/EgdHQ9BJJ1lLo5LnX4Aw
c1u6f6hFKTC7+Wq9ghB46KLxAkPUj+ow3VyKfYt83hllRh3bO18Xo2EJ6ySeYaWUl1GfOR02bJyb
QCYQ/EURwoT2TmOuqFwpxMn2hn1cSK77zQ6YfO4bTcF6km69Fj3pLdSxZK+AOkjTfBR0pHDBhdfJ
MFrbTWcxrlFdnA+0QuGiVMWwOBGKyzKp3VABtvir36h/QWyS2ivKwxVKvIUqroNqNK+Gvt9UISuE
Sfy5iOxhdIW14HlfBjYMijbmW0eNk4d56I64GF9vXtrIQR+E6ddyz8OVj8XtneZtRq7m6SYpuRhG
YpCjRPs5GYhctrCpG60lzTjYZzxnz2GZBM2Tf8PDzjewlHVgH5z1z66H0br05Gno4J2USreOTrfA
a7zvtJ25k4P5pDLYPl6ilxizQkArCquFwEfP2YueGtcPXJ1UvvM8W0hLrllXKRGa2IUNvi10845y
hXk0ZMOWwHpDIECmlIyxD8S+MTIW/MEMsttLv6+drImm5oR9w7dhFb6UYzfiTm6knBeejmxw3YJO
q4h901lLu5/JHqbXmsXve9vuJRtKmTK54J53hfTjujHwKxlD3dj2u7qWM/CSFJscouER3JgaCuGo
VeS1t+D1MNrfIPZbBtrU6nASdP1wVg9RBRqQQhmCUZqlW0SGmoMY663c4jcnDLZEVAodIJlIvF2x
y0VB7thcpUrPO2k6gOYLkJbDKIin0LhCLtF/ar3OrpUM4zgnAkEZQNUXiM9bsbpuOppgZ9vO0ilV
Ear+W6zD719XAs72QVUTlPJBacMKwWcY/31EVhFo2eji1mobF0FOHPN1vzi1qum/xHb/ujquWwcb
crzoSnfKN+4FFItEKviCZLUiTZelCQd6s5WaWM9l/vuL+n2IbP1pao5OLySYIXxu+lX/H2FEb9o2
Dg2scP8hT6cvJ6ZjR4C6GyhrmGV8N9KwOzP2bdgAv5ukLfkJCqI+cQ8t1vZHfAFk3viibW7hd9Gp
WScrGH7UUJuiLLwHnYy2jlBE6QTnpEmItoxb2aVmM1pRAMYqoi1oxcwJawNFcEBuA17jpT/bLJ65
Ms8SKd7ktaokXv9co+Ln1wy9HI/j6/AJk5+gzGe1tYMB5yECj5UjDS/PB8BH15Qff2vpZOCBXeg3
94QbC5NNPiZWDoK1jE35Or7+L+w/ekN2W1aBEHpBM74eDuOISOtOpZkD0XJy+ZV0wLHHLW2Bbn63
6B0g+hgSGtTU6An6xJrGLQaQI5Ba9HxG6HmnnydmSCa+4jJUBiRLjtBJ7YjVND/8Js6giUmZBO59
E+hFbFG0OEDXpmoX/3N7rtt656FUNe3GjnSAZDJzeBQDxKBzqrXtUIj/llSpxuKBKJolutTrQUxf
bTq4wPIrXEU1EVuRydYfKJ5UIRUj+6UUh1d5dqMqXyKEoNzSDqhGjee37Rjlgls65IvvkHyZFxLI
qNF9Gm5jFJy/+0xZOqSnigMTTRzxmGPBGx19gGmow86+SffDalVjerXK6/IFIiixQrMEFgRYB3ZX
RIV4JeerH2B0NBynTExt1OAIMIHwoEVnBs93JCfaas9/cRmSpPXrBaCmIL6gGj1PypVUOv+duz+g
4fVOxAesOsBj9xCZkkSfEfMgLAfZkNZpQSgWfxaYx+S6niYLTpbHzq1X3fyq/kMN32kXgpNcr73Z
Jb4PREyoUGnwdw+MUCEH1yfljEQIELknKqDneRttTC7chrEX4/QPj8cS5WkvJ8mLtrwQwytWEYnD
xnQv02TOO9kY0dTWo38K1WS7iyyFZEN/s4miNIzbdIEq8Yi+FmZJmf0zVRQeDkfMctsGUwVJtTUR
67j6LVs1eMfQjCvNatXfK0RCwBhHOea0n33ytYBAd65xuDzWdxgJKUxn8bzvY+xhAbWEh2BTUKs5
Y9PZYxWrryBmnSqFvlbCyGqOtQmecW7O4wkoK/iZnQZv3dOBud9I/+H+fcXBIfG5QD1MXX4J3TNA
3V90JsgSp9inrYIKarqfS38rEufJledPUnhWSzN93tM+eUO83/2g+6K92XHxMzedfLeISmab6lXt
PqtuPUDx2u2GSvNlRiTJbK59We02PzHZdmNVM5q/OG+UkGHSfjmG/kMqyW3I2VxDsr2V+6952viB
38xVRec7lry87xFv6hnIVC3sREFbx39/ybKugHNmrbD40hszT6k09AF+kSM7EkHWbdaNGZPOZ3tr
N1hGxHVOYrim4NHZ+1gzIMWS5Cst1biaQOpsDqgiJCsEW/XD8dsbZivxqi4k7ZQ5a7/xMAu6cVZC
SSmeSu6vBqhiZub4EWVoW4zDe5ldr6GjNs8HrEhMq7r0Ktg0rnvVAWf+ZjNw2yeWhJW9NrFBr0PN
xOJlI34+g7OB2zghYDCgKvRS1bnrSTepU7qLnIn8dfY7zYsntosk3awWsetPvi7/p93on02qxNA9
aHKEwEu8wOT3YO4kFxNM/lTO522jAFYFQfwBzt+jStHAue8y14Wzja7RKenuNZ4xBJQk/j10f4rC
Tfu7y2PaoejtlqhlCny2xLVf/+y9wpKn8ZdRoh8J+HbIHZxHMqRo92DTT1di1vJVvMWm9AaJ03n5
A2COM3632lt4VLPoptnXeLR89zmmHja7Sc9MGl7t1BlMqExv22de0WBdog3UaIEPI04iDzpSh2XO
fBOGn7AHQ4v+VB8QXo3jCjChp1qv0g88OGgzGXYmaudgrFGw5Z+TBtF/pwE0LVOwe9qdtAG0sNUJ
5raItYiqThQLm6p0A4Ds2bm8Y25A94QJuFzmL0+YiGzcOkpaxfnrsonFFLM6KYfSNU6nmynzlMA5
jDmXbor5vFMBznR7J3aVHMNXfizNbMB4BUYv0TMIhBNVLo4u6vCKs2midF+VzaJxDPHpWQ/1rTCa
Se/yVo+j/Z0dX11yiI19AbbyJ0RTgfmW/pU3G4VNkJKEgZ+9Z8T3fvJXicytr9qmBanrL5OWJ8Av
OUYzqqRS2wrAr0BMgSdpguPiuoC6wMD1U6AOG11apQjLZioI0PZdVTRUa/qraayI9c/WJ+c0kaNc
Dni42ZQ9A5+1jhjFITSgp6SNxASP6JyHs/JxZqoI5PU0bC3ydEAZ+82ehqRpaUX+llTTnWCulJRo
gVytN4LoxdhPbSXHtF1k6fuXT/JXHnoC1usZ/XU5faTvS9XErGHJA/ul9ybhyjs0S1jPhw5rSGQi
FG6Q6LeWmcTZkt91K8rAOILE0tXU7GljzmtR8rsr6uEF1gA1exiHSP4XtheqPDyYfs8OnzvyzrvS
5C/0Wc2tvGblUTwJPhhVTFbG7CqTmZkJSMFX+dFTL53QRKCPhlVhpr81hTQ80uWF+yEkRmko7UX1
Xt0gZ9f4Dxu2CX036bIC/7u1iM1JOXP5goKB7dVf51//6r/42i473RPkVzHSI1ED1PUHGdoDMBhF
sqbHK9ao//guFu6blKPyT4QM8J7L9C2OlQh4nJf6W7CCUXjvfcmX1uLKRTVND60eV8gpS/C/0lWB
gyaOk6ROSYC6ftyvar3ze45tc217EUpliVuJ5TSGSPtkAU0TXNOXqvI5rohmYlwo5zwK8aQn52mh
kJdWsKrFdCU5v830SnNH0R9kROVgJ0XQF6cJNvwcqgaQwZ/BQBTviTmI2mUbPSq4e7RSB+b7LnnH
0Do7OSir5dMPvJU2rjrPWT5xttMEkf6VMC4jr46zIpWnuRvbKbDMGSDVebTnoBQMYIn/jTBLbF46
Bm+icW7jXjJEMtkpgfNxoLhY5s9G9uxz4fe1Tt5jOOQ0SRm7w0rcu41xntt/BWuOQJjPtdRNcT/X
XkpDRW+40FVT/psAIiiLck6v9SJ3PRSY4QYQWPmeNwBGU66l7AKOK7tueKoydR/l/N8kNNpClEBh
YGkMMAcLXHSDrjq9g2c0pTpXdATyDXFb26suMp0X3Pg2w8WP4Q4q/38xyhr+elgXTYDiwHVSDcxt
hgDFUnyVDNUiMZmg/MdDL1V/3mCCqFvXEMvQUhwgDrRr+s6JJdINK4fgI53SdanJkvUVDatw9rHI
ecq4g+HGtXul/kiLQQ8LpxikLJluRQCJhSfEUP0nisV2yUQBmVoyfgNJVh0gIoa3/79r10au51Ke
lRSobovBmufrxgNUV4GWImk8N3NFhqDNAWdk6vuWjcm4aH2GSaLgqP13XUY2L2u+TFs7rvjr5WNf
exoBqC20G98oiPbwy1zqMJK1JPZlOyP2CT02lHJ3VEiA/JXqVnLLFM6EN4Eluj4wG6+/K7PrGuH+
u0Af5Atg9PEJsG/PhCb5+O6C91OfoltLX32YpPWya3JCOw4bQHxpiV//18pw3Vor5ibvSlWH+TC6
ztKU0Gc+LnYvOCba8zUwcXTKZZWnUP9lJPMrj6yRocK+PWm8L6vABcNNG0x3I4ePWXItUL0zmHxK
27z9egBJbI7okuKCi1w7UD5OoOspHMvaa43IiB3OEijZIdVteYRh/g/sa0HoHt8lHmT9LIGJ4QW9
//bcnX9cwaTm9CAg1NyJ0yTSHc+2hwu1HSKYeHNOtOEVm8z7hO2zo+7+TB7Ry/5FSLUFvbjZ00OD
zk4PffQ5/2/1bF/0QpFvfU3iprjHbx+FavxtOE6OC8Ev/hcPbbmfeCbnTBhzuyoLaXqBagg62rpL
J/hLH1pBURF3pbLgHrJ6Q/gwLvNnkicpmb766VlodFUdtaEabb9BKwfNtXBVm7sJOHRcn5oQUpMT
I8ojVT055kNQ01QFJqCC/0Fbm4rSWXA1mWQD3BAybFAG3wabCISuHVwI2onm91ukkVB9O8GSAmnf
bar5hfh7eAeW174nbCsryEXeFnBqHEMZNkHN0ze6TX2QCrrEk0hub8RrzVIWqvKEAfYVI9XrXU5L
8joXPARMEIDMmT8uxIgOVAwamMafAojUzOHruyBdjcypO6I3LMedNipEXEreQvaaK1pXpoGCJy52
6T9dGHEQpkGu0m5c481WKOtP2OgkDBJLqk0hhPnpojF7q7lUXp9OPwPk6ztISO+rLOmQ77gWIH72
Fc6CMMX7TftvhMN0nFDBAZpe/r5FWpv8D05iPxQg7P/gE8/u0DcKmsy6eD/1r4fg7QtDh0FuTDCG
nx9Q3SXHlBOS0if5dmaJUzdTWoQd7X3EJSOVhN0dU+WYT5iZ+kCRmfQOQbuPj62m6lcjdqxvS4ob
QahsfkP1bwb1Z4lMqDs7yMXva01N9xV5y85Zvc+A8LwACVQ9eoZ79qVqeWJcIzHCXKs+2p/+kFNg
xLAwUAMVFDz9oKTG1xa65dxL3N/33D8+spXCGaZ8mKCZvQ0tPTr7f0mQqWREM1t/HGPU4bZ3o6hn
4e2Y1ImKjk4gARTbLGGeGxTgNm0NEcfXPj4wyRptdYVNEf/gyHdHSquGf2LWyyF/D3bQIbIB7kCo
xJ3mXLDdbNcD78Kwq08y5ur/JyxHaLvnr+ysrZG5DCro87viFW8g5e8OUKl4xmaDzNeMS0PzWTL9
N8ODVCtUpnkNd+qrkQx+shLtxfRRFvFK+nTAbO80Li66KDS4PVeg9Endo89kvwv1S+xlEO1W+4cT
pwHR5QaJJqiTWjGQz9qCVdgtqFLwaQWmytfRqSH5BGEEVqcsrhVApz3fK3MLvy5f7qDawnkPTAB7
n81cnJCAafYpvcIBsLxI6Jg0fUCVbnVG3FI7zfQt4RPZBdlIXGxxId2g7UFfAw0djqGuqxVgV1pB
9SuhdFyYx9GChMe3ejAgXb/dWcpcnDV7ONw2Tpss/7qtB3KXMKSl3df9nlSnkbTmoKlrZOQnlemT
5SI2nTXRvv9QyPnPN9DHq8By8ZLekcc8i0eJcA3ujDRSAO2p4XqEYQU6qQOmu9vDTnlhDqngAsLe
9jSKCmBls5JBxzEJGF5ZhOH4omlTW91pxAK01tYRg7MGOvxZFoCiRck75W+CsMAZzvHqgJNRAMZk
fQHPJBXczRMRP2kki57jc3Bh0IFuyIwntR8JEenVKndk+mXgr4k2Whmkw4aj0M/d+aTdO5wgHrQQ
IigsPHGUfQTTlQtzlo3ydH2C7AYSbs7Jn175dqO30WGFuFAWYXmzTrTHi3YDhGvvhLokZG40cDdg
ICgdhifWopWJ81wPCrHhPDbzzuusXvoL7nabNnLJmIE07Lc5kmWECkHJ6GDx7XzXhySmAZIviHg8
ws87eh5smpsNzYZC6NiO4bfodipaWfZFXAGbb0SyRGSoJ/AMCoT7RcnKkGPBQgO66G23ne6NaPye
u4uj0F58B+OBv5gWu5YSRlQnzvOMUdmVDP5q6nxxf9V4bLslUYR+OePEqYAdDGD3oU0gs0J7fQ8P
MBZKcciZbcsRf3uJSIMTImFnxp+t4ofWAFfDEoPJDUVJjsQ6TDfJ9WQhmpTSaU47MQqTWb90lLQu
NrTkBF625GkCbq9+jvhDHurzeFf3LnuDgu/bdkSrW7Fz+N5yY37plh9t9DgXVTuZFW3Nmt97IP4e
w8zG6SH8iKyfqdJCmM7PUTwNnmBXGEXH8MEgBW81Zk5MjpS5mApy57Dq4Wq/bQTLjRWkV0qn0C9b
FwG61oB/rHLGiCQho+gg7Td8N19Mq7B2Hz2JX335Wy0e5e8bE+QToaCe2UeecPWwPA2kmU2P9pcQ
QNzhYaAepLeU58HXjRU730CbwSyXPOU8NtpDNOrY2gY9ExcJeTgNOQU2R9NClQ19m4HFjYlNnc8y
Mh15XI0HHQWgTScd2NmuiMwEXryl8iL+P1pQwu3OtKiDRrWZOfkwzYss/Rt4ms+ESfY7lwWqIt07
gYNwec90LOpdLVfWj/s8Z1RmUF1IvbWEXabVYD9c3406BztNU1QX6jlV4EEebApYlF+p0jyA/wfV
hGnhWc764IdPr+rMrsIXnXaM6c8hlNRM1JGIxc9eKKYDXYxMCToSs3QnZMcZxkhAPPBohf06UN6n
CvACoQXlr3OspedOtOgemHuSN0kcQjTW1FAqArOn1KGuhSd62sKLiCOQo3OTWuI9IzXddM70yl7B
UyMHD548G4VkEj/3GgHwfDhp2bnZwVi3NxszQZ2wS9gf+Rn1uxNETFrG4kb5Mww2EiXs2ofWWTw9
xm2kxSQZvnbsF7KJ/dxLf/Lkdf7SCx5rCk58OP9eiWchHCQaY0qHXA8v6Uq/UPt3mgCcD7SLvNwD
IhdFiFUeagEAVvW/28uXR9UdCEopHwOtzBO0AG8RpgL0uZtlAxfDg5Rx/QQz8MdwQtjX/2e6yK3P
axdrxYEZs4sWekf3D7xT7PL9kRYHIbeWVtztHla/NH7/MQoh7to3SB4MeeWbx7A3HdNLFhm0DOXO
nlf3gL+4Hux3ekf8mCNx7KL3KqOhYopOH1iJSSaGf5Yz0hCwo/vDRxzfy6o5POoCn6vG5ZPPsnND
hUwBIVSSeHwS7yJb62fixRtQkZJXALzh3QBbVnj8ul3uVfnIAgXGlyCY1J15ccedLuDrdp+Na6OM
FOmeYSEwepHICf6MxbC6bSqDfwNmHPr0RFGhFq/xs/zfCDZKg9/+6fl26T2VPWz4sZWVDIQEwTGE
cMI+UUs2QU0l0/WrzdjN6yEmUEQLd9woVOw7pZC78/3GGXh+yEfL1nEskHRXSLgzst+XK0CgfF6K
o89GEQwkpCjAimh4caKiBzlmDGD0B0+5YNcMu68YmZ5NEoqlwh9nwGIRHAcnUPaWHvFmwYRDvz6U
S6q0YNCRDvhdBoZeP3twwQDUOQ7GhRA3BL+WSMSo2KpMl4W1pkkDIx4sXyPsUHHUbHMqXVbR2/yb
Puw+bNXJcwOyGMu/LOdNIDqWrkC1PokGQY7L6VILQMCUBmv6FxqYj6gdnIEC9RATW3m1NPxPoTv6
nctz1b8rQoW/F/9koBhrzHSekK6rQKZYIf5UAiV86rHHsqDRP3Dcqp88FyKlSoay65jHinTszgYR
XM8PnqvZqB7ULJVJfV2R2LDv/L6AsYFb1bGaosk3wyTaeEBfD+z2PlI9280WDDjFzENDEeURhho6
uc6L0DSRRxFLML7538ssXmkg98aml2rr9fsP0rAKGzA2TlwOuBUmZG/fhgX3zGfyrJPl8SNb8lBL
u450Gwh7GP6zV/qwGkuwHEBbcUCIqM0FlhNxnqGyeF1vXiAsERmCpdt4uoC/clBYvoHGjWOsvq5E
+p8UwlZJTmrSmy9wGB31Olnhi4AuJHbtSMUm787fHN0La2XgPxKPxpskj8sfpJurNvqPqi/Mmt1Q
5Hwm7LL0aKzL8ybhE5iOOHDfecG9PZJ98CyRG7IjNKpprKB8fD+2H80xyHa2QQSUE17Vs0wyV5h9
0gV9+w+8lGZjqbaNZ6Dnq1oZ9HZ7UCMnjrZwNbr0Xx9AbLmv22OwwXBDAnHkmAehkHZ2cfR+zQvS
5A3e+57c0Jf4alX4TLr4HZjYsobs+KaaIAerFp/RxfOm1R9KmG2g5PQqOZ1Ap1WajpBhGhrDDCxz
4eZjfsBBDBiv3rD8HgDe8e0c60qH/MCuqtWhsy9q74+pVt7vX3rdFm5AYsCjjCaAMApcNYRAjd64
ttcft1PbCzmgUj9eFH1H63n01VD9FG2GgJxG9uAXxbfUXNihcnIPSMS1yFM8jRb6FIJa1mwLOnx7
iRZ9gIMl+woTf1PzTUvafTb/bgx8TXH9SOaynkXmHJh+7xAx6vJ4Gz39sqvFJM/J//I8UduuvBIX
xguxAmoAOOwKZOqo9ch18+zGCYOcuWkD8r37xHTxq2iVENniq9uSU9pthdltROuKPC0bCX5qp3EM
U3BTsLxEN6tc0lNDDrK1cWCOERP4AGF1z/fu9amVhmJlJ82MRvzmudrih6eaATUtRahJfnQhD7lX
ovHkUFGdpy6Y9/IbgJE7yIvGClTo+JgfrfCOilGyz1lWiXP7bP971q/2qdLHiAYnUkHDI/G2X1t9
b3oi6fsbmNa2niiWlgqAWcW+d81Z1sQaKZaDLIfySp4YSTwqaAUx0NMD4tst2WMZ0HsMg87vbYjI
64+5UBGf8wiUzRByL8KwudEMWV/D1FvwVXTJFXcy65J2G/IpLrOkshh59hObSfLeNnuZBSYgB8/d
xktRZYD6b3bkE5ymo7I8AyFTwRydukRi0Tx3rk+UuOyopPmGzYROb7/8g8IhN9ASTuwy03GBarSa
KhGLeU+qlJCGBa0EuuxzSdTNcCEqAW7h9GDUc39nedA3lNrikQjlj+KamNcBTSXL3QOn49F44d6x
EvQc59tye5Mija/spJG4KEUDWCmfjua7TLK1CMO6Btf2r/ZPGq7O/TAiZ9/2YIDR00xa6lIeFUK2
EyOyDlyvMCIfJ+epNqNva4aqw5xVxwcjWcJGrYtacC7T/WqHkdmDu9hZvLh44OkfadEd9Dmf25Pu
DwHQ6ZfT5CrWNnWpTfoFDZtlgI/Mww7HURTBe1OkflTEwhehPvc4rVb8oO9NadoBAyLerp+8sqQ2
UwU289qriXhp6uH+69JR7Eodpa5L9OUCqqMTPcYJgBGGarsL1HseB/ja086Peypgo4JUXwwEYtIg
suaxJRojn+3/PZOoEnvfDf2S2CYevfivhEUg3jtGK64bsQMrIvXvWZgYQ2VrBlhKLKuvz3rI4yWJ
fcpaa5yP1w3XVOqOku3GMqETOU+wmhTFgvExczqoOSFbudrv2wS4GHK3R0qKPfyn14pNc8xf2FdF
WiEESw8wQapQOgcZmUTV4TL5+rJgv5tMZbbFQDE+IFZwwKQdLZsmiD4PktxpPeHTyE+c9zFfr9Qr
RvNne9wsVDHMz7RKIAJGdkLkTE7w69kEYsQyJAkl1ojZKxng8G64ctASiiT7UKLbUf0a8UmwAWe0
GcaIhHh4sNaayCqriIyLjtwcDHFhCW1T99O8v7g7+aLlMnDy1SkmhhIBajTdHaSr2kAxMs1+8AI8
2BsCP7r4xudMwCfC35b6AICzNZdXX665kJJQYA2IR/bnNqZmJMKbP4rJTGyBjAQm1DhA8ltUZxHb
ZSBKQ863mMwzPC7qjEQs/9se/6P5f9NxPptKqgYe2gY4fZOUnQnN5zU6VeD7ThFnFw/Q0VMQpj3r
0t5/K0BKshZvh2VGKGTcaq916/wPcRsdRCIVJ6u6yRe0EcslkJb5+FnThp+WIV4Vj7/Ckl7pNII2
totpnO/vl6pQf5TxkD+amoFmPNVwXOCCNI4fH9iK+6ewOELnm2gIBJmDmf1gopdCeTSCB7ajy7hj
pBqA41ZKXPkgGr/QgkRLzmiykkP4KUjW/dlEXY5/rKB60DxiA9shtrxLd4o3UsjjFxcCUJejwr4S
d9cWO/y98M9T8IXbiz0BQzzJ1ZHpLuY+IyhP+PEHvrfPbn5l8LHN5FpNHb4kZvF/pHvJBdIFBGXa
39ycQWvc/seAvxMuh1qZXeQwsHL4C+DqeIbuRNcwgwAZcKiR0QdYhDUiUsHxMS0uIiYmOgXvfH7C
igYFYzd1dv2mDPgUct4OI+aC8zBu8YJxMt/tPNoX6/x+bg0m7LC+jfp1Qp2c+TC04eYUm8Rj+ZJd
LOksj1x07toj4BeVp9KPBk/XYZAOG5evYETLoAOwakF6KKK0u+QAUt5IO8/rIOTeKIH4poTPOK+S
jvz3e99BP1NSp0Cs9d8saUdZtEDWq//HM2N/DU2IQUHA5ftrkY8mZ774RASDV7yZ51yknrJuSdSY
9A27HDdyFOr1EYNat+N8UEkXe1QYLkP4H2hSucmUAtZ7qPwNJS+F9k/rRHpGu/26fjjZZ/PLuEM7
HZ8MlRj7zgi7Ck0qrPiXQ/f+ukNkJcMkZ7tc9Sjy1psmFGpMmSFD8ZLZGOUtgjmLVUTfIMq1xu5G
eL7s4vMIGrHCXMryxDdqpmmRgS+Bu+KVNuTaD+1ou0ya62nhT5adSYET/zm78hP6NJMGCOSmYv0z
Xm6lcLafGS7QdJNVU1x7j9tpezUxRitT6BpVSzrfYFv0EiiGx7L2jWlpUJJC9vPVXMO1FphcIBcM
kS16ppGSKikktxZkRAZlHIYRHifoino18gFABR8Yh166VD6N8F35L/ABQugwlcU9dqCiSqoyWntn
KpyeH5TlD+IrXTFH2jhxIFQiSh4zeNEX4O0zFwmBX0SeEhMS/hSqe7A1+JDKHs9a5k9Tqn2BbUnw
8sgMBCgXu522VnTpyUf+K2GCBG1L4FvS81gChdqBh90iksdXx3CsqtQZCcKQ0vv0xnGKax4fbMkV
kun3lC74v8Fhdkb/LC+fmsvb/POosPWH+YjjqxfyPt0mJb4dT8WU2nnT1Cu1Rama7w/i7ZVsI7Pr
Ucv4gzCg+k4+hIMtMSGy8SSsFynzc0TBIxm5v4H0wg4znkhsuc6WnOWePgOS/HNkFsc2umx5dJkY
1tieSG7L/SKoxwhzdnYfBDZ1FOfOgA+N+IS8zkYV1BSluXtbh6vpsCwLify8/mWtFzFh7X1dhUHF
gW3Zs25byqt5NVY9xTOhK7Q2VFmKayCN2N4H3NneNcme6et/zk5MTyzHxA4S4vf83TU/nbMUyhP5
1/hhmX3/NhYDd6sEb/UwWS4lTLn13OlbPKAaB10cC/WfnSbX1SYXm8Qg1ZwXW/ni23SJGV5KZYrZ
SzSdicm+WMN92cKE67l6TVkyZNyao0vHPl7nov/bgXv0FmiCGYhzB5RlU9dewyZFOAyGDjB/U41P
SzxMaRpc/Ux6SOYvE+gyScsLRZiXucCLXFIy9JPjJMJ5FtlNE2RbOf4Fqp6YxtGMNy839U7UTqnc
p4lR3O4j4lCqvWI7bJ0les/RVlQJ1O2npWXrqJPatk6G+ifrcnMayXXRYemHMR9MWUTOw6G2vp5K
wgzOBeg0y41kfzFXjNEXVEC+cwI4Ku+wv2uv2HcOHBEgs1Phl6C4KIgkynL9FlyZjiFqxsbu3cFv
pr5/rdS7toMfMTK0icdUwwIlV3SQAAUjqSqnUs+WnpuiIDkPnCqeY11HOOEVc+uXYbHwnquzn0La
z3BkCSalgNS+sNouqBZf5y2PY8cp0JlCF950Me/7tbfXVyS4nNA+2190N4XayEcJmGIo6Vki4TCl
b+u220tksOyLjNMTtOFt+kJeCquVGa7UUXFfCkrWDNlVa/KjTtzSp7NRer2Z+ADL5B3WLRD9xkBj
zVu9nogoIY2UXN3g1ho4PsYvMfWqPmFN//RCys++gGUzNv4b7OQMSHspfI0Ufe7Xegm7U0e4m3em
c2x1fOnO0coBx5md0pgr2qaA5dAhugJryrH5pgiq9/E3xfiZ75sjhQ1LiGrvy5mv1OIdZruzirBD
y8woxPJlSZztMy9U0Gno/+qzw5vQLdserPxzZRwv0Ivcdbv6oxc6REA2Uv+RjD9LwZVGM8vo7Tlr
e9i0Ew5l/QqkS2/O75s6M6/c3gS1ofsqJ3cz8VzdOaGVZambzEHK7mG8PStaa0GJ6/JSoqTWw+ps
WGXJh8OLF6BGOT2JpfYMHF5m0Tm9Hp3A5eVIpBc2w6lXSn7jX1mDFv847e/qRyKLNB70ff2kowvi
rNXZ8Hsa36ZxFIG5MLQ9HU6aFyDCljhbf3ye21i7WwrcrtAaqud25HSt/dooTLHhb/VaVNqOczv8
drZkcsGb5f8cG3h0D06bikqvjV19mEoJVJ7em/KtlOJfuJ+sKaHP7BDfXVBff4uYTTz0yQ9led9l
OY7WA0jxH+/VeTGTkFbZacQ56jojmlJsP/+Vyo29Iu+ynxGxkDqx8GjAIz2E+D78WSMmWBAn2OZT
vGFpLrbU4ym2Unb2LGz1jZDm70lFEUVAIOAAovPW+XFP8jrdW7ydtPTBkOZRoMCHh95rC6Vte5mO
XIwAvfmY4evQXUTdgYJvAofwzQbE8DQAmwLVMahwdJQbACj4nUNwMVClEd+YAdNRrXTZ3NkbGRYF
meceQIFkz1H8yOp9nH6utvAKtMjIHxn4Qs/hw531v5hiUqcjPvVyo0zgrUY/wrjHWfSw+4CwRsc1
qHaGuExGyqhTRkEKJWSEz0d3iM10ZlrJlJUjUkopJTEQZgdjenDBuoTKLU34thK/e07szzaQtwhs
7B/U0mLO69K+EFawlcVEqUeSumHy6shGL0RyjYlthr8enG0f7xE3oPeIBrhieR5DbXspFSzhEKel
xggj7tBXA7jgYAtLGD+rNUJZOyep/lTFLyaFHiEIoprkLqGM5j/veH5b3ieMTAC+ESGfVl7ot0ig
navVzHGhNMKRnGgiYMulNwiZ4x1QJ3/In+CqC5AgCXLVW6NlF17CLcue2kR7cPAN9ym37ReXUcvD
ibRB/iuIiXd73z+h9DqFaQXx6yyRjv4R/B1f8BPCpdt4R1IPjTMW+qfjtrmopNRnle1hYHulb1Sm
78PiZdT9rGTDgBguVyZGCbnIF7DAICIMbcQzjYpKNY+yM4vkKnrJNYRuzFV3Pj1ay3fK0MR33GKF
I4OJn2Y5wAUECJ0bmxA9azX1qjox/PRxfdERu5CzTk5xOAwTZYqiJ9oSowbCAqUGv21gKr9N0C4u
uL9/gyPVFw1VH9gOrhKWRW0bHAdM+6IUpwAeCZuq/nW15ygBWcFymrE5+KzNtYgAYO9RMVQXitDF
MXmgshpR4scT9pszLvoewy2F+bfs367Og9Qz3lSIibF4yMZSTfkAUbKGNpKu+cGp69qhvlmA7sYv
lQLZe9ugmdhGTCdCwzX/u38/Vo3VliGjrX6+bvffTLIUMKjooTurSPnz9UFXdIdu16pkAQ5+41nx
C4b/qH4rwfo+wAgd97jaWLQ1tzy/PbkHHehuNdeoOdoLCORzCiXpr+TMfemu/JP5N5P0lR5Ui2ma
Mko64yDHlGMayJrU2d39vv/mU1EpRjw+YGGeUtED56Uot1T3JmBkDj+TeEzvIjN94IvuxKx0DHBN
0NGI2JzZuL37sv0oo9tnbNuxYGTLkajJdcpxjoYG2Ze7PnuZO0wlhq9ay0m47qJ0MbzemdI0EEkQ
4Rgslbd7rNlHyZFIX6Gkm2tCEZpUs9O/e8hnYH+LEFpf8D4hPfVisSjQdRp9I+mx6+6Uj4PuNtr5
m0CwCpEwSQG+aUDx1GfADPFEyXt1Kl/3v9uSKndNOwgmjOHsoyb7ZbIOLJWmHvCU1SCxcrqAhMiX
4/7sa9jvMw3gSl83ETSMGdU1mLW3Hi5smN6VaKzXovFoauL31jkfe7uCVoCWiCFSfva/rLrvo6UA
WoNN0LDM3rkwvDr7wzuhJ5kgH9md+mWlH4oDnXaJ2WOq9ZNFIrlYn+v3kVGdmgO8uoIUnZwmwwgZ
dGJQVmk49W9oonHx506uxNjYyL7UgoxQcfj9+H1dgasLasixlwypIbY9HSHZwlxQBjSTsTczM5Ix
ajmYL8Nm04KYnfLTZO9IlYUbKka10XvTf53vHAFFwQ2lz9yjqja4AmPYCbDGlrvqc8BPl1rqORmY
lLKLVz+xX219QrNgb6KuyOfD5CxjLMJhFqPms+CE9qN19xJAHdb0lrGan8qqj1PtkX1EC5EnmsxF
HxrM4zYSod8f63i/0qEby70Bj2GJt2p8hneNGLHDNga4qd7ImpvWclS24dGndCELU7Z9xXlyz/ri
kijQO9NUreuancaL8h07EA4zbq4TYHIhw7FpDLtXj/NXx4cUzABeaBygWthIfK3isyYe6yfMnWW5
nIDhLMo4KJ/vEw+zg99BTLNt68Jl6RVVLLt6uXGqwFqPIIsm1uAVnRRo9CbVLh9aSGqktR6QlZel
KjWaXNptYF3AxO7W61YPq10wC+zidEum4pOnZoL/Z4nF/7o8Z+fZCeNVbaKq79RKdZfGcHybc8Hs
J+B3FIiPLFvLT+fMgSL4KBaSQvU/dwQ4X8cE7+9DxUw2eHjsaMB+QhYJz+hvnLG1GQuEV5tGCpFd
mFeg5nWz+YdY9EYfHvy3aJ17HIjCnQr4oLdtgPvlPj1iOw9kYskYlOImNFQIFPAgpKZIy7gCsgLT
Fbz3liOtYaM4l1IOa5l8QvfvlxBGLNXmBG3bm5cDdlGIIK5gks2ZfbP6lUMvNjyjuNZCPQm+s8YF
XP4V6w5jWeI3+sise1Gq8C9jyYlZfY1GKJp36Az7fyBgEvea96HQlYKNo8UvkLfplt1lHp5w/Dl/
CjWxX/H1XaDfsTpwaXLb44m33kzs2POrmtB74rjIwaY1Ct7vpLpd6voboHWvuE252ERfCVCrNJN0
XgmvEz4nhk+7Ac5K8AUyowWsAmXh8Z+znrFIRSSG+UDQjSXg9CgbUAm3f7KNudJknILdIiyaXLEC
n3viGaD5jXOBNXQOyrtK9OtyXwqvs+VzbakPuziYGEahwP2ot5I9YoG9+YzGl4KA7mbYW5CiRDfM
WFbz1988wAZrD2IRTkUKeEUCFumfMagneyk/ca6ebt9PQ54hQ++aeIZX4n1AQM59wpxGpOe8VjYR
mgWYZFkeLHOSCEjG2p1TkW6vgfjqIFs40/bc54mcSYiwSswmimdP4+vdft+AlQt/Zh8CM1egHXhk
icN/JH/c80Q7Z0RHouiIaFmJpCN3ydjrueyYQ/BkZ2eQ1VWyUGrM0l/iOtrqC+km7kugtgTb3xj6
saE+5XSgR4EqvlecQuP3XlkcRx1KtUfvwzHL5jXKvnu/BTPdlAh/XnoBAU27LuHKDwHl2HYFNtcF
UT1eoP2hCenYho2E/jSAUGqKYRhbPLEZbED1zalqjzajwTeUCvS+kEF5NknXmBTjVkl2OrbLYwiO
bW8+8QiEu7ISB058A69QxzXT/QuisZ16q8XfXpMYyiDV+fKBM2WCUIkkvKkCblkFH4drY0D8B24S
YS0d5Cx5WzaDH55XKbfMEWUpHRKcsO13bVNbNNJO/jq55iqM9AHjCx1V8uFCfPt/7UjFCwmTFh2s
fRFeyEmCsUauhBDbYe7ONq5lYbePfcNt2jFwN7t4TzxbzVkGTkgbi3yDI1vyHAupbN7r/VM2odiw
crVd4LynhhEi36NbO/Q2AAr+wLaOImE7JKl7aQT8LcASODU9ge9f75kc9U9SRqMuUvjbX4K3cB8t
bKPzTEejtHmgVf7L27UpZPAwyqmVABtCiAYW4lAbM1hZm7KL76b+8WwU1GAX2zJJ2d3Khybf7LYO
RM2Yob0QEizkfI2TxlkLdeIytCr8L6U5aoFBCApH2sVP7kY61fdsf9B5nyHdInJ4wjL9AU5iGUC/
4UrTNIH9alO0kOYQhPrv2jEy9ySb+mmQAW1M3hxlT86SRc/mOOw97cb1cnuMFFG9zsgc9EX8YZbZ
79EF/m8YyCfWP4AW54LnOCZx4f45LvpDWjryy7/twrGUvAgqVnWvsQLQja4azMFYJ/oY63Wv58rN
O7l0t0/wfgx6k8OpR2K8ZLhVy25lUe8eXFQSiaASlGiqSIcb/F4PHVE7nnQTJ81c42AFEqSkTWhf
X9ewTx2YhxTozwUWp3hSYKrpy0jAc7ceN68yE5NhhVvg43rJbTzEmOPaoXbsr9N7z/W4Vl8DQlhH
ezrdaTCTqg2hhPwIBuzEuxMHi58jSTe5FtZ13W6tt+IwdDFZ1+f2VirLHj7ySo4JULeTkFhehY7s
cPjgQwMr5T0d8L4l9msEmb4Wg6ec3Xq/cgSbveOHmGx1l0lXwlWIHjSQ7P52NI3DYfJVEGZJf9yF
3BlDiF5qax1V+qJfMpHMdu+nrS19+OzcmGVbybptUG93hj55CRFvfWX9f8PIBfkn/mHzBy9h69CW
8Q+DEDwUJSG1PFdXVR/E0slxogMFfFZVUbspHmV4yz/JNskh+dcihxEMVu00WRG0eFRm0RPqmGKF
0LY+iyjoy8KsulRps8K8XG14y8qFTgAW7CHbh1vHLyg5m0tSJsgEaUCnE/OUHnmuPrr0uRd5GMm0
E+uNF9jlkIhfGw/bX+5vqUhJZ9DnhARPTqG0DYGumpiqHy6IEj2OA+sgsFgtbMFNKPJ9405YAZrD
Ib3Vz4gUtq3WQzS2QBA9Drd8FAiGznKht+8Jg7puUwHOkNYo4rMZTRVTLayFB2dX0O7iZA9QVJXX
HolFcwI1ylQ3Vcb8lUv6XCQB+PHvAhSjiHVxxTVBI9Z47/AY2c+W+bquLn0rsZrBbzg9R9gpX7pt
8nUxROwm+O703UdTdhTx6dcU++IunHH4WhQ6711zbkEpzu/wBwOSK8CKbShBpJZ+iAHFzIHZtC+S
CJmjrtmAEhlfRYCEp6YA5LBxpobqS99AV5/573IDTiANZBrd+1VG8Vlj9WR6bSajr2xAiH1cY6cp
GZg9CqQln8KZrk21J4hr1pP7rXNU6IVLJqp0FNDFPCWZint0l8EshGTgeA9az+1Q0oUYyhsCIPsu
QqKx89vxTFibHxiRiXR9Mjsn2/MiYqpeK2cvu5H7E1gteBnsLD+OcGYKp3licaUmZLfNpZ5EuvZo
16nkW7vsiBiWgg/RjWyKDoRSkO7SFHQWXGV7o+Z5TchokWBxC122DO5RyC9TcxEVUci9tglPh/3a
yl7dlWcIFucolWWGmwdkXIqqf54disLNqiPsmYKpT0OAaQf8lrZpPgKq1SZM/dbdU7qBZ+WdIDXt
6Sz8yxX8U9xw0g6yY9K7Yodbk/mU/6kAxe/dm2q1/wS52cKZYv73jGpq8bbV1OLI0ihDWhpBNtHw
hKqLmoG4tHJ09BEhZ7mgYWVsvA3Gc5W/az4iDOQNHpl1o87uGfWQ5vXBppzig00HzZHhXsnI0zWb
KNDdC10HCj8MNSm961PcoRcryDkkI+eKZ9yC4JcR8qQ2jcHzpuQp5wNlDLr4Fafva9ukGyE9ccSo
b8p+gS2uohgRI6CGniAR1Q2vFMBkxM356Id1ILyEJGFnCUfu+A6QsHjtCZzHn3MaGFUvU1wJHc+B
nq1QMbG5PhTgA92dCzqcFxmkhZV/MK+B+xtoyvHH3OcaJ3QcTCKlCcu2EWtdKHvqatGCN2zdmwa8
q6Buu9iZj97ZgeHHbczJ72wjhahERJKkzbL//3stBrNN/C+oLNea7jUxjHPwwVMQ3BF9ziPZSFTO
CpqY0agLKCWJycYYsUfSov78UEV5/f1mSjAOM21M16mfFAdoiVhXBXKxHA9y7MN1s1Yds9NyOmol
y5mHjB+zWj0XJ7KXG8hf9pjUos/nb+m8JcogW0wdc6lDJVh5w39i4LrJkOaloTtAwWoZdJ+cwM/n
bpEBZ623cS+xcIuELOAU0NTxkG5mhlI+ulGx1uTpBrNqbEpx0a17hmtF91kbEPW9qCNY7v9h5A/Z
s/IedrBB9fgszbu4JOK7iNqm0N/+6ednMQObZjyG0wCMgQ+A1h7avxr/6Xs+4/1KLVGLWkuMR1Jr
8D2lIcBEXji7NsXC/qhhuYKWJo+RtKW4VxTmIUZDDwlz2PeJ9L5XoPLmRltkYmVSKd+9fZenjLRq
idc8k9f6IvKyy8wBAuCpooIgx8LVD63F3nu7TNwgBsQ3x6UckAunHgqzeLjulrmbbbDCdHbo7/Kr
tSflx72kwKnORBEQIkpDocJgiagHqVpkjQCWEAiT2iQxU6H6Ns8TJZtZtSn7LzjqXdPAKPzbLqrf
szVL11fSiR3eNdUiDOKOC8FLltSlVSZjxJUTQtJSjJgdt30tcMKJN4wCavhoRyTTQvFrSKqvJuka
mcVyHV+yY1swybg4X+ZBgaMZBaO0MuRWCkuM/nK34/blI2/wPL9naWbKweW3A4lp08XukrWlYbZQ
uI02GwiKemYWsEvaSo5I26qiKpHdDetEiaJjabKGiw6PbLrNRWA6yyLnDTkw0n5ncrONFKIfF1/5
9KB/7DGrLJBME/QoHEOvsyTIjymKZ6kLrHeP2kiFASS98nvWMK5bGOQR5m8C6rPIHeZjVJdgVd8L
17M9t7wGcSkjXMQkPd9RjsVOU784mNBa6sFiOYYIN8LhNhSdfNlI4rLK/r8hOPd5S6x6vYdIzp2Q
HBCQFhcqDJdzCPKidCr2wgAdTUii9S0Wy1vkk++RaYNNBMTjo/JcqanVP80zvJJt4yvm6gZPEd9s
2OBCMGiOZGdep+FL8iVa6kHcKs/K8fhvrnJM4m7RCglM8kMtuu8UmRDK8qt5VRXcbTyJNZ696bKa
pE/BpZRc5uHMo7bTbmqvWXI99qapMxN/+1qkzMn6s5GW0+blIn8boa8AphnUKfVvRiEvFn1lceQN
vO9jSqCBbjjOj5QGNC2HHDticoTly7w3AugniyYXvjwnGF0z7eDyIDcrhFaRsK2FG8/P/KdLNIFV
oNR2yFaFzOJSD/5zAbewMyPoviUqY7T7IKMHKbxGvn5k0zoItf0+2tfqFeTmQyVVr5erOc4iFDRs
4eur5ZjXlzA+UwIkLWpmRtW45/QNO041tNwbPQj8j1cuxGiHMRJhuSlXawHmFhiQemFursPtlsbH
3JJWRv7cC3Sl22e4K6044MGRWoSCy8BEv0FrQFkZouCjxhCPzbuqdl7QrsZHXDTYzQevq/O7GVA8
kb/q6j41unZU4Rkbe/rsIgI1JlCFN3ek8QizWXWIvbD59CnPSYbZfZFU0NsDDLDnlk+pBvZizMy5
oGRjyWDfFh8QeTqCQvepx072IKuRfog0g9VrjXfLfqbyqUfmHpx1jnDwWxMdMVZ2PuxTI/y7dyQ4
gzWoohOXWRjRoIvYEDu5xjfkDbkkfHjaLXhWlOk8IylLJetH6/zQ2Y7pbBwJ65EIfiqNTSFsYXeW
YfXjWzW3UuAg0fUCeJ/rXUjvJRyjxLqapLOOmakTZjR4Erq5VYZEl5t2ECwsfVwKwr9eysrjSVmx
NL5sY7tsX/Dns4hlh5NhdViMdg3U3sG0deLgEqnDdTUrBdae+WBYLXIU8LXrU6xuqS2Q9jYwgMG4
JBNVft1CEsfmLRahrYQ2z0qydyHyobQ3px0gVtvPogQjfJsw3/3rs9E8MYe+QH/lFnMI+ajMGqTK
YwEMmt8gfFir9TAG9eKGXRuDG/dlu66kgdRpddxN37iIsdOv0jue1lXIgmMcPiI9utyqGZAZrdAK
gr49gAdRy6KjO15pcvGu5zwWtJX/XDbnTEhbC1Z0EddrNGvAfl4fekyCNdm6mSrPsSyN7ZC0tA/3
qJOrpLIk8BUL02HE7gJNBONp5oo+ed2WF4avIDYYz6ZEcVnCBQZ0ingI0oT7dT1A06E4hcPEDahI
WwXZGdwk6Ds0ezbPOVodaeWuVoyJONjaBRYBCXX00Vhqq5NDMsPkSS84/btqMBwj/oxGRDRnjbKN
f2uX/FjnYs5t1yB5x4AX6HDfnjkI5ddhNHQNrb3qimf6amKpMhGK/Di/qU1At4fdjJQcFc1z71Tv
uP/yezNytE07C/ExOKaq5HxYyQrRJr4dDmD+WIkqeUwVATit27zVI1ftdFZMl0/osIhD7M5h7EFO
3itxBzqakf4Ne4BmxANV1lWLvbN7O//afTIChFr7+PqBG0DhlEZGJ/RB0QHoGeqWFMVEftu8V/EK
ZBhwvnhdWZnZSmSakk11pILF9j/8X8jZl44xDb32hbt9/nwZi46TnUXx+0wtjYM1+pKWKB11L+HG
qSULbWO5J4H5Ht9bsMucl5zvz9DDXIl2TxdQmgTKFQ0cjsJDrPe+MO7EaarZSvKba8zV2YeC3hyQ
NAZmno1ZjOQalXAfo4JPP8ZHF9v6PvqASoTAMMWK+wbRLpgGtzn37KwpCQEvkz1UnV6vf2xASNpZ
HQ9x82lWjYYUsVUAapa7S8d96FwekNtuJb/av00P0gLIPMCUsH0KdR9zkGP/M/vM4Csr8YoBj8V4
gfasN6NZ1WFkvbgsGMd1LJ9STsPX5+WYbQuEY+ZwYSLCtU2KMTzbD5VpmLYlIYYeMDqM99CnrFun
VB13v0moatrSVENxxhNkUzuFdI4Ymt5um21tYSNWObFOjs5kuv7m/9Tc3ZiJqN19d+PaGt8n4TfF
ynD0CPqTgUjUFtUfzBiZUnGO7zt6/g64zUy4shZFuQ7VA9dEz5l8ukVVfwAFhPLCkQKahnr2mkq4
Nf2c98Dc2j+YqlbYKHUwFC/ODJTlK8z/N+uTlie5V1miMvm5FBO7+qlMZGuIRHLjvn34hVHTzBG2
Em+h+RX4Wm8HV6bClxKfjI6XgnyIItPZ5DxzShQgCE01G5x9mjhtfQeLt8M+ah8eYFdm13aNx4rt
SCo+X/99peCOrBauJufA9oelR/oRtMBx0S9MJqTbR3Cn5deaSJBGNRIsCAt52O5DZ3caHa0JakBK
+lJ1YZeGXtT1iLKJmyF8eczLvd7iidgyXJJZ/XRJIJI582XLjyu3ZFj4nm66oKL7qrua6njS7an7
hukK64dF+30RQa/mxdQGx8VQRnA1zKU0xM4d+gJY4l+ySQlrZle73rRK0JaoAxZwGhd7sVAJF4Gl
Y24YZgDGjmwaiK8leJk5sA+4/mmqC6tygp19nE0cvX/JT+xDkmiERufVfI/p5S9vxbski5XoGAiQ
zleqOynobVP9YzK6KVd4HfQv6bEctLBKPAYWQimtJJkcT7Lqe8EUGwBqvPNQBzYq/CutRcj7aFK0
lmOivjR/VpNYc1Nd4GeCaDGvLUBg6BJ4D36a9PXmM5jnRAjqKVwb4N0MPW9lzhnx0f5o7uVH+/uc
B7WHCeG+8DZ7QLVG97slBj5sHq/qce+7rGvNBlckmY26Os7kJ1DYwgEoQYG6H347LvEh+jcSxpSt
QegPkZgmYMIAeOr/7X2T/lbL5gxbEK/blgXyPLqc7YDWQYNTydySUHDcfjc5er05IbGgpMUFrci5
/uPIMawGby7jID7IA/cN4F5NrhjTOb5FQ0CUpT35BM6ZbriLWKjv0yJQSTkXZ8DCaj/qwV4iXaHC
M2i8fAayGVPj/+cL2+gLQuurEGwEeJwN0EVJIdbx0NJVOext1P6T6lHsa8FMYHt8jmzXnfr8zrdK
2SDSR4RhyGe40WJ2fALtJ0hgQLy6672vDFr4QmRJwE3JDIf/ssz3pse1A2DHw7/AJ+FZ0SWA1RlZ
Prl6FA6BypJtTwj5mxfwPID/Ggdih+CkB0PyjbgEgc0zndVthD+ZEFIE26PV54IUXr2axsOgTc8U
kyPtb62zeTa5JDAQqF2kI1spL5H2EEE5uIwLbZ5DCeCrPlgYOxjUhfsci+9X/Y4P4BpeZnYmXMtx
OefRBT+XY+8bGzCMu9K1rB3HizM01ZR3T3r1azJk8w34HQ7gVFkoxF0ZKvyel8QlNPtCOFnb8vLT
hpn0TdsP23eRvWLIV7GCxGGrr77I+3J1rdWAsPt7F6TKIJMnxcn4xKxHcEcWA7HUc9Jkrl0q+BTu
JsD+5oulvu4nsvFjx09M+rtm/k4VxRr+Jhg4ePELo6kLAZHkXZdEFDre6C11QFqaYWPTWv8BxS/n
CIJpt2KWpccdJtX2UwRxUfcGkkk/+StQtKZHf33kp2YRkkYVFuxqWjmm04lQPPHm7m6FbgwfZaus
QT6GdsrLPKNTpnv4rPZfMWPNW2cLjLqjTW55WlxtkEInvw1vMxFJvb8DC+2qNknAMUgiSgGW1S2Q
CO/OjJhg+cA7lP8P0VaxPb2ohDt6mnvC9wc6gPP8PQm7BuKp3lVc8IsQHKAzvYulLKjNKWwKGSqM
vAlY5F0oQw5J/ls7GC2IxaLsBxMcTIB+BrSZ4HPfIXFkkVZIb69JRgGPjr9ZCR+SdxRLkKRT19jq
76MKSm1J9BrpjLpJUl+RqCUvdaaX2sdiVBWPVfVGl4Mpm7vQ8rBY+EJkAnjwADdA9qWC3y7UJBcQ
oU6sUynK003lzE39G7SDd7xG9lBkM9b3asRgCP6PtSAUzt8Ou9EKHfC0cGbyze5gnbUH/+5zU/ih
dW4McJfHUfnKx2ZLbGIAalVhnP3AM6GeUjBl3AWh4GdhdGHzGdTG3rjavI5ujj5JN5VrOIwkih5Z
Z1NKrIOGV0nRmtaArYq7iFhnj2Rd8iiGGQXoToC+FL+mB+MTpu1l9+Nx4pMBgdVtqpZnk+fTRJ/F
/ZNeOffMJ2jpc+Q4aYN8LYRhBP2CPajYm+7fw34EacmCz8X/w5qiTvp1WuUvWsl1THYiNJy1fwko
uQoIgU63o2P5OOrb+bxlhbugaFIVUPyv0HwrcQ7TvPRlduSmr4DKTmKZqzXFHvCLCOX+h5/iRYHm
seQFWCTEZl9eKqMmslP4doZGybW70WFmi0VuUYFOvefIwi+RrmGToW2QPFbC7wcCr5qo4NeV9MCt
gkG8qTOiBvRAMI2agSPGSO3qbPj7FkQEOjW3fEi9moALGzATAPLpc3pwDyNih3rgQeTktrhxjDXd
GEiRTo5HTo2LWol8E+jISay/W7cmyQu6jsife0spdZxx3i40f+pu2aoUuB7jGO1kMshU0lQk7nFw
KjEOIpbuKvdcvnH5ae9eKyoXTpvLPwDzIQNM00oZho073ze5wgZMgmnpHiCuyOR9OMxz5QB1VlXW
wWLkITuiKLputLoWEPObwEm9MMePUKnMTI5L1wo86s1WOMc11OfKVHDKA1zTx2DF635/+G9+Kr50
jEoCfGL7fctCLDg5wcXsY6k//5tLXfr7+AjWBoHtMZwXZ3pX81yecVyKFLGpv7S3y1AJWRm8kLYy
tTHTseAImi5Rhu+7p70VcyzhKz3zsxWNdm6sOjYNy/hBNWwFwNJT1fyAJU7ztf+4cBcrymzJnhPi
V10vGPrGsqcDvMwBO0cW9TwNAM/Vks4pyTXRFKWvj66llvroWes67L54zeO6pHmdpvnRdbzdkV4a
FbNMQ6W9he7eT1SxW4UjNgB/mQi76Tf02oN/Do/iYhBj0DlNbSQ89iu5CFZ8ZTwpa2VtKo0MTpcj
uy96bpt+Aejstx/FfsrLQqGyHW+m9t5Qg207BC934xAgysbibSyPj2D77SOvUFTN+GYGQ46po3hO
JQZugaWuqCIQYqIwbG/mqgQuA9gV3g0LQLui9GNUyH/J5K2eUaqdKC40U14+0VO8acBztLMsq7Bc
AQA1TvIQUfheL+rWPeaN6XE2/01YJaeH692KL978RycALzzG2svIgASsVXX8PUhbEdtxc+O3m85C
IoAyFjG91xknLopZ2/0tlrVjRNeD6acul+0Lvk3FaamEETKy8e4sc1govDD3v6sVrwc1ud6apPEj
fqWdl2sr/kmMgWip1b4vFz0zDhe8Ljc8YniCGlCFNZyGds+a1siJVbrPpIXxPDmMGFkY30/lJ4HR
hAdYd6/BltC/A4I5kU0Sw/gm1GGrCoIbk7b7f4DVqCVD/iiB6C6TeklhXjtFBzttxvJj4eT8lmDt
6uVix6eOr5fdzWGcJ/UBiXv7sVxXGDIqI6m/wJ5c0g5/sKiGW7Y88BjF9nbYtLfLoe7QFyt51mI7
XkLM88lIW8/LS/PIIK8AqwQh2HtbPfU7Bx52mEoE2abq0HK5ZD8MYiqQWMTdTisE3ZZ96Y2OthL6
NnLvf3tc5o2cFkbbjTnkRBeRO4G3QlbZ2RhOYqx6x7viTcIjhH3Xw33KZuc37y89OcQ8msGNn6Rw
YpbXHtJoLDKAjt4VXpJVja5VO6exEf9Gg+pY01ghgjQqSd0GnEhGXZDWHA4wqMYEIlHMQcclaQCt
zG5yHiCrrsllDT3Q+fKtLTEhzvp5woFJPNdm3oWQ/MyDvhaYcYLjIvf7jfwBEW5qifJD6CVUAy+d
UXlrAsMGVdaEWuuTwognX1GQEXCj/w8OORsBoaRUAm8QFpd074qXjUSkXVAUYbFTgJhgKbmcV3zI
8dOEl6gZJoCWF8QDBUnDAg2LkT+rPYEHWJ+I7Ix639KOmiGDEER9Jlkkom+NnynsJudUTmRWbHOU
zN+26M1kZC1JYjaWJm9Qyne5oVjLp2y7dZPWlZSBH8qD75YagqLBEV780wvSXiSxyrmo9oW6mKCo
QkeFEf80uXcXMNejX4CdmmIBDcEY5FN1VPMCx2GQVcn5/INvt5J8iR7Dd6nUuhHyMdQIf9tXHqiw
22RvW6KsmPRo5mK0AhWwb9PMohLsJEAZuLXFprsh7AD/jn5MURODW2Mo2KX1NNG/XhBn1Bapen5H
sp3fCt/rNSeGZn8lXHID5iM8TsVKH+lN5y5B49sx9ELBV7bYRcVdasgycPF6t9suSp83CS01XMTz
cGpmve9IfdKN9XfpcFag84VQlw1W3o+PWEGUBxmoK3kOhI8iom8NL79tLQoZTZr0byXoN03wXMfQ
dZpeRb4S3DLdQ/6A5DqZu6SpmX4FsYAy0r5kjihGj07mcZO9NB7+yOY8CyAAmOgbNm+iQijkbqKp
xjvDha8SIsJ8SvVY5rp/WUcTz4YLJWWwoxYwPTUv5YYBpq7Pazt230pdFeEbK2wi1uRIzHiI1H6h
lhvXtRo/YrDCs6g5saOq3xgKzTMuGWV+WejB8SzppFMq+xDqT9C6g82CCxaNLwG87dpOesWsEF2P
Era3i4pcyi/A8CwuIzHgphbCke5wI1rnQVtEEiorgOdMrlqNaDVX6xaNL/N8GVz8V60nv9yoMKnG
bP4gjPFHzoQpEiB2duJ5yUZnTY5RUFdDy+Pp64aYqDq8DJuaQntjgseauK1V86KVsMjRmCGPUiB+
AEHumLPaHeuHuZviwgkxk2J6VBfSVZ0ro5JUUMNNPrqiu9HIi3xYbnQcFbb4ODbMQaPDo2ewBS7/
003Rv+SIebzkrjUaIrjN469FJtlkeIhD1pqWtf+1rdl9uAX3DmDdVAtizZMhAuIBnh861Rxra6qv
vx7Mo1JAB/2wvuTByQrvv7p3sLc0Qarn3ywflSLTTwf0uYOarRNgrUz22UHhZxlZpIq6ArXX8iyy
Xtc0tkjEfTIIFsms7UH2s57jFVpGlIMvDjD8YvfyKcw2cCOB2rQT91fhefCMS/3RjIVEbWYlU6Wb
USpU4Pp/DPEw0GAVtizGEnzc5DK8ahmlBDUJTABjFS6eX/2RkeSMZJdY7AqHCsZVYnZRTebI/zwy
fFCDzr6AHNuoAu+TZHV6Ut8yaK8PcGgKyAl/1L2moiYl7UfJF3kIWHaMw8qpIzduzgkM7o2m6g+W
hVOVfjoxPKxlo4FTebP7IVQNxtuJJk0R82nSeflPlAzrymbJh+n7ojjOKAZ6UkpehSA4CtsOziLj
+qEUfsBFzbcXCgJbgprJu+WU6URNnvZY7ZBOvaEMjQKHkUzJfkTxKxvlDlE/gcoCU6ysF2sUL47z
eyt7yTzZ/WQKEjk8DebPz+io+tSmchVeTeKzTNflYUVMPDgg+WRvGv43PLOu+1WGofrZ5eJlTpXJ
1pQVPudFu+Q3vekU7xFwMpHGwi+Qul9hR/sKTWUsNXbbXxrpl7Agwl3af4FRL2a87r/Sj099YJGI
GUX/65trfo889eQmqnueUcvxuoxRBJRKbn7b0cR0yTxwwkhB29EiBAxsc5TXB/suJsGXY051OF/U
HKEgzo6m8z951Rjod1mw37BVfgumwr0hs0LYib0/zTysvveUU2Rre13+2lzxAzGdX7UwvkDIVeSk
o3zoHqdLqjd5KMab7I7UX9RCREdwsTI7c16z0nFvhNrcyCOxrlWywL6OS4ChJvhwiCFBd96Eo/Re
43YkBQFVevwYdvkX+fq5h/jZbqHROZF/vihz/K0af807RUeiJyJbht/wVBsKLYczA+BCLiU0qmkA
SLXpbwNHCF32WdSwvaoFVa/Ca43nU43kPK1e+fnwWaMjeSybz/TYE08vH0oV4Ky+n3fsyUSatDsU
+pNxDIkLbAdDH9nXMkp/vL3K5smyawajivt+oEa/ibq8cElk2/RLaLp2Fa7eOoI4+AYMLmI7ZiUP
ofaR3IHLofPGO09/lPJZHq/9zkDqC45LAqdL263uuntU6tkocPF1uHabq6hOZ7XfZURgbuBKjGkD
+5c0OdTbKOGYr1fzNSKgkG8L5xfg6Nd6C3CBC6x1f9+OxD+Vn1EUhIhFVCZ6eBQE+vytmyLSw2Ki
w+r55pO5XaEahg4CabOwNkVw981YouQg7bQLDIYLULGa0I0ABk4SZq0J9DwwpXBU1o1zTtqzZJri
GmtL179D2sGgJPokZoLF8oQzjes/ZH1n6lDIaTsPSt3A8RnSgmeBMbUdEZpCWJAqqSjblJald2+O
4XH6+mgjsAy3ZPKG7UPWPiDZVI2FGtTKTaUyPvsSxiu20b7QD9m+8MeDvXFiC/QWFXdqYOX5PwjD
800PNPLdRUdQyOENPTIQOyiSSqYfbOEDXR48kiQGFpZCTyG6pUp25Rd9VNppw6MrpyCgHfUYFRYk
lDkJa3XCPufJUXvo4c7L1fbHQtVk75U9PqIVk0AHfs6TX9/K+XAKxwRBHZ1l+tMN8qgnuR3I7Pd4
8P3QW/nX0EaY0MiXhzNTJskX7wKPFRpuk6Gx9kbuhFw5H5wMyR5xSGWdllLJoGIJSXOT3xqu2Kdb
iI0h6Tc/ZFnx7LYa7J94bRwLabHLGKc4O7rKEiOrgUvasMDIClmZWMPAZIBvQlgBuPw1MByUZxZd
eXsHjjq7WqU6FTp4FbX+J+B2RiQXfOMZrM0DI/s/zTTfl3W+mZXUvrhMq+ZucwT6VpZVlv22ifXJ
9h8tw0VQ9Ema9NyIVLypSS68xxST+A745IlGoywp/MYhrZ9Ianv9jjlcIeqhqzRmXsnJBbB5oZ+y
U1sv/cAtrn69fjm/EKc9XR6gkUsx6kIrJYFqLkZ3ZtVjuN2U89Yd+S/6uMLdhzH/DU71/+6cNI3X
G5+940PTA0d+qkRUv96MzMQQv8AdK80d2/ZZB+keN4vYDltd0N4rbHZXP8194zLnbpmWV2ohxkED
giytgS9kvWbDej9NVS8HKxeQ7ruVqfkClEEKSK2vjKr8UwA4NhlcBMEZW8/39iJPxOQW7fCMWehc
t+54MoP/YeRhGQhtADxZO9+1o9aCegMnVrh63JL4n5Go2JIiE1aI9gx7Efv7MjtNjT7bs/svyLkp
xqRvXSRKY6vGm13sFR2Iw8euMTijr19H64exLxcxoYpNCAO1Ljbx81QN1+XMadeADYsn+0ACi+UA
70YU4vaEDzBmQ0xcfjimtzZi0o4JLbKv+pmYBDS8rfJmZe3vOlPJp6VkZ7oZfZ2lJMkYfpsgGFPQ
K09AeCEBbgm6kKkhD8BeXsDryB3teP4QdIhxBW238jYZqnQxQFn5RrvUxnjD8qSYPbvSPUdh96Pa
IL4fePDYVwNtd9O7ZRWep9acngcxLlpnL7ocea7Ne1nRCYa7bHTQgHqVSPBZYzDAV9nEziVe/Ztq
1vmhqgdTGi1UQuiUpzol2pIWnyJHa6imx6GaKXRUsueiCHpDddmiD+mFWN4G2s4KkUoQr1MSfA1y
5RYPpihkcN6fMzjvlCAhQDRXfFUgTdqSDIKChrIM4Lc3WIDYKLZLAvon5lF+M1hIyT7hw25fvH2X
8p0DsirwsvwiU/CowNboHPT78QbwoCyxgwz6h7aMkapTUhJJTlff1y4uia6RHa3G2CIBbeT9G071
TpLlG6hcEvVas1BmOu+OnZZLuVGMXkPt+hUpmIlKJyvU7WZWu4r38fYCzjdwEHWSb04MMOw+vjAS
vymo5+y997Athx7I/9VUem3eqioP44gWliXFkAjdpo764CT/FaX06GeonFPTwUVfehzlGPaANu7B
GomqmaLVh3gIuWfs9Oq8hdOO6kYMks/46On8YCWcmw3rCHipKy89l/fCiHzU3HvAQjjvYMKLc4Rq
ZrGd402yppJJ1dF+FLjaazprFkAfCVTwHjuzxVpS+xPVbXvDWV5m3IJ1LENrKCHzPP+92Qfuk5W2
fgizi8D/Miqqw3mEFwqdRx0H/2VgYXI04JXjN5zQB6J+K49YDiQoh7yJHTElswZ0ZcU6tbPACeUE
flFP8qp4EEShrRg6VnBX7AQQj6BTLdsbocCw6EDkDNgsZsxZPf51uYQDWQOcfI6VwgpOu+rk5njf
TTMwXUuXoYHt/bp3uP/9G2cUAD/bDUpz+mc+HMyKfvgpj/7Sl+lvlug0+mVXMHN4JdP3m+Z1X1BN
gQz9UZpHs1Ue7G6Nc9My8VxvapVKhjYXyZ27BrzUaS5jMz07Oqv0K+HUjhjWRFgvdKtnrdwYDcHc
WjTa+HzQ36CjaYwDT3uu8I/p87xQ8LcBCtqX56wwxMPdfD/Meu7Y/pLncU0F5rkJ9lbpA9xvDutV
XEZWRgMVQ2HLFrZA3/HI8A3dPUooQz5zV/LP3HCHkMijIjIBBPKUk73c1dt4VlDmDFqdAj3p9a1r
BM2b7X40Acv2zL31XZIc4SkF74Mb9KK1CUVI9Mk8INydMA+BGQV0uCzjcdErjqcb7astn7suDmXf
w/QX0u2dUmA5Tu1nflheY4qvbw/mg+GmY8gZBkqEzxpmum8xnc/mm/l6M6HcPiTQXCyz/wF5LHla
biTCJWcc4+/BTZGrm+cNBe5cL+s5ayx+Uv8zOv3l35Yes+7Qs4Hv9LP2vLn1hH67116QUsN4MQ1i
wvMtI43H4WIFebEeqawHZYUfgcZp0uQsY0GOJu3mFRSWYx4QGVNnZfdMgRWM0PyBf6oGucrwZ5Fa
Z0BKIbyXYIWBfiCCvIMIfJTVr0gI3cjcC3jI6i6ip9ZdVrO7B/6ILbQp9DHX8NqxYbrZe7bLbrXk
A2aM3yse7pMUOZieoaj3ZUQio1l+lKZIkOc0s76q96FWUhNpxKzXX5KVKGk25R+mVPRJwTTE7u/B
BUvV6GhZ6rzXiUhVF1AIu3oWt4DP4hFL6rmzYwittLEX1JjUxodQ3MMFrt36WK4EQImTeeEUbFpt
mGvBOxsQncn5zBJDhlUUz+t8iexlzp2qNOAea5GVI3WoM0fPRZuTrpNWIQrYY3HmuDhMI2RYDbN2
c9eppX+riiXOJI+rrhaXAEdA2/gvjAHdiVaQOCqgLC6EK9X/SiCTb4VVIbj9c4Tzf1t8j8Etr7gz
4S64x/dKLd1b1g+qpmUdpFZaD24aOTwkva/ZOlKW6AmsH+S/Ct6zqoR52yW2sagCshhvzYVqXHh4
idxYRjAN5MGqaCFIc9H8OmnIpOGddV3uEXh8v1eDq/ovtreNpp+363N1nAE1U18MEUUhnVPyEncZ
qFC4v1UoIorxfJsGFyVh/mA20x4DsXpgGFnWB1t/qoj1v+KeU0eo9v2qZZpUf7l7DjYYhvRsCkjq
4B7hbUabAys1LIF4hEagoIcrKs3HGk5Li2ZKjOwM1WvGrkbdf6yMi8P7gIEVD9E+imWtHi2T7qHO
JPKHUywWJ+T9C9T8KB+tZdBVQPyT9UvJBjmUSdMe1G9XJnW5k6o5+pGY7jBf3Ss/Yf+ZBB8Oq5p7
01IRZ3c7+1hTN0aJzaCc9Tl7FzvqTa48rz0K2CZgdlLjl7gUfxDGfhEZnhpygtJK4XkWtiYpMMrx
oZQcx59JchEI51GqEA6CAC6BXMCLQkuUn1ogOe5mk8LpNhwKboquzdyffyUNxj/sxJq2vOVrvMO+
KcSa6GLYfDFHB5mtaP99eKom0gJgElSV48SxxNcCuM9LNsunV1LKGZA9yLLOhRbHwVjPbz0D8d2k
v6amCLjLbejVFBh26QSN/zIgVgfkNiFImkPevbEsDL71bB+Zuh2YWkfbaaNyDpAYYwQXDq3kCkdG
esogsndQQXxgLjLlGg0csPX71c/zI3/QO3Vu0gIGsoaCIM53b2MlkmLJ5h3x0wzRjls2Ljnx9FHB
k+YK8niGY/M/9LI6jj8VNQArAb5oJt5evviR9PSi+mCraSr8/FoUWj1FDerscaPVCt/rcQPlbbNh
TRQJRQ58C2oEEDq+7CB54m4Sb5FHsY1rWOE+8oGpcdT12CuMa3r8ngg17LniU5iL2WkJPDSlbrnv
+wfvMWChuS62/Hn3ib+KUV93kTAmclEIHvgBr6VtCLxbUji7huHsmWzdpY2xY56xcaF6FfZe7Ac3
wzt7UFXmkdAS60PmnewDDRZsxrw6dwZIMx9HoONGc0MAxfJyaz7zKYKDM9828OaHgH7+9sJe/eTU
xcI/bwE4Ozu45u5eH5Sz/lNHu+JiVBGP1zKb41+1tMmPP3jvPjfyjL25+wDY6C/e/6pTfBplIOll
8vji2HNDhWvLMNVGAGe6t6f69Q3hwrLtVxFry5l86nVQUBQfflMh3hiaEAxP9pTUZbbMZ/6FIvf6
B8WDVvayiCvJBPQ5viLtG6NAoDlhchVOOAnwJNRnyvhmX6TTHZEfAo6WoxL+BiGizEChySoNxtKV
LIxWznIMbhFllZAHLc97JIn38KRqGj4GTKG27S2bHT/5n/0vznl9F/IZBmKt/5m8xbimxSoyRFAS
T2wVAxAhpMJhJvOTnAfwIqQBlR4gkOhFtUQ+7hz79dl6R9AAXkI5Q+qQ3m+/LBlqEeqSCFb2uG94
IykfYnXhWx1pHc/ve/HsyiTxlgYGkMOvVq541EgrHdf215JneA92rWttDoKoPy+UsntfKhmh0cjT
wYNe/K/iS8cz6Y6FHUj2rpDCyBg1vk/yBvEhsPSCAGzt5dnCwJL3bGwawWZnGrWSXnX/aKzIkaGv
rlce8dz5ElkYSaIjzXH6xGB2iogA1KssfvQi3GJUoG5NC8YNlY1h04wAvV+sZBWymUWvqvjYXDCl
PVo5BNFqobFgLD51xY3H1FKm0hCyhi1hP2rFHXitzareeD8+dPHxIry93vj20nMrZcCcbkClB5Su
jfmsUJQYQhOioi5FGmqc1RBhaoU4EOJWY1m5PSXjrzCERoCGLSfl0TWwSrsuy5wagbPMV+znUuUu
7Zs2yVrGBMY0HddM+/FU9oUjf8tgyas5LA89IcmV3y6b58Y+/WLFcu/h7FxGygw14ELHGRcGF9kI
syRtXg8Hcyq7kiIrY5Kb7GJjA9XyqJOWMxYpizJLYmOjUdzLTMdZMEHA3uIJgB7ZsuiMXbi2jBIF
nBZEAqLziDw18CAiZnu5iBHjoCZe2P823faX1QsMgs7N+goOeTKEyclcQTbyV8Epxr7UTFx3UerQ
kg0/BI6Xtp3ievFR6ifr4OIPXnAqlEYy9LB1vE2d9dJa8PbLDDqOoXr3HyoUfrlkWkEqS0TcmPAU
ZgSbn8MDM8DAc5qHYUs7/Q+9lofwJKLDdFuDxDcR7tYrnsaamiVDYpIES29/jA5ZDzY/9w+7aks0
VJ9dWecHmSpNV8FWYILMZ5WubThBl8Jx7q/c3kmmdj5Z0CDFPw5+ZJtqItjVxHyfC3FE43AragEQ
InrovjI3MI4gnUmTuIsD5eUhJKDf1h8JY8CFeMHQ8h8jyK38EoQ+j7nQ2UrEP0VdHBJ9WH25gyvK
JPoMhSVlkecYhSI1iewyreij+6A9+mk4LB4CCtLai1xrp/rMON58Qq4MSJAoM/Wf2cDR/7UwVMpT
ROZgkCjUsPl76or2YSWgcrMzss/OTljXQn6dQgDdevdEN3uytQi7c7vor9etyKFa+X7VQh4ZlWhu
q0s5OMgCOC+oiOQA2QaDA7YzIE978fLS0whl72pshs2+nD3VKDDLqukXwBSu1qNL4NSnsXTkPkT4
yrSfsYgS6+tmKnRC1OK1NkIav3s9xkEsNycDa/nzkFw5iMmaj+/YoI6wXBi5PCWbogMlS4czLr6k
vzYRX+3sBrK/If7SMG5vk41fFqWOsq1ZoH5Gt3R4xTckJkeS/pBXfkdwvKjKYFNM9bZaBAN2XQGW
pQfL2jh1xfJ4SldT8k7ofGfO9xl46YAgVsaL1jKVFIPyGJ2nxc6xmCuiTje8+vrGmwwD5Kd5B9Nj
w6XTSrWxHh4c/0DIqxcloDih0AvIc4c8x1XlWcJmXNZg5UMb/o/5bviFASFkxOsmSHVL1c/n42ge
FpKWTDrof+LHatH+dgi4vMXq8Kimdpf0yEA4mGigeD8Q3BLf8cEjDuPvBsShdmRlF71NnSWg4rJP
CGQZ+C+ibSvRIqwR4zDd6+y+1asfCqV9KH5UJpEBMPsikUM3kk9kQ3Hw+LlkYwIERYWejdncNesv
iaEYPPqHUTcHG49oo2x0S9ZRPt8RABZsL5mKpxWISWvJz7gDbhAlmvOWISI9WiXLgo4gUYmxRezQ
tCQ7FTUilZ1w68hZQfuEdqsmSKHFG4ze10hm4ktQf9NEbR8qUOLg7tRHXH4m/4dOFnHQTpZ5+6Zu
GRg77kEMDtODKM3eMbzrC6CLcnSyf25kUUNgHVTSof8i+rEi4+H5denssaAJFZ04UG2z5egtYAgv
Eo3Hjwdcj3Y/9FheMVMbtvZxgcV4LOXDRh6lNfR3axUrUI4dz/y2x0NpBxHx81vxh4daE32hZ9o9
ZLnOjOHuewzB+gFdrAbqktxgFtua5f77//Vp4j+1ggvZLPKddOJa9fgRJyuNbgbdwpCiQXpZ9onX
MrsHS/GxpnBUqiaVDir1NV7MWbJ2uLftTaJmtH4kOewaKQ4sygamnl9MUDIGvrUrKsBGbPjG/oKH
0uPnE+HFlb57TTj+N6LYXSC9W2IkD70WzB/EqLRPkM5K5YLlvknWrmUyk9SigfPjoX4M4pDKXNhO
GKB+PSMg+s12LG4/pjAaSTKQT/J67MOnhHqxZgzmwmRCXr4IkmONwXBNKEXpNxtVXRVpzDxay9yK
/3Diuf1nlPqNSg9Y/UvwmInwH50ai7wK06W4DTteMAlHG1zCXgvFAJJO6/g/Ls4cs/2ftN1BAL+S
Oc3gJzAfQ2CPi5EA15PzmH5EQNxKgC2S7Usj0tkvGLP0Ey57XJJ7bjiyEDdevb0s4E6cnV80tUav
szIde8Lv/OxMfhBnpJJ4DE8H0iwW5uZjEC9EQidelG2PDs90/Ic4u9plivZnoq5TQe88VVMCM7EX
1O6wbCa7UqJHW0BStkjZCvUesaNFuF+VaIklhMuKk8NL8YmQ20ha4wne24ficw9bu0cyxhIXvgX0
o9oFOUCbG3koI8rm4w7gO9Hn/o6zTCB5SU0L0vXyUCf5OCBRQYzjlRMGXj7yNyXgOECqN94VN4VB
9uxWtJdDDI1wJE0yuSIKdsl/HDu3nyXU5yEhpG56S/UTOuU24ZJ+Tk5HACK7tsWDEFD71jvb+ArJ
YHxFDXoUihMVGTP1A1JygDgLmgvi4xDq5yG+gDPnrahV8rdCpFOo1BV3gjwe6Zn+BBXAFHc2dgGI
YN+NYYKwBg5JUuBdbHbfc/DxJW/i1yBJ+CUIJDKvDg/jywB7SQpRrNQYVJ6MndK56ax/LNgLp4cN
ZH0ppxDbpGXsE3qdJpUiZ1dHCJsiOh7kSNl1SstedfrryVajRtJIN2yMXTgKMfl0ecB1y7dFB2OS
3OUkl5flJtp6k4IE8Um5gMD6WYMXP2zYNBegwWONpP8qhmHTenArbwUNGIA6Oh0ltmYbocFhvvmw
/z1SXxXzMmTykE6spqt4M7oK1yFKEr08qIQNYYVPpQ/JfojkKZ+fqQSMWN9bMWAG63iJrN6t00n1
G2UbSz24H1NYPxIQhUwPftCYWOJOYuSWkLvFxcHT5OBUEi1NtzFu+/UlZdC7eHSn/J184ptv6eh7
pC6AWKueR21SMavbcF5ExtrTBqVBGR4ue3NJWobcEd/OgM6G3GnzhyqiKWWbfuJAt6b9qC6dj8JD
W8/jgDmgkvKnRwRQsDf6mXRpSVOFcggFGJ9Uw4N4x+c72aYvgSwEAmE0ysCMuaOrQzgqFcvGstAs
VpGpIRN3gdSkTwMcuq+xWLDUuof6r5a30IX22JfF+TfregCguoPaydu0fhFD3Q5gHROSIVDlrH/A
qtW+mZxv2HxmRkjsNQRRuMigscU5sacptdLqIcMJqQOVXCmvWxJhGo5P2yLrmMIiiZj+AJd+d1Cc
3dSqSIBPe1h4FGHMOG5ymxrqWMuMBZMxPhr5A1/YeaDiSD+ZE5F15wRrjp1dVAduVLH38duO5SbR
ehYZgP0BDblGNEG7AsJ/hMYKVMuuJVmU/8tSp5yuTReUtjBOXvM4vNIIk1D9Tz2wxtGGgPsDrzsw
FJCMnJCBpqH4SJOYKGPMvXFJNkOrHINAJPJs6Ga+RFOYDVHu8HIMELQABpD35AxHqL8WV3DzMRQg
dVgTjDXkexXLuUxo9NkileWwlIoe+rDMjbijgM93Ii9+XPOpPTUsojFMVImuOsUi8b/YOYnmHN1W
/eWFyatkqnzLyfdrYcR/mVpdpMVXHWatVrm0cTm7gjiJnPiMLeDtT5dMOjRl6eN83kuiX8dCJkX6
0UMR/yzFoMN8IkptUEbEtN20KpiPY43h3pbd/ojOH26vInvAz5gvT4iHGdXV/KPGdpFLkxXD/pOT
iWIl33i7zCjoQ4mD1O9uw0lGHDmS2PVEjhhbLgOBFj8nQbh3PjKaP+b98rSBiHTbCTSA7qux1/lr
dN2ntOvYa9lfD8ZG5iCqJBcE9f1VX1DyzX9gEvgl1vZLytHbdQECmKVNd6OL9lbA9h7tcFhRsu0n
xe7IWF1jjhj6EeAP9e/h1tI4hOnJ6HhTthLLkcT10rIW0h3zSKXbTzstg6nVOuPX+fhoC+2hIeK1
t7MjavroLffhdSeADcMKXXR9RvL5K9GIjxH7I6nWn+T9gNi5SIGx+NIgYSbWcq39ywMswCgC1Tbh
1rwyDTGRRPIPcSEDAkJmIqHdCQ7AQ9DVLUj0+XNJe9Y8vqgE3h5X1du0iyFQIjqPs2i8NhBTBEwv
eZwle9aBA4Oz3GsJHEeFzJHTc+OcDcKqUfdy1e+Axc+ypAB/Z0JTKQoFyoIA6dJTC3oBbsRDG8e0
Cww54hQ+6/ALmnZIUbJePcmGTb/aP/Vz3TBWOIrdK6vUpQ2nU5gfbvmS/dZqXNzaLY5zoc9WRNr8
jaHtm6WxDO/k7wChBTWfuLSCaLvnsXcrM6jEu9wCHnk1668MeMBF2XY8dVC6/OB21SuCHatdT9Wg
sUd8LVgbm+U/Zebphi7rRz15ntxeCAxtLegQyRjFY2ALQGmN1WIX9C04BPTGzyCSX4BPxN5N0p8X
hunnnVkBBBZqoO11E69Z+kM+UXGzaXiQQ059b/R0/zThf718M9YibbZsdkmFxUEDQcheuxub2FV9
C32qKoOI+rVFaLC5HymZX2zrWU2cO9Z5QqUABlTYUE70jhvKCYEIBBFjE3fkGk6aNIRNZJ+yn8eF
2XmxpGKSOm0z+H9ZRiSVSVGS+LKIvHYI6dflxZ56VbcnxIJgAbGVXVdci7sDZXABYz+rbLqujs8D
CWn3JvAAMWCs+KSJHquMmbRAKJyXQzIh0d5XuYcli69UaDPvb5h2HkAXRJ/KfZriVovXRO/CZdHp
oa6qpL5NJzFFxzCTRF7T50nlcyM79r17Tz1vFcxmzJ9QdcF07spknoncEkpv++uv2k6eHR6OqXt3
si937LwMm9QQ/1VYCRMe6Mep7Gsohy2qpPW1RnfjVEQR1zYlqM8b0v5X4PEp6XtGpPcCI6lhwLNI
Xkrzm5ymudcjA8LXytuvGXrC/ACiRRRbMk8NHXbL5OEWsk3nOGrvS1y0H7sX2nf5Lib+PTED4JYZ
7UhPHaWpEYnzyUNhrkr7R+8ltzT8Jcen0vfgxjQsOA5KsJVikzT5AQ84ys3h5t17TJli8VQo402W
jvw/dBedyx/l8bBGohNBJb8EBYPOzRugmG6z/LVrrt8f0wfzdgjm02E90JvgEjBr/cqCWwSI/yZl
HEvHdatU2240/zIw4agTydkOHPsCUfe/TF82DCtbGBe7fhuf9f39s6tTO1WLcZODixSx44K9IFBX
Vx9WqJg3Ow2/mN086hyLoN2968yTWhPZN6gWz0r6Awr225U5+lds2cJgcRTE0EawdaiQti6NxVQj
+eRIk+sopRDN/KrrmR1NLBCzznh40chOil4zbeUB6Sn2Rmhrc45ry48+woJbGFwfBvlnxjVzFI7f
ah5lzyblowHwEMBDDh6ie5P+GToLED+r32WGhseef6sz9Ust01hnHWocoCk9bMpcmqmQxM3iT+2J
x+rSxHyZTFsbB80Dn7cJo8MdySlEPkBYQMPCUuLuPWvOz00qTD7GIeJ/N9xsVeIYey5ykuyTf7X3
B3pFebPzyPEQjPpvBq9IVBdKD2mqo2MqBE5sZRfdSsjelEj6JVfJY5dfeFEWrMi2dYZ8EolSCeMH
5h54lD+ulBfEQfmBDC35sOLMLzgg3rtEm596nyX9xQJgcSmUJWdgZ6xDl9PGHTLQtWOh4xsM87/K
OyA4uktqDmtUISGEDDtSw3vv6mPdg3YBJCpS2lnA3jVnFa4EI0cVkCGAb/p3nHIA7swYrAmEAotq
pKIx/feiYEgy08at1WNFxs+GsevWdUajtj6wf/Pqm800PrY663bJqISzh0/21fBfGp7Ymveg8a0P
N4cfvIg48LBjLRwBofmOwCxgxo3WJLlEd+DPjDIDqeVq98C82ttSu7478BhcJQCdLaef1naBQChF
KNVB9IGP8c+N7jIz5q9x57NzZCcq32Sdpmi01Vxp4E7YpXPylJxgpxU3ZNYCnxqIc2k8ipUKSXGL
Ei8QX6WhmUCHRqnz/ZemvTstomX6k43U3TkinfDwIRpoedeH8ONU8MqUkNzy11ewdFIMqNPJ4dtP
ffJrKhBI1/9i8k8+6qKmHAo4MeMlH1epiLsW5UYXJisqOw95TCr+kscVtU8aaCJ/ySsiDqbhX+l8
EaCwUGhwz1T/VSQtwzKDUAlQHje2ZwCQrSZqUNzKEtUhaim/OoE+bsdqfMO0wychvfTi1/iQTHzu
sOv0tN4IhqM3RPpxMHf+iVWe3AiwZHdwu9EZd2qMRGgy60w9BySud6ZYmpB5DOvkzItLUEIf3Qm+
kQcwYh3LIxTaoC8QipO9NSs8fGz62uvCq1Q76ilifhuX65AGwzsZBs908aairgACl+410S2bwsWo
YQTJ/Kp5cUdPm3v19Jgs1OLYM7d11F9aiXONG90Q8Dvrc3ffYfUEVdjL3zqhApgiYLNjwQDDvvqb
KoJhFbb82nBuqY3s3P2i8PbiSN8fbX65b/GPSP2phfDj6Y5+sJmIBtp15Oj8Vhusg3cYtcj/596h
cyvYe+0WtX5pauoP+TWaqTlBSrZiAHZh1A/Sc4VoXA5goY7ZuS79kK2M1FTQW8OBjTYWBL+sfCk+
N7gXA0w3RnozTiUNaT+f3SQcCdHBG8YO9bCE0xT84JvOXgE1J7Ny7QGUbXq/ba/fV/14DK9BINe+
5MJZa6GL2eTDsjeBsRcu32WCeLPFAPJIUQlMWj76JtW3tZ3huygGq08A/0f5DS2cdYB+XoRbdC0X
Hxq1q07hPHfyZmIkCUH7HXf0Pyxm+7VHixFDLPgodcVoZ7bdsWJBU+w0a8DZaB7rWCJAMlH8rj+L
yz2UI8mgydUz0EeA76Sc67pc5GcT/gBV3jmju2oKBLucLnDNK7muXKcCmfboB6xdiu0xxvNpPbHn
eb7uhclsg9vKO7cKTUnuJMXrYUGM75+tY65ebNWqus6HzBLc6xPZ6ILawujz3oKa6SmOjsMP2/oS
6MPFDDwrZ6nXufR02MdORugN8K9MruUEZx6OGXOD0I2/2Kb/cEyp5uj1T04dBrtZrXDaTehB1ztc
Nulx/e8YwUp+GI0O8l2+vFCXzmR2Hw/PWMKFsEq4yQtg30olf0vXumpyOGuUQWWbq6mccYaVvna4
cUgan7yhyqnHEg7tQ2sasAwfxS/hOpGN6HDBnl4Hi4x376iNMH0CmcUarcEOBVhuveyJURttrrLq
9v+E4MT23Dc42//3VZb/npSSbxTtVo9KngZ3EZmSrYKP0U/GZWOpaqO40Nq7SUYS8a2uKhc4kkcG
TWwa55EpMSRC1xHX1uTGqARgRpJFNWR9FYN1zaAxIc70z0YEaGNIJ79+eEziSDLvsErtiJzxK4/1
ZWTe0bvfEyx1mZy9XVbS5Cc5kHk/8/edjILY4Wa55EnDG7oF2X0Yrc8JbHA4DixlKAdbebbzpha8
McGqdkuy39LEunGHTiY0zZKhcppiu/Qi30st/S5G9W3wy0iOWuthVSSJtXPOYzluq22BH9E7Th9G
IAgqI6hzLouyti86+VGhE1kImV9kSP/VRHSuL1la3HTfSZn8/F93Ql4F8RzgYzD9OALlKoa/Ykqj
Zxz6h0SBg+xmmR5XMTuZohuVJcG3mK3f5RZM2/1YI9tN8LAqIrRwjO1/QJ/9AEeAzOh7vOzReWkP
E3xbYkNq0l6t5vNkAzE+cb+IFBWCIUKaBDxnRzmWgYh35zPuf98ABi5tYQSSnB1jWYTOAgV6nTkL
wctlLvYYQ3JSfutAXydtSDx+C7EY48Zz+nmZpTVbcBvwuubbL9jogDfOjnrtMYsNq6nckMnhC2P1
lScJl95vEilqM9Fh4cUi9XeCNi1YMw8aGJhr94/TItJtHtGzm2O/lqHxC2GKI1v1KCy9aalIjzrh
9I5TQIifJdxiNmnQW28AYYR1suZkPxU4+W1AJuUJpyMZUTsZWwL8IRAOh7JiKCDBxVREM8rreLU8
K9sAsdEjnPnroLNxxuWgGwDSJb9yh0E+2RJSql/kxG3+KN8obcFKp71+1WRpxDNBwz/xBSIDb9Hm
5u6RMvJuNzSwbV/ckj7x+KCzrt9r2pdopvD0fjObQHUXSCUUMTtgBKwzM8N1Os8qZ5HKNMeOtfny
/lcjr5OXMT4vNWz3R/M4m7GfwCJ8KSFlTvauY9SI1fXa9tNj2HJgu6HckIdW4ekDh7OMvoFCZt1W
41ys2agfc4XkkMXfqe4eWyTw1dmpp2wQUEuR5HKgkiCxJiZSa5xNaDZ6p+vuZzkJiIga3yNOK6To
kiUlyqz9KkxBnZkTIYyLlBIhY0p8ohGMQVyGYn0z6E/rq8fzej2lJeaOcMHXmU1p0FsLsPn/MtX2
zcwWwZJFyV9fJIng5ZydHnyKQWbuRl7A6IimjzGToou7qk7a/KGLrE66t4fl3bXzMZ1/cA0zpaCo
neqm8RK1SiFLfdKHwwRbb6sLypgUzGdI1ANqFqFUzVhhTFjEIpPnaS8GS45gTCWnrBjalUq78yyE
9lB8wv2QC6LLzxxIexTPRbTkrjnrKc/FJsFv8L3COEk8XfsZOyhQGLtjZP9d4yVe34g4uXzzb7PY
Otqyb5Sy26csFNJ6VlRIxTWIw95LPCEiJADzUBHwxai3RXzLgXIo5EkknI9v14p0aJw8XxM9+h4a
zsHL93eEHhGxyYaF3MoV8K7vacrsdFhUuh+91+1GdHbkl16ARf/kQ56IA7jNxxXmLKU3e6zFy++Y
+552sBUrWjGLdKpMtPx08KMXWtqjBt4xE+gtRchRDc3EtOEjg3LnEx9yhN6z0JcPIjfJ9TDFPvy9
FThsetirDsGpOTzYjMS5l4VBa4EX+aUixMA2Co/44HwAqc16IJC+kzQcBI1aud1uXdx/tYYT85JI
2C6BxtFXzOfIO87vhuOI5wx0wHIB4rlnnZ5ue2sobtiTg8qEXDx5Mec8Iatm0LjCEY+gDP6X4gFO
oPGcJC9kqtoCJmsqwpGHC03nhIietX3xLzqRCdihMroesNE0q/iK74kuFX8pXGNJzYP6mT/30wEP
fIjln/1cVrEggxRBRAxaYFl6+tiv7e0Uant2WJXyHOUUxJmIiG10WOdkQAsT4Cq0FPM8kgu+RT6U
SHNrUs/THYo/ASz7xDAode6HwLuRpz2F8vnrROkoDlBgyrDgTcnKZRGB9Cl0eiA9XgvZCdUttVv/
cgQsyc0OYxBNKQPIy5K7ed0YTtDsZpdfqrH2CKCv5jumwIrE4nNkKF/c/X/6anVAcfLOZvpL0UsE
HMcY+tD0rO+syxmbOwovf8hXGbZrf9NCbsaFTkocy9jn9q8NFuPxnE/QpMwDoHgYNNOzaoIlMc1C
+W5PpS+msKrZcjVZMKfrIhm81FvC/Qx9InYZPfweOaY7CWu1FLH767du4wG2vtarOgId0Ou6iryV
3L+GiaQLxORdqDCW0hlDjsG/3hIsJTab90Y+JzSpUe6qnz+QRfFnXOL6nxqmvhKzuUmuhNaR0K3K
4wj5fmN3TeATuspVVg3+7KfIcOR4eHXs5fw1mIROpv61UTcYz3SVI6rJAN7SIhk+yihZVCxC4TCn
XbYNTDUqcRHg1Ip6Xmd/rF+eQz+f+h52wfB0tyhemcTMywXchmsqUIjpr5mHqYlxibxNQ0Qi2He6
6u1O5Z4JmKHsTEv5ebEU81M+vkNFUfkHxDZcaNMzNf/8RvkHv8DPbEgpfkJ0qOxGVz5SSMeS4XfM
GfRK5lIoZdbj/5JWmt17iocWjB93uoRXL/KzM+DOUj4OBYkfFEFBVedgUnPDXBQ+WGlBJvO5OtFd
fKStmrvFLJgjwzY91X48yN3N0YFHSNaxaouv1T5C6wtmq2aICXX0qj80RU4/nwIT/dMu4VFMTh+s
U4gwH1tQ5ZJSBxjUgNCYTPuu7o2vhe8Out1WNA6v3obfnZ9h+ZBh2ZhO4dtR0VkqsH+Sl10c44cP
jHjoMSVuSLtjJOnYiUx++GSYw/+ty8KbXoe+yjzp5r7Nr0319eQ0bjrmpIAh7SzCmqAxKTQOb5jS
fO8ca44y0kBB/ha7IEwH+HWbuDUJDmbWfhOlJmoJKUOZA9cvz5Jf0Enr6qk/ECiDWKCr9gRJQ+S4
lz4HSeJSBUPnMyRTBEu1cm1G5OWQyW42jQOrXxE7d1fxAePlC+/wYaWDa5AAkUbU5Qa4mrybGn86
Ip6ZpyOarN0gAWYL88Zm2zYJmaQf2X3h39eUts/rB9Z7eG4jKOt8tBaawymaknklaQckQ0TRMmEU
8u6nOz8NcvknAetWwJmMVJH+WSPol0WF8tegqMHLCHsiLM8ry1TGEwQjU+RxsJWHY/LTZUmxoZnz
1PcegznxeiKTSpdxBe1yBleED2Jb5uzi4ggFSEuUUdPoJuuzH37Wu3GrA7m+AlovJNcvgHUoF7Tx
25vt/TDPJ3QCQ3z86h2fk6CaAi7OjSX5UqXhbNzMHafjOZjhdBwBrWsP2DVDcINjJ/OBBzuYXCTz
UwqfbSlId4zz6wkGoaRbqGXSCMEzUbPkpFkmkbt9DtJ9TwUYEbzrTUfXgBSJVjUWye6CyJo8MQW6
XkRGbt1jqm+Rh2yodBQH1/JEx95bUtU08EABEdzyN+NHWIHqEtPi9vPyGWJtsTg8/7g+vyFFbXtc
zmdncc+FJumtLmunn+QNXS2iFuNe3LBvoifm21jblfiLZArs51ggE9Z2mP+fHM0Jh3IzuNsbT7+Q
UoYM5HO2uIvIrgw0YOZ6KOUSSbCLxVxL6h3YrJnLMxGmqjSdhSt0UV4gHonxS2SP28E9pd0hx454
cckUM/MOd0A9MLsHq4lnpQclbGE9gpiCUuJR6daV81P2XNrTz1WF+s2omGAzXDBZTijQlxWzOUlU
A6OIx/moPGz0UIYJ1JwydK7PrKxCgLqix1ADssuWSBA0sFG3DAXQi1NVlVxwo2G6vyhTNlult4qo
gurBu0qBRWfnLwFTYiilHdWRt8OVX4ldeRatbTyeTrWZY1SI9LE9ajcicOi8fvWXCgd2u2fCpyrP
YgyQjBaAOk2br1LlSnMFo6v7CBBjKDfROhSpOlgMqHWSD7yomg/aotDYcLTNfja01VH/cJ83pgmF
SMF9cN7MOee502v7iTTh1djq+MDxjJu7hYW3DWZMu/EFGHHDkdIdgVMmzcsyXO4uVzGYmpgqC+ti
EwFLgjK38AImEu0UYrORFOxQTMRfMZQSbgwPlmsWGfD7raaXM8xpcRSCuaE1ZAhdrX6GO/Ktw84E
osDNVh1J5UnezLaBAXxrYn2K6Y9kSkosls/hy6wqKgPb9k86rRYjnZNNxL0VfnRK5CV6s2MW+BhG
/ETkCMrAEfyOwlRXgElTyzjvI1ZVE3eEPFC+xdKfa4TOz33Bogeljv65DzjcHAQMchqSWXAU0ao9
CXjsS3pbA6wiXWlj4Px6BXEdbyGG5QNz9ba7EMGDQJhPLeVGQWhG6D1cZr7Cbc5d5ORxX9jc8FAk
4Vvu/BuMk+Qjt4ofNZ5WdryjTyM9SKg5F698dH3V9nLTWFqtkrFBNCfODMODkQ23JleBBAiJCm5h
paIBxVuGlx+DMwAL6Ay/dmTgS2Wc21V5CLJBqC5xVLI6d8JxJMK+G5fsmO6OkyXXYq5E+qLMDOgC
1N/AVhTXtF4txVvfrhlOmRppzgIM2Do0VRAUfAIv6NYnyaaZJOElM5jnBQpL2mwFCspX/7PjVUOe
iqeoBM7WalrS87hu95PgLpaBK+5MTl7hOCH0OdmybMuGVwl6pkQrS2j82b/0WfqmVbRoHkLUQNtT
PKilzsBHr/Uqi1olzDsl5e/JxtwgZpb6Ar9LHQDQsfrxAd8WceiReH5jalnsziLWXHTmggTmfkRm
wdXEJPIqd8n1LIjRIDkIGffB/9Q4O4jqsNLwwcWH/jIjC2Ozt7HYUvnVEDKHcUTEmzqdnTxlwbYF
qcS0WuEhVGQUZ7pRaapvZ+uYQeVjKO6IEWL2H608/Cn+05pEVgIlHQxFOqkfdHtPceNMpygvx/Sb
uFVvFgpkMYFi/2WfnqJPIidZ/qPq+lxTo03oGeV874EEYjYGTLYCSqdLH8x7FfGynEKZaRBkgk9I
k0sf6dxtzHambo0nZnOwnazkCkrpAAYAlp4hiZWEVUsBn8rVqkCAX2oNN/jKWX91ym4nhepLLIO0
AWIgjCgmNRtK8RSuFqs5FD3rpfb1BPL2hnxl4dPiAIzwYVOY4DhVnTO4X47V+1u6EvX/ZmpNooqc
iN2rMuSQpDxzk6cvcT/1zpLmcKS6wZx1BDCmA5FWRC1dKXrmAQBsbqhp4ezVdTti0NxjXqWQ6UUN
XQxWTYkqmcIl8YYjUL6ltxCWl0JQ4yfPa8L4bNEIvoXjZMIR5bDa5hgV3bfFWLOxGOHQe7g3A+U4
wOqrtP7Gum+i2fXkXFxQmWMVAV0yy3Oz9N7+R9rgtDNLrOiZUlQIbq0SyyJsiPS6RwD9fN7niOHs
cA0zmK8OfVdWjx27/99LY6GAxMhyFynA1WPWYVjeVwgm4gFlnidt1EOJB+v6QU8J7zpO5aKtzp/l
QMe+MjXLVCJ5VL3sOshbUZRRFF0/DEVXZzYHAlxxamx+tAB/b9HXMW26EQxaaZKBPpKhiMLaGPno
dELNT/N98Iz2G3DH6746KQSLPA7GUz3h3NRaMoXFjhqErVZYa1Bjf+kJvK6LIYkWEnmrmDM8Nm1F
Oiz/sOiowL9kmwzYRx+Fr0hOLBx65CimLWvhJQHXHkNimeCRNqAfgnEQ2bvU1zTvx8hPS5Poj2HL
w0NweVIKxnN1jF5+IgtutBTZH5oLmzPS3yyVDK8/kyu5fPwOuhsWVjxtOnbImKjeSUhx8Op0p7kp
sdFthI54zIXvy+5X5GMRNT7Qw79ty+r19p70wD3iWSIftY2nyBzXKQIfTWirTipHLolG60plH5fR
9eoOvOLlki5yOQPp+izCk9eee96jM9DguFNdCQPhiavy3T3zjnjmYI0hVhzSqg0xE1XKsmLVye1g
6tzR5Wnz+iahruHsv/C9wTLiYFBjDksxOnkSNvykYBHCC0KiXAx+t1MJ/Ev5NWPIxpjpV/s/hQIo
zzaYip2eYye/KIsTmVdGnQCL8fHzyOulLbWhi/3Oxf+6t7ptNZXwTakS+eWhw8svEQ8f96vQ4y5t
evn3nVi8wVGcUqUNj6PCZ3vMHLiH83ZLOsQBH1sYdqb02GF8fnSG9VljJMgNp1ZYevGMao7yDo9Q
ccG1+PlVrloCVTwnQVPpgEpq7BoR2PZJQDzb2O6eIWaMWWA9Xx6fKcR4DsOqxkwKs+ReUwI6O/fs
ijPyHtnh+Bp3t4UE+m/QBI7nU6F7/SrsrH+uBAt4P9z1+xHkngssVloCDOHj16AqZ3IHecVrETGG
cP3U7FhkBynxrMtj1vc9S/iolVSX5z/fOg2dp4ZZpET1gzqTHOM7N5XCAmLdGpjl0F11W2AdfTjt
Cral/lwuZ7SNsPFMlCc5FkRkvFM0Tkihfeu2BnHp0iYlpUAZSFUKty3TBpWd3o6PxLCOgs/uwShj
ZNFqdFQ7HDl9wV3o8P8aUT+FNos0+BMEjjW1okFdaRDHoaaLNQJ/ofS5hPMkEVP3ILv1tB5lF0MD
mfTA/cwfnMxE8TD8z2f4HWVzySYiNButrnzUbIkxgVJnTLpqCLDsJLnMkM0zwk1Cw38ZOHMo45Q/
YlbvZ8M4nXsB54mOzQkIg7qCsQeqmjn1f2ANFIisM65oz9vpjRnAXWksX4dyFw+Oq55NxPwX9BZR
QiGHtATOalQfdgUKBQZ9lB8qHHnLrNXsdLdEcyUGF/ocDFGojWq3NEZIyaQcsr+utuJiv2f5hta8
EeIpZPopmeFv/34DMEiwA17Sll3lXc2tDOVdk54wlvUlqyr6TbRqhtLFlZ8BBkP5FxaDzjEIvTm2
5kMxs7Mt2ceOU1Ah47lGmDheBg6lvu8GJte+0vXYYo5eOz0dSr7/6XvN70gRYFTNaDwJf8UrMoz4
Q6sxX6bECoS3GHJ6CkqMC9c46tITTVu5YCaOJhHNS2zYWGbAesRJpUF7Hq9PiwtrNVuF6+wjV9ji
udXhCOZP7kWPoYX/hwlayivec2NIudjYc1hgo/wYWF2xvxjBMF+iOs+AgKAeYpnkMLCgUmKMHF8/
rBYebAdQxtq0rTzves5N0f2HYiS3JzZoXYAPoU3JYHk4opFtBAV/dxA0OVYxgNNvyZqmTXr581b/
Qj7KTDElST+F5fgsVIeKTKnKSb5xjUJ+T/xKYgiJAFbKlF64+uu9I8nXaX4ePd+ObOrTDaLKkKJ3
keWVTyfi65cHihSR6IwePrgrBe1dmNuiLAnpTGOcrdQdUodhEjF6VePvp9mrY2keTjnFsoOIg/17
qNmI6x6o22E4VyBfFzlWm9m2fThsgfAsf3iexY3S0Y5cONVydBSWQp05zKV+3KV5vy0dPVs+ojCn
HTu7dOk19qn4HMK/x5GEMgMTENfxuCo+rNe35JX2M+DIS5SF7E6J2mrO69pmijw9Y0BqTw4FVX46
KpjuIu2mgspxtOKLw57wp61KoXWqT2+PtIuscBxap4TjOIk1tDuJsfMdyVuznfiy2QDrPTCbiMyd
mYUlkcW1DGeyNpHrnbF87i1EFPVEUU0p658ABcjcmXb4pNNylzUh0ZkOcFAtDNnBjioh+DLUu7IU
OKGoQpZvdZ6WYtsxW6/HmbCzBbKzSVPD5RfxttzhIqr683Lo1/UZ3TzEpc5mAsPgb5KYxPlKKsE9
DfMNDb/QJZohj0ICJYVjPAXw1xe/IGEuiuX8uf8Cg1xgONw7kh1MHC9gYu7WrHnUi7OlmG80yA/a
y3w9fSx7wPHHQTlLvh9zuFTXVuzIEWnfKD/CgjxdH85Gtnw838rDSTGRNJNL9piQueX210FQfSXP
4B7ZgkzzTV7fXDF96ya3NnMn99PPY4+mw3ie9M97MTh1QfbQrncb/UioG3YnEmgfPI9imF1Phq7E
u3vyGEOlU+t3rmQU2g3AVoIebKwA7zNwo3w3yLLG3osNGDtJDe7yrlQXU0uC+36QQvbvEu6qX+b2
toogGDKsYfO7SScLt2LQ+8oKfrujWHhiIv24EFeZm7aCj8ffhCZxMm2awOeYO9N8GVDAXPuMu6Nj
ZOokAHxyHgYMnEj98pOTSQQemgW638pCt094D9aQXxdozCv6HRfu6C8pkca92Ho1hVZRhc7rhpmg
/m/VvP+RoPP8wfjJgs+kK+o9Gs08OnBvl/pQDkwZx1BsY+aohDHSNUMl82IDNaXugmsvbz4LsPU3
tmgZ77Kl9m4ilIV/+JdiaiWGKzXHaCww3SP90dZHsYag5m2GsH45+WwBAlChrT6cgdAg0MMMJwOJ
vC5zOrGTXyoHHUSUvxap5iTMsjurRK+gG7fTKdn8+aWhoPIW+vdG/E5gEC/LREFiqVfspSTUKIaU
4DX6zXU8zlFp2IPXTaSOArQ3rwKR7yrrDEUAQP9ysyYkF4E7GB8Ou7tAdJfv1u93LsW7EI4IMDm2
5rfWVveaN2TD5hhqdLuj11E3oLCAA6QISGys3j7YenuydcP74zHHpniJqd/3O3DKbNuPXcYowK6F
qp7VV6ruQSJpBcnRn/6eGiNG/GQaWEdzoC6+4oge3+pvz6vau3lNYBpXcKJBj1gIRHf6iz2xin+i
eswW7CqLELv1/Png7C94gcF6s9Lqg5yZm0Or34+hzwgJaxwslemPikgUlTjl3HC514fno8WyTtbZ
WfDMNtzCdg4+wcNfe2eLMI9h0NyQUsottYm8WSAtZjUx5iCUvuLxD/12dR6QCmZeQ9XWU5TGRp9M
2APMcI8OQqAIXBUEqfGslddfH6pAHlA0hV9DYblD5RJXpjtyfieoQVXk+m5HjvywHXBK9xXSNjXr
JuVJ5h0CmMwbXLyoM8Ge3ZPGIGJRX4PJCXksvNz1E30YQYLiOwQ0kBi31ffE2VW1FP2iDVxTIysn
/DZhhEdR84QX5owj736iE3GP6yxR4p04sAKDDn0T5aeGkWp6COkbFWijgu4I9VBFKztal8NRifjC
KP2VTTSxijS6+/bltExS7QRMDcp5d7oTJ45sQ0Up691BB2XY7UK1zuwn9VhFLKFmmb03PoN+4EK0
sSQ8WW/yyPsYsa51xmJbjbHKKwr4dVGT2+oINfTy3NC0gEayQlJi+vgCaID4fJrQ2QPm8GIbZK6g
NowVApn/ZEPETFsfYmU94Y2SmwxjTW2YclH33weTyVyC9UGToEi9/B/pHQOFOKd7GIt7x9LSXq7K
3kqVeYrgnHcwunS6u1Z6ZFEIN8RXX4HQ+UfFFDNBHKI9H+UygkFsDbgstCcdfJG/VkUy3MMsVC52
0LtmreWohgN28FCKPEUWYyxshmrN/BwT05NGL6+QG3Ryi6vLWt38VsXmKkfyz48AD+JCH7kbfZc5
FvWiCjUPOSo+bWDLyOEtmafkrXv0K1Bo9yBOYRqAQ8Byo2ZqRHc1oiPvyKnxtnv8nXJd22tueDfR
odgQivuRWEbrGii1kWHb8tmp1g9rUsMRGuRNJ48tGARRnC3DrQUG/jPV7426km7w2NssLmwz9RBL
FYp3CV2Phq+VpSFsly9AO+G9daOHpyVsl4dh2LKkdg60aNkprPuWRBzqrO+aD/AdNGTCyrTqS1Yk
DoS2665hNAUhKanraFvoD7ZvQ9ErWOfIV1QLZiRbED9RfPDzxdpHSl2qQwepCbhFkQTHz3JIUtV6
1vMvpFUM8DVy/hjukrm0/06fIHY/wpQ1fgBQLOYRXiQMU03X28bD54xfIWu3zTTd19SXNUyqTpdU
ML8NZgub/QUoqkM0ot1j/NsRUvoWx93cpzZI4Hw+fsladP4So517f5utHahNT9yLbN7S29WPsKpi
LIfEr3WmrKB6Bat4913C/OKtAvcX0MIRCuGXvpywCRP45Qzqs9df1y9EEQzpz6tIRJz53eVSzfo3
kA9aXF2yeV92A1DBSCz+welPk+UOLm2Vnohabs0qN/2KJeUfjLIXPSlMx7/JXHFf9IrSzpBWs3o5
GUMncm8m4qlRRORdHrpDXCn1Imfp+oedjeYoSrR8ryHOb1HF2IctzvLMMvHqDX1fieY/BEKgGtT/
SCc9zKMGCbJwgrpAluFhIQoohwsBKvW4LxFUodWx6sCjYkp8rXqi+HouIOObtZoyJrdwxPVYq/Gu
Psk1ThAI1ditjkk5QpKkSZlT4rYM+wULVeUBrvzQE3WeNbjdvXbgSLsdpDbdSpdHXvk+BMqztCCz
SkC9XYIBXlYA7vuYMNePY7FVlrf2WOpR2AnJ6rm9h9qKTkluUZrgqdClw8pxeMZJUR1EUN0BV5m+
7/IDMH+YiPgfB8VtTm3rm4mlHotMQpj0u/gkg71V1/3LMJpsfvOKxcHche33K+PDd6acEgjZ+07M
Y7xJTaLWL+W7h4FXifNeg4VveePmUqHsODbS8C4HC0hmr8nPz+t6g99j10JKL3EhQ43KUMbzv6LX
djqGvPdPygmRHAAoKJ7cyBDDIO7UTbwdg7Qk6EIqNlwBtoIgCw90FtgtTcAnzfeHSo0Y5lXXATDA
/+czEiVz4DTXJkodQaQ/szjZwDvFga6hk3403q5cGfFvVCVGdTIx9Tw2x7epXfAn44iHluWK2Ynt
zj+W56IyIWXKoBsFAl+FDtwl4IIVnuxjWC0Mz4lK5ZiV4wYhLLfAU2AcP+z2MT60JHjAblld4FI0
aQkrFJguo83KkFADHtuFYwLJNxfX6dCSfCsieWXW5TxbRLmz2GXcpdhKAcGxjP8O/wnnAin5K3j3
VgvOHYX3QUwklQoJGlGbcePLlbJkAbubVB0IzH3jV7NXA/J4GsdIwuwBJYAr9rkywUnJlLPJu3vq
+1Drybt5bzO2s67Dq1pi2XsD8JwNPxSureLnreo7EpOkzTdzbgTtp0YiQp7b64vLvg/gFPRKxPnq
3nsDrJiN9G89KswIS9a7KFOFWe6X6ZhfvLariKSvPdupYPHXwgT/FNwj4vVvEtq0WUjJe6/fVazp
up0AukcPFM1fDs8aGJSbzdttdhnZSJKE9LnUvwLmq9aIYjojm5/3sKs1+F8ExueacxjjGB+42bZw
NEOzgD1HYzJ8nrLRPbOsJo2mfOHQL6nDw3j1emjVM3oVuz4L6HlkQXrUZzhK83/1fm6BsViykGMT
dcRcc4EVffkzGpd5/HczZ4A1DIuwhnv2OXJ/SNWab9z0RCMuDxWeU/fhuiG2zKi9su2ov2HBbI4T
YoMuE79QbHoLlh/gjvW12C9MZgLbtNr/3vQoKvNFuYNmpUr8k5bRS2HPjmG9LMNlgfqYWw/qMnwv
Wf0sFI6pCm80t9D6GJeddTDvC6+fbOWvH9a+ai6Yy4OG/Ymp9ng27XCK2byk8f4LQ51VXQD//xYv
Rt2mhxw1unuoKpkkjj8LM8rPj6tl5TY28589JddhoiujhhSBgrKVMQYn5RC3Kl/rTDYhXtG5Fyqx
3wLcZu2r9JtLpTSJ1wiC9OgcGLlt7/7dhDueiUNk7fwlgYRHrCAP8y4G6011VehoDhwsxVYBmhEC
+S5x3wGU2jcojCg3iYhHud9SOuCMjdFOanrjwNhFta51wAj81mt+8OnlBtBVwYuS9FL7mbU0Ztka
OCPhKyPwTv/wwwSRu+pYSqFzK1T/MIgBuaRZBiWokA5E7AZ4bIx6ijFeawceKweRM/dXYGEGvJid
IQPsMZ3Jmr1/2e6NHCeDV+T6aSTHa9VMZ6x4tq/H+Yx3FTgeNQ/oShmKGwQzXRGNwxJRKmVgVbpt
wxXpoMiT1TBTIG7EFKW3agTVImbOMHBfFCVMfpjNgUm37TApbz4YzpAnAQQxHx6rXdOgBugApfgP
RaJRIyVelQ/0UXHTfcn0GACZGvrX0sfUT1VB7vUHSiUnZy4+vRfis8nwAOsiVIZYyL8c3Fk2VPc3
Yqe4Cm2zd6yvuXiCFQLk4SAawOgFLMeJKnUPTOtAYN0CqrckY4d7Eu7gnx92kOxi3emF9a6JOUNJ
H8Jm5892P9xh9M0DwNoKZSO2ysPAXMm5MW8A1WXx55OBEYYFFhabXDbVT4xvLxDh/NeLFVxmyGPr
fcwUtQOqYkv7DmuKD/o5+2CV2qCHwrdPmQ3I8G2+60AZ6klQEmt6r9QpzQEhIETr3my55jNfAj+5
kt2KtYfdUJGfwx6KMDjMDr7oM0yHw6kDgqeDQLMgXdwEL0btDVv5VDuO4pMZw48BXYGP4vh+ti+G
tg8k//JE9wJiVh2rMkgY5mBka8hk5dNj4dCMtmKqEOcWtVifeKQ9izyQ2jsQoJzfqMQlnRxzGc1H
3Vv0NmQnqj+j6lFOyERK+aUSvh6cQc0WBZwgyCF+kLILzsA0rBz9RhgYTujauJ6cL0REjf0RU8oQ
vlQqywqiJYeIK/aPQZ7vXzG2iWBCc15BniVqGJfimIMePq5KgZiORMyTRqzTr4O+2dk6rLCfYJkF
CQMBvTJZMOJ3nmOmAd0PRxA8NCtg/LJNyfkcQXK73eiNFmisnL/1L1Zx0z850EXaRbbXKbrO5I1z
gGJmCmfdBE8U386b1zxCSp7O6LosKG4BQt/FDaRZXPe9nV+aYrYlMub0SJiHjpt/jklj2G1eWFsv
MDCOyYvhzTQhmHdv05g0KR1JvylkoVTeiQ95E5S3MUIgzr44cYzJ/JiYcQLyVmJgTxvj9RT5Uzgi
Lxzfo0OvbKbjgPvAHF55nxdxWyiKFPjoOMB6pqKKMoH3p5zulkV3Tf2aH0wteS9XBZQYt0lsNE36
SIgK5ylH4q08zJRgRSxbreRAlVhagJR2UFmqIH0GSAacasEV2TzvlhNfhNmMy2hi5GoPPKc3KooG
H8C5WLFNiXQutN100W0B81SCl66nxQ969suyb3WFdtXWSCdnobgxKxrlCqJ1lR2+s1Rvm4iab0z3
/S05SebeaIagvLjoCNttZ2DW2A4EATH7i/IqSnb+g49UzHM0D3FL0LpTbxZzWrmR8TJrQHhrxkXS
YzOIeIY6ye3jpNBSQxuh00F17JzaC7P6Lkf5yR30KRyGWE2dY9KDM/ITlWaH7XA9V1uHrKGOzEmN
Fgbd7wNnBXJwUVv6q+lgR/iX9eMBOrgAcb3LUqB1Myf7Vs9yWVbxWZo3zV++A3UpAGliICRTQaU3
hzygoawON0T3+knrhAVSdfHFYFUQm22ejE6F0ub9u3kwcHjtrnqayhSCJjursnfTfCc5YdtyJKKh
4Sx3vqPhR0/xxYOj83C0fV2aNBUFJUU9/FqpPqZPbus3qc+c14hzI+Xnt4ikCtuSm4FgoyezWa4i
nfK76QPuG1OinNdmiYI3fX5JuB4b6KU5Xqkd7FgupcGHUe981/Uuiv1Z6vDLA/BiX7+91Iv1ILsu
vyLMOvnbJL8U2MXueKilkT4OTPtf7dGd44QGyK50QIh4qZnaqKofcMDv6p8AvyyD/oPs9hPpupUL
Dzvgtyb/vW0CO4RrSwpjqo3N8XAPVxhQpdqCBnOLrJW+L7/Si8vbBWiPMSdOUV1rX5mkgKdRmW0X
bTFWfYhDBPQ58Zty/FGOQYhmLZJWIy2SHVKCAhHcHrL/8ZC+9k8CvfJ8VAao1lVp/BVxwBEfxWrX
3r2AHlPjTl0atSTMM6GvUcIkOaiKl2dCDZLe4x88khRDIfiG6yjiboH9+ZFB7ceLBdx+s2c9ZaxH
pCxcvu5xzcLh6SH87WVNRLeA5YBvRIt56VKaxneYUeZK/Ku+/nDqsrb7uxYXatt/YwnJZgOzit7c
cwtRK7g/FXNXvS2uQTKUsltq6GDIDi20jSCRQKOCCbYtMzGeWMRKSUN6uvyrXMQ4ZRFHSANPBms3
qz9Ay/eCFeYCfmcolhzkFisYH5d9t8uoObpmsbmCo8WDqdGKVkSz5dlvUpZLdP9srhwNCzgWyxAK
I1czYcznNST/hh9MgAkM+an7PzBScvPsV3DWpgP7Zrd3PA+WSHh00Z2uTG/ApooJsCRoRghxJnOF
IV6F07hdH6DuFMsCOChiYjFmzl39RXCTfDOoQ7w5sQ6ltmBYZVtDZ7Cn1PAAf8Y8mDOGPC2LgC5F
7M27ecM7kujRShICYgscPpfdf875CFDWAhvNyX+JvNqkNmB3JQegeV4RtBH3mccrnE+xz0Ca7hXA
SbavSsNkYwKXHjVGFJgdnriodXYmCohBe5WUuEwYeBPbvIP0sLzxfikFRAATdUQ9pv6ZZNHSk8ww
icpPXlLDrUKMGkevjYP6+NsLk78KnfIXGtzrYYCbyEj5WZhP68jwCSggQI+MGHOyxz+YSy/+DUjf
oy7l/TNhpYUsIbWdpNBUj3c5mDGA82gIE6EHG6fIw0QjQCMpr6GbJkw+rHpWmVhpXx5W9qIahPxw
kw8MdBhZ721aBF0cTagId06NIkOeh5T+HQY10wIV6yd0SvJSLnvhO5sANY3fJApmf9uP20C9PnF6
x5NrPSi2/Ou8oQ3L6s4k2nngS8pslz7L3LIw0bvPVD5+83K0Icn3aQLvAcqcCT+0RWBnF3Gz706U
KZC+fzKsbqCENfaxzr9LpM64X6apHmzDkzXjo187Hp6EEgVLidwp8BIARLB59E1Z4n4Xly5OnjL9
IHO+AmReV7hJAl8JwFyokq1quQS81N1J4BqXPigE18RjXUdvVwyLr7AUinvntrT89Nkdp3eH0yLn
dgyJ0ncabZediH5QbxSEkNkae90k2pbEK85vYX48/jX7WWDp5+/dznbXNSwFNqDZU/dIQfzaiNYc
v65r+EQmJ5guiHWDKcXu+b9swGHey+D/CJ9Y/IAbQwooJwPmlBhPN5kSu8gz6hDAPlwE/ZDASuE9
0Fv+MVehhcUZwP8/svofseLFMYS3ZlSDZ/JeCmV/hXNLxEUygrT5DsWc+DDlMZtNlsOX3AoRPUpG
IzkYOFq9xcPu0pxXoEshceWpaalaGro3AzIeMkutYCGqMD5K5TZ43GI8a47fa2znHlpYx9e5VrmW
4jvdf/hTIrKPbEYkp5nyWdV8+owtDMD7XLs5dtfM616zDf0xjxOivTo5HAyqu8QL8ggbPy/HeWvn
4MrLmtvGD3SFc4Lt/K/NT5MP/ePB+i1qa3oJptou+rAL3udWnKBoUMMo9Oti5x/TuvzzbhbSYGxQ
4MZKsboed0WgiEAouHgAPadPqA6QEq840fABLI4ZcA5fA82iDwevUZmoC6XX9WLm1zt7jN70GTtS
z2XXtqmJ1xapM6sb3/h8cRiDRM6Hy1mAvzZFA0IFLjYLnz+EZuw6fNX2o+ohYGHGQCGbuhVZsLab
mxcDw4v+EbqmJXysgBHqI++fwrMqN767aLgx/QJuZHk9mGDFLzBoPWm6wam/D+e4thyXMWSikknz
x7sNvkU4+7Fh8auVuLd8q5II2jaCcbSxM0nZw9lJp59qZv67LJyUT6jvGHw+brDXNz/BX9RCmA/q
dyU5/wUbEfz2TKA7BuM+nayyxcLiCWvYe9D+fdCo9e1KqRR36MyuxBWHzIlk9jhPMPnd0iYkQfgG
bD0KI52FU0P9HSjUYZUNl2rxY87O6dnIxlCqVyX8iX2Z7D0G+TpFx/rWZU0xYjf40ZjS79a1H1fj
/7D6dRb5qO47hZaB6Cn1pP837BaoKDY2x5F9D1QQFSysphoSCZVCBZBS6JtSo+QdYKXEizzVL2uC
wR1SFEF/OMnqhJBylWaIp57024OXmNDhMGOIzgpD20ojBxnFUJHIHUQaR/xImO7m4MH+gX8lV07w
T56Woho55aNblo2PUO+YgcZHXa3qIf+CfD+h0DXG22nPtTVMZjpzkimpvWaYl7T06YsfYdxTqPl9
8aqrtgqjZfoILwQL4xNjR1QjZYr+KM0YuxGGljSraFfjPV9ATRUvA3JGGYy3g6DOewFbGkEA8fic
8In8MKG8HF6vXGttPP1tr/0iJgsLNfUXDygLqPG4LI43hBfYSRg1HcvTh6Ja6WHBYYxhhlMo2bjx
3BEdJbQpDbBH90pkg8LbuHJGQGXhyHiEVNuUOQgZKPBxATfPWNJm0kXMHtaNKwojC40+okB5DmSd
YvFb+pxNMZXsSXnvoHYQcjFVoiXhSj2Bf2tZDWiqpP3PvDqgh5z20ptbwV9kg5sqoO63wja1LauZ
OHBUvRcVtCgxrG2I1t6zyaWyKprzPwed9nhM7iL8xGmLwzmWm7aRJ8h0BUpwI7dxnwCx6nYXHT7l
IGJFxtqWpBCCKGMbOa7/79d2xsRkao9Wer5Rb8TtUuPOJE6EaOqwPKKAC6yfEiHqwJQ355eID980
f3n/pkqJySV4nljXScbDPEFjWX4FGujOr4sWV502hiFIGgvIEd2v/bzBJkOp2lmtdGzzzNMt3vwX
EIX/yWty1SR7dj5+A9sEZrd8k0RNBNERhLeqoLYQmy2l3dHgxCWXUXI0wuHVaGAZw91s3Dv5a15i
FCnGQVDA/ugET3G7u/JqAdbdPuNTVpP/3nlBzaXbqAfPqNKmL/I5x+S5gA5o3o+Aa8GScMgf+rfz
Hirb32nydou75RCWjJXo6jiyYL9muqvwYGAAzxbF9yIC++jb2QvVJsnG52K1Wi8Y0x+vGc+fmafB
KumJLW2JPeJtUk/g4yo1RGeXYZorpcHdgOSk6ho6KuA4EbTB85UWYLmdoKYIeUCSR8tucde5EHnn
yfEZOtPe9jl5KQzfhn7mK4bybTYUeIAvJ3MwY9AwXoJ91z1Go+TJnqAh47bHRBhspTi33ylzs6wW
wMWBMtxHM6KYhtg9dZR6CL0FlNz6WSpQ+lh2dMeUQuK65jRgvipj/iUHZlbfSgXLlq6Ca/GY+3B2
0TypKWqysbtsmav0FgkjamqjwGlQNQdYhNTu9pG97NI57bqpkFw4y+Dg40TRwf5I10JCnmkRryg1
o15QyiGCkEtpkB6wBBr7ZatW2HNyITi2PYE8Ufxc4/p1LqLyBvV85ihFPNPfGxsEnj2Ll/VKe5/S
saLQHngBBvRLCYV3p8zx9Agu171FQT3tJgM3RyK7HmIdLIb4qc7tH/dgkJRibdL3VvzkicOdGuGX
CMfwUeatkxIjY4qMIaOGyLUQ8gxE2UA9l1Sk11dFbBu7lU9XHFEJqvvh2Bo5ja1KEPWO+om59gtz
OjxuXoVswGYo/fFKJNYLN/tipo8QyoiSYu5VTAsRqPo38QNTb/hNj73RjUxBZDtJ66bqqiA/0Jd5
siFauv2UoXJd8NlFVbCeJnD0GYYZfFU4xMwfPQtCmVfK3GEWxT72LjtJaUY++bAZfklIjt1cY0hv
BqYZXThgCz2W1+PeANca2piFLp+0cL67n4gpSBgv0MOMEUsZnTyAXe4XWLka6KYbTh2UiXUmf43X
WVc2zrFlWpqzZURD1Zy3cx8NCrjcPKe/dS68/u8w7WGvm58SJjjn/JNrj0klnfNeUPuD7u09l0gK
8+CNLX10jxENNq5UJgiHZznN3dfRDOIXMgnsL2gIMm16kRi+kiLqvReRx8H5MAZ33/mZCnA3T5Cn
cbkOWVw4KOZOS1MGuUARjKOaXgr0Qfy0uu9+dcSrcjieH52+53fyVZkygaJf3FIdfwBU4CyuvGG2
y0ftp5sys6nggtlbw5mhBFR6PhSWx9GJdvgOZetvmmdRjWwy7/blIB4ua43C70/YIoHi3haV7ZJn
ubAjA4tTssWHzpgqDDqoOi0bAshBi7qEBzcZP6RnfDvjk4z1GFyq7lps2CbbkCrfF0cN6POovjh9
yB3ylVWCbhxOS8HTmn2tpHEY9I5dTGnTOVp0GpDd1VgD4xE0l9QdjuxbP+V/C/0LLajpISRR/1kM
RyRLe2oO0raqFOC0b7vV/lP27iR+JJ3JX7ei66dnreyuvAeUeadYuxmsok1WT28t6inOOo8v+usJ
E42vW5uI0FOthoQik73JuKFpb+I7cISgnN7oY7eEhqI6ASqhVhiSnEfahYeOYwWrJEOUje64XOTR
fjuLKuzVW8iUC9wjZq3DwyoQU+r+LJvqw+RrerElFunwCEYvMaAJlSi5jaJVobZVwHA3Q105Cd0x
mcjnrF9k/ISmz2jGCgVZ7iQxCmGsHm7jdtDdTGuZFeop6fnkGIdIMCVJ5e3dFf9yXATezX8841GB
64aJ468jto0qyE6Z4CzDXN8/lj05VeiTf1ZchrKyzHRdg70nB4M6Cml+OItVtlBXicNFjQ6f0pV4
rgHHZBj/4Vdnd+cDinv3XnYzgL80hkwpjU304NSsF/BzKDGu0JlJU3YaiXPwwa7v5Ctt7CT8aiDD
W122MQCKj+neC4eyoKu3LJ7Yh4uZtlLtsRL3wli7DoKy4gu7MN+O0wT4WNWrV9bUdFsfjfwhP1UF
jDwEHbtUww3OyTt7fTUn7MuVGejXbKcN7qFUALbqv+/IYwlnLRCYJQaE2URdhlf/PrPJHO7lpiP6
/KJL974EZCegr5JebPlrOdsfJXmY9d/oCAeo55A/uYQOh4EMoueXhaD/JGInN8BNl3Yuz6oBu4wj
KKG79a3tTY3l0lxcDwCH99oyQ7fREyKkH/kpWyitoN6mhByNaGN0l3gXAkwq0aFE/eAFnEryCpMg
Tx0TLLPdotZ+MaGJu8MfNX0ZnogcwHjscqavzKd7ekfGuW8199CyoQcu04xF0ITAKfiO6kWP/+cc
LgOuMAJqZ7i3yh7yYRdGwzvDfX08SkCL3ucquYZOXA/5I+dMz4gbHNhMW+doqFhGOY924qYFIDXD
bSyD5LjQqghc8q1/S7SK/zbAqxbrh4/+7hve0tL1Hj+JBDsakD6+s5Hp1zzYS4EX5hW0psPFm0fa
r2G53AoAYKTffRGMYIyAZVXVZpZe5uhkMQeusPeaeGJleyhmsEVI2C5DzDNHatZz44wFWofnVau6
bbVfyJzJNh7fxRWsA8kXekPC/xJ6QqaVv/XrAYuEuu5z4qv0kdiB3kWQjBa8/0QRoWDGUshFuoQM
PEWJJLTnW/WWQ7Znk7zsdppxymtF4Ip7mJKtpt6xJFTd3WMTSAnRWVevnHiF2Dr4wAdq3QvaynSP
VL6PewAuR3qzmYUWYU+0vFjAM8kBFsqst84y/pS9tzxc7ELvzWlCyqhJqgd1Z8QsrtrBWIrCdOmB
aBlnUSpNTRrqsd0CL9jw7qBSd3D+esu9PImdqgHCsziti9RUkD/J9zN0e/s60g9srLjV/e8i96SW
qL/vP/kyBB/9RPbkrB7K344u8697ynPPfx+IOQj5/td6yj3IZYe6JrpYMtSldaGHwZNMEVEtEYPB
HkObIohc49Y4seIXXFhkvjM3FHmq26+Z/DpcOiwI2nKh4R900XkRZOgFmQYOX/23woRGwfQkMor8
v65R40hSgG4rodBhc1WzS3TPSFKIM5F70XbGHdJNgxXUE5g/1oIWdPqz5OIY+FwhYWSzpQUkuFjr
Lago9bF6/PdPGK2cAZUV3z8HOXzl9kiNIWMxZjObbEGA9yG+Mib/DzQaC/gPE9qbrUkJPHQxd452
BWLEuIt8L6j9dhw0zABnI3SaqOIc2gLjgPVTkuEscheMGiRSfLBlwdlbwab9TTXYPX3gup7MZJk3
G7iz3I1/EcNOoZfjeiQBuBchKL1nOSM2OygKwEshny/Lw2tbVmtQCb6FKCjV6AovjZrtHMwSkMVL
JZXvh/+OG3IN4caNh0IiP9ImXvpu0N72YismJeYhXyZEGTKIUENM3mSYetuT9z2nZ0kkwbrU7bPk
ARTuZcRasbbQfpIJYAFfwuqltU5ReHpuENn760/gvxs4ZdVZ7tUmblJbuDR5VrLaGwbe4zoNzK5P
ftFYMpa0ucg6XrumDJ1ugHsOy5R/jnJ5NCWnhrDqkKs6OqwYgv3TgfDi4K2iwAHrDXv1BWW3U1la
kQUEXNE9px/VFHp9IArw9sivD9AwyJb9Jrjm4MUP0Ugv54mThCr+c3s0TLAlOmK7aJSRu7qfUlN2
zyyLu1WuyLX5y9N2PmA/iBdftaCAtogfJR4hoTRyUdsEovpQAK4LCfvDu0KICgCGfWt1o7mriX40
uqb8BixwZ9bpLiKVUHpGMkVVPLRzQ7rew/3KlaDonLZln6vJCtRL6maYyj0SDuIYk0pgnBw74OAj
Ifxc49YmAJO41HVF5lJoass7JeeWUcz1+szW/6rG2TRAO/4mmgiD9bMLLx7ugE8Kgkur20AHcYn8
RvJudUJS5CJftoH6suyd1gg31a8jEN/YGm4zzggxoMRawwqnjDszNMy3YCH+sLYsrNxcb/IUk97G
tHF3Tk5ChCDd4jqreA4Jf9fPhpHJ7gj4bM8tvMzMcFsXdcLU16c2h97fu8Aj/4ODvWfnpnBdhcv5
X9NZYmZGTWhIs0sgCnU7kwddu0tXq+v7gBAA8EAMw2HJvyLBLsjBdiA1NLOY+OoHuVZ81PjTxypp
j/1Prnz8dwBNkqvKhzligNSFEvN9FH1Xz+PxVfS6omuD0scNkchVcJnP9Yqn+ZdDoQ6GZze0BW6x
qrwHGeQQ2tSrX2ARMNV+qJUOUhEdH2GOwBjOAwADBYaxfrSnSpajGmDoNj5+LavqN1EQ7PQLlXxO
i7i7uTC3DPC2607/nHRTcda6HvC8hiPpLgDcThQqsuVsbfk7E/woj7I0Q+7R1M1sEJDE/L2adMgC
vKA5tgCuITHxDlKy9pdU2ZWds7hIc6LP6OVZwCFWyMRyvyesWaj0cY/OpImBpJCoiPoaKDRgrDwF
IMJV/yM6enkopaNrCgUcaJ96Y2q6kevvQwSoCkbhslL1nTrFEksywSu3JGiFABpKg8emZ7Hvp2b/
coA86ADgFpjJhCfbe92FUwbqoEj1x23NboZFEnzL4UpThq9OnT5Re9eRhWR2/J8vqVAsTL1iqnHT
wujgIDIlU4A2TgjJRukWrZwRVmkMrj/VflZAtCXUpdN+jDsiSqDCXwgnlMHAjMjPuBE5vtBZMoVy
nQTJ5Dlc/90NOWQXLdhwKRPVRAlX3Fgkhob+yKLZdL91qnqwOI13WpzTDA1aft+1UGqEaUtOisYq
z1H+wrhvwjzxtgLz8I9G43b1eJmrWcrU7Iap2SUNeOZsaygB+PhbYqXFkkjIrb/J73ihCuW6y5ks
61vZ8MR5ZgFh4447EbC7bIlBCnsaGs2njtZNizfeODRbdgoWYqz7cnRGsemQXkhcwN/J1ypyTNBg
+Z9uAkWpmqFXb8QRP2+UPlsIgbHiEFqZDM91cDyaSeiBycWTAuuKW8TIieOyr0wMpuO6bP3oB0uN
4xoFcDg1IfOfZbQ6arvNkVBlxqlcJHMDXlwRlsZ+b9YxVh8EsA4Htrwwtv+4FS6pPlZvb248mvAc
TYlZUfpY2x980NBlDv5MI5Wa1PFFnxFARn1V/CvkTHnGlitKp2HIg9WUhU8uKlLiXiooYfFnpCW4
nCCJNBk41gSVTiu+aTD1QfN8fYBo3R1JY/IxwtuLlivRF2qpZpGMD6A2ypBrQ3QU1H4pZiscWjo4
eFIqkHVLJwKrP1nVZQV7KOuzwYzCDk/nv6z95OpmsrAubi5ZhcCBVGgWIpYYn7PO5hjq1wMBHJ6O
ATPmmmzqP9S6S2emuo7CpxlnnsQCYHQTsZQP5HDdXjJApWRRdvwGlS3ZQyFT3arayySR6i1rV5fi
P/1ttDiIaDQ5sQp2/TE8IoWjVW2E8VxsMJJIsBk4pPOlJzwtGRVPRTer1irymKDewO7JIzOvQXHt
K2lVH45LBVBgmm6goerBwAp76X6SWLSoR8F48ed9ejGZZY0anDKukIRPS8aWvxsO5pr9soezaO6l
cQ/aKzYRd1mRZWVp1m1huewY2M/Bth/QIiGGb/Fw4YBngVwb3me/0pTLWBD4Tqh36k92TVTSZ/6W
yFotcnSuwac2PLAJFu5tGa7wUxdxPlgnWvE8LjMM1mpg5IhGeLOGg14FswxjP8UuLEQcO+ZPdlAJ
a9YfCm2sW8OhwSBS3FSKXjCso9+YRCVmNPNACCtL3HWRRKQPR8J9MwqhzJ7vi5iyvk3CaGe5yKZ5
v8oKNZJTXaY/ZsFSBUj28HKr52jPziVqOSk8OK5Z5L8uaYfbgJjf9iRhrE4i6XOCGO9e5AjHRmbe
GV8CwBRj1qiWMz0W9NjQZ5mZ46TRWvcr6WXPiCgFpYfv1Cj+SCXFgxldBEZOyRoBO6mqvJEBvig0
N+jHxbSEoVgxF3qvqxKgpd0H9hNZO5i+h3xsRkZnNLy+DTuoojcv55TiTZW7YwByC+8mj14dfQZn
Q4kjEXiX1JBQonoP3vPQ1WxYon6rdBJayjJJh8lKUIaBSBLmSnO0Ar+xB8NDvWzdrwHnarA450Iy
Bkp5hE7KN/fCgDG/rRL+S1NX36ldqdFONKDnAVvbezFvetZC3ras79Aha9GxurdypMeLZhrBwUIL
qm0ZWPg1Q4c0dFOtHTJgC2hEBImQXfZnMduk5zACNdVDESZ8cNvn9QHV+LQSxT/W41ixVxxn7Uwd
Ej0zQO7Iq5AduvjHY4qJVa907tkVTertP71TqJMIDiJneNPqF7qFgekb4edDNPr4Zg0j3YedrKfe
h39TYu1L3awrhb08nVPBKv+sn0EUbG6KviOJEJAnI0V/qCLRffL3INk6nv5YQxXaSe6QQa8zKATc
66w12SLnFKkYP4rfD/BSLleixgrWPFvhmobRPrs1q3ggOjvGZ15gJ7b+4LI79kXwGYdbw6Qyl7vX
YtQwVXRC1RMlvgO1nQvnwbmWVz4DChKuKkACB+hxhlWDd3B0PeEngDxculCcU7gAIJyFw5e2zWHE
a0icU45+Q0MUDcs6gXkAdr5ieiCnkvSNfZxFV1N/CF2gLoDN3eM44XZqNnA0ZNaqY9w19wB+A0Tp
2RhtvoR3wpupgxPo/T36u7Ol5Tc+JChO5GllNqkMLttFySuYjp6ge4cFh618tb9t4jIHmfHOXQKH
ej7Lx0NoAdFZUdZvDjYHm6VnKz7rpY6GPprMnHEeVsNxE7aFyGErnVfulcCNJ7ggI3Ubs+n3j1Pg
SY/9aSi73aJ4kIiyO5DjzJ4rSAHNNmA+mtusv/kS09jR1iCydbdq+diexK0MS4LBOYahR0voesp5
En8x5RUhlP0JjD4Itgigvu++WWEhOqPvgXtLSl/cd6B/6GNaTZK1mufNSFTHwL87Zm00HD9P/xqO
7a2YAva8zOPehI9mTcobbluFxUezeCjrIwXSYBmePLhwDfa0HBDBV9VivwiXwj4AjUC+D5q2i0j6
IGKAJFQAdtYtDfdsfP6lGsqbV69/hGCJt8SUfOMrkfCPmT2YTYL0tCnYRSyPHMsd0hh1ctQ0KsJc
DfBRqTAbNYECl3GU0yj6plUTYuvUV6/mxTuZyA+jcRktuY8GuKKCBzA07JEIjcw+7deuYtNt9+hJ
w+eXfhLbrtXooQ65PdJfWPE7yKeCEq3tky/Ovyw6+qUH8xlOEH9hYS7AgwJhskKMdRfoB5tpJ6rG
6wP3NSZV3TD3RNqn7RM4zxVQ7u5lrgT4ZsyjdU9tSTgzfo2+os9wahL4FTPqR4orPULGM/3tk6Ti
iR4n9E3q17WGW8qOy/7QwnbqkmGBgDfA85peesK/BvyiMBZvOw0G66Pm5NRC6Vyw9S4fVguiVx5h
tzYqtN4Oy9wDeSz+FVHjkMERtqk5vhyhxEB1J5pWOD8mXefVSnsJPY6uddlDRjSoJ6gU270dwyC4
mnwDsf7uVgTnVFbT1UvmyKlfSr/v2Tb5gQPkj9IXJdMcohlmq/+HZjucCzlrIa/k1KRgtvyiQbGu
n+AvM0w91fUhMGfrjZwYdCJFZmr6XbpnY1Qk9nxzO6p1qN7PeqJwbKRleMVsRuv2HZyntY8vkm7T
qXUrnDicyv820iqcDED9KSwBNyA70tsSYSJEOU7IAA1z52Xw85cHqQsXlSjamxcn89+W3Y4rHUtp
MomAZgQrjg49z7qsI4BmEaYSxLSzaSL+nvqmAjQ33NQBejq2/sQJ5fHuwg+5TLf0O4S0RrMUUJq6
LpN1MNHk3zOHdnEz48Oel8gMDPT4suTYwOr7aRVMlFVytp78wsDwhPPxnHc3Ik3+qgPItgCfwWER
8gFeJDxB8rraNgnqNQQ+T+Ae9HvK8IUd6CZ0wwfn3W8jyKnrceS7f2F2udIASB8txZdMFjkflYbb
wN838uwVB4eBP5RN4VopPUYHI63cPTTauzDRVFFrNm2UKpGMVqNtXCg90ycyzOsYnz8s/Qo1Xbr4
/p1PzPjw48oqk7sCBYg0EoS4uZRLECHKkQcHRh9amCqWx06aVMYL+B7X+qRoXChk+RaOafqZqitv
UZ0lUfRd3eL9HP/lfjFN0XN5uvzhLEXYX7zBRyIMRqvKezD1UWmeYcAPmh7Ozal07L7LGFuRb505
JjRn8eph60o0WSoVDCoFUSXDwlRiK3zaUhKXUqTJksmS61UT6J/ldsza5PsZ8cL64jmdJxxSLYWR
1POmlH3GBqdnbN5wtX+Zn6/bwRWWhvOJCwjxaJ4nCbjib35nEhhbpAr3gyKEKFGDVw5hBx2xF4bm
wAr1AhqVGG/0Hdw4t+69MvzaBH6In9EWf67zmj9QoHywbt3iHUQMTiKKAw6/Aw2VXMB5eiB1SdIl
p1xemp1V4okZJ3jkX/9Pt0Iv7jnejafcghkUvRsYYmj47+uVyAWaYmql4VWpnZwK/PFvyaQbpOjS
pMl4tgpsaj4QZuWfLPPzORzLKIJKQEaf3J431xPVDYr1Ts5UmsNhm8HXjfUGiLLBQM60eQ17xBOw
hffny++ZvIUOZ1Q1GBFtGj70ASyTria/s/NPZuC9twu3CerLjNvO6fGtvH4lnIs6haplfOR9FPGU
wL0l9BLVGgDK8do+M/Kn0d5grEu/wK7KJliGWJHTq0R56EjPCa9p8ssaB4TXY1qoX7GdMEct6Cl1
IEL1mroxG3dkNJSwUfbVYD1buvCBrMCVtQH+wjjkAkQUOJHlZVy5HIkVhuEYN2zVkrZWprpUNy3d
/6LpwxWj2xIJUCPbSxQKC/9DAaQS16nN6AgtZG/rayBhIxbtFDZoUW3ot8EVnF0/TLVHIHcRcV95
59VRrHuYeusQrBjEk+lk1kT/7rPx5mjD5nsd00ilSJmYS/J0Tcm3cEVEQ20gRJ2d9EbDmv8q9T1a
gM+RN7cenTHYQYJY962qm2ON07Xo68S+h6pEeugZi4yKTRQvuxJw4HNC26rZpdWkP3N6QsP63Qp6
6qS4/+QefIr1AKUqbQD0e5tLnrdW2z6/Y++/K9RY7FWjYWMCKEKln81ZvFc0k76p6dKaE9CEPqIs
XDv+L59vmA6s+BK9YdB/n8PNDp700WeqigPVOGa+cPHB/Zu5c1a/CuqJ8uqmfXcniR8Ahr176K73
tzaTRmsb1sB2J2PDL8HPDfEOd17qZubZsGIQUX0mil33tAwzya3ycQgIYT+icxnTT9of3MVaiuvj
fJ6eKaAYVE36rFn/N4mpeFiT2xvPCSj5UjAptBe8mI/3sATBH0WB+wUN/EkAbpsHpqKRJ3KSDkys
T72dS9Y7fKI2EJQ3Y9rdsSqPXeSTWUq4YuF1MLqa1GYIaOvN7MSaa5+QBdJO4brP5FP6d+k3KIR+
lOJv1ntHcU+bt3D3TR5JFrl4GR3nlN5cI/AD4ghNt96OUwdgHbMHy7FOLQpYH+qRgqvfgRpuTY7O
59adpojrEvf6eVob746QBZjl9UBmFqYy4uGPKZ51WD4t9aqTGYIYwBPmLb3QBeE/BijXJBk3RHiB
EIk41PDaVM6TnnIqiLTv4cANRWRr/9Bmeon+QkAnMx3YT/CultsySAvrLZu+CaRABot6qIA8f6PB
YGfa4itII4JZdbc3A3zC8Uhy7Owq2uecIvX7EbtXLamWwwyJt7/bcfEGi2a96JC5C9U2jp4JYC6r
n1LNUBFXaSTgUUyqLUyeYKA5O/UCjy7yosNVMEbEdXGRbn5H+F5O5njMTc81jRJKrLiepazEe7YP
axJ5ay60DiUvA9BN637kw7uavuXs/Z+maqCmX31RS0nKYY4I6nlWtDdIpPszL/YKjmprMw1EsLye
pcAL18/dLmN8l4uW1a6ovsFDNFzHJECqWr8Cdb3jn3w7kVqfBNgpxLOLwWhxepygO2K9AHRfk7ci
Kp5BfGkppdaU1tEfOwUd+dLYcN0xY5OXbqFhFQf4ALOA7zSiE4vd9jvZAb7EVxRnwR1yArnA1MZo
DXx0HTI2keAv64nhIzmJZmPQEWuPAbmePKfdBeRrnzTisOvGiUNkl0dYNfUouVKOqgY95JcWgZXm
MTudaqG5sqJqLnO22+LWLrUncxAOddbP8llI96QlOwvhLeNotGChfVG4DXACNjHTL86l2xyj9O6L
w8+05tfDiNSjbJH2FAQwblCfnJJcrYSlLpgFyLzAG8auGOHx8YjLWQpUAjDN0YSeZXI9LoUrrc4L
sfP1By5N4aN7vV1Jz5xx0Kv0mh2TG5jGf1XXv9siOv5zBqn8z32Ejx4MiNehqiwvEWWvkL4C4n9Z
K2oKBHQ4R/ScDJqOVUTzBSPkqG2HXLq7Qdw4+UAFRCXbnZc2QuXjcusicvLzGXxHJ2hdNpw+H/0N
8YXz3FfbCeKqecbEjgnKtGUssqixcSAqCPfFGtqPaVt4ZKhqCqNgNVBUL5QDJ1sXeU2wOdioyDWM
OWq4dmgEItkDVrRd2N4ZdTHauvknNqzhR82GEamk1jToxwiW0guKlaD2Z2Cwffg2uGJ6npchWDf+
TbDxJmbGT1D8zur6+rz3K2nfqfqzxJAQC5hY4jDwjeED13aDkJBleheYy/jiuP4Uq7ZCTh/Ic9MU
ay8yQ0BR4aNr6NUafFk4dTxa4oQCh7ARnvhfr4mR9xiV9akch7UDztbY7faPvhK2SjnWTwXtRHDO
DZWQaBwSQc6RKpAmEEtbB/wAIlz/ZgPmysoo2JAQ360TDKJBJKoTMojTgqw5Ux2VGE/iUWg2MZYr
zCQQYSogfdGZLvySPoSo6idlClnqF7u09gp425ceI2nOWvR5j1fmi3nv/+rU1GIMo9r0VxhS8D7r
Zp0j3E0TeGc8qy8L3FyjXtBMjHeEfN7s+yA8vd5yv1F1BcbyxIbBtQLqzt/4o4ouXKG9F8r7vn50
F54PTfEzJ1ZzLRrkaj5+HD2fmZykup7fRUBqdRpsAVikMLe3hKeHNgSo//a8BQWsCiQJbIcQ5s+u
5aNN2D8r/wBNR45Um2E3wYLWIylHOmi0Q9MIwkRugO9tRBAhpD9Bimh4iPjQa957bOtL/GyuCUgQ
2/COqQcvzy/UzMo42pzOwJ4P9BSX8839t4blOMkE191Umr4Hl19NrFYRIvZhftiQ2NSOY4t5GxDP
e8iLsMg7d7zCZLGDMOO5ziH7OwCag1bUeWViqDeRBKmvzV9AN8FWsZhOdwe2LtylhzZXmMmQjmXJ
Ygu6Gz5tICCutk3Y/e139kS5L6t19EFrgjJrQFCcQQW1J4T4oKP5tEqqUeEjfx4Ir0/jY0ATSMz4
0wUZbyvcbazRZX+g0/cYE+0FWg+mYrmeG1Ogf0CJZ2xDdlZEqEhIISf/X1ruWhp/50N3FP+tBgjG
dsBW8ffvUDdZqA7/xg9ktw+MTOalstHvTBJqyhOm4+Wvdw0tYh3m4MD4yiCdVeM9RxTzkJK2KDBT
V1kYFqcx5XPvgOmcQQPrKCdpuPKbGMFZsDv/LNYgA6bZe22/u8idYOiWJGsaoZCkYx2oaIJqCeSd
UB1P3YRSLxsGXFwOWhtSTMvfKKwc03lOIJ/GfDGcGM8VrnuUBL6ezN/TeTq8UAfVDZOZ0c1jlzjS
FtYoiklqMKulDwUDpEfwLWlrraCijGYOG4dEBt+HoKASQi5169Mn0aUoRVlbUie5D5azacKBzVaf
too7vuIA8dNXFvcjO6zU6zuckQv6qqmfbGZ00Zu7ZkMlJBxV6UKEw6ZyRprW045W0tCrM/T0pFQ8
gkVtex0eTPsay+IymtkdF5bR1EYbKJjkqe8B2UkHG7iqKKI+ZOu9NUoOkm2IkT8XnG/QhRgta3ab
DoBbonz7g+F/kZOJRyQ+r6HVyhMNVBX8BvXwcFxDAwAXWA7xayu232wH9jhhjDpEOSAGo90PahFS
RhosVc27p1nkSxTQUewe+AVunPnlOFD3LLkngbIlo4Rrhzdc7svWj6OLcWz5WpUIhMXaxu7qujZW
9yKf621zozCOkqC99bxugnDiZt8wqg5Xw2QzDXeu12uWTywJTSHo0maGvmaEAeuSj0si7GPEONh4
PrL9Spxq/wOvmbUPdJFcS6EEDOdW1zCXem06T+WUlq0MEkJxUGby0tL8W20awfR2ejywbIuyNqHB
EBPn9j1suIW2D22i2Q56U0+UIzaV3K6HCco1LCcTgRmR7lFnETCRTtl1zDGMsBSX50IJxXMKTFeW
Bczh20M64wHhYIWOvNkKb2ey506YpHrnbbFAQSj7OlzCpx7DTyouDCzVVSpuPE5IT/R92dix1YAt
ahFdEfy9CA7GQROUh7I1oxelqZSN/VpaKkvg1sYd6ZliqebsgpjPv8h92bZI6+J6NLTg+ScE72e1
OybUtDlHWTsfXOsOy65maU2/ZN1SHIehWna8bW9pUzYaSA0Ye5//E5k4ZI9qf00JWvzm8HpY8S1m
y9gENHdW3/FBs0e2MxOGqVJIaACTcgHor11GxTbaxuUXpXrmS8iQQRv7xaqO0lCeW20/2hGIBEEo
wijcgVeav51OLWwxiA/8Eja2vbBPyw6vnodEPptbdcXWeQEb1Lj4bZI5QP3RxU5Sc/IxuSo/e3pp
Vsx5uApv/VIbbzLOyiBIuCn4R5aio73Fb07D1PtIY60XeX1L/hGWX0ASngfQrkz6yQntXkQaoIff
qTs8AnsaAZ5XAdvQ3eyVSzE1CCuqaHmGAzswICq9KfnShu2qE+fh5Q7UEG5zmuUDQ+a2kXFYqDMl
WCldZ9NvgBbW2eyNtIlTA7eKJlIbRMF0pMW2ck4bmK1IHNjnGRoMqFVUcI+++5g+3A4FZbbB67wM
vwMsqeOfLoVnLrA0kzIqckCwO7HB+aAVaower74LNdE2UWn1MGWjXtwiotanLcCQmC3BfwCozs+Y
qzCQnc0nl+EHcN9V8IgQ2HYN7sDajbs4nqrPiP+YveaYxLfLwAwkW6a9yvfleGAhzPlfHAoyume3
UmAhtsGoCpHAbYa+HRJhmAmQadYKCNyCW4XP1W3rWvDy6vVtEZgjr2uGGL/Na8xW+9buo+h2vgM+
u+8sdhlutuT5Xa0XkZ6OSSc8fsubYktbuRp5yVxgBGnFy00Crg/wbyuRKeFMAvKG/rM8JqLDHoOB
PGkgcYpDI1U82jMWNYHRuD6+kStzR7E1LAM4lcF6jVKFPpS6hOJL8cMTgXJMq5P9Dq93GhgMrVmx
iXRFsU6JWKt57ipjMY8caRjaCsIkwKP1iuVKrDIPv7gALxK5hNpCDCsOwz60Iel3UNL9JJlJxkNt
V5/yzUJe860mYrFEMswT0sAC59zyBpbV11+xqFKyBWo4idfaM5R2RUJxSmAl/frPzcUEGJtHSbtB
CyGBdqPGabs7a+ADxmfqi7t6HIOhpforPFUXm9cqdx/A7wbcHvD4+Xy1Cjcpr2tVETScXFgBIYOX
TyE10uzztgJ6Ub5MWKfwbhj3ct0L2rhY3Mq+N1fYDO08CsHSb7WbrOY7o4q8HR6WXPc3Ag53vM6G
75lMeh5keR3DCwWQtjVDrUAyxI9qH1N+yNzmz96JhNFcvxKIayVolkSgvgZBGV69p0oYXT5vKkx/
AQqFJf2X02Vu8qmk5pYnMvdJ67blyvQSkxgpHLDuvp6Od6CMCQS34Utre+IJJW40Lb6VGUeBCUaa
Tc/4fXLQ0Xhf6wzMU2Th5S5Fdg0ioszvUqkiGyGAqWP4siLfkBuJveCBqi58KFVo8jy8lKS/e8gQ
fegU4mV9FI68hX8Yk4uCnwLlGes+VvQmBlesMpIReIFu1fTkmo8tgECRr00AQ1FSRaUKXQXQWD/u
LjLabvE4fCo3nQMTHsZ4VXJmX+q3mizmGOpe4SW8xkTw7+IKj+zPkJ+CunHBBhxhM+8OcZy+TJUK
viOqkVGK9VXr/FzNqIKE9cCgJK8xu+KYco3oglpURHdmS48h2Z74YBDMGfka9ZuowwxS0sUp+9b5
OBGJ7rJ1XB9ImgKR3sAgeGcGEAhmGHadMU5wVRZCM+KvPnlzQ7p84b0wLaMnC+nUaD5Yt0XNUVJH
jjRj2ktFgvg7pVSnhuJnCqHeWKSWg3+N44y8ep84Uiqxt34rzB3kzQ7apItcYKOeO+jVD7T1E2aE
Ran+4KNc86ai5TU04CHc9WBz4GxYlsnO6kGlQUI9OXjkrI3fu8iKNSRYVezYuIReDexUynlH8I90
Kpt+6NbDZzxIMwEYJKx6kQEJkRRJdC8IlWMTDRjJb0VyQ0hgZRS17hU1HBwFP8WHZoavYDIMclG3
/wDhbQ78JwzedXkDsLB8kevFuUKE9yrFz5Brg+Xdi3vtvU0ZC8ew/kiRpbzGMcfULHE4XoHk4Szc
/9Z3pbzzabIFi4Ildgv5AVl0kjoys1jzjz1CkLzRadMZtvadynoV2DwM5dbg/PesQWbHTizzwNu8
JwDKUizLb2LT+UhVIu51obTQQGafRIY8EvtpwPCLNqNgViO1WPBSdKY1sCs29go2MGUTLhwUBAVX
rRWJewadIj58otIUy5FM6Eoqa0ZuVvHDajFrWPr2M2FgqFaYvw55KoOFtu9Dbw5ZLhZO54Ncu66D
SkOMCtle7vUXe5p5THI+ri92cP6xyzlRU2LtRPMWwsO7ZuTIf+oCXTSxdAmsXRl7HHqnmwlLjrh7
5ZwOE3tKieaoAQTo0FGldhwuRED73nn4lzRnylBVTTKypWxS1O1b5vXYB5nvxnWoHcfEoSKHcd1E
wlkmLazieueuyI7H9QgfvcrgXFSZRFtwQeFHZW2PAzyiEOaOeD8MjtLD/Y8Prq9ogI9pbWS5wTlT
7yhADexbAiTEkWVBce6I1Makbm+IyrLZDU5LodrcjWVvk6VTSaYGMWTbEs8Bv63ORex0WGrDop2c
JLYSBGD/kBoAecfB5b5/33XVMsBe/hDRoBT9u0uEwNPvmHm+21K502LYCG65DB7Yopy+C/8sqYUT
c1a1O8WXjnpMlS1Y8YmmbJWKHXv08IXOUBLWjdvKexPQl2rAVSwdICO2kJHD5DotOfEibebxE0KK
Z+YlaHsaP5p3vEcOoYAVW7+xwGXgjwPAIXd1206zfU7jHQ1hKIBRRplcJhGqqQ6PupiH59bb40ba
k2N3SBj0G21RqGZZ9IJju3v2s+batp7uDIAUBW+mgQlAgokMAxkfxKc3C5uCW/d0F3RX4wk7oglO
cnY8pbgoxwyCZJT9x0fPwXiDNkjUorZmnLI2OfvhI76Wng2B2IcsBGxdjzKTy2hzF1nztGioAcW1
MUHYwbtBLiUONkFsQ0buG/YZxV2Va7uj5t9DlAuKvWtxTjFtP86u+mDUY7WfiZTSGrl/76FkQNU4
pGSyQwAvCiT+MRo1wb0ZGw24Q5PBKdgmTUUdjJas1UPt04y45KIo1N587TmC3D+G4tWa4/Ih0xNl
B3vlPajfbgtJTIwyjgBvQtlm+S1/KY2TiA9IQWUMvH7MobcIoQ6GrvD8HgTdJg6Tw8+ZQT0njnQj
C6BVNDdSLODhXIvxemg9Kg2x5O/7ksbH4iWFUUyj/ukHm5Ol4JQQYZVKGVTUYQ0Cjv4OMBansWWQ
nakcO3bnAidJKSEN/A6eyNe1wy+ksKFeUorAJVRERN9e5Rl3Hc79x90c1Mij1lbXKeuZkiFKD0bM
QtNkKFvWW4WgHbVYHUYEtywCFRbkiGnlwtIViod2temRnUmE7/dsgnicmWrDOcjgDXQzWIvWWsWM
Yh0tt7OiPqyUFPnNqtCNXO31zXJmuWCoDhXXr88rGjCZDOllyS0SHKhP8tUlOW1u0XvgP/VCY15/
rKDHKuIZTij3GhPUISndjgvva+zIEZaFeAOvbVia4JNVYb56wz876emwQ59zN9Bx4TQxGX+BVbJQ
PymUTD7o1/OXgQ1EGM7TAZ0gZStGQ7xlPwGqlDEm87xJ1/LhvUIwtMP5PSM+afdXlcpzJCP1M6rh
Jim1AWz57SSa8ngrduCEC3Z/zpo+cgzIIGpreNpo5/+oa7K3ZLEuL+T1JJqWaq03ighVwQGovDPf
tuWX0jqFuPwse1a8VyR/HFOLtvxIbnnmAabNpV3kD/kF0t43Ryb8qbbm8jPpzNiddC9fNRWT6Gsn
iEc/aArNdII0qzRQGSYNI394BQ9HpP071hUIa8X8ENtX7Z1k9pr+5WQ6mECjuJ6W8mjeolNBQjki
wGzolLyDUJtkWJgq1L0VnoSKEQI9mND/e01yZYEFkWTMV0STzoeafCtrCLNmO91y6sSQ5noFLNqM
GiINKjdMaKy9fxKi63KPIEA6cVnewMPJwpJ3PsKlXMGFvjSfSotJ37Xy+jFA5xlwuCW5oTjVWQtj
X49WDrTehzFqFNBKiUMkl9iM5DC9RknnQx41iWscT72vMMS/j2rjq9Ys48jPb1dA55O8FTGQFpW5
gYgABXQB2usITM0K7uYfPZ96p4AQJD4XFCAzFohLiruq+5xCia4YOjeOnE5z8/US5rWqvH4W1GFy
gke/SNWwgaws+XyAXwJPUND+9DHRW9Cr0GrUcJj9itY2j8wl9nZGeJ4qLbxpEJH+Nt0FbCg37hcJ
9kq6LQOimdI4Y+DdsAEkJQ4FX0WhdD5p7pHOqvNIAR+CPg+DSNTjLgeRVgNUTtQYlDEX/2ivwJUY
CekPbqq+zkk+5hgJxPjDsZ6mkRUNes9GoXEAwS1kALBiLb0IGO90xF0A3/a/acXJ0V0qwfWJlphm
sOAINvUbt1mg4M+D2XUGU2SwbPHSdhHX/vYmXXAy3Mvepe0FTVbaRJn1Y8JOAcxpZ3Xrci6WaOCp
AGGybpfzD9Ejo2CllIqwOSdtcA7w1/OpOWeeEPUV02r1P5VccCxH9zubNjL4+ZHWEyNOpgDzjFy9
vW7F1NNprDFl6sWWTdWsOmImx39rf5cJ4WJgSJ9iT+/GVQLr112J3mWyTqinp6Ka0u+6zUKCSq2y
eFUmTkhZ2seylJM1HOlWtaxtoCtPjBo8h+ampND17mkpyGJqU0XpLKMWNz1xeV1qm3LNiW1FfLex
oXrksZIvUlLjfo6jEC30144TuiTifKpLuPPVuNiazIXAgwWgfwZLTHEcbF7mYuyr0iC0yzOiKT4Q
DnHCEf9JVM9gT3a8fKXxVjMin3ASxmWQf2TziRvDpjtF4aDmAB1RBEhS6V1fRCxH9ij1vl/aSO/W
MkAQPyyqg1/I11jOb0IvBD57RN+EmMngtU2H9ckAv4hfrglO1aq8N5HhbvOvxC0WJ5U0B1/4EL40
1GQbU/kN/jaz3z4alw9w+10YZknP/Y2bceFJ6mJVsZDlNGWTkjSb1VAVgHzhQVOyoyEszfsAZtvw
LNKJtRbN/ZcIxoQFBnKu9gL0C0s9PMuOBGRr9g10tj4b1y289K5ZQsdqO2i8Q3lFMfui6hTHtBni
YkFL+xAiJFEzUq3IX70j/ivfnPo75tfiNnpaBet9guvyv98ocQ55Nap7mQ2cpWiKELaNrCTUSMam
aICD/VkEb1gQey+zKeH088yKrL57CsHaS45coS7l5Z6JAzAQCzczMbO9ihoT2dDPvg2MNLbOuaZZ
P/jh9TnhZCmVycEtvmEn81Z9aPWSBcBr9sE8h8oUzMFeNOtdTlLyfc0A8xrdfpeIVOX5JbBBba8e
31XwWKVYUK7l3Ewpf87xuhPtTYB82gMxseTZpqFx4+X5gqeMWbKYcSIoz0z60ihOLlqhEca4UeHG
MLv4TwfANdjhOpGvzQPQdJXIG4RQ8rSUmTic0b48KknELmOn7apdt1TzTKdBJOjIOPWNyL7zg3c+
jwzEjwANKW4LPEDIKm6rHjMg+9BQb+/q4+1CJAtfp8d4h9eHN7ccS5Fd7Mk7fwuKTSPeI1WdswWU
xyy/C6uznTpn55/C0UriHBQwu8slGqDsIjOGLEZgI9n5JJvQc6cxrb91viPqP3wuLda7wfAtQFnB
n1d/4eQ1V6vE6Owvo64JKwL8yhTnBadcNf/IbH7tC0+MUP7mnRoCBl9LFzEo7LEB/GVQ/v3Zum2U
thiD23rRdI+XxlqkS/HTdXU1zE/EQIfHkMHbL5jCWfL1W1+PLHbWgvJE7L8qR4L/5RYcCnXqr/zX
5oGOHLnfoqm7qIBG6Nk198X3DJMvDOiz8o0c6y5LxwNYOq9Dda3FlY6lzmZpn618QQa/zJfT+gpG
u6AIgeW/sk7UVkhbJC6PO+rrmhrzPmPP9tGi/NeC7qWJxkjgG2JQ82xo56UGMljf+ld/yB+CVsAs
LMzuqsuvSGlAeXpwxA9lqm9r4i5B1MGKgM1mV575guMfX5lEr2yAuSdq7K/96HYoJy17h24cjwIk
UvN5qjgRLBVh2dDjziM7+yK6VOlgPJfpFEtCYQsGZk2ETXyiy5TPeln7NnFRNp/R3vGzOh1cHqlp
kqUKzmV1pFsmPumLftoR22/cLGBFYHWGuK1blSKY7sJLNhjQb1fzEubjkSgCey2Xh1A7z82SpRs7
Q6kpW9JuCy51lvA91pJVtCSZ7jskUZ9/DMlluEzgYjKqWOT6wbJZKwYnFdkAVWqkSBsF/fh1RZpu
y/krVGu2VdLHhbbPFl8HhVvhhBN5NiOg+gFGQxxEPZRcTt85Ch4COvkRAdsKcLLqpvd86ocjCGdE
kO2cKGUH5pFL+NxT+2Aq0HJkboA57D1T7zFf6wqXWorz+klJAlOuvd8hkesooLxPSHKTQ/NsOzxY
sGaZofzSmoo8ePrnhXkrH7mfTrmQaTW22MUEwhMUIm7CHFNHYMcW3uf04owh7nWXlK+IxvQN96y0
MeCoEkKBZs6/4iVpkiBxTnpD8T3N26LR8tHybHg78Ia3D4eE3wAdh80lFUUEVV9CX97NIQApK/Gd
PgU1TD+kZCi9+Tv29fkIF2MHdAAd8/n+6lMMnJNoLv2t1bjBJoD8yMkguvssW8zjVthPh8hz7qDk
PMbR2l2UCbH+rV/ikk7m8qAWOxIE+ZBf0Ik34WmompKanOo4QNDVBschCIgQja/8oIZ6jTsYF8R5
tLgXozlDg5SNyceFw7uanGcewN/84WS4bXAHz6v7ne+9OFihZsl7wyMwqCDKLXr6Ij8z9kIhMl9L
Ob4Fsfq2Qbnho1tuGo0Zah7nTahhiWZVXQId+2p/85D6A86+UpoJpXnukeSuq9oGAwZ0A59XU5iC
2kPADtBRAZ0vm9k9LU9LKdabSYxpInLlnI9q7daP805LhHgP3RBVM9SSUVcd6Izah2FQn4Wtuowl
KTTg8xD5/z31BBvfqXDLz0sSqG4uvqEsiTZwf07C8QmLS0N18/dy+VXExh11fb4Ogae2KddRJLu2
OJfmWYIu2aDz8HHXdis2eqCGcVZf83P70hTbw++jWR1tx221+wLnhB67u1tIoGruoGJr2Cb1sDX4
xK3Kel7RKIjFKEBUsAfuZ4LRAZewjDFp+ftGMaU0VmwocHxrf+tCKszT95Vqq2yP8I+uegW43lPB
GiZg+0sG9TDJ/Mc67LIHVtOyxsDRJptdrU5Awx2Vu+BMplaM9ai73B0defaZMjBSnMT6RvaIwQp9
5Gs18qlsAcGF5yB0NAKdgc/H0ldlUPnVBMZyS6n/hyG8RKNf++Neg2EgcC6MaoTG01WLLmiQAClV
DSfPlNJFwtP9H1K9ohSPAcpx02zX2dut8GpFK2l3sK+J7r2XEQYdsGBk9CeVFRvHzJakuxMU/q1J
7EaBed9cWnoku3jxCPKghX3evlVHFsCy0dp9ICYEkgBViSFdqHgnd0vxhJAkPNg25NzaD2+WzRO9
3Aa8vaeaiFPZlcjC2Y4L2Obc7es1ibT7QoYo3eOnUlQdR/Am+Uuj6Hb5l3C9G7Ldeu7ozMPirw0B
ULjto5PDoSB2JuN/fWC38a5xkLivPmDPlsxjrf6bhKlbp7loGUbL1yr4R3CNHQulBd8zrSP65UcU
wI/5H/nQM07Q5Y38qLI6yB2WpxRPtcXsfh4GAFCcaPsWI5t9lKM7p47iyHmhkmTxE+Ncpm7bWu45
dIfnI5XrEkDQG2p0Se+hRf/rzD9Zi8/dPtWHSaUN9T9i8p1ZTiZdfS4EjULXGrFbajKByKemhTUc
GhCKh1VxGPhUeBv1iSbhWWbXSe8b0SOmr0qZe1NDIQ3deZM6Cb22Yy4ywVhqAtHU4CyJdV4lHy5Q
4PNZJwwpGfaeZ9SJUTgjzIAtmELBAj7MMavFig49Z5kiDAVGPYh2rSEvtOAUrbnvlI7gTpJ+7cWG
q7Hg66sHwf4XTL7nEIheur1w+CyOIKtTIN35pSkGgR4Xnlvy/LghADFCXfm6vHGQC95CiW7VBZ3q
/sCDkutwtXD5d10OUJLfGJR15t5gCt1D0SySppA0F53ChnYj14maH7uTcvjoBPpXaYn7AJN0ytQQ
fKxH1fJi9Raxb8FgzIsWVD7v1oqwUGLa8uJSFeCPBZ/p6j8nObxyauOY5g31nU+LRzxyYzIIQPbr
WFoFPao7NLNjWdVgg7uWjVVlPUxd0IsY1A0n+b3yjZWTq68qJ8NFNQ7uj1VKozELUK5ltp+cAVXQ
MUuGIZyFopk4b24NnZ9pEUzLW7fP5HULQBLClN5bH2Mmkqv+Kh/krm8optlKy4HpLbFsqTdIROAV
+M5L1LBG1yrzirJkYJFNUOaVZRH2Qt0Fsu09p0DIfR9TtU2XNX9hcNtyWrM7cNAqI83+hJPLW6qE
mHVGJZdnb+QTQClqZEWS71pCVP9wPlA0jSl/4+fGHx/2zAOaH+CebG1RS9tyarNaRCNgXa95P83G
YNghaQbhwNerN69l67x6WUDJMKjVmXZYdM3HZSLqYqo05Y2VDZmn+yB6P+NOkOIc711CgVVOXVZD
hysLHElfqOjIcnykyGBIVWyihd/V1fRlE9zHrHvuQuRGJGnbUa2GThyFvqBVyW+O5+wCgizf1grw
+5zzsk8tLWaCXJGVR92Vl/Q2peEUR9msIO42+krmr/eIzXYhmsZMkbduCDqTKKSxpx7hKzsVYUaD
QYUmPXT4NCbdUhPb2jgtET0BjRetWjU5+GWaKxsVJxyvx2GT92JRm1NCVTYjUF/+92X4Ev67hLvN
9Fr+iVKN4Pe+UZlqcczsnVaTvP1yTT3I/LsjDavwFO3ZKwqv/4ckJqLJDnNldwaqPTzQE5ehcasH
jc8QPp4qQpsXmFOLTaB58D9Kx+02vuRX219s/bCxXSV8UAsyWTtn5JKBShfq9JVV5bhI9qTkii/y
sxcCvGPe6TYD9FlO5YZNQLy02wESNk0zBQGruvEMxfN+n29Q+7KnmOPvXTKV3cH6zdLVtiQh2R01
wyxch27D5iLmdIv7PoQaNJkkvMNI5B2XFBbspFoQBWwPwQiU2OzLJY3AaO7YjETvUIbpGpBPAWjG
ShqhMuSC4/GOEb+TKVlJxjpi9yQGjTo/ghYUHUHd2D352xz3ztMb+OaOqVdpHZyrBIK0Vg2jPFpE
JSCVPeK5YmaqOxAtdWjvlWajZSh7wrOncxKs1rwvDPUBw5qBA66zkEcsQL6ZYlj7hEcoXfFj9WFR
5Dy8cFWk6vzR91VVz9olbIrAQcTwVvIb+/EL4OYcM21+7rexvvHzarmt9FuXXhaztCGk00k5qk8f
qgUl9zVJVFqqtUymwA8M/JtU4CHbFQotVY2NhGkLAXiZ3xtzOO9nmYYYdlFbZtCOs/PzUubwO8Ip
3NTkCugLbGmf40HQ0Z+N6nMhtsGUVMqwcfMX0J87kJWlfPAm2gIyCrQiM8jH+5O9aygkVNXe3qMb
Rhc1ErmEra1C+adR53Ta1iV65xE+I88ZfaGGhX8nSxco+ZWAo6lP+HAvwZBuzTmJMWHw3I3cNT9i
hy+Grh2K7/jfO7TMmb0lCw1ht10BEKy9+kWh3TYi4rIROGrAHsiidiPgGhTg6vZGlCj6cel1WlbD
mD44bX6aZg9wT/IsbmQ42mGf5vQYhausHrL7rQUE5wBweGltFaYlcWER3dNhboVD440Ft3Udpr0u
ZgxHJESmVCCacfJhzvTtr4p4qvds/pkAsGiP9vogt2uh7gKlvzmjZaU9S2qPTWsx6iYw65cypjVX
HS340Mc7PyHBwl+pOk92MIOP4dxusSCskr4Arl8lPqAP9AhJgSaAoHmfNXXwCsL4BDauChPmJeP0
x22LIEefIByPrLgp6Bn/vIHYCxbKAZ4n56gGcxXBANtBV0Y67XuEy9VWQipBiTw1dscoCRXpUj1R
eGx/V11jtWUET5ZlNWmt5axFV8bBsHa+LcEt9GL7mEWitC+79Tv6xeCYE+EjmfTaWlaUhXkRjujB
FFcp+hvVqCXOADc5A3jMb03wjuwu9hH9WutsceOTpovH3Ee9VHgL6et4aAS7qkvyaMYgNXfv6ZPF
MBWeLiy3kWHLzdNuMFUViVjTeuxhzMKEIw6sbeRfeF3PUulq8PF0vRW8Pes8jQEKYKHROm765E6O
Fnf1sQRt1VGl9rTRwAy62yF0SsmwvSdAi1Sr2qVTn9IZhooCwxu0st1XhYNOd8sUJlVNYDWX51Ty
Q9OAPpgNVj2u/YDsQ+KAyA/aePx7IY/nWWjqeAShOJ/5k+f3Xii7gNHiGPxt6aL0VE989n5Uw5we
0uZ9o5byRtHGeJUQ/b9i6+okwS+iumD+ahbrEYa4UHFe26Tb64Cnl5a1Bfk4Xd1TqQAxpOmk7IBC
U9AHF5rH1tAvL6vuBwdce0qV8LBaCvfWHHsUaozw/zRNI61CwAv0eQ3YMi9777LIdIC42D+jm34c
0Xmh61MdQwYDwYKjm5m5njLYMY8eSk1qi7w71uUQ3nV3HNQbCYCBlMzpF7lyizdHCymvfXFO6VvO
hFaEGo8RSNrtYelYOxokY8obdqlDcHp68GobM/1lV3WQ9YVRacKo3TxVSMjb169mOg+AQ+FpXwQM
ylDM5XJVl+ZPtlJRM4lDiS6NUe4yBi3PB1+iesnjoJDWh7zFdT2fhJH8vYfcQ2nPBJTt17ulsITg
kEyq6SmS1mlTK7t1nFqUo0dKZm19tBTUYanib2zHP+xP2ctpWD/4e0n5XtrGNlyAHvvsCylfGyEV
dO2FQl/Yy5tB4hbOM6/l6nFQeF4PUv1bh6eflog2DSjL2nGvsv2tkfzW5yfGuqsX/CNLP3jQi3/p
4dfe4MTUv1b1VChGUmDQvTAb+6kE4S7pLLItoyZQ1v0uyXTbmSyzlMMuLS0bNbHCsTdJ6ugrDL0Z
/pIdTj6wsIx9mAMTY5BUFnnmI6LqPkWdDoeyU9tWq8y2v+t8/TBJ4+tU1/FYlpAk1aJYKxMgIIwt
JTkf2oPD2W53VVUY7qbhZe9ULCr4xWgEFGqYdxesybSuTZqzadDzCYyJjKQPTPa1lyoJqhYgLVgs
CygIVoGROVAMSOSNDZMR3JN0NHf16vhV4yFwGrf/6g/QDNxUXXnC+JiRojvRiOMrq6rTb9r4zDCr
j4Vs46G0SWsTxxr5HiES6/jGjh5ybTPUsKDpZ6Jp9aR172pWxJ1f9YyHEglLawlpF3v9NG9te+nx
mygBKXRnY9gmZAkiD1EUuVg5xmdWft/B08q2++V/C/uKMY0S6cFUiwfB5ibP/9TYS2kje0nZtZLH
CzUUromroTD+euEA173uUhArtmrbjkXiK8A5gKVRvOuy35G0SHgyCZHGaDa317J7zsOHaONXnz9T
4Ly6C1BSA8BR2bC0gaDTi/fmG9prTuAZHNQ5vXP93DSoxNhxN3p4mCAXbfjtlnAzqNShlENT/aKd
Gxy0Xk4panI188qEAn9a9LD2VeTsEAPsETdY0Fa55Inoye8K4+ExNjUflMiuy/lIda9A14y5pMmb
xz9rAyR+Y+lQfbYQlzCWQxjVTo0YnpSAWlp3XcTRzClG0Fk03OUfKFVkkaBHLiBOXUW6SaUyMXsc
WB7wbozYm5N64Vh3JIo0A89sFDaEvyA3v7CPAwulQzeF0laWGi6qDxY4Mt5HVXxin+ji3tNnxzH9
vwTqOvFjd0pT2F7I/Xp3IlYEUQz3YT1qnKcht58AsDeTIliBH/JGMFOMwVZeXXb1JeMsjO8Ob0Z4
rJvfxyE9UVEJwMVrNK5UqAselDbr8H3HF0K5icQtSDrm9a2ymxBCv0vWOVdercUMI7MNtd9YIWhV
LKyKIfoKcYIjwNSJu/SWSoccbTUeQ7/dmRqCXhTmKWZyQdG2gjqkHcJF/5hvLWjndV6DFN4DUrM7
2pZLSAn94klwbt+fGt5ZAuYNncAX6jy5rNSH68flI/os+jiORxeesbgIezXKNDTGjHXSc7+cOMf6
lvzMoGM3vBwUjNqIJ1gs6rmb9HnC6tHZwDAfeSJAIcq2viucmpd4mv9cSDnYSxsY6XsRiVrAyLRN
fYa533/KKVJ1f1ejQWOG2Ik6aKR8G+RKpetprQLW5i0XvgF+NEW3pv3KORPv/n0OjrR8xm6AU6Ho
a9MABqwVsXTfQsh998Wx9sYDhTjq9MxBu/diJquVf9AhePFTYjw2/O+UnBvlcHQPU/8Xsf4rW/3d
27uF6oDwOnZMhCJ2rwB9awViLTeRq/OmAW4IDLnZ19u3r0mUvt/xCm8asoYouMPPh4lV5z8X5qC1
5BjOkL7gXPQsB5EEZoifTnh8nmJaRITekhjp9yWvNTSQiH5aVVxiF+MAiKIMJg82AkC9U8LzBv68
4WRbGTHKcxh3dTp1eWSUBvRwVCWMlWIY5kglM5Z3TYW7N2TjRFWz9dmbjhonMnt9XCGMHsc8euxT
GVa6yVkn4bB5aQa+cQqNxdDVYaNJGFJmYo3L/RCrWQDe4gATAZWzxovOOc7l8J3ag7CJ8UlW7Qz/
85NDCLEzgbrreSgTZ1rI1bwkvPLPyeV9ziDOraCJkZNOuPNsrwfMh6MrNncZV0VF79VeJJlsV2AA
yUOr1wrgkCfgK03HmGO/+Jzt7zqmEUGqHG24iSfobkBagvznhDERUZcYHjSPgBJRVgW0E+nO7rWs
87JFJXK81CSzPknsPJZpoDfvdCqlzFYecHnT6X1tmiI6RlosfVzqC81N0iPlVQqbYgO/WCv0iVuV
3zzR6fbUWMhqOG/nAZh4Jp74+/1UJKvbB4RIz+IkP1hiNjcMw8uNxXaG1RRhEKZ1Gmb/xD7tiSne
bsuRZ+NuSzf7OuEekENrZZhRvCcFWztBjK6z/nzkZmB87BKfDXFSctG7RTPOajIUhWWlqTRjST7g
SHmpRZ6fV/ZmjPlu+0lcaiLWlEnXsJo0pYpZ9UBSigxbCNhwek5ILvDkPyS/i0y7dAbOI1ZW61RX
4AEI9OnzulQLLG8JQ73ED02UFZ0M7sZQG96m8R7JpSzFKVV1RBnjXgAk4OVsMR3w04BLA9nouE+u
+4gMhYxBh6AUSj49fwpH7Nqvowt4HaJTYQs3zzCj4s6KyYV+jyIrWJnqWveIMJ1qXpq4P11fXHhy
dCFDcNKy/GLsW5Ag6DZPa+SjzbJB1RxrU5eJcLH2io6vctQsuTwuHBnGZ8EvJHUSD8Ed1TPyHXr2
yXD6nAkc6CcbBLb67BvajYoRwnOPeAZ9jcuSoOvQ7nTz75g24tZUW3P5UsgO6t6rCJ5J5TIzjTSP
sYmPGstD76/T1DOwTBxzHf/kCNe1eNiEf4u8BHerWAJi+oUfbljSTaC4zCxnca1ehBiVsA2pdnuZ
vFtcrTxwrdDiqZribtm5N+8T95YsEs1zr8XKba92mD0/dapcqcodcjmy94UDeUv5vqIwV+EmsGRR
xmzPU6FXCIm/EdKABX34hY7h2sgEDeL+Htp7jHuPxfehDLCnCucnnFcg9ZB+R+jHhWLm75mvcC9c
c+VSxkWt7U1JraVJQUPEMxg9U9LjMgYOyzDYM6BS3CxdB7JDHzM2GkhalRHNCRJ8eUjyJ7y3MBiF
WofleVFLvQ/zHVQB8yNvUJHLNR1YS/v3RtANcQUpi6t0aqpciyL2RzP4hcG9yMr+JaSPmNRloMZi
lNXf4xgjRwB8d41/0B/ooZv39bwmXgV9jmRfgp0tS+qRqEhA7OHYVOci5YPZ4psqF7Sm6CbT1ooG
xjI5LXOW0e8ZkqOmJdp9zB6PKOgzzrVw7TCbrzBN8MBH5lOLFTD/FfjbpqkVTQMrU/KbA7XeNCLJ
6vRbnCSUIUSr6rG71apG3iQ5nBzmqwV9udyoqvG0XpshuBqyHnvMzBe1VTjGe7QEg9JTTVEwE7e1
fRabOhsuV+LsXCa4UnLbpkv6L+JtFTI0rjf6GhtycSaD582LM+pgTdDvLnbLB/u5y2qqkFaE5kw3
eNH5OVVETiMG4gSVJr2tN9eyM9CKIEzvh6pvzD6E3p02DpdhQjxU9T9Jns+XXni2QwmCUqohwBCH
SvmlsGp+6KfgGhBCRLs5/4RgWPAeORDcqVFU/qVuU4kX/YfY59wQDGRYgABcJMFmLJ0g2DHjjxbX
56Mgfg5qGfoapKPPdfSAf9q/CN3xhzM6KpfN9SH91fJeJttYlkLwTJuP8N9ziMahkcqitTOBQ7Ke
1qPpMIi0fDlimNdEWg8UP9ua02aMIChJlJKDb07lVtxpa/hxMCnoKSMKMT+ldGUL33B2QnpnNiOW
1PnFM/xNDy42t9981cypoP+aWjoH69FpKenqGRh2GigD1IrrmbgkLPj8BT8NAvE974MUNcylHzYv
CweHZdzEs8LRjsLIC0FEj/HFfeBMKrZK4do7tBKUtbuCeoq62RWclX5D2/TuVqNQ5fuAD+t8qyY3
09C/FJUfEpnhnXMDivgMQx2n2/0xPXZ0SQT8TRtLk7syuQ4H+LvQv+95TiMLPePJpblC4gmcsbOS
MF+JDlgYImA+svBVRsMfXFknOQXbAENLE/AA2ftJ8CkWSeRWF6eOJaUyy4kZUAJNzl4KsnY6Dbka
QCh13/s2U4lQisQjCJLAtkZEbauaZQ4zK5WM9FdUXqu7AIOkEAmeWIKpky8SHQ+h0uHSK1sUOf5o
5eIjU4W6RcZ2s9ermyfvlTOANJ1IbSkD0pRMkqFelTcRwz5hnLhoJOgHmrBbukgYB4G6i7t7mqau
c6omsz5VSxFErzZ0TmME46XcN+kxvGC+tijLSR4jKcyNf5e81wQeA2CGCyZDJUpSxnIBg9Q7glZI
zmXGiqbxSoDOT6BqkPXrD/RcoEyd/Rl3+eZwVXCscgkTSLP6iU1Ei0ekgd0A8jr7jqbe8az/ZGKX
bAul317R4Tu/90NgsMj4o//9z78bX8TDYcBjGrSCi1NU/6q4EVdbe5SN/tshQaQfkml/jy3/lEOt
x+UtlDzQWqG7BoTbXxLbqwARH5Jf1Q+LMhDDO6bHFqWPF4TWNKs/5Bt/rND4e0KiC/XUeI4jPqgS
QOdV7ueOb54mtlMNfL1NpP6H5misM02aGXzLyte2INCbYKBGdk5JSFtmNdOOwIhRXzAwQciXd644
5Wo9MdgCIJfJVDQs75X19uytzFRbktzXhbL/o1v4KZuVn1Qpg+A/dAeuqNYEc3mItKilUJj3iYX5
3Px3IBfHS1TpuueMD4lf0Qxixv0fVK/mJb8oNXBrfEmEPMFVdgUllfLfEWCvXIDB8DlOaWDcNAdv
2nhoVEIITqKT1OPS9NZR57iO+mMiNsCPE3pFRewdjc7GPnr97Qv4LTBvyqaLV85fFs9GmWOVTaMW
WzXtZv7KvBF04nkJ2HHUIkNZ/sQh7z7F2jQ9EQBCrXx8MK+QdIwiG/nVlm2i/ylwA7wfChg3YDyJ
eWIgDS8R+fdUR+03k6ayBL+Dq2VJ8hf2TA+Xdv0e2Zj+/6YVxsdU2eiRMu2Nr+WQTzO5Uazs4nXv
3iOaNJM77vE1AA/MfDeE8E9ViUtMXRIwqpS5ZvcCW9ugi+3V9xFp2Q4qqSwPKe6KZeZfbK21cv7m
hL5bQpOkgbi7jMCCDvgFGHo9T6jvZlp+pOI0AwSQOopvrz2zPD7+iZWPz+ksrDydCB5c7OFJpEln
472V7BRcuyH3yZBp1yVfAR2gpbHZuHmDtwPk0mdA0pFhXwQgoXDjZyHoybMfi86KPNtywdpDslK7
rCJREChQOC27aKYqLVhj9D3RSCQsu/1oYziscJGa2P3ap2hLrTBdXvausj6jajYOv16XxksHwiEU
+1zkh/Z6qeebDKYCALguWYC2B3rqLdq6gA+jk8WYCUjEKnqiwcFv8ZNmuEte0gkqq1G9y5RRLgtr
RFOn8tQb/kUYRXgTEOyJW2IE+wuOgP4vBiRbZT+OmjLfaDdmae9l8eKX+H+v8KdTkroQPb3VKtqv
bbWyc+gWI2XfIc+Yvlva5GwytUSCEHC/bxHW1unZLxsT4wSxmBL53m88BGxcukfUIBr8W2PfLnnV
6NMX3i50LpPBCmKivyfLFPPV9GJOYe2ei3rzhVk1jpDZepU0lUGvAOlmL3T4E1vdBPZ34ySMIRa6
l/N7FpFolEV45QoPHOuO8B1JPF7cjotFdLLwyDTZUO3y25a5yuyu79nkIzuxHZvbYN81r4Lhm86g
0nGd9iKJGpj6Ha4OlZPMw/3jmINZCFLOTaYUohEHwCvnfP7XH7CbbRuTW9mNri9rhJtmJHuIzD92
hw/owhx97zTQ4NpY3qx0Jt0jSDhh9a5Vty/t+wpHd4HOdo/A25QSHiQ0S7mnqv40uJa1u+eSWMeR
22P3i9QCQmvO4nEppXKX2UfZaQ9rLPz/Kqg/5ZYDeF3yijSB5LBQ3oIGEeKWKGqMTouxn6LDUEJW
KHiKerBaGQmFqOJaaJeCdnneAjvi50cX6hobjFLVueCXAuRDqqqygmqGm1Hn9/miMGszJZW/53z3
FZX9Fnj+3I7QYrR3wXfX794Mxde9dN3aveYayB31m6ddASlRmvxjfJdLDagoEgLOQ9OjY3dAZxPU
VUx5VtWQnfCd32PzgRDz16E5lzQiCRbW1td/oEtT6teDL2aOtx/D76dLoBh8rL7i37ZFfwN4sIJA
g9dgDm4tMhTsT9mmw0utuKM/hW1tLO3Olw4refqHfaidu3XG+bmKsyiMkV2Bw0lN5TU2T1IPsQTv
h+KFN7sDQBoIUe19yJffOiuEkAcCQH6Gf8Q0jCipJq2AcfbgNb4fopyKlqFf1eeBFSYPPgY4SOTT
d4bVCOneV5PUrT8XT0Y2qSxMh2q7PI/SUWBReec2nKKlWgRD0EK8K6ggzJi2hjP2BSngI6fKCGyk
EMtFWKYx/MnFyfA7LRtQvsKzDz3ICBmfBuSBNAPO+aLQKTBmOnXTu0dA4BG62Vuk4NPlB6uZfJ3w
ZF+B607pfuf+TuWUtafoQ96eMDBPZxnzGIiSATjGamXsZkeojMSqUdMoWUJX3YpQnlOTBuqzrMXs
KCiru7Xqd4XO4LRbP32dqtDVzOH+oLMDGgfWz9DO58tQl0mgJj4Tm3QYOKTfJYMcgeoydgUB/aQv
hZ7reiL+0CkGpputER7203UvKAy8RPu7QeylxZtvEflbfyUNbruTAN9gPFBKoyzvgUQpE1Ou6r4j
wuI3jVfO2y7+2Nd2kESrGbBKamHeTqlM3JdzPZxHIorlILKWjGC2OWUKAeWnTpDXoC868sFIqYfz
NDQT7KNjTSOKS6qrmAbBLqJxXCSxRskCm9uH82UYGMfGofy6EeKAO9X3zoRGPgZrDrjpQRND+Vz/
mE+/nIzAAfRYkatVVrpPpvvZ/0Wce4HX4YaHvB0+dluPu8popkdp2YiFwi/+l7dQ2opmfMTHca2d
WY8VDntFEcDbpoiup6HWjw11jWmpIPu5ly+2YuEQLwbkKgv5Xidbgeghn+Xsta1RL+hgDegaopg9
EoPiu5JSFnT0AWf3V2fcS9x/CDIYvxaUlQUoXF2yZmwUgH1Hwipcw71E4yqo1wcL5X0xxebQdtSC
1kFa5N1gmDP8uKeK3UqZc5NBiU3uGbmP1RM2kwq4BfBVwgmB//JE6nIYE4HMGKbq49LpY77sDy5i
Sc1c2u9Pf6LMntFw78EcM+v+NPy9/N8uyFIr1rrfYltrpWd/CHpS1vAox1Oea6cdDLBj0e7y7kBz
jYU9Fhrlbt5G32+myCjAKs7mkIkem8bhp9enOvcpBPTq
`protect end_protected
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/sim/vhdl/sin_taylor_serieseOg.vhd | 4 | 3084 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_serieseOg is
generic (
ID : integer := 9;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_serieseOg is
--------------------- Component ---------------------
component sin_taylor_series_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_ddiv_29_no_dsp_64_u : component sin_taylor_series_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/sim/vhdl/fact.vhd | 4 | 19741 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of fact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal result_int_reg_38 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_50 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_73_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_reg_95 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_fu_79_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_89_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_2_reg_109 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal grp_fu_66_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_reg_114 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal grp_fu_61_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal i_phi_fu_54_p4 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal grp_fu_66_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_cast_fu_69_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state9_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component sin_taylor_seriesbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_seriescud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesbkb_x_U4 : component sin_taylor_seriesbkb
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => result_int_reg_38,
din1 => tmp_s_reg_114,
ce => ap_const_logic_1,
dout => grp_fu_61_p2);
sin_taylor_seriescud_U5 : component sin_taylor_seriescud
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_66_p0,
ce => ap_const_logic_1,
dout => grp_fu_66_p1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_50_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
i_reg_50 <= i_2_reg_109;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_50 <= ap_const_lv6_1;
end if;
end if;
end process;
result_int_reg_38_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_reg_pp0_iter1_exitcond_reg_100 = ap_const_lv1_0))) then
result_int_reg_38 <= grp_fu_61_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
result_int_reg_38 <= ap_const_lv64_3FF0000000000000;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_reg_100 <= exitcond_reg_100;
exitcond_reg_100 <= exitcond_fu_79_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
i_2_reg_109 <= i_2_fu_89_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp_3_reg_95 <= tmp_3_fu_73_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0))) then
tmp_s_reg_114 <= grp_fu_66_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_fu_79_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if (((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state14 <= ap_CS_fsm(7);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_fu_79_p2)
begin
if ((exitcond_fu_79_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= result_int_reg_38;
exitcond_fu_79_p2 <= "1" when (i_phi_fu_54_p4 = tmp_3_reg_95) else "0";
grp_fu_66_p0 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_phi_fu_54_p4),32));
i_2_fu_89_p2 <= std_logic_vector(unsigned(i_phi_fu_54_p4) + unsigned(ap_const_lv6_1));
i_phi_fu_54_p4_assign_proc : process(i_reg_50, exitcond_reg_100, ap_CS_fsm_pp0_stage0, i_2_reg_109, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_54_p4 <= i_2_reg_109;
else
i_phi_fu_54_p4 <= i_reg_50;
end if;
end process;
tmp_3_fu_73_p2 <= std_logic_vector(unsigned(tmp_cast_fu_69_p1) + unsigned(ap_const_lv6_1));
tmp_cast_fu_69_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x),6));
end behav;
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_ddiv_29_no_dsp_64/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 20 | 30077 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
N0hMcXbI5hCFMXvbzZaWNMXky7Cb78UlPrOh26mC4IyomLPXkDt4pohvBi74RwhMjj/Bp6A1/EjU
BW4AL9d6yw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
O4cgU289ETKimPPpC1lQoWfngvpNmR5tUZAEw+00K8UK2gEeqXn1hb3g7AZENGEwMii7hns4XQy8
DXQ5xw0Yp1Lt5kPvabj5mKM1bMdX8dvR9NHP3g1Qjd7okAVBl07/JG0NTnpHDOfWPgdIKiG5gomz
/inOtmJ9dyw3SQwornQ=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
DU+IJVy0UCp9Ru4O1AHH4hAsURQvG4KWjfdJuBdXBn/Aw7vf76lLrDggWEsh/tDsD2w8gcTI1KZj
gte8Qz0RBjJA/tV/Q7C3IGP9sKs04WbpHeToWiLkJhGVSOi1cfBwcXqun7kk3rw8tbtRvnn4LLnQ
VVSnOUM0P3u3t9b+354=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VU2OWBPAFdMWY9YsdLW9vHBQultKfSyqJgSm8GFxf210g4AV7503RY1sTzcwbpKduWx2mEapVrlR
2+Drhdzv1Rts/cH1vI36ZrlUVzIXAPfly2Vw/ZI3vZ8ecksIx4K68q0S13FJLdHLryPXLuFGokYw
gCOZnAxTuOQQMCgsJA0iDJVXFdmLXzqwRYBXguqf1r+OMVPXs57gcwlgVB8r2wrtRxBvH0uRcmEd
9XDbIcnUXETCLhyRgVVpblWBh8bZbcQBY/zZZ/sbyAPD6J7Rp8CEPhLVVCsK4EjNey5PsDgo/izg
h4bUKLC5eF2W7tVckgp7jyOfw3DgIr/wn7RxeQ==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
V2G0fgDEE2OFe05Cx8OR1KsgdINzVEXBIBadpSnPXIoTc7xRwAe4/VP6V+6MXz0QrLZuQHVAj7G3
9F/ijf7v4vM07B7zCCzqKWXPOd8bPZE51/A2H7Mt+ilGqjbh/VKLmxGs4hilsENWISKVXeBdKnPY
gj2HGvaphMJpBpJwjPAKBmbUyTX5Sd9nNIMzcSRJNulwiaiEOrABFlrZOI+c7bZY5sHmVeOtg9CQ
vhwpJiZDt2xEUYZdJ+nAzC0+NS9jg6KFWoyyUeNOwHZC9//fhh1MCUzJ0nZg2R4hBpRaxLZstp3w
PM0at5MBtCkDuhRItVUmq9A0HtCUCEmB412P1w==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RN/6I+vbSUSbgQKZutSOM516q9s9JryaK6V/qqxo3gcYd+gU9W/srRAx8TWXTu0WbgzNnJ4y7Myb
hqdFZXcfJ/PxMgXPrrBTM9dc9q6Om0xxWrgSNxYalV3KY2vgAYOZai6mnccqhDfT+ZicibnnsYmh
yf5l9IBMwTbxQ9cpGytJTrr0jtjFG8izeH9CEj3vxYZQ4tA0TFJhsFvQhk2xXEnWnEBhTQbSX/B3
CADhGzXitOUqpBt3ylEkYkNM5wRAzze9LtBQhOCFWc4AJq4+3/P22qqco2g+VSDFNt7Sbc/BGwyj
q/3tdC0FZkEZB5DXnSDvgc9OVq2Fggic0aDyNw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
0lfuWTRLbdGpP+bt43o7Y3baOR3u7fPK0pBLqY7uP0pQ+2ht0P208f6mMmjAZkVFJU5i9ZpW1tkF
wD5qhRjJ/mff1za19WGTM8NEjj3Lgv2vtZrOQlSeCSfLEOAT7NsfQ4kQqqhmT1zaHkk89YCN8a9q
9xPGyMCXJGJSQ2huwnzDsHOnhWHlWL/ilzzMT7dDXnOUeGPNVal/ZBe72iYJj4f5eoRHew9SvI0S
Ut2Q3RHzpI/teRWNAdgVt15pdsyvyo9uqAtiHOlP5A7uqdndV94bWqKkoWPHzcYQJvuE59QFQ1WE
cr6/pK1peH4vFlM8W2tuxlyW6OcL51xzLPEmg4W+8TkWa9OFYdBlsYbUHYOc3tMeeOtnR5C2WgJN
uxU0Mo1Pdosa0/c7ja8j39ols+/uBkhEYy8hbWXRUa7dOAQ3PE920SjzPMeGxb1BnlgMCvr/m4r9
Ubn/TP99CteWMzrL6ZpVoWUIoukbZMgqMSfJHi1YJqkDs6TFjJsfUhzmW581OYiW1j3C3OYLCLCK
oBksaAsNUUcBviHK9jSJBuZ30Pz904QILhsG0psuSICS+hNgqGwOD6MLn6Lf3sb4rftwt1kARblZ
3yi23yicRqrkKfPlVMHjM5+uNQpHxp5eLdClNs9lw0NC2o822auv2DzRUHQkLwTWCJpmKLnGmOJ+
d7s5CwoI9pLtJnxLcuLxnvUS8HrPyy0cE4y/+ncgJjBLHsjVfn753do3GAyfbbl+HilGJBCVlbPu
MOgSNxucReCoaY0BjDf+WH8IdlP6XUysGVCru+V0OfA2BYi+tNuRPmS9CGg05mViNa4HvvOv8fi2
TtURkBzS3lw8EyUhejx1AX5UG30FrlrJBrMguOiK4HORdCSOxGbfIBlZssLeF1cObZM37iAzBiKO
QRT5kneG8EgxdjC0ceYQu26RlZ5NJeS9kLjDNXuRgE0V+aPkjl39p0ZWQDSTnVlx7ytnwr3ZiJ/W
QT2m9mlD/5ek+JQtegloHQbu35GWW6aLCJOlRgj4op8Uw/H0Igi3yY9NBdkFigZ3eprXgAfgSI+J
jS41wRxrjwBfTY3s7yJNNGNEGv5Zgh/YmrRMNF7u4+z8JIZ4ugBrRP1oV0hRthi5aaNS1tFGa2p3
2MNApyP3+QbBfjKgB4kYdsHfRvuSJHFfsaS5bbaY1gUKjw9/J89vxht0UMIWLQ5j0Wzsw4dTTSSf
jtnrWCWP8O84mPsdhFVVwKWqb5zyZv+FMQ1SXDlR4cW1wM6ztREdT738MOR1SAZr1ZC8NVuBduMY
QIT1SasWBzzvsV8ybhuL//DxumnlzG9PO5StfN1AEpgH2FTFuu2zj37p2rjkao//ExLhgh2JpKdG
PcvgsMNVBDHmjtopEny4pc6Utsii9DXZ6ZqDaDVExyjcQFqU52tbbXIaAwgaw2fYgbSGKaGT9uNz
pwAxBM/34qbtQWs/SNwZDVmzBqjrD8Jjqu4VZFrrvfEAgcD8KOdqW/PSCrHLIWyOwgMc2ZGnX5eX
RQwWS9dA9eYlcLJmR8ve5QcjRHYtoEpD1rpJIXrh24bKV0qBaE6d/cbYwsOL/iT76TNVwbkP5twH
1Ejf+xftsyMXQxZfGDYdju5MTjaf3uP1i0hYJUl42w1++jPvCkeal1oSteOdcbDC2k49HvrZ1UA6
Gj8BbGQbpgfz6R7XceGg/QNgfiZSvB7fQwF+q3ZrrK/RJNacTPI6mm+5+yf8UOxEQm5gGXRbHE6Q
dfFZWQQnW8YHPvFYkZbdAgBYfnBrNx9/Ws9zt3n5b1FcdUdZGkiZxFheoN25CIF0gY9vM8AsuIOD
4rNjCjwiuc1egbUGyn/31DcO0xK0JGIZ1OLcF0+YYn0FOz/UYFZdvTM3Jt6un/bnkho5Sw1DLFOB
2gQF3QA0phY2RyodT4Xi6HAzo8Ll+mGXoUd2rr+a6gdqZE/NSJl775XfaI79ohhx60Go1gdGbl1R
RDqCE9Gy9qjysZUwbv2xp26OwVAhR9t5fQBQbNIeSO116jBa78ORJc9mFuR5S7S3yvrQum4aJQ9a
C1rXsZmuGiGcUBb1fixLoAnTUm4RsRu6kI3LjDCuh3qQXQ9YK+KyE8LaqPCE8mAmv5DC2XttvijI
7PGW3xw5V0ZAgXPXcYjSXI8nF4Wh6mfOtm049GvERQ3XHWbiblczfGvg2juTK5T8/VlIIRLpzVud
PiNsETaTbbveJyri9LiyelqU2dTfC2o1T7RzIyG5J2Ru38q+RsSHLmWDBk8Z9dYPoSP2ixAv1ksG
dI8nTwEAQHxXTfl2myiJUwBTZesMlzdeafiOku8lXp6Gz6e9EBLfHjKgr7Yl64Qzft1KwM+geBfk
mUBVzQICuCpsPDEe4DYMbyS2Htl/uDQzxUl5z3OjeEAW3A9PfndqnM6KE0VvmPj/FMNkmyLzxcp/
y7N+lhsMtpEd5sKXyzOiV8mnwKKnwzk+6QqR2A9rkgAhUjcp4Yv1wbSnyntzAhyBTUotDMLxe64D
LjQe+wtSnekxoabmFc7OYL5vJQHk/8ngcB2iaO25X4wnubRRwbfSPBxRM6pU8ZQtnHboGJeWhc+Q
3HfnpTys3IHyAlIXWkwSDVbtWsZAMd3XOvdlcoDzjr4Sx7snBfRD8A3wTRBTn5TdhG2xYsAqtAep
iTlqEn85MdSA1wSQv58MJ0Kwtuvu9T/3U0ghJbkW3z2di28qlJcSFmz96dEnIeZlevWHHHl5ZFNE
9EanjO3xbEa0h6NZnqD5PI+qxNq91qVL2+Wuy274uT27hHo3pcv1FCWU5SjPunGzyD0wn3vtHxfI
37Ly+WGEthwqFMtmE/Ojqnbvqs/aMX/1I/25EVk7ryVkiufd81KLfvwNYG4dDHwMTkt5wrR5wJ+a
tYYFePQmMX4MscXysY3cyMZnSe30sNxox8EJv+UHJjqrgEaibIxi5XSoqlcAR0oJZOV1iNgB60FT
TwcxnYiTGisJ5hNAa9dSzQo8Kxs/S1rrW7eqCkAmJpsNTl2gFFAMyvtbxHcRN+9JHGWei0Hylnsw
Wg8gr6DYxLHG065R1pTiSgmO964HH2xue6iSH7mgfIxaRwapkc0pVF/Fz+M5ksSjp3HI9yLdodwM
84a1QeTCZRnSZx17NXyfLmzkznMIBD64raCgZiwksclyO00iVJYo8uapEbEDji+bFePmFNJAnNpR
LwvAFQYt1eOg9C2Kf2ZOuVZmRDCzUcd+pBEE+dp71f8D/TwCY+fCaSEAFJROUoz8FgS+vCNG78ND
vw9Sg2dFCdIDW0SRTbcQEte+5ZB26thLHQjTv2BuRMNyjVzq1BeaztXrbIgrVIkSNqVmujVt8+NK
W47lIxkODvUIxXaVIoU5R2DXudlNhBdWmUcnTE6jnLPLEyF9jewTgQ4bxqvvf2QhVEujXXOe58Xd
FrIhV92MFR+nGK1U8RdsqY4C1hbbWlMmSSj1DAL7+KEi3RuwOkZpR9m/mD8SyqReouviaP/e5J2c
6BPFAyTD6QHGbqYxqVcBOFbkYtARwapEIWkqu0/0f6UAiHighu5Kr7+oJf+94WAlgGo8wLhAq34k
W14pNfkWNeF+jB3Ctx2DJzVYLimfyQkLS/oYdN9eeXqHgC6RmIbiZ71380zV5+ikbuSunuVbJTGC
tyilOySkOQIOZHxxHDWCcTujl/netKRiSXm5f7ctX67UKkExlnqouLufKleTlJOgT1trNADOfzoP
VQRpP3JLaG5HUuOMLst8qqRCB+hMUI/Yw+NJgmElpjtcmv5kkxhP43ZZ7VIkcihEzj2z3aOSMAwN
sbnPgC97zgzvee+CcklRhwtGpnkRIWj3SxZW8y37boRC2DAIgOTMN3iCCf8EKeM57JALKebCBEG7
UxF4ixdrn/jez3dW1A71oSTo8SfeCLkD6ZxYCqnSwySi/vPocb8W4UyMX7TMv2qcZ4RzIG+NG1x4
9rLs4IFfQ5rLa/0SVO3rzJmL+RvYrfIzG31QyXg9G3AcHg1S6QpDPvjPeLoyunG7g0uKlFcgUOEa
VgE3yv0AscwMlXKaLt6qI0b21GhCmfdUoVCdoWSn+/894q+PbFnljcq85caGjQR/Vt85RFZ6ZMC6
218JzA4WlRUVrSFqp2WjuvOCdf+SH4xKMRWBUy1+APeDhMocelpwhpEVibK4rZr5uu8HCNm+2afQ
8WUHc5aSvGclQJUrO6nUM+03dtkfnlLA3qT3P1F1DVfJEuCt52WWLw54OY+G8flDeBWz4JZv/MCT
Q1QIzmOsSjWN/LlR/qmZaSrreKdkqL2LkspKqPvL7rB8mfCg96S6zeRtAJkYuogKgO1m2HU/tRMw
EqMvusXp9ZgVRT/GZ0VbwSM5jptGlZl3Ty8xVmyhzAiCyMBktZeZRbT28F+9LZITa/WxSlPWv34B
VEQwrRQBwphx0nV1+b+pKSFT6Jp/Yb0oPYLUSs9GRKn3ZaDXni6GeSSjhRwKwz/GCJL9opu7h0k2
5OdIJhOVy26JnWha7VXKyMV4OCxXiWjGY05qXLy0OoDhkQGfbvo+iaGLnMhAwYOFUJwFcJT7h7FS
1a2CaeiEHnC8tYsBY0Yg3oEYeh3TLg4ibr8kmIPvQQ/97lgLU4vC24Rqs5akXDSJrzBEzjI1QNI5
yJuBNOcATW5GwNdCokxLUg0NCKqgp05fmooxxuPXdX/uXKqp3umNRveHnGX4RP0cNpx0ANrrl7YY
vgHnH5BUOKaSLBU+2SYFAUis7BzzYSIect5JSivfpGpmq9KVhPMT9j0kOooIHu8gdmTeNKvCpeOE
OQRWhbPUtM0drC1n0lX7zUXdXXR69EuxPxR2HnqiAyDHMqpUsNNOXVlCd6iE5EYPJnwY6ns0DlSX
FnLFqcKy/Eje49VWLVJKORPbYXYtxeuxwuFrJMVkrchJTrqOPZp/90Rl7LIlE8gjc//RSdps26Zr
Wmzh9nRsvRcYaZrKfFTeo62jLTP09Wu0NK4KcKQZm1As4ol+7rkwczvqFhOE5YDzdbhcOhXEOQVm
/oou/hzQqKfKr8iv7yUwwu/qkiCsY/tapd0O+ExidCIQNyBocb0A5ve2Q7srLiL/Mk8//tTKKjrS
f/K54j2UJPhT2OrYsDNSvllrOt8Edn/u5OAgmxWsyDLJjX31Y38qvdWE5F8VGFHxh2YAYoMBU3n2
lw84HRR7W7xQI8bMxlHa7smbZjzPxmxYgxH6HVCXUwLeCMCMA3+ZvMQay8uL1vRC0yrBM4nysWSM
VySKeULi3Y7CPYSUq+07n7wh6rMzM4nEgiacjNs5YNpMn9KAqjtx/qh81aKrhppUb+mDeGvuDvN/
8qw8x+e2yHLgIuYfAEXjowqVznGoV1OyVaiqkmUncFk1q+br/WHuaXorpr93w/iAPQIaWUc7arle
GtYAPf2vHgMLbnxqnm5d9/rwDoQdiaRfSGZ9h4NpNiPkxK/C27KwIPUceyjDYXlS/5BAEgl+DpOS
/q4V0tIPUIUpcVCcz7QRz5suZbbiISstNKv6oe7tTg7f4jItMJhHDEjwQaZWvePqylLYjQW3g3FV
XfbgvJcQrPsnoFFUqN30c2DENHmGU+lFZcloovVRc3li07kD6Zw4ly4DUJdlh0CBl1hrdKuKErRw
bNtBugM89rpcMlo/iC5LnBPsDBUfEyBLldt0laxWQpYI4bAfcZL45R/Xjen9Q2G9Z01K8snUg3wA
5LiB1NOcjSFIACRyUaTD4goTq0BBV+Nd6i5jHkdXzYgjHvNxhM+FgrcTIpceJk6lv1I4PVqGXOId
iC/EME8VjcG1Pk7TkTtFbSNJMf/UewGABatJVhEmXI5ZMGumtmtcC0Oz+xE0a0casBpdwGVeHoPC
DW4WbzBd8jvzP5d6RXkcpZny7y19FynZ/aCRJ7MwBZltpJ67YokGQPsQDQTzWGD/onwc3+Zmj9Ua
MJWiSFWmyQU3uTCRvRDk1MQEhcTfV+HG0+qjFXBnzwoqOxAklfFCToFjZ0W9Ql+EPPFDTHZkoQ+r
dzIWuyAIhG+bPP/rPex7nvKG3f/iZZs+7iYG3D2TLUZwiWIYagqOS7GKFr1LSpjukw6VD11AUemT
6KdoCdPX2m+HdEfhJGao/gcR66edFAztTE5jz65fklKpaucFCgsrfJApvujW1HHzTxpZfyMh9Dxf
XHabki4fd1yCUrt8Ap93EXmR2ecCwrSCMZgVnfFwovMf04GRUU4cXX+eQRiBxylWgFRD5JmVOymg
aqA2NG49bhxLjrySjywlO0yZccu2/ZQsnDl/UBK3EZdnC89c19UBJzFKOxUQZIbJBOhTYgBpHwZ7
jEYu3VRVz5N3EKoUb6Ga30QwmANLgnLoLHbyYu5VqEOwnNNjkWVMyRHIkG5ekraCLduSRdPX9tM1
dL6lz41PvoEpInwJjPrQaiSK2afapY/25LFOVXvwgM1o1e272oALGYrgquoYBnVr0wOQ4cuFHc8h
lfP1ESCYduobhKCwDKN0awHC7buTMHFw/fujKErCw5w4G/frYBolYlFslmvSo+xpDk6uJAhladGo
dGXDlQ3fBp6tm92BxaY4Fv7PniU03p/DSRXR/waJO3fGWVjDHK7ZSDn/zihr01WCVVg75/sq2uQ0
1z0tSZ8pfUGDoVb+JtjWYMQCdKSEd0r2/rq2gYXcoX8eT6unRJk1BAWIhqcz15cIG0u6DBU9Oxaf
2stguzgFmRDjfFu2o6zaug0r9wm4y7a4TLKgb3N5Lz5Zwasl38dI7mrkyO/k4R9NihN4rawufl1S
FqKPMT3N+1Gmk0BBt4I+vGXW7dlQgr98RfHB0o++mBR4Eu+9xPNJxeU+jekfHD1+Pdf4nde3GliY
gqAHbuFDmm1/5d48PxVSFxrF8i0nsAVGsi/viieswl69ApK9PmclFM68GEqfabZaVHCfIO4LvGhJ
fROjCWdfbWEI+uREskSYuC32su76rERwa/JyHIonuFZhVixPN0rBgM8scpF7lzy39KJL32cGzm3g
TZesiOMDrHEffTOSA6oGndKA1gJBibtcx/s5H6IM9a2iPY3uEh/XX7+5Xgu71ML4nZCpYXnCHOCZ
VslATI+VyamTdLAdIoLAoYcqDoKWtXbaYSu0CSvd63J2qw6UV6Qn1ugWq4aZb7pH3iBFJ2HIAYd0
tdZnGgwkZQqNiKYoXrhVP5i3q/No8Usl/4wtCIQ2TYCDUD9zaBIj4aVpZ7vwBowcbbJxYLttNILa
1i7SNfrdoKPCt2PNrNLIZuHnPHODTN/wQkrUJlG5AjI53qc0KfohR8nfOVopOvLyfpb0zxkuJnFp
pGTjNIpV3bpfjo+Fd8OtgZACCuyNBHr1ZJGGU3FGvuX01P4nCc0srh1/b+QCBb4fXCUtDmmN1dcg
jdlAixd+FZPJR0gPQeNzOYtrEo6K0ZCLGvPkBbPW4Hv1s4pHNJfmVvbla4HCq8luWMT5zyVlYIVi
viuHXelKGPTZ4oFKUvL50te3fZnSeOi4ciOkmq+wsWrU3ztyZPoFI6Ons/cRMiIXsxe9tSMmDYPC
DQ7uuBp5IWKYLOdqLF7dvDQiXXFQRvamk/Mo2kONRD1EHkZ7PN4LflbuCQaEZ3ZgkKs/6wJBjXaB
RyfqTb1pJ03BYXeyXUTW7y8lzay9kTsefuv0O0vDG7afyHqGuOdvpE62YWPu3TnLSMg96A5Jmv8Y
zR0mHGqxOfKTFDxG9Y8waxuA7LsnnIYfvq1kaZFz7uaYfy50dAF5n+/Xyn///WaD9GzNWurzdsUc
+ohfpCDtl8WeNJNAruRD9AATeoS9r+2Ey3WIKITR3ayS+CgdZIYcjQmEXxmWbKK1tXWCirccJGbu
7Dq8YtpsWFi4LzqlugRlUk8wU87/nnSjnrUWnIkK09ehQou8H96aUTKU52swcp4CQpPm0dRjbJTM
URCLQZql6xzLV9O7gHPjKtfapvT/Ckxx4ngbcdQt01DWqhDTBspSQaFFGWPoaltZiirFpQp9aFT/
zO9HII7epckLRveCNnnAuCKL3nWkXMquH7KQ3Cx8qe/U4bxxqDXGGMBBGejtFJ5sIgZ4Py080lwV
ROUeoDTmWtIlEA8mrEFY/mc71foOMrJYVUmlFrr85DxGJUjV4wQbZ7wYJoGBAraWeBpMd9csmHSk
IS2NTziEKYmQK4CTekR59Y/HM5jDmns6TnTXoQEWAwXMaG7lEkc2jO91DjsG8SBdVAo/XbGGe7E9
9PhhvbTRc2NHrce8uRacUzWOfTQgf7PAecoSnVtFXpSVqBMsr0FT1+i8ti4JKAfBL4jyJgwRP2lG
9Rfivy1+owc1VNLuLGZPiDHjwN64QWJyHJ55ncRbhaE289zqPQFaneDs9frfi+TPn4sMxdAWsDeB
Vgn1LXv8sEYdGYUxL6gB1+NBAWBukf+25jWN3xUOiS17sV99NkRnamKKnBA6/10KLRwcB8xt/EHp
jmANfIiTOUA84UP0eE9x8bkr4QOUVxB/g3/wMA5J975elV+mE2jZRkILHYN5jvVxGmIvWKX9QJI2
8COMcoCU03lXyABeOUtfzu+frc6gRBAMlrdOPgTEca6ZsR9RjLrpt1ufEsBS4+48vqGjKxXGnJ2O
4gzTMbTc1ZdkNqZeWEXu5NYx4xAzucw279wL9kTklqgsaz9VskwQ397UO+fkAzLPClxH3IetQYxa
EjLu59/MG3WtIYy7BCBHIgQa8fuaIBMsYPq6o9YrYHeHmTKS7JY3cvUq9/ujYOHa2tN8WqZu07PG
OWh8pC6/jhEvXiXByw9idhs6Hdzq/FqBwYAQrV8DQkN8+2iDEpC1jXrdt+PXZS6zR0xLyZuBjugR
y+AvgT0lZA9p1KJHU7XmG3qDujg5RRTnUMOIDD5eWjzaBY7poeCM2YSdDLgKITeVkDqkwMGEkHmb
UoDICkXDNbvBlxF4XoLYYFOVZhQxDJTdoCM9FS25ne1S+KCIIagUb0A5eW0eQmJJxBbZu3KZ2Paa
aQO4eKhijlPdlNEvYZQOriwOdaimq8V/iL0ZdESOM8mX6gEO3MfcmiH3p8dgnmelPYfK9GPDkdSu
WZtpbgeiMfR054jNM1QPWHyjy+3AwaEOSda8KQZHIli2a6CNZcxmWxDz4lUM49EqhLK13J7Fdmgs
29U7y6xacuxc6bhxxuDj0m8673anhcELLQpKP+YvFYus7B+87fdb9WAM8/OhC8Gf25pGm/qxwoZS
eLSsdhm/nF3ASPP6KaXnFsSu4VmmJAgQZkqWZCRaWot4dUWKWsdBlJhX2zUsst1r0myqJEHM99EX
kNijkQfWJ86uQwllRxZ2C4LfAUmpZIll8BVB6Nsjb6z+p/uogYC2DPBEfC7diODko4yKiMthHvZx
7tSf7La9hZGLMiwztCBtHKITjtCQ2H60n8daAubd3mqayiDrrnMxbMqoRZmK+g4yeYChWY/UEmXt
ExQ25fxrzfx/tT7g0aOwHBjaYIEjiAx9iZcu5ke9D/jtgLb2uj/9ykifJAFNI205m2WGyRNvc5a8
8t6K0QZSI1aL+KXcd+i0AnGX4wP/sCJy5KF6+lhWiEbljYwcte2vydYvCQbCKbOtXYje81dQswLQ
xalwZgasBo9UeR4I5Xz+b/ZYpxi3C3zNheDLYXOjoQe+sPKLB4QNDgnwv8zfSlHZk2CVMCjIhS7T
CbwBkuYQCYQQwqRAzI+bbMp7c/7OD/NCW1t/9b/HGwBnPmQXSEWMXxObuX9/jr7w5p1T9nzQ3oA0
A77QrYGfmHXlEDlBULtNfcMoTqOPjb+KfxFitc3aeLS1QrNp+FUvMg/MHEQmp6+McxupYj7R6ZFH
aag8kMTPhP5ac76qn+xVdDf1JtEAyHFijZ53Xn7qj01WTuqoteOc/XWrRhapwDSbHb6GoYokpb8k
JTfPdYtmMYg/xvS9ZlRB0NKbJ+R8rj4X+myvl79STczz+YCEQSp/ex8ZklB3aR8KdgsNAqhQnLbj
rWaXXcWnConDm23TLADSttY3GayD3niWDCevDGsh/d/3g+cIgcrr53UAtbOcJ7YA8cBKPk6R3ywm
cqYa1vGWoC2zHJuCibQq8tdl7wOhbXnAVv5nYE0PuIkQAVpZoscytDQmwKFoa8deBMqkuVDZcc07
l5B8L9WGSl2r/Z/oqyxUUsoHLb4OUu+R8jXT8H1BFhJeFp0JQ4fP9BtcfdB7dq6v91AZ+opzlwJ0
1iTjEuZ/tDzsf9Cavv9QRYYVoEpl0EFxOKN9R/MkRx0BZUixPlt2UssLtWzCUG24lA5Wfmo3dKIT
IEt9+n5BhTMCtpx+E3LlQm1a+ZDnpa0wLnkzZ5DkIDKWSBE7vTCQx1+ScM/VVdiqktXviWKUohPI
Sr5QeAGW+Z++OxjamsIqxf9t5EfBQSbRFfL4vot2DgktyWtrepeR6FkiDL4CMe99j2J/A8RSAdJU
BbrKMdSNs0C2jiSGHXa+uxXlo5gimXeb7BpNy+6SsAr//bOmlGHgsopq44bFREZ4R9C6GMQckwjc
meo+5fyef+qGp5z1tLIJNhZGDltpy1wN/W/3hCSWXLY6x2d+3kW2fc626PCpJu0vAHZNaCdid/Vc
Fya00RwZBA7BOWL/kBE654kxwWvvWou+uObD7+FXARube/WIZWTzsTj/4Q6Fh6G+l1ioUa2zyHOb
RsjWTsZTdcBwcX4GfHyXD8o44Pb1NwtYYZdGJmMNAjMLNMCZ66sK5rEgy1fSCpvxMxzy3ISKOWxd
Y1YtgR5u0L2dAXBb7jU8hKywSgkXpDSbzUthJwQ6R7veSuFxxrO2z2mgKwodpLiHX4jLxK1xcqOQ
pSLnOPR5Oxr8yJRnFK4gKRrtoYeQ2Aszt8P1J/kfTi8gUmTMayniGnHAVQFX84krJJ7sv87uyqXA
/ujgJOjocz6kUfkCBqf4RYGY7qv5eIrzwhVLdsL9Fbl1Q80iPTzdjn6cB3x67kvEc3x4r53n57M1
cedGQOH6V2rLm3UmNTBO6DYABMzr8YZWIs1k5/07u1/1/PCQ1MoSNpSDmwTMRxUIxW17+OpMD56R
rDLV7/fYfFT7K82qlaKaDC+7yxmgwyXZf4BrQaQpXX5nmdcdii70e8daMKy7GGsrJ2TVz9cbVlbq
fbCSFpLbm2mMVJrNHf5LRfdCIGG9cvH4svmO3ndnYazjpdLFgVSf+ScdR7Kf16v6HX3r1R3l1sYk
OguVJC1L8m47lY8SKfeC7tRgZXw/bXe5uLB/pOetUSjk+KDPCWnRVKsh0OPigbZ7o0uxwi2Ai9J+
JDK79X/P2Y3m6MZehjzIjJtgulVwCr4ofQt4/thWPgvGiXH21H2esjsyOjoqU+7oSPFHk47EaQhM
UMKIQVHzPyLdf5csq1qGW+gfAaU+3NW2jccP074NtXRdm48fUyG3DbACNWKSnIplyvivWLIDooh/
Qr1Amdo7K97IuTIXmHeCclx4cBCCRhLU6FbJzxhS5U+AOVQNvhFxOadhWrEmeXPSy5MTwN44YpXu
d5Oo77wUpgXIVFH5uv3HI4BqilieFOMgyoFtsCltRzM8R0QpuJpEuwcfwdxvtBYYGDHduTtHtn6V
JxZZ9PCCGl5eHl0eHqrJhp18HiV9nexp2G75NEuXs8Y4qa3W6mnfg3fI+t+T2+/sF7DlK8LMNLYk
FwrJ/ChY5KXD+A3k9DjYuuBZKHzrgpyzfOyIDoqt14OoCh7S5j7pWnGrnF/d+OERJJqe1XWYnffA
h7g1MO1qN1QGGhYaeV+dKziQvqf4+zGsAwGYVME+dpFmIBLCVPZiYB7PzOnsghHcKB7Oc33KXWQh
7Q4o5fgOBITG3hFgMWNA7iKhpQVvMnBisqjmLjwFMBOSfOcUel7K6UZMpmk36Cw81B8nYXpYlzfl
pBk8Kb5ZyteB1IUP2fRUU3ivrqhHB3cQl/3qPx9n1PT1PEUz/224NFCPCkiUmg2AMj7EzJ+IW/M9
iTkWnVCDMd76ZV7muGHN3CXmsya3wau7UK2tJu++gJJipW4UVZ02zv7nC96F3k3A0Kwkl0LdS2aX
Kr7k1qqEVyUZBjWLzetNASmbPRCk9Eg/AOln4bNzKdrtB1fzRbDvhXUMIVF96bwZmjfRAZ/qC0bK
/EVfXYvtMwxnOPPTCdQxL1aIj19e5Xxp0HlUaQavFsu6z2kXxF4zmYsLgrI30eV6s3hD85kcRiLf
SZiaVA5fGT9nxjOX23YWNL/73GzkdZkpTjEK2PUXk5i71UxIpVzVdbZ6a+NRpWqPxLTJuAdxDvBV
Df/Y44OfDtqLVu7vZTmWOq5hHrBQvez0mzwNnXpG5TYf2WiOKtUiaNInIF/rfAjrZUAn7c5TWIGr
d/tWRfaqF1EDuyt66xzKl/8ojUhKSQk0bmOBx5HWDVe21e4KBmZWi97HFOoPmno/svfJCRAgCZLY
95SAAfBvCWx1i5f5GYYoTC2HYTr7YYWrjFZrK1hIR34G0+KKQWxZWm9BF2dT8jzMWU5W1W8pAlSU
w2Sq7FbwttFN8i2lnGvS5UfcXSayFmgpss7qr+Zalqw9lkCqIakOMOvRCar//Ty2JFfeLxpQicCo
Unl55/+sWjHy0lVBRVAd6BbnW84I6VexZV5uFe7HBs51mFat/c33A465exwSzt2KabP4Oshdak8B
mJk2TNMqaqOVMcTVe+mfKDqAUfaPZs3kM+HcoYrcukQVY1psuL+H2nJPb9AZ0rixhLdk3yBKDeP7
XxMB7CDkZCwZdPtohafO64lTmYUmxyH4YLnflE1WXs6GhN9sjmacWhln1zL7TPi9TP57M7S/yzPC
xjdS8liHPF6tHYjTn9UHrE4kOvwtsLFse7XE0CRlVf9MZjlzpmlz4nBGR6qVI/rqsQ5FYZf4sABv
enUpLQ0RGQaMPo+Upyd8Rde40L7VihAlvL2gjeHekMWOwvrz0khJI9/YTDy+aa2vopVObbhU3qyB
LbRJZ0oGrHNtFtMfF+Ew+LvZBQSqoOaowLXH1RxpgeGFxWpmb19gjN3R0ogvm0gkTl+K5fZLwrWL
Xd0UY2bKwLTXTBkHe/4nUwFrVbS7m6/1FIIjn+85EOTZjpvAdXr9023JZihxSfsO8V1cyPmOjjXg
i8wC5NPQphKel8DH2Yb8xhkLyt/ui34TJhR6bkY7KaNx/Rzw+Hcvc1yeHUrdhWdqtiuyVJ+sXujc
tAzu8/+woMB4zkEB2NA7KjuUX9Yl1UE/3Mm+JYgX3J2bGy+Rnw3OxqQjDnWARp1UWHOaMLcxeO3a
LbN/df7F5f6uI1/n4ExPskjMTQryDB8BP7Ve1UDT6fbkra6M6KyA4vTOvoM7zYK5z3Wge2OArEUD
TYlqWRSHVXGSgog1Fs3XNG8pqKCMdNcYhmKHKqWdUTeAqDUB8de4k5VrOu9Z4Q5Qp76CuNBPRMOI
rcBvhIdKnfIeODrBVdFVhPVJEs2Bpz/mns6vFj4YkZJ8rbkmXRe3jB7uTY/hJtoBhPHNQqRJTdeb
H9ydKsGhjdbE8v6gR7YMcRl7Fh8H5uq7U8r2Uu/9G1yai/eIBuLZ+uJcZr+2bLAW/itY8t4vyc+j
7gzgkoK3jo8ZQzwXYbkwSeuUQsjr1ExMHeKNWGAyVPqBjLki4XUz9Cn4N5XfzSSqX51TcJy7fw3F
Xo78gi9iUP2bY4lGKptuV4nzYXqu+cRuHtDhqHQv26mjGWNhctzLp5Sxm3khyd76SpKqeAkc5y7W
xMhLFCY1YSuh1NQ7szJDt2aWH3Z8iRZkmtyhD/8zCvcQkOrJOIlVI5of1xvHUZBh6qW9jMFQyATn
i27rv2zkbN88N5bzrIqGo9zrjlgv2K6VUixqS6eBTDWik17GbHg9dYPgcYSeaCROBKivdbyP1mEt
EuGc9POdiHaTBgnNT7wuf0MVMuJpcwid0im8RsrlkWsOVcccUFdx6f7uHwKtPZscoluvOz1p4BJ8
Cmp7/POzKEbvvuomPHm8rIEb++nM3EZsp+UagNGSFHItCjzVjlkBxeDrMZzgHyjvs7VHAth+V6Ee
JJVmK+djkakW6a78oBpE0xsmvunwe5M7W1xrzLnUJ7xKWn1gof12DO0FILbs9/vMLn/Tvb+eVfog
guGRfBMlz7/tHHHX2VJku8MrnTVsUvk8jBIN9hrutnLt5Vfu/ltyGcnF/rhvYwVGGcjJIKiSC//H
SgDsSHKLRd140xpSSPLAEKRmZHEj7WtVrEE2o4EN/T9gdXykUKg4rW0tuRNs4LySne84JdumarDL
Ln3x3PH1KfVyCtRaBFTHh90gXX3nuzwJIbF/JGFlCE5UuArR6kHdrQ/623JREYbLw+6PV76qGLDC
/xukmeoNCbvLYxKaa3pm0pePKThws2Md75nIXRiR8SAUAtj5ASdoezs4DPxV5JAfJSexTiO8ELaV
lzDu6zzo6WG6iyrfLLbVFVLcIL5Z4t6Ls+4JQeSP/1b4m+c4ySCEEw/Ga9pMJqTMP1/MQf1PxGGn
geXKsbv30tnE0aHL3rbtOUTIBFk+UToopbQt+AEdb7VzIlg6FBb+PkBpin2e7RZriW6fbOq+Vm/2
qDgPjT4DLPX9esqLofidrEvSUDIkuGkSyoZmrdzfNh2xV8fe1gAyn7qmwUTrHxnKV4+gaRAURIrL
M804vfVh4EeoavHpkpsQ+jG7me/nupo4/LrWrCqP9zj31FRIAUSdcJsJh5BldLHQU66n5WbPpvrQ
KQ9DO7Vt3SQy3lFsNsADLYHlP+ekHeOzPqcB2DPp+xP/oXn7S9fETmQnswe/l4MEoXZx9mIYZzDs
gAK08p3dwNsC8p7B9fRzGg77uc2tUgeOf1KTRRZMfxY5n+2Ls2sRm1oy1J1XZQZRzJs8dheuL3Qi
qBs7LlZprPt85a3ZTzTCJuxO29f2KEaCh2kpAesINiRXfeRIdlls/IjCVlWE4Ftl/LcVcRFkRWuI
eQlInc9+N1GlJs1Hgr75Rwb+HAkSB323w/PsPSBIkINq1GChywndXgHC02pQRGH3HL02T5zgtnui
Vb2cYpGxuoDMdxUtdag/bEwZlVZZtG+S5GeVzLAjpkss+/AuvI7x+fPXq6hZPx0XIIZq2p4IGobe
bkwZLUKKb0G5W+5Pw7/5pc1efMGxM5aYNqRHCmzOe3alO4vAyu+E6CLomLhDbrrtDuEdIoyTBOFR
iSlGTxx7VNMI67n8dV+BQRHkwi9l+hrFjoM7fh1Kkfi+RmhTgGqzbcMRj6n8IGx9LZoIiidpBQqR
5NBvtaVUkfkaCe/lFilVueeHuzvNkEvybXlvUJWo7FPWrP8zkJqQ+rtigydaLBIeDYXHg+a4SMjX
rq8MUe1kwBfQHQGy6eRMZ7EVUVc9R+qPrcLNqGLyywWZbE7aub0Tt/JBM6mkbKluVGVaz8HAHKi6
CYCjPbzO5UMsgBa5VY39vsq2LYqHTwpnSTBC7LbhplM5LppbpHeYKcPyr3VcHEEjblYfWyBtykIR
mJw1Q4hP/vRozWW8dYupc1jPG8Q0ewOOJlpK9ARrxLq7FPdYtLwQdYPbj2JmpWUBZjl8ENcwXREZ
mJGFg2sZboQf0lhTA0+AclqMJQ8x1Vg+O3mPIBevLCfZj3SiQkhnq3Igff1OULxu2TV5o+7PZs9M
gbKo+tWirYNFGmDe0SbiAyAD0dY0C5gtEqmIAAhAmHLpbd8eMllYBr77RZpHB8n+9uFdZYt/RGnm
IeGhFj+HDdoe3/00fjHoYcVlNz3TYuKXzr6mhmeuHlq2yDFrrxZLYN/qWIxfjZicUqNj3nM3mpMu
+dfY4klEOJGiecJihILhqjY2INjiL0IhKDhLwIv+M7QRwy+NF+m4y8dPsLTyId6/mcZYt1MKgsrg
A1HgYYnzf3ePZkl1dtpiy1G57f+hIwh5A8QcgZupgI07JtccU1HprBLEJ0LcfpKD4DxVO74raU3n
LWbDPOzA4pOV0RQHQoZ/sBrunYHXY0UBNbPfihlAad46PhS4qi0TCHJZ3B+EmdEKi9MfyDO0Zkqd
VkZDfmCb7iireyWO0hka2Ic2J5XdayoDfsleD89CAZPuZJ1WNveSAnVcJNlvZzpsAuEOeTQ7e/ri
AMTx4XLZuKKBpRPfQL/4k441AN+Dwhe78+rGiMmR1tx0wZQrZcUBZrZMQnHN43FWhfIwtmDp98Sh
rVSalJUoPwarkacUzRhBg373yp/r+FaCfGKR4OHSDJtyGz8DV0yaWu1P7jGY/voECnz3qQqqNLVm
0QY7npKcQtitlnMoV1O4bO6Rmno7GN7y1pkuXiRdfrkAAr53cSI5I2e5F4MKMfOITjXi7/7c0aKT
DEe8t01o6O3zObd5IP9yDXeigLyu/5vax7ZNb2BETNfcAF2OhPgkmHvDqFCmYbFL3PelKI6/5q5x
Spx/AvNUkRcPRzqSaw9+ajDXZVcZXu4G6KfPGsTl6TXQn7VqrobBaiWxhshbg1OZFk742z60CsFA
mgpIoHS4a4nubdudVukWHNhD9x/eE1F+dhWb3FmmMuzaNs0rinfGOM3p2tik3eudXYNLTnCBrib6
q+h1a3+GXnj+E11fhTxZ0T7TX+BU1ilXcp7ovR9FSELBS88Nb5zPRYxucZd35IYv2dyHxzhQ5HOw
BiFuUfD0GCTT/TMNDStcyMF7fr231TLfQ89daXMXIevcufflkuvv1SsAMvsVL+dSlq7b1XKerQdh
vgng+pRtLOQj6FXWTxdHFdZnvN+cAxNuM2R6xao8LBOtlzmnno1sLD003Lsmhp6tPGKSD8a411yf
8CypMGYsWrlgbMSv5b/BNFPNWvHOo004ysCsA922rD9fHv2xc61dXG+jEXqLOqR/8QxALHZ4Hof8
PgrU6ig89lj9xjMMXTBVFISmBeB1oxZvtW3Fc07IVC7EyNXTRqR3y/1UBITjPxN5JO7pXt84L42V
QtdwFT6e5GSaE3VEwJLZlbFPkrmad9rGRKh9V0Zzp6CUv10LD0DtsQxpq3BzSD3kBaxl1/Q6Xggp
5yYSS3ZvJOV4vI20IoL9s9RaY07jACGODK32QBPr0xisWZPCdf7DJI2H80r7hdi6v9EUTK5kcyR6
diME8Nhw+n+Ggy8YGJZT3w4kuHr7/EOCIe6+9nsv5dGvVuYbJc4ywL3Itd60uNJjzKKFqhZDuZoG
gcoUcgwdNS2IddrKke7Hxfb8cLdOsjqVt6uq+BeyoN6O3b3c5Z0/l8ffsL/mccvM8ukc9nQ0ixxj
5hiAZhlui4G3Qyie9Znz5m0uy8C5CNpGkZdjbKYKubzv23sgzJElTWc2h/EUtSXurdXz5tnnNSWT
8jIywDq0dIZfA+L/XaQCYf6xVz9OmrF7JDcs1oA5VemOzyIPjccLvP+HicPean4gCehHUxv2X02m
QD+5lqWGxdaLkPYukUa3cGuov4TlJS0/ZfhRxvY0qzoScAmiHkBqWgcEHje+oGT7Y8941SbJRBOH
8IRsSLe5KB4wbxNODBH45ymjDWv4EBciS3hXCUiNsAoeCrvwNy+7MzNBv6cYEnX/wAyEUow3NmT4
8hO/beP6rZ9Y2lVP/Bm4DfI//t2T94n0abH+tfm7sXFhZhbwT/RRHhlehbbTTNGM6n0fM7JvWoH0
TEtDxOQX5DgQKkRkzc2ZM5mJUfeeXtZdJvEyTR7pSlWzt1L+a15gwP+kRsEW+ZcBz5liFJocHeyS
yyvVByOmYHlNzbnJ3kGU8wdJetovt6/RtPkhedf+CEkTMeLj08/2LnSoa4xVjbPID/x7x9CYeVFC
2Y3yxNIm94Qr8ol+f/So259g+rmF5vJ1iQndwqhSWGkjPfrNIeTMoICvdFyduSL3yT36i5a1bGZo
TYk6At3Z4OvE8uKjX1R0a+L+UDNyVhcR3QSlaR70RHy6vkl8dZadcXX5/ZcyaTAotAIN6ARSHnbs
MWzPqxE43/lXeCBQtrWh7FnVm9v5Mb4XXoV5gLCNn52Clb9QRg5ATdGgADto75mYlXqX8T2i1xR6
vU1vMCr1rSRwfmtaLVbWoX/zeOGHpaYk9tAxLOSsejZvi3vONNw8+A6MZGvFRpU3iG+XGbtv/LfC
9AMg4ba3WLNssWrdnj4Nqq93BXvyyx/3Xw34+cNDgYQK2rXBjEAmEwxiFZuFU0x9SUuEob1CK57U
WbnVuOBajTQQFDKOVnO2pL0ZG7S7wTGBSVc42J/Auh6qtZlxEZTmYvGSiuyzJwP0M2BDqjsuZpg3
VxAclZP+DAJj1F6j0S6uVzuzmIcJGTsRLOmz7yK2x25aTbkaKPDEgiTaWQ0l8USrVqn067QdftCT
UiGncCVYsdmlUOvcCHPWoFPE7UBHGR2HtJeqs/IBMCHnWff5Rq8p9SiH4/c/UodPyp3bWpgBtVeb
VTFS0qXsZrIyceWT7c06/GqvPWT3fF7a+gxJGGOF0IbXc2VN+EkBLFkfuRNQKcIMlgcpciMi3XaP
0FXd7MGLvhZsNUDG7i9OvQz1+lHvmR/Pgp6MFb/l1/zxduk63jDtKUGYCyjaW+IkVkKzYYYdNrQZ
O6MygzdFwV96sBc052NX7B3zMcnFvwyIvQ2aHWS1GM2pJuly8n5fouqgjN8un1jHxaQ4GIcLdGaM
S7pZqE+P1X0+O0OM2NAILLw9ByMoNYFEyY9X8AbKtEdBKWx1Ffoya7z7h5JfWw0RY0RE9/L+wOcA
TqJY4g/rvhdNXstGIs4rxsaYZMm3VYE90ckYj4GTUvmHuambI+I25xtH7+502rqlT/nCdxKQbTJ7
JyckBSpVkElTpkefk/LDDhitrHA23vWFAXMgmZgNCM+iii5vIWuS2ndhtCElKalxp0qOTjXgLfpy
/7uQlDAUT4Y9gkU61JlwENOyByyDJIYVSi0xdAYGF3v8K5z01NwMqK/xwfkxxej2GdYkX1K+v1Zl
/dMnR2g8kvgAA/ig/Pvq3do9bGcTegdz76IfcHVk4q/jOehmAX7NfX6snWYqIBjwY2EDwHeieEUS
byoBobnLEWJXndxikq/nh5F+uj/7ShVZpqUe5hwwxMuhwYvmK/NG2O4mb4IV95xJ3FCioiSpSrFc
gv4yQ5IvOZfhHXPM0OqViYjXaCE5vVoCoqrbulUVeR+9xuzlIc+8/+qsIDYhKgmmaE6Cyx6fimZ5
fy85XlKb9CiyRBrdeuVeAUUCe/1sxT8XTzWLw5JQzlv9OfUIaQD922LkVFq7ltEsY9dz1wCXI9iF
NXLupci3cBuXSkWatAnqhHvj7hehPLTTUnQG/jnaF2AP56LWCfpmillSV3zA6UuGr75oIpF1hdUc
wEz9S+8dN47anumMriy8iq5aIaT3P/g9+z2HyVtwTzJ9i6RDTBC/+DVGrQq4msRJjaOFTC6qqTcg
MOQMrTowy3UyTlZmlvSkWKWH9gDpM/3bl20GXKt775T7L8ydxTRHiLeT/gyhVSdxI6PJGD0NjvFc
5ByBYGww2MxpybWh9u9WmGICsSqpkKFtw8mhLsKUV2Ld3hfR3ndXFLne9JZdLAF6tpd5HqVPckZ3
oF5+PuM9ea49N750jdVnaRxiOgAr4dS4P5J4DhmigZ4JOi155pgRCdJkwg7gTRHdsWTdr1S3vaR/
ImSIofSYHZXZKmDzSt5TvsekRkzHC2IMrjfDhQConoH3QUAXPMNrP9liXRQA3SGUja0UNuirD6Om
UXriMNKx0gDMwToqJaETu+M1FrvIAZxTjcWv98m+L1OQgKmn76uSFOtiMJj2yLMgxPNd37jxC144
zxO2dWB3Nmw4zDPVIMzJw5RkcGSJkL55PKCvPjqGn6TsYsw82zqKzpGzlKXzwuSD3eNoVAnQWv0E
yLMsWVSPWDAtIU55IFNUZSLrn6aj8afpckMrkH/fK7xqy9/a8/5rGZCWzIw2JaOiBvK8KUgvoVT0
vPPIsrkkaCDyefJmo46nJVQ8vOdWbfg+0uOmsyGZj5K9UePpDLEWqm5KfkkqrnFf0fhUp/b2UO29
mJnUBcB03mpVBBWnfnpkWSzJWTwM80VzOOLCtnS3dpZGdGOVRWuoLSe0zlvcMly5YfDSQ0VF7E+J
Y6/6G8lMOGxepzhdjnQVA9q47JcUhIL88CdCVSJvKg4nVID/4o8DASZ6sfGuV8GXGAK0RrPob9Zb
HS+JbyqbbABzfVPUcLxoVHG71ecP/0rbfLDxg32m4pOQ33jLzRh8DtzaiX3Hjg2E0M/5Kh3iip/4
/mvQaA/Fz3otzYn81SsG5Xe91P3rILOlJYr6cgiMPoU6RNQAFZFRHmdeWuiRjlus7UKTh9Lw3M4y
w3J8EU5erWTiGEqjyJbQIx2dEsI0nGliszODddM6HKQ0mmLzJU69RpA29DRO4vqyotDdDtSqZDBp
C67xvzcIOKUaJrSDf8OXfGqqZoeWwHfw4AThQszFZDZhkXxVV9Ac+ulnWIDkRQbsCKFW0536XgYO
T/uHRtlM/Ve3eBo9s3rQvD5F6orFyZmzFDqPmTOw89wERuRDZtVRZBjZ5sygnK6EgrYkJ425+KdT
CU/8Lq5edQogWklvHMDCUOlbrWiAT6OGw+pR6vM5ago92B7P9Zbr6PG1VA2wEIZ7zsrksHOLCL6U
wx4+Xvi6UJ7zWq6G5ryTMPsIZeIOxiLUYFA3FDeXBpspDLuu2uVjDyL+QOJqjUfSMz21Ra1vGXPG
qCjPZlMsfcCaGSJLw4yIF+fdvzbpJOFTv/Aq8yml9ffHdpHd39IjyUA4jSKP31/urOeEt53VFdoS
dYSputKIGXmsNSLdPCcCR5Vdle2MWpREmJprW1XaiwWgsp3dCd9sNhMlmfy4NADCEkdVtRYcd6C0
m7f7uEEXE2v1GwL8/JI4g5LgjodSFReKkz4ah5BK67nLkY/2Zu4U2CPGpNDLN3OKyvRwdI82r+5H
oH/ZQ3y0caHOtZ/GHEYh6haD4dhWDlSlc3rTuRVSv7xUiPgFriMrm746Vma0XLePa1rivL8dRlyX
jKtsXGC7wMyskKUvA/8Zs2v//JBP0Gr2/TsHU6DFdTU6uVl7h8PSaJM2AqHn0s987RtV1ioFjkVM
OQgWjqVMEaddpFmgpxhfbiFSK3qAOnzcpRuwGhvr3AxZ4WsRqGDTZId1HAhDRSU126Uaf56cUlsZ
kOZ/Xdo0kHlObRGgeu80A+q/Ejfa7bV39R0S6vzJ+pZVYeMRfc+Y+Y06jFA7sZ1QKGcuESnHLf3t
Zfgs6FGwGDHwm+px9cwk1mADI9ixnIEoz0OLElKbDxR5x1plbO7/5l9AIKhn+j0Vhx2KDNL3eusk
gflU8yqP9tvvVmj3Gx4E3ac2l6RGejI1J6Ypcdm/gIRee5NdIs5uQuQppj1JtnlkWtTUiLao6mw/
zHUOPInHZvFBPJQ20osJ6+QrAKLt5QXF0gLHIuy328XEvLTNUmrEjbQ5mzTBspcVKaH3xo40wKlj
efsHbK4KQANska8mfH4kwzWEziUqcFV2XnuU0YCueYHJmhXJeR9VmQBIlPjn6I9YRE+XBjC61/fA
eJG2caL+WpdLfi788bePJ0tiioEsahUw3gLNo9b+yDAHkw5wAHdKNf26SuhWpVCdw/ApnXWnCL/w
FWq4dBQyGZyL4aLXPBy/S0CChc8JybuGUlNmMpdaWwQyQwlfmK7XZ6mdTLDR8da0h+XlyH2nKjFt
JIxXWApnaPlGolYDNA9bNA98kNZ5SH2QWrMnusbaxTy1JAtxGcOY7Tuwg/bRtrqZis4ORmAvlYgR
iVJGJZDS0CHGXyqCGggVFq0wPanq3BaDnQcA7Yk0GkgUntOz1twgsNIRniVMHEbdQIocRYJmyxOr
RRIQiRjeMctSotpTOlDDtjjUBJrRN1UbIgD1Im4aWSqT52ztdeDBA3hn0qxwn0PDMKoQ0kGnUUEf
4dlOenRDCDd6+/bCH//39ESAanwAXAHHndPSElnWiso+x6xNjfSPa7HxPC4HkhDQyvL1KDBQanzz
3ReVizyP/MhASphKhZKHwQ70hlPhZHAtsSKM78Nc5q0ovPRPDLHUpS+JrGMpTg2HSQcI8zBE5O2X
Aj5za1Mw7grUlQRiq3d1uvx4j2vslr1rvB6KXYvfVlkRJheYa5fqhX8lH2w+vRvVOvB8+hQ66SYT
mUYRZYFOXJGJm8sI5y5Xdt/DSArUjg6zTaoA5/XOJY4Vr/8gyEN196SynCZ+GgQbObOylxdHMkt4
A7OC8/2b+VZRPD4k8iuddOOkehyg9XYVQ21FEZIs16/KxFnm2U+RpZaP26M+zq8T4jAteyVBcTMb
SH+YviOIG3qvSEmvXo2bx+WioUJ6NUJVd6Q+uqW1B7mF+/xyH0+4TMc8U3ouHH7SL6KS38+vVFof
UkglBfT13qlRiFGbk7SPae4CnKIeIRfFhRMZ68P/SeZAqOq6nJHXJzrN7pKcqAZVpymICZByKHaS
c2UrmNzL3eu73fK1R5m5VzbhF8ns/ZEceNGNspcsYo3+b5zmy01WlkITQeKZ5Stf8T6bemAd2a9W
Q6HBKiMEzwKM99SxKyGALBFoe932/ADTxmP6EAp/OD2+cvwnuURyhcpnP7Y1tkpvyZjp6sqQEMBO
4zvz58m79wDFdjRFrd12KE3mAA1nXPGR9mK6rBOt/IYVXDXL4LbH+UrAgVOhEq86gZSB8fv1b+Sd
xqtHI8pqrVv8OqG+akhfrxQmdfs/RNI0vuCmxzjEXOXKYgNw1P7ubr3320MwdR1gF46GdT4c84jC
F0uAtK3zflAmQ5buvApKyINC5P2R20HoeKZBFpkKp0K9SqvjYJol0yH5HSO7z6AX+viHy8d7hmqZ
IgQ7nwqbnwOvnk8GJ/Tc6vlOGkMy31M6ZZCOeaYsIa6sR1j/FxLG920/PS3rgrqyh8Z8AIhWLLVo
BHN10Mmt+N8ZOtgpxGnpdB0RiEhGccW7ytO2Sl9zQ/xfFQoEz4tKD4V88dhTvmR+GWwfLJFvaN1N
9C2TPCJ9apE0MYqPkOHna+pw4y5McKKUkImt3iWmNFvMdcPXs8XblPLu09X2fqhoNSaI9zkjdBal
sk2yqcQue1E46uu7Jo9QNo7c2YojZb9dMSq+6oGi46/A5rjTyU3Iwr+R+YJNcT3gUzigFT8eII3H
E20+1WW5e7h2GxXbtxumn7H9SbxhvOQk0FXwMBg4mkySYFQINAmJkvFh2Xr7e2LQyxTlrpXq2vrZ
5/UNQx0qbVldy2+gecEHD/Wm0uh4+s+lT2nePFVqrZKjZ2ju2EUb6ATZczQakwn3rtXjBtJX8dQ4
9WC/BtujQKe3zrIM3pBfjzBQPBkJUei1KRoHOBdUTrnqUA4WfWy2t/58ujXEEN3twTRQYkczu9sJ
CYX0AG8brnlsljzIAvHnvM6U54bbqY/bwE2XkhcR+5yJef2ag18QoBdrxz97QFaVECb77bgArdXQ
9oykFy+h8ZV8fjQstsEmCwD0THr7JoaPE/HOcSXSHMCdW3wPCoZbyIZteRtdc63sTu0dCt7j8zIG
iYoLIkIhutAEZC6DoYVwLsqjzWI0v73E7JTPnUTrpjkHICeq79APYswQhjE1IcG8XIlQiHiK0lZT
PxC5mvBK0WuWTKObhYij+8XcV1DLmwdEDq/tYir/4fVNpdDC7vqqvO9e4RvffmMKSPpQOImEsVRf
vlX8KkW+/ZU9t0mELjML8xuDOqSgbczucEJk7f5WoaCDA47LZw0WAgVuspnkq89MvdPshFoGpATI
3zE+QSMLnA+daSxgPppU3fECVVMDEG0tCQYfIZZENDeMfgbr9sFsnPShio68qpbbOjV6qpkXl5st
50yfaYSICRwEIxbE4ZZ6K7n4ESbMJv/vOnnyR9XvjcHLMjQfEzlV8XpYgYBk6dipLxZ4qtNv2o3Q
+6qfE2PeXzg5MCAuUlZ/T9UACZXPnK9xFhG25YThn7Es1LxpvFXWQCnTu4YjifFZ5tSyJs6PGgm4
2t9DEL9OxigsUFWcWHFJgYAtpDVun07LO/iMbDczKIpHcYhg3dPbQfIYC5y46W/tNgFa2F1TVSCT
R4BCfPavmoGrAgcbSkN3xhdQf76IBTedCZ4+InxY2R50l40+VFySUqF9RXl/4mfn6FxetfpwvpA8
BSmR8ZldyC5ZzgXPlwyvxL99/XIVGCCXB4mjmNX8H084rdmqcB7O1PHvQ1BW75BiRpvrgEPm27wZ
z5ZLvFVpPesZJXcyt0h50PzQ5A9AtZ/lBbsIZuyIbi63Bua9pIO7ZpdPjzbib7E45vya3nHlyXUM
8b5O9Pz4LrRfshu8CY4b+rLEXfG+RuZzYqMBDYIr3/TCpjqSWuw+JhHGl73WdXESPcpsmTmGbnxv
RMz7KWYljJtQQt6DbEyNfMcHofk6Vur+C+l3LCQ1Tmkxna7g2tTEmIkC1VrPa2TA7sDhu23E1x//
EI/inxSjZ1IENbEaigYdfqkxsBl64H1H6QEMInODB44IgdjiCu5S1d9WDKTBJAB6OxYAT/K0dJpw
OzGo7FZdSrPqslV8AATeynrPDUUzy12ydPHniw4qdQsJeagOVp4QCEnZmT+DJngSwLt42xwm/p9i
IsCZTl95D6Q2+kJW3Zw1qR8OOwkYqP5Y0NWXKRYomM8rA5gUBsIOgvYn7W/xlJzYx/MKagTtkxxD
dBAQAykAh09Dl/SYxJ1R67k+JhpyooG+yuiNZSEpomskuBm+lf62s+li21EakB5LZ7igJzFcmbFH
/US3qytF+ns+C2oJvO0DcRbTtUI8J3h+yKnvo0qUyL0zefFooJraUMJElcbagRqdkaYG8MkbGhgR
wHm9URPHGXZamQB1v/v2Yb6/pF5Q6buOhEQKZqqshUUBgvB3KqMLBkUctb3UoAhTAoTAFSqXRjVV
wHTthuWXiBRDwZGIOKMYDxyZEgY21Tc4sL+7BppZFLsdsB/d2rgIp38kHJLA3fHS2huJfYSlve4f
zB3iqW2Poi7ddwUYZhT37ukoEsl1mL2twRAYgORxxME02h0IIRSxObb77MvC9PDoB0Oz31wbuN5u
Tknx/ALgqDOnYrIpisEsIb6l1LZu5jeGKtXL/6V/31AThlonAohxxFqidf3M6USPuC0LH5YC9QK6
JRTF2gkemhYv4pLKdz+hs5jMVDm4jIa1fOL3WqeZ6vLAYl4hvWEQJWR8XWgqn6EBCms0wj4i3z5m
wp044p8PMmg3qkROgW5qnR8KB0AcK7yp+0gK+7lQyK/Ljb48HBtDW+W3eZnmsqps0A2/J7oots1D
7Q2VZZ8MGjgZYPU6i4IT0PdEv/DJAaWnx5tqIg9+G2GfQUIsh+OTX37WVexeWJO4xWm1nyt8YBl/
uBOAHdnU4Apy5yHNpxln/qInJ8aJ4XQOhQiqk4gaykQ58D8ZKCaXgoP7CNAw5dCJuoiZLno3wKMi
tVcTBCQjwNWrCvC9xpSLraScAcsLsvIQW376tUwPTxAo5vQPJIFarx1H5OpRfg/mCjFMb1+aKyji
hYcRGf3HDc21xAqDSjRDdEWDoNiopo+F5ZTB27SQ6i76DcbK43cTMQ+H0N1q4laXyK7WWByjSqAT
FW0L+cStxOtUJDEcG665b0mDZGYjSuMffJm87zdYYsdcA9jcVi3S5JjZ78ztflBuRpyaXerew+ek
BoY9KMuFlkwkGTn/MZGPu3dzH7Jo2SVbuVetzsmzR5cA/ITsOlBB8bU/CTG1rGglYsnKt9J6/rcR
+EoUnZMhLYjD1L61KxjsaS+jiWYUa+sfsIoARtG1G7U4c6gxeoJiaUv0wVJecwBPghWtV+ICWCRM
Keqwzl2NqZK97QrDHl/VLonEnKAsGV7GGjSZmB2CTa02reEw+LNmCYHIiRfR6hZCTZ+DWCziN9Ue
VYhKG+zNmvm3budR3C8HUNgxEaAKUOh/qs+tzo4kEokuxoFL6EbviC0WqH1wbR9RDXkLGAvLyU/O
DGXvNKDUGz2ZZxJWd/9CuTD7Obu8scuDWAawZunpiEAT4DgOvigYcsREyJkWEFo+6y7K4HJfXSf4
iR0VY4lvjPwzqCIS+n55a+JwnZ0+bMyeC/PnBhkEKbvfwkH6nnbop9OWg86URz3/0h0X6j8ivNnB
g3Vw29Bqm2f6XoFGkgZqVmaXNleD3sYPtolT597u8tOD/tn5l2SNisGlwT8f0eanB1ijSoV89FDQ
FcmtJVtA/pPOrAhlZjJSSvm2s1cqywZN6jMMqNBVygBLulPul/XBXPrzRuu4O7X8BzVR+WFC3deR
DTSGcHyl2XlW2osxlAdAOQKlmXpdHK7LtF2tSfYFgb9+3AzM0SzugvU3lUbpXWRNwwqY/tQX2UkR
y2sySFaaBwskbEiKA2B2ZxWfpl7PFzKQdPHNMvUSvfkIemfjYsRkDwGcQpUtBpA5wTY8bLTeY9jw
w4o+vjfy2Y4n6RzNNrM60DDPlSnoJSnX+tCWFcpO7mcgvUuxmCG1nUcN2B28GnDBZ/7lqNMOEa7n
iLafwJKMjiLFdKYfMc90PwDz8LYiq9QpFW0QlhzLXgiljeYSFmt1GMqt/HAPMofAYqPH1jgziBRD
3JImgoPyQS7ktlXOQZihlxMYdUtZKKRGjoBX0Kj03jV4q+FeNEdPaMcup6+lN7XRegQWItUL8jvc
U5fZRDA+QlyD1nmgUNykZqk+iZh2/xKilTCkKgeEdhBvwSU2sgEiFBpwkI6tii4IACeHlR/2E1qh
VMhTHwdO2W7mxLXkRW3pJJNNnNroOMUhJyUCZR7Z7QjzfEP12wZgeqBarPeUI3q4eFNWT4BkLhxI
0WIPLRqdut9VkcfNZFhhwNFzVCueEEFfTrS6+b8F2dGBd9sKDIM1gMwWOBwO8jH5RGQcjChC1FA5
7UJbJlIHgSIzkqpPcFbxmRQKO1jetTjrs73dyo4fowEbngX7gJuCnDDLLjnDpax4XfgVBf+0PyEA
It2gLwpVBg==
`protect end_protected
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dsub_3_full_dsp_64/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 20 | 30077 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
N0hMcXbI5hCFMXvbzZaWNMXky7Cb78UlPrOh26mC4IyomLPXkDt4pohvBi74RwhMjj/Bp6A1/EjU
BW4AL9d6yw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
O4cgU289ETKimPPpC1lQoWfngvpNmR5tUZAEw+00K8UK2gEeqXn1hb3g7AZENGEwMii7hns4XQy8
DXQ5xw0Yp1Lt5kPvabj5mKM1bMdX8dvR9NHP3g1Qjd7okAVBl07/JG0NTnpHDOfWPgdIKiG5gomz
/inOtmJ9dyw3SQwornQ=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
DU+IJVy0UCp9Ru4O1AHH4hAsURQvG4KWjfdJuBdXBn/Aw7vf76lLrDggWEsh/tDsD2w8gcTI1KZj
gte8Qz0RBjJA/tV/Q7C3IGP9sKs04WbpHeToWiLkJhGVSOi1cfBwcXqun7kk3rw8tbtRvnn4LLnQ
VVSnOUM0P3u3t9b+354=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VU2OWBPAFdMWY9YsdLW9vHBQultKfSyqJgSm8GFxf210g4AV7503RY1sTzcwbpKduWx2mEapVrlR
2+Drhdzv1Rts/cH1vI36ZrlUVzIXAPfly2Vw/ZI3vZ8ecksIx4K68q0S13FJLdHLryPXLuFGokYw
gCOZnAxTuOQQMCgsJA0iDJVXFdmLXzqwRYBXguqf1r+OMVPXs57gcwlgVB8r2wrtRxBvH0uRcmEd
9XDbIcnUXETCLhyRgVVpblWBh8bZbcQBY/zZZ/sbyAPD6J7Rp8CEPhLVVCsK4EjNey5PsDgo/izg
h4bUKLC5eF2W7tVckgp7jyOfw3DgIr/wn7RxeQ==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
V2G0fgDEE2OFe05Cx8OR1KsgdINzVEXBIBadpSnPXIoTc7xRwAe4/VP6V+6MXz0QrLZuQHVAj7G3
9F/ijf7v4vM07B7zCCzqKWXPOd8bPZE51/A2H7Mt+ilGqjbh/VKLmxGs4hilsENWISKVXeBdKnPY
gj2HGvaphMJpBpJwjPAKBmbUyTX5Sd9nNIMzcSRJNulwiaiEOrABFlrZOI+c7bZY5sHmVeOtg9CQ
vhwpJiZDt2xEUYZdJ+nAzC0+NS9jg6KFWoyyUeNOwHZC9//fhh1MCUzJ0nZg2R4hBpRaxLZstp3w
PM0at5MBtCkDuhRItVUmq9A0HtCUCEmB412P1w==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RN/6I+vbSUSbgQKZutSOM516q9s9JryaK6V/qqxo3gcYd+gU9W/srRAx8TWXTu0WbgzNnJ4y7Myb
hqdFZXcfJ/PxMgXPrrBTM9dc9q6Om0xxWrgSNxYalV3KY2vgAYOZai6mnccqhDfT+ZicibnnsYmh
yf5l9IBMwTbxQ9cpGytJTrr0jtjFG8izeH9CEj3vxYZQ4tA0TFJhsFvQhk2xXEnWnEBhTQbSX/B3
CADhGzXitOUqpBt3ylEkYkNM5wRAzze9LtBQhOCFWc4AJq4+3/P22qqco2g+VSDFNt7Sbc/BGwyj
q/3tdC0FZkEZB5DXnSDvgc9OVq2Fggic0aDyNw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
0lfuWTRLbdGpP+bt43o7Y3baOR3u7fPK0pBLqY7uP0pQ+2ht0P208f6mMmjAZkVFJU5i9ZpW1tkF
wD5qhRjJ/mff1za19WGTM8NEjj3Lgv2vtZrOQlSeCSfLEOAT7NsfQ4kQqqhmT1zaHkk89YCN8a9q
9xPGyMCXJGJSQ2huwnzDsHOnhWHlWL/ilzzMT7dDXnOUeGPNVal/ZBe72iYJj4f5eoRHew9SvI0S
Ut2Q3RHzpI/teRWNAdgVt15pdsyvyo9uqAtiHOlP5A7uqdndV94bWqKkoWPHzcYQJvuE59QFQ1WE
cr6/pK1peH4vFlM8W2tuxlyW6OcL51xzLPEmg4W+8TkWa9OFYdBlsYbUHYOc3tMeeOtnR5C2WgJN
uxU0Mo1Pdosa0/c7ja8j39ols+/uBkhEYy8hbWXRUa7dOAQ3PE920SjzPMeGxb1BnlgMCvr/m4r9
Ubn/TP99CteWMzrL6ZpVoWUIoukbZMgqMSfJHi1YJqkDs6TFjJsfUhzmW581OYiW1j3C3OYLCLCK
oBksaAsNUUcBviHK9jSJBuZ30Pz904QILhsG0psuSICS+hNgqGwOD6MLn6Lf3sb4rftwt1kARblZ
3yi23yicRqrkKfPlVMHjM5+uNQpHxp5eLdClNs9lw0NC2o822auv2DzRUHQkLwTWCJpmKLnGmOJ+
d7s5CwoI9pLtJnxLcuLxnvUS8HrPyy0cE4y/+ncgJjBLHsjVfn753do3GAyfbbl+HilGJBCVlbPu
MOgSNxucReCoaY0BjDf+WH8IdlP6XUysGVCru+V0OfA2BYi+tNuRPmS9CGg05mViNa4HvvOv8fi2
TtURkBzS3lw8EyUhejx1AX5UG30FrlrJBrMguOiK4HORdCSOxGbfIBlZssLeF1cObZM37iAzBiKO
QRT5kneG8EgxdjC0ceYQu26RlZ5NJeS9kLjDNXuRgE0V+aPkjl39p0ZWQDSTnVlx7ytnwr3ZiJ/W
QT2m9mlD/5ek+JQtegloHQbu35GWW6aLCJOlRgj4op8Uw/H0Igi3yY9NBdkFigZ3eprXgAfgSI+J
jS41wRxrjwBfTY3s7yJNNGNEGv5Zgh/YmrRMNF7u4+z8JIZ4ugBrRP1oV0hRthi5aaNS1tFGa2p3
2MNApyP3+QbBfjKgB4kYdsHfRvuSJHFfsaS5bbaY1gUKjw9/J89vxht0UMIWLQ5j0Wzsw4dTTSSf
jtnrWCWP8O84mPsdhFVVwKWqb5zyZv+FMQ1SXDlR4cW1wM6ztREdT738MOR1SAZr1ZC8NVuBduMY
QIT1SasWBzzvsV8ybhuL//DxumnlzG9PO5StfN1AEpgH2FTFuu2zj37p2rjkao//ExLhgh2JpKdG
PcvgsMNVBDHmjtopEny4pc6Utsii9DXZ6ZqDaDVExyjcQFqU52tbbXIaAwgaw2fYgbSGKaGT9uNz
pwAxBM/34qbtQWs/SNwZDVmzBqjrD8Jjqu4VZFrrvfEAgcD8KOdqW/PSCrHLIWyOwgMc2ZGnX5eX
RQwWS9dA9eYlcLJmR8ve5QcjRHYtoEpD1rpJIXrh24bKV0qBaE6d/cbYwsOL/iT76TNVwbkP5twH
1Ejf+xftsyMXQxZfGDYdju5MTjaf3uP1i0hYJUl42w1++jPvCkeal1oSteOdcbDC2k49HvrZ1UA6
Gj8BbGQbpgfz6R7XceGg/QNgfiZSvB7fQwF+q3ZrrK/RJNacTPI6mm+5+yf8UOxEQm5gGXRbHE6Q
dfFZWQQnW8YHPvFYkZbdAgBYfnBrNx9/Ws9zt3n5b1FcdUdZGkiZxFheoN25CIF0gY9vM8AsuIOD
4rNjCjwiuc1egbUGyn/31DcO0xK0JGIZ1OLcF0+YYn0FOz/UYFZdvTM3Jt6un/bnkho5Sw1DLFOB
2gQF3QA0phY2RyodT4Xi6HAzo8Ll+mGXoUd2rr+a6gdqZE/NSJl775XfaI79ohhx60Go1gdGbl1R
RDqCE9Gy9qjysZUwbv2xp26OwVAhR9t5fQBQbNIeSO116jBa78ORJc9mFuR5S7S3yvrQum4aJQ9a
C1rXsZmuGiGcUBb1fixLoAnTUm4RsRu6kI3LjDCuh3qQXQ9YK+KyE8LaqPCE8mAmv5DC2XttvijI
7PGW3xw5V0ZAgXPXcYjSXI8nF4Wh6mfOtm049GvERQ3XHWbiblczfGvg2juTK5T8/VlIIRLpzVud
PiNsETaTbbveJyri9LiyelqU2dTfC2o1T7RzIyG5J2Ru38q+RsSHLmWDBk8Z9dYPoSP2ixAv1ksG
dI8nTwEAQHxXTfl2myiJUwBTZesMlzdeafiOku8lXp6Gz6e9EBLfHjKgr7Yl64Qzft1KwM+geBfk
mUBVzQICuCpsPDEe4DYMbyS2Htl/uDQzxUl5z3OjeEAW3A9PfndqnM6KE0VvmPj/FMNkmyLzxcp/
y7N+lhsMtpEd5sKXyzOiV8mnwKKnwzk+6QqR2A9rkgAhUjcp4Yv1wbSnyntzAhyBTUotDMLxe64D
LjQe+wtSnekxoabmFc7OYL5vJQHk/8ngcB2iaO25X4wnubRRwbfSPBxRM6pU8ZQtnHboGJeWhc+Q
3HfnpTys3IHyAlIXWkwSDVbtWsZAMd3XOvdlcoDzjr4Sx7snBfRD8A3wTRBTn5TdhG2xYsAqtAep
iTlqEn85MdSA1wSQv58MJ0Kwtuvu9T/3U0ghJbkW3z2di28qlJcSFmz96dEnIeZlevWHHHl5ZFNE
9EanjO3xbEa0h6NZnqD5PI+qxNq91qVL2+Wuy274uT27hHo3pcv1FCWU5SjPunGzyD0wn3vtHxfI
37Ly+WGEthwqFMtmE/Ojqnbvqs/aMX/1I/25EVk7ryVkiufd81KLfvwNYG4dDHwMTkt5wrR5wJ+a
tYYFePQmMX4MscXysY3cyMZnSe30sNxox8EJv+UHJjqrgEaibIxi5XSoqlcAR0oJZOV1iNgB60FT
TwcxnYiTGisJ5hNAa9dSzQo8Kxs/S1rrW7eqCkAmJpsNTl2gFFAMyvtbxHcRN+9JHGWei0Hylnsw
Wg8gr6DYxLHG065R1pTiSgmO964HH2xue6iSH7mgfIxaRwapkc0pVF/Fz+M5ksSjp3HI9yLdodwM
84a1QeTCZRnSZx17NXyfLmzkznMIBD64raCgZiwksclyO00iVJYo8uapEbEDji+bFePmFNJAnNpR
LwvAFQYt1eOg9C2Kf2ZOuVZmRDCzUcd+pBEE+dp71f8D/TwCY+fCaSEAFJROUoz8FgS+vCNG78ND
vw9Sg2dFCdIDW0SRTbcQEte+5ZB26thLHQjTv2BuRMNyjVzq1BeaztXrbIgrVIkSNqVmujVt8+NK
W47lIxkODvUIxXaVIoU5R2DXudlNhBdWmUcnTE6jnLPLEyF9jewTgQ4bxqvvf2QhVEujXXOe58Xd
FrIhV92MFR+nGK1U8RdsqY4C1hbbWlMmSSj1DAL7+KEi3RuwOkZpR9m/mD8SyqReouviaP/e5J2c
6BPFAyTD6QHGbqYxqVcBOFbkYtARwapEIWkqu0/0f6UAiHighu5Kr7+oJf+94WAlgGo8wLhAq34k
W14pNfkWNeF+jB3Ctx2DJzVYLimfyQkLS/oYdN9eeXqHgC6RmIbiZ71380zV5+ikbuSunuVbJTGC
tyilOySkOQIOZHxxHDWCcTujl/netKRiSXm5f7ctX67UKkExlnqouLufKleTlJOgT1trNADOfzoP
VQRpP3JLaG5HUuOMLst8qqRCB+hMUI/Yw+NJgmElpjtcmv5kkxhP43ZZ7VIkcihEzj2z3aOSMAwN
sbnPgC97zgzvee+CcklRhwtGpnkRIWj3SxZW8y37boRC2DAIgOTMN3iCCf8EKeM57JALKebCBEG7
UxF4ixdrn/jez3dW1A71oSTo8SfeCLkD6ZxYCqnSwySi/vPocb8W4UyMX7TMv2qcZ4RzIG+NG1x4
9rLs4IFfQ5rLa/0SVO3rzJmL+RvYrfIzG31QyXg9G3AcHg1S6QpDPvjPeLoyunG7g0uKlFcgUOEa
VgE3yv0AscwMlXKaLt6qI0b21GhCmfdUoVCdoWSn+/894q+PbFnljcq85caGjQR/Vt85RFZ6ZMC6
218JzA4WlRUVrSFqp2WjuvOCdf+SH4xKMRWBUy1+APeDhMocelpwhpEVibK4rZr5uu8HCNm+2afQ
8WUHc5aSvGclQJUrO6nUM+03dtkfnlLA3qT3P1F1DVfJEuCt52WWLw54OY+G8flDeBWz4JZv/MCT
Q1QIzmOsSjWN/LlR/qmZaSrreKdkqL2LkspKqPvL7rB8mfCg96S6zeRtAJkYuogKgO1m2HU/tRMw
EqMvusXp9ZgVRT/GZ0VbwSM5jptGlZl3Ty8xVmyhzAiCyMBktZeZRbT28F+9LZITa/WxSlPWv34B
VEQwrRQBwphx0nV1+b+pKSFT6Jp/Yb0oPYLUSs9GRKn3ZaDXni6GeSSjhRwKwz/GCJL9opu7h0k2
5OdIJhOVy26JnWha7VXKyMV4OCxXiWjGY05qXLy0OoDhkQGfbvo+iaGLnMhAwYOFUJwFcJT7h7FS
1a2CaeiEHnC8tYsBY0Yg3oEYeh3TLg4ibr8kmIPvQQ/97lgLU4vC24Rqs5akXDSJrzBEzjI1QNI5
yJuBNOcATW5GwNdCokxLUg0NCKqgp05fmooxxuPXdX/uXKqp3umNRveHnGX4RP0cNpx0ANrrl7YY
vgHnH5BUOKaSLBU+2SYFAUis7BzzYSIect5JSivfpGpmq9KVhPMT9j0kOooIHu8gdmTeNKvCpeOE
OQRWhbPUtM0drC1n0lX7zUXdXXR69EuxPxR2HnqiAyDHMqpUsNNOXVlCd6iE5EYPJnwY6ns0DlSX
FnLFqcKy/Eje49VWLVJKORPbYXYtxeuxwuFrJMVkrchJTrqOPZp/90Rl7LIlE8gjc//RSdps26Zr
Wmzh9nRsvRcYaZrKfFTeo62jLTP09Wu0NK4KcKQZm1As4ol+7rkwczvqFhOE5YDzdbhcOhXEOQVm
/oou/hzQqKfKr8iv7yUwwu/qkiCsY/tapd0O+ExidCIQNyBocb0A5ve2Q7srLiL/Mk8//tTKKjrS
f/K54j2UJPhT2OrYsDNSvllrOt8Edn/u5OAgmxWsyDLJjX31Y38qvdWE5F8VGFHxh2YAYoMBU3n2
lw84HRR7W7xQI8bMxlHa7smbZjzPxmxYgxH6HVCXUwLeCMCMA3+ZvMQay8uL1vRC0yrBM4nysWSM
VySKeULi3Y7CPYSUq+07n7wh6rMzM4nEgiacjNs5YNpMn9KAqjtx/qh81aKrhppUb+mDeGvuDvN/
8qw8x+e2yHLgIuYfAEXjowqVznGoV1OyVaiqkmUncFk1q+br/WHuaXorpr93w/iAPQIaWUc7arle
GtYAPf2vHgMLbnxqnm5d9/rwDoQdiaRfSGZ9h4NpNiPkxK/C27KwIPUceyjDYXlS/5BAEgl+DpOS
/q4V0tIPUIUpcVCcz7QRz5suZbbiISstNKv6oe7tTg7f4jItMJhHDEjwQaZWvePqylLYjQW3g3FV
XfbgvJcQrPsnoFFUqN30c2DENHmGU+lFZcloovVRc3li07kD6Zw4ly4DUJdlh0CBl1hrdKuKErRw
bNtBugM89rpcMlo/iC5LnBPsDBUfEyBLldt0laxWQpYI4bAfcZL45R/Xjen9Q2G9Z01K8snUg3wA
5LiB1NOcjSFIACRyUaTD4goTq0BBV+Nd6i5jHkdXzYgjHvNxhM+FgrcTIpceJk6lv1I4PVqGXOId
iC/EME8VjcG1Pk7TkTtFbSNJMf/UewGABatJVhEmXI5ZMGumtmtcC0Oz+xE0a0casBpdwGVeHoPC
DW4WbzBd8jvzP5d6RXkcpZny7y19FynZ/aCRJ7MwBZltpJ67YokGQPsQDQTzWGD/onwc3+Zmj9Ua
MJWiSFWmyQU3uTCRvRDk1MQEhcTfV+HG0+qjFXBnzwoqOxAklfFCToFjZ0W9Ql+EPPFDTHZkoQ+r
dzIWuyAIhG+bPP/rPex7nvKG3f/iZZs+7iYG3D2TLUZwiWIYagqOS7GKFr1LSpjukw6VD11AUemT
6KdoCdPX2m+HdEfhJGao/gcR66edFAztTE5jz65fklKpaucFCgsrfJApvujW1HHzTxpZfyMh9Dxf
XHabki4fd1yCUrt8Ap93EXmR2ecCwrSCMZgVnfFwovMf04GRUU4cXX+eQRiBxylWgFRD5JmVOymg
aqA2NG49bhxLjrySjywlO0yZccu2/ZQsnDl/UBK3EZdnC89c19UBJzFKOxUQZIbJBOhTYgBpHwZ7
jEYu3VRVz5N3EKoUb6Ga30QwmANLgnLoLHbyYu5VqEOwnNNjkWVMyRHIkG5ekraCLduSRdPX9tM1
dL6lz41PvoEpInwJjPrQaiSK2afapY/25LFOVXvwgM1o1e272oALGYrgquoYBnVr0wOQ4cuFHc8h
lfP1ESCYduobhKCwDKN0awHC7buTMHFw/fujKErCw5w4G/frYBolYlFslmvSo+xpDk6uJAhladGo
dGXDlQ3fBp6tm92BxaY4Fv7PniU03p/DSRXR/waJO3fGWVjDHK7ZSDn/zihr01WCVVg75/sq2uQ0
1z0tSZ8pfUGDoVb+JtjWYMQCdKSEd0r2/rq2gYXcoX8eT6unRJk1BAWIhqcz15cIG0u6DBU9Oxaf
2stguzgFmRDjfFu2o6zaug0r9wm4y7a4TLKgb3N5Lz5Zwasl38dI7mrkyO/k4R9NihN4rawufl1S
FqKPMT3N+1Gmk0BBt4I+vGXW7dlQgr98RfHB0o++mBR4Eu+9xPNJxeU+jekfHD1+Pdf4nde3GliY
gqAHbuFDmm1/5d48PxVSFxrF8i0nsAVGsi/viieswl69ApK9PmclFM68GEqfabZaVHCfIO4LvGhJ
fROjCWdfbWEI+uREskSYuC32su76rERwa/JyHIonuFZhVixPN0rBgM8scpF7lzy39KJL32cGzm3g
TZesiOMDrHEffTOSA6oGndKA1gJBibtcx/s5H6IM9a2iPY3uEh/XX7+5Xgu71ML4nZCpYXnCHOCZ
VslATI+VyamTdLAdIoLAoYcqDoKWtXbaYSu0CSvd63J2qw6UV6Qn1ugWq4aZb7pH3iBFJ2HIAYd0
tdZnGgwkZQqNiKYoXrhVP5i3q/No8Usl/4wtCIQ2TYCDUD9zaBIj4aVpZ7vwBowcbbJxYLttNILa
1i7SNfrdoKPCt2PNrNLIZuHnPHODTN/wQkrUJlG5AjI53qc0KfohR8nfOVopOvLyfpb0zxkuJnFp
pGTjNIpV3bpfjo+Fd8OtgZACCuyNBHr1ZJGGU3FGvuX01P4nCc0srh1/b+QCBb4fXCUtDmmN1dcg
jdlAixd+FZPJR0gPQeNzOYtrEo6K0ZCLGvPkBbPW4Hv1s4pHNJfmVvbla4HCq8luWMT5zyVlYIVi
viuHXelKGPTZ4oFKUvL50te3fZnSeOi4ciOkmq+wsWrU3ztyZPoFI6Ons/cRMiIXsxe9tSMmDYPC
DQ7uuBp5IWKYLOdqLF7dvDQiXXFQRvamk/Mo2kONRD1EHkZ7PN4LflbuCQaEZ3ZgkKs/6wJBjXaB
RyfqTb1pJ03BYXeyXUTW7y8lzay9kTsefuv0O0vDG7afyHqGuOdvpE62YWPu3TnLSMg96A5Jmv8Y
zR0mHGqxOfKTFDxG9Y8waxuA7LsnnIYfvq1kaZFz7uaYfy50dAF5n+/Xyn///WaD9GzNWurzdsUc
+ohfpCDtl8WeNJNAruRD9AATeoS9r+2Ey3WIKITR3ayS+CgdZIYcjQmEXxmWbKK1tXWCirccJGbu
7Dq8YtpsWFi4LzqlugRlUk8wU87/nnSjnrUWnIkK09ehQou8H96aUTKU52swcp4CQpPm0dRjbJTM
URCLQZql6xzLV9O7gHPjKtfapvT/Ckxx4ngbcdQt01DWqhDTBspSQaFFGWPoaltZiirFpQp9aFT/
zO9HII7epckLRveCNnnAuCKL3nWkXMquH7KQ3Cx8qe/U4bxxqDXGGMBBGejtFJ5sIgZ4Py080lwV
ROUeoDTmWtIlEA8mrEFY/mc71foOMrJYVUmlFrr85DxGJUjV4wQbZ7wYJoGBAraWeBpMd9csmHSk
IS2NTziEKYmQK4CTekR59Y/HM5jDmns6TnTXoQEWAwXMaG7lEkc2jO91DjsG8SBdVAo/XbGGe7E9
9PhhvbTRc2NHrce8uRacUzWOfTQgf7PAecoSnVtFXpSVqBMsr0FT1+i8ti4JKAfBL4jyJgwRP2lG
9Rfivy1+owc1VNLuLGZPiDHjwN64QWJyHJ55ncRbhaE289zqPQFaneDs9frfi+TPn4sMxdAWsDeB
Vgn1LXv8sEYdGYUxL6gB1+NBAWBukf+25jWN3xUOiS17sV99NkRnamKKnBA6/10KLRwcB8xt/EHp
jmANfIiTOUA84UP0eE9x8bkr4QOUVxB/g3/wMA5J975elV+mE2jZRkILHYN5jvVxGmIvWKX9QJI2
8COMcoCU03lXyABeOUtfzu+frc6gRBAMlrdOPgTEca6ZsR9RjLrpt1ufEsBS4+48vqGjKxXGnJ2O
4gzTMbTc1ZdkNqZeWEXu5NYx4xAzucw279wL9kTklqgsaz9VskwQ397UO+fkAzLPClxH3IetQYxa
EjLu59/MG3WtIYy7BCBHIgQa8fuaIBMsYPq6o9YrYHeHmTKS7JY3cvUq9/ujYOHa2tN8WqZu07PG
OWh8pC6/jhEvXiXByw9idhs6Hdzq/FqBwYAQrV8DQkN8+2iDEpC1jXrdt+PXZS6zR0xLyZuBjugR
y+AvgT0lZA9p1KJHU7XmG3qDujg5RRTnUMOIDD5eWjzaBY7poeCM2YSdDLgKITeVkDqkwMGEkHmb
UoDICkXDNbvBlxF4XoLYYFOVZhQxDJTdoCM9FS25ne1S+KCIIagUb0A5eW0eQmJJxBbZu3KZ2Paa
aQO4eKhijlPdlNEvYZQOriwOdaimq8V/iL0ZdESOM8mX6gEO3MfcmiH3p8dgnmelPYfK9GPDkdSu
WZtpbgeiMfR054jNM1QPWHyjy+3AwaEOSda8KQZHIli2a6CNZcxmWxDz4lUM49EqhLK13J7Fdmgs
29U7y6xacuxc6bhxxuDj0m8673anhcELLQpKP+YvFYus7B+87fdb9WAM8/OhC8Gf25pGm/qxwoZS
eLSsdhm/nF3ASPP6KaXnFsSu4VmmJAgQZkqWZCRaWot4dUWKWsdBlJhX2zUsst1r0myqJEHM99EX
kNijkQfWJ86uQwllRxZ2C4LfAUmpZIll8BVB6Nsjb6z+p/uogYC2DPBEfC7diODko4yKiMthHvZx
7tSf7La9hZGLMiwztCBtHKITjtCQ2H60n8daAubd3mqayiDrrnMxbMqoRZmK+g4yeYChWY/UEmXt
ExQ25fxrzfx/tT7g0aOwHBjaYIEjiAx9iZcu5ke9D/jtgLb2uj/9ykifJAFNI205m2WGyRNvc5a8
8t6K0QZSI1aL+KXcd+i0AnGX4wP/sCJy5KF6+lhWiEbljYwcte2vydYvCQbCKbOtXYje81dQswLQ
xalwZgasBo9UeR4I5Xz+b/ZYpxi3C3zNheDLYXOjoQe+sPKLB4QNDgnwv8zfSlHZk2CVMCjIhS7T
CbwBkuYQCYQQwqRAzI+bbMp7c/7OD/NCW1t/9b/HGwBnPmQXSEWMXxObuX9/jr7w5p1T9nzQ3oA0
A77QrYGfmHXlEDlBULtNfcMoTqOPjb+KfxFitc3aeLS1QrNp+FUvMg/MHEQmp6+McxupYj7R6ZFH
aag8kMTPhP5ac76qn+xVdDf1JtEAyHFijZ53Xn7qj01WTuqoteOc/XWrRhapwDSbHb6GoYokpb8k
JTfPdYtmMYg/xvS9ZlRB0NKbJ+R8rj4X+myvl79STczz+YCEQSp/ex8ZklB3aR8KdgsNAqhQnLbj
rWaXXcWnConDm23TLADSttY3GayD3niWDCevDGsh/d/3g+cIgcrr53UAtbOcJ7YA8cBKPk6R3ywm
cqYa1vGWoC2zHJuCibQq8tdl7wOhbXnAVv5nYE0PuIkQAVpZoscytDQmwKFoa8deBMqkuVDZcc07
l5B8L9WGSl2r/Z/oqyxUUsoHLb4OUu+R8jXT8H1BFhJeFp0JQ4fP9BtcfdB7dq6v91AZ+opzlwJ0
1iTjEuZ/tDzsf9Cavv9QRYYVoEpl0EFxOKN9R/MkRx0BZUixPlt2UssLtWzCUG24lA5Wfmo3dKIT
IEt9+n5BhTMCtpx+E3LlQm1a+ZDnpa0wLnkzZ5DkIDKWSBE7vTCQx1+ScM/VVdiqktXviWKUohPI
Sr5QeAGW+Z++OxjamsIqxf9t5EfBQSbRFfL4vot2DgktyWtrepeR6FkiDL4CMe99j2J/A8RSAdJU
BbrKMdSNs0C2jiSGHXa+uxXlo5gimXeb7BpNy+6SsAr//bOmlGHgsopq44bFREZ4R9C6GMQckwjc
meo+5fyef+qGp5z1tLIJNhZGDltpy1wN/W/3hCSWXLY6x2d+3kW2fc626PCpJu0vAHZNaCdid/Vc
Fya00RwZBA7BOWL/kBE654kxwWvvWou+uObD7+FXARube/WIZWTzsTj/4Q6Fh6G+l1ioUa2zyHOb
RsjWTsZTdcBwcX4GfHyXD8o44Pb1NwtYYZdGJmMNAjMLNMCZ66sK5rEgy1fSCpvxMxzy3ISKOWxd
Y1YtgR5u0L2dAXBb7jU8hKywSgkXpDSbzUthJwQ6R7veSuFxxrO2z2mgKwodpLiHX4jLxK1xcqOQ
pSLnOPR5Oxr8yJRnFK4gKRrtoYeQ2Aszt8P1J/kfTi8gUmTMayniGnHAVQFX84krJJ7sv87uyqXA
/ujgJOjocz6kUfkCBqf4RYGY7qv5eIrzwhVLdsL9Fbl1Q80iPTzdjn6cB3x67kvEc3x4r53n57M1
cedGQOH6V2rLm3UmNTBO6DYABMzr8YZWIs1k5/07u1/1/PCQ1MoSNpSDmwTMRxUIxW17+OpMD56R
rDLV7/fYfFT7K82qlaKaDC+7yxmgwyXZf4BrQaQpXX5nmdcdii70e8daMKy7GGsrJ2TVz9cbVlbq
fbCSFpLbm2mMVJrNHf5LRfdCIGG9cvH4svmO3ndnYazjpdLFgVSf+ScdR7Kf16v6HX3r1R3l1sYk
OguVJC1L8m47lY8SKfeC7tRgZXw/bXe5uLB/pOetUSjk+KDPCWnRVKsh0OPigbZ7o0uxwi2Ai9J+
JDK79X/P2Y3m6MZehjzIjJtgulVwCr4ofQt4/thWPgvGiXH21H2esjsyOjoqU+7oSPFHk47EaQhM
UMKIQVHzPyLdf5csq1qGW+gfAaU+3NW2jccP074NtXRdm48fUyG3DbACNWKSnIplyvivWLIDooh/
Qr1Amdo7K97IuTIXmHeCclx4cBCCRhLU6FbJzxhS5U+AOVQNvhFxOadhWrEmeXPSy5MTwN44YpXu
d5Oo77wUpgXIVFH5uv3HI4BqilieFOMgyoFtsCltRzM8R0QpuJpEuwcfwdxvtBYYGDHduTtHtn6V
JxZZ9PCCGl5eHl0eHqrJhp18HiV9nexp2G75NEuXs8Y4qa3W6mnfg3fI+t+T2+/sF7DlK8LMNLYk
FwrJ/ChY5KXD+A3k9DjYuuBZKHzrgpyzfOyIDoqt14OoCh7S5j7pWnGrnF/d+OERJJqe1XWYnffA
h7g1MO1qN1QGGhYaeV+dKziQvqf4+zGsAwGYVME+dpFmIBLCVPZiYB7PzOnsghHcKB7Oc33KXWQh
7Q4o5fgOBITG3hFgMWNA7iKhpQVvMnBisqjmLjwFMBOSfOcUel7K6UZMpmk36Cw81B8nYXpYlzfl
pBk8Kb5ZyteB1IUP2fRUU3ivrqhHB3cQl/3qPx9n1PT1PEUz/224NFCPCkiUmg2AMj7EzJ+IW/M9
iTkWnVCDMd76ZV7muGHN3CXmsya3wau7UK2tJu++gJJipW4UVZ02zv7nC96F3k3A0Kwkl0LdS2aX
Kr7k1qqEVyUZBjWLzetNASmbPRCk9Eg/AOln4bNzKdrtB1fzRbDvhXUMIVF96bwZmjfRAZ/qC0bK
/EVfXYvtMwxnOPPTCdQxL1aIj19e5Xxp0HlUaQavFsu6z2kXxF4zmYsLgrI30eV6s3hD85kcRiLf
SZiaVA5fGT9nxjOX23YWNL/73GzkdZkpTjEK2PUXk5i71UxIpVzVdbZ6a+NRpWqPxLTJuAdxDvBV
Df/Y44OfDtqLVu7vZTmWOq5hHrBQvez0mzwNnXpG5TYf2WiOKtUiaNInIF/rfAjrZUAn7c5TWIGr
d/tWRfaqF1EDuyt66xzKl/8ojUhKSQk0bmOBx5HWDVe21e4KBmZWi97HFOoPmno/svfJCRAgCZLY
95SAAfBvCWx1i5f5GYYoTC2HYTr7YYWrjFZrK1hIR34G0+KKQWxZWm9BF2dT8jzMWU5W1W8pAlSU
w2Sq7FbwttFN8i2lnGvS5UfcXSayFmgpss7qr+Zalqw9lkCqIakOMOvRCar//Ty2JFfeLxpQicCo
Unl55/+sWjHy0lVBRVAd6BbnW84I6VexZV5uFe7HBs51mFat/c33A465exwSzt2KabP4Oshdak8B
mJk2TNMqaqOVMcTVe+mfKDqAUfaPZs3kM+HcoYrcukQVY1psuL+H2nJPb9AZ0rixhLdk3yBKDeP7
XxMB7CDkZCwZdPtohafO64lTmYUmxyH4YLnflE1WXs6GhN9sjmacWhln1zL7TPi9TP57M7S/yzPC
xjdS8liHPF6tHYjTn9UHrE4kOvwtsLFse7XE0CRlVf9MZjlzpmlz4nBGR6qVI/rqsQ5FYZf4sABv
enUpLQ0RGQaMPo+Upyd8Rde40L7VihAlvL2gjeHekMWOwvrz0khJI9/YTDy+aa2vopVObbhU3qyB
LbRJZ0oGrHNtFtMfF+Ew+LvZBQSqoOaowLXH1RxpgeGFxWpmb19gjN3R0ogvm0gkTl+K5fZLwrWL
Xd0UY2bKwLTXTBkHe/4nUwFrVbS7m6/1FIIjn+85EOTZjpvAdXr9023JZihxSfsO8V1cyPmOjjXg
i8wC5NPQphKel8DH2Yb8xhkLyt/ui34TJhR6bkY7KaNx/Rzw+Hcvc1yeHUrdhWdqtiuyVJ+sXujc
tAzu8/+woMB4zkEB2NA7KjuUX9Yl1UE/3Mm+JYgX3J2bGy+Rnw3OxqQjDnWARp1UWHOaMLcxeO3a
LbN/df7F5f6uI1/n4ExPskjMTQryDB8BP7Ve1UDT6fbkra6M6KyA4vTOvoM7zYK5z3Wge2OArEUD
TYlqWRSHVXGSgog1Fs3XNG8pqKCMdNcYhmKHKqWdUTeAqDUB8de4k5VrOu9Z4Q5Qp76CuNBPRMOI
rcBvhIdKnfIeODrBVdFVhPVJEs2Bpz/mns6vFj4YkZJ8rbkmXRe3jB7uTY/hJtoBhPHNQqRJTdeb
H9ydKsGhjdbE8v6gR7YMcRl7Fh8H5uq7U8r2Uu/9G1yai/eIBuLZ+uJcZr+2bLAW/itY8t4vyc+j
7gzgkoK3jo8ZQzwXYbkwSeuUQsjr1ExMHeKNWGAyVPqBjLki4XUz9Cn4N5XfzSSqX51TcJy7fw3F
Xo78gi9iUP2bY4lGKptuV4nzYXqu+cRuHtDhqHQv26mjGWNhctzLp5Sxm3khyd76SpKqeAkc5y7W
xMhLFCY1YSuh1NQ7szJDt2aWH3Z8iRZkmtyhD/8zCvcQkOrJOIlVI5of1xvHUZBh6qW9jMFQyATn
i27rv2zkbN88N5bzrIqGo9zrjlgv2K6VUixqS6eBTDWik17GbHg9dYPgcYSeaCROBKivdbyP1mEt
EuGc9POdiHaTBgnNT7wuf0MVMuJpcwid0im8RsrlkWsOVcccUFdx6f7uHwKtPZscoluvOz1p4BJ8
Cmp7/POzKEbvvuomPHm8rIEb++nM3EZsp+UagNGSFHItCjzVjlkBxeDrMZzgHyjvs7VHAth+V6Ee
JJVmK+djkakW6a78oBpE0xsmvunwe5M7W1xrzLnUJ7xKWn1gof12DO0FILbs9/vMLn/Tvb+eVfog
guGRfBMlz7/tHHHX2VJku8MrnTVsUvk8jBIN9hrutnLt5Vfu/ltyGcnF/rhvYwVGGcjJIKiSC//H
SgDsSHKLRd140xpSSPLAEKRmZHEj7WtVrEE2o4EN/T9gdXykUKg4rW0tuRNs4LySne84JdumarDL
Ln3x3PH1KfVyCtRaBFTHh90gXX3nuzwJIbF/JGFlCE5UuArR6kHdrQ/623JREYbLw+6PV76qGLDC
/xukmeoNCbvLYxKaa3pm0pePKThws2Md75nIXRiR8SAUAtj5ASdoezs4DPxV5JAfJSexTiO8ELaV
lzDu6zzo6WG6iyrfLLbVFVLcIL5Z4t6Ls+4JQeSP/1b4m+c4ySCEEw/Ga9pMJqTMP1/MQf1PxGGn
geXKsbv30tnE0aHL3rbtOUTIBFk+UToopbQt+AEdb7VzIlg6FBb+PkBpin2e7RZriW6fbOq+Vm/2
qDgPjT4DLPX9esqLofidrEvSUDIkuGkSyoZmrdzfNh2xV8fe1gAyn7qmwUTrHxnKV4+gaRAURIrL
M804vfVh4EeoavHpkpsQ+jG7me/nupo4/LrWrCqP9zj31FRIAUSdcJsJh5BldLHQU66n5WbPpvrQ
KQ9DO7Vt3SQy3lFsNsADLYHlP+ekHeOzPqcB2DPp+xP/oXn7S9fETmQnswe/l4MEoXZx9mIYZzDs
gAK08p3dwNsC8p7B9fRzGg77uc2tUgeOf1KTRRZMfxY5n+2Ls2sRm1oy1J1XZQZRzJs8dheuL3Qi
qBs7LlZprPt85a3ZTzTCJuxO29f2KEaCh2kpAesINiRXfeRIdlls/IjCVlWE4Ftl/LcVcRFkRWuI
eQlInc9+N1GlJs1Hgr75Rwb+HAkSB323w/PsPSBIkINq1GChywndXgHC02pQRGH3HL02T5zgtnui
Vb2cYpGxuoDMdxUtdag/bEwZlVZZtG+S5GeVzLAjpkss+/AuvI7x+fPXq6hZPx0XIIZq2p4IGobe
bkwZLUKKb0G5W+5Pw7/5pc1efMGxM5aYNqRHCmzOe3alO4vAyu+E6CLomLhDbrrtDuEdIoyTBOFR
iSlGTxx7VNMI67n8dV+BQRHkwi9l+hrFjoM7fh1Kkfi+RmhTgGqzbcMRj6n8IGx9LZoIiidpBQqR
5NBvtaVUkfkaCe/lFilVueeHuzvNkEvybXlvUJWo7FPWrP8zkJqQ+rtigydaLBIeDYXHg+a4SMjX
rq8MUe1kwBfQHQGy6eRMZ7EVUVc9R+qPrcLNqGLyywWZbE7aub0Tt/JBM6mkbKluVGVaz8HAHKi6
CYCjPbzO5UMsgBa5VY39vsq2LYqHTwpnSTBC7LbhplM5LppbpHeYKcPyr3VcHEEjblYfWyBtykIR
mJw1Q4hP/vRozWW8dYupc1jPG8Q0ewOOJlpK9ARrxLq7FPdYtLwQdYPbj2JmpWUBZjl8ENcwXREZ
mJGFg2sZboQf0lhTA0+AclqMJQ8x1Vg+O3mPIBevLCfZj3SiQkhnq3Igff1OULxu2TV5o+7PZs9M
gbKo+tWirYNFGmDe0SbiAyAD0dY0C5gtEqmIAAhAmHLpbd8eMllYBr77RZpHB8n+9uFdZYt/RGnm
IeGhFj+HDdoe3/00fjHoYcVlNz3TYuKXzr6mhmeuHlq2yDFrrxZLYN/qWIxfjZicUqNj3nM3mpMu
+dfY4klEOJGiecJihILhqjY2INjiL0IhKDhLwIv+M7QRwy+NF+m4y8dPsLTyId6/mcZYt1MKgsrg
A1HgYYnzf3ePZkl1dtpiy1G57f+hIwh5A8QcgZupgI07JtccU1HprBLEJ0LcfpKD4DxVO74raU3n
LWbDPOzA4pOV0RQHQoZ/sBrunYHXY0UBNbPfihlAad46PhS4qi0TCHJZ3B+EmdEKi9MfyDO0Zkqd
VkZDfmCb7iireyWO0hka2Ic2J5XdayoDfsleD89CAZPuZJ1WNveSAnVcJNlvZzpsAuEOeTQ7e/ri
AMTx4XLZuKKBpRPfQL/4k441AN+Dwhe78+rGiMmR1tx0wZQrZcUBZrZMQnHN43FWhfIwtmDp98Sh
rVSalJUoPwarkacUzRhBg373yp/r+FaCfGKR4OHSDJtyGz8DV0yaWu1P7jGY/voECnz3qQqqNLVm
0QY7npKcQtitlnMoV1O4bO6Rmno7GN7y1pkuXiRdfrkAAr53cSI5I2e5F4MKMfOITjXi7/7c0aKT
DEe8t01o6O3zObd5IP9yDXeigLyu/5vax7ZNb2BETNfcAF2OhPgkmHvDqFCmYbFL3PelKI6/5q5x
Spx/AvNUkRcPRzqSaw9+ajDXZVcZXu4G6KfPGsTl6TXQn7VqrobBaiWxhshbg1OZFk742z60CsFA
mgpIoHS4a4nubdudVukWHNhD9x/eE1F+dhWb3FmmMuzaNs0rinfGOM3p2tik3eudXYNLTnCBrib6
q+h1a3+GXnj+E11fhTxZ0T7TX+BU1ilXcp7ovR9FSELBS88Nb5zPRYxucZd35IYv2dyHxzhQ5HOw
BiFuUfD0GCTT/TMNDStcyMF7fr231TLfQ89daXMXIevcufflkuvv1SsAMvsVL+dSlq7b1XKerQdh
vgng+pRtLOQj6FXWTxdHFdZnvN+cAxNuM2R6xao8LBOtlzmnno1sLD003Lsmhp6tPGKSD8a411yf
8CypMGYsWrlgbMSv5b/BNFPNWvHOo004ysCsA922rD9fHv2xc61dXG+jEXqLOqR/8QxALHZ4Hof8
PgrU6ig89lj9xjMMXTBVFISmBeB1oxZvtW3Fc07IVC7EyNXTRqR3y/1UBITjPxN5JO7pXt84L42V
QtdwFT6e5GSaE3VEwJLZlbFPkrmad9rGRKh9V0Zzp6CUv10LD0DtsQxpq3BzSD3kBaxl1/Q6Xggp
5yYSS3ZvJOV4vI20IoL9s9RaY07jACGODK32QBPr0xisWZPCdf7DJI2H80r7hdi6v9EUTK5kcyR6
diME8Nhw+n+Ggy8YGJZT3w4kuHr7/EOCIe6+9nsv5dGvVuYbJc4ywL3Itd60uNJjzKKFqhZDuZoG
gcoUcgwdNS2IddrKke7Hxfb8cLdOsjqVt6uq+BeyoN6O3b3c5Z0/l8ffsL/mccvM8ukc9nQ0ixxj
5hiAZhlui4G3Qyie9Znz5m0uy8C5CNpGkZdjbKYKubzv23sgzJElTWc2h/EUtSXurdXz5tnnNSWT
8jIywDq0dIZfA+L/XaQCYf6xVz9OmrF7JDcs1oA5VemOzyIPjccLvP+HicPean4gCehHUxv2X02m
QD+5lqWGxdaLkPYukUa3cGuov4TlJS0/ZfhRxvY0qzoScAmiHkBqWgcEHje+oGT7Y8941SbJRBOH
8IRsSLe5KB4wbxNODBH45ymjDWv4EBciS3hXCUiNsAoeCrvwNy+7MzNBv6cYEnX/wAyEUow3NmT4
8hO/beP6rZ9Y2lVP/Bm4DfI//t2T94n0abH+tfm7sXFhZhbwT/RRHhlehbbTTNGM6n0fM7JvWoH0
TEtDxOQX5DgQKkRkzc2ZM5mJUfeeXtZdJvEyTR7pSlWzt1L+a15gwP+kRsEW+ZcBz5liFJocHeyS
yyvVByOmYHlNzbnJ3kGU8wdJetovt6/RtPkhedf+CEkTMeLj08/2LnSoa4xVjbPID/x7x9CYeVFC
2Y3yxNIm94Qr8ol+f/So259g+rmF5vJ1iQndwqhSWGkjPfrNIeTMoICvdFyduSL3yT36i5a1bGZo
TYk6At3Z4OvE8uKjX1R0a+L+UDNyVhcR3QSlaR70RHy6vkl8dZadcXX5/ZcyaTAotAIN6ARSHnbs
MWzPqxE43/lXeCBQtrWh7FnVm9v5Mb4XXoV5gLCNn52Clb9QRg5ATdGgADto75mYlXqX8T2i1xR6
vU1vMCr1rSRwfmtaLVbWoX/zeOGHpaYk9tAxLOSsejZvi3vONNw8+A6MZGvFRpU3iG+XGbtv/LfC
9AMg4ba3WLNssWrdnj4Nqq93BXvyyx/3Xw34+cNDgYQK2rXBjEAmEwxiFZuFU0x9SUuEob1CK57U
WbnVuOBajTQQFDKOVnO2pL0ZG7S7wTGBSVc42J/Auh6qtZlxEZTmYvGSiuyzJwP0M2BDqjsuZpg3
VxAclZP+DAJj1F6j0S6uVzuzmIcJGTsRLOmz7yK2x25aTbkaKPDEgiTaWQ0l8USrVqn067QdftCT
UiGncCVYsdmlUOvcCHPWoFPE7UBHGR2HtJeqs/IBMCHnWff5Rq8p9SiH4/c/UodPyp3bWpgBtVeb
VTFS0qXsZrIyceWT7c06/GqvPWT3fF7a+gxJGGOF0IbXc2VN+EkBLFkfuRNQKcIMlgcpciMi3XaP
0FXd7MGLvhZsNUDG7i9OvQz1+lHvmR/Pgp6MFb/l1/zxduk63jDtKUGYCyjaW+IkVkKzYYYdNrQZ
O6MygzdFwV96sBc052NX7B3zMcnFvwyIvQ2aHWS1GM2pJuly8n5fouqgjN8un1jHxaQ4GIcLdGaM
S7pZqE+P1X0+O0OM2NAILLw9ByMoNYFEyY9X8AbKtEdBKWx1Ffoya7z7h5JfWw0RY0RE9/L+wOcA
TqJY4g/rvhdNXstGIs4rxsaYZMm3VYE90ckYj4GTUvmHuambI+I25xtH7+502rqlT/nCdxKQbTJ7
JyckBSpVkElTpkefk/LDDhitrHA23vWFAXMgmZgNCM+iii5vIWuS2ndhtCElKalxp0qOTjXgLfpy
/7uQlDAUT4Y9gkU61JlwENOyByyDJIYVSi0xdAYGF3v8K5z01NwMqK/xwfkxxej2GdYkX1K+v1Zl
/dMnR2g8kvgAA/ig/Pvq3do9bGcTegdz76IfcHVk4q/jOehmAX7NfX6snWYqIBjwY2EDwHeieEUS
byoBobnLEWJXndxikq/nh5F+uj/7ShVZpqUe5hwwxMuhwYvmK/NG2O4mb4IV95xJ3FCioiSpSrFc
gv4yQ5IvOZfhHXPM0OqViYjXaCE5vVoCoqrbulUVeR+9xuzlIc+8/+qsIDYhKgmmaE6Cyx6fimZ5
fy85XlKb9CiyRBrdeuVeAUUCe/1sxT8XTzWLw5JQzlv9OfUIaQD922LkVFq7ltEsY9dz1wCXI9iF
NXLupci3cBuXSkWatAnqhHvj7hehPLTTUnQG/jnaF2AP56LWCfpmillSV3zA6UuGr75oIpF1hdUc
wEz9S+8dN47anumMriy8iq5aIaT3P/g9+z2HyVtwTzJ9i6RDTBC/+DVGrQq4msRJjaOFTC6qqTcg
MOQMrTowy3UyTlZmlvSkWKWH9gDpM/3bl20GXKt775T7L8ydxTRHiLeT/gyhVSdxI6PJGD0NjvFc
5ByBYGww2MxpybWh9u9WmGICsSqpkKFtw8mhLsKUV2Ld3hfR3ndXFLne9JZdLAF6tpd5HqVPckZ3
oF5+PuM9ea49N750jdVnaRxiOgAr4dS4P5J4DhmigZ4JOi155pgRCdJkwg7gTRHdsWTdr1S3vaR/
ImSIofSYHZXZKmDzSt5TvsekRkzHC2IMrjfDhQConoH3QUAXPMNrP9liXRQA3SGUja0UNuirD6Om
UXriMNKx0gDMwToqJaETu+M1FrvIAZxTjcWv98m+L1OQgKmn76uSFOtiMJj2yLMgxPNd37jxC144
zxO2dWB3Nmw4zDPVIMzJw5RkcGSJkL55PKCvPjqGn6TsYsw82zqKzpGzlKXzwuSD3eNoVAnQWv0E
yLMsWVSPWDAtIU55IFNUZSLrn6aj8afpckMrkH/fK7xqy9/a8/5rGZCWzIw2JaOiBvK8KUgvoVT0
vPPIsrkkaCDyefJmo46nJVQ8vOdWbfg+0uOmsyGZj5K9UePpDLEWqm5KfkkqrnFf0fhUp/b2UO29
mJnUBcB03mpVBBWnfnpkWSzJWTwM80VzOOLCtnS3dpZGdGOVRWuoLSe0zlvcMly5YfDSQ0VF7E+J
Y6/6G8lMOGxepzhdjnQVA9q47JcUhIL88CdCVSJvKg4nVID/4o8DASZ6sfGuV8GXGAK0RrPob9Zb
HS+JbyqbbABzfVPUcLxoVHG71ecP/0rbfLDxg32m4pOQ33jLzRh8DtzaiX3Hjg2E0M/5Kh3iip/4
/mvQaA/Fz3otzYn81SsG5Xe91P3rILOlJYr6cgiMPoU6RNQAFZFRHmdeWuiRjlus7UKTh9Lw3M4y
w3J8EU5erWTiGEqjyJbQIx2dEsI0nGliszODddM6HKQ0mmLzJU69RpA29DRO4vqyotDdDtSqZDBp
C67xvzcIOKUaJrSDf8OXfGqqZoeWwHfw4AThQszFZDZhkXxVV9Ac+ulnWIDkRQbsCKFW0536XgYO
T/uHRtlM/Ve3eBo9s3rQvD5F6orFyZmzFDqPmTOw89wERuRDZtVRZBjZ5sygnK6EgrYkJ425+KdT
CU/8Lq5edQogWklvHMDCUOlbrWiAT6OGw+pR6vM5ago92B7P9Zbr6PG1VA2wEIZ7zsrksHOLCL6U
wx4+Xvi6UJ7zWq6G5ryTMPsIZeIOxiLUYFA3FDeXBpspDLuu2uVjDyL+QOJqjUfSMz21Ra1vGXPG
qCjPZlMsfcCaGSJLw4yIF+fdvzbpJOFTv/Aq8yml9ffHdpHd39IjyUA4jSKP31/urOeEt53VFdoS
dYSputKIGXmsNSLdPCcCR5Vdle2MWpREmJprW1XaiwWgsp3dCd9sNhMlmfy4NADCEkdVtRYcd6C0
m7f7uEEXE2v1GwL8/JI4g5LgjodSFReKkz4ah5BK67nLkY/2Zu4U2CPGpNDLN3OKyvRwdI82r+5H
oH/ZQ3y0caHOtZ/GHEYh6haD4dhWDlSlc3rTuRVSv7xUiPgFriMrm746Vma0XLePa1rivL8dRlyX
jKtsXGC7wMyskKUvA/8Zs2v//JBP0Gr2/TsHU6DFdTU6uVl7h8PSaJM2AqHn0s987RtV1ioFjkVM
OQgWjqVMEaddpFmgpxhfbiFSK3qAOnzcpRuwGhvr3AxZ4WsRqGDTZId1HAhDRSU126Uaf56cUlsZ
kOZ/Xdo0kHlObRGgeu80A+q/Ejfa7bV39R0S6vzJ+pZVYeMRfc+Y+Y06jFA7sZ1QKGcuESnHLf3t
Zfgs6FGwGDHwm+px9cwk1mADI9ixnIEoz0OLElKbDxR5x1plbO7/5l9AIKhn+j0Vhx2KDNL3eusk
gflU8yqP9tvvVmj3Gx4E3ac2l6RGejI1J6Ypcdm/gIRee5NdIs5uQuQppj1JtnlkWtTUiLao6mw/
zHUOPInHZvFBPJQ20osJ6+QrAKLt5QXF0gLHIuy328XEvLTNUmrEjbQ5mzTBspcVKaH3xo40wKlj
efsHbK4KQANska8mfH4kwzWEziUqcFV2XnuU0YCueYHJmhXJeR9VmQBIlPjn6I9YRE+XBjC61/fA
eJG2caL+WpdLfi788bePJ0tiioEsahUw3gLNo9b+yDAHkw5wAHdKNf26SuhWpVCdw/ApnXWnCL/w
FWq4dBQyGZyL4aLXPBy/S0CChc8JybuGUlNmMpdaWwQyQwlfmK7XZ6mdTLDR8da0h+XlyH2nKjFt
JIxXWApnaPlGolYDNA9bNA98kNZ5SH2QWrMnusbaxTy1JAtxGcOY7Tuwg/bRtrqZis4ORmAvlYgR
iVJGJZDS0CHGXyqCGggVFq0wPanq3BaDnQcA7Yk0GkgUntOz1twgsNIRniVMHEbdQIocRYJmyxOr
RRIQiRjeMctSotpTOlDDtjjUBJrRN1UbIgD1Im4aWSqT52ztdeDBA3hn0qxwn0PDMKoQ0kGnUUEf
4dlOenRDCDd6+/bCH//39ESAanwAXAHHndPSElnWiso+x6xNjfSPa7HxPC4HkhDQyvL1KDBQanzz
3ReVizyP/MhASphKhZKHwQ70hlPhZHAtsSKM78Nc5q0ovPRPDLHUpS+JrGMpTg2HSQcI8zBE5O2X
Aj5za1Mw7grUlQRiq3d1uvx4j2vslr1rvB6KXYvfVlkRJheYa5fqhX8lH2w+vRvVOvB8+hQ66SYT
mUYRZYFOXJGJm8sI5y5Xdt/DSArUjg6zTaoA5/XOJY4Vr/8gyEN196SynCZ+GgQbObOylxdHMkt4
A7OC8/2b+VZRPD4k8iuddOOkehyg9XYVQ21FEZIs16/KxFnm2U+RpZaP26M+zq8T4jAteyVBcTMb
SH+YviOIG3qvSEmvXo2bx+WioUJ6NUJVd6Q+uqW1B7mF+/xyH0+4TMc8U3ouHH7SL6KS38+vVFof
UkglBfT13qlRiFGbk7SPae4CnKIeIRfFhRMZ68P/SeZAqOq6nJHXJzrN7pKcqAZVpymICZByKHaS
c2UrmNzL3eu73fK1R5m5VzbhF8ns/ZEceNGNspcsYo3+b5zmy01WlkITQeKZ5Stf8T6bemAd2a9W
Q6HBKiMEzwKM99SxKyGALBFoe932/ADTxmP6EAp/OD2+cvwnuURyhcpnP7Y1tkpvyZjp6sqQEMBO
4zvz58m79wDFdjRFrd12KE3mAA1nXPGR9mK6rBOt/IYVXDXL4LbH+UrAgVOhEq86gZSB8fv1b+Sd
xqtHI8pqrVv8OqG+akhfrxQmdfs/RNI0vuCmxzjEXOXKYgNw1P7ubr3320MwdR1gF46GdT4c84jC
F0uAtK3zflAmQ5buvApKyINC5P2R20HoeKZBFpkKp0K9SqvjYJol0yH5HSO7z6AX+viHy8d7hmqZ
IgQ7nwqbnwOvnk8GJ/Tc6vlOGkMy31M6ZZCOeaYsIa6sR1j/FxLG920/PS3rgrqyh8Z8AIhWLLVo
BHN10Mmt+N8ZOtgpxGnpdB0RiEhGccW7ytO2Sl9zQ/xfFQoEz4tKD4V88dhTvmR+GWwfLJFvaN1N
9C2TPCJ9apE0MYqPkOHna+pw4y5McKKUkImt3iWmNFvMdcPXs8XblPLu09X2fqhoNSaI9zkjdBal
sk2yqcQue1E46uu7Jo9QNo7c2YojZb9dMSq+6oGi46/A5rjTyU3Iwr+R+YJNcT3gUzigFT8eII3H
E20+1WW5e7h2GxXbtxumn7H9SbxhvOQk0FXwMBg4mkySYFQINAmJkvFh2Xr7e2LQyxTlrpXq2vrZ
5/UNQx0qbVldy2+gecEHD/Wm0uh4+s+lT2nePFVqrZKjZ2ju2EUb6ATZczQakwn3rtXjBtJX8dQ4
9WC/BtujQKe3zrIM3pBfjzBQPBkJUei1KRoHOBdUTrnqUA4WfWy2t/58ujXEEN3twTRQYkczu9sJ
CYX0AG8brnlsljzIAvHnvM6U54bbqY/bwE2XkhcR+5yJef2ag18QoBdrxz97QFaVECb77bgArdXQ
9oykFy+h8ZV8fjQstsEmCwD0THr7JoaPE/HOcSXSHMCdW3wPCoZbyIZteRtdc63sTu0dCt7j8zIG
iYoLIkIhutAEZC6DoYVwLsqjzWI0v73E7JTPnUTrpjkHICeq79APYswQhjE1IcG8XIlQiHiK0lZT
PxC5mvBK0WuWTKObhYij+8XcV1DLmwdEDq/tYir/4fVNpdDC7vqqvO9e4RvffmMKSPpQOImEsVRf
vlX8KkW+/ZU9t0mELjML8xuDOqSgbczucEJk7f5WoaCDA47LZw0WAgVuspnkq89MvdPshFoGpATI
3zE+QSMLnA+daSxgPppU3fECVVMDEG0tCQYfIZZENDeMfgbr9sFsnPShio68qpbbOjV6qpkXl5st
50yfaYSICRwEIxbE4ZZ6K7n4ESbMJv/vOnnyR9XvjcHLMjQfEzlV8XpYgYBk6dipLxZ4qtNv2o3Q
+6qfE2PeXzg5MCAuUlZ/T9UACZXPnK9xFhG25YThn7Es1LxpvFXWQCnTu4YjifFZ5tSyJs6PGgm4
2t9DEL9OxigsUFWcWHFJgYAtpDVun07LO/iMbDczKIpHcYhg3dPbQfIYC5y46W/tNgFa2F1TVSCT
R4BCfPavmoGrAgcbSkN3xhdQf76IBTedCZ4+InxY2R50l40+VFySUqF9RXl/4mfn6FxetfpwvpA8
BSmR8ZldyC5ZzgXPlwyvxL99/XIVGCCXB4mjmNX8H084rdmqcB7O1PHvQ1BW75BiRpvrgEPm27wZ
z5ZLvFVpPesZJXcyt0h50PzQ5A9AtZ/lBbsIZuyIbi63Bua9pIO7ZpdPjzbib7E45vya3nHlyXUM
8b5O9Pz4LrRfshu8CY4b+rLEXfG+RuZzYqMBDYIr3/TCpjqSWuw+JhHGl73WdXESPcpsmTmGbnxv
RMz7KWYljJtQQt6DbEyNfMcHofk6Vur+C+l3LCQ1Tmkxna7g2tTEmIkC1VrPa2TA7sDhu23E1x//
EI/inxSjZ1IENbEaigYdfqkxsBl64H1H6QEMInODB44IgdjiCu5S1d9WDKTBJAB6OxYAT/K0dJpw
OzGo7FZdSrPqslV8AATeynrPDUUzy12ydPHniw4qdQsJeagOVp4QCEnZmT+DJngSwLt42xwm/p9i
IsCZTl95D6Q2+kJW3Zw1qR8OOwkYqP5Y0NWXKRYomM8rA5gUBsIOgvYn7W/xlJzYx/MKagTtkxxD
dBAQAykAh09Dl/SYxJ1R67k+JhpyooG+yuiNZSEpomskuBm+lf62s+li21EakB5LZ7igJzFcmbFH
/US3qytF+ns+C2oJvO0DcRbTtUI8J3h+yKnvo0qUyL0zefFooJraUMJElcbagRqdkaYG8MkbGhgR
wHm9URPHGXZamQB1v/v2Yb6/pF5Q6buOhEQKZqqshUUBgvB3KqMLBkUctb3UoAhTAoTAFSqXRjVV
wHTthuWXiBRDwZGIOKMYDxyZEgY21Tc4sL+7BppZFLsdsB/d2rgIp38kHJLA3fHS2huJfYSlve4f
zB3iqW2Poi7ddwUYZhT37ukoEsl1mL2twRAYgORxxME02h0IIRSxObb77MvC9PDoB0Oz31wbuN5u
Tknx/ALgqDOnYrIpisEsIb6l1LZu5jeGKtXL/6V/31AThlonAohxxFqidf3M6USPuC0LH5YC9QK6
JRTF2gkemhYv4pLKdz+hs5jMVDm4jIa1fOL3WqeZ6vLAYl4hvWEQJWR8XWgqn6EBCms0wj4i3z5m
wp044p8PMmg3qkROgW5qnR8KB0AcK7yp+0gK+7lQyK/Ljb48HBtDW+W3eZnmsqps0A2/J7oots1D
7Q2VZZ8MGjgZYPU6i4IT0PdEv/DJAaWnx5tqIg9+G2GfQUIsh+OTX37WVexeWJO4xWm1nyt8YBl/
uBOAHdnU4Apy5yHNpxln/qInJ8aJ4XQOhQiqk4gaykQ58D8ZKCaXgoP7CNAw5dCJuoiZLno3wKMi
tVcTBCQjwNWrCvC9xpSLraScAcsLsvIQW376tUwPTxAo5vQPJIFarx1H5OpRfg/mCjFMb1+aKyji
hYcRGf3HDc21xAqDSjRDdEWDoNiopo+F5ZTB27SQ6i76DcbK43cTMQ+H0N1q4laXyK7WWByjSqAT
FW0L+cStxOtUJDEcG665b0mDZGYjSuMffJm87zdYYsdcA9jcVi3S5JjZ78ztflBuRpyaXerew+ek
BoY9KMuFlkwkGTn/MZGPu3dzH7Jo2SVbuVetzsmzR5cA/ITsOlBB8bU/CTG1rGglYsnKt9J6/rcR
+EoUnZMhLYjD1L61KxjsaS+jiWYUa+sfsIoARtG1G7U4c6gxeoJiaUv0wVJecwBPghWtV+ICWCRM
Keqwzl2NqZK97QrDHl/VLonEnKAsGV7GGjSZmB2CTa02reEw+LNmCYHIiRfR6hZCTZ+DWCziN9Ue
VYhKG+zNmvm3budR3C8HUNgxEaAKUOh/qs+tzo4kEokuxoFL6EbviC0WqH1wbR9RDXkLGAvLyU/O
DGXvNKDUGz2ZZxJWd/9CuTD7Obu8scuDWAawZunpiEAT4DgOvigYcsREyJkWEFo+6y7K4HJfXSf4
iR0VY4lvjPwzqCIS+n55a+JwnZ0+bMyeC/PnBhkEKbvfwkH6nnbop9OWg86URz3/0h0X6j8ivNnB
g3Vw29Bqm2f6XoFGkgZqVmaXNleD3sYPtolT597u8tOD/tn5l2SNisGlwT8f0eanB1ijSoV89FDQ
FcmtJVtA/pPOrAhlZjJSSvm2s1cqywZN6jMMqNBVygBLulPul/XBXPrzRuu4O7X8BzVR+WFC3deR
DTSGcHyl2XlW2osxlAdAOQKlmXpdHK7LtF2tSfYFgb9+3AzM0SzugvU3lUbpXWRNwwqY/tQX2UkR
y2sySFaaBwskbEiKA2B2ZxWfpl7PFzKQdPHNMvUSvfkIemfjYsRkDwGcQpUtBpA5wTY8bLTeY9jw
w4o+vjfy2Y4n6RzNNrM60DDPlSnoJSnX+tCWFcpO7mcgvUuxmCG1nUcN2B28GnDBZ/7lqNMOEa7n
iLafwJKMjiLFdKYfMc90PwDz8LYiq9QpFW0QlhzLXgiljeYSFmt1GMqt/HAPMofAYqPH1jgziBRD
3JImgoPyQS7ktlXOQZihlxMYdUtZKKRGjoBX0Kj03jV4q+FeNEdPaMcup6+lN7XRegQWItUL8jvc
U5fZRDA+QlyD1nmgUNykZqk+iZh2/xKilTCkKgeEdhBvwSU2sgEiFBpwkI6tii4IACeHlR/2E1qh
VMhTHwdO2W7mxLXkRW3pJJNNnNroOMUhJyUCZR7Z7QjzfEP12wZgeqBarPeUI3q4eFNWT4BkLhxI
0WIPLRqdut9VkcfNZFhhwNFzVCueEEFfTrS6+b8F2dGBd9sKDIM1gMwWOBwO8jH5RGQcjChC1FA5
7UJbJlIHgSIzkqpPcFbxmRQKO1jetTjrs73dyo4fowEbngX7gJuCnDDLLjnDpax4XfgVBf+0PyEA
It2gLwpVBg==
`protect end_protected
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prj.srcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 20 | 30077 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
N0hMcXbI5hCFMXvbzZaWNMXky7Cb78UlPrOh26mC4IyomLPXkDt4pohvBi74RwhMjj/Bp6A1/EjU
BW4AL9d6yw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
O4cgU289ETKimPPpC1lQoWfngvpNmR5tUZAEw+00K8UK2gEeqXn1hb3g7AZENGEwMii7hns4XQy8
DXQ5xw0Yp1Lt5kPvabj5mKM1bMdX8dvR9NHP3g1Qjd7okAVBl07/JG0NTnpHDOfWPgdIKiG5gomz
/inOtmJ9dyw3SQwornQ=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
DU+IJVy0UCp9Ru4O1AHH4hAsURQvG4KWjfdJuBdXBn/Aw7vf76lLrDggWEsh/tDsD2w8gcTI1KZj
gte8Qz0RBjJA/tV/Q7C3IGP9sKs04WbpHeToWiLkJhGVSOi1cfBwcXqun7kk3rw8tbtRvnn4LLnQ
VVSnOUM0P3u3t9b+354=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VU2OWBPAFdMWY9YsdLW9vHBQultKfSyqJgSm8GFxf210g4AV7503RY1sTzcwbpKduWx2mEapVrlR
2+Drhdzv1Rts/cH1vI36ZrlUVzIXAPfly2Vw/ZI3vZ8ecksIx4K68q0S13FJLdHLryPXLuFGokYw
gCOZnAxTuOQQMCgsJA0iDJVXFdmLXzqwRYBXguqf1r+OMVPXs57gcwlgVB8r2wrtRxBvH0uRcmEd
9XDbIcnUXETCLhyRgVVpblWBh8bZbcQBY/zZZ/sbyAPD6J7Rp8CEPhLVVCsK4EjNey5PsDgo/izg
h4bUKLC5eF2W7tVckgp7jyOfw3DgIr/wn7RxeQ==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
V2G0fgDEE2OFe05Cx8OR1KsgdINzVEXBIBadpSnPXIoTc7xRwAe4/VP6V+6MXz0QrLZuQHVAj7G3
9F/ijf7v4vM07B7zCCzqKWXPOd8bPZE51/A2H7Mt+ilGqjbh/VKLmxGs4hilsENWISKVXeBdKnPY
gj2HGvaphMJpBpJwjPAKBmbUyTX5Sd9nNIMzcSRJNulwiaiEOrABFlrZOI+c7bZY5sHmVeOtg9CQ
vhwpJiZDt2xEUYZdJ+nAzC0+NS9jg6KFWoyyUeNOwHZC9//fhh1MCUzJ0nZg2R4hBpRaxLZstp3w
PM0at5MBtCkDuhRItVUmq9A0HtCUCEmB412P1w==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RN/6I+vbSUSbgQKZutSOM516q9s9JryaK6V/qqxo3gcYd+gU9W/srRAx8TWXTu0WbgzNnJ4y7Myb
hqdFZXcfJ/PxMgXPrrBTM9dc9q6Om0xxWrgSNxYalV3KY2vgAYOZai6mnccqhDfT+ZicibnnsYmh
yf5l9IBMwTbxQ9cpGytJTrr0jtjFG8izeH9CEj3vxYZQ4tA0TFJhsFvQhk2xXEnWnEBhTQbSX/B3
CADhGzXitOUqpBt3ylEkYkNM5wRAzze9LtBQhOCFWc4AJq4+3/P22qqco2g+VSDFNt7Sbc/BGwyj
q/3tdC0FZkEZB5DXnSDvgc9OVq2Fggic0aDyNw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
0lfuWTRLbdGpP+bt43o7Y3baOR3u7fPK0pBLqY7uP0pQ+2ht0P208f6mMmjAZkVFJU5i9ZpW1tkF
wD5qhRjJ/mff1za19WGTM8NEjj3Lgv2vtZrOQlSeCSfLEOAT7NsfQ4kQqqhmT1zaHkk89YCN8a9q
9xPGyMCXJGJSQ2huwnzDsHOnhWHlWL/ilzzMT7dDXnOUeGPNVal/ZBe72iYJj4f5eoRHew9SvI0S
Ut2Q3RHzpI/teRWNAdgVt15pdsyvyo9uqAtiHOlP5A7uqdndV94bWqKkoWPHzcYQJvuE59QFQ1WE
cr6/pK1peH4vFlM8W2tuxlyW6OcL51xzLPEmg4W+8TkWa9OFYdBlsYbUHYOc3tMeeOtnR5C2WgJN
uxU0Mo1Pdosa0/c7ja8j39ols+/uBkhEYy8hbWXRUa7dOAQ3PE920SjzPMeGxb1BnlgMCvr/m4r9
Ubn/TP99CteWMzrL6ZpVoWUIoukbZMgqMSfJHi1YJqkDs6TFjJsfUhzmW581OYiW1j3C3OYLCLCK
oBksaAsNUUcBviHK9jSJBuZ30Pz904QILhsG0psuSICS+hNgqGwOD6MLn6Lf3sb4rftwt1kARblZ
3yi23yicRqrkKfPlVMHjM5+uNQpHxp5eLdClNs9lw0NC2o822auv2DzRUHQkLwTWCJpmKLnGmOJ+
d7s5CwoI9pLtJnxLcuLxnvUS8HrPyy0cE4y/+ncgJjBLHsjVfn753do3GAyfbbl+HilGJBCVlbPu
MOgSNxucReCoaY0BjDf+WH8IdlP6XUysGVCru+V0OfA2BYi+tNuRPmS9CGg05mViNa4HvvOv8fi2
TtURkBzS3lw8EyUhejx1AX5UG30FrlrJBrMguOiK4HORdCSOxGbfIBlZssLeF1cObZM37iAzBiKO
QRT5kneG8EgxdjC0ceYQu26RlZ5NJeS9kLjDNXuRgE0V+aPkjl39p0ZWQDSTnVlx7ytnwr3ZiJ/W
QT2m9mlD/5ek+JQtegloHQbu35GWW6aLCJOlRgj4op8Uw/H0Igi3yY9NBdkFigZ3eprXgAfgSI+J
jS41wRxrjwBfTY3s7yJNNGNEGv5Zgh/YmrRMNF7u4+z8JIZ4ugBrRP1oV0hRthi5aaNS1tFGa2p3
2MNApyP3+QbBfjKgB4kYdsHfRvuSJHFfsaS5bbaY1gUKjw9/J89vxht0UMIWLQ5j0Wzsw4dTTSSf
jtnrWCWP8O84mPsdhFVVwKWqb5zyZv+FMQ1SXDlR4cW1wM6ztREdT738MOR1SAZr1ZC8NVuBduMY
QIT1SasWBzzvsV8ybhuL//DxumnlzG9PO5StfN1AEpgH2FTFuu2zj37p2rjkao//ExLhgh2JpKdG
PcvgsMNVBDHmjtopEny4pc6Utsii9DXZ6ZqDaDVExyjcQFqU52tbbXIaAwgaw2fYgbSGKaGT9uNz
pwAxBM/34qbtQWs/SNwZDVmzBqjrD8Jjqu4VZFrrvfEAgcD8KOdqW/PSCrHLIWyOwgMc2ZGnX5eX
RQwWS9dA9eYlcLJmR8ve5QcjRHYtoEpD1rpJIXrh24bKV0qBaE6d/cbYwsOL/iT76TNVwbkP5twH
1Ejf+xftsyMXQxZfGDYdju5MTjaf3uP1i0hYJUl42w1++jPvCkeal1oSteOdcbDC2k49HvrZ1UA6
Gj8BbGQbpgfz6R7XceGg/QNgfiZSvB7fQwF+q3ZrrK/RJNacTPI6mm+5+yf8UOxEQm5gGXRbHE6Q
dfFZWQQnW8YHPvFYkZbdAgBYfnBrNx9/Ws9zt3n5b1FcdUdZGkiZxFheoN25CIF0gY9vM8AsuIOD
4rNjCjwiuc1egbUGyn/31DcO0xK0JGIZ1OLcF0+YYn0FOz/UYFZdvTM3Jt6un/bnkho5Sw1DLFOB
2gQF3QA0phY2RyodT4Xi6HAzo8Ll+mGXoUd2rr+a6gdqZE/NSJl775XfaI79ohhx60Go1gdGbl1R
RDqCE9Gy9qjysZUwbv2xp26OwVAhR9t5fQBQbNIeSO116jBa78ORJc9mFuR5S7S3yvrQum4aJQ9a
C1rXsZmuGiGcUBb1fixLoAnTUm4RsRu6kI3LjDCuh3qQXQ9YK+KyE8LaqPCE8mAmv5DC2XttvijI
7PGW3xw5V0ZAgXPXcYjSXI8nF4Wh6mfOtm049GvERQ3XHWbiblczfGvg2juTK5T8/VlIIRLpzVud
PiNsETaTbbveJyri9LiyelqU2dTfC2o1T7RzIyG5J2Ru38q+RsSHLmWDBk8Z9dYPoSP2ixAv1ksG
dI8nTwEAQHxXTfl2myiJUwBTZesMlzdeafiOku8lXp6Gz6e9EBLfHjKgr7Yl64Qzft1KwM+geBfk
mUBVzQICuCpsPDEe4DYMbyS2Htl/uDQzxUl5z3OjeEAW3A9PfndqnM6KE0VvmPj/FMNkmyLzxcp/
y7N+lhsMtpEd5sKXyzOiV8mnwKKnwzk+6QqR2A9rkgAhUjcp4Yv1wbSnyntzAhyBTUotDMLxe64D
LjQe+wtSnekxoabmFc7OYL5vJQHk/8ngcB2iaO25X4wnubRRwbfSPBxRM6pU8ZQtnHboGJeWhc+Q
3HfnpTys3IHyAlIXWkwSDVbtWsZAMd3XOvdlcoDzjr4Sx7snBfRD8A3wTRBTn5TdhG2xYsAqtAep
iTlqEn85MdSA1wSQv58MJ0Kwtuvu9T/3U0ghJbkW3z2di28qlJcSFmz96dEnIeZlevWHHHl5ZFNE
9EanjO3xbEa0h6NZnqD5PI+qxNq91qVL2+Wuy274uT27hHo3pcv1FCWU5SjPunGzyD0wn3vtHxfI
37Ly+WGEthwqFMtmE/Ojqnbvqs/aMX/1I/25EVk7ryVkiufd81KLfvwNYG4dDHwMTkt5wrR5wJ+a
tYYFePQmMX4MscXysY3cyMZnSe30sNxox8EJv+UHJjqrgEaibIxi5XSoqlcAR0oJZOV1iNgB60FT
TwcxnYiTGisJ5hNAa9dSzQo8Kxs/S1rrW7eqCkAmJpsNTl2gFFAMyvtbxHcRN+9JHGWei0Hylnsw
Wg8gr6DYxLHG065R1pTiSgmO964HH2xue6iSH7mgfIxaRwapkc0pVF/Fz+M5ksSjp3HI9yLdodwM
84a1QeTCZRnSZx17NXyfLmzkznMIBD64raCgZiwksclyO00iVJYo8uapEbEDji+bFePmFNJAnNpR
LwvAFQYt1eOg9C2Kf2ZOuVZmRDCzUcd+pBEE+dp71f8D/TwCY+fCaSEAFJROUoz8FgS+vCNG78ND
vw9Sg2dFCdIDW0SRTbcQEte+5ZB26thLHQjTv2BuRMNyjVzq1BeaztXrbIgrVIkSNqVmujVt8+NK
W47lIxkODvUIxXaVIoU5R2DXudlNhBdWmUcnTE6jnLPLEyF9jewTgQ4bxqvvf2QhVEujXXOe58Xd
FrIhV92MFR+nGK1U8RdsqY4C1hbbWlMmSSj1DAL7+KEi3RuwOkZpR9m/mD8SyqReouviaP/e5J2c
6BPFAyTD6QHGbqYxqVcBOFbkYtARwapEIWkqu0/0f6UAiHighu5Kr7+oJf+94WAlgGo8wLhAq34k
W14pNfkWNeF+jB3Ctx2DJzVYLimfyQkLS/oYdN9eeXqHgC6RmIbiZ71380zV5+ikbuSunuVbJTGC
tyilOySkOQIOZHxxHDWCcTujl/netKRiSXm5f7ctX67UKkExlnqouLufKleTlJOgT1trNADOfzoP
VQRpP3JLaG5HUuOMLst8qqRCB+hMUI/Yw+NJgmElpjtcmv5kkxhP43ZZ7VIkcihEzj2z3aOSMAwN
sbnPgC97zgzvee+CcklRhwtGpnkRIWj3SxZW8y37boRC2DAIgOTMN3iCCf8EKeM57JALKebCBEG7
UxF4ixdrn/jez3dW1A71oSTo8SfeCLkD6ZxYCqnSwySi/vPocb8W4UyMX7TMv2qcZ4RzIG+NG1x4
9rLs4IFfQ5rLa/0SVO3rzJmL+RvYrfIzG31QyXg9G3AcHg1S6QpDPvjPeLoyunG7g0uKlFcgUOEa
VgE3yv0AscwMlXKaLt6qI0b21GhCmfdUoVCdoWSn+/894q+PbFnljcq85caGjQR/Vt85RFZ6ZMC6
218JzA4WlRUVrSFqp2WjuvOCdf+SH4xKMRWBUy1+APeDhMocelpwhpEVibK4rZr5uu8HCNm+2afQ
8WUHc5aSvGclQJUrO6nUM+03dtkfnlLA3qT3P1F1DVfJEuCt52WWLw54OY+G8flDeBWz4JZv/MCT
Q1QIzmOsSjWN/LlR/qmZaSrreKdkqL2LkspKqPvL7rB8mfCg96S6zeRtAJkYuogKgO1m2HU/tRMw
EqMvusXp9ZgVRT/GZ0VbwSM5jptGlZl3Ty8xVmyhzAiCyMBktZeZRbT28F+9LZITa/WxSlPWv34B
VEQwrRQBwphx0nV1+b+pKSFT6Jp/Yb0oPYLUSs9GRKn3ZaDXni6GeSSjhRwKwz/GCJL9opu7h0k2
5OdIJhOVy26JnWha7VXKyMV4OCxXiWjGY05qXLy0OoDhkQGfbvo+iaGLnMhAwYOFUJwFcJT7h7FS
1a2CaeiEHnC8tYsBY0Yg3oEYeh3TLg4ibr8kmIPvQQ/97lgLU4vC24Rqs5akXDSJrzBEzjI1QNI5
yJuBNOcATW5GwNdCokxLUg0NCKqgp05fmooxxuPXdX/uXKqp3umNRveHnGX4RP0cNpx0ANrrl7YY
vgHnH5BUOKaSLBU+2SYFAUis7BzzYSIect5JSivfpGpmq9KVhPMT9j0kOooIHu8gdmTeNKvCpeOE
OQRWhbPUtM0drC1n0lX7zUXdXXR69EuxPxR2HnqiAyDHMqpUsNNOXVlCd6iE5EYPJnwY6ns0DlSX
FnLFqcKy/Eje49VWLVJKORPbYXYtxeuxwuFrJMVkrchJTrqOPZp/90Rl7LIlE8gjc//RSdps26Zr
Wmzh9nRsvRcYaZrKfFTeo62jLTP09Wu0NK4KcKQZm1As4ol+7rkwczvqFhOE5YDzdbhcOhXEOQVm
/oou/hzQqKfKr8iv7yUwwu/qkiCsY/tapd0O+ExidCIQNyBocb0A5ve2Q7srLiL/Mk8//tTKKjrS
f/K54j2UJPhT2OrYsDNSvllrOt8Edn/u5OAgmxWsyDLJjX31Y38qvdWE5F8VGFHxh2YAYoMBU3n2
lw84HRR7W7xQI8bMxlHa7smbZjzPxmxYgxH6HVCXUwLeCMCMA3+ZvMQay8uL1vRC0yrBM4nysWSM
VySKeULi3Y7CPYSUq+07n7wh6rMzM4nEgiacjNs5YNpMn9KAqjtx/qh81aKrhppUb+mDeGvuDvN/
8qw8x+e2yHLgIuYfAEXjowqVznGoV1OyVaiqkmUncFk1q+br/WHuaXorpr93w/iAPQIaWUc7arle
GtYAPf2vHgMLbnxqnm5d9/rwDoQdiaRfSGZ9h4NpNiPkxK/C27KwIPUceyjDYXlS/5BAEgl+DpOS
/q4V0tIPUIUpcVCcz7QRz5suZbbiISstNKv6oe7tTg7f4jItMJhHDEjwQaZWvePqylLYjQW3g3FV
XfbgvJcQrPsnoFFUqN30c2DENHmGU+lFZcloovVRc3li07kD6Zw4ly4DUJdlh0CBl1hrdKuKErRw
bNtBugM89rpcMlo/iC5LnBPsDBUfEyBLldt0laxWQpYI4bAfcZL45R/Xjen9Q2G9Z01K8snUg3wA
5LiB1NOcjSFIACRyUaTD4goTq0BBV+Nd6i5jHkdXzYgjHvNxhM+FgrcTIpceJk6lv1I4PVqGXOId
iC/EME8VjcG1Pk7TkTtFbSNJMf/UewGABatJVhEmXI5ZMGumtmtcC0Oz+xE0a0casBpdwGVeHoPC
DW4WbzBd8jvzP5d6RXkcpZny7y19FynZ/aCRJ7MwBZltpJ67YokGQPsQDQTzWGD/onwc3+Zmj9Ua
MJWiSFWmyQU3uTCRvRDk1MQEhcTfV+HG0+qjFXBnzwoqOxAklfFCToFjZ0W9Ql+EPPFDTHZkoQ+r
dzIWuyAIhG+bPP/rPex7nvKG3f/iZZs+7iYG3D2TLUZwiWIYagqOS7GKFr1LSpjukw6VD11AUemT
6KdoCdPX2m+HdEfhJGao/gcR66edFAztTE5jz65fklKpaucFCgsrfJApvujW1HHzTxpZfyMh9Dxf
XHabki4fd1yCUrt8Ap93EXmR2ecCwrSCMZgVnfFwovMf04GRUU4cXX+eQRiBxylWgFRD5JmVOymg
aqA2NG49bhxLjrySjywlO0yZccu2/ZQsnDl/UBK3EZdnC89c19UBJzFKOxUQZIbJBOhTYgBpHwZ7
jEYu3VRVz5N3EKoUb6Ga30QwmANLgnLoLHbyYu5VqEOwnNNjkWVMyRHIkG5ekraCLduSRdPX9tM1
dL6lz41PvoEpInwJjPrQaiSK2afapY/25LFOVXvwgM1o1e272oALGYrgquoYBnVr0wOQ4cuFHc8h
lfP1ESCYduobhKCwDKN0awHC7buTMHFw/fujKErCw5w4G/frYBolYlFslmvSo+xpDk6uJAhladGo
dGXDlQ3fBp6tm92BxaY4Fv7PniU03p/DSRXR/waJO3fGWVjDHK7ZSDn/zihr01WCVVg75/sq2uQ0
1z0tSZ8pfUGDoVb+JtjWYMQCdKSEd0r2/rq2gYXcoX8eT6unRJk1BAWIhqcz15cIG0u6DBU9Oxaf
2stguzgFmRDjfFu2o6zaug0r9wm4y7a4TLKgb3N5Lz5Zwasl38dI7mrkyO/k4R9NihN4rawufl1S
FqKPMT3N+1Gmk0BBt4I+vGXW7dlQgr98RfHB0o++mBR4Eu+9xPNJxeU+jekfHD1+Pdf4nde3GliY
gqAHbuFDmm1/5d48PxVSFxrF8i0nsAVGsi/viieswl69ApK9PmclFM68GEqfabZaVHCfIO4LvGhJ
fROjCWdfbWEI+uREskSYuC32su76rERwa/JyHIonuFZhVixPN0rBgM8scpF7lzy39KJL32cGzm3g
TZesiOMDrHEffTOSA6oGndKA1gJBibtcx/s5H6IM9a2iPY3uEh/XX7+5Xgu71ML4nZCpYXnCHOCZ
VslATI+VyamTdLAdIoLAoYcqDoKWtXbaYSu0CSvd63J2qw6UV6Qn1ugWq4aZb7pH3iBFJ2HIAYd0
tdZnGgwkZQqNiKYoXrhVP5i3q/No8Usl/4wtCIQ2TYCDUD9zaBIj4aVpZ7vwBowcbbJxYLttNILa
1i7SNfrdoKPCt2PNrNLIZuHnPHODTN/wQkrUJlG5AjI53qc0KfohR8nfOVopOvLyfpb0zxkuJnFp
pGTjNIpV3bpfjo+Fd8OtgZACCuyNBHr1ZJGGU3FGvuX01P4nCc0srh1/b+QCBb4fXCUtDmmN1dcg
jdlAixd+FZPJR0gPQeNzOYtrEo6K0ZCLGvPkBbPW4Hv1s4pHNJfmVvbla4HCq8luWMT5zyVlYIVi
viuHXelKGPTZ4oFKUvL50te3fZnSeOi4ciOkmq+wsWrU3ztyZPoFI6Ons/cRMiIXsxe9tSMmDYPC
DQ7uuBp5IWKYLOdqLF7dvDQiXXFQRvamk/Mo2kONRD1EHkZ7PN4LflbuCQaEZ3ZgkKs/6wJBjXaB
RyfqTb1pJ03BYXeyXUTW7y8lzay9kTsefuv0O0vDG7afyHqGuOdvpE62YWPu3TnLSMg96A5Jmv8Y
zR0mHGqxOfKTFDxG9Y8waxuA7LsnnIYfvq1kaZFz7uaYfy50dAF5n+/Xyn///WaD9GzNWurzdsUc
+ohfpCDtl8WeNJNAruRD9AATeoS9r+2Ey3WIKITR3ayS+CgdZIYcjQmEXxmWbKK1tXWCirccJGbu
7Dq8YtpsWFi4LzqlugRlUk8wU87/nnSjnrUWnIkK09ehQou8H96aUTKU52swcp4CQpPm0dRjbJTM
URCLQZql6xzLV9O7gHPjKtfapvT/Ckxx4ngbcdQt01DWqhDTBspSQaFFGWPoaltZiirFpQp9aFT/
zO9HII7epckLRveCNnnAuCKL3nWkXMquH7KQ3Cx8qe/U4bxxqDXGGMBBGejtFJ5sIgZ4Py080lwV
ROUeoDTmWtIlEA8mrEFY/mc71foOMrJYVUmlFrr85DxGJUjV4wQbZ7wYJoGBAraWeBpMd9csmHSk
IS2NTziEKYmQK4CTekR59Y/HM5jDmns6TnTXoQEWAwXMaG7lEkc2jO91DjsG8SBdVAo/XbGGe7E9
9PhhvbTRc2NHrce8uRacUzWOfTQgf7PAecoSnVtFXpSVqBMsr0FT1+i8ti4JKAfBL4jyJgwRP2lG
9Rfivy1+owc1VNLuLGZPiDHjwN64QWJyHJ55ncRbhaE289zqPQFaneDs9frfi+TPn4sMxdAWsDeB
Vgn1LXv8sEYdGYUxL6gB1+NBAWBukf+25jWN3xUOiS17sV99NkRnamKKnBA6/10KLRwcB8xt/EHp
jmANfIiTOUA84UP0eE9x8bkr4QOUVxB/g3/wMA5J975elV+mE2jZRkILHYN5jvVxGmIvWKX9QJI2
8COMcoCU03lXyABeOUtfzu+frc6gRBAMlrdOPgTEca6ZsR9RjLrpt1ufEsBS4+48vqGjKxXGnJ2O
4gzTMbTc1ZdkNqZeWEXu5NYx4xAzucw279wL9kTklqgsaz9VskwQ397UO+fkAzLPClxH3IetQYxa
EjLu59/MG3WtIYy7BCBHIgQa8fuaIBMsYPq6o9YrYHeHmTKS7JY3cvUq9/ujYOHa2tN8WqZu07PG
OWh8pC6/jhEvXiXByw9idhs6Hdzq/FqBwYAQrV8DQkN8+2iDEpC1jXrdt+PXZS6zR0xLyZuBjugR
y+AvgT0lZA9p1KJHU7XmG3qDujg5RRTnUMOIDD5eWjzaBY7poeCM2YSdDLgKITeVkDqkwMGEkHmb
UoDICkXDNbvBlxF4XoLYYFOVZhQxDJTdoCM9FS25ne1S+KCIIagUb0A5eW0eQmJJxBbZu3KZ2Paa
aQO4eKhijlPdlNEvYZQOriwOdaimq8V/iL0ZdESOM8mX6gEO3MfcmiH3p8dgnmelPYfK9GPDkdSu
WZtpbgeiMfR054jNM1QPWHyjy+3AwaEOSda8KQZHIli2a6CNZcxmWxDz4lUM49EqhLK13J7Fdmgs
29U7y6xacuxc6bhxxuDj0m8673anhcELLQpKP+YvFYus7B+87fdb9WAM8/OhC8Gf25pGm/qxwoZS
eLSsdhm/nF3ASPP6KaXnFsSu4VmmJAgQZkqWZCRaWot4dUWKWsdBlJhX2zUsst1r0myqJEHM99EX
kNijkQfWJ86uQwllRxZ2C4LfAUmpZIll8BVB6Nsjb6z+p/uogYC2DPBEfC7diODko4yKiMthHvZx
7tSf7La9hZGLMiwztCBtHKITjtCQ2H60n8daAubd3mqayiDrrnMxbMqoRZmK+g4yeYChWY/UEmXt
ExQ25fxrzfx/tT7g0aOwHBjaYIEjiAx9iZcu5ke9D/jtgLb2uj/9ykifJAFNI205m2WGyRNvc5a8
8t6K0QZSI1aL+KXcd+i0AnGX4wP/sCJy5KF6+lhWiEbljYwcte2vydYvCQbCKbOtXYje81dQswLQ
xalwZgasBo9UeR4I5Xz+b/ZYpxi3C3zNheDLYXOjoQe+sPKLB4QNDgnwv8zfSlHZk2CVMCjIhS7T
CbwBkuYQCYQQwqRAzI+bbMp7c/7OD/NCW1t/9b/HGwBnPmQXSEWMXxObuX9/jr7w5p1T9nzQ3oA0
A77QrYGfmHXlEDlBULtNfcMoTqOPjb+KfxFitc3aeLS1QrNp+FUvMg/MHEQmp6+McxupYj7R6ZFH
aag8kMTPhP5ac76qn+xVdDf1JtEAyHFijZ53Xn7qj01WTuqoteOc/XWrRhapwDSbHb6GoYokpb8k
JTfPdYtmMYg/xvS9ZlRB0NKbJ+R8rj4X+myvl79STczz+YCEQSp/ex8ZklB3aR8KdgsNAqhQnLbj
rWaXXcWnConDm23TLADSttY3GayD3niWDCevDGsh/d/3g+cIgcrr53UAtbOcJ7YA8cBKPk6R3ywm
cqYa1vGWoC2zHJuCibQq8tdl7wOhbXnAVv5nYE0PuIkQAVpZoscytDQmwKFoa8deBMqkuVDZcc07
l5B8L9WGSl2r/Z/oqyxUUsoHLb4OUu+R8jXT8H1BFhJeFp0JQ4fP9BtcfdB7dq6v91AZ+opzlwJ0
1iTjEuZ/tDzsf9Cavv9QRYYVoEpl0EFxOKN9R/MkRx0BZUixPlt2UssLtWzCUG24lA5Wfmo3dKIT
IEt9+n5BhTMCtpx+E3LlQm1a+ZDnpa0wLnkzZ5DkIDKWSBE7vTCQx1+ScM/VVdiqktXviWKUohPI
Sr5QeAGW+Z++OxjamsIqxf9t5EfBQSbRFfL4vot2DgktyWtrepeR6FkiDL4CMe99j2J/A8RSAdJU
BbrKMdSNs0C2jiSGHXa+uxXlo5gimXeb7BpNy+6SsAr//bOmlGHgsopq44bFREZ4R9C6GMQckwjc
meo+5fyef+qGp5z1tLIJNhZGDltpy1wN/W/3hCSWXLY6x2d+3kW2fc626PCpJu0vAHZNaCdid/Vc
Fya00RwZBA7BOWL/kBE654kxwWvvWou+uObD7+FXARube/WIZWTzsTj/4Q6Fh6G+l1ioUa2zyHOb
RsjWTsZTdcBwcX4GfHyXD8o44Pb1NwtYYZdGJmMNAjMLNMCZ66sK5rEgy1fSCpvxMxzy3ISKOWxd
Y1YtgR5u0L2dAXBb7jU8hKywSgkXpDSbzUthJwQ6R7veSuFxxrO2z2mgKwodpLiHX4jLxK1xcqOQ
pSLnOPR5Oxr8yJRnFK4gKRrtoYeQ2Aszt8P1J/kfTi8gUmTMayniGnHAVQFX84krJJ7sv87uyqXA
/ujgJOjocz6kUfkCBqf4RYGY7qv5eIrzwhVLdsL9Fbl1Q80iPTzdjn6cB3x67kvEc3x4r53n57M1
cedGQOH6V2rLm3UmNTBO6DYABMzr8YZWIs1k5/07u1/1/PCQ1MoSNpSDmwTMRxUIxW17+OpMD56R
rDLV7/fYfFT7K82qlaKaDC+7yxmgwyXZf4BrQaQpXX5nmdcdii70e8daMKy7GGsrJ2TVz9cbVlbq
fbCSFpLbm2mMVJrNHf5LRfdCIGG9cvH4svmO3ndnYazjpdLFgVSf+ScdR7Kf16v6HX3r1R3l1sYk
OguVJC1L8m47lY8SKfeC7tRgZXw/bXe5uLB/pOetUSjk+KDPCWnRVKsh0OPigbZ7o0uxwi2Ai9J+
JDK79X/P2Y3m6MZehjzIjJtgulVwCr4ofQt4/thWPgvGiXH21H2esjsyOjoqU+7oSPFHk47EaQhM
UMKIQVHzPyLdf5csq1qGW+gfAaU+3NW2jccP074NtXRdm48fUyG3DbACNWKSnIplyvivWLIDooh/
Qr1Amdo7K97IuTIXmHeCclx4cBCCRhLU6FbJzxhS5U+AOVQNvhFxOadhWrEmeXPSy5MTwN44YpXu
d5Oo77wUpgXIVFH5uv3HI4BqilieFOMgyoFtsCltRzM8R0QpuJpEuwcfwdxvtBYYGDHduTtHtn6V
JxZZ9PCCGl5eHl0eHqrJhp18HiV9nexp2G75NEuXs8Y4qa3W6mnfg3fI+t+T2+/sF7DlK8LMNLYk
FwrJ/ChY5KXD+A3k9DjYuuBZKHzrgpyzfOyIDoqt14OoCh7S5j7pWnGrnF/d+OERJJqe1XWYnffA
h7g1MO1qN1QGGhYaeV+dKziQvqf4+zGsAwGYVME+dpFmIBLCVPZiYB7PzOnsghHcKB7Oc33KXWQh
7Q4o5fgOBITG3hFgMWNA7iKhpQVvMnBisqjmLjwFMBOSfOcUel7K6UZMpmk36Cw81B8nYXpYlzfl
pBk8Kb5ZyteB1IUP2fRUU3ivrqhHB3cQl/3qPx9n1PT1PEUz/224NFCPCkiUmg2AMj7EzJ+IW/M9
iTkWnVCDMd76ZV7muGHN3CXmsya3wau7UK2tJu++gJJipW4UVZ02zv7nC96F3k3A0Kwkl0LdS2aX
Kr7k1qqEVyUZBjWLzetNASmbPRCk9Eg/AOln4bNzKdrtB1fzRbDvhXUMIVF96bwZmjfRAZ/qC0bK
/EVfXYvtMwxnOPPTCdQxL1aIj19e5Xxp0HlUaQavFsu6z2kXxF4zmYsLgrI30eV6s3hD85kcRiLf
SZiaVA5fGT9nxjOX23YWNL/73GzkdZkpTjEK2PUXk5i71UxIpVzVdbZ6a+NRpWqPxLTJuAdxDvBV
Df/Y44OfDtqLVu7vZTmWOq5hHrBQvez0mzwNnXpG5TYf2WiOKtUiaNInIF/rfAjrZUAn7c5TWIGr
d/tWRfaqF1EDuyt66xzKl/8ojUhKSQk0bmOBx5HWDVe21e4KBmZWi97HFOoPmno/svfJCRAgCZLY
95SAAfBvCWx1i5f5GYYoTC2HYTr7YYWrjFZrK1hIR34G0+KKQWxZWm9BF2dT8jzMWU5W1W8pAlSU
w2Sq7FbwttFN8i2lnGvS5UfcXSayFmgpss7qr+Zalqw9lkCqIakOMOvRCar//Ty2JFfeLxpQicCo
Unl55/+sWjHy0lVBRVAd6BbnW84I6VexZV5uFe7HBs51mFat/c33A465exwSzt2KabP4Oshdak8B
mJk2TNMqaqOVMcTVe+mfKDqAUfaPZs3kM+HcoYrcukQVY1psuL+H2nJPb9AZ0rixhLdk3yBKDeP7
XxMB7CDkZCwZdPtohafO64lTmYUmxyH4YLnflE1WXs6GhN9sjmacWhln1zL7TPi9TP57M7S/yzPC
xjdS8liHPF6tHYjTn9UHrE4kOvwtsLFse7XE0CRlVf9MZjlzpmlz4nBGR6qVI/rqsQ5FYZf4sABv
enUpLQ0RGQaMPo+Upyd8Rde40L7VihAlvL2gjeHekMWOwvrz0khJI9/YTDy+aa2vopVObbhU3qyB
LbRJZ0oGrHNtFtMfF+Ew+LvZBQSqoOaowLXH1RxpgeGFxWpmb19gjN3R0ogvm0gkTl+K5fZLwrWL
Xd0UY2bKwLTXTBkHe/4nUwFrVbS7m6/1FIIjn+85EOTZjpvAdXr9023JZihxSfsO8V1cyPmOjjXg
i8wC5NPQphKel8DH2Yb8xhkLyt/ui34TJhR6bkY7KaNx/Rzw+Hcvc1yeHUrdhWdqtiuyVJ+sXujc
tAzu8/+woMB4zkEB2NA7KjuUX9Yl1UE/3Mm+JYgX3J2bGy+Rnw3OxqQjDnWARp1UWHOaMLcxeO3a
LbN/df7F5f6uI1/n4ExPskjMTQryDB8BP7Ve1UDT6fbkra6M6KyA4vTOvoM7zYK5z3Wge2OArEUD
TYlqWRSHVXGSgog1Fs3XNG8pqKCMdNcYhmKHKqWdUTeAqDUB8de4k5VrOu9Z4Q5Qp76CuNBPRMOI
rcBvhIdKnfIeODrBVdFVhPVJEs2Bpz/mns6vFj4YkZJ8rbkmXRe3jB7uTY/hJtoBhPHNQqRJTdeb
H9ydKsGhjdbE8v6gR7YMcRl7Fh8H5uq7U8r2Uu/9G1yai/eIBuLZ+uJcZr+2bLAW/itY8t4vyc+j
7gzgkoK3jo8ZQzwXYbkwSeuUQsjr1ExMHeKNWGAyVPqBjLki4XUz9Cn4N5XfzSSqX51TcJy7fw3F
Xo78gi9iUP2bY4lGKptuV4nzYXqu+cRuHtDhqHQv26mjGWNhctzLp5Sxm3khyd76SpKqeAkc5y7W
xMhLFCY1YSuh1NQ7szJDt2aWH3Z8iRZkmtyhD/8zCvcQkOrJOIlVI5of1xvHUZBh6qW9jMFQyATn
i27rv2zkbN88N5bzrIqGo9zrjlgv2K6VUixqS6eBTDWik17GbHg9dYPgcYSeaCROBKivdbyP1mEt
EuGc9POdiHaTBgnNT7wuf0MVMuJpcwid0im8RsrlkWsOVcccUFdx6f7uHwKtPZscoluvOz1p4BJ8
Cmp7/POzKEbvvuomPHm8rIEb++nM3EZsp+UagNGSFHItCjzVjlkBxeDrMZzgHyjvs7VHAth+V6Ee
JJVmK+djkakW6a78oBpE0xsmvunwe5M7W1xrzLnUJ7xKWn1gof12DO0FILbs9/vMLn/Tvb+eVfog
guGRfBMlz7/tHHHX2VJku8MrnTVsUvk8jBIN9hrutnLt5Vfu/ltyGcnF/rhvYwVGGcjJIKiSC//H
SgDsSHKLRd140xpSSPLAEKRmZHEj7WtVrEE2o4EN/T9gdXykUKg4rW0tuRNs4LySne84JdumarDL
Ln3x3PH1KfVyCtRaBFTHh90gXX3nuzwJIbF/JGFlCE5UuArR6kHdrQ/623JREYbLw+6PV76qGLDC
/xukmeoNCbvLYxKaa3pm0pePKThws2Md75nIXRiR8SAUAtj5ASdoezs4DPxV5JAfJSexTiO8ELaV
lzDu6zzo6WG6iyrfLLbVFVLcIL5Z4t6Ls+4JQeSP/1b4m+c4ySCEEw/Ga9pMJqTMP1/MQf1PxGGn
geXKsbv30tnE0aHL3rbtOUTIBFk+UToopbQt+AEdb7VzIlg6FBb+PkBpin2e7RZriW6fbOq+Vm/2
qDgPjT4DLPX9esqLofidrEvSUDIkuGkSyoZmrdzfNh2xV8fe1gAyn7qmwUTrHxnKV4+gaRAURIrL
M804vfVh4EeoavHpkpsQ+jG7me/nupo4/LrWrCqP9zj31FRIAUSdcJsJh5BldLHQU66n5WbPpvrQ
KQ9DO7Vt3SQy3lFsNsADLYHlP+ekHeOzPqcB2DPp+xP/oXn7S9fETmQnswe/l4MEoXZx9mIYZzDs
gAK08p3dwNsC8p7B9fRzGg77uc2tUgeOf1KTRRZMfxY5n+2Ls2sRm1oy1J1XZQZRzJs8dheuL3Qi
qBs7LlZprPt85a3ZTzTCJuxO29f2KEaCh2kpAesINiRXfeRIdlls/IjCVlWE4Ftl/LcVcRFkRWuI
eQlInc9+N1GlJs1Hgr75Rwb+HAkSB323w/PsPSBIkINq1GChywndXgHC02pQRGH3HL02T5zgtnui
Vb2cYpGxuoDMdxUtdag/bEwZlVZZtG+S5GeVzLAjpkss+/AuvI7x+fPXq6hZPx0XIIZq2p4IGobe
bkwZLUKKb0G5W+5Pw7/5pc1efMGxM5aYNqRHCmzOe3alO4vAyu+E6CLomLhDbrrtDuEdIoyTBOFR
iSlGTxx7VNMI67n8dV+BQRHkwi9l+hrFjoM7fh1Kkfi+RmhTgGqzbcMRj6n8IGx9LZoIiidpBQqR
5NBvtaVUkfkaCe/lFilVueeHuzvNkEvybXlvUJWo7FPWrP8zkJqQ+rtigydaLBIeDYXHg+a4SMjX
rq8MUe1kwBfQHQGy6eRMZ7EVUVc9R+qPrcLNqGLyywWZbE7aub0Tt/JBM6mkbKluVGVaz8HAHKi6
CYCjPbzO5UMsgBa5VY39vsq2LYqHTwpnSTBC7LbhplM5LppbpHeYKcPyr3VcHEEjblYfWyBtykIR
mJw1Q4hP/vRozWW8dYupc1jPG8Q0ewOOJlpK9ARrxLq7FPdYtLwQdYPbj2JmpWUBZjl8ENcwXREZ
mJGFg2sZboQf0lhTA0+AclqMJQ8x1Vg+O3mPIBevLCfZj3SiQkhnq3Igff1OULxu2TV5o+7PZs9M
gbKo+tWirYNFGmDe0SbiAyAD0dY0C5gtEqmIAAhAmHLpbd8eMllYBr77RZpHB8n+9uFdZYt/RGnm
IeGhFj+HDdoe3/00fjHoYcVlNz3TYuKXzr6mhmeuHlq2yDFrrxZLYN/qWIxfjZicUqNj3nM3mpMu
+dfY4klEOJGiecJihILhqjY2INjiL0IhKDhLwIv+M7QRwy+NF+m4y8dPsLTyId6/mcZYt1MKgsrg
A1HgYYnzf3ePZkl1dtpiy1G57f+hIwh5A8QcgZupgI07JtccU1HprBLEJ0LcfpKD4DxVO74raU3n
LWbDPOzA4pOV0RQHQoZ/sBrunYHXY0UBNbPfihlAad46PhS4qi0TCHJZ3B+EmdEKi9MfyDO0Zkqd
VkZDfmCb7iireyWO0hka2Ic2J5XdayoDfsleD89CAZPuZJ1WNveSAnVcJNlvZzpsAuEOeTQ7e/ri
AMTx4XLZuKKBpRPfQL/4k441AN+Dwhe78+rGiMmR1tx0wZQrZcUBZrZMQnHN43FWhfIwtmDp98Sh
rVSalJUoPwarkacUzRhBg373yp/r+FaCfGKR4OHSDJtyGz8DV0yaWu1P7jGY/voECnz3qQqqNLVm
0QY7npKcQtitlnMoV1O4bO6Rmno7GN7y1pkuXiRdfrkAAr53cSI5I2e5F4MKMfOITjXi7/7c0aKT
DEe8t01o6O3zObd5IP9yDXeigLyu/5vax7ZNb2BETNfcAF2OhPgkmHvDqFCmYbFL3PelKI6/5q5x
Spx/AvNUkRcPRzqSaw9+ajDXZVcZXu4G6KfPGsTl6TXQn7VqrobBaiWxhshbg1OZFk742z60CsFA
mgpIoHS4a4nubdudVukWHNhD9x/eE1F+dhWb3FmmMuzaNs0rinfGOM3p2tik3eudXYNLTnCBrib6
q+h1a3+GXnj+E11fhTxZ0T7TX+BU1ilXcp7ovR9FSELBS88Nb5zPRYxucZd35IYv2dyHxzhQ5HOw
BiFuUfD0GCTT/TMNDStcyMF7fr231TLfQ89daXMXIevcufflkuvv1SsAMvsVL+dSlq7b1XKerQdh
vgng+pRtLOQj6FXWTxdHFdZnvN+cAxNuM2R6xao8LBOtlzmnno1sLD003Lsmhp6tPGKSD8a411yf
8CypMGYsWrlgbMSv5b/BNFPNWvHOo004ysCsA922rD9fHv2xc61dXG+jEXqLOqR/8QxALHZ4Hof8
PgrU6ig89lj9xjMMXTBVFISmBeB1oxZvtW3Fc07IVC7EyNXTRqR3y/1UBITjPxN5JO7pXt84L42V
QtdwFT6e5GSaE3VEwJLZlbFPkrmad9rGRKh9V0Zzp6CUv10LD0DtsQxpq3BzSD3kBaxl1/Q6Xggp
5yYSS3ZvJOV4vI20IoL9s9RaY07jACGODK32QBPr0xisWZPCdf7DJI2H80r7hdi6v9EUTK5kcyR6
diME8Nhw+n+Ggy8YGJZT3w4kuHr7/EOCIe6+9nsv5dGvVuYbJc4ywL3Itd60uNJjzKKFqhZDuZoG
gcoUcgwdNS2IddrKke7Hxfb8cLdOsjqVt6uq+BeyoN6O3b3c5Z0/l8ffsL/mccvM8ukc9nQ0ixxj
5hiAZhlui4G3Qyie9Znz5m0uy8C5CNpGkZdjbKYKubzv23sgzJElTWc2h/EUtSXurdXz5tnnNSWT
8jIywDq0dIZfA+L/XaQCYf6xVz9OmrF7JDcs1oA5VemOzyIPjccLvP+HicPean4gCehHUxv2X02m
QD+5lqWGxdaLkPYukUa3cGuov4TlJS0/ZfhRxvY0qzoScAmiHkBqWgcEHje+oGT7Y8941SbJRBOH
8IRsSLe5KB4wbxNODBH45ymjDWv4EBciS3hXCUiNsAoeCrvwNy+7MzNBv6cYEnX/wAyEUow3NmT4
8hO/beP6rZ9Y2lVP/Bm4DfI//t2T94n0abH+tfm7sXFhZhbwT/RRHhlehbbTTNGM6n0fM7JvWoH0
TEtDxOQX5DgQKkRkzc2ZM5mJUfeeXtZdJvEyTR7pSlWzt1L+a15gwP+kRsEW+ZcBz5liFJocHeyS
yyvVByOmYHlNzbnJ3kGU8wdJetovt6/RtPkhedf+CEkTMeLj08/2LnSoa4xVjbPID/x7x9CYeVFC
2Y3yxNIm94Qr8ol+f/So259g+rmF5vJ1iQndwqhSWGkjPfrNIeTMoICvdFyduSL3yT36i5a1bGZo
TYk6At3Z4OvE8uKjX1R0a+L+UDNyVhcR3QSlaR70RHy6vkl8dZadcXX5/ZcyaTAotAIN6ARSHnbs
MWzPqxE43/lXeCBQtrWh7FnVm9v5Mb4XXoV5gLCNn52Clb9QRg5ATdGgADto75mYlXqX8T2i1xR6
vU1vMCr1rSRwfmtaLVbWoX/zeOGHpaYk9tAxLOSsejZvi3vONNw8+A6MZGvFRpU3iG+XGbtv/LfC
9AMg4ba3WLNssWrdnj4Nqq93BXvyyx/3Xw34+cNDgYQK2rXBjEAmEwxiFZuFU0x9SUuEob1CK57U
WbnVuOBajTQQFDKOVnO2pL0ZG7S7wTGBSVc42J/Auh6qtZlxEZTmYvGSiuyzJwP0M2BDqjsuZpg3
VxAclZP+DAJj1F6j0S6uVzuzmIcJGTsRLOmz7yK2x25aTbkaKPDEgiTaWQ0l8USrVqn067QdftCT
UiGncCVYsdmlUOvcCHPWoFPE7UBHGR2HtJeqs/IBMCHnWff5Rq8p9SiH4/c/UodPyp3bWpgBtVeb
VTFS0qXsZrIyceWT7c06/GqvPWT3fF7a+gxJGGOF0IbXc2VN+EkBLFkfuRNQKcIMlgcpciMi3XaP
0FXd7MGLvhZsNUDG7i9OvQz1+lHvmR/Pgp6MFb/l1/zxduk63jDtKUGYCyjaW+IkVkKzYYYdNrQZ
O6MygzdFwV96sBc052NX7B3zMcnFvwyIvQ2aHWS1GM2pJuly8n5fouqgjN8un1jHxaQ4GIcLdGaM
S7pZqE+P1X0+O0OM2NAILLw9ByMoNYFEyY9X8AbKtEdBKWx1Ffoya7z7h5JfWw0RY0RE9/L+wOcA
TqJY4g/rvhdNXstGIs4rxsaYZMm3VYE90ckYj4GTUvmHuambI+I25xtH7+502rqlT/nCdxKQbTJ7
JyckBSpVkElTpkefk/LDDhitrHA23vWFAXMgmZgNCM+iii5vIWuS2ndhtCElKalxp0qOTjXgLfpy
/7uQlDAUT4Y9gkU61JlwENOyByyDJIYVSi0xdAYGF3v8K5z01NwMqK/xwfkxxej2GdYkX1K+v1Zl
/dMnR2g8kvgAA/ig/Pvq3do9bGcTegdz76IfcHVk4q/jOehmAX7NfX6snWYqIBjwY2EDwHeieEUS
byoBobnLEWJXndxikq/nh5F+uj/7ShVZpqUe5hwwxMuhwYvmK/NG2O4mb4IV95xJ3FCioiSpSrFc
gv4yQ5IvOZfhHXPM0OqViYjXaCE5vVoCoqrbulUVeR+9xuzlIc+8/+qsIDYhKgmmaE6Cyx6fimZ5
fy85XlKb9CiyRBrdeuVeAUUCe/1sxT8XTzWLw5JQzlv9OfUIaQD922LkVFq7ltEsY9dz1wCXI9iF
NXLupci3cBuXSkWatAnqhHvj7hehPLTTUnQG/jnaF2AP56LWCfpmillSV3zA6UuGr75oIpF1hdUc
wEz9S+8dN47anumMriy8iq5aIaT3P/g9+z2HyVtwTzJ9i6RDTBC/+DVGrQq4msRJjaOFTC6qqTcg
MOQMrTowy3UyTlZmlvSkWKWH9gDpM/3bl20GXKt775T7L8ydxTRHiLeT/gyhVSdxI6PJGD0NjvFc
5ByBYGww2MxpybWh9u9WmGICsSqpkKFtw8mhLsKUV2Ld3hfR3ndXFLne9JZdLAF6tpd5HqVPckZ3
oF5+PuM9ea49N750jdVnaRxiOgAr4dS4P5J4DhmigZ4JOi155pgRCdJkwg7gTRHdsWTdr1S3vaR/
ImSIofSYHZXZKmDzSt5TvsekRkzHC2IMrjfDhQConoH3QUAXPMNrP9liXRQA3SGUja0UNuirD6Om
UXriMNKx0gDMwToqJaETu+M1FrvIAZxTjcWv98m+L1OQgKmn76uSFOtiMJj2yLMgxPNd37jxC144
zxO2dWB3Nmw4zDPVIMzJw5RkcGSJkL55PKCvPjqGn6TsYsw82zqKzpGzlKXzwuSD3eNoVAnQWv0E
yLMsWVSPWDAtIU55IFNUZSLrn6aj8afpckMrkH/fK7xqy9/a8/5rGZCWzIw2JaOiBvK8KUgvoVT0
vPPIsrkkaCDyefJmo46nJVQ8vOdWbfg+0uOmsyGZj5K9UePpDLEWqm5KfkkqrnFf0fhUp/b2UO29
mJnUBcB03mpVBBWnfnpkWSzJWTwM80VzOOLCtnS3dpZGdGOVRWuoLSe0zlvcMly5YfDSQ0VF7E+J
Y6/6G8lMOGxepzhdjnQVA9q47JcUhIL88CdCVSJvKg4nVID/4o8DASZ6sfGuV8GXGAK0RrPob9Zb
HS+JbyqbbABzfVPUcLxoVHG71ecP/0rbfLDxg32m4pOQ33jLzRh8DtzaiX3Hjg2E0M/5Kh3iip/4
/mvQaA/Fz3otzYn81SsG5Xe91P3rILOlJYr6cgiMPoU6RNQAFZFRHmdeWuiRjlus7UKTh9Lw3M4y
w3J8EU5erWTiGEqjyJbQIx2dEsI0nGliszODddM6HKQ0mmLzJU69RpA29DRO4vqyotDdDtSqZDBp
C67xvzcIOKUaJrSDf8OXfGqqZoeWwHfw4AThQszFZDZhkXxVV9Ac+ulnWIDkRQbsCKFW0536XgYO
T/uHRtlM/Ve3eBo9s3rQvD5F6orFyZmzFDqPmTOw89wERuRDZtVRZBjZ5sygnK6EgrYkJ425+KdT
CU/8Lq5edQogWklvHMDCUOlbrWiAT6OGw+pR6vM5ago92B7P9Zbr6PG1VA2wEIZ7zsrksHOLCL6U
wx4+Xvi6UJ7zWq6G5ryTMPsIZeIOxiLUYFA3FDeXBpspDLuu2uVjDyL+QOJqjUfSMz21Ra1vGXPG
qCjPZlMsfcCaGSJLw4yIF+fdvzbpJOFTv/Aq8yml9ffHdpHd39IjyUA4jSKP31/urOeEt53VFdoS
dYSputKIGXmsNSLdPCcCR5Vdle2MWpREmJprW1XaiwWgsp3dCd9sNhMlmfy4NADCEkdVtRYcd6C0
m7f7uEEXE2v1GwL8/JI4g5LgjodSFReKkz4ah5BK67nLkY/2Zu4U2CPGpNDLN3OKyvRwdI82r+5H
oH/ZQ3y0caHOtZ/GHEYh6haD4dhWDlSlc3rTuRVSv7xUiPgFriMrm746Vma0XLePa1rivL8dRlyX
jKtsXGC7wMyskKUvA/8Zs2v//JBP0Gr2/TsHU6DFdTU6uVl7h8PSaJM2AqHn0s987RtV1ioFjkVM
OQgWjqVMEaddpFmgpxhfbiFSK3qAOnzcpRuwGhvr3AxZ4WsRqGDTZId1HAhDRSU126Uaf56cUlsZ
kOZ/Xdo0kHlObRGgeu80A+q/Ejfa7bV39R0S6vzJ+pZVYeMRfc+Y+Y06jFA7sZ1QKGcuESnHLf3t
Zfgs6FGwGDHwm+px9cwk1mADI9ixnIEoz0OLElKbDxR5x1plbO7/5l9AIKhn+j0Vhx2KDNL3eusk
gflU8yqP9tvvVmj3Gx4E3ac2l6RGejI1J6Ypcdm/gIRee5NdIs5uQuQppj1JtnlkWtTUiLao6mw/
zHUOPInHZvFBPJQ20osJ6+QrAKLt5QXF0gLHIuy328XEvLTNUmrEjbQ5mzTBspcVKaH3xo40wKlj
efsHbK4KQANska8mfH4kwzWEziUqcFV2XnuU0YCueYHJmhXJeR9VmQBIlPjn6I9YRE+XBjC61/fA
eJG2caL+WpdLfi788bePJ0tiioEsahUw3gLNo9b+yDAHkw5wAHdKNf26SuhWpVCdw/ApnXWnCL/w
FWq4dBQyGZyL4aLXPBy/S0CChc8JybuGUlNmMpdaWwQyQwlfmK7XZ6mdTLDR8da0h+XlyH2nKjFt
JIxXWApnaPlGolYDNA9bNA98kNZ5SH2QWrMnusbaxTy1JAtxGcOY7Tuwg/bRtrqZis4ORmAvlYgR
iVJGJZDS0CHGXyqCGggVFq0wPanq3BaDnQcA7Yk0GkgUntOz1twgsNIRniVMHEbdQIocRYJmyxOr
RRIQiRjeMctSotpTOlDDtjjUBJrRN1UbIgD1Im4aWSqT52ztdeDBA3hn0qxwn0PDMKoQ0kGnUUEf
4dlOenRDCDd6+/bCH//39ESAanwAXAHHndPSElnWiso+x6xNjfSPa7HxPC4HkhDQyvL1KDBQanzz
3ReVizyP/MhASphKhZKHwQ70hlPhZHAtsSKM78Nc5q0ovPRPDLHUpS+JrGMpTg2HSQcI8zBE5O2X
Aj5za1Mw7grUlQRiq3d1uvx4j2vslr1rvB6KXYvfVlkRJheYa5fqhX8lH2w+vRvVOvB8+hQ66SYT
mUYRZYFOXJGJm8sI5y5Xdt/DSArUjg6zTaoA5/XOJY4Vr/8gyEN196SynCZ+GgQbObOylxdHMkt4
A7OC8/2b+VZRPD4k8iuddOOkehyg9XYVQ21FEZIs16/KxFnm2U+RpZaP26M+zq8T4jAteyVBcTMb
SH+YviOIG3qvSEmvXo2bx+WioUJ6NUJVd6Q+uqW1B7mF+/xyH0+4TMc8U3ouHH7SL6KS38+vVFof
UkglBfT13qlRiFGbk7SPae4CnKIeIRfFhRMZ68P/SeZAqOq6nJHXJzrN7pKcqAZVpymICZByKHaS
c2UrmNzL3eu73fK1R5m5VzbhF8ns/ZEceNGNspcsYo3+b5zmy01WlkITQeKZ5Stf8T6bemAd2a9W
Q6HBKiMEzwKM99SxKyGALBFoe932/ADTxmP6EAp/OD2+cvwnuURyhcpnP7Y1tkpvyZjp6sqQEMBO
4zvz58m79wDFdjRFrd12KE3mAA1nXPGR9mK6rBOt/IYVXDXL4LbH+UrAgVOhEq86gZSB8fv1b+Sd
xqtHI8pqrVv8OqG+akhfrxQmdfs/RNI0vuCmxzjEXOXKYgNw1P7ubr3320MwdR1gF46GdT4c84jC
F0uAtK3zflAmQ5buvApKyINC5P2R20HoeKZBFpkKp0K9SqvjYJol0yH5HSO7z6AX+viHy8d7hmqZ
IgQ7nwqbnwOvnk8GJ/Tc6vlOGkMy31M6ZZCOeaYsIa6sR1j/FxLG920/PS3rgrqyh8Z8AIhWLLVo
BHN10Mmt+N8ZOtgpxGnpdB0RiEhGccW7ytO2Sl9zQ/xfFQoEz4tKD4V88dhTvmR+GWwfLJFvaN1N
9C2TPCJ9apE0MYqPkOHna+pw4y5McKKUkImt3iWmNFvMdcPXs8XblPLu09X2fqhoNSaI9zkjdBal
sk2yqcQue1E46uu7Jo9QNo7c2YojZb9dMSq+6oGi46/A5rjTyU3Iwr+R+YJNcT3gUzigFT8eII3H
E20+1WW5e7h2GxXbtxumn7H9SbxhvOQk0FXwMBg4mkySYFQINAmJkvFh2Xr7e2LQyxTlrpXq2vrZ
5/UNQx0qbVldy2+gecEHD/Wm0uh4+s+lT2nePFVqrZKjZ2ju2EUb6ATZczQakwn3rtXjBtJX8dQ4
9WC/BtujQKe3zrIM3pBfjzBQPBkJUei1KRoHOBdUTrnqUA4WfWy2t/58ujXEEN3twTRQYkczu9sJ
CYX0AG8brnlsljzIAvHnvM6U54bbqY/bwE2XkhcR+5yJef2ag18QoBdrxz97QFaVECb77bgArdXQ
9oykFy+h8ZV8fjQstsEmCwD0THr7JoaPE/HOcSXSHMCdW3wPCoZbyIZteRtdc63sTu0dCt7j8zIG
iYoLIkIhutAEZC6DoYVwLsqjzWI0v73E7JTPnUTrpjkHICeq79APYswQhjE1IcG8XIlQiHiK0lZT
PxC5mvBK0WuWTKObhYij+8XcV1DLmwdEDq/tYir/4fVNpdDC7vqqvO9e4RvffmMKSPpQOImEsVRf
vlX8KkW+/ZU9t0mELjML8xuDOqSgbczucEJk7f5WoaCDA47LZw0WAgVuspnkq89MvdPshFoGpATI
3zE+QSMLnA+daSxgPppU3fECVVMDEG0tCQYfIZZENDeMfgbr9sFsnPShio68qpbbOjV6qpkXl5st
50yfaYSICRwEIxbE4ZZ6K7n4ESbMJv/vOnnyR9XvjcHLMjQfEzlV8XpYgYBk6dipLxZ4qtNv2o3Q
+6qfE2PeXzg5MCAuUlZ/T9UACZXPnK9xFhG25YThn7Es1LxpvFXWQCnTu4YjifFZ5tSyJs6PGgm4
2t9DEL9OxigsUFWcWHFJgYAtpDVun07LO/iMbDczKIpHcYhg3dPbQfIYC5y46W/tNgFa2F1TVSCT
R4BCfPavmoGrAgcbSkN3xhdQf76IBTedCZ4+InxY2R50l40+VFySUqF9RXl/4mfn6FxetfpwvpA8
BSmR8ZldyC5ZzgXPlwyvxL99/XIVGCCXB4mjmNX8H084rdmqcB7O1PHvQ1BW75BiRpvrgEPm27wZ
z5ZLvFVpPesZJXcyt0h50PzQ5A9AtZ/lBbsIZuyIbi63Bua9pIO7ZpdPjzbib7E45vya3nHlyXUM
8b5O9Pz4LrRfshu8CY4b+rLEXfG+RuZzYqMBDYIr3/TCpjqSWuw+JhHGl73WdXESPcpsmTmGbnxv
RMz7KWYljJtQQt6DbEyNfMcHofk6Vur+C+l3LCQ1Tmkxna7g2tTEmIkC1VrPa2TA7sDhu23E1x//
EI/inxSjZ1IENbEaigYdfqkxsBl64H1H6QEMInODB44IgdjiCu5S1d9WDKTBJAB6OxYAT/K0dJpw
OzGo7FZdSrPqslV8AATeynrPDUUzy12ydPHniw4qdQsJeagOVp4QCEnZmT+DJngSwLt42xwm/p9i
IsCZTl95D6Q2+kJW3Zw1qR8OOwkYqP5Y0NWXKRYomM8rA5gUBsIOgvYn7W/xlJzYx/MKagTtkxxD
dBAQAykAh09Dl/SYxJ1R67k+JhpyooG+yuiNZSEpomskuBm+lf62s+li21EakB5LZ7igJzFcmbFH
/US3qytF+ns+C2oJvO0DcRbTtUI8J3h+yKnvo0qUyL0zefFooJraUMJElcbagRqdkaYG8MkbGhgR
wHm9URPHGXZamQB1v/v2Yb6/pF5Q6buOhEQKZqqshUUBgvB3KqMLBkUctb3UoAhTAoTAFSqXRjVV
wHTthuWXiBRDwZGIOKMYDxyZEgY21Tc4sL+7BppZFLsdsB/d2rgIp38kHJLA3fHS2huJfYSlve4f
zB3iqW2Poi7ddwUYZhT37ukoEsl1mL2twRAYgORxxME02h0IIRSxObb77MvC9PDoB0Oz31wbuN5u
Tknx/ALgqDOnYrIpisEsIb6l1LZu5jeGKtXL/6V/31AThlonAohxxFqidf3M6USPuC0LH5YC9QK6
JRTF2gkemhYv4pLKdz+hs5jMVDm4jIa1fOL3WqeZ6vLAYl4hvWEQJWR8XWgqn6EBCms0wj4i3z5m
wp044p8PMmg3qkROgW5qnR8KB0AcK7yp+0gK+7lQyK/Ljb48HBtDW+W3eZnmsqps0A2/J7oots1D
7Q2VZZ8MGjgZYPU6i4IT0PdEv/DJAaWnx5tqIg9+G2GfQUIsh+OTX37WVexeWJO4xWm1nyt8YBl/
uBOAHdnU4Apy5yHNpxln/qInJ8aJ4XQOhQiqk4gaykQ58D8ZKCaXgoP7CNAw5dCJuoiZLno3wKMi
tVcTBCQjwNWrCvC9xpSLraScAcsLsvIQW376tUwPTxAo5vQPJIFarx1H5OpRfg/mCjFMb1+aKyji
hYcRGf3HDc21xAqDSjRDdEWDoNiopo+F5ZTB27SQ6i76DcbK43cTMQ+H0N1q4laXyK7WWByjSqAT
FW0L+cStxOtUJDEcG665b0mDZGYjSuMffJm87zdYYsdcA9jcVi3S5JjZ78ztflBuRpyaXerew+ek
BoY9KMuFlkwkGTn/MZGPu3dzH7Jo2SVbuVetzsmzR5cA/ITsOlBB8bU/CTG1rGglYsnKt9J6/rcR
+EoUnZMhLYjD1L61KxjsaS+jiWYUa+sfsIoARtG1G7U4c6gxeoJiaUv0wVJecwBPghWtV+ICWCRM
Keqwzl2NqZK97QrDHl/VLonEnKAsGV7GGjSZmB2CTa02reEw+LNmCYHIiRfR6hZCTZ+DWCziN9Ue
VYhKG+zNmvm3budR3C8HUNgxEaAKUOh/qs+tzo4kEokuxoFL6EbviC0WqH1wbR9RDXkLGAvLyU/O
DGXvNKDUGz2ZZxJWd/9CuTD7Obu8scuDWAawZunpiEAT4DgOvigYcsREyJkWEFo+6y7K4HJfXSf4
iR0VY4lvjPwzqCIS+n55a+JwnZ0+bMyeC/PnBhkEKbvfwkH6nnbop9OWg86URz3/0h0X6j8ivNnB
g3Vw29Bqm2f6XoFGkgZqVmaXNleD3sYPtolT597u8tOD/tn5l2SNisGlwT8f0eanB1ijSoV89FDQ
FcmtJVtA/pPOrAhlZjJSSvm2s1cqywZN6jMMqNBVygBLulPul/XBXPrzRuu4O7X8BzVR+WFC3deR
DTSGcHyl2XlW2osxlAdAOQKlmXpdHK7LtF2tSfYFgb9+3AzM0SzugvU3lUbpXWRNwwqY/tQX2UkR
y2sySFaaBwskbEiKA2B2ZxWfpl7PFzKQdPHNMvUSvfkIemfjYsRkDwGcQpUtBpA5wTY8bLTeY9jw
w4o+vjfy2Y4n6RzNNrM60DDPlSnoJSnX+tCWFcpO7mcgvUuxmCG1nUcN2B28GnDBZ/7lqNMOEa7n
iLafwJKMjiLFdKYfMc90PwDz8LYiq9QpFW0QlhzLXgiljeYSFmt1GMqt/HAPMofAYqPH1jgziBRD
3JImgoPyQS7ktlXOQZihlxMYdUtZKKRGjoBX0Kj03jV4q+FeNEdPaMcup6+lN7XRegQWItUL8jvc
U5fZRDA+QlyD1nmgUNykZqk+iZh2/xKilTCkKgeEdhBvwSU2sgEiFBpwkI6tii4IACeHlR/2E1qh
VMhTHwdO2W7mxLXkRW3pJJNNnNroOMUhJyUCZR7Z7QjzfEP12wZgeqBarPeUI3q4eFNWT4BkLhxI
0WIPLRqdut9VkcfNZFhhwNFzVCueEEFfTrS6+b8F2dGBd9sKDIM1gMwWOBwO8jH5RGQcjChC1FA5
7UJbJlIHgSIzkqpPcFbxmRQKO1jetTjrs73dyo4fowEbngX7gJuCnDDLLjnDpax4XfgVBf+0PyEA
It2gLwpVBg==
`protect end_protected
| mit |
223323/lab2 | HDL/source/tb/vhdl/top_tb.vhd | 1 | 2130 | -------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <lprs2@rt-rk.com>
--
-- Module Name: top_tb
--
-- Description:
--
-- TB for top
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity top_tb is
end top_tb;
architecture behavior of top_tb is
-- component Declaration
component top
generic (
RES_TYPE : natural := 0;
TEXT_MEM_DATA_WIDTH : natural := 6;
GRAPH_MEM_DATA_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
reset_n_i : in std_logic;
--
direct_mode_i : in std_logic;
display_mode_i : in std_logic_vector(1 downto 0);
-- vga
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic;
blank_o : out std_logic;
pix_clock_o : out std_logic;
psave_o : out std_logic;
sync_o : out std_logic;
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0)
);
end component;
signal clk : std_logic;
signal reset_n : std_logic;
begin
clk_gen : process
begin
clk <= '1';
wait for 41.66 ns;
clk <= '0';
wait for 41.66 ns;
end process clk_gen;
-- component instantiation
uut: top
generic map(
RES_TYPE => 1,
TEXT_MEM_DATA_WIDTH => 6,
GRAPH_MEM_DATA_WIDTH => 32
)
port map(
clk_i => clk,
reset_n_i => reset_n,
--
direct_mode_i => '0',
display_mode_i => "10"
);
-- test bench statements
tb : process
begin
reset_n <= '0';
wait for 100 us; -- wait until global set/reset completes
reset_n <= '1';
-- add user defined stimulus here
wait; -- will wait forever
end process tb;
-- end test bench
end; | mit |
ComputerArchitectureGroupPWr/SimulationCore | src/Heater.vhd | 1 | 1081 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Heater is
port(
rst : in std_logic;
clk50Mhz : in std_logic;
pulseWidth : in std_logic_vector(7 downto 0);
heaterEnable : out std_logic
);
end Heater;
architecture Behavioral of Heater is
signal counter : integer range 0 to 255;
signal pulseWidthReg : integer range 0 to 255;
signal heaterEnableSignal : std_logic;
attribute keep : string;
attribute keep of heaterEnable: signal is "true";
attribute S: string;
attribute S of heaterEnable: signal is "yes";
begin
heaterEnable <= heaterEnableSignal;
process(clk50Mhz,rst,counter)
begin
if rst='1' or counter = 255 then
counter <= 0;
elsif clk50Mhz'event and clk50Mhz = '1' then
counter <= counter + 1;
end if;
end process;
process(clk50Mhz,rst)
begin
if rst = '1' then
pulseWidthReg <= 0;
elsif clk50Mhz'event and clk50Mhz = '1' then
pulseWidthReg <= to_integer(unsigned(pulseWidth));
end if;
end process;
heaterEnableSignal <= '1' when pulseWidthReg > counter else '0';
end Behavioral;
| mit |
APastorG/APG | int_const_mult/int_const_mult_s.vhd | 1 | 3403 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an int_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity int_const_mult_s is
generic(
SPEED_opt : T_speed := t_min; --exception: value not set
MULTIPLICANDS : integer_v --compulsory
);
port(
input : in u_sfixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture int_const_mult_s1 of int_const_mult_s is
function to_real(
vector : integer_v)
return real_v is
variable result : real_v(vector'range);
begin
for i in vector'range loop
result(i) := real(vector(i));
end loop;
return result;
end function;
constant MULTIPLICANDS_real : real_v(MULTIPLICANDS'range) := to_real(MULTIPLICANDS);
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_core_s2:
entity work.real_const_mult_core_s
generic map(
SPEED_opt => SPEED_opt,
--ROUND_STYLE_opt => ROUND_STYLE_opt,
--ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
--MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
CONSTANTS => MULTIPLICANDS_real,
input_high => input'high,
input_low => input'low
)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; | mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/fifo_w64_d2_A.vhd | 4 | 4437 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w64_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w64_d2_A_shiftReg;
architecture rtl of fifo_w64_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w64_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w64_d2_A is
component fifo_w64_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w64_d2_A_shiftReg : fifo_w64_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| mit |
APastorG/APG | real_const_mult/real_const_mult_tb.vhd | 1 | 6347 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a testbench generated for the real_const_mult.
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.tb_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_tb1 of real_const_mult_tb is
/* generics' constants 1 */
/**************************************************************************************************/
constant UNSIGNED_2COMP_opt : boolean_tb := (true, true); --default
constant SPEED_opt : T_speed_tb := (t_min, true); --exception: value not set
constant ROUND_STYLE_opt : T_round_style_tb := (fixed_round, true);--default
constant ROUND_TO_BIT_opt : integer_exc_tb := (-13, true); --exception: value not set
constant MAX_ERROR_PCT_opt : real_exc_tb := (0.01, false); --exception: value not set
constant MULTIPLICANDS : real_v := (44.0, 130.0, 172.0); --compulsory
constant used_UNSIGNED_2COMP_opt : boolean := value_used(UNSIGNED_2COMP_opt, false);
constant used_SPEED_opt : T_speed := value_used(SPEED_opt);
constant used_ROUND_STYLE_opt : T_round_style := value_used(ROUND_STYLE_opt, fixed_truncate);
constant used_ROUND_TO_BIT_opt : integer_exc := value_used(ROUND_TO_BIT_opt);
constant used_MAX_ERROR_PCT_opt : real_exc := value_used(MAX_ERROR_PCT_opt);
constant used_MULTIPLICANDS : real_v := MULTIPLICANDS;
/* constants 2 */
/**************************************************************************************************/
constant NORM_IN_HIGH : integer := 0;
constant NORM_IN_LOW : integer := -5;
constant IN_HIGH : integer := NORM_IN_HIGH + SULV_NEW_ZERO;
constant IN_LOW : integer := NORM_IN_LOW + SULV_NEW_ZERO;
constant NORM_OUT_HIGH : integer := real_const_mult_OH(used_ROUND_STYLE_opt,
used_ROUND_TO_BIT_opt,
used_MAX_ERROR_PCT_opt,
used_MULTIPLICANDS,
NORM_IN_HIGH,
NORM_IN_LOW,
not used_UNSIGNED_2COMP_opt);
constant NORM_OUT_LOW : integer := real_const_mult_OL(used_ROUND_STYLE_opt,
used_ROUND_TO_BIT_opt,
used_MAX_ERROR_PCT_opt,
used_MULTIPLICANDS,
NORM_IN_LOW,
not used_UNSIGNED_2COMP_opt);
constant OUT_HIGH : integer := SULV_NEW_ZERO + NORM_OUT_HIGH;
constant OUT_LOW : integer := SULV_NEW_ZERO + NORM_OUT_LOW;
/* signals 3 */
/**************************************************************************************************/
--IN
signal input : std_ulogic_vector(IN_HIGH DOWNTO IN_LOW);
signal clk : std_ulogic := '1';
signal valid_input : std_ulogic := '1';
--OUT
signal output : sulv_v(1 to MULTIPLICANDS'length)(OUT_HIGH downto OUT_LOW);
signal valid_output : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_1:
entity work.real_const_mult
generic map(
UNSIGNED_2COMP_opt => used_UNSIGNED_2COMP_opt,
SPEED_opt => used_SPEED_opt,
ROUND_STYLE_opt => used_ROUND_STYLE_opt,
ROUND_TO_BIT_opt => used_ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => used_MAX_ERROR_PCT_opt,
MULTIPLICANDS => used_MULTIPLICANDS)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
--pragma translate off
--synthesis translate_off
process (clk)
begin
clk <= not clk after 2 ps;
end process;
process
begin
valid_input <= '0';
input <= (others => '0');
wait for 10 ps;
valid_input <= '1';
input <= (SULV_NEW_ZERO => '1', others => '0');
wait for 4 ps;
valid_input <= '0';
input <= (others => '0');
wait;
end process;
--pragma translate on
--synthesis translate_on
end architecture; | mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/sin_taylor_series.vhd | 4 | 12640 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC );
end;
architecture behav of sin_taylor_series is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal Loop_sum_loop_proc_U0_ap_start : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_done : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_continue : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_idle : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (63 downto 0);
signal Loop_sum_loop_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_sum_negative_0_loc_l : STD_LOGIC;
signal sum_negative_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_negative_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_negative_0_loc_l : STD_LOGIC;
signal ap_channel_done_sum_positive_0_loc_l : STD_LOGIC;
signal sum_positive_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_positive_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_positive_0_loc_l : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_start : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_done : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_continue : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_idle : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_ready : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_tmp_loc_channel : STD_LOGIC;
signal tmp_loc_channel_full_n : STD_LOGIC;
signal p_source_files_sr_U0_ap_start : STD_LOGIC;
signal p_source_files_sr_U0_ap_done : STD_LOGIC;
signal p_source_files_sr_U0_ap_continue : STD_LOGIC;
signal p_source_files_sr_U0_ap_idle : STD_LOGIC;
signal p_source_files_sr_U0_ap_ready : STD_LOGIC;
signal p_source_files_sr_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_p_source_files_sr_fu_42_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal sum_positive_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_positive_0_loc_l_empty_n : STD_LOGIC;
signal sum_negative_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_empty_n : STD_LOGIC;
signal tmp_loc_channel_dout : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_loc_channel_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_full_n : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_write : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_full_n : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_write : STD_LOGIC;
signal p_source_files_sr_U0_start_full_n : STD_LOGIC;
signal p_source_files_sr_U0_start_write : STD_LOGIC;
component Loop_sum_loop_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component Block_sin_taylor_ser IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component p_source_files_sr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component fifo_w64_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (63 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (63 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
Loop_sum_loop_proc_U0 : component Loop_sum_loop_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Loop_sum_loop_proc_U0_ap_start,
ap_done => Loop_sum_loop_proc_U0_ap_done,
ap_continue => Loop_sum_loop_proc_U0_ap_continue,
ap_idle => Loop_sum_loop_proc_U0_ap_idle,
ap_ready => Loop_sum_loop_proc_U0_ap_ready,
x => x,
ap_return_0 => Loop_sum_loop_proc_U0_ap_return_0,
ap_return_1 => Loop_sum_loop_proc_U0_ap_return_1);
Block_sin_taylor_ser_U0 : component Block_sin_taylor_ser
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Block_sin_taylor_ser_U0_ap_start,
ap_done => Block_sin_taylor_ser_U0_ap_done,
ap_continue => Block_sin_taylor_ser_U0_ap_continue,
ap_idle => Block_sin_taylor_ser_U0_ap_idle,
ap_ready => Block_sin_taylor_ser_U0_ap_ready,
p_read => sum_positive_0_loc_l_dout,
p_read1 => sum_negative_0_loc_l_dout,
ap_return => Block_sin_taylor_ser_U0_ap_return);
p_source_files_sr_U0 : component p_source_files_sr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => p_source_files_sr_U0_ap_start,
ap_done => p_source_files_sr_U0_ap_done,
ap_continue => p_source_files_sr_U0_ap_continue,
ap_idle => p_source_files_sr_U0_ap_idle,
ap_ready => p_source_files_sr_U0_ap_ready,
p_read => tmp_loc_channel_dout,
ap_return => p_source_files_sr_U0_ap_return);
sum_positive_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_0,
if_full_n => sum_positive_0_loc_l_full_n,
if_write => ap_channel_done_sum_positive_0_loc_l,
if_dout => sum_positive_0_loc_l_dout,
if_empty_n => sum_positive_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
sum_negative_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_1,
if_full_n => sum_negative_0_loc_l_full_n,
if_write => ap_channel_done_sum_negative_0_loc_l,
if_dout => sum_negative_0_loc_l_dout,
if_empty_n => sum_negative_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
tmp_loc_channel_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_sin_taylor_ser_U0_ap_return,
if_full_n => tmp_loc_channel_full_n,
if_write => Block_sin_taylor_ser_U0_ap_done,
if_dout => tmp_loc_channel_dout,
if_empty_n => tmp_loc_channel_empty_n,
if_read => p_source_files_sr_U0_ap_ready);
ap_sync_reg_channel_write_sum_negative_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
end if;
end if;
end if;
end process;
ap_sync_reg_channel_write_sum_positive_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
end if;
end if;
end if;
end process;
Block_sin_taylor_ser_U0_ap_continue <= tmp_loc_channel_full_n;
Block_sin_taylor_ser_U0_ap_start <= (sum_positive_0_loc_l_empty_n and sum_negative_0_loc_l_empty_n);
Block_sin_taylor_ser_U0_start_full_n <= ap_const_logic_0;
Block_sin_taylor_ser_U0_start_write <= ap_const_logic_0;
Loop_sum_loop_proc_U0_ap_continue <= (ap_sync_channel_write_sum_negative_0_loc_l and ap_sync_channel_write_sum_positive_0_loc_l);
Loop_sum_loop_proc_U0_ap_start <= ap_start;
Loop_sum_loop_proc_U0_start_full_n <= ap_const_logic_0;
Loop_sum_loop_proc_U0_start_write <= ap_const_logic_0;
ap_channel_done_sum_negative_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_negative_0_loc_l xor ap_const_logic_1));
ap_channel_done_sum_positive_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_positive_0_loc_l xor ap_const_logic_1));
ap_channel_done_tmp_loc_channel <= Block_sin_taylor_ser_U0_ap_done;
ap_done <= p_source_files_sr_U0_ap_done;
ap_idle <= (Loop_sum_loop_proc_U0_ap_idle and Block_sin_taylor_ser_U0_ap_idle and p_source_files_sr_U0_ap_idle and (sum_positive_0_loc_l_empty_n xor ap_const_logic_1) and (sum_negative_0_loc_l_empty_n xor ap_const_logic_1) and (tmp_loc_channel_empty_n xor ap_const_logic_1));
ap_ready <= Loop_sum_loop_proc_U0_ap_ready;
ap_return <= p_source_files_sr_U0_ap_return;
ap_sync_channel_write_sum_negative_0_loc_l <= ((ap_channel_done_sum_negative_0_loc_l and sum_negative_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_negative_0_loc_l);
ap_sync_channel_write_sum_positive_0_loc_l <= ((ap_channel_done_sum_positive_0_loc_l and sum_positive_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_positive_0_loc_l);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= p_source_files_sr_U0_ap_done;
ap_sync_ready <= Loop_sum_loop_proc_U0_ap_ready;
p_source_files_sr_U0_ap_continue <= ap_const_logic_1;
p_source_files_sr_U0_ap_start <= tmp_loc_channel_empty_n;
p_source_files_sr_U0_start_full_n <= ap_const_logic_0;
p_source_files_sr_U0_start_write <= ap_const_logic_0;
tmp_p_source_files_sr_fu_42_ap_return <= ap_const_lv64_0;
end behav;
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/sim/vhdl/sin_taylor_seriesfYi.vhd | 4 | 3087 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_seriesfYi is
generic (
ID : integer := 12;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_seriesfYi is
--------------------- Component ---------------------
component sin_taylor_series_ap_dsub_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_dsub_3_full_dsp_64_u : component sin_taylor_series_ap_dsub_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/Loop_sum_loop_proc.vhd | 4 | 29010 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Loop_sum_loop_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of Loop_sum_loop_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (37 downto 0) := "00000000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (37 downto 0) := "00000000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (37 downto 0) := "00000000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (37 downto 0) := "00000001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (37 downto 0) := "00000010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (37 downto 0) := "00000100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (37 downto 0) := "00001000000000000000000000000000000000";
constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (37 downto 0) := "00010000000000000000000000000000000000";
constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (37 downto 0) := "00100000000000000000000000000000000000";
constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (37 downto 0) := "01000000000000000000000000000000000000";
constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (37 downto 0) := "10000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal tmp_5_i_fu_122_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_5_i_reg_157 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_i_fu_116_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_fu_130_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_163 : STD_LOGIC_VECTOR (4 downto 0);
signal grp_power_fu_81_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_power_fu_81_ap_done : STD_LOGIC;
signal grp_fact_fu_70_ap_done : STD_LOGIC;
signal grp_power_fu_88_ap_done : STD_LOGIC;
signal grp_fact_fu_76_ap_done : STD_LOGIC;
signal ap_block_state3_on_subcall_done : BOOLEAN;
signal grp_fact_fu_70_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal grp_power_fu_88_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fact_fu_76_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_104_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_i_reg_188 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
signal grp_fu_110_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_8_i_reg_193 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_94_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state38 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state38 : signal is "none";
signal grp_fu_99_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fact_fu_70_ap_start : STD_LOGIC;
signal grp_fact_fu_70_ap_idle : STD_LOGIC;
signal grp_fact_fu_70_ap_ready : STD_LOGIC;
signal grp_fact_fu_76_ap_start : STD_LOGIC;
signal grp_fact_fu_76_ap_idle : STD_LOGIC;
signal grp_fact_fu_76_ap_ready : STD_LOGIC;
signal grp_power_fu_81_ap_start : STD_LOGIC;
signal grp_power_fu_81_ap_idle : STD_LOGIC;
signal grp_power_fu_81_ap_ready : STD_LOGIC;
signal grp_power_fu_88_ap_start : STD_LOGIC;
signal grp_power_fu_88_ap_idle : STD_LOGIC;
signal grp_power_fu_88_ap_ready : STD_LOGIC;
signal sum_positive_0_loc_l_reg_34 : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_reg_46 : STD_LOGIC_VECTOR (63 downto 0);
signal i_0_i_i_reg_58 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_grp_fact_fu_70_ap_start : STD_LOGIC := '0';
signal ap_reg_grp_fact_fu_76_ap_start : STD_LOGIC := '0';
signal ap_reg_grp_power_fu_81_ap_start : STD_LOGIC := '0';
signal ap_reg_grp_power_fu_88_ap_start : STD_LOGIC := '0';
signal ap_CS_fsm_state34 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state34 : signal is "none";
signal grp_fu_104_ce : STD_LOGIC;
signal ap_CS_fsm_state35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state35 : signal is "none";
signal ap_CS_fsm_state36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state36 : signal is "none";
signal ap_CS_fsm_state37 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state37 : signal is "none";
signal grp_fu_110_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (37 downto 0);
component fact IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component power IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
y : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_seriesdEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_serieseOg IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
grp_fact_fu_70 : component fact
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_fact_fu_70_ap_start,
ap_done => grp_fact_fu_70_ap_done,
ap_idle => grp_fact_fu_70_ap_idle,
ap_ready => grp_fact_fu_70_ap_ready,
x => i_0_i_i_reg_58,
ap_return => grp_fact_fu_70_ap_return);
grp_fact_fu_76 : component fact
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_fact_fu_76_ap_start,
ap_done => grp_fact_fu_76_ap_done,
ap_idle => grp_fact_fu_76_ap_idle,
ap_ready => grp_fact_fu_76_ap_ready,
x => tmp_5_i_reg_157,
ap_return => grp_fact_fu_76_ap_return);
grp_power_fu_81 : component power
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_power_fu_81_ap_start,
ap_done => grp_power_fu_81_ap_done,
ap_idle => grp_power_fu_81_ap_idle,
ap_ready => grp_power_fu_81_ap_ready,
x => x,
y => i_0_i_i_reg_58,
ap_return => grp_power_fu_81_ap_return);
grp_power_fu_88 : component power
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_power_fu_88_ap_start,
ap_done => grp_power_fu_88_ap_done,
ap_idle => grp_power_fu_88_ap_idle,
ap_ready => grp_power_fu_88_ap_ready,
x => x,
y => tmp_5_i_reg_157,
ap_return => grp_power_fu_88_ap_return);
sin_taylor_seriesdEe_U7 : component sin_taylor_seriesdEe
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => sum_positive_0_loc_l_reg_34,
din1 => tmp_3_i_reg_188,
ce => ap_const_logic_1,
dout => grp_fu_94_p2);
sin_taylor_seriesdEe_U8 : component sin_taylor_seriesdEe
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => sum_negative_0_loc_l_reg_46,
din1 => tmp_8_i_reg_193,
ce => ap_const_logic_1,
dout => grp_fu_99_p2);
sin_taylor_serieseOg_U9 : component sin_taylor_serieseOg
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_power_fu_81_ap_return,
din1 => grp_fact_fu_70_ap_return,
ce => grp_fu_104_ce,
dout => grp_fu_104_p2);
sin_taylor_serieseOg_U10 : component sin_taylor_serieseOg
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_power_fu_88_ap_return,
din1 => grp_fact_fu_76_ap_return,
ce => grp_fu_110_ce,
dout => grp_fu_110_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_grp_fact_fu_70_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_fact_fu_70_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
ap_reg_grp_fact_fu_70_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_fact_fu_70_ap_ready)) then
ap_reg_grp_fact_fu_70_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_fact_fu_76_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_fact_fu_76_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
ap_reg_grp_fact_fu_76_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_fact_fu_76_ap_ready)) then
ap_reg_grp_fact_fu_76_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_power_fu_81_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_power_fu_81_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
ap_reg_grp_power_fu_81_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_power_fu_81_ap_ready)) then
ap_reg_grp_power_fu_81_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_power_fu_88_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_power_fu_88_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
ap_reg_grp_power_fu_88_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_power_fu_88_ap_ready)) then
ap_reg_grp_power_fu_88_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_0_i_i_reg_58_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state38)) then
i_0_i_i_reg_58 <= i_reg_163;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
i_0_i_i_reg_58 <= ap_const_lv5_1;
end if;
end if;
end process;
sum_negative_0_loc_l_reg_46_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state38)) then
sum_negative_0_loc_l_reg_46 <= grp_fu_99_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
sum_negative_0_loc_l_reg_46 <= ap_const_lv64_0;
end if;
end if;
end process;
sum_positive_0_loc_l_reg_34_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state38)) then
sum_positive_0_loc_l_reg_34 <= grp_fu_94_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
sum_positive_0_loc_l_reg_34 <= ap_const_lv64_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
i_reg_163 <= i_fu_130_p2;
tmp_5_i_reg_157 <= tmp_5_i_fu_122_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state33)) then
tmp_3_i_reg_188 <= grp_fu_104_p2;
tmp_8_i_reg_193 <= grp_fu_110_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_i_fu_116_p2, ap_CS_fsm_state3, ap_block_state3_on_subcall_done)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_block_state3_on_subcall_done = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_state4;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state27;
when ap_ST_fsm_state27 =>
ap_NS_fsm <= ap_ST_fsm_state28;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state29;
when ap_ST_fsm_state29 =>
ap_NS_fsm <= ap_ST_fsm_state30;
when ap_ST_fsm_state30 =>
ap_NS_fsm <= ap_ST_fsm_state31;
when ap_ST_fsm_state31 =>
ap_NS_fsm <= ap_ST_fsm_state32;
when ap_ST_fsm_state32 =>
ap_NS_fsm <= ap_ST_fsm_state33;
when ap_ST_fsm_state33 =>
ap_NS_fsm <= ap_ST_fsm_state34;
when ap_ST_fsm_state34 =>
ap_NS_fsm <= ap_ST_fsm_state35;
when ap_ST_fsm_state35 =>
ap_NS_fsm <= ap_ST_fsm_state36;
when ap_ST_fsm_state36 =>
ap_NS_fsm <= ap_ST_fsm_state37;
when ap_ST_fsm_state37 =>
ap_NS_fsm <= ap_ST_fsm_state38;
when ap_ST_fsm_state38 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state33 <= ap_CS_fsm(32);
ap_CS_fsm_state34 <= ap_CS_fsm(33);
ap_CS_fsm_state35 <= ap_CS_fsm(34);
ap_CS_fsm_state36 <= ap_CS_fsm(35);
ap_CS_fsm_state37 <= ap_CS_fsm(36);
ap_CS_fsm_state38 <= ap_CS_fsm(37);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state3_on_subcall_done_assign_proc : process(grp_power_fu_81_ap_done, grp_fact_fu_70_ap_done, grp_power_fu_88_ap_done, grp_fact_fu_76_ap_done)
begin
ap_block_state3_on_subcall_done <= ((ap_const_logic_0 = grp_power_fu_81_ap_done) or (ap_const_logic_0 = grp_fact_fu_70_ap_done) or (ap_const_logic_0 = grp_power_fu_88_ap_done) or (ap_const_logic_0 = grp_fact_fu_76_ap_done));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state2, tmp_i_fu_116_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_0))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_i_fu_116_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_0 <= sum_positive_0_loc_l_reg_34;
ap_return_1 <= sum_negative_0_loc_l_reg_46;
grp_fact_fu_70_ap_start <= ap_reg_grp_fact_fu_70_ap_start;
grp_fact_fu_76_ap_start <= ap_reg_grp_fact_fu_76_ap_start;
grp_fu_104_ce_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_block_state3_on_subcall_done, ap_CS_fsm_state38, ap_CS_fsm_state34, ap_CS_fsm_state35, ap_CS_fsm_state36, ap_CS_fsm_state37)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state34) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_boolean_1 = ap_block_state3_on_subcall_done)) or (ap_const_logic_1 = ap_CS_fsm_state35) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state37))) then
grp_fu_104_ce <= ap_const_logic_0;
else
grp_fu_104_ce <= ap_const_logic_1;
end if;
end process;
grp_fu_110_ce_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_block_state3_on_subcall_done, ap_CS_fsm_state38, ap_CS_fsm_state34, ap_CS_fsm_state35, ap_CS_fsm_state36, ap_CS_fsm_state37)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state34) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_boolean_1 = ap_block_state3_on_subcall_done)) or (ap_const_logic_1 = ap_CS_fsm_state35) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state37))) then
grp_fu_110_ce <= ap_const_logic_0;
else
grp_fu_110_ce <= ap_const_logic_1;
end if;
end process;
grp_power_fu_81_ap_start <= ap_reg_grp_power_fu_81_ap_start;
grp_power_fu_88_ap_start <= ap_reg_grp_power_fu_88_ap_start;
i_fu_130_p2 <= std_logic_vector(unsigned(i_0_i_i_reg_58) + unsigned(ap_const_lv5_4));
tmp_5_i_fu_122_p2 <= std_logic_vector(unsigned(i_0_i_i_reg_58) + unsigned(ap_const_lv5_2));
tmp_i_fu_116_p2 <= "1" when (unsigned(i_0_i_i_reg_58) < unsigned(ap_const_lv5_15)) else "0";
end behav;
| mit |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/src/spwxmit_fast.vhd | 2 | 28908 | --
-- SpaceWire Transmitter
--
-- This entity translates outgoing characters and tokens into
-- data-strobe signalling.
--
-- The output stage is driven by a separate transmission clock "txclk" which
-- will typically be faster than the system clock. The actual transmission
-- rate is determined by dividing the transmission clock by an integer factor.
--
-- The code is tuned for implementation on Xilinx Spartan-3.
--
-- Concept
-- -------
--
-- Logic in the system clock domain generates a stream of tokens to be
-- transmitted. These tokens are encoded as instances of the token_type
-- record. Tokens are queued in a two-slot FIFO buffer (r.token0 and r.token1)
-- with a 1-bit pointer (r.tokmux) pointing to the head of the queue.
-- When a token is pushed into the buffer, a flag register is flipped
-- (r.sysflip0 and r.sysflip1) to indicate to the txclk domain that the
-- buffer slot has been refilled.
--
-- The txclk domain pulls tokens from the FIFO buffer, flipping flag
-- registers (rtx.txflip0 and rtx.txflip1) to indicate to the system clock
-- domain that a token has been pulled. When the system clock domain detects
-- that a token has been consumed, it refills the buffer slot with a new
-- token (assuming that there are tokens waiting to be transmitted).
-- Whenever the FIFO buffer is empty, the txclk domain sends NULLs instead.
-- This can happen either when there are no tokens to send, or when the
-- system clock domain is late to refill the buffer.
--
-- Details
-- -------
--
-- Logic in the system clock domain accepts transmission requests through
-- the external interface of the entity. Pending requests are translated
-- into a stream of tokens. The tokens are pushed to the txclk domain through
-- the FIFO buffer as described above.
--
-- The data path through the txclk domain is divided into stages B through F
-- in a half-hearted attempt to keep things simple.
--
-- Stage B takes a token from the FIFO buffer and updates a buffer status
-- flag to indicate that the buffer slot needs to be refilled. If the FIFO
-- is empty, a NULL is inserted. Stage B is triggered one clock after
-- stage E switches to a new token. If the previous token was ESC, stage B
-- skips a turn because stage C will already know what to do.
--
-- Stage C takes a token from stage B and translates it into a bit pattern.
-- Time codes and NULL tokens are broken into two separate tokens starting
-- with ESC. Stage C is triggered one clock after the shift buffer in
-- stage E drops to 3 tokens.
--
-- Stage D completes the task of translating tokens to bit patterns and
-- distinguishes between 10-bit and 4-bit tokens. It is not explicitly
-- triggered but simply follows stage C.
--
-- Stage E is the bit shift register. It shifts when "txclken" is high.
-- A one-hot counter keeps track of the number of bits remaining in
-- the register. When the register falls empty, it loads a new 10-bit or
-- 4-bit pattern as prepared by stage D. Stage E also computes parity.
--
-- Stage F performs data strobe encoding. When the transmitter is disabled,
-- the outputs of stage F fall to zero in a controlled way.
--
-- To generate the transmission bit clock, the txclk is divided by an
-- integer factor (divcnt+1) using an 8-bit down counter. The implementation
-- of this counter has become quite complicated in order to meet timing goals.
-- The counter consists of 4 blocks of two bits each (txclkcnt), with a
-- carry-save concept used between blocks (txclkcy). Detection of terminal
-- count (txclkdone) has a pipeline delay of two cycles. Therefore a separate
-- concept is used if the initial count is less than 2 (txdivnorm). This is
-- all glued together in the final assignment to txclken.
--
-- The initial count for txclk division (divcnt) comes from the system clock
-- domain and thus needs to be synchronized for use in the txclk domain.
-- To facilitate this, the system clock domain latches the value of divcnt
-- once every 6 sysclk cycles and sets a flag to indicate when the latched
-- value can safely be used by the txclk domain.
--
-- A tricky aspect of the design is the initial state of the txclk logic.
-- When the transmitter is enabled (txen goes high), the txclk logic starts
-- with the first ESC pattern already set up in stage D, and stage C ready
-- to produce the FCT part of the first NULL.
--
-- The following guidelines are used to get good timing for the txclk domain:
-- * The new value of a register depends on at most 4 inputs (single LUT),
-- or in a few cases on 5 inputs (two LUTs and F5MUX).
-- * Synchronous resets may be used, but only if the reset signal comes
-- directly from a register (no logic in set/reset path);
-- * Clock enables may be used, but only if the enable signal comes directly
-- from a register (no logic in clock enable path).
--
-- Synchronization issues
-- ----------------------
--
-- There is a two-slot FIFO buffer between the system and txclk domains.
-- After the txclk domain pulls a token from the buffer, the system clock
-- domain should ideally refill the buffer before the txclk domain again
-- tries to pull from the same buffer slot. If the refill occurs late,
-- the txclk domain needs to insert a NULL token which is inefficient
-- use of bandwidth.
--
-- Assuming the transmission consists of a stream of data characters,
-- 10 bits per character, there are exactly 2*10 bit periods between
-- successive reads from the same buffer slot by the txclk logic.
--
-- The time needed for the system clock logic to refill a buffer slot =
-- 1 txclk period (update of rtx.txflipN)
-- + 1 txclk period (routing delay between domains)
-- + 2 sysclk periods (synchronizer for txflipN)
-- + 1 sysclk period (refill buffer slot and update r.sysflipN)
-- + 1 txclk period (routing delay between domains)
-- + 2 txclk periods (synchronizer for sysflipN)
-- = 5 txclk periods + 3 sysclk periods
--
-- If for example txclk is 4 times as fast as sysclk, this amounts to
-- 5 txclk + 3 sysclk = 5 + 3*4 txclk = 17 txclk
-- is less than 20 bit periods even at maximum transmission rate, so
-- no problem there.
--
-- This is different when the data stream includes 4-bit tokens.
-- See the manual for further comments.
--
-- Implementation guidelines
-- -------------------------
--
-- To minimize clock skew, IOB flip-flops should be used to drive
-- spw_do and spw_so.
--
-- "txclk" must be at least as fast as the system clock;
-- "txclk" does not need to be phase-related to the system clock;
-- it is allowed for "txclk" to be equal to "clk".
--
-- The following timing constraints are needed:
-- * PERIOD constraint on the system clock;
-- * PERIOD constraint on "txclk";
-- * FROM-TO constraint from "txclk" to the system clock, equal to
-- one "txclk" period;
-- * FROM-TO constraint from the system clock to "txclk", equal to
-- one "txclk" period.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwxmit_fast is
port (
-- System clock.
clk: in std_logic;
-- Transmit clock.
txclk: in std_logic;
-- Synchronous reset (active-high)
-- Used asynchronously by fast clock domain (must be glitch-free).
rst: in std_logic;
-- Scaling factor minus 1, used to scale the system clock into the
-- transmission bit rate. The system clock is divided by
-- (unsigned(divcnt) + 1). Changing this signal will immediately
-- change the transmission rate.
divcnt: in std_logic_vector(7 downto 0);
-- Input signals from spwlink.
xmiti: in spw_xmit_in_type;
-- Output signals to spwlink.
xmito: out spw_xmit_out_type;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
-- Turn off FSM extraction to avoid synchronization problems.
attribute FSM_EXTRACT: string;
attribute FSM_EXTRACT of spwxmit_fast: entity is "NO";
end entity spwxmit_fast;
architecture spwxmit_fast_arch of spwxmit_fast is
-- Convert boolean to std_logic.
type bool_to_logic_type is array(boolean) of std_ulogic;
constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
-- Data records passed between clock domains.
type token_type is record
tick: std_ulogic; -- send time code
fct: std_ulogic; -- send FCT
fctpiggy: std_ulogic; -- send FCT and N-char
flag: std_ulogic; -- send EOP or EEP
char: std_logic_vector(7 downto 0); -- character or time code
end record;
-- Registers in txclk domain
type txregs_type is record
-- sync to system clock domain
txflip0: std_ulogic;
txflip1: std_ulogic;
-- stage B
b_update: std_ulogic;
b_mux: std_ulogic;
b_txflip: std_ulogic;
b_valid: std_ulogic;
b_token: token_type;
-- stage C
c_update: std_ulogic;
c_busy: std_ulogic;
c_esc: std_ulogic;
c_fct: std_ulogic;
c_bits: std_logic_vector(8 downto 0);
-- stage D
d_bits: std_logic_vector(8 downto 0);
d_cnt4: std_ulogic;
d_cnt10: std_ulogic;
-- stage E
e_valid: std_ulogic;
e_shift: std_logic_vector(9 downto 0);
e_count: std_logic_vector(9 downto 0);
e_parity: std_ulogic;
-- stage F
f_spwdo: std_ulogic;
f_spwso: std_ulogic;
-- tx clock enable logic
txclken: std_ulogic;
txclkpre: std_ulogic;
txclkcnt: std_logic_vector(7 downto 0);
txclkcy: std_logic_vector(2 downto 0);
txclkdone: std_logic_vector(1 downto 0);
txclkdiv: std_logic_vector(7 downto 0);
txdivnorm: std_ulogic;
end record;
-- Registers in system clock domain
type regs_type is record
-- sync status to txclk domain
txenreg: std_ulogic;
txdivreg: std_logic_vector(7 downto 0);
txdivnorm: std_ulogic;
txdivtmp: std_logic_vector(1 downto 0);
txdivsafe: std_ulogic;
-- data stream to txclk domain
sysflip0: std_ulogic;
sysflip1: std_ulogic;
token0: token_type;
token1: token_type;
tokmux: std_ulogic;
-- transmitter management
pend_fct: std_ulogic; -- '1' if an outgoing FCT is pending
pend_char: std_ulogic; -- '1' if an outgoing N-Char is pending
pend_data: std_logic_vector(8 downto 0); -- control flag and data bits of pending char
pend_tick: std_ulogic; -- '1' if an outgoing time tick is pending
pend_time: std_logic_vector(7 downto 0); -- data bits of pending time tick
allow_fct: std_ulogic; -- '1' when allowed to send FCTs
allow_char: std_ulogic; -- '1' when allowed to send data and time
sent_fct: std_ulogic; -- '1' when at least one FCT token was sent
end record;
-- Initial state of system clock domain
constant token_reset: token_type := (
tick => '0',
fct => '0',
fctpiggy => '0',
flag => '0',
char => (others => '0') );
constant regs_reset: regs_type := (
txenreg => '0',
txdivreg => (others => '0'),
txdivnorm => '0',
txdivtmp => "00",
txdivsafe => '0',
sysflip0 => '0',
sysflip1 => '0',
token0 => token_reset,
token1 => token_reset,
tokmux => '0',
pend_fct => '0',
pend_char => '0',
pend_data => (others => '0'),
pend_tick => '0',
pend_time => (others => '0'),
allow_fct => '0',
allow_char => '0',
sent_fct => '0' );
-- Signals that are re-synchronized from system clock to txclk domain.
type synctx_type is record
rstn: std_ulogic;
sysflip0: std_ulogic;
sysflip1: std_ulogic;
txen: std_ulogic;
txdivsafe: std_ulogic;
end record;
-- Signals that are re-synchronized from txclk to system clock domain.
type syncsys_type is record
txflip0: std_ulogic;
txflip1: std_ulogic;
end record;
-- Registers
signal rtx: txregs_type;
signal rtxin: txregs_type;
signal r: regs_type := regs_reset;
signal rin: regs_type;
-- Synchronized signals after crossing clock domains.
signal synctx: synctx_type;
signal syncsys: syncsys_type;
-- Output flip-flops
signal s_spwdo: std_logic;
signal s_spwso: std_logic;
-- Force use of IOB flip-flops
attribute IOB: string;
attribute IOB of s_spwdo: signal is "TRUE";
attribute IOB of s_spwso: signal is "TRUE";
begin
-- Reset synchronizer for txclk domain.
synctx_rst: syncdff
port map ( clk => txclk, rst => rst, di => '1', do => synctx.rstn );
-- Synchronize signals from system clock domain to txclk domain.
synctx_sysflip0: syncdff
port map ( clk => txclk, rst => rst, di => r.sysflip0, do => synctx.sysflip0 );
synctx_sysflip1: syncdff
port map ( clk => txclk, rst => rst, di => r.sysflip1, do => synctx.sysflip1 );
synctx_txen: syncdff
port map ( clk => txclk, rst => rst, di => r.txenreg, do => synctx.txen );
synctx_txdivsafe: syncdff
port map ( clk => txclk, rst => rst, di => r.txdivsafe, do => synctx.txdivsafe );
-- Synchronize signals from txclk domain to system clock domain.
syncsys_txflip0: syncdff
port map ( clk => clk, rst => rst, di => rtx.txflip0, do => syncsys.txflip0 );
syncsys_txflip1: syncdff
port map ( clk => clk, rst => rst, di => rtx.txflip1, do => syncsys.txflip1 );
-- Drive SpaceWire output signals
spw_do <= s_spwdo;
spw_so <= s_spwso;
-- Combinatorial process
process (r, rtx, rst, divcnt, xmiti, synctx, syncsys) is
variable v: regs_type;
variable vtx: txregs_type;
variable v_needtoken: std_ulogic;
variable v_havetoken: std_ulogic;
variable v_token: token_type;
begin
v := r;
vtx := rtx;
v_needtoken := '0';
v_havetoken := '0';
v_token := token_reset;
-- ---- FAST CLOCK DOMAIN ----
-- Stage B: Multiplex tokens from system clock domain.
-- Update stage B three bit periods after updating stage C
-- (i.e. in time for the next update of stage C).
-- Do not update stage B if stage C is indicating that it needs to
-- send a second token to complete its task.
vtx.b_update := rtx.txclken and rtx.e_count(0) and (not rtx.c_busy);
if rtx.b_mux = '0' then
vtx.b_txflip := rtx.txflip0;
else
vtx.b_txflip := rtx.txflip1;
end if;
if rtx.b_update = '1' then
if rtx.b_mux = '0' then
-- get token from slot 0
vtx.b_valid := synctx.sysflip0 xor rtx.b_txflip;
vtx.b_token := r.token0;
-- update mux flag if we got a valid token
vtx.b_mux := synctx.sysflip0 xor rtx.b_txflip;
vtx.txflip0 := synctx.sysflip0;
vtx.txflip1 := rtx.txflip1;
else
-- get token from slot 1
vtx.b_valid := synctx.sysflip1 xor rtx.b_txflip;
vtx.b_token := r.token1;
-- update mux flag if we got a valid token
vtx.b_mux := not (synctx.sysflip1 xor rtx.b_txflip);
vtx.txflip0 := rtx.txflip0;
vtx.txflip1 := synctx.sysflip1;
end if;
end if;
-- Stage C: Prepare to transmit EOP, EEP or a data character.
vtx.c_update := rtx.txclken and rtx.e_count(3);
if rtx.c_update = '1' then
-- NULL is broken into two tokens: ESC + FCT.
-- Time-codes are broken into two tokens: ESC + char.
-- Enable c_esc on the first pass of a NULL or a time-code.
vtx.c_esc := (rtx.b_token.tick or (not rtx.b_valid)) and
(not rtx.c_esc);
-- Enable c_fct on the first pass of an FCT and on
-- the second pass of a NULL (also the first pass, but c_esc
-- is stronger than c_fct).
vtx.c_fct := (rtx.b_token.fct and (not rtx.c_busy)) or
(not rtx.b_valid);
-- Enable c_busy on the first pass of a NULL or a time-code
-- or a piggy-backed FCT. This will tell stage B that we are
-- not done yet.
vtx.c_busy := (rtx.b_token.tick or (not rtx.b_valid) or
rtx.b_token.fctpiggy) and (not rtx.c_busy);
if rtx.b_token.flag = '1' then
if rtx.b_token.char(0) = '0' then
-- prepare to send EOP
vtx.c_bits := "000000101"; -- EOP = P101
else
-- prepare to send EEP
vtx.c_bits := "000000011"; -- EEP = P110
end if;
else
-- prepare to send data char
vtx.c_bits := rtx.b_token.char & '0';
end if;
end if;
-- Stage D: Prepare to transmit FCT, ESC, or the stuff from stage C.
if rtx.c_esc = '1' then
-- prepare to send ESC
vtx.d_bits := "000000111"; -- ESC = P111
vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit
vtx.d_cnt10 := '0';
elsif rtx.c_fct = '1' then
-- prepare to send FCT
vtx.d_bits := "000000001"; -- FCT = P100
vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit
vtx.d_cnt10 := '0';
else
-- send the stuff from stage C.
vtx.d_bits := rtx.c_bits;
vtx.d_cnt4 := rtx.c_bits(0);
vtx.d_cnt10 := not rtx.c_bits(0);
end if;
-- Stage E: Shift register.
if rtx.txclken = '1' then
if rtx.e_count(0) = '1' then
-- reload shift register; output parity bit
vtx.e_valid := '1';
vtx.e_shift(vtx.e_shift'high downto 1) := rtx.d_bits;
vtx.e_shift(0) := not (rtx.e_parity xor rtx.d_bits(0));
vtx.e_count := rtx.d_cnt10 & "00000" & rtx.d_cnt4 & "000";
vtx.e_parity := rtx.d_bits(0);
else
-- shift bits to output; update parity bit
vtx.e_shift := '0' & rtx.e_shift(rtx.e_shift'high downto 1);
vtx.e_count := '0' & rtx.e_count(rtx.e_count'high downto 1);
vtx.e_parity := rtx.e_parity xor rtx.e_shift(1);
end if;
end if;
-- Stage F: Data/strobe encoding.
if rtx.txclken = '1' then
if rtx.e_valid = '1' then
-- output next data/strobe bits
vtx.f_spwdo := rtx.e_shift(0);
vtx.f_spwso := not (rtx.e_shift(0) xor rtx.f_spwdo xor rtx.f_spwso);
else
-- gentle reset of spacewire signals
vtx.f_spwdo := rtx.f_spwdo and rtx.f_spwso;
vtx.f_spwso := '0';
end if;
end if;
-- Generate tx clock enable
-- An 8-bit counter decrements on every clock. A txclken pulse is
-- produced 2 cycles after the counter reaches value 2. Counter reload
-- values of 0 and 1 are handled as special cases.
-- count down in blocks of two bits
vtx.txclkcnt(1 downto 0) := std_logic_vector(unsigned(rtx.txclkcnt(1 downto 0)) - 1);
vtx.txclkcnt(3 downto 2) := std_logic_vector(unsigned(rtx.txclkcnt(3 downto 2)) - unsigned(rtx.txclkcy(0 downto 0)));
vtx.txclkcnt(5 downto 4) := std_logic_vector(unsigned(rtx.txclkcnt(5 downto 4)) - unsigned(rtx.txclkcy(1 downto 1)));
vtx.txclkcnt(7 downto 6) := std_logic_vector(unsigned(rtx.txclkcnt(7 downto 6)) - unsigned(rtx.txclkcy(2 downto 2)));
-- propagate carry in blocks of two bits
vtx.txclkcy(0) := bool_to_logic(rtx.txclkcnt(1 downto 0) = "00");
vtx.txclkcy(1) := rtx.txclkcy(0) and bool_to_logic(rtx.txclkcnt(3 downto 2) = "00");
vtx.txclkcy(2) := rtx.txclkcy(1) and bool_to_logic(rtx.txclkcnt(5 downto 4) = "00");
-- detect value 2 in counter
vtx.txclkdone(0) := bool_to_logic(rtx.txclkcnt(3 downto 0) = "0010");
vtx.txclkdone(1) := bool_to_logic(rtx.txclkcnt(7 downto 4) = "0000");
-- trigger txclken
vtx.txclken := (rtx.txclkdone(0) and rtx.txclkdone(1)) or rtx.txclkpre;
vtx.txclkpre := (not rtx.txdivnorm) and ((not rtx.txclkpre) or (not rtx.txclkdiv(0)));
-- reload counter
if rtx.txclken = '1' then
vtx.txclkcnt := rtx.txclkdiv;
vtx.txclkcy := "000";
vtx.txclkdone := "00";
end if;
-- Synchronize txclkdiv
if synctx.txdivsafe = '1' then
vtx.txclkdiv := r.txdivreg;
vtx.txdivnorm := r.txdivnorm;
end if;
-- Transmitter disabled.
if synctx.txen = '0' then
vtx.txflip0 := '0';
vtx.txflip1 := '0';
vtx.b_update := '0';
vtx.b_mux := '0';
vtx.b_valid := '0';
vtx.c_update := '0';
vtx.c_busy := '1';
vtx.c_esc := '1'; -- need to send 2nd part of NULL
vtx.c_fct := '1';
vtx.d_bits := "000000111"; -- ESC = P111
vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit
vtx.d_cnt10 := '0';
vtx.e_valid := '0';
vtx.e_parity := '0';
vtx.e_count := (0 => '1', others => '0');
end if;
-- Reset.
if synctx.rstn = '0' then
vtx.f_spwdo := '0';
vtx.f_spwso := '0';
vtx.txclken := '0';
vtx.txclkpre := '1';
vtx.txclkcnt := (others => '0');
vtx.txclkdiv := (others => '0');
vtx.txdivnorm := '0';
end if;
-- ---- SYSTEM CLOCK DOMAIN ----
-- Hold divcnt and txen for use by txclk domain.
v.txdivtmp := std_logic_vector(unsigned(r.txdivtmp) - 1);
if r.txdivtmp = "00" then
if r.txdivsafe = '0' then
-- Latch the current value of divcnt and txen.
v.txdivsafe := '1';
v.txdivtmp := "01";
v.txdivreg := divcnt;
if unsigned(divcnt(divcnt'high downto 1)) = 0 then
v.txdivnorm := '0';
else
v.txdivnorm := '1';
end if;
v.txenreg := xmiti.txen;
else
-- Drop the txdivsafe flag but keep latched values.
v.txdivsafe := '0';
end if;
end if;
-- Pass falling edge of txen signal as soon as possible.
if xmiti.txen = '0' then
v.txenreg := '0';
end if;
-- Store requests for FCT transmission.
if xmiti.fct_in = '1' and r.allow_fct = '1' then
v.pend_fct := '1';
end if;
if xmiti.txen = '0' then
-- Transmitter disabled; reset state.
v.sysflip0 := '0';
v.sysflip1 := '0';
v.tokmux := '0';
v.pend_fct := '0';
v.pend_char := '0';
v.pend_tick := '0';
v.allow_fct := '0';
v.allow_char := '0';
v.sent_fct := '0';
else
-- Determine if a new token is needed.
if r.tokmux = '0' then
if r.sysflip0 = syncsys.txflip0 then
v_needtoken := '1';
end if;
else
if r.sysflip1 = syncsys.txflip1 then
v_needtoken := '1';
end if;
end if;
-- Prepare new token.
if r.allow_char = '1' and r.pend_tick = '1' then
-- prepare to send time code
v_token.tick := '1';
v_token.fct := '0';
v_token.fctpiggy := '0';
v_token.flag := '0';
v_token.char := r.pend_time;
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_tick := '0';
end if;
else
if r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then
-- prepare to send FCT
v_token.fct := '1';
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_fct := '0';
v.sent_fct := '1';
end if;
end if;
if r.allow_char = '1' and r.pend_char = '1' then
-- prepare to send N-Char
-- Note: it is possible to send an FCT and an N-Char
-- together by enabling the fctpiggy flag.
v_token.fctpiggy := v_token.fct;
v_token.flag := r.pend_data(8);
v_token.char := r.pend_data(7 downto 0);
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_char := '0';
end if;
end if;
end if;
-- Put new token in slot.
if v_havetoken = '1' then
if r.tokmux = '0' then
if r.sysflip0 = syncsys.txflip0 then
v.sysflip0 := not r.sysflip0;
v.token0 := v_token;
v.tokmux := '1';
end if;
else
if r.sysflip1 = syncsys.txflip1 then
v.sysflip1 := not r.sysflip1;
v.token1 := v_token;
v.tokmux := '0';
end if;
end if;
end if;
-- Determine whether we are allowed to send FCTs and characters
v.allow_fct := not xmiti.stnull;
v.allow_char := (not xmiti.stnull) and (not xmiti.stfct) and r.sent_fct;
-- Store request for data transmission.
if xmiti.txwrite = '1' and r.allow_char = '1' and r.pend_char = '0' then
v.pend_char := '1';
v.pend_data := xmiti.txflag & xmiti.txdata;
end if;
-- Store requests for time tick transmission.
if xmiti.tick_in = '1' then
v.pend_tick := '1';
v.pend_time := xmiti.ctrl_in & xmiti.time_in;
end if;
end if;
-- Synchronous reset of system clock domain.
if rst = '1' then
v := regs_reset;
end if;
-- Drive outputs.
-- Note: the outputs are combinatorially dependent on certain inputs.
-- Set fctack high if (FCT requested) and (FCTs allowed) AND
-- (no FCT pending)
xmito.fctack <= xmiti.fct_in and xmiti.txen and r.allow_fct and
(not r.pend_fct);
-- Set txrdy high if (character requested) AND (characters allowed) AND
-- (no character pending)
xmito.txack <= xmiti.txwrite and xmiti.txen and r.allow_char and
(not r.pend_char);
-- Update registers.
rin <= v;
rtxin <= vtx;
end process;
-- Synchronous process in txclk domain
process (txclk) is
begin
if rising_edge(txclk) then
-- drive spacewire output signals
s_spwdo <= rtx.f_spwdo;
s_spwso <= rtx.f_spwso;
-- update registers
rtx <= rtxin;
end if;
end process;
-- Synchronous process in system clock domain
process (clk) is
begin
if rising_edge(clk) then
-- update registers
r <= rin;
end if;
end process;
end architecture spwxmit_fast_arch;
| mit |
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