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dh1dm/q27 | src/vhdl/PoC/arith/arith_counter_free.vhdl | 2 | 2946 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module: Poc.arith_counter_free
--
-- Authors: Thomas B. Preusser
--
-- Description:
-- ------------
-- Implements a free-running counter that generates a strobe signal
-- every DIVIDER-th cycle the increment input was asserted.
-- There is deliberately no output or specification of the counter
-- value so as to allow an implementation to optimize as much as
-- possible.
-- The implementation guarantees a strobe output directly from a
-- register. It is asserted exactly for one clock after DIVIDER cycles
-- of an asserted increment input have been observed.
--
-- License:
-- ===========================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity arith_counter_free is
generic (
DIVIDER : positive
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
inc : in std_logic;
stb : out std_logic -- End-of-Period Strobe
);
end arith_counter_free;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of arith_counter_free is
begin
genNoDiv: if DIVIDER = 1 generate
process(clk)
begin
if rising_edge(clk) then
stb <= inc;
end if;
end process;
end generate genNoDiv;
genDoDiv: if DIVIDER > 1 generate
-- Note: For DIVIDER=2**K+1, this could be marginally reduced to log2ceil(DIVIDER-1)
-- if it was known that the increment input inc would never be deasserted.
constant N : natural := log2ceil(DIVIDER);
signal Cnt : unsigned(N downto 0) := (others => '0');
signal cin : unsigned(0 downto 0);
begin
cin(0) <= not inc;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= to_unsigned(DIVIDER-2, N+1);
else
Cnt <= Cnt + ite(Cnt(N) = '0', (Cnt'range => '1'), to_unsigned(DIVIDER-1, N+1)) + cin;
end if;
end if;
end process;
stb <= Cnt(N);
end generate genDoDiv;
end rtl;
| agpl-3.0 |
dh1dm/q27 | src/vhdl/queens/queens_slice.vhdl | 1 | 8378 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-- Benedikt Reuter <breutr@gmail.com>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity queens_slice is
generic (
N : positive; -- size of field
L : positive -- number of preplaced outer rings
);
port (
-- Global Clock
clk : in std_logic;
rst : in std_logic;
-- Inputs (strobed)
start : in std_logic; -- Strobe for Start
BH_l : in std_logic_vector(0 to N-2*L-1); -- Blocking for leftmost Column
BU_l : in std_logic_vector(0 to 2*N-4*L-2);
BD_l : in std_logic_vector(0 to 2*N-4*L-2); -- 0 to 6
BV_l : in std_logic_vector(0 to N-2*L-1);
-- Output Strobes
sol : out std_logic;
done : out std_logic
);
end queens_slice;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of queens_slice is
---------------------------------------------------------------------------
-- Matrix to iterate through
-- These types are plain ugly but the multidiemsional tMatrix(<>, <>)
-- is not slicable. Thus, these types are still better than lots of
-- generate loops working through the columns.
subtype tColumn is std_logic_vector(L to N-L-1);
type tField is array(L to N-L-1) of tColumn;
-- Placed Queen Matrix
signal QN : tField := (others => (others => '-'));
component arbit_forward
generic (
N : positive -- Length of Token Chain
);
port (
tin : in std_logic; -- Fed Token
have : in std_logic_vector(0 to N-1); -- Token Owner
pass : in std_logic_vector(0 to N-1); -- Token Passers
grnt : out std_logic_vector(0 to N-1); -- Token Output
tout : out std_logic -- Unused Token
);
end component;
-- Blocking Signals
signal BH : std_logic_vector( L to N-L-1) := (others => '-'); -- Window: L to N-L-1
signal BV : std_logic_vector(2*L+1 to 2*N-2*L-1) := (others => '-'); -- Window: N
-- put shifts left
signal BU : std_logic_vector(2*L+1 to 3*N-4*L-2) := (others => '-'); -- Window: N to 2*N-2*L-1
-- put shifts right
signal BD : std_logic_vector(2*L+1 to 3*N-4*L-2) := (others => '-'); -- Window: N to 2*N-2*L-1
-- put shifts left
signal s : std_logic_vector(L to N-L-1);
signal put : std_logic;
begin
assert false
report LF&
"Queens@TUD Solver Slice " &LF&
"Copyright (C) 2015 Thomas B. Preusser <thomas.preusser@utexas.edu> " &LF&
" Benedikt Reuter <breutr@gmail.com>" &LF&
"This design is free software, and you are welcome to redistribute it " &LF&
"under the conditions of the GPL version 3. " &LF&
"It comes with ABSOLUTELY NO WARRANTY. " &LF&
"For details see the notice in the file COPYING."&LF
severity note;
---------------------------------------------------------------------------
-- Queen Matrix
process(clk)
begin
if rising_edge(clk) then
if put = '1' then
QN(L to N-L-2) <= QN(L+1 to N-L-1);
else
QN(L to N-L-2) <= tColumn'(tColumn'range => '-') & QN(L to N-L-3);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Blocking Signals
process(clk)
begin
if clk'event and clk = '1' then
-- Initialization
if start = '1' then
BH <= BH_l;
BV <= (BV'left to N-1 => '-') & BV_l;
BU <= BU_l & (2*N-2*L to BU'right => '-');
BD <= (BD'left to N-1 => '-') & BD_l;
else
-- In Progress
if put = '1' then
-- Add placed Queen
BH <= BH or s;
BV <= BV(BV'left+1 to BV'right) & '-';
BU <= '-' & BU(BU'left to N-1) & (BU(N to 2*N-2*L-1) or s) & BU(2*N-2*L to BU'right-1);
BD <= BD(BD'left+1 to N-1) & (BD(N to 2*N-2*L-1) or s) & BD(2*N-2*L to BD'right) & '-';
else
-- Clear Queen
BH <= BH and not QN(N-L-2);
BV <= '-' & BV(BV'left to BV'right-1);
BU <= BU(BU'left+1 to N) & (BU(N+1 to 2*N-2*L) and not QN(N-L-2)) & BU(2*N-2*L+1 to BU'right) & '-';
BD <= '-' & BD(BD'left to N-2) & (BD(N-1 to 2*N-2*L-2) and not QN(N-L-2)) & BD(2*N-2*L-1 to BD'right-1);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Placement Calculation
blkPlace : block
-- State
signal CS : std_logic_vector(L to N-L-1) := (others => '0'); -- Column Front Selector
signal Fwd : std_logic := '-'; -- Direction
signal H : std_logic_vector(L to N-L-1) := (others => '-'); -- Last Placement in active Col
-- Combined Blocking
signal pass : std_logic_vector(L to N-L-1);
signal tout : std_logic;
signal st : std_logic_vector(L to N-L-1);
signal tt : std_logic;
begin
-- Combine Blocking Signals
pass <= BH or BD(N to 2*N-2*L-1) or BU(N to 2*N-2*L-1);
col : arbit_forward
generic map (
N => N-2*L
)
port map (
tin => Fwd, -- Richtung (=put)
have => H, -- FWD-> 000000 ; -FWD-> QN(N-2)
pass => pass, -- BH or BU or BD
grnt => st,
tout => tt -- overflow (q(N)) -> Reihe fertig -> keine dame gesetzt
);
tout <= not Fwd when BV(N) = '1' else tt;
s <= (others => '0') when BV(N) = '1' else st;
QN(N-L-1) <= s;
-- Column Front Selector, a shift-based counter with:
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
CS <= (others => '0');
elsif start = '1' then
CS <= (others => '0');
CS(CS'left) <= '1';
else
if put = '1' then
CS <= '0' & CS(CS'left to CS'right-1);
else
CS <= CS(CS'left+1 to CS'right) & '0';
end if;
end if;
end if;
end process;
-- Direction Control
process(clk)
begin
if clk'event and clk = '1' then
if start = '1' or put = '1' then
H <= (others => '0');
Fwd <= '1';
else
H <= QN(N-L-2);
Fwd <= '0';
end if;
end if;
end process;
-- Control
put <= (not tout) and not CS(CS'right);
-- Outputs
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' or start = '1' then
sol <= '0';
done <= '0';
else
sol <= (not tout) and CS(CS'right);
done <= tout and CS(CS'left);
end if;
end if;
end process;
end block blkPlace;
end rtl;
| agpl-3.0 |
dh1dm/q27 | src/vhdl/queens/unframe.vhdl | 1 | 6282 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity unframe is
generic (
SENTINEL : std_logic_vector(7 downto 0); -- Start Byte
PAY_LEN : positive
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dat : in std_logic_vector(7 downto 0);
rx_vld : in std_logic;
rx_got : out std_logic;
odat : out std_logic_vector(7 downto 0);
oeof : out std_logic;
oful : in std_logic;
oput : out std_logic;
ocommit : out std_logic;
orollback : out std_logic
);
end unframe;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of unframe is
-- CRC Table for 0x1D5 (CRC-8)
type tFCS is array(0 to 255) of std_logic_vector(7 downto 0);
constant FCS : tFCS := (
x"00", x"D5", x"7F", x"AA", x"FE", x"2B", x"81", x"54",
x"29", x"FC", x"56", x"83", x"D7", x"02", x"A8", x"7D",
x"52", x"87", x"2D", x"F8", x"AC", x"79", x"D3", x"06",
x"7B", x"AE", x"04", x"D1", x"85", x"50", x"FA", x"2F",
x"A4", x"71", x"DB", x"0E", x"5A", x"8F", x"25", x"F0",
x"8D", x"58", x"F2", x"27", x"73", x"A6", x"0C", x"D9",
x"F6", x"23", x"89", x"5C", x"08", x"DD", x"77", x"A2",
x"DF", x"0A", x"A0", x"75", x"21", x"F4", x"5E", x"8B",
x"9D", x"48", x"E2", x"37", x"63", x"B6", x"1C", x"C9",
x"B4", x"61", x"CB", x"1E", x"4A", x"9F", x"35", x"E0",
x"CF", x"1A", x"B0", x"65", x"31", x"E4", x"4E", x"9B",
x"E6", x"33", x"99", x"4C", x"18", x"CD", x"67", x"B2",
x"39", x"EC", x"46", x"93", x"C7", x"12", x"B8", x"6D",
x"10", x"C5", x"6F", x"BA", x"EE", x"3B", x"91", x"44",
x"6B", x"BE", x"14", x"C1", x"95", x"40", x"EA", x"3F",
x"42", x"97", x"3D", x"E8", x"BC", x"69", x"C3", x"16",
x"EF", x"3A", x"90", x"45", x"11", x"C4", x"6E", x"BB",
x"C6", x"13", x"B9", x"6C", x"38", x"ED", x"47", x"92",
x"BD", x"68", x"C2", x"17", x"43", x"96", x"3C", x"E9",
x"94", x"41", x"EB", x"3E", x"6A", x"BF", x"15", x"C0",
x"4B", x"9E", x"34", x"E1", x"B5", x"60", x"CA", x"1F",
x"62", x"B7", x"1D", x"C8", x"9C", x"49", x"E3", x"36",
x"19", x"CC", x"66", x"B3", x"E7", x"32", x"98", x"4D",
x"30", x"E5", x"4F", x"9A", x"CE", x"1B", x"B1", x"64",
x"72", x"A7", x"0D", x"D8", x"8C", x"59", x"F3", x"26",
x"5B", x"8E", x"24", x"F1", x"A5", x"70", x"DA", x"0F",
x"20", x"F5", x"5F", x"8A", x"DE", x"0B", x"A1", x"74",
x"09", x"DC", x"76", x"A3", x"F7", x"22", x"88", x"5D",
x"D6", x"03", x"A9", x"7C", x"28", x"FD", x"57", x"82",
x"FF", x"2A", x"80", x"55", x"01", x"D4", x"7E", x"AB",
x"84", x"51", x"FB", x"2E", x"7A", x"AF", x"05", x"D0",
x"AD", x"78", x"D2", x"07", x"53", x"86", x"2C", x"F9"
);
-- State Machine
type tState is (Idle, Load, CheckCRC);
signal State : tState := Idle;
signal NextState : tState;
signal CRC : std_logic_vector(7 downto 0) := (others => '-');
signal Start : std_logic;
signal Append : std_logic;
signal Last : std_logic;
signal CRC_next : std_logic_vector(7 downto 0);
begin
-- State
CRC_next <= FCS(to_integer(unsigned(CRC xor rx_dat)));
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
CRC <= (others => '-');
else
State <= NextState;
if Start = '1' then
CRC <= FCS(255);
elsif Append = '1' then
CRC <= CRC_next;
end if;
end if;
end if;
end process;
process(State, rx_vld, rx_dat, oful, Last, CRC)
begin
NextState <= State;
Start <= '0';
Append <= '0';
odat <= (others => '-');
oeof <= Last;
oput <= '0';
ocommit <= '0';
orollback <= '0';
rx_got <= '0';
if rx_vld = '1' then
case State is
when Idle =>
rx_got <= '1';
if rx_dat = SENTINEL then
Start <= '1';
NextState <= Load;
end if;
when Load =>
if oful = '0' then
odat <= rx_dat;
oput <= '1';
rx_got <= '1';
Append <= '1';
if Last = '1' then
NextState <= CheckCRC;
end if;
end if;
when CheckCRC =>
if rx_dat = CRC then
ocommit <= '1';
else
orollback <= '1';
end if;
NextState <= Idle;
end case;
end if;
end process;
-- Payload Counter
genPayEq1: if PAY_LEN = 1 generate
Last <= '1';
end generate genPayEq1;
genPayGt1: if PAY_LEN > 1 generate
signal Cnt : unsigned(log2ceil(PAY_LEN-1) downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= (others => '-');
else
if Start = '1' then
Cnt <= to_unsigned(PAY_LEN-2, Cnt'length);
elsif Append = '1' then
Cnt <= Cnt - 1;
end if;
end if;
end if;
end process;
Last <= Cnt(Cnt'left);
end generate genPayGt1;
end rtl;
| agpl-3.0 |
UnofficialRepos/OSVVM | ResolutionPkg.vhd | 1 | 16067 | --
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@SynthWorks.com
-- Contributor(s):
-- Jim Lewis email: jim@SynthWorks.com
--
-- Package Defines
-- resolved resolution functions for integer, real, and time
-- types resolved_integer, resolved_real, resolved_time
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2021 2021.06 Moved To/FromTransaction and SafeResize to Resize package
-- 12/2020 2020.12 Updated ToTransaction and FromTransaction with length parameter.
-- Downsizing now permitted when it does not change the value.
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Removed Asserts as they are not working as intended.
-- See ResolutionPkg_debug as it uses Alerts to correctly detect errors
-- 05/2015 2015.05 Added Alerts
-- -- Replaced Alerts with asserts as alerts are illegal in pure functions
-- 02/2009 1.0 VHDL-2008 STANDARD VERSION
-- 09/2006 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package ResolutionPkg is
constant MULTIPLE_DRIVER_SEVERITY : severity_level := ERROR ;
--
-- Note that not all simulators support resolution functions of the form:
-- subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
--
-- Hence, types of the form are offered as a temporary workaround until they do:
-- std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
--
-- resolved_max
-- return maximum value.
-- No initializations required on ports, default of type'left is ok
function resolved_max ( s : std_ulogic_vector) return std_ulogic ;
subtype std_logic_max is resolved_max std_ulogic ;
subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
type std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype unsigned_max is (resolved_max) unresolved_unsigned ;
type unsigned_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype signed_max is (resolved_max) unresolved_signed ;
type signed_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
function resolved_max ( s : bit_vector) return bit ;
subtype bit_max is resolved_max bit ;
subtype bit_vector_max is (resolved_max) bit_vector ;
type bit_vector_max_c is array (natural range <>) of bit_max ; -- for non VHDL-2008
function resolved_max ( s : integer_vector ) return integer ;
subtype integer_max is resolved_max integer ;
subtype integer_vector_max is (resolved_max) integer_vector ;
type integer_vector_max_c is array (natural range <>) of integer_max ; -- for non VHDL-2008
function resolved_max ( s : time_vector ) return time ;
subtype time_max is resolved_max time ;
subtype time_vector_max is (resolved_max) time_vector ;
type time_vector_max_c is array (natural range <>) of time_max ; -- for non VHDL-2008
function resolved_max ( s : real_vector ) return real ;
subtype real_max is resolved_max real ;
subtype real_vector_max is (resolved_max) real_vector ;
type real_vector_max_c is array (natural range <>) of real_max ; -- for non VHDL-2008
function resolved_max ( s : string) return character ;
subtype character_max is resolved_max character ;
subtype string_max is (resolved_max) string ;
type string_max_c is array (positive range <>) of character_max ; -- for non VHDL-2008
function resolved_max ( s : boolean_vector) return boolean ;
subtype boolean_max is resolved_max boolean ;
subtype boolean_vector_max is (resolved_max) boolean_vector ;
type boolean_vector_max_c is array (natural range <>) of boolean_max ; -- for non VHDL-2008
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
function resolved_sum ( s : integer_vector ) return integer ;
subtype integer_sum is resolved_sum integer ;
subtype integer_vector_sum is (resolved_sum) integer_vector ;
type integer_vector_sum_c is array (natural range <>) of integer_sum ; -- for non VHDL-2008
function resolved_sum ( s : time_vector ) return time ;
subtype time_sum is resolved_sum time ;
subtype time_vector_sum is (resolved_sum) time_vector ;
type time_vector_sum_c is array (natural range <>) of time_sum ; -- for non VHDL-2008
function resolved_sum ( s : real_vector ) return real ;
subtype real_sum is resolved_sum real ;
subtype real_vector_sum is (resolved_sum) real_vector ;
type real_vector_sum_c is array (natural range <>) of real_sum ; -- for non VHDL-2008
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
function resolved_weak (s : std_ulogic_vector) return std_ulogic ; -- no init, type'left
subtype std_logic_weak is resolved_weak std_ulogic ;
subtype std_logic_vector_weak is (resolved_weak) std_ulogic_vector ;
-- legacy stuff
-- requires ports to be initialized to 0 in the appropriate type.
function resolved ( s : integer_vector ) return integer ;
subtype resolved_integer is resolved integer ;
function resolved ( s : time_vector ) return time ;
subtype resolved_time is resolved time ;
function resolved ( s : real_vector ) return real ;
subtype resolved_real is resolved real ;
function resolved (s : string) return character ; -- same as resolved_max
subtype resolved_character is resolved character ;
-- subtype resolved_string is (resolved) string ; -- subtype will replace type later
type resolved_string is array (positive range <>) of resolved_character; -- will change to subtype -- assert but no init
function resolved ( s : boolean_vector) return boolean ; --same as resolved_max
subtype resolved_boolean is resolved boolean ;
end package ResolutionPkg ;
package body ResolutionPkg is
-- resolved_max
-- return maximum value. Assert FAILURE if more than 1 /= type'left
-- No initializations required on ports, default of type'left is ok
-- Optimized version is just the following:
-- ------------------------------------------------------------
-- function resolved_max ( s : <array_type> ) return <element_type> is
-- ------------------------------------------------------------
-- begin
-- return maximum(s) ;
-- end function resolved_max ;
------------------------------------------------------------
function resolved_max (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : bit_vector ) return bit is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : integer_vector ) return integer is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : time_vector ) return time is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : real_vector ) return real is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : string ) return character is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : boolean_vector) return boolean is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
-- resolved_sum - appropriate for numeric types
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
------------------------------------------------------------
function resolved_sum ( s : integer_vector ) return integer is
------------------------------------------------------------
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : time_vector ) return time is
------------------------------------------------------------
variable result : time := 0 sec ;
begin
for i in s'RANGE loop
if s(i) /= time'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : real_vector ) return real is
------------------------------------------------------------
variable result : real := 0.0 ;
begin
for i in s'RANGE loop
if s(i) /= real'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant weak_resolution_table : stdlogic_table := (
-- Resolution order: Z < U < W < X < - < L < H < 0 < 1
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'X', '0', '1', 'U', 'W', 'L', 'H', '-'), -- | U |
('X', 'X', '0', '1', 'X', 'X', 'L', 'H', '-'), -- | X |
('0', '0', '0', '1', '0', '0', '0', '0', '0'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), -- | Z |
('W', 'X', '0', '1', 'W', 'W', 'L', 'H', '-'), -- | W |
('L', 'L', '0', '1', 'L', 'L', 'L', 'H', 'L'), -- | L |
('H', 'H', '0', '1', 'H', 'H', 'W', 'H', 'H'), -- | H |
('-', '-', '0', '1', '-', '-', 'L', 'H', '-') -- | - |
);
------------------------------------------------------------
function resolved_weak (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
variable result : std_ulogic := 'Z' ;
begin
for i in s'RANGE loop
result := weak_resolution_table(result, s(i)) ;
end loop ;
return result ;
end function resolved_weak ;
-- legacy stuff.
-- requires ports to be initialized to 0 in the appropriate type.
------------------------------------------------------------
function resolved ( s : integer_vector ) return integer is
-- requires interface to be initialized to 0
------------------------------------------------------------
variable result : integer := 0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0 then
failed := failed or (result /= 0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on integer" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on integer") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : time_vector ) return time is
-- requires interface to be initialized to 0 ns
------------------------------------------------------------
variable result : time := 0 ns ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) > 0 ns then
failed := failed or (result /= 0 ns) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on time" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on time") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : real_vector ) return real is
-- requires interface to be initialized to 0.0
------------------------------------------------------------
variable result : real := 0.0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0.0 then
failed := failed or (result /= 0.0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on real" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on real") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved (s : string) return character is
-- same as resolved_max
------------------------------------------------------------
variable result : character := NUL ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= NUL then
failed := failed or (result /= NUL) ;
result := maximum(result, s(i)) ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on character" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on character") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : boolean_vector) return boolean is
-- same as resolved_max
------------------------------------------------------------
variable result : boolean := FALSE ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) then
failed := failed or result ;
result := TRUE ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on boolean" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on boolean") ;
return result ;
end function resolved ;
end package body ResolutionPkg ;
| artistic-2.0 |
hterkelsen/mal | vhdl/step6_file.vhdl | 13 | 10297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 |
hterkelsen/mal | vhdl/stepA_mal.vhdl | 11 | 17057 | entity stepA_mal is
end entity stepA_mal;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of stepA_mal is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
procedure is_pair(ast: inout mal_val_ptr; pair: out boolean) is
begin
pair := is_sequential_type(ast.val_type) and ast.seq_val'length > 0;
end procedure is_pair;
procedure quasiquote(ast: inout mal_val_ptr; result: out mal_val_ptr) is
variable ast_pair, a0_pair: boolean;
variable seq: mal_seq_ptr;
variable a0, rest: mal_val_ptr;
begin
is_pair(ast, ast_pair);
if not ast_pair then
seq := new mal_seq(0 to 1);
new_symbol("quote", seq(0));
seq(1) := ast;
new_seq_obj(mal_list, seq, result);
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol and a0.string_val.all = "unquote" then
result := ast.seq_val(1);
else
is_pair(a0, a0_pair);
if a0_pair and a0.seq_val(0).val_type = mal_symbol and a0.seq_val(0).string_val.all = "splice-unquote" then
seq := new mal_seq(0 to 2);
new_symbol("concat", seq(0));
seq(1) := a0.seq_val(1);
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
else
seq := new mal_seq(0 to 2);
new_symbol("cons", seq(0));
quasiquote(a0, seq(1));
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
end if;
end if;
end procedure quasiquote;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure is_macro_call(ast: inout mal_val_ptr; env: inout env_ptr; is_macro: out boolean) is
variable f, env_err: mal_val_ptr;
begin
is_macro := false;
if ast.val_type = mal_list and
ast.seq_val'length > 0 and
ast.seq_val(0).val_type = mal_symbol then
env_get(env, ast.seq_val(0), f, env_err);
if env_err = null and f /= null and
f.val_type = mal_fn and f.func_val.f_is_macro then
is_macro := true;
end if;
end if;
end procedure is_macro_call;
procedure macroexpand(in_ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, macro_fn, call_args, macro_err: mal_val_ptr;
variable is_macro: boolean;
begin
ast := in_ast;
is_macro_call(ast, env, is_macro);
while is_macro loop
env_get(env, ast.seq_val(0), macro_fn, macro_err);
seq_drop_prefix(ast, 1, call_args);
apply_func(macro_fn, call_args, ast, macro_err);
if macro_err /= null then
err := macro_err;
return;
end if;
is_macro_call(ast, env, is_macro);
end loop;
result := ast;
end procedure macroexpand;
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure fn_apply(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn: mal_val_ptr := args.seq_val(0);
variable rest: mal_val_ptr;
variable mid_args_count, rest_args_count: integer;
variable call_args: mal_val_ptr;
variable call_args_seq: mal_seq_ptr;
begin
rest := args.seq_val(args.seq_val'high);
mid_args_count := args.seq_val'length - 2;
rest_args_count := rest.seq_val'length;
call_args_seq := new mal_seq(0 to mid_args_count + rest_args_count - 1);
call_args_seq(0 to mid_args_count - 1) := args.seq_val(1 to args.seq_val'length - 2);
call_args_seq(mid_args_count to call_args_seq'high) := rest.seq_val(rest.seq_val'range);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, result, err);
end procedure fn_apply;
procedure fn_map(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn: mal_val_ptr := args.seq_val(0);
variable lst: mal_val_ptr := args.seq_val(1);
variable call_args, sub_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
new_seq := new mal_seq(lst.seq_val'range); -- (0 to lst.seq_val.length - 1);
for i in new_seq'range loop
new_one_element_list(lst.seq_val(i), call_args);
apply_func(fn, call_args, new_seq(i), sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
new_seq_obj(mal_list, new_seq, result);
end procedure fn_map;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
elsif func_sym.string_val.all = "apply" then
fn_apply(args, result, err);
elsif func_sym.string_val.all = "map" then
fn_map(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, catch_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
macroexpand(ast, env, ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "quote" then
result := ast.seq_val(1);
return;
elsif a0.string_val.all = "quasiquote" then
quasiquote(ast.seq_val(1), ast);
next; -- TCO
elsif a0.string_val.all = "defmacro!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
val.func_val.f_is_macro := true;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "macroexpand" then
macroexpand(ast.seq_val(1), env, result, err);
return;
elsif a0.string_val.all = "try*" then
EVAL(ast.seq_val(1), env, result, sub_err);
if sub_err /= null then
if ast.seq_val'length > 2 and
ast.seq_val(2).val_type = mal_list and
ast.seq_val(2).seq_val(0).val_type = mal_symbol and
ast.seq_val(2).seq_val(0).string_val.all = "catch*" then
new_one_element_list(ast.seq_val(2).seq_val(1), vars);
new_one_element_list(sub_err, call_args);
new_env(catch_env, env, vars, call_args);
EVAL(ast.seq_val(2).seq_val(2), catch_env, result, err);
else
new_nil(result);
end if;
end if;
return;
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! *host-language* " & '"' & "vhdl" & '"' & ")", repl_env, dummy_val, err);
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
RE("(defmacro! cond (fn* (& xs) (if (> (count xs) 0) (list 'if (first xs) (if (> (count xs) 1) (nth xs 1) (throw " & '"' & "odd number of forms to cond" & '"' & ")) (cons 'cond (rest (rest xs)))))))", repl_env, dummy_val, err);
RE("(def! *gensym-counter* (atom 0))", repl_env, dummy_val, err);
RE("(def! gensym (fn* [] (symbol (str " & '"' & "G__" & '"' & " (swap! *gensym-counter* (fn* [x] (+ 1 x)))))))", repl_env, dummy_val, err);
RE("(defmacro! or (fn* (& xs) (if (empty? xs) nil (if (= 1 (count xs)) (first xs) (let* (condvar (gensym)) `(let* (~condvar ~(first xs)) (if ~condvar ~condvar (or ~@(rest xs)))))))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
RE("(println (str " & '"' & "Mal [" & '"' & " *host-language* " & '"' & "]" & '"' & "))", repl_env, dummy_val, err);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 |
foresterre/mal | vhdl/step6_file.vhdl | 13 | 10297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/tg_status.vhd | 20 | 5700 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: tg_status.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:42 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
-- Error signal will be asserted if the comparsion is not equal.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity tg_status is
generic (
TCQ : TIME := 100 ps;
DWIDTH : integer := 32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
manual_clear_error : in std_logic;
data_error_i : in std_logic;
cmp_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
cmp_addr_i : in std_logic_vector(31 downto 0);
cmp_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
mcb_wr_full_i : in std_logic;
mcb_rd_empty_i : in std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
error : out std_logic
);
end entity tg_status;
architecture trans of tg_status is
signal data_error_r : std_logic;
signal error_set : std_logic;
begin
error <= error_set;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_error_r <= data_error_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i or manual_clear_error) = '1') then
-- error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
error_status <= (others => '0');
error_set <= '0';
else
-- latch the first error only
if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
error_status(31 downto 0) <= cmp_addr_i;
error_status(37 downto 32) <= cmp_bl_i;
error_status(40) <= mcb_cmd_full_i;
error_status(41) <= mcb_wr_full_i;
error_status(42) <= mcb_rd_empty_i;
error_set <= '1';
error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
end if;
error_status(39 downto 38) <= "00"; -- reserved
error_status(63 downto 43) <= "000000000000000000000"; -- reserved
end if;
end if;
end process;
end architecture trans;
| cc0-1.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/example_design/rtl/memc1_wrapper.vhd | 2 | 47712 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc1_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector (15 downto 0) := x"0000";
C_MC_CALIBRATION_BA : bit_vector (2 downto 0):= "000";
C_MC_CALIBRATION_CA : bit_vector (11 downto 0):= x"000";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
-- memory interface signals
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
-- mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb1_dram_dqs : inout std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc1_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011";
constant C_PORT_CONFIG : string := "B32_B32_B32_B32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb1_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_lpddr_s6, Coregen 14.7";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb1_lpddr_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=LPDDR, CLK_PERIOD=6000, MEMORY_PART=mt46h16m16xxxx-6-it, MEMORY_DEVICE_WIDTH=16, PA_SR=FULL, OUTPUT_DRV=HALF, PORT_CONFIG=Four 32-bit bi-directional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=4, CLKOUT_DIVIDE=2, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc1_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb1_dram_a,
mcbx_dram_ba => mcb1_dram_ba,
mcbx_dram_ras_n => mcb1_dram_ras_n,
mcbx_dram_cas_n => mcb1_dram_cas_n,
mcbx_dram_we_n => mcb1_dram_we_n,
mcbx_dram_cke => mcb1_dram_cke,
mcbx_dram_clk => mcb1_dram_ck,
mcbx_dram_clk_n => mcb1_dram_ck_n,
mcbx_dram_dq => mcb1_dram_dq,
mcbx_dram_odt => open,
mcbx_dram_ldm => mcb1_dram_dm,
mcbx_dram_udm => mcb1_dram_udm,
mcbx_dram_dqs => mcb1_dram_dqs,
mcbx_dram_dqs_n => open,
mcbx_dram_udqs => mcb1_dram_udqs,
mcbx_dram_udqs_n => open,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb1_rzq,
zio => mcb1_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| cc0-1.0 |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/wr_data_gen.vhd | 20 | 18946 | --*****************************************************************************
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: wr_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose:
-- Reference:
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wr_data_gen is
generic (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
MODE : string := "WR"; --"WR", "RD"
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
last_word_o : out std_logic;
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
data_wr_end_o : out std_logic
);
end entity wr_data_gen;
architecture trans of wr_data_gen is
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
MEM_BURST_LEN : integer := 8;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
cmd_startE : IN STD_LOGIC;
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal cmd_rdyB : std_logic;
signal cmd_rdyC : std_logic;
signal cmd_rdyD : std_logic;
signal cmd_rdyE : std_logic;
signal cmd_rdyF : std_logic;
signal cmd_start : std_logic;
signal cmd_startB : std_logic;
signal cmd_startC : std_logic;
signal cmd_startD : std_logic;
signal cmd_startE : std_logic;
signal cmd_startF : std_logic;
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal walk_cnt : std_logic_vector(2 downto 0);
signal fifo_not_full : std_logic;
signal i : integer;
signal j : integer;
signal w3data : std_logic_vector(31 downto 0);
-- counter to count user burst length
-- bl_i;
signal u_bcount_2 : std_logic;
signal last_word_t : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_o <= data_o_xhdl0;
fifo_not_full <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
data_wr_end_o <= '1';
else
data_wr_end_o <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_start <= cmd_validC_i and cmd_rdyC;
cmd_startB <= cmd_valid_i and cmd_rdyB;
cmd_startC <= cmd_validB_i and cmd_rdyC;
cmd_startD <= cmd_validB_i and cmd_rdyD;
cmd_startE <= cmd_validB_i and cmd_rdyE;
cmd_startF <= cmd_validB_i and cmd_rdyF;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000" ;
elsif (cmd_start = '1') then
if (FAMILY = "SPARTAN6") then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (fifo_not_full = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001" ;
else
user_burst_cnt <= "0000000" ;
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
u_bcount_2 <= '1' ;
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0' ;
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
cmd_rdy_o <= cmd_rdy and fifo_not_full;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1' ;
elsif (cmd_start = '1') then
if (bl_i = "000001") then
cmd_rdy <= '1' ;
else
cmd_rdy <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdy <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyB <= '1' ;
elsif (cmd_startB = '1') then
if (bl_i = "000001") then
cmd_rdyB <= '1' ;
else
cmd_rdyB <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyB <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyC <= '1' ;
elsif (cmd_startC = '1') then
if (bl_i = "000001") then
cmd_rdyC <= '1' ;
else
cmd_rdyC <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyC <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyD <= '1' ;
elsif (cmd_startD = '1') then
if (bl_i = "000001") then
cmd_rdyD <= '1' ;
else
cmd_rdyD <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyD <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyE <= '1' ;
elsif (cmd_startE = '1') then
if (bl_i = "000001") then
cmd_rdyE <= '1' ;
else
cmd_rdyE <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyE <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyF <= '1' ;
elsif (cmd_startF = '1') then
if (bl_i = "000001") then
cmd_rdyF <= '1' ;
else
cmd_rdyF <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyF <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(1)) = '1') then
data_valid <= '0' ;
elsif (cmd_start = '1') then
data_valid <= '1' ;
elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
data_valid <= '0' ;
end if;
end if;
end process;
data_valid_o <= data_valid and fifo_not_full;
s6_wdgen : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_startB,
cmd_startC => cmd_startC,
cmd_startD => cmd_startD,
cmd_startE => cmd_startE,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
v6_wdgen : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_starta => cmd_start,
cmd_startb => cmd_startB,
cmd_startc => cmd_startC,
cmd_startd => cmd_startD,
cmd_starte => cmd_startE,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --m_addr_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
end architecture trans;
| cc0-1.0 |
qu1x/fsio | src/lib/fsio_put.vhd | 1 | 1412 | -- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <n3vu0r@qu1x.org>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
library fsio;
use fsio.fsio.all;
entity fsio_put is
generic (
cap: integer := CAP;
len: integer := LEN
);
port (
clk: in std_logic;
hsi: in std_logic;
hso: out std_logic;
fsi: in std_logic_vector(cap - 1 downto 0);
fso: out std_logic_vector(cap - 1 downto 0);
dat: in std_logic_vector(len - 1 downto 0);
req: out std_logic;
ack: in std_logic
);
end fsio_put;
architecture behavioral of fsio_put is
begin
fso(len - 1 downto 0) <= dat;
req <= hso xor hsi;
ctl: process(clk)
begin
if rising_edge(clk) then
if fso = fsi then
hso <= hso xor (req and ack);
end if;
end if;
end process ctl;
end behavioral;
| agpl-3.0 |
chastell/art-decomp | kiss/opus_nov.vhd | 1 | 3496 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_nov;
architecture behaviour of opus_nov is
constant init0: std_logic_vector(3 downto 0) := "0001";
constant init1: std_logic_vector(3 downto 0) := "1000";
constant init2: std_logic_vector(3 downto 0) := "1100";
constant init4: std_logic_vector(3 downto 0) := "0011";
constant IOwait: std_logic_vector(3 downto 0) := "0000";
constant RMACK: std_logic_vector(3 downto 0) := "1101";
constant WMACK: std_logic_vector(3 downto 0) := "0010";
constant read0: std_logic_vector(3 downto 0) := "1010";
constant read1: std_logic_vector(3 downto 0) := "1111";
constant write0: std_logic_vector(3 downto 0) := "1110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "------";
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
else
case current_state is
when init0 =>
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
elsif std_match(input, "--0--") then next_state <= init1; output <= "110000";
end if;
when init1 =>
if std_match(input, "--00-") then next_state <= init1; output <= "110000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when init2 =>
if std_match(input, "--0--") then next_state <= init4; output <= "110100";
end if;
when init4 =>
if std_match(input, "--01-") then next_state <= init4; output <= "110100";
elsif std_match(input, "--00-") then next_state <= IOwait; output <= "000000";
end if;
when IOwait =>
if std_match(input, "0000-") then next_state <= IOwait; output <= "000000";
elsif std_match(input, "1000-") then next_state <= init1; output <= "110000";
elsif std_match(input, "01000") then next_state <= read0; output <= "101000";
elsif std_match(input, "11000") then next_state <= write0; output <= "100010";
elsif std_match(input, "01001") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "11001") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when RMACK =>
if std_match(input, "--0-0") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= read0; output <= "101000";
end if;
when WMACK =>
if std_match(input, "--0-0") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= write0; output <= "100010";
end if;
when read0 =>
if std_match(input, "--0--") then next_state <= read1; output <= "101001";
end if;
when read1 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when write0 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when others => next_state <= "----"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/ex6_rnd.vhd | 1 | 4231 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_rnd;
architecture behaviour of ex6_rnd is
constant s1: std_logic_vector(2 downto 0) := "101";
constant s3: std_logic_vector(2 downto 0) := "010";
constant s2: std_logic_vector(2 downto 0) := "011";
constant s4: std_logic_vector(2 downto 0) := "110";
constant s5: std_logic_vector(2 downto 0) := "111";
constant s6: std_logic_vector(2 downto 0) := "001";
constant s7: std_logic_vector(2 downto 0) := "000";
constant s8: std_logic_vector(2 downto 0) := "100";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--------";
case current_state is
when s1 =>
if std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11000000";
elsif std_match(input, "10---") then next_state <= s4; output <= "00101000";
end if;
when s2 =>
if std_match(input, "0-0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--1--") then next_state <= s5; output <= "00001110";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s3 =>
if std_match(input, "10---") then next_state <= s4; output <= "00111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11010000";
elsif std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "01---") then next_state <= s6; output <= "00110101";
end if;
when s4 =>
if std_match(input, "010--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "--1--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "000--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s5 =>
if std_match(input, "1-10-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--11-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "0-10-") then next_state <= s5; output <= "00001110";
end if;
when s6 =>
if std_match(input, "----1") then next_state <= s2; output <= "11000001";
elsif std_match(input, "10--0") then next_state <= s4; output <= "00101001";
elsif std_match(input, "00--0") then next_state <= s2; output <= "11000001";
elsif std_match(input, "11--0") then next_state <= s3; output <= "10111001";
elsif std_match(input, "01--0") then next_state <= s6; output <= "00100101";
end if;
when s7 =>
if std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "011--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "001--") then next_state <= s2; output <= "11000000";
end if;
when s8 =>
if std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "0-1--") then next_state <= s8; output <= "10000100";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
end if;
when others => next_state <= "---"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/dk16_jed.vhd | 1 | 12212 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk16_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk16_jed;
architecture behaviour of dk16_jed is
constant state_1: std_logic_vector(4 downto 0) := "11000";
constant state_3: std_logic_vector(4 downto 0) := "11100";
constant state_2: std_logic_vector(4 downto 0) := "01000";
constant state_4: std_logic_vector(4 downto 0) := "01010";
constant state_5: std_logic_vector(4 downto 0) := "01001";
constant state_6: std_logic_vector(4 downto 0) := "11011";
constant state_7: std_logic_vector(4 downto 0) := "11001";
constant state_9: std_logic_vector(4 downto 0) := "11010";
constant state_8: std_logic_vector(4 downto 0) := "10010";
constant state_15: std_logic_vector(4 downto 0) := "11110";
constant state_10: std_logic_vector(4 downto 0) := "10100";
constant state_14: std_logic_vector(4 downto 0) := "11101";
constant state_11: std_logic_vector(4 downto 0) := "10110";
constant state_12: std_logic_vector(4 downto 0) := "10000";
constant state_20: std_logic_vector(4 downto 0) := "01110";
constant state_13: std_logic_vector(4 downto 0) := "11111";
constant state_16: std_logic_vector(4 downto 0) := "10011";
constant state_17: std_logic_vector(4 downto 0) := "10001";
constant state_18: std_logic_vector(4 downto 0) := "01111";
constant state_19: std_logic_vector(4 downto 0) := "01100";
constant state_21: std_logic_vector(4 downto 0) := "00100";
constant state_22: std_logic_vector(4 downto 0) := "00101";
constant state_23: std_logic_vector(4 downto 0) := "01101";
constant state_24: std_logic_vector(4 downto 0) := "10111";
constant state_25: std_logic_vector(4 downto 0) := "10101";
constant state_26: std_logic_vector(4 downto 0) := "01011";
constant state_27: std_logic_vector(4 downto 0) := "00111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "00") then next_state <= state_3; output <= "001";
elsif std_match(input, "01") then next_state <= state_10; output <= "001";
elsif std_match(input, "10") then next_state <= state_11; output <= "001";
elsif std_match(input, "11") then next_state <= state_12; output <= "001";
end if;
when state_2 =>
if std_match(input, "00") then next_state <= state_1; output <= "001";
elsif std_match(input, "01") then next_state <= state_2; output <= "001";
elsif std_match(input, "10") then next_state <= state_8; output <= "001";
elsif std_match(input, "11") then next_state <= state_9; output <= "001";
end if;
when state_3 =>
if std_match(input, "00") then next_state <= state_4; output <= "001";
elsif std_match(input, "01") then next_state <= state_5; output <= "001";
elsif std_match(input, "10") then next_state <= state_6; output <= "001";
elsif std_match(input, "11") then next_state <= state_7; output <= "001";
end if;
when state_4 =>
if std_match(input, "00") then next_state <= state_4; output <= "010";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "010";
elsif std_match(input, "11") then next_state <= state_7; output <= "010";
end if;
when state_5 =>
if std_match(input, "00") then next_state <= state_1; output <= "010";
elsif std_match(input, "01") then next_state <= state_2; output <= "010";
elsif std_match(input, "10") then next_state <= state_16; output <= "010";
elsif std_match(input, "11") then next_state <= state_17; output <= "010";
end if;
when state_6 =>
if std_match(input, "00") then next_state <= state_3; output <= "010";
elsif std_match(input, "01") then next_state <= state_21; output <= "010";
elsif std_match(input, "10") then next_state <= state_10; output <= "010";
elsif std_match(input, "11") then next_state <= state_22; output <= "010";
end if;
when state_7 =>
if std_match(input, "00") then next_state <= state_9; output <= "010";
elsif std_match(input, "01") then next_state <= state_18; output <= "010";
elsif std_match(input, "10") then next_state <= state_19; output <= "010";
elsif std_match(input, "11") then next_state <= state_20; output <= "010";
end if;
when state_8 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_26; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_9 =>
if std_match(input, "00") then next_state <= state_1; output <= "000";
elsif std_match(input, "01") then next_state <= state_5; output <= "000";
elsif std_match(input, "10") then next_state <= state_6; output <= "000";
elsif std_match(input, "11") then next_state <= state_7; output <= "000";
end if;
when state_10 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_1; output <= "000";
elsif std_match(input, "11") then next_state <= state_2; output <= "000";
end if;
when state_11 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_24; output <= "000";
elsif std_match(input, "11") then next_state <= state_25; output <= "000";
end if;
when state_12 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_13 =>
if std_match(input, "00") then next_state <= state_3; output <= "101";
elsif std_match(input, "01") then next_state <= state_10; output <= "101";
elsif std_match(input, "10") then next_state <= state_11; output <= "101";
elsif std_match(input, "11") then next_state <= state_12; output <= "101";
end if;
when state_14 =>
if std_match(input, "00") then next_state <= state_1; output <= "101";
elsif std_match(input, "01") then next_state <= state_2; output <= "101";
elsif std_match(input, "10") then next_state <= state_8; output <= "101";
elsif std_match(input, "11") then next_state <= state_9; output <= "101";
end if;
when state_15 =>
if std_match(input, "00") then next_state <= state_4; output <= "101";
elsif std_match(input, "01") then next_state <= state_5; output <= "101";
elsif std_match(input, "10") then next_state <= state_6; output <= "101";
elsif std_match(input, "11") then next_state <= state_7; output <= "101";
end if;
when state_16 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_17 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_27; output <= "000";
end if;
when state_18 =>
if std_match(input, "00") then next_state <= state_4; output <= "100";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "100";
elsif std_match(input, "11") then next_state <= state_7; output <= "100";
end if;
when state_19 =>
if std_match(input, "00") then next_state <= state_18; output <= "100";
elsif std_match(input, "01") then next_state <= state_23; output <= "010";
elsif std_match(input, "10") then next_state <= state_24; output <= "100";
elsif std_match(input, "11") then next_state <= state_25; output <= "100";
end if;
when state_20 =>
if std_match(input, "00") then next_state <= state_19; output <= "100";
elsif std_match(input, "01") then next_state <= state_20; output <= "010";
elsif std_match(input, "10") then next_state <= state_9; output <= "100";
elsif std_match(input, "11") then next_state <= state_26; output <= "100";
end if;
when state_21 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_22 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "100";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_23 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_24 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_25 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_26 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_21; output <= "000";
end if;
when state_27 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/dk512_hot.vhd | 1 | 4742 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_hot;
architecture behaviour of dk512_hot is
constant state_1: std_logic_vector(14 downto 0) := "100000000000000";
constant state_8: std_logic_vector(14 downto 0) := "010000000000000";
constant state_2: std_logic_vector(14 downto 0) := "001000000000000";
constant state_4: std_logic_vector(14 downto 0) := "000100000000000";
constant state_3: std_logic_vector(14 downto 0) := "000010000000000";
constant state_5: std_logic_vector(14 downto 0) := "000001000000000";
constant state_6: std_logic_vector(14 downto 0) := "000000100000000";
constant state_13: std_logic_vector(14 downto 0) := "000000010000000";
constant state_7: std_logic_vector(14 downto 0) := "000000001000000";
constant state_9: std_logic_vector(14 downto 0) := "000000000100000";
constant state_10: std_logic_vector(14 downto 0) := "000000000010000";
constant state_11: std_logic_vector(14 downto 0) := "000000000001000";
constant state_12: std_logic_vector(14 downto 0) := "000000000000100";
constant state_14: std_logic_vector(14 downto 0) := "000000000000010";
constant state_15: std_logic_vector(14 downto 0) := "000000000000001";
signal current_state, next_state: std_logic_vector(14 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---------------"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_9; output <= "000";
end if;
when state_2 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "000";
end if;
when state_3 =>
if std_match(input, "0") then next_state <= state_5; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when state_4 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_11; output <= "000";
end if;
when state_5 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_12; output <= "000";
end if;
when state_6 =>
if std_match(input, "0") then next_state <= state_13; output <= "000";
elsif std_match(input, "1") then next_state <= state_14; output <= "000";
end if;
when state_7 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_15; output <= "000";
end if;
when state_8 =>
if std_match(input, "0") then next_state <= state_1; output <= "001";
elsif std_match(input, "1") then next_state <= state_2; output <= "001";
end if;
when state_9 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_10 =>
if std_match(input, "0") then next_state <= state_1; output <= "010";
elsif std_match(input, "1") then next_state <= state_2; output <= "010";
end if;
when state_11 =>
if std_match(input, "0") then next_state <= state_3; output <= "010";
elsif std_match(input, "1") then next_state <= state_4; output <= "010";
end if;
when state_12 =>
if std_match(input, "0") then next_state <= state_4; output <= "100";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_13 =>
if std_match(input, "0") then next_state <= state_5; output <= "100";
elsif std_match(input, "1") then next_state <= state_6; output <= "100";
end if;
when state_14 =>
if std_match(input, "0") then next_state <= state_3; output <= "100";
elsif std_match(input, "1") then next_state <= state_7; output <= "100";
end if;
when state_15 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when others => next_state <= "---------------"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/sse_jed.vhd | 1 | 6957 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_jed;
architecture behaviour of sse_jed is
constant st11: std_logic_vector(3 downto 0) := "0010";
constant st10: std_logic_vector(3 downto 0) := "0011";
constant st4: std_logic_vector(3 downto 0) := "1011";
constant st12: std_logic_vector(3 downto 0) := "1001";
constant st7: std_logic_vector(3 downto 0) := "0001";
constant st6: std_logic_vector(3 downto 0) := "0000";
constant st1: std_logic_vector(3 downto 0) := "1000";
constant st0: std_logic_vector(3 downto 0) := "1111";
constant st8: std_logic_vector(3 downto 0) := "1110";
constant st9: std_logic_vector(3 downto 0) := "1101";
constant st3: std_logic_vector(3 downto 0) := "0101";
constant st2: std_logic_vector(3 downto 0) := "0111";
constant st5: std_logic_vector(3 downto 0) := "1010";
constant st13: std_logic_vector(3 downto 0) := "1100";
constant st14: std_logic_vector(3 downto 0) := "0100";
constant st15: std_logic_vector(3 downto 0) := "0110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/dk27_nov.vhd | 1 | 2406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_nov;
architecture behaviour of dk27_nov is
constant START: std_logic_vector(2 downto 0) := "110";
constant state2: std_logic_vector(2 downto 0) := "010";
constant state3: std_logic_vector(2 downto 0) := "001";
constant state4: std_logic_vector(2 downto 0) := "111";
constant state5: std_logic_vector(2 downto 0) := "000";
constant state6: std_logic_vector(2 downto 0) := "100";
constant state7: std_logic_vector(2 downto 0) := "011";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/s27_jed.vhd | 1 | 3869 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_jed;
architecture behaviour of s27_jed is
constant s000: std_logic_vector(2 downto 0) := "110";
constant s001: std_logic_vector(2 downto 0) := "100";
constant s101: std_logic_vector(2 downto 0) := "000";
constant s100: std_logic_vector(2 downto 0) := "010";
constant s010: std_logic_vector(2 downto 0) := "011";
constant s011: std_logic_vector(2 downto 0) := "001";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s000 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
elsif std_match(input, "00-0") then next_state <= s000; output <= "1";
elsif std_match(input, "-0-1") then next_state <= s010; output <= "0";
end if;
when s001 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s101 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s100 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "00--") then next_state <= s000; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "10--") then next_state <= s100; output <= "1";
end if;
when s010 =>
if std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "000-") then next_state <= s010; output <= "0";
elsif std_match(input, "010-") then next_state <= s011; output <= "0";
elsif std_match(input, "1101") then next_state <= s101; output <= "1";
elsif std_match(input, "1111") then next_state <= s100; output <= "1";
elsif std_match(input, "10-1") then next_state <= s010; output <= "0";
elsif std_match(input, "1100") then next_state <= s101; output <= "1";
elsif std_match(input, "1110") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
end if;
when s011 =>
if std_match(input, "0-0-") then next_state <= s011; output <= "0";
elsif std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/lion_jed.vhd | 1 | 1832 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion_jed;
architecture behaviour of lion_jed is
constant st0: std_logic_vector(1 downto 0) := "10";
constant st1: std_logic_vector(1 downto 0) := "00";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "-0") then next_state <= st0; output <= "0";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "0-") then next_state <= st1; output <= "1";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "1-") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "0-") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/shiftreg_nov.vhd | 1 | 2558 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_nov;
architecture behaviour of shiftreg_nov is
constant st0: std_logic_vector(2 downto 0) := "000";
constant st1: std_logic_vector(2 downto 0) := "100";
constant st2: std_logic_vector(2 downto 0) := "011";
constant st3: std_logic_vector(2 downto 0) := "111";
constant st4: std_logic_vector(2 downto 0) := "010";
constant st5: std_logic_vector(2 downto 0) := "110";
constant st6: std_logic_vector(2 downto 0) := "001";
constant st7: std_logic_vector(2 downto 0) := "101";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st0; output <= "1";
elsif std_match(input, "1") then next_state <= st4; output <= "1";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st1; output <= "1";
elsif std_match(input, "1") then next_state <= st5; output <= "1";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st2; output <= "1";
elsif std_match(input, "1") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st3; output <= "1";
elsif std_match(input, "1") then next_state <= st7; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/dk14_jed.vhd | 1 | 6084 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk14_jed is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk14_jed;
architecture behaviour of dk14_jed is
constant state_1: std_logic_vector(2 downto 0) := "010";
constant state_3: std_logic_vector(2 downto 0) := "100";
constant state_2: std_logic_vector(2 downto 0) := "000";
constant state_4: std_logic_vector(2 downto 0) := "001";
constant state_5: std_logic_vector(2 downto 0) := "110";
constant state_6: std_logic_vector(2 downto 0) := "101";
constant state_7: std_logic_vector(2 downto 0) := "111";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-----";
case current_state is
when state_1 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_2 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_1; output <= "00001";
elsif std_match(input, "010") then next_state <= state_2; output <= "00001";
end if;
when state_3 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_4 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "10100";
elsif std_match(input, "010") then next_state <= state_7; output <= "10000";
end if;
when state_5 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_6 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10100";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_7 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when others => next_state <= "---"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/train4_jed.vhd | 1 | 2066 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_jed;
architecture behaviour of train4_jed is
constant st0: std_logic_vector(1 downto 0) := "11";
constant st1: std_logic_vector(1 downto 0) := "10";
constant st2: std_logic_vector(1 downto 0) := "00";
constant st3: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "10") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "10") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/bbara_rnd.vhd | 1 | 6275 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbara_rnd;
architecture behaviour of bbara_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st4: std_logic_vector(3 downto 0) := "1011";
constant st2: std_logic_vector(3 downto 0) := "1110";
constant st3: std_logic_vector(3 downto 0) := "1111";
constant st7: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "0110";
constant st6: std_logic_vector(3 downto 0) := "0000";
constant st8: std_logic_vector(3 downto 0) := "1010";
constant st9: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "--01") then next_state <= st0; output <= "00";
elsif std_match(input, "--10") then next_state <= st0; output <= "00";
elsif std_match(input, "--00") then next_state <= st0; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st1 =>
if std_match(input, "--01") then next_state <= st1; output <= "00";
elsif std_match(input, "--10") then next_state <= st1; output <= "00";
elsif std_match(input, "--00") then next_state <= st1; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st2; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st2 =>
if std_match(input, "--01") then next_state <= st2; output <= "00";
elsif std_match(input, "--10") then next_state <= st2; output <= "00";
elsif std_match(input, "--00") then next_state <= st2; output <= "00";
elsif std_match(input, "0011") then next_state <= st1; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st3 =>
if std_match(input, "--01") then next_state <= st3; output <= "10";
elsif std_match(input, "--10") then next_state <= st3; output <= "10";
elsif std_match(input, "--00") then next_state <= st3; output <= "10";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "10";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st4 =>
if std_match(input, "--01") then next_state <= st4; output <= "00";
elsif std_match(input, "--10") then next_state <= st4; output <= "00";
elsif std_match(input, "--00") then next_state <= st4; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st5; output <= "00";
end if;
when st5 =>
if std_match(input, "--01") then next_state <= st5; output <= "00";
elsif std_match(input, "--10") then next_state <= st5; output <= "00";
elsif std_match(input, "--00") then next_state <= st5; output <= "00";
elsif std_match(input, "0011") then next_state <= st4; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "00";
end if;
when st6 =>
if std_match(input, "--01") then next_state <= st6; output <= "01";
elsif std_match(input, "--10") then next_state <= st6; output <= "01";
elsif std_match(input, "--00") then next_state <= st6; output <= "01";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "01";
end if;
when st7 =>
if std_match(input, "--01") then next_state <= st7; output <= "00";
elsif std_match(input, "--10") then next_state <= st7; output <= "00";
elsif std_match(input, "--00") then next_state <= st7; output <= "00";
elsif std_match(input, "0011") then next_state <= st8; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st8 =>
if std_match(input, "--01") then next_state <= st8; output <= "00";
elsif std_match(input, "--10") then next_state <= st8; output <= "00";
elsif std_match(input, "--00") then next_state <= st8; output <= "00";
elsif std_match(input, "0011") then next_state <= st9; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st9 =>
if std_match(input, "--01") then next_state <= st9; output <= "00";
elsif std_match(input, "--10") then next_state <= st9; output <= "00";
elsif std_match(input, "--00") then next_state <= st9; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/s1_nov.vhd | 1 | 11803 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_nov;
architecture behaviour of s1_nov is
constant st0: std_logic_vector(4 downto 0) := "10110";
constant st1: std_logic_vector(4 downto 0) := "11010";
constant st2: std_logic_vector(4 downto 0) := "10101";
constant st3: std_logic_vector(4 downto 0) := "01010";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st5: std_logic_vector(4 downto 0) := "00110";
constant st6: std_logic_vector(4 downto 0) := "00011";
constant st7: std_logic_vector(4 downto 0) := "01110";
constant st8: std_logic_vector(4 downto 0) := "00000";
constant st9: std_logic_vector(4 downto 0) := "11111";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st11: std_logic_vector(4 downto 0) := "01001";
constant st12: std_logic_vector(4 downto 0) := "00001";
constant st13: std_logic_vector(4 downto 0) := "10001";
constant st14: std_logic_vector(4 downto 0) := "10010";
constant st15: std_logic_vector(4 downto 0) := "11100";
constant st16: std_logic_vector(4 downto 0) := "11110";
constant st17: std_logic_vector(4 downto 0) := "01101";
constant st18: std_logic_vector(4 downto 0) := "00010";
constant st19: std_logic_vector(4 downto 0) := "11101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000001";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000011";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "001001";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "011001";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "001011";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "010001";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "001101";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "001001";
elsif std_match(input, "----1---") then next_state <= st3; output <= "001011";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "011001";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "001101";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "101001";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "101001";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "001101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "001101";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "010001";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "001010";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "011000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000010";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000010";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "010000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "010000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "010000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "001000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "001000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "001001";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "001010";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "001011";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "011001";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "------1-") then next_state <= st7; output <= "001101";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "101000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "001100";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "101000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "001101";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "101000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000100";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "101000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/ex3_rnd.vhd | 1 | 4215 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex3_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex3_rnd;
architecture behaviour of ex3_rnd is
constant s1: std_logic_vector(3 downto 0) := "1101";
constant s2: std_logic_vector(3 downto 0) := "0010";
constant s4: std_logic_vector(3 downto 0) := "1011";
constant s3: std_logic_vector(3 downto 0) := "1110";
constant s0: std_logic_vector(3 downto 0) := "1111";
constant s7: std_logic_vector(3 downto 0) := "0001";
constant s8: std_logic_vector(3 downto 0) := "0110";
constant s6: std_logic_vector(3 downto 0) := "0000";
constant s5: std_logic_vector(3 downto 0) := "1010";
constant s9: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "01";
elsif std_match(input, "10") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "10";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "--";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/styr_rnd.vhd | 1 | 18712 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity styr_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(9 downto 0)
);
end styr_rnd;
architecture behaviour of styr_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st12: std_logic_vector(4 downto 0) := "00010";
constant st10: std_logic_vector(4 downto 0) := "11011";
constant st1: std_logic_vector(4 downto 0) := "11110";
constant st2: std_logic_vector(4 downto 0) := "11111";
constant st8: std_logic_vector(4 downto 0) := "10001";
constant st3: std_logic_vector(4 downto 0) := "10110";
constant st7: std_logic_vector(4 downto 0) := "01011";
constant st4: std_logic_vector(4 downto 0) := "01111";
constant st5: std_logic_vector(4 downto 0) := "00001";
constant st6: std_logic_vector(4 downto 0) := "10000";
constant st29: std_logic_vector(4 downto 0) := "11010";
constant st9: std_logic_vector(4 downto 0) := "11000";
constant st28: std_logic_vector(4 downto 0) := "01000";
constant st11: std_logic_vector(4 downto 0) := "00100";
constant st13: std_logic_vector(4 downto 0) := "01001";
constant st14: std_logic_vector(4 downto 0) := "00110";
constant st15: std_logic_vector(4 downto 0) := "11100";
constant st16: std_logic_vector(4 downto 0) := "00011";
constant st22: std_logic_vector(4 downto 0) := "10111";
constant st19: std_logic_vector(4 downto 0) := "10011";
constant st17: std_logic_vector(4 downto 0) := "10010";
constant st18: std_logic_vector(4 downto 0) := "00111";
constant st20: std_logic_vector(4 downto 0) := "01100";
constant st21: std_logic_vector(4 downto 0) := "10101";
constant st25: std_logic_vector(4 downto 0) := "10100";
constant st23: std_logic_vector(4 downto 0) := "00000";
constant st24: std_logic_vector(4 downto 0) := "01101";
constant st26: std_logic_vector(4 downto 0) := "00101";
constant st27: std_logic_vector(4 downto 0) := "11001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "----------";
case current_state is
when st0 =>
if std_match(input, "1-0000---") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-10-----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-1-0----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0010---") then next_state <= st10; output <= "1000----10";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "1010100110";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st1 =>
if std_match(input, "------0--") then next_state <= st2; output <= "0110010000";
elsif std_match(input, "------1--") then next_state <= st8; output <= "0110100100";
end if;
when st2 =>
if std_match(input, "1-00000--") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0011---") then next_state <= st2; output <= "010100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st7; output <= "010000--00";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st3 =>
if std_match(input, "1-0000---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st3; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st5; output <= "0110001100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st4 =>
if std_match(input, "---------") then next_state <= st6; output <= "0110010000";
end if;
when st5 =>
if std_match(input, "---------") then next_state <= st1; output <= "0110010100";
end if;
when st6 =>
if std_match(input, "1-00000--") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st6; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st7 =>
if std_match(input, "1-0000---") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st7; output <= "110100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0010------";
elsif std_match(input, "1-010----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st29 =>
if std_match(input, "1-0000---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st29; output <= "110100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st8 =>
if std_match(input, "---------") then next_state <= st9; output <= "0110010000";
end if;
when st9 =>
if std_match(input, "1-00000--") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-001----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-00001--") then next_state <= st28; output <= "010010--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st28 =>
if std_match(input, "1-0000---") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-001----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st10 =>
if std_match(input, "1--0---00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1---0--00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1--0---10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0----1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0---1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st11 =>
if std_match(input, "1--011-0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0--0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--010-0-") then next_state <= st10; output <= "0100----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0---1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st12 =>
if std_match(input, "1--011---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--10----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--000---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0001---") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1--010---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st13 =>
if std_match(input, "1--000---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--01----") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--001---") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st14 =>
if std_match(input, "1--000---") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--01----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--001---") then next_state <= st15; output <= "0010100100";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st15 =>
if std_match(input, "--1------") then next_state <= st16; output <= "0010010000";
elsif std_match(input, "--0------") then next_state <= st22; output <= "0010010000";
end if;
when st16 =>
if std_match(input, "1--000---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--011---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st17 =>
if std_match(input, "1--000---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st18; output <= "0010001100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st18 =>
if std_match(input, "---------") then next_state <= st19; output <= "0010010100";
end if;
when st19 =>
if std_match(input, "---------") then next_state <= st16; output <= "0010010000";
end if;
when st20 =>
if std_match(input, "---------") then next_state <= st21; output <= "0010010000";
end if;
when st21 =>
if std_match(input, "1--000---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st22 =>
if std_match(input, "1-0000---") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st23 =>
if std_match(input, "1-0000---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st24; output <= "0010001100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st24 =>
if std_match(input, "---------") then next_state <= st25; output <= "0010010100";
end if;
when st25 =>
if std_match(input, "---------") then next_state <= st22; output <= "0010010000";
end if;
when st26 =>
if std_match(input, "---------") then next_state <= st27; output <= "0010010000";
end if;
when st27 =>
if std_match(input, "1-0000---") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when others => next_state <= "-----"; output <= "----------";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/s510_jed.vhd | 1 | 13167 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_jed is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_jed;
architecture behaviour of s510_jed is
constant s000000: std_logic_vector(5 downto 0) := "011011";
constant s010010: std_logic_vector(5 downto 0) := "111010";
constant s010011: std_logic_vector(5 downto 0) := "110010";
constant s000100: std_logic_vector(5 downto 0) := "110011";
constant s000001: std_logic_vector(5 downto 0) := "111011";
constant s100101: std_logic_vector(5 downto 0) := "111100";
constant s100100: std_logic_vector(5 downto 0) := "111110";
constant s000010: std_logic_vector(5 downto 0) := "111101";
constant s000011: std_logic_vector(5 downto 0) := "111111";
constant s011100: std_logic_vector(5 downto 0) := "101000";
constant s011101: std_logic_vector(5 downto 0) := "100000";
constant s000111: std_logic_vector(5 downto 0) := "110110";
constant s000101: std_logic_vector(5 downto 0) := "110111";
constant s010000: std_logic_vector(5 downto 0) := "101110";
constant s010001: std_logic_vector(5 downto 0) := "101010";
constant s001000: std_logic_vector(5 downto 0) := "010110";
constant s001001: std_logic_vector(5 downto 0) := "000110";
constant s010100: std_logic_vector(5 downto 0) := "000010";
constant s010101: std_logic_vector(5 downto 0) := "000000";
constant s001010: std_logic_vector(5 downto 0) := "100110";
constant s001011: std_logic_vector(5 downto 0) := "100010";
constant s011000: std_logic_vector(5 downto 0) := "100011";
constant s011001: std_logic_vector(5 downto 0) := "100001";
constant s011010: std_logic_vector(5 downto 0) := "010000";
constant s011011: std_logic_vector(5 downto 0) := "010001";
constant s001100: std_logic_vector(5 downto 0) := "010101";
constant s001101: std_logic_vector(5 downto 0) := "010100";
constant s011110: std_logic_vector(5 downto 0) := "101100";
constant s011111: std_logic_vector(5 downto 0) := "100100";
constant s100000: std_logic_vector(5 downto 0) := "001010";
constant s100001: std_logic_vector(5 downto 0) := "001000";
constant s100010: std_logic_vector(5 downto 0) := "101101";
constant s100011: std_logic_vector(5 downto 0) := "101111";
constant s001110: std_logic_vector(5 downto 0) := "011100";
constant s001111: std_logic_vector(5 downto 0) := "011101";
constant s100110: std_logic_vector(5 downto 0) := "010111";
constant s100111: std_logic_vector(5 downto 0) := "000111";
constant s101000: std_logic_vector(5 downto 0) := "000011";
constant s101001: std_logic_vector(5 downto 0) := "001011";
constant s101010: std_logic_vector(5 downto 0) := "100101";
constant s101011: std_logic_vector(5 downto 0) := "100111";
constant s101100: std_logic_vector(5 downto 0) := "001100";
constant s101101: std_logic_vector(5 downto 0) := "001101";
constant s101110: std_logic_vector(5 downto 0) := "101001";
constant s010110: std_logic_vector(5 downto 0) := "000100";
constant s010111: std_logic_vector(5 downto 0) := "000101";
constant s000110: std_logic_vector(5 downto 0) := "011010";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "-------------------") then next_state <= s010010; output <= "0011100";
end if;
when s010010 =>
if std_match(input, "--1----------------") then next_state <= s010011; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010010; output <= "0000100";
end if;
when s010011 =>
if std_match(input, "-------------------") then next_state <= s000100; output <= "0001101";
end if;
when s000100 =>
if std_match(input, "---11--------------") then next_state <= s000001; output <= "0000101";
elsif std_match(input, "---10--------------") then next_state <= s000000; output <= "0000101";
elsif std_match(input, "---0---------------") then next_state <= s000100; output <= "0000101";
end if;
when s000001 =>
if std_match(input, "-------------------") then next_state <= s100101; output <= "0011000";
end if;
when s100101 =>
if std_match(input, "-----1-------------") then next_state <= s100100; output <= "0000000";
elsif std_match(input, "-----0-------------") then next_state <= s100101; output <= "0000000";
end if;
when s100100 =>
if std_match(input, "-------------------") then next_state <= s000010; output <= "0001001";
end if;
when s000010 =>
if std_match(input, "------0------------") then next_state <= s000010; output <= "0000001";
elsif std_match(input, "------10-----------") then next_state <= s000001; output <= "0000001";
elsif std_match(input, "------11-----------") then next_state <= s000011; output <= "0000001";
end if;
when s000011 =>
if std_match(input, "-------------------") then next_state <= s011100; output <= "0011100";
end if;
when s011100 =>
if std_match(input, "--1----------------") then next_state <= s011101; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s011100; output <= "0000100";
end if;
when s011101 =>
if std_match(input, "-------------------") then next_state <= s000111; output <= "0001101";
end if;
when s000111 =>
if std_match(input, "---0---------------") then next_state <= s000111; output <= "0000101";
elsif std_match(input, "---1----0----------") then next_state <= s000011; output <= "0000101";
elsif std_match(input, "---1----1----------") then next_state <= s000101; output <= "0000101";
end if;
when s000101 =>
if std_match(input, "-------------------") then next_state <= s010000; output <= "0001100";
end if;
when s010000 =>
if std_match(input, "--1----------------") then next_state <= s010001; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010000; output <= "0000100";
end if;
when s010001 =>
if std_match(input, "-------------------") then next_state <= s001000; output <= "0001101";
end if;
when s001000 =>
if std_match(input, "---------0---------") then next_state <= s001000; output <= "0000101";
elsif std_match(input, "---------1---------") then next_state <= s001001; output <= "0000101";
end if;
when s001001 =>
if std_match(input, "-------------------") then next_state <= s010100; output <= "0011100";
end if;
when s010100 =>
if std_match(input, "----------0--------") then next_state <= s010100; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s010101; output <= "0000100";
end if;
when s010101 =>
if std_match(input, "-------------------") then next_state <= s001010; output <= "0001101";
end if;
when s001010 =>
if std_match(input, "-----------00------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------10------") then next_state <= s001001; output <= "0000101";
elsif std_match(input, "-----------01------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------11------") then next_state <= s001011; output <= "0000101";
end if;
when s001011 =>
if std_match(input, "-------------------") then next_state <= s011000; output <= "0101100";
end if;
when s011000 =>
if std_match(input, "----------0--------") then next_state <= s011000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s011001; output <= "0000100";
end if;
when s011001 =>
if std_match(input, "-------------------") then next_state <= s011010; output <= "0001101";
end if;
when s011010 =>
if std_match(input, "-------------0-----") then next_state <= s011010; output <= "0000101";
elsif std_match(input, "-------------1-----") then next_state <= s011011; output <= "0000101";
end if;
when s011011 =>
if std_match(input, "-------------------") then next_state <= s001100; output <= "0001111";
end if;
when s001100 =>
if std_match(input, "--------------0----") then next_state <= s001100; output <= "0000111";
elsif std_match(input, "--------------1----") then next_state <= s001101; output <= "0000111";
end if;
when s001101 =>
if std_match(input, "-------------------") then next_state <= s011110; output <= "0001101";
end if;
when s011110 =>
if std_match(input, "---------------1---") then next_state <= s011111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s011110; output <= "0000101";
end if;
when s011111 =>
if std_match(input, "-------------------") then next_state <= s100000; output <= "0011100";
end if;
when s100000 =>
if std_match(input, "----------1--------") then next_state <= s100001; output <= "0000100";
elsif std_match(input, "----------0--------") then next_state <= s100000; output <= "0000100";
end if;
when s100001 =>
if std_match(input, "-------------------") then next_state <= s100010; output <= "0001101";
end if;
when s100010 =>
if std_match(input, "------0------------") then next_state <= s100010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s100011; output <= "0000101";
end if;
when s100011 =>
if std_match(input, "-------------------") then next_state <= s001110; output <= "0001111";
end if;
when s001110 =>
if std_match(input, "----------------00-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------10-") then next_state <= s001101; output <= "0000111";
elsif std_match(input, "----------------01-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------11-") then next_state <= s001111; output <= "0000111";
end if;
when s001111 =>
if std_match(input, "-------------------") then next_state <= s100110; output <= "0001101";
end if;
when s100110 =>
if std_match(input, "---------------1---") then next_state <= s100111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s100110; output <= "0000101";
end if;
when s100111 =>
if std_match(input, "-------------------") then next_state <= s101000; output <= "0001100";
end if;
when s101000 =>
if std_match(input, "----------0--------") then next_state <= s101000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s101001; output <= "0000100";
end if;
when s101001 =>
if std_match(input, "-------------------") then next_state <= s101010; output <= "0001101";
end if;
when s101010 =>
if std_match(input, "------0------------") then next_state <= s101010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s101011; output <= "0000101";
end if;
when s101011 =>
if std_match(input, "-------------------") then next_state <= s101100; output <= "0001111";
end if;
when s101100 =>
if std_match(input, "------------------1") then next_state <= s101101; output <= "0000111";
elsif std_match(input, "------------------0") then next_state <= s101100; output <= "0000111";
end if;
when s101101 =>
if std_match(input, "-------------------") then next_state <= s101110; output <= "1000111";
end if;
when s101110 =>
if std_match(input, "-------------------") then next_state <= s010110; output <= "1000111";
end if;
when s010110 =>
if std_match(input, "1------------------") then next_state <= s010111; output <= "0000000";
elsif std_match(input, "0------------------") then next_state <= s010110; output <= "0000000";
end if;
when s010111 =>
if std_match(input, "-------------------") then next_state <= s000110; output <= "0101100";
end if;
when s000110 =>
if std_match(input, "-1-----------------") then next_state <= s000000; output <= "0000100";
elsif std_match(input, "-0-----------------") then next_state <= s000110; output <= "0000100";
end if;
when others => next_state <= "------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/tbk_nov.vhd | 1 | 133046 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tbk_nov is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(2 downto 0)
);
end tbk_nov;
architecture behaviour of tbk_nov is
constant st0: std_logic_vector(4 downto 0) := "00000";
constant st16: std_logic_vector(4 downto 0) := "01000";
constant st1: std_logic_vector(4 downto 0) := "10101";
constant st17: std_logic_vector(4 downto 0) := "01110";
constant st2: std_logic_vector(4 downto 0) := "11011";
constant st18: std_logic_vector(4 downto 0) := "01111";
constant st3: std_logic_vector(4 downto 0) := "11000";
constant st19: std_logic_vector(4 downto 0) := "01011";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st20: std_logic_vector(4 downto 0) := "01100";
constant st5: std_logic_vector(4 downto 0) := "10111";
constant st21: std_logic_vector(4 downto 0) := "01101";
constant st6: std_logic_vector(4 downto 0) := "11110";
constant st22: std_logic_vector(4 downto 0) := "01001";
constant st7: std_logic_vector(4 downto 0) := "11111";
constant st23: std_logic_vector(4 downto 0) := "00110";
constant st8: std_logic_vector(4 downto 0) := "11100";
constant st24: std_logic_vector(4 downto 0) := "00111";
constant st9: std_logic_vector(4 downto 0) := "10100";
constant st25: std_logic_vector(4 downto 0) := "00011";
constant st10: std_logic_vector(4 downto 0) := "11101";
constant st26: std_logic_vector(4 downto 0) := "00101";
constant st11: std_logic_vector(4 downto 0) := "10010";
constant st27: std_logic_vector(4 downto 0) := "00100";
constant st12: std_logic_vector(4 downto 0) := "10011";
constant st28: std_logic_vector(4 downto 0) := "00001";
constant st13: std_logic_vector(4 downto 0) := "11010";
constant st29: std_logic_vector(4 downto 0) := "10110";
constant st15: std_logic_vector(4 downto 0) := "10000";
constant st31: std_logic_vector(4 downto 0) := "01010";
constant st14: std_logic_vector(4 downto 0) := "10001";
constant st30: std_logic_vector(4 downto 0) := "00010";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when st0 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st16 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st1 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st1; output <= "000";
elsif std_match(input, "000010") then next_state <= st1; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "010";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st17 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st17; output <= "000";
elsif std_match(input, "000010") then next_state <= st17; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "010";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st2 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st2; output <= "000";
elsif std_match(input, "000010") then next_state <= st2; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "010";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st18 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st18; output <= "000";
elsif std_match(input, "000010") then next_state <= st18; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "010";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st3 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st3; output <= "000";
elsif std_match(input, "000010") then next_state <= st3; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "010";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st19 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st19; output <= "000";
elsif std_match(input, "000010") then next_state <= st19; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "010";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st4 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st4; output <= "000";
elsif std_match(input, "000010") then next_state <= st4; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "010";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st20 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st20; output <= "000";
elsif std_match(input, "000010") then next_state <= st20; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "010";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st5 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st5; output <= "000";
elsif std_match(input, "000010") then next_state <= st5; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "010";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st21 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st21; output <= "000";
elsif std_match(input, "000010") then next_state <= st21; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "010";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st6 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st6; output <= "000";
elsif std_match(input, "000010") then next_state <= st6; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "010";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st22 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st22; output <= "000";
elsif std_match(input, "000010") then next_state <= st22; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "010";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st7 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st7; output <= "000";
elsif std_match(input, "000010") then next_state <= st7; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "010";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st23 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st23; output <= "000";
elsif std_match(input, "000010") then next_state <= st23; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "010";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st8 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st8; output <= "000";
elsif std_match(input, "000010") then next_state <= st8; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "010";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st24 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st24; output <= "000";
elsif std_match(input, "000010") then next_state <= st24; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "010";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st9 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st9; output <= "000";
elsif std_match(input, "000000") then next_state <= st9; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "010";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st25 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st25; output <= "000";
elsif std_match(input, "000000") then next_state <= st25; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "010";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st10 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st10; output <= "000";
elsif std_match(input, "000000") then next_state <= st10; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "010";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st26 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st26; output <= "000";
elsif std_match(input, "000000") then next_state <= st26; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "010";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st11 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st11; output <= "000";
elsif std_match(input, "000000") then next_state <= st11; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "010";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st27 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st27; output <= "000";
elsif std_match(input, "000000") then next_state <= st27; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "010";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st12 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st12; output <= "000";
elsif std_match(input, "000000") then next_state <= st12; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st28 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st28; output <= "000";
elsif std_match(input, "000000") then next_state <= st28; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st13 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st13; output <= "100";
elsif std_match(input, "000010") then next_state <= st13; output <= "100";
elsif std_match(input, "000000") then next_state <= st13; output <= "100";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st29 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st29; output <= "100";
elsif std_match(input, "000010") then next_state <= st29; output <= "100";
elsif std_match(input, "000000") then next_state <= st29; output <= "100";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st15 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st15; output <= "000";
elsif std_match(input, "000010") then next_state <= st15; output <= "000";
elsif std_match(input, "000000") then next_state <= st15; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st31 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st31; output <= "000";
elsif std_match(input, "000010") then next_state <= st31; output <= "000";
elsif std_match(input, "000000") then next_state <= st31; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st14 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st14; output <= "000";
elsif std_match(input, "000010") then next_state <= st14; output <= "000";
elsif std_match(input, "000000") then next_state <= st14; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st30 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st30; output <= "000";
elsif std_match(input, "000010") then next_state <= st30; output <= "000";
elsif std_match(input, "000000") then next_state <= st30; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/keyb_nov.vhd | 1 | 16319 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_nov;
architecture behaviour of keyb_nov is
constant st0: std_logic_vector(4 downto 0) := "00000";
constant st1: std_logic_vector(4 downto 0) := "00100";
constant st2: std_logic_vector(4 downto 0) := "01100";
constant st3: std_logic_vector(4 downto 0) := "00001";
constant st4: std_logic_vector(4 downto 0) := "00101";
constant st5: std_logic_vector(4 downto 0) := "01101";
constant st6: std_logic_vector(4 downto 0) := "00111";
constant st7: std_logic_vector(4 downto 0) := "00110";
constant st8: std_logic_vector(4 downto 0) := "01110";
constant st9: std_logic_vector(4 downto 0) := "00011";
constant st10: std_logic_vector(4 downto 0) := "00010";
constant st11: std_logic_vector(4 downto 0) := "01000";
constant st12: std_logic_vector(4 downto 0) := "01001";
constant st13: std_logic_vector(4 downto 0) := "01111";
constant st14: std_logic_vector(4 downto 0) := "01010";
constant st15: std_logic_vector(4 downto 0) := "10101";
constant st16: std_logic_vector(4 downto 0) := "01011";
constant st17: std_logic_vector(4 downto 0) := "11010";
constant st18: std_logic_vector(4 downto 0) := "10100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "---0000") then next_state <= st1; output <= "1-";
elsif std_match(input, "---0100") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0010") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0001") then next_state <= st2; output <= "1-";
elsif std_match(input, "---1100") then next_state <= st3; output <= "1-";
elsif std_match(input, "---1000") then next_state <= st3; output <= "1-";
elsif std_match(input, "---011-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---01-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---101-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---10-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---111-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st1 =>
if std_match(input, "0000000") then next_state <= st4; output <= "1-";
elsif std_match(input, "1000000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0100000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0010000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0001000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "11-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1--1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "1---1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "1----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st2 =>
if std_match(input, "0000000") then next_state <= st5; output <= "--";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st3 =>
if std_match(input, "0000000") then next_state <= st6; output <= "1-";
elsif std_match(input, "0011000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st4 =>
if std_match(input, "-000000") then next_state <= st7; output <= "1-";
elsif std_match(input, "-100000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-010000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-001000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st5 =>
if std_match(input, "-000000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st6 =>
if std_match(input, "-011000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000000") then next_state <= st9; output <= "1-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st7 =>
if std_match(input, "--00000") then next_state <= st10; output <= "1-";
elsif std_match(input, "--10000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st8 =>
if std_match(input, "--00000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st9 =>
if std_match(input, "--00000") then next_state <= st12; output <= "--";
elsif std_match(input, "--11000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st10 =>
if std_match(input, "----000") then next_state <= st13; output <= "1-";
elsif std_match(input, "----100") then next_state <= st14; output <= "0-";
elsif std_match(input, "----010") then next_state <= st14; output <= "0-";
elsif std_match(input, "----001") then next_state <= st14; output <= "0-";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st11 =>
if std_match(input, "----000") then next_state <= st14; output <= "0-";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st12 =>
if std_match(input, "-----00") then next_state <= st14; output <= "--";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st13 =>
if std_match(input, "-----00") then next_state <= st15; output <= "1-";
elsif std_match(input, "-----10") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----01") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st14 =>
if std_match(input, "-----00") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st15 =>
if std_match(input, "------0") then next_state <= st17; output <= "--";
elsif std_match(input, "------1") then next_state <= st18; output <= "0-";
end if;
when st16 =>
if std_match(input, "------0") then next_state <= st18; output <= "0-";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st17 =>
if std_match(input, "-------") then next_state <= st0; output <= "-0";
end if;
when st18 =>
if std_match(input, "-------") then next_state <= st0; output <= "-1";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/ex2_hot.vhd | 1 | 8089 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_hot;
architecture behaviour of ex2_hot is
constant s1: std_logic_vector(18 downto 0) := "1000000000000000000";
constant s2: std_logic_vector(18 downto 0) := "0100000000000000000";
constant s4: std_logic_vector(18 downto 0) := "0010000000000000000";
constant s0: std_logic_vector(18 downto 0) := "0001000000000000000";
constant s3: std_logic_vector(18 downto 0) := "0000100000000000000";
constant s6: std_logic_vector(18 downto 0) := "0000010000000000000";
constant s9: std_logic_vector(18 downto 0) := "0000001000000000000";
constant s7: std_logic_vector(18 downto 0) := "0000000100000000000";
constant s8: std_logic_vector(18 downto 0) := "0000000010000000000";
constant s5: std_logic_vector(18 downto 0) := "0000000001000000000";
constant s10: std_logic_vector(18 downto 0) := "0000000000100000000";
constant s11: std_logic_vector(18 downto 0) := "0000000000010000000";
constant s13: std_logic_vector(18 downto 0) := "0000000000001000000";
constant s12: std_logic_vector(18 downto 0) := "0000000000000100000";
constant s15: std_logic_vector(18 downto 0) := "0000000000000010000";
constant s18: std_logic_vector(18 downto 0) := "0000000000000001000";
constant s16: std_logic_vector(18 downto 0) := "0000000000000000100";
constant s17: std_logic_vector(18 downto 0) := "0000000000000000010";
constant s14: std_logic_vector(18 downto 0) := "0000000000000000001";
signal current_state, next_state: std_logic_vector(18 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------------"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s3; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s7; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "11";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s10 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s13; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s12; output <= "--";
end if;
when s11 =>
if std_match(input, "00") then next_state <= s15; output <= "--";
elsif std_match(input, "01") then next_state <= s18; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s12 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s16; output <= "--";
elsif std_match(input, "11") then next_state <= s17; output <= "--";
end if;
when s13 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s10; output <= "00";
elsif std_match(input, "10") then next_state <= s15; output <= "--";
elsif std_match(input, "11") then next_state <= s14; output <= "--";
end if;
when s14 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s15; output <= "--";
end if;
when s15 =>
if std_match(input, "00") then next_state <= s10; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s11; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s16 =>
if std_match(input, "00") then next_state <= s14; output <= "11";
elsif std_match(input, "01") then next_state <= s11; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s17 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s10; output <= "00";
end if;
when s18 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s12; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "-------------------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/ex7_hot.vhd | 1 | 4287 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_hot;
architecture behaviour of ex7_hot is
constant s1: std_logic_vector(9 downto 0) := "1000000000";
constant s7: std_logic_vector(9 downto 0) := "0100000000";
constant s0: std_logic_vector(9 downto 0) := "0010000000";
constant s2: std_logic_vector(9 downto 0) := "0001000000";
constant s5: std_logic_vector(9 downto 0) := "0000100000";
constant s3: std_logic_vector(9 downto 0) := "0000010000";
constant s8: std_logic_vector(9 downto 0) := "0000001000";
constant s4: std_logic_vector(9 downto 0) := "0000000100";
constant s6: std_logic_vector(9 downto 0) := "0000000010";
constant s9: std_logic_vector(9 downto 0) := "0000000001";
signal current_state, next_state: std_logic_vector(9 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s7; output <= "11";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "11";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s7; output <= "00";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "00";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s4; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s4; output <= "11";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s6; output <= "11";
elsif std_match(input, "01") then next_state <= s3; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/scf_nov.vhd | 1 | 39256 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_nov is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_nov;
architecture behaviour of scf_nov is
constant state1: std_logic_vector(6 downto 0) := "1000101";
constant state2: std_logic_vector(6 downto 0) := "1100001";
constant state3: std_logic_vector(6 downto 0) := "1111101";
constant state4: std_logic_vector(6 downto 0) := "1110101";
constant state5: std_logic_vector(6 downto 0) := "0010111";
constant state6: std_logic_vector(6 downto 0) := "1001101";
constant state7: std_logic_vector(6 downto 0) := "1101001";
constant state8: std_logic_vector(6 downto 0) := "1100111";
constant state9: std_logic_vector(6 downto 0) := "1100100";
constant state10: std_logic_vector(6 downto 0) := "1011101";
constant state11: std_logic_vector(6 downto 0) := "1000001";
constant state12: std_logic_vector(6 downto 0) := "1101111";
constant state13: std_logic_vector(6 downto 0) := "1110100";
constant state14: std_logic_vector(6 downto 0) := "0101101";
constant state15: std_logic_vector(6 downto 0) := "0101001";
constant state16: std_logic_vector(6 downto 0) := "1101101";
constant state17: std_logic_vector(6 downto 0) := "1010101";
constant state18: std_logic_vector(6 downto 0) := "1101110";
constant state19: std_logic_vector(6 downto 0) := "1110001";
constant state20: std_logic_vector(6 downto 0) := "0001110";
constant state21: std_logic_vector(6 downto 0) := "1100011";
constant state22: std_logic_vector(6 downto 0) := "0010000";
constant state23: std_logic_vector(6 downto 0) := "1101100";
constant state24: std_logic_vector(6 downto 0) := "0010011";
constant state25: std_logic_vector(6 downto 0) := "0001101";
constant state26: std_logic_vector(6 downto 0) := "1111110";
constant state27: std_logic_vector(6 downto 0) := "1100000";
constant state28: std_logic_vector(6 downto 0) := "0010101";
constant state29: std_logic_vector(6 downto 0) := "0010001";
constant state30: std_logic_vector(6 downto 0) := "0101111";
constant state31: std_logic_vector(6 downto 0) := "1001010";
constant state32: std_logic_vector(6 downto 0) := "1011110";
constant state33: std_logic_vector(6 downto 0) := "0001010";
constant state34: std_logic_vector(6 downto 0) := "0000001";
constant state35: std_logic_vector(6 downto 0) := "1011010";
constant state36: std_logic_vector(6 downto 0) := "1101010";
constant state37: std_logic_vector(6 downto 0) := "1111111";
constant state38: std_logic_vector(6 downto 0) := "0100000";
constant state39: std_logic_vector(6 downto 0) := "1011111";
constant state40: std_logic_vector(6 downto 0) := "0111010";
constant state41: std_logic_vector(6 downto 0) := "1000000";
constant state42: std_logic_vector(6 downto 0) := "0111110";
constant state43: std_logic_vector(6 downto 0) := "0101010";
constant state44: std_logic_vector(6 downto 0) := "0111111";
constant state45: std_logic_vector(6 downto 0) := "1110000";
constant state46: std_logic_vector(6 downto 0) := "0001111";
constant state47: std_logic_vector(6 downto 0) := "0011101";
constant state48: std_logic_vector(6 downto 0) := "0011001";
constant state49: std_logic_vector(6 downto 0) := "1101000";
constant state50: std_logic_vector(6 downto 0) := "0000110";
constant state51: std_logic_vector(6 downto 0) := "0011000";
constant state52: std_logic_vector(6 downto 0) := "0110001";
constant state53: std_logic_vector(6 downto 0) := "0011011";
constant state54: std_logic_vector(6 downto 0) := "1011100";
constant state55: std_logic_vector(6 downto 0) := "0100011";
constant state56: std_logic_vector(6 downto 0) := "1011011";
constant state57: std_logic_vector(6 downto 0) := "0100100";
constant state58: std_logic_vector(6 downto 0) := "1011000";
constant state59: std_logic_vector(6 downto 0) := "0100111";
constant state60: std_logic_vector(6 downto 0) := "1011001";
constant state61: std_logic_vector(6 downto 0) := "1100110";
constant state62: std_logic_vector(6 downto 0) := "0100101";
constant state63: std_logic_vector(6 downto 0) := "0001100";
constant state64: std_logic_vector(6 downto 0) := "1100101";
constant state65: std_logic_vector(6 downto 0) := "1110011";
constant state66: std_logic_vector(6 downto 0) := "0100010";
constant state67: std_logic_vector(6 downto 0) := "0001011";
constant state68: std_logic_vector(6 downto 0) := "0110100";
constant state69: std_logic_vector(6 downto 0) := "0000010";
constant state70: std_logic_vector(6 downto 0) := "1010110";
constant state71: std_logic_vector(6 downto 0) := "1000010";
constant state72: std_logic_vector(6 downto 0) := "1001001";
constant state73: std_logic_vector(6 downto 0) := "0010010";
constant state74: std_logic_vector(6 downto 0) := "0111100";
constant state75: std_logic_vector(6 downto 0) := "0110010";
constant state76: std_logic_vector(6 downto 0) := "1000011";
constant state77: std_logic_vector(6 downto 0) := "1010010";
constant state78: std_logic_vector(6 downto 0) := "0111101";
constant state79: std_logic_vector(6 downto 0) := "1110010";
constant state80: std_logic_vector(6 downto 0) := "1100010";
constant state81: std_logic_vector(6 downto 0) := "0011100";
constant state82: std_logic_vector(6 downto 0) := "0100110";
constant state83: std_logic_vector(6 downto 0) := "1010011";
constant state84: std_logic_vector(6 downto 0) := "0101000";
constant state85: std_logic_vector(6 downto 0) := "1010111";
constant state86: std_logic_vector(6 downto 0) := "1001000";
constant state87: std_logic_vector(6 downto 0) := "0011111";
constant state88: std_logic_vector(6 downto 0) := "0011010";
constant state89: std_logic_vector(6 downto 0) := "0111011";
constant state90: std_logic_vector(6 downto 0) := "1000100";
constant state91: std_logic_vector(6 downto 0) := "0111000";
constant state92: std_logic_vector(6 downto 0) := "1000111";
constant state93: std_logic_vector(6 downto 0) := "0111001";
constant state94: std_logic_vector(6 downto 0) := "0011110";
constant state95: std_logic_vector(6 downto 0) := "1000110";
constant state96: std_logic_vector(6 downto 0) := "0110110";
constant state97: std_logic_vector(6 downto 0) := "1111001";
constant state98: std_logic_vector(6 downto 0) := "0001000";
constant state99: std_logic_vector(6 downto 0) := "1110111";
constant state100: std_logic_vector(6 downto 0) := "0001001";
constant state101: std_logic_vector(6 downto 0) := "1110110";
constant state102: std_logic_vector(6 downto 0) := "0000111";
constant state103: std_logic_vector(6 downto 0) := "1111000";
constant state104: std_logic_vector(6 downto 0) := "0000100";
constant state105: std_logic_vector(6 downto 0) := "1101011";
constant state106: std_logic_vector(6 downto 0) := "0000101";
constant state107: std_logic_vector(6 downto 0) := "1111010";
constant state108: std_logic_vector(6 downto 0) := "0000011";
constant state109: std_logic_vector(6 downto 0) := "1111100";
constant state110: std_logic_vector(6 downto 0) := "0000000";
constant state111: std_logic_vector(6 downto 0) := "0010100";
constant state112: std_logic_vector(6 downto 0) := "1111011";
constant state113: std_logic_vector(6 downto 0) := "0010110";
constant state114: std_logic_vector(6 downto 0) := "0110111";
constant state115: std_logic_vector(6 downto 0) := "1001100";
constant state116: std_logic_vector(6 downto 0) := "0110101";
constant state117: std_logic_vector(6 downto 0) := "1001110";
constant state118: std_logic_vector(6 downto 0) := "0110011";
constant state119: std_logic_vector(6 downto 0) := "1010000";
constant state120: std_logic_vector(6 downto 0) := "0101110";
constant state121: std_logic_vector(6 downto 0) := "1001011";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "--------------------------------------------------------";
if std_match(input, "0--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
else
case current_state is
when state1 =>
if std_match(input, "1--------------------------") then next_state <= state3; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state2 =>
if std_match(input, "1--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state3 =>
if std_match(input, "1--------------------------") then next_state <= state4; output <= "00000010010000001-0000000-00-0001001000010-0-----00-0---";
end if;
when state4 =>
if std_match(input, "1--------------------------") then next_state <= state5; output <= "00000010000000000-0000000-00-0000000110101-0-----00-0---";
end if;
when state5 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state6 =>
if std_match(input, "1--------------------------") then next_state <= state2; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state7 =>
if std_match(input, "1-----0--------------------") then next_state <= state9; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----1--------------------") then next_state <= state8; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state8 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000010000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state9 =>
if std_match(input, "1----0---------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----1---------------------") then next_state <= state10; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state10 =>
if std_match(input, "1--------------------------") then next_state <= state11; output <= "00000010000000000-0000001-00-0000000000001-0-----00-0---";
end if;
when state11 =>
if std_match(input, "1--------------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000010000000-0-----00-0---";
end if;
when state12 =>
if std_match(input, "1---0----------------------") then next_state <= state15; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---1----------------------") then next_state <= state13; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state13 =>
if std_match(input, "1--------------------------") then next_state <= state29; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state14 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state15 =>
if std_match(input, "1--------------------------") then next_state <= state59; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state16 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state17 =>
if std_match(input, "1--------------------------") then next_state <= state18; output <= "0000000000010100001000000-10-000000000000011-----00-0---";
end if;
when state18 =>
if std_match(input, "1--------------------------") then next_state <= state19; output <= "00100000000000000-0000000-00-0000000000000-0000--00-0---";
end if;
when state19 =>
if std_match(input, "1--0-----------------------") then next_state <= state21; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state20; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state20 =>
if std_match(input, "1--------------------------") then next_state <= state21; output <= "00000001000000000-0000000-00-0000000100000-0-----00-0---";
end if;
when state21 =>
if std_match(input, "1--------------------------") then next_state <= state22; output <= "01000000000100000-0000000-10-100000000000000000001001---";
end if;
when state22 =>
if std_match(input, "1--------------------------") then next_state <= state23; output <= "00010000000000000-0000000-00-0000000000000-0000--01-0---";
end if;
when state23 =>
if std_match(input, "1--------------------------") then next_state <= state24; output <= "00000000100000000-0000000-00-0000000000000-0---0000-0---";
end if;
when state24 =>
if std_match(input, "1-0------------------------") then next_state <= state26; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-1------------------------") then next_state <= state25; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state25 =>
if std_match(input, "1--------------------------") then next_state <= state26; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state26 =>
if std_match(input, "10-------------------------") then next_state <= state28; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "11-------------------------") then next_state <= state27; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
end if;
when state27 =>
if std_match(input, "1--------------------------") then next_state <= state28; output <= "00000000000000000-0000000-00-0010000000000-0-----00-0---";
end if;
when state28 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state29 =>
if std_match(input, "1------1-------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state34; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state32; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state30; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state30 =>
if std_match(input, "1--------------------------") then next_state <= state38; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state31 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state32 =>
if std_match(input, "1--------------------------") then next_state <= state55; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state33 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state34 =>
if std_match(input, "1--------------------------") then next_state <= state57; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state35 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state36 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state37 =>
if std_match(input, "1--------------------------") then next_state <= state14; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state38 =>
if std_match(input, "1----------1---------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------01--------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------001-------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0001------------") then next_state <= state41; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0000------------") then next_state <= state39; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state39 =>
if std_match(input, "1--------------------------") then next_state <= state45; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state40 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state41 =>
if std_match(input, "1--------------------------") then next_state <= state50; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state42 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state43 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state44 =>
if std_match(input, "1--------------------------") then next_state <= state31; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state45 =>
if std_match(input, "1--------------0-----------") then next_state <= state48; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state46; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state46 =>
if std_match(input, "1--------------------------") then next_state <= state47; output <= "0000000001000101001000000-00-0000000000000-0-----00-0---";
end if;
when state47 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state48 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state49 =>
if std_match(input, "1--------------------------") then next_state <= state40; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state50 =>
if std_match(input, "1--------------0-----------") then next_state <= state52; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state51; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state51 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state52 =>
if std_match(input, "1--------------------------") then next_state <= state53; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state53 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state54 =>
if std_match(input, "1--------------------------") then next_state <= state42; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state55 =>
if std_match(input, "1--------------------------") then next_state <= state56; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state56 =>
if std_match(input, "1--------------------------") then next_state <= state33; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state57 =>
if std_match(input, "1--------------------------") then next_state <= state58; output <= "00000000001000001-0001000-00-0000000000000-0-----00-0---";
end if;
when state58 =>
if std_match(input, "1--------------------------") then next_state <= state35; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state59 =>
if std_match(input, "1---------------0----------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---------------1----------") then next_state <= state60; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state60 =>
if std_match(input, "1------1-------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state65; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state63; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state61; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state61 =>
if std_match(input, "1--------------------------") then next_state <= state82; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state62 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state63 =>
if std_match(input, "1--------------------------") then next_state <= state83; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state64 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state65 =>
if std_match(input, "1--------------------------") then next_state <= state89; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state66 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state67 =>
if std_match(input, "1------1-------------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------011-----------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0101----------------") then next_state <= state78; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0100----------------") then next_state <= state76; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state74; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state72; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state70; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state68; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state68 =>
if std_match(input, "1--------------------------") then next_state <= state96; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state69 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state70 =>
if std_match(input, "1--------------------------") then next_state <= state98; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state71 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state72 =>
if std_match(input, "1--------------------------") then next_state <= state103; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state73 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state74 =>
if std_match(input, "1--------------------------") then next_state <= state107; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state75 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state76 =>
if std_match(input, "1--------------------------") then next_state <= state115; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state77 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state78 =>
if std_match(input, "1--------------------------") then next_state <= state117; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state79 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state80 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state81 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state82 =>
if std_match(input, "1--------------------------") then next_state <= state62; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state83 =>
if std_match(input, "1--------------------------") then next_state <= state84; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state84 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00001000000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state85 =>
if std_match(input, "1--------------------------") then next_state <= state64; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state86 =>
if std_match(input, "1----------------0---------") then next_state <= state88; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------------1---------") then next_state <= state87; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state87 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000001000000000-0000000-00-0000100001000-0-----00-0---";
end if;
when state88 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state89 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00001001000000000-0000000-00-0001000001000-0-----00-0---";
end if;
when state90 =>
if std_match(input, "1--------------------------") then next_state <= state66; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state91 =>
if std_match(input, "1--------------------------") then next_state <= state92; output <= "00000010000000000-0000000-00-0000000000000-0010--00-0---";
end if;
when state92 =>
if std_match(input, "1--0-----------------------") then next_state <= state95; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state93; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state93 =>
if std_match(input, "1--------------------------") then next_state <= state94; output <= "00000000000100001-0000000-10-0000000000000-0-----00-0---";
end if;
when state94 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state95 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00000000000000000-0000000-00-0010100000000-0-----00-0---";
end if;
when state96 =>
if std_match(input, "1--------------------------") then next_state <= state97; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state97 =>
if std_match(input, "1--------------------------") then next_state <= state69; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state98 =>
if std_match(input, "1--------------0-----------") then next_state <= state101; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state99; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state99 =>
if std_match(input, "1--------------------------") then next_state <= state100; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state100 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state101 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state102 =>
if std_match(input, "1--------------------------") then next_state <= state71; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state103 =>
if std_match(input, "1--------------0-----------") then next_state <= state105; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state104; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state104 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state105 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state106 =>
if std_match(input, "1--------------------------") then next_state <= state73; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state107 =>
if std_match(input, "1--------------0-----------") then next_state <= state112; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state108; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state108 =>
if std_match(input, "1-----------------00000000-") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------1--------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------01-------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------001------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0001-----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00001----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------000001---") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0000001--") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00000001-") then next_state <= state109; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state109 =>
if std_match(input, "1--------------------------") then next_state <= state112; output <= "0000000000001100101000000-00-0000000000000-0-----00-0100";
end if;
when state110 =>
if std_match(input, "1--------------------------") then next_state <= state111; output <= "0000010000000101001010000-0000100000000000111000110-0100";
end if;
when state111 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000100001-0000000000001-0-----00-0---";
end if;
when state112 =>
if std_match(input, "1--------------------------") then next_state <= state113; output <= "00000100000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state113 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state114 =>
if std_match(input, "1--------------------------") then next_state <= state75; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state115 =>
if std_match(input, "1--------------------------") then next_state <= state116; output <= "00001000000010001-0010000-00-0000000000000-01011010-0101";
end if;
when state116 =>
if std_match(input, "1--------------------------") then next_state <= state77; output <= "10000001000000000-0000100-00-0001000001101-0-----00-0---";
end if;
when state117 =>
if std_match(input, "1--------------------------") then next_state <= state118; output <= "00000010000000000-0000000-00-0000000000000-0-----00-0011";
end if;
when state118 =>
if std_match(input, "1-------------------------0") then next_state <= state121; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-------------------------1") then next_state <= state119; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state119 =>
if std_match(input, "1--------------------------") then next_state <= state120; output <= "0000010000001000001000000-00-0000000000000111011010-0101";
end if;
when state120 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00010010000000010-000000000110100000000100-0-----00-0---";
end if;
when state121 =>
if std_match(input, "1--------------------------") then next_state <= state79; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when others => next_state <= "-------"; output <= "--------------------------------------------------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 |
chastell/art-decomp | kiss/dk27_rnd.vhd | 1 | 2406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_rnd;
architecture behaviour of dk27_rnd is
constant START: std_logic_vector(2 downto 0) := "101";
constant state6: std_logic_vector(2 downto 0) := "010";
constant state2: std_logic_vector(2 downto 0) := "011";
constant state5: std_logic_vector(2 downto 0) := "110";
constant state3: std_logic_vector(2 downto 0) := "111";
constant state4: std_logic_vector(2 downto 0) := "001";
constant state7: std_logic_vector(2 downto 0) := "000";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 |
JimLewis/OSVVM | TbUtilPkg.vhd | 1 | 37308 | --
-- File Name: TbUtilPkg.vhd
-- Design Unit Name: TbUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@SynthWorks.com
-- Contributor(s):
-- Jim Lewis email: jim@SynthWorks.com
--
-- Package Defines
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2021 2021.02 Added AckType, RdyType, RequestTransaction, WaitForTransaction for AckType/RdyType
-- 12/2020 2020.12 Added IfElse functions for string and integer.
-- Added Increment function for integer
-- 01/2020 2020.01 Updated Licenses to Apache
-- 08/2018 2018.08 Updated WaitForTransaction to allow 0 time transactions
-- 04/2018 2018.04 Added RequestTransaction, WaitForTransaction, Toggle, WaitForToggle for bit.
-- Added Increment and WaitForToggle for integer.
-- 11/2016 2016.11 First Public Release Version
-- Updated naming for consistency.
-- 10/2013 2013.10 Split out Text Utilities
-- 11/1999: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 1999 - 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
library osvvm ;
use osvvm.AlertLogPkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.ResolutionPkg.all ;
package TbUtilPkg is
constant CLK_ACTIVE : std_logic := '1' ;
constant t_sim_resolution : time := std.env.resolution_limit ; -- VHDL-2008
-- constant t_sim_resolution : time := 1 ns ; -- for non VHDL-2008 simulators
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean ;
------------------------------------------------------------
-- IfElse
-- Crutch until VHDL-2019 conditional initialization
-- If condition is true return first parameter otherwise return second
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : std_logic_vector) return std_logic_vector ;
function IfElse(Expr : boolean ; A, B : integer) return integer ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- RequestTransaction - Transaction initiation in transaction procedure
-- WaitForTransaction - Transaction execution control in VC
------------------------------------------------------------
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- std_logic
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- bit
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- integer
------------------------------------------------------------
subtype RdyType is resolved_max integer range 0 to integer'high ;
subtype AckType is resolved_max integer range -1 to integer'high ;
procedure RequestTransaction (
signal Rdy : InOut RdyType ;
signal Ack : In AckType
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) ;
------------------------------------------------------------
-- WaitForTransaction
-- Specializations for interrupt handling
-- Currently only std_logic based
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) ;
-- Variation for model that stops waiting when IntReq is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) ;
-- Set Ack to Model starting value
procedure StartTransaction ( signal Ack : Out std_logic ) ;
-- Set Ack to Model finishing value
procedure FinishTransaction ( signal Ack : Out std_logic ) ;
-- If a transaction is pending, return true
function TransactionPending ( signal Rdy : In std_logic ) return boolean ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) ;
procedure Toggle ( signal Sig : InOut std_logic ) ;
procedure ToggleHS ( signal Sig : InOut std_logic ) ;
function IsToggle ( signal Sig : In std_logic ) return boolean ;
procedure WaitForToggle ( signal Sig : In std_logic ) ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) ;
procedure Toggle ( signal Sig : InOut bit ) ;
procedure ToggleHS ( signal Sig : InOut bit ) ;
function IsToggle ( signal Sig : In bit ) return boolean ;
procedure WaitForToggle ( signal Sig : In bit ) ;
-- Integer type versions
procedure Increment ( signal Sig : InOut integer ; constant RollOverValue : in integer := 0) ;
function Increment (constant Sig : in integer ; constant Amount : in integer := 1) return integer ;
procedure WaitForToggle ( signal Sig : In integer ) ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) ;
-- resolved_barrier : summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer ;
subtype integer_barrier is resolved_barrier integer ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time
) ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
------------------------------------------------------------
-- Deprecated subprogram names
-- Maintaining backward compatibility using aliases
------------------------------------------------------------
-- History of RequestTransaction / WaitForTransaction
alias RequestAction is RequestTransaction [std_logic, std_logic] ;
alias WaitForRequest is WaitForTransaction [std_logic, std_logic, std_logic] ;
-- History of WaitForToggle
alias WaitOnToggle is WaitForToggle [std_logic] ;
-- History of WaitForBarrier
alias WayPointBlock is WaitForBarrier [std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic_vector] ;
-- Backward compatible name
alias SyncToClk is WaitForClock [std_logic, time] ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) ;
procedure StrobeAck ( signal Ack : Out std_logic ) ;
end TbUtilPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body TbUtilPkg is
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return found_one ; -- found a one
end function OneHot ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return TRUE ; -- all zero or found a one
end function ZeroOneHot ;
------------------------------------------------------------
-- IfElse
-- Crutch until VHDL-2019 conditional initialization
-- If condition is true return first parameter otherwise return second
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : std_logic_vector) return std_logic_vector is
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
function IfElse(Expr : boolean ; A, B : integer) return integer is
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- RequestTransaction - Transaction initiation in transaction procedure
-- WaitForTransaction - Transaction execution control in VC
------------------------------------------------------------
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- std_logic
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end procedure WaitForTransaction ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- bit
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end procedure WaitForTransaction ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- integer
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : InOut RdyType ;
signal Ack : In AckType
) is
begin
-- Initiate Transaction Request
Rdy <= Increment(Rdy) ;
wait for 0 ns ;
-- Wait for Transaction Completion
wait until Rdy = Ack ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= Increment(Ack) ;
AckTime := NOW ;
-- Find Start of Transaction
wait until Ack /= Rdy ;
-- Align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure WaitForTransaction ;
------------------------------------------------------------
-- WaitForTransaction
-- Specializations for interrupt handling
-- Currently only std_logic based
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) is
variable AckTime : time ;
variable FoundRdy : boolean ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Ready or Time out
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if (Rdy /= '1' and TimeOut /= Polarity) then
wait until Rdy = '1' or TimeOut = Polarity ;
end if ;
FoundRdy := Rdy = '1' ;
-- align to clock if Rdy or TimeOut does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
if FoundRdy then
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end if ;
end procedure WaitForTransaction ;
-- Variation for model that stops waiting when IntReq is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) is
variable AckTime : time ;
constant POLARITY : std_logic := '1' ;
begin
AckTime := NOW ;
-- Find Ready or Time out
wait for 0 ns ; -- allow Rdy from previous cycle to clear
if (Rdy /= '1' and IntReq /= POLARITY) then
wait until Rdy = '1' or IntReq = POLARITY ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if Rdy or IntReq does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure ;
-- Set Ack to Model starting value
-- Pairs with WaitForTransactionOrIrq above
procedure StartTransaction ( signal Ack : Out std_logic ) is
begin
Ack <= '0' ;
wait for 0 ns ; -- Allow transactions without time passing
end procedure StartTransaction ;
-- Set Ack to Model finishing value
-- Pairs with WaitForTransactionOrIrq above
procedure FinishTransaction ( signal Ack : Out std_logic ) is
begin
-- End of Cycle
Ack <= '1' ;
wait for 0 ns ; -- Allow Ack to update
end procedure FinishTransaction ;
-- If a transaction is pending, return true
-- Used to detect presence of transaction stream,
-- such as an interrupt handler
function TransactionPending (
signal Rdy : In std_logic
) return boolean is
begin
return Rdy = '1' ;
end function TransactionPending ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- allow 0 time transactions
end procedure WaitForTransaction ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
type stdulogic_indexby_stdulogic is array (std_ulogic) of std_ulogic;
constant toggle_sl_table : stdulogic_indexby_stdulogic := (
'0' => '1',
'L' => '1',
others => '0'
);
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec, "osvvm.TbUtilPkg.Toggle: Delay value < 0 ns") ;
end if ;
Sig <= toggle_sl_table(Sig) after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In std_logic ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In std_logic ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec,
"osvvm.TbUtilPkg.Toggle: Delay value < 0 ns", WARNING) ;
end if ;
Sig <= not Sig after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In bit ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In bit ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Integer type versions
procedure Increment (signal Sig : InOut integer ; constant RollOverValue : in integer := 0) is
begin
--!! if Sig = integer'high then
if Sig = 2**30-1 then -- for consistency with function increment
Sig <= RollOverValue ;
else
Sig <= Sig + 1 ;
end if ;
end procedure Increment ;
function Increment (constant Sig : in integer ; constant Amount : in integer := 1) return integer is
begin
return (Sig + Amount) mod 2**30 ;
end function Increment ;
procedure WaitForToggle ( signal Sig : In integer ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
------------------------------------------------------------
-- resolved_barrier
-- summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer is
variable result : integer := 0 ;
begin
for i in s'RANGE loop
-- if s(i) /= integer'left then
-- result := result + s(i);
-- else
if s(i) /= 0 then
result := result + 1; -- removes the initialization requirement
end if ;
end loop ;
return result ;
end function resolved_barrier ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) is
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until other process' Rdy is at level 1
if SyncIn /= '1' then
wait until SyncIn = '1' ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) is
constant ALL_ONE : std_logic_vector(SyncInV'Range) := (others => '1');
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until all other process' Rdy is at level 1
if SyncInV /= ALL_ONE then
wait until SyncInV = ALL_ONE ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) is
begin
if delay > t_sim_resolution then
wait for delay - t_sim_resolution ;
end if ;
wait until Clk = CLK_ACTIVE ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) is
begin
for i in 1 to NumberOfClocks loop
wait until Clk = CLK_ACTIVE ;
end loop ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable = Polarity ;
end procedure WaitForClock ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) is
begin
if not A then
wait until A ;
end if ;
end procedure WaitForLevel ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) is
begin
if A /= Polarity then
-- wait on A until A = Polarity ;
if Polarity = '1' then
wait until A = '1' ;
else
wait until A = '0' ;
end if ;
end if ;
end procedure WaitForLevel ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) is
constant HIGH_TIME : time := Period * DutyCycle ;
constant LOW_TIME : time := Period - HIGH_TIME ;
begin
if HIGH_TIME = LOW_TIME then
loop
Clk <= toggle_sl_table(Clk) after HIGH_TIME ;
wait on Clk ;
end loop ;
else
-- Schedule s.t. all assignments after the first occur on delta cycle 0
Clk <= '0', '1' after LOW_TIME ;
wait for period - 1 ns ; -- allows after on future Clk <= '0'
loop
Clk <= '0' after 1 ns, '1' after LOW_TIME + 1 ns ;
wait for period ;
end loop ;
end if ;
end procedure CreateClock ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
variable LastLogTime, ObservedPeriod : time ;
begin
wait until Clk = CLK_ACTIVE ;
LastLogTime := now ;
-- Check First HowMany clocks
for i in 1 to HowMany loop
wait until Clk = CLK_ACTIVE ;
ObservedPeriod := now - LastLogTime ;
AffirmIf(AlertLogID, ObservedPeriod = Period,
"CheckClockPeriod: " & ClkName & " Period: " & to_string(ObservedPeriod) &
" = Expected " & to_string(Period)) ;
LastLogTime := now ;
end loop ;
wait ;
end procedure CheckClockPeriod ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
begin
CheckClockPeriod (
AlertLogID => ALERTLOG_DEFAULT_ID,
Clk => Clk,
Period => Period,
ClkName => ClkName,
HowMany => HowMany
) ;
end procedure CheckClockPeriod ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time
) is
begin
wait until Clk = CLK_ACTIVE ;
Reset <= ResetActive after tpd ;
wait for Period - t_sim_resolution ;
wait until Clk = CLK_ACTIVE ;
Reset <= not ResetActive after tpd ;
wait ;
end procedure CreateReset ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
-- Does not log the value of Reset at time 0.
for_ever : loop
wait on Reset ;
if Reset = ResetActive then
LOG(AlertLogID, ResetName & " now active", INFO) ;
print("") ;
elsif Reset = not ResetActive then
LOG(AlertLogID, ResetName & " now inactive", INFO) ;
print("") ;
else
LOG(AlertLogID, ResetName & " = " & to_string(Reset), INFO) ;
print("") ;
end if ;
end loop for_ever ;
end procedure LogReset ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
LogReset (
AlertLogID => ALERTLOG_DEFAULT_ID,
Reset => Reset,
ResetActive => ResetActive,
ResetName => ResetName,
LogLevel => LogLevel
) ;
end procedure LogReset ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) is
begin
-- Wait for Model to be done
wait until Ack = '1' ;
wait for 0 ns ;
end procedure ;
procedure StrobeAck ( signal Ack : Out std_logic ) is
begin
-- Model done, drive rising edge on Ack
Ack <= '0' ;
wait for 0 ns ;
Ack <= '1' ;
wait for 0 ns ;
end procedure ;
end TbUtilPkg ;
| artistic-2.0 |
aggroskater/ee4321-vhdl-digital-design | Project-4-4bit-ALU/lib/mux/mux4_bit.vhd | 1 | 517 | --Helpful resource:
--ftp://www.cs.uregina.ca/pub/class/301/multiplexer/lecture.html
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4_bit is
port(
bit3 : in std_logic;
bit2 : in std_logic;
bit1 : in std_logic;
bit0 : in std_logic;
S : in std_logic_vector(1 downto 0);
R : out std_logic
);
end mux4_bit;
architecture Behavioural of mux4_bit is
begin
with S select
R <= bit0 when "00",
bit1 when "01",
bit2 when "10",
bit3 when others;
end Behavioural;
| agpl-3.0 |
aggroskater/ee4321-vhdl-digital-design | Project-4-4bit-ALU/lib/add_sub/cl_logic.vhd | 2 | 2085 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cl_logic is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cin1 : out STD_LOGIC;
Cin2 : out STD_LOGIC;
Cin3 : out STD_LOGIC;
Cout : out STD_LOGIC);
end cl_logic;
architecture Behavioral of cl_logic is
begin
-- Cin1 = G_0 + P_0 * Cin0
Cin1 <= ( A(0) AND B(0) )
OR ( (Cin)
AND (A(0) OR B(0)) );
-- Cin2 = G_1 + P_1 * Cin1
Cin2 <= ( A(1) AND B(1) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1)) );
-- Cin3 = G_2 + P_2 * Cin2
Cin3 <= ( A(2) AND B(2) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) );
-- Cout = G_3 + P_3 * Cin3
Cout <= ( A(3) AND B(3) )
OR ( (A(2) AND B(2))
AND (A(3) OR B(3)) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) );
end Behavioral;
| agpl-3.0 |
aggroskater/ee4321-vhdl-digital-design | Project-4-4bit-ALU/alu.vhd | 1 | 1816 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity alu_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (5 downto 0);
R : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end alu_4_bit;
architecture Behavioral of alu_4_bit is
--these signals carry internal outputs from the different blocks for routing to
--appropriate stages (mostly the output choice mux4)
signal add_sub_zero : std_logic:='0';
signal add_sub_Cout : std_logic:='0';
signal add_sub_overflow : std_logic:='0';
signal add_sub_R : std_logic_vector (3 downto 0);
signal comparator_R: std_logic_vector (3 downto 0) := (others => '0');
signal logical_R: std_logic_vector (3 downto 0);
signal shift_rot_R: std_logic_vector (3 downto 0);
begin
--adder/subtractor unit
add_sub: entity work.cla_4_bit port map (A, B, op(3), add_sub_R,
add_sub_Cout, add_sub_zero, add_sub_overflow);
--comparator unit
comparator: entity work.comparator port map (A, B, op(2 downto 0),
add_sub_zero, add_sub_Cout, add_sub_overflow, add_sub_R, comparator_R(0));
--logical unit
logical: entity work.logical port map (A, B, op(1 downto 0), logical_R);
--shift/rotate unit
shift_rot: entity work.shift_rotate port map (A, B, op(2 downto 0), shift_rot_R);
--output selection mux
output_choice_mux: entity work.mux4 port map (add_sub_R, comparator_R, logical_R,
shift_rot_R, op(5 downto 4), R);
--make sure Cout gets assigned
Cout <= add_sub_Cout;
end Behavioral;
--A note: This design is entirely combinatorial and likely purely insane. EVERY
--operation is carried out, and the output choice mux merely selects which
--block_R to push to the ALU's "R" output. This would be a truly terrible
--design as far as power constraints go.
| agpl-3.0 |
aggroskater/ee4321-vhdl-digital-design | Project-4-4bit-ALU/lib/comparator/comparator.vhd | 1 | 3008 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--NOTE: the "diff" input comes from the output of the add_sub module.
--the way the opcodes are defined, the output is always the difference
--of A and B if the user is requesting a comparison operation. Otherwise,
--the output of this module will technically be undefined/wrong, but it
--doesn't matter because we won't be selecting it for the final output.
entity comparator is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (2 downto 0);
zero : in STD_LOGIC;
cout : in STD_LOGIC;
overflow : in STD_LOGIC;
diff : in STD_LOGIC_VECTOR (3 downto 0);
R : out STD_LOGIC
);
end comparator;
architecture Behavioral of comparator is
--signals
signal a_GEQ_b_SIGNED_R : std_logic:='0';
signal a_LE_b_SIGNED_R : std_logic:='0';
signal a_NEQ_b_UNSIGNED_R : std_logic:='0';
signal a_EQ_b_UNSIGNED_R : std_logic:='0';
signal a_GEQ_b_UNSIGNED_R : std_logic:='0';
signal a_LE_b_UNSIGNED_R : std_logic:='0';
signal s : std_logic_vector(3 downto 0);
begin
-------------------------------------------
--SIGNED PORTIONS
-------------------------------------------
--SIGNED is a bit more tricky. However, we can take
--advantage of the overflow flag and arrive at the
--following conclusions:
--(thanks to: http://teahlab.com/4-Bit_Signed_Comparator/)
-- X = Y <--> zero
-- X < Y <--> diff(3) XOR overflow
-- X > Y <--> !( zero OR ( diff(3) XOR overflow) )
--GEQ SIGNED
a_GEQ_b_SIGNED_R <= NOT(zero OR (diff(3) XOR overflow) ) OR zero;
--LE SIGNED
a_LE_b_SIGNED_R <= diff(3) XOR overflow;
-------------------------------------------
--UNSIGNED PORTIONS
-------------------------------------------
--EQ/NEQ
--well, *that* was easy :D
a_NEQ_b_UNSIGNED_R <= NOT(zero);
a_EQ_b_UNSIGNED_R <= zero;
--GEQ UNSIGNED
--Well, it turns out unsigned is harder. I'm way behind and
--so close to being done, so I'm borrowing some code from here
--to make sure the tests all work:
--http://sid-vlsiarena.blogspot.com/2013/03/4-bit-magnitude-comparator-vhdl-code.html
--I'll have to explain the karnaugh map theory behind it later in the report.
s(0)<= a(0) xnor b(0);
s(1)<= a(1) xnor b(1);
s(2)<= a(2) xnor b(2);
s(3)<= a(3) xnor b(3);
a_GEQ_b_UNSIGNED_R <= (a(3) and (not b(3)))
or (s(3) and a(2) and (not b(2)))
or (s(3) and s(2) and a(1)and (not b(1)))
or (s(3) and s(2) and s(1) and a(0) and (not b(0)))
or zero;
--LE UNSIGNED
a_LE_b_UNSIGNED_R <= (b(3) and (not a(3)))
or (s(3) and b(2) and (not a(2)))
or (s(3) and s(2) and b(1)and (not a(1)))
or (s(3) and s(2) and s(1) and b(0) and (not a(0)));
-------------------------------------------
--select output based on opcode
-------------------------------------------
output: entity work.mux8_bit port map (open, a_GEQ_b_SIGNED_R, a_LE_B_SIGNED_R,
a_NEQ_b_UNSIGNED_R, a_EQ_b_UNSIGNED_R, a_GEQ_b_UNSIGNED_R, a_LE_b_UNSIGNED_R,
open, op, R);
end Behavioral;
| agpl-3.0 |
eggcar/time-holdover-cycloneIV-board-old | TimeHoldOver_Qsys/TimeHoldOver_Qsys_inst.vhd | 1 | 13558 | component TimeHoldOver_Qsys is
port (
clk_clk : in std_logic := 'X'; -- clk
epcs_flash_controller_dclk : out std_logic; -- dclk
epcs_flash_controller_sce : out std_logic; -- sce
epcs_flash_controller_sdo : out std_logic; -- sdo
epcs_flash_controller_data0 : in std_logic := 'X'; -- data0
on_chip_rst_and_pps_switch_export : out std_logic_vector(8 downto 0); -- export
io_update_ctrl_export : out std_logic; -- export
ocxo_lock_export : in std_logic := 'X'; -- export
pps_interrupt_export : in std_logic := 'X'; -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_controller_addr : out std_logic_vector(11 downto 0); -- addr
sdram_controller_ba : out std_logic_vector(1 downto 0); -- ba
sdram_controller_cas_n : out std_logic; -- cas_n
sdram_controller_cke : out std_logic; -- cke
sdram_controller_cs_n : out std_logic; -- cs_n
sdram_controller_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_controller_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_controller_ras_n : out std_logic; -- ras_n
sdram_controller_we_n : out std_logic; -- we_n
timer_ecc_fault_itr_export : in std_logic := 'X'; -- export
timer_interface_coe_sec_cnt_set_data_out : out std_logic_vector(192 downto 0); -- coe_sec_cnt_set_data_out
timer_interface_coe_sec_cnt_get_data_in : in std_logic_vector(191 downto 0) := (others => 'X'); -- coe_sec_cnt_get_data_in
timer_interface_coe_ns_cnt_set_data_out : out std_logic_vector(96 downto 0); -- coe_ns_cnt_set_data_out
timer_interface_coe_ns_cnt_get_data_in : in std_logic_vector(95 downto 0) := (others => 'X'); -- coe_ns_cnt_get_data_in
timer_interface_coe_ctrl_cnt_set_out : out std_logic_vector(24 downto 0); -- coe_ctrl_cnt_set_out
timer_interface_coe_ctrl_cnt_get_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- coe_ctrl_cnt_get_in
timer_interface_coe_err_cnt_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- coe_err_cnt_in
timer_interface_coe_utc_time_in : in std_logic_vector(55 downto 0) := (others => 'X'); -- coe_utc_time_in
timer_interface_coe_time_zone_set_out : out std_logic_vector(8 downto 0); -- coe_time_zone_set_out
timer_interface_coe_time_zone_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_time_zone_get_in
timer_interface_coe_leap_cnt_set_out : out std_logic_vector(16 downto 0); -- coe_leap_cnt_set_out
timer_interface_coe_leap_cnt_get_in : in std_logic_vector(15 downto 0) := (others => 'X'); -- coe_leap_cnt_get_in
timer_interface_coe_leap_occur_set_out : out std_logic_vector(64 downto 0); -- coe_leap_occur_set_out
timer_interface_coe_leap_occur_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_leap_occur_get_in
timer_interface_coe_dst_ingress_set_out : out std_logic_vector(64 downto 0); -- coe_dst_ingress_set_out
timer_interface_coe_dst_ingress_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_dst_ingress_get_in
timer_interface_coe_dst_engress_set_out : out std_logic_vector(64 downto 0); -- coe_dst_engress_set_out
timer_interface_coe_dst_engress_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_dst_engress_get_in
timer_interface_coe_leap_direct_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_leap_direct_get_in
timer_interface_coe_leap_direct_set_out : out std_logic_vector(8 downto 0); -- coe_leap_direct_set_out
timer_interface_coe_io_update_in : in std_logic := 'X'; -- coe_io_update_in
timer_interface_coe_time_quality_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_time_quality_get_in
timer_interface_coe_time_quality_set_out : out std_logic_vector(8 downto 0); -- coe_time_quality_set_out
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
uart_1_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_1_external_connection_txd : out std_logic; -- txd
uart_2_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_2_external_connection_txd : out std_logic; -- txd
uart_3_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_3_external_connection_txd : out std_logic -- txd
);
end component TimeHoldOver_Qsys;
u0 : component TimeHoldOver_Qsys
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
epcs_flash_controller_dclk => CONNECTED_TO_epcs_flash_controller_dclk, -- epcs_flash_controller.dclk
epcs_flash_controller_sce => CONNECTED_TO_epcs_flash_controller_sce, -- .sce
epcs_flash_controller_sdo => CONNECTED_TO_epcs_flash_controller_sdo, -- .sdo
epcs_flash_controller_data0 => CONNECTED_TO_epcs_flash_controller_data0, -- .data0
on_chip_rst_and_pps_switch_export => CONNECTED_TO_on_chip_rst_and_pps_switch_export, -- on_chip_rst_and_pps_switch.export
io_update_ctrl_export => CONNECTED_TO_io_update_ctrl_export, -- io_update_ctrl.export
ocxo_lock_export => CONNECTED_TO_ocxo_lock_export, -- ocxo_lock.export
pps_interrupt_export => CONNECTED_TO_pps_interrupt_export, -- pps_interrupt.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_controller_addr => CONNECTED_TO_sdram_controller_addr, -- sdram_controller.addr
sdram_controller_ba => CONNECTED_TO_sdram_controller_ba, -- .ba
sdram_controller_cas_n => CONNECTED_TO_sdram_controller_cas_n, -- .cas_n
sdram_controller_cke => CONNECTED_TO_sdram_controller_cke, -- .cke
sdram_controller_cs_n => CONNECTED_TO_sdram_controller_cs_n, -- .cs_n
sdram_controller_dq => CONNECTED_TO_sdram_controller_dq, -- .dq
sdram_controller_dqm => CONNECTED_TO_sdram_controller_dqm, -- .dqm
sdram_controller_ras_n => CONNECTED_TO_sdram_controller_ras_n, -- .ras_n
sdram_controller_we_n => CONNECTED_TO_sdram_controller_we_n, -- .we_n
timer_ecc_fault_itr_export => CONNECTED_TO_timer_ecc_fault_itr_export, -- timer_ecc_fault_itr.export
timer_interface_coe_sec_cnt_set_data_out => CONNECTED_TO_timer_interface_coe_sec_cnt_set_data_out, -- timer_interface.coe_sec_cnt_set_data_out
timer_interface_coe_sec_cnt_get_data_in => CONNECTED_TO_timer_interface_coe_sec_cnt_get_data_in, -- .coe_sec_cnt_get_data_in
timer_interface_coe_ns_cnt_set_data_out => CONNECTED_TO_timer_interface_coe_ns_cnt_set_data_out, -- .coe_ns_cnt_set_data_out
timer_interface_coe_ns_cnt_get_data_in => CONNECTED_TO_timer_interface_coe_ns_cnt_get_data_in, -- .coe_ns_cnt_get_data_in
timer_interface_coe_ctrl_cnt_set_out => CONNECTED_TO_timer_interface_coe_ctrl_cnt_set_out, -- .coe_ctrl_cnt_set_out
timer_interface_coe_ctrl_cnt_get_in => CONNECTED_TO_timer_interface_coe_ctrl_cnt_get_in, -- .coe_ctrl_cnt_get_in
timer_interface_coe_err_cnt_in => CONNECTED_TO_timer_interface_coe_err_cnt_in, -- .coe_err_cnt_in
timer_interface_coe_utc_time_in => CONNECTED_TO_timer_interface_coe_utc_time_in, -- .coe_utc_time_in
timer_interface_coe_time_zone_set_out => CONNECTED_TO_timer_interface_coe_time_zone_set_out, -- .coe_time_zone_set_out
timer_interface_coe_time_zone_get_in => CONNECTED_TO_timer_interface_coe_time_zone_get_in, -- .coe_time_zone_get_in
timer_interface_coe_leap_cnt_set_out => CONNECTED_TO_timer_interface_coe_leap_cnt_set_out, -- .coe_leap_cnt_set_out
timer_interface_coe_leap_cnt_get_in => CONNECTED_TO_timer_interface_coe_leap_cnt_get_in, -- .coe_leap_cnt_get_in
timer_interface_coe_leap_occur_set_out => CONNECTED_TO_timer_interface_coe_leap_occur_set_out, -- .coe_leap_occur_set_out
timer_interface_coe_leap_occur_get_in => CONNECTED_TO_timer_interface_coe_leap_occur_get_in, -- .coe_leap_occur_get_in
timer_interface_coe_dst_ingress_set_out => CONNECTED_TO_timer_interface_coe_dst_ingress_set_out, -- .coe_dst_ingress_set_out
timer_interface_coe_dst_ingress_get_in => CONNECTED_TO_timer_interface_coe_dst_ingress_get_in, -- .coe_dst_ingress_get_in
timer_interface_coe_dst_engress_set_out => CONNECTED_TO_timer_interface_coe_dst_engress_set_out, -- .coe_dst_engress_set_out
timer_interface_coe_dst_engress_get_in => CONNECTED_TO_timer_interface_coe_dst_engress_get_in, -- .coe_dst_engress_get_in
timer_interface_coe_leap_direct_get_in => CONNECTED_TO_timer_interface_coe_leap_direct_get_in, -- .coe_leap_direct_get_in
timer_interface_coe_leap_direct_set_out => CONNECTED_TO_timer_interface_coe_leap_direct_set_out, -- .coe_leap_direct_set_out
timer_interface_coe_io_update_in => CONNECTED_TO_timer_interface_coe_io_update_in, -- .coe_io_update_in
timer_interface_coe_time_quality_get_in => CONNECTED_TO_timer_interface_coe_time_quality_get_in, -- .coe_time_quality_get_in
timer_interface_coe_time_quality_set_out => CONNECTED_TO_timer_interface_coe_time_quality_set_out, -- .coe_time_quality_set_out
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd, -- .txd
uart_1_external_connection_rxd => CONNECTED_TO_uart_1_external_connection_rxd, -- uart_1_external_connection.rxd
uart_1_external_connection_txd => CONNECTED_TO_uart_1_external_connection_txd, -- .txd
uart_2_external_connection_rxd => CONNECTED_TO_uart_2_external_connection_rxd, -- uart_2_external_connection.rxd
uart_2_external_connection_txd => CONNECTED_TO_uart_2_external_connection_txd, -- .txd
uart_3_external_connection_rxd => CONNECTED_TO_uart_3_external_connection_rxd, -- uart_3_external_connection.rxd
uart_3_external_connection_txd => CONNECTED_TO_uart_3_external_connection_txd -- .txd
);
| agpl-3.0 |
mpwillson/mal | vhdl/printer.vhdl | 17 | 3030 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package printer is
procedure pr_str(ast: inout mal_val_ptr; readable: in boolean; result: out line);
procedure pr_seq(start_ch: in string; end_ch: in string; delim: in string; a_seq: inout mal_seq_ptr; readable: in boolean; result: out line);
end package printer;
package body printer is
procedure pr_string(val: inout line; readable: in boolean; result: out line) is
variable s: line;
variable src_i, dst_i: integer;
begin
if readable then
s := new string(1 to val'length * 2);
dst_i := 0;
for src_i in val'range loop
dst_i := dst_i + 1;
case val(src_i) is
when LF =>
s(dst_i) := '\';
dst_i := dst_i + 1;
s(dst_i) := 'n';
when '"' =>
s(dst_i) := '\';
dst_i := dst_i + 1;
s(dst_i) := '"';
when '\' =>
s(dst_i) := '\';
dst_i := dst_i + 1;
s(dst_i) := '\';
when others =>
s(dst_i) := val(src_i);
end case;
end loop;
result := new string'("" & '"' & s(1 to dst_i) & '"');
deallocate(s);
else
result := val;
end if;
end;
procedure pr_str(ast: inout mal_val_ptr; readable: in boolean; result: out line) is
variable l: line;
begin
case ast.val_type is
when mal_nil =>
result := new string'("nil");
when mal_true =>
result := new string'("true");
when mal_false =>
result := new string'("false");
when mal_number =>
write(l, ast.number_val);
result := l;
when mal_symbol =>
result := ast.string_val;
when mal_string =>
pr_string(ast.string_val, readable, result);
when mal_keyword =>
result := new string'(":" & ast.string_val.all);
when mal_list =>
pr_seq("(", ")", " ", ast.seq_val, readable, result);
when mal_vector =>
pr_seq("[", "]", " ", ast.seq_val, readable, result);
when mal_hashmap =>
pr_seq("{", "}", " ", ast.seq_val, readable, result);
when mal_atom =>
pr_str(ast.seq_val(0), true, l);
result := new string'("(atom " & l.all & ")");
when mal_nativefn =>
result := new string'("#<NativeFunction:" & ast.string_val.all & ">");
when mal_fn =>
result := new string'("#<MalFunction>");
end case;
end procedure pr_str;
procedure pr_seq(start_ch: in string; end_ch: in string; delim: in string; a_seq: inout mal_seq_ptr; readable: in boolean; result: out line) is
variable s, element_s: line;
begin
s := new string'(start_ch);
for i in a_seq'range loop
pr_str(a_seq(i), readable, element_s);
if i = 0 then
s := new string'(s.all & element_s.all);
else
s := new string'(s.all & delim & element_s.all);
end if;
end loop;
s := new string'(s.all & end_ch);
result := s;
end procedure pr_seq;
end package body printer;
| mpl-2.0 |
mpwillson/mal | vhdl/pkg_readline.vhdl | 17 | 928 | library STD;
use STD.textio.all;
package pkg_readline is
procedure mal_printline(l: string);
procedure mal_readline(prompt: string; eof_detected: out boolean; l: inout line);
end package pkg_readline;
package body pkg_readline is
type charfile is file of character;
file stdout_char: charfile open write_mode is "STD_OUTPUT";
procedure mal_printstr(l: string) is
begin
for i in l'range loop
write(stdout_char, l(i));
end loop;
end procedure mal_printstr;
procedure mal_printline(l: string) is
begin
mal_printstr(l);
write(stdout_char, LF);
end procedure mal_printline;
procedure mal_readline(prompt: string; eof_detected: out boolean; l: inout line) is
begin
mal_printstr(prompt);
if endfile(input) then
eof_detected := true;
else
readline(input, l);
eof_detected := false;
end if;
end procedure mal_readline;
end package body pkg_readline;
| mpl-2.0 |
kraigher/axi_bfm | src/axi_memory.vhd | 1 | 6868 | -- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2015, Olof Kraigher olof.kraigher@gmail.com
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_model_ptype_pkg.all;
package axi_memory_pkg is
procedure simulate_read_slave(
variable memory_model : inout memory_model_t;
signal aclk : in std_logic;
signal arvalid : in std_logic;
signal arready : out std_logic;
signal arid : in std_logic_vector;
signal araddr : in std_logic_vector;
signal arlen : in std_logic_vector;
signal arsize : in std_logic_vector;
signal arburst : in std_logic_vector;
signal rvalid : out std_logic;
signal rready : in std_logic;
signal rid : out std_logic_vector;
signal rdata : out std_logic_vector;
signal rresp : out std_logic_vector;
signal rlast : out std_logic);
procedure simulate_write_slave(
variable memory_model : inout memory_model_t;
signal aclk : in std_logic;
signal awvalid : in std_logic;
signal awready : out std_logic;
signal awid : in std_logic_vector;
signal awaddr : in std_logic_vector;
signal awlen : in std_logic_vector;
signal awsize : in std_logic_vector;
signal awburst : in std_logic_vector;
signal wvalid : in std_logic;
signal wready : out std_logic;
signal wid : in std_logic_vector;
signal wdata : in std_logic_vector;
signal wstrb : in std_logic_vector;
signal wlast : in std_logic;
signal bvalid : out std_logic;
signal bready : in std_logic;
signal bid : out std_logic_vector;
signal bresp : out std_logic_vector);
end package;
package body axi_memory_pkg is
type burst_type_t is (fixed, incr, wrap);
function to_burst_type_t(value : std_logic_vector) return burst_type_t is
begin
case value is
when "00" => return fixed;
when "01" => return incr;
when "10" => return wrap;
when others => report "Invalid burst type" severity error;
end case;
return fixed;
end function;
procedure simulate_read_slave(
variable memory_model : inout memory_model_t;
signal aclk : in std_logic;
signal arvalid : in std_logic;
signal arready : out std_logic;
signal arid : in std_logic_vector;
signal araddr : in std_logic_vector;
signal arlen : in std_logic_vector;
signal arsize : in std_logic_vector;
signal arburst : in std_logic_vector;
signal rvalid : out std_logic;
signal rready : in std_logic;
signal rid : out std_logic_vector;
signal rdata : out std_logic_vector;
signal rresp : out std_logic_vector;
signal rlast : out std_logic) is
variable address : integer;
variable burst_length : integer;
variable burst_size : integer;
variable burst_type : burst_type_t;
begin
-- Static Error checking
assert arid'length = rid'length report "arid vs rid data width mismatch";
assert (arlen'length = 4 or
arlen'length = 8) report "arlen must be either 4 (AXI3) or 8 (AXI4)";
-- Initialization
rvalid <= '0';
rid <= (rid'range => '0');
rdata <= (rdata'range => '0');
rresp <= (rresp'range => '0');
rlast <= '0';
loop
-- Read AR channel
arready <= '1';
wait until (arvalid and arready) = '1' and rising_edge(aclk);
arready <= '0';
address := to_integer(unsigned(araddr));
burst_length := to_integer(unsigned(arlen)) + 1;
burst_size := 2**to_integer(unsigned(arsize));
burst_type := to_burst_type_t(arburst);
rid <= arid;
assert burst_type /= wrap report "Wrapping burst type not supported";
rdata <= (rdata'range => '0');
rresp <= "00"; -- Okay
for i in 0 to burst_length-1 loop
for j in 0 to burst_size-1 loop
rdata(8*j+7 downto 8*j) <= std_logic_vector(to_unsigned(memory_model.read_byte(address+j), 8));
end loop;
if burst_type = incr then
address := address + burst_size;
end if;
rvalid <= '1';
if i = burst_length - 1 then
rlast <= '1';
else
rlast <= '0';
end if;
wait until (rvalid and rready) = '1' and rising_edge(aclk);
rvalid <= '0';
end loop;
end loop;
end;
procedure simulate_write_slave(
variable memory_model : inout memory_model_t;
signal aclk : in std_logic;
signal awvalid : in std_logic;
signal awready : out std_logic;
signal awid : in std_logic_vector;
signal awaddr : in std_logic_vector;
signal awlen : in std_logic_vector;
signal awsize : in std_logic_vector;
signal awburst : in std_logic_vector;
signal wvalid : in std_logic;
signal wready : out std_logic;
signal wid : in std_logic_vector;
signal wdata : in std_logic_vector;
signal wstrb : in std_logic_vector;
signal wlast : in std_logic;
signal bvalid : out std_logic;
signal bready : in std_logic;
signal bid : out std_logic_vector;
signal bresp : out std_logic_vector) is
variable address : integer;
variable burst_length : integer;
variable burst_size : integer;
variable burst_type : burst_type_t;
begin
-- Static Error checking
assert awid'length = bid'length report "arwid vs wid data width mismatch";
assert (awlen'length = 4 or
awlen'length = 8) report "awlen must be either 4 (AXI3) or 8 (AXI4)";
-- Initialization
wready <= '0';
bvalid <= '0';
bid <= (bid'range => '0');
bresp <= (bresp'range => '0');
loop
awready <= '1';
wait until (awvalid and awready) = '1' and rising_edge(aclk);
awready <= '0';
address := to_integer(unsigned(awaddr));
burst_length := to_integer(unsigned(awlen)) + 1;
burst_size := 2**to_integer(unsigned(awsize));
burst_type := to_burst_type_t(awburst);
assert burst_type /= wrap report "Wrapping burst type not supported";
bid <= awid;
bresp <= "00"; -- Okay
for i in 0 to burst_length-1 loop
wready <= '1';
wait until (wvalid and wready) = '1' and rising_edge(aclk);
wready <= '0';
for j in 0 to burst_size-1 loop
if wstrb(j) = '1' then
memory_model.write_byte(address+j, to_integer(unsigned(wdata(8*j+7 downto 8*j))));
end if;
end loop;
if burst_type = incr then
address := address + burst_size;
end if;
assert (wlast = '1') = (i = burst_length-1) report "invalid wlast";
end loop;
bvalid <= '1';
wait until (bvalid and bready) = '1' and rising_edge(aclk);
bvalid <= '0';
end loop;
end;
end package body;
| mpl-2.0 |
preusser/q27 | src/vhdl/PoC/fifo/fifo_cc_got.vhdl | 2 | 12858 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Module: FIFO, Common Clock (cc), Pipelined Interface
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- DATA_REG (=true) is a hint, that distributed memory or registers should be
-- used as data storage. The actual memory type depends on the device
-- architecture. See implementation for details.
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
use poc.utils.all;
use poc.ocram.ocram_sdp;
entity fifo_cc_got is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0)
);
end fifo_cc_got;
architecture rtl of fifo_cc_got is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
OP0 <= (others => '0');
else
-- Update Input Pointer upon Write
if we = '1' then
IP0 <= IP1;
end if;
-- Update Output Pointer upon Read
if re = '1' then
OP0 <= OP1;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(IP0, OP0, fulli)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
estate_wr <= (others => 'X');
fstate_rd <= (others => 'X');
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
-- Fix assignment to outputs
if ESTATE_WR_BITS > 0 then
-- one's complement is pessimistically low by one but
-- benefits optimization by synthesis
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
end if;
if FSTATE_RD_BITS > 0 then
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
-- Cheapest implementation using a direction flag DF to determine
-- full or empty condition on equal input and output pointers.
-- Both conditions are derived combinationally involving a comparison
-- of the two pointers.
genStateCmb: if not STATE_REG generate
signal DF : std_logic := '0'; -- Direction Flag
signal Peq : std_logic; -- Pointer Comparison
begin
-- Direction Flag remembering the last Operation
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
DF <= '0'; -- get => empty
elsif we /= re then
DF <= we;
end if;
end if;
end process;
-- Fill Conditions
Peq <= '1' when IP0 = OP0 else '0';
fulli <= Peq and DF;
empti <= Peq and not DF;
end generate genStateCmb;
-- Implementation investing another comparator so as to provide both full and
-- empty indications from registers.
genStateReg: if STATE_REG generate
signal Ful : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Avl <= '0';
elsif we /= re then
-- Update Full Indicator
if we = '0' or IP1 /= OP0 then
Ful <= '0';
else
Ful <= '1';
end if;
-- Update Empty Indicator
if re = '0' or OP1 /= IP0 then
Avl <= '1';
else
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end generate genStateReg;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
| agpl-3.0 |
preusser/q27 | src/vhdl/PoC/common/my_config_KC705.vhdl | 2 | 1751 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "KC705"; -- KC705 - Xilinx Kintex 7 reference design board: XC7K325T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
| agpl-3.0 |
preusser/q27 | src/vhdl/queens/queens_chain.vhdl | 1 | 7997 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity queens_chain is
generic (
-- Problem Size
N : positive;
L : positive;
-- Design Spec
SOLVERS : positive;
COUNT_CYCLES : boolean
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Problem Chain
piful : out std_logic;
pidat : in std_logic_vector(7 downto 0);
pieof : in std_logic;
piput : in std_logic;
poful : in std_logic := '1'; -- Open-end as default
podat : out std_logic_vector(7 downto 0);
poeof : out std_logic;
poput : out std_logic;
-- Solution Chain
sivld : in std_logic := '0';
sidat : in std_logic_vector(7 downto 0) := (others => '-');
sieof : in std_logic := '-';
sigot : out std_logic;
sovld : out std_logic;
sodat : out std_logic_vector(7 downto 0);
soeof : out std_logic;
sogot : in std_logic
);
end queens_chain;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.fifo.all;
architecture rtl of queens_chain is
-- Bit Length of Pre-Placement
constant PRE_BITS : positive := 4*L*log2ceil(N)-1;
constant PRE_BYTES : positive := (PRE_BITS+7)/8;
-- Inter-Stage Input Distribution
signal pful : std_logic_vector(0 to SOLVERS);
signal pdat : byte_vector(0 to SOLVERS);
signal peof : std_logic_vector(0 to SOLVERS);
signal pput : std_logic_vector(0 to SOLVERS);
-- Inter-Stage Result Stream
signal svld : std_logic_vector(0 to SOLVERS);
signal sdat : byte_vector(0 to SOLVERS);
signal seof : std_logic_vector(0 to SOLVERS);
signal sgot : std_logic_vector(0 to SOLVERS);
begin
-- Connect Subproblem Chain
piful <= pful(0);
pdat(0) <= pidat;
peof(0) <= pieof;
pput(0) <= piput;
pful(SOLVERS) <= poful;
podat <= pdat(SOLVERS);
poeof <= peof(SOLVERS);
poput <= pput(SOLVERS);
-- Connect Result Chain
svld(0) <= sivld;
sdat(0) <= sidat;
seof(0) <= sieof;
sigot <= sgot(0);
sovld <= svld(SOLVERS);
sodat <= sdat(SOLVERS);
soeof <= seof(SOLVERS);
sgot(SOLVERS) <= sogot;
-- Linear Solver Chain
-- Input @index i
-- Output @index i+1
genSolvers: for i in 0 to SOLVERS-1 generate
-- Widened Tap for this Stage
signal tful : std_logic;
signal tput : std_logic;
signal tdat : std_logic_vector(8*PRE_BYTES-1 downto 0);
-- Decoded Pre-Placement
signal bh, bv : std_logic_vector(L to N-L-1);
signal bu, bd : std_logic_vector(0 to 2*N-4*L-2);
-- Solver Strobes
signal sol, done : std_logic;
-- Computation State
signal Act : std_logic := '0';
signal Vld : std_logic := '0';
-- Result Buffer
constant BUF_LEN : positive := ite(COUNT_CYCLES, 48, 0) + 8*PRE_BYTES + 52;
signal Buf : unsigned(BUF_LEN-1 downto 0) := (others => '-');
signal Cnt : unsigned(log2ceil((BUF_LEN+7)/8-1) downto 0) := (others => '-');
alias Cycles : unsigned(47 downto 0) is Buf(BUF_LEN-1 downto BUF_LEN-48);
alias Pre : unsigned(8*PRE_BYTES-1 downto 0) is Buf(8*PRE_BYTES+51 downto 52);
alias Sols13 : unsigned( 3 downto 0) is Buf(51 downto 48);
alias Sols15 : unsigned( 3 downto 0) is Buf(47 downto 44);
alias Sols : unsigned(43 downto 0) is Buf(43 downto 0);
-- Streamed Stage Result
signal rvld : std_logic;
signal rdat : byte;
signal reof : std_logic;
signal rgot : std_logic;
begin
-- Input Tap
tap: entity work.msg_tap
generic map (
D => PRE_BYTES
)
port map (
clk => clk,
rst => rst,
iful => pful(i),
idat => pdat(i),
ieof => peof(i),
iput => pput(i),
oful => pful(i+1),
odat => pdat(i+1),
oeof => peof(i+1),
oput => pput(i+1),
tful => tful,
tdat => tdat,
tput => tput
);
-- Pre-Placement Expansion
expander: entity work.expand_blocking
generic map (
N => N,
L => L
)
port map (
pre => tdat(PRE_BITS-1 downto 0),
bh => bh,
bv => bv,
bu => bu,
bd => bd
);
-- Solver Slice
slice: entity work.queens_slice
generic map (
N => N,
L => L
)
port map (
clk => clk,
rst => rst,
start => tput,
BH_l => bh,
BU_l => bu,
BD_l => bd,
BV_l => bv,
sol => sol,
done => done
);
-- Computation Control
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Act <= '0';
Vld <= '0';
Cnt <= (others => '-');
Buf <= (others => '-');
else
if tput = '1' then
-- Start
Act <= '1';
Buf <= (others => '-');
if COUNT_CYCLES then
Cycles <= (others => '0');
end if;
Pre <= unsigned(tdat);
Sols <= (others => '0');
Sols13 <= (others => '0');
Sols15 <= (others => '0');
else
-- Counting Cycles
if COUNT_CYCLES and Act = '1' and Vld = '0' then
Cycles <= Cycles + 1;
end if;
-- Counting Solutions
if sol = '1' then
Sols <= Sols + 1;
Sols13 <= Sols13 - ("11" & (1 downto 0 => (not(Sols13(3) and Sols13(2)))));
Sols15 <= Sols15 - ("111" & (not(Sols15(3) and Sols15(2) and Sols15(1))));
end if;
-- Result Output
if done = '1' then
Vld <= '1';
Cnt <= to_unsigned((BUF_LEN+7)/8-2, Cnt'length);
end if;
if rgot = '1' then
Buf <= Buf(Buf'left-8 downto 0) & (1 to 8 => '-');
Cnt <= Cnt - 1;
if Cnt(Cnt'left) = '1' then
Act <= '0';
Vld <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
tful <= Act;
rvld <= Vld;
rdat <= byte(Buf(Buf'left downto Buf'left-7));
reof <= Cnt(Cnt'left);
-- Connect Result Stream
blkFunnel: block
-- Funnel-to-FIFO Interface
signal f2f_ful : std_logic;
signal f2f_dat : std_logic_vector(8 downto 0);
signal f2f_put : std_logic;
begin
-- Merge local Output with Result Stream
funnel: entity work.msg_funnel
generic map (
N => 2
)
port map (
clk => clk,
rst => rst,
ivld(0) => rvld,
ivld(1) => svld(i),
idat(0) => rdat,
idat(1) => sdat(i),
ieof(0) => reof,
ieof(1) => seof(i),
igot(0) => rgot,
igot(1) => sgot(i),
oful => f2f_ful,
odat => f2f_dat(7 downto 0),
oeof => f2f_dat(8),
oput => f2f_put
);
-- Stage Output through FIFO
glue : fifo_glue
generic map (
D_BITS => 9
)
port map (
clk => clk,
rst => rst,
ful => f2f_ful,
di => f2f_dat,
put => f2f_put,
vld => svld(i+1),
do(7 downto 0) => sdat(i+1),
do(8) => seof(i+1),
got => sgot(i+1)
);
end block blkFunnel;
end generate genSolvers;
end rtl;
| agpl-3.0 |
preusser/q27 | src/vhdl/PoC/uart/uart_tx.vhdl | 3 | 2785 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module:
--
-- Authors: Thomas B. Preusser
--
-- Description: UART (RS232) Transmitter: 1 Start + 8 Data + 1 Stop
-- ------------
--
-- License:
-- ===========================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity uart_tx is
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Bit Clock and TX Line
bclk : in std_logic; -- bit clock, one strobe each bit length
tx : out std_logic;
-- Byte Stream Input
di : in std_logic_vector(7 downto 0);
put : in std_logic;
ful : out std_logic
);
end entity;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of uart_tx is
-- Buf Cnt
-- Idle "---------1" "0----"
-- Start "hgfedcba01" -10
-- Send "1111hgfedc" -10 -> -1
-- Done "1111111111" 0
signal Buf : std_logic_vector(9 downto 0) := (0 => '1', others => '-');
signal Cnt : signed(4 downto 0) := "0----";
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (0 => '1', others => '-');
Cnt <= "0----";
else
if Cnt(Cnt'left) = '0' then
-- Idle
if put = '1' then
-- Start Transmission
Buf <= di & "01";
Cnt <= to_signed(-10, Cnt'length);
else
Buf <= (0 => '1', others => '-');
Cnt <= "0----";
end if;
else
-- Transmitting
if bclk = '1' then
Buf <= '1' & Buf(Buf'left downto 1);
Cnt <= Cnt + 1;
end if;
end if;
end if;
end if;
end process;
tx <= Buf(0);
ful <= Cnt(Cnt'left);
end;
| agpl-3.0 |
preusser/q27 | src/vhdl/top/xilinx/ml605_queens_uart.vhdl | 1 | 4783 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity ml605_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 127;
COUNT_CYCLES : boolean := false;
CLK_FREQ : FREQ := 200 MHz;
CLK_MULA : positive := 6;
CLK_DIVA : positive := 1;
CLK_DIVB : positive := 7;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clk_p : in std_logic;
clk_n : in std_logic;
rx : in std_logic;
tx : out std_logic;
rts_n : in std_logic;
cts_n : out std_logic;
FanControl_PWM : out std_logic
);
end ml605_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library PoC;
architecture rtl of ml605_queens_uart is
-- Global Control
constant CLK_COMP_FREQ : FREQ := CLK_FREQ * CLK_MULA / CLK_DIVA / CLK_DIVB;
constant CLK_SLOW_FREQ : FREQ := CLK_FREQ * CLK_MULA / CLK_DIVA / 100;
signal clk200 : std_logic; -- 200 MHz Input Clock
signal clk_comp : std_logic; -- Computation Clock
signal clk_slow : std_logic; -- Slow Interface Clock
signal rst : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clkfb : std_logic; -- Feedback Clock
signal clk_compu : std_logic; -- Unbuffered Synthesized Clock
signal clk_slowu : std_logic; -- Unbuffered Synthesized Clock
begin
clk_in : IBUFGDS
port map(
O => clk200,
I => clk_p,
IB => clk_n
);
pll : MMCM_BASE
generic map (
CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns),
CLKFBOUT_MULT_F => real(CLK_MULA),
DIVCLK_DIVIDE => CLK_DIVA,
CLKOUT0_DIVIDE_F => real(CLK_DIVB),
CLKOUT1_DIVIDE => 100,
STARTUP_WAIT => false
)
port map (
CLKIN1 => clk200,
CLKFBIN => clkfb,
RST => '0',
CLKOUT0 => clk_compu,
CLKOUT1 => clk_slowu,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => clkfb,
LOCKED => open,
PWRDWN => '0'
);
comp_buf : BUFG
port map (
I => clk_compu,
O => clk_comp
);
slow_buf : BUFH
port map (
I => clk_slowu,
O => clk_slow
);
-- No Reset
rst <= '0';
end block blkGlobal;
-----------------------------------------------------------------------------
-- Fan Control
fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => CLK_SLOW_FREQ
)
port map (
Clock => clk_slow,
Reset => '0',
Fan_PWM => FanControl_PWM,
TachoFrequency => open
);
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer(to_real(CLK_COMP_FREQ, 1 Hz)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk_comp,
rst => rst,
rx => rx,
tx => tx,
avail => open
);
cts_n <= rts_n;
end rtl;
| agpl-3.0 |
preusser/q27 | src/vhdl/PoC/fifo/fifo.pkg.vhdl | 2 | 9509 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.fifo namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use PoC.utils.all;
package fifo is
-- Minimal FIFO with single clock to decouple enable domains.
component fifo_glue
generic (
D_BITS : positive -- Data Width
);
port (
-- Control
clk : in std_logic; -- Clock
rst : in std_logic; -- Synchronous Reset
-- Input
put : in std_logic; -- Put Value
di : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input
ful : out std_logic; -- Full
-- Output
vld : out std_logic; -- Data Available
do : out std_logic_vector(D_BITS - 1 downto 0); -- Data Output
got : in std_logic -- Data Consumed
);
end component;
-- Minimal Local-Link-FIFO with single clock and first-word-fall-through mode.
component fifo_ll_glue
generic (
D_BITS : positive;
FRAME_USER_BITS : natural;
REGISTER_PATH : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
-- in port
sof_in : in std_logic;
data_in : in std_logic_vector(D_BITS downto 1);
frame_data_in : in std_logic_vector(imax(1, FRAME_USER_BITS) downto 1);
eof_in : in std_logic;
src_rdy_in : in std_logic;
dst_rdy_in : out std_logic;
-- out port
sof_out : out std_logic;
data_out : out std_logic_vector(D_BITS downto 1);
frame_data_out : out std_logic_vector(imax(1, FRAME_USER_BITS) downto 1);
eof_out : out std_logic;
src_rdy_out : out std_logic;
dst_rdy_out : in std_logic
);
end component;
-- Simple FIFO backed by a shift register.
component fifo_shift
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive -- Minimum FIFO Size in Words
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
ful : out std_logic; -- Capacity Exhausted
-- Reading Interface
got : in std_logic; -- Read Done Strobe
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
vld : out std_logic -- Data Valid
);
end component;
-- Full-fledged FIFO with single clock domain using on-chip RAM.
component fifo_cc_got
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
);
end component;
component fifo_dc_got_sm
generic (
D_BITS : positive;
MIN_DEPTH : positive);
port (
clk_wr : in std_logic;
rst_wr : in std_logic;
put : in std_logic;
din : in std_logic_vector(D_BITS - 1 downto 0);
full : out std_logic;
clk_rd : in std_logic;
rst_rd : in std_logic;
got : in std_logic;
valid : out std_logic;
dout : out std_logic_vector(D_BITS - 1 downto 0));
end component;
component fifo_ic_got
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Write Interface
clk_wr : in std_logic;
rst_wr : in std_logic;
put : in std_logic;
din : in std_logic_vector(D_BITS - 1 downto 0);
full : out std_logic;
estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS - 1, 0) downto 0);
-- Read Interface
clk_rd : in std_logic;
rst_rd : in std_logic;
got : in std_logic;
valid : out std_logic;
dout : out std_logic_vector(D_BITS - 1 downto 0);
fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS - 1, 0) downto 0)
);
end component;
component fifo_cc_got_tempput
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
commit : in std_logic;
rollback : in std_logic;
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
);
end component;
component fifo_cc_got_tempgot is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0);
commit : in std_logic;
rollback : in std_logic
);
end component;
end fifo;
package body fifo is
end fifo;
| agpl-3.0 |
preusser/q27 | src/vhdl/queens/msg_funnel.vhdl | 2 | 4246 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
entity msg_funnel is
generic (
N : positive -- Number of Funnel Inputs
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Funnel Inputs
ivld : in std_logic_vector(0 to N-1);
idat : in byte_vector(0 to N-1);
ieof : in std_logic_vector(0 to N-1);
igot : out std_logic_vector(0 to N-1);
-- Funnel Output
oful : in std_logic;
odat : out byte;
oeof : out std_logic;
oput : out std_logic
);
end msg_funnel;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of msg_funnel is
component arbit_forward
generic (
N : positive -- Length of Token Chain
);
port (
tin : in std_logic; -- Fed Token
have : in std_logic_vector(0 to N-1); -- Token Owner
pass : in std_logic_vector(0 to N-1); -- Token Passers
grnt : out std_logic_vector(0 to N-1); -- Token Output
tout : out std_logic -- Unused Token
);
end component;
signal Active : std_logic := '0';
signal SelBin : unsigned(log2ceil(N)-1 downto 0) := (others => '-');
signal grnt : std_logic_vector(0 to N-1);
signal tout : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Active <= '0';
SelBin <= (others => '-');
else
if oful = '0' then
if Active = '0' then
if tout = '0' then
for i in 0 to N-1 loop
if grnt(i) = '1' then
SelBin <= to_unsigned(i, SelBin'length);
end if;
end loop;
Active <= '1';
end if;
else
if ivld(to_integer(SelBin)) = '1' and ieof(to_integer(SelBin)) = '1' then
SelBin <= (others => '-');
Active <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
odat <= (others => 'X') when Is_X(std_logic_vector(SelBin)) else idat(to_integer(SelBin));
oeof <= 'X' when Is_X(std_logic_vector(SelBin)) else ieof(to_integer(SelBin));
genGots: for i in 0 to N-1 generate
igot(i) <= '0' when Active = '0' else
'0' when oful = '1' else
'X' when Is_X(std_logic_vector(SelBin)) else
'0' when SelBin /= to_unsigned(i, SelBin'length) else
ivld(i);
end generate genGots;
oput <= Active and ivld(to_integer(SelBin)) and not oful;
-- Arbitration
blkArbit: block is
signal pass : std_logic_vector(0 to N-1);
begin
pass <= not ivld;
arbit : arbit_forward
generic map (
N => N
)
port map (
tin => '1',
have => (others => '0'),
pass => pass,
grnt => grnt,
tout => tout
);
end block;
end rtl;
| agpl-3.0 |
BBN-Q/APS2-Comms | src/tcp_demux.vhd | 1 | 5203 | -- Cross from tcp clock domain
-- Demux tcp stream between AXI memory and CPLD
-- Packetize by adding tlast to stream
-- Adapt to 32bit wide data path
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tcp_bridge_pkg.all;
entity tcp_demux is
port (
clk : in std_logic;
rst : in std_logic;
clk_tcp : in std_logic;
rst_tcp : in std_logic;
--TCP stream receive
tcp_rx_tdata : in std_logic_vector(7 downto 0);
tcp_rx_tvalid : in std_logic;
tcp_rx_tready : out std_logic;
--rx stream passed to memory
memory_rx_tdata : out std_logic_vector(31 downto 0);
memory_rx_tvalid : out std_logic;
memory_rx_tready : in std_logic;
memory_rx_tlast : out std_logic;
--rx stream passed to CPLD bridge
cpld_rx_tdata : out std_logic_vector(31 downto 0);
cpld_rx_tvalid : out std_logic;
cpld_rx_tready : in std_logic;
cpld_rx_tlast : out std_logic
);
end entity;
architecture arch of tcp_demux is
signal tcp_rx_long_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_long_tvalid, tcp_rx_long_tready : std_logic := '0';
signal tcp_rx_long_cc_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_long_cc_tvalid, tcp_rx_long_cc_tready : std_logic := '0';
signal demux_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal demux_tvalid, demux_tlast, demux_tready : std_logic := '0';
type main_state_t is (IDLE, LATCH_COMMAND, COUNT_PACKET);
signal main_state : main_state_t := IDLE;
signal cmd : std_logic_vector(31 downto 0);
alias cmd_rw_bit : std_logic is cmd(28);
alias cmd_cpld_bit : std_logic is cmd(29);
alias cmd_length : std_logic_vector(15 downto 0) is cmd(15 downto 0);
signal word_ct : unsigned(16 downto 0);
begin
--Adapt up to 32 bit wide data path
axis_adapter_inst : axis_adapter
generic map (
INPUT_DATA_WIDTH => 8,
INPUT_KEEP_WIDTH => 1,
OUTPUT_DATA_WIDTH => 32,
OUTPUT_KEEP_WIDTH => 4
)
port map (
clk => clk_tcp,
rst => rst_tcp,
input_axis_tdata => tcp_rx_tdata,
input_axis_tkeep(0) => '1',
input_axis_tvalid => tcp_rx_tvalid,
input_axis_tready => tcp_rx_tready,
input_axis_tlast => '0',
input_axis_tuser => '0',
output_axis_tdata => tcp_rx_long_tdata,
output_axis_tkeep => open,
output_axis_tvalid => tcp_rx_long_tvalid,
output_axis_tready => tcp_rx_long_tready,
output_axis_tlast => open,
output_axis_tuser => open
);
--Cross from the tcp clock domain
tcp2axi_fifo_inst : axis_async_fifo
generic map (
ADDR_WIDTH => 5,
DATA_WIDTH => 32
)
port map (
async_rst => rst,
input_clk => clk_tcp,
input_axis_tdata => byte_swap(tcp_rx_long_tdata),
input_axis_tvalid => tcp_rx_long_tvalid,
input_axis_tready => tcp_rx_long_tready,
input_axis_tlast => '0',
input_axis_tuser => '0',
output_clk => clk,
output_axis_tdata => tcp_rx_long_cc_tdata,
output_axis_tvalid => tcp_rx_long_cc_tvalid,
output_axis_tready => tcp_rx_long_cc_tready,
output_axis_tlast => open,
output_axis_tuser => open
);
--Main decision loop
main : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
main_state <= IDLE;
word_ct <= (others => '0');
cmd <= (others => '0');
else
case( main_state ) is
when IDLE =>
cmd <= tcp_rx_long_cc_tdata;
--Wait for valid to announce start of packet
if tcp_rx_long_cc_tvalid = '1' then
main_state <= LATCH_COMMAND;
end if;
when LATCH_COMMAND =>
main_state <= COUNT_PACKET;
--For reads only have command and address so mask out word_ct
--normally - 2 for zero indexed and roll-over but count cmd and address
--TODO: change to when/else when I get VHDL 2008 working
if cmd_rw_bit = '0' then
word_ct <= resize(unsigned(cmd_length),17);
else
word_ct <= (others => '0');
end if;
when COUNT_PACKET =>
if demux_tvalid = '1' and demux_tready = '1' then
if word_ct(word_ct'high) = '1' then
main_state <= IDLE;
end if;
word_ct <= word_ct - 1;
end if;
end case;
end if;
end if;
end process;
--Combinational AXI stream signals
demux_tdata <= tcp_rx_long_cc_tdata;
demux_tvalid <= tcp_rx_long_cc_tvalid when main_state = COUNT_PACKET else '0';
tcp_rx_long_cc_tready <= demux_tready when main_state = COUNT_PACKET else '0';
demux_tlast <= demux_tvalid when main_state = COUNT_PACKET and word_ct(word_ct'high) = '1' else '0';
--Demux between memory and CPLD
memory_cpld_demux : axis_demux_2
generic map ( DATA_WIDTH => 32)
port map (
clk => clk,
rst => rst,
input_axis_tdata => demux_tdata,
input_axis_tvalid => demux_tvalid,
input_axis_tready => demux_tready,
input_axis_tlast => demux_tlast,
input_axis_tuser => '0',
output_0_axis_tdata => memory_rx_tdata,
output_0_axis_tvalid => memory_rx_tvalid,
output_0_axis_tready => memory_rx_tready,
output_0_axis_tlast => memory_rx_tlast,
output_0_axis_tuser => open,
output_1_axis_tdata => cpld_rx_tdata,
output_1_axis_tvalid => cpld_rx_tvalid,
output_1_axis_tready => cpld_rx_tready,
output_1_axis_tlast => cpld_rx_tlast,
output_1_axis_tuser => open,
enable => '1',
control(0) => cmd_cpld_bit
);
end architecture;
| mpl-2.0 |
sils1297/HWPrak14 | task_2/project_2/project_2.srcs/sim_1/new/LEDPWM_tb.vhd | 1 | 476 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LEDPWM_tb is
end LEDPWM_tb;
architecture Behavioral of LEDPWM_tb is
signal led : std_ulogic_vector(3 downto 0);
signal clock : std_ulogic := '0';
begin
uut : entity work.Dimmer(DimmerArchitecture)
generic map (WIDTH => 25)
port map (
LED => led,
CLK_66MHZ => clock
);
clock <= not clock after 7.57575757 ns;
stimuli : process
begin
wait for 5 sec;
end process;
end Behavioral;
| agpl-3.0 |
sils1297/HWPrak14 | task_1/task_1.srcs/sim_1/new/FlasherTestBench.vhd | 1 | 529 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FlasherTestBench is
end FlasherTestBench;
architecture Behavioral of FlasherTestBench is
signal led : std_ulogic_vector(3 downto 0);
signal clock : std_ulogic := '0';
begin
uut : entity work.Flasher(FlasherArchitecture)
generic map (WIDTH => 6)
port map (
LED => led,
CLK_66MHZ => clock
);
clock <= not clock after 7.57575757 ns;
stimuli : process
variable lastledstate : std_ulogic_vector(3 downto 0);
begin
wait for 5 sec;
end process;
end Behavioral;
| agpl-3.0 |
BBN-Q/APS2-Comms | test/eprom_cfg_reader_tb.vhd | 1 | 6247 | -- Testbench for the eprom_cfg_reader
-- Tests:
-- * default values until done
-- * request sent
-- * response processed and addresses set
-- * done asserted
-- * AXIS pass through after done asserted
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eprom_cfg_reader_tb is
end;
architecture bench of eprom_cfg_reader_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rx_in_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal rx_in_tvalid : std_logic := '0';
signal rx_in_tready : std_logic := '0';
signal rx_in_tlast : std_logic := '0';
signal rx_out_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal rx_out_tvalid : std_logic := '0';
signal rx_out_tlast : std_logic := '0';
signal rx_out_tready : std_logic := '0';
signal tx_in_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal tx_in_tvalid : std_logic := '0';
signal tx_in_tready : std_logic := '0';
signal tx_in_tlast : std_logic := '0';
signal tx_out_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal tx_out_tvalid : std_logic := '0';
signal tx_out_tlast : std_logic := '0';
signal tx_out_tready : std_logic := '0';
signal mac_addr : std_logic_vector(47 downto 0) := (others => '0');
signal ip_addr : std_logic_vector(31 downto 0) := (others => '0');
signal dhcp_enable : std_logic := '0';
signal done : std_logic := '0';
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean := false;
type TestBenchState_t is (RESET, WAIT_FOR_READ_REQ, FLASH_READ_DELAY, SEND_READ_RESPONSE, WAIT_FOR_DONE, RX_PASS_THROUGH, TX_PASS_THROUGH, FINISHED);
signal testBench_state : TestBenchState_t;
type array_slv32 is array(natural range <>) of std_logic_vector(31 downto 0);
constant FLASH_DATA : array_slv32 := (x"92000004", x"4651db00", x"002e0000", x"c0a80202", x"00000001");
begin
uut: entity work.eprom_cfg_reader
port map (
clk => clk,
rst => rst,
rx_in_tdata => rx_in_tdata,
rx_in_tvalid => rx_in_tvalid,
rx_in_tready => rx_in_tready,
rx_in_tlast => rx_in_tlast,
rx_out_tdata => rx_out_tdata,
rx_out_tvalid => rx_out_tvalid,
rx_out_tlast => rx_out_tlast,
rx_out_tready => rx_out_tready,
tx_in_tdata => tx_in_tdata,
tx_in_tvalid => tx_in_tvalid,
tx_in_tready => tx_in_tready,
tx_in_tlast => tx_in_tlast,
tx_out_tdata => tx_out_tdata,
tx_out_tvalid => tx_out_tvalid,
tx_out_tlast => tx_out_tlast,
tx_out_tready => tx_out_tready,
ip_addr => ip_addr,
mac_addr => mac_addr,
dhcp_enable => dhcp_enable,
done => done
);
clk <= not clk after clock_period / 2 when not stop_the_clock;
stimulus: process
begin
wait until rising_edge(clk);
--Reset
testBench_state <= RESET;
rst <= '1';
wait for 100ns;
rst <= '0';
wait for 100ns;
--Wait for read request to come out
testBench_state <= WAIT_FOR_READ_REQ;
rx_out_tready <= '1';
wait until rising_edge(clk) and rx_out_tlast = '1' for 100 ns;
--flash read delay (probably much longer)
testBench_state <= FLASH_READ_DELAY;
wait for 1 us;
--send back data
testBench_state <= SEND_READ_RESPONSE;
for ct in 0 to FLASH_DATA'high loop
wait until rising_edge(clk) and tx_in_tready = '1';
tx_in_tdata <= FLASH_DATA(ct);
tx_in_tvalid <= '1';
if ct = FLASH_DATA'high then
tx_in_tlast <= '1';
else
tx_in_tlast <= '0';
end if;
for ct2 in 0 to 2 loop
wait until rising_edge(clk);
tx_in_tdata <= (others => '0');
tx_in_tvalid <= '0';
tx_in_tlast <= '0';
end loop;
end loop;
--wait for done
wait until done = '1' for 100 ns;
assert done = '1' report "Done failed to assert";
--Test pass through an rx side
testBench_state <= RX_PASS_THROUGH;
rx_out_tready <= '0';
wait until rising_edge(clk);
assert rx_in_tready = '0' report "rx tready pass through failed";
rx_in_tvalid <= '1';
wait until rising_edge(clk);
assert rx_out_tvalid = '1' report "rx tvalid pass through failed";
rx_in_tlast <= '1';
wait until rising_edge(clk);
assert rx_out_tlast = '1' report "rx tlast pass through failed";
rx_in_tdata <= x"12345678";
wait until rising_edge(clk);
assert rx_out_tdata = x"12345678" report "rx tdata pass through failed";
--Test pass through an rx side
testBench_state <= TX_PASS_THROUGH;
tx_out_tready <= '1';
wait until rising_edge(clk);
assert tx_in_tready = '1' report "tx tready pass through failed";
tx_in_tvalid <= '1';
wait until rising_edge(clk);
assert tx_out_tvalid = '1' report "tx tvalid pass through failed";
tx_in_tlast <= '1';
wait until rising_edge(clk);
assert tx_out_tlast = '1' report "tx tlast pass through failed";
tx_in_tdata <= x"12345678";
wait until rising_edge(clk);
assert tx_out_tdata = x"12345678" report "tx tdata pass through failed";
stop_the_clock <= true;
end process;
checking: process
begin
--Check defaults are set
wait until falling_edge(rst);
wait for 10 ns;
assert mac_addr = x"4651dbbada55" report "Incorrect default MAC address";
assert ip_addr = x"c0a8027b" report "Incorrect default IP address";
assert dhcp_enable = '0' report "incorrect default DHCP bit";
--check read request is sent
wait until rising_edge(clk) and rx_out_tvalid = '1' and rx_out_tready = '1';
assert rx_out_tdata = x"12000004" report "Read command incorrect";
assert rx_out_tlast = '0' report "Read tlast incorrect";
wait until rising_edge(clk) and rx_out_tvalid = '1';
assert rx_out_tdata = x"00FF0000" report "Read address incorrect";
assert rx_out_tlast = '1' report "Read tlast incorrect";
wait until done = '1' for 2 us;
--check updated addresses
assert mac_addr = x"4651db00002e" report "Incorrect MAC address";
assert ip_addr = x"c0a80202" report "Incorrect IP address";
assert dhcp_enable = '1' report "incorrect DHCP bit";
end process;
end;
| mpl-2.0 |
sils1297/HWPrak14 | task_1/task_1.srcs/sources_1/new/Flasher.vhd | 1 | 719 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Toggles the LED state every half second
entity Flasher is
generic (
WIDTH : integer := 25
);
port (
LED : out std_ulogic_vector(3 downto 0);
CLK_66MHZ : in std_ulogic
);
end;
architecture FlasherArchitecture of Flasher is
signal counter : unsigned(WIDTH downto 0) := (others => '0'); -- that makes 67108864 bit combinations
begin
LED(0) <= counter(WIDTH);
LED(1) <= counter(WIDTH);
LED(2) <= counter(WIDTH);
LED(3) <= counter(WIDTH); -- toggle LED together with the upper most bit
counterProcess : process(CLK_66MHZ)
begin
if(rising_edge(CLK_66MHZ)) then
counter <= counter + 1;
end if;
end process;
end FlasherArchitecture;
| agpl-3.0 |
sils1297/HWPrak14 | task_3/task_3.srcs/sources_1/new/i2c.vhd | 1 | 11526 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchronous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
--report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural; | agpl-3.0 |
BBN-Q/APS2-TDM | src/TDM_top.vhd | 1 | 20095 | -- TDM_top.vhd
--
-- This is the top level module of the ATM firmware.
-- It instantiates the main BD with the comms., 9 SATA outputs, and one SATA input.
-- Original authors: Colm Ryan and Blake Johnson
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.all;
entity TDM_top is
generic (
TDM_VERSION : std_logic_vector(31 downto 0) := x"0000_0000"; -- bits 31-28 = d for dirty; bits 27-16 commits since; bits 15-8 version major; bits 7-0 version minor;
GIT_SHA1 : std_logic_vector(31 downto 0) := x"0000_0000"; -- git SHA1 of HEAD;
BUILD_TIMESTAMP : std_logic_vector(31 downto 0) := x"0000_0000" -- 32h'YYMMDDHH as hex string e.g. 16032108 for 2016-March-21 8am
);
port
(
ref_fpga : in std_logic; -- Global 10MHz reference
fpga_resetl : in std_logic; -- Global reset from config FPGA
-- Temp Diode Pins
vp : in std_logic;
vn : in std_logic;
-- Config Bus Connections
cfg_clk : in std_logic; -- 100 MHZ clock from the Config CPLD
cfgd : inout std_logic_vector(15 downto 0); -- Config Data bus from CPLD
fpga_cmdl : out std_logic; -- Command strobe from FPGA
fpga_rdyl : out std_logic; -- Ready Strobe from FPGA
cfg_rdy : in std_logic; -- Ready to complete current transfer. Connected to CFG_RDWR_B
cfg_err : in std_logic; -- Error during current command. Connecte to CFG_CSI_B
cfg_act : in std_logic; -- Current transaction is complete
stat_oel : out std_logic; -- Enable CPLD to drive status onto CFGD
-- SFP Tranceiver Interface
sfp_mgt_clkp : in std_logic; -- 125 MHz reference
sfp_mgt_clkn : in std_logic;
sfp_txp : out std_logic; -- TX out to SFP
sfp_txn : out std_logic;
sfp_rxp : in std_logic; -- RX in from SPF
sfp_rxn : in std_logic;
-- SFP control signals
sfp_enh : buffer std_logic; -- sfp enable high
sfp_scl : out std_logic; -- sfp serial clock - unused
sfp_txdis : buffer std_logic; -- sfp disable laser
sfp_sda : in std_logic; -- sfp serial data - unused
sfp_fault : in std_logic; -- sfp tx fault -unused
sfp_los : in std_logic; -- sfp loss of signal input laser power too low; also goes high when ethernet jack disconnected; low when plugged in -unused
sfp_presl : in std_logic; -- sfp present low ??? doesn't seem to be in spec.
-- External trigger comparator related signals
trg_cmpn : in std_logic_vector(7 downto 0);
trg_cmpp : in std_logic_vector(7 downto 0);
thr : out std_logic_vector(7 downto 0);
-- Trigger Outputs
trgclk_outn : out std_logic_vector(8 downto 0);
trgclk_outp : out std_logic_vector(8 downto 0);
trgdat_outn : out std_logic_vector(8 downto 0);
trgdat_outp : out std_logic_vector(8 downto 0);
-- Trigger input
trig_ctrln : in std_logic_vector(1 downto 0);
trig_ctrlp : in std_logic_vector(1 downto 0);
-- Internal Status LEDs
led : out std_logic_vector(9 downto 0);
-- Debug LEDs / configuration jumpers
dbg : inout std_logic_vector(8 downto 0)
);
end TDM_top;
architecture behavior of TDM_top is
--- Constants ---
constant SUBNET_MASK : std_logic_vector(31 downto 0) := x"ffffff00"; -- 255.255.255.0
constant TCP_PORT : std_logic_vector(15 downto 0) := x"bb4e"; -- BBN
constant UDP_PORT : std_logic_vector(15 downto 0) := x"bb4f"; -- BBN + 1
constant GATEWAY_IP_ADDR : std_logic_vector(31 downto 0) := x"c0a80201"; -- TODO: what this should be?
constant PCS_PMA_AN_ADV_CONFIG_VECTOR : std_logic_vector(15 downto 0) := x"0020"; --full-duplex see Table 2-55 (pg. 74) of PG047 November 18, 2015
constant PCS_PMA_CONFIGURATION_VECTOR : std_logic_vector(4 downto 0) := b"10000"; --auto-negotiation enabled see Table 2-54 (pg. 73) of PG047 November 18, 2015
--- clocks
signal clk_100, clk_100_skewed, clk_100_axi, clk_125, clk_200, clk_400,
ref_125 : std_logic;
signal cfg_clk_mmcm_locked : std_logic;
signal ref_locked : std_logic;
signal ref_locked_s : std_logic;
signal ref_locked_d : std_logic;
signal sys_clk_mmcm_locked : std_logic;
-- Resets
signal rst_comm_stack, rst_cfg_reader, rst_comblock,
rst_cpld_bridge, rst_eth_mac, rst_pcs_pma, rst_tcp_bridge,
rst_udp_responder, rstn_axi,
rst_sync_clk125, rst_sync_clk100, rst_sync_clk_100_axi,
rst_sata : std_logic := '0';
signal cfg_reader_done : std_logic;
--SFP
signal mgt_clk_locked : std_logic;
signal pcs_pma_status_vector : std_logic_vector(15 downto 0);
alias link_established : std_logic is pcs_pma_status_vector(0);
signal pcs_pma_an_restart_config : std_logic;
signal ExtTrig : std_logic_vector(7 downto 0);
signal sys_clk_mmcm_reset : std_logic := '0';
-- Trigger signals
type BYTE_ARRAY is array (0 to 8) of std_logic_vector(7 downto 0);
signal TrigOutDat : BYTE_ARRAY;
signal TrigWr : std_logic_vector(8 downto 0);
signal TrigInDat : std_logic_vector(7 downto 0);
signal TrigClkErr : std_logic;
signal TrigOvflErr : std_logic;
signal TrigLocked : std_logic;
signal TrigInReady : std_logic;
signal TrigInRd : std_logic;
signal TrigFull : std_logic;
signal ext_valid : std_logic;
signal ext_valid_d : std_logic;
signal ext_valid_re : std_logic;
signal CMP : std_logic_vector(7 downto 0);
-- etherenet comms status
signal comms_active : std_logic;
signal ethernet_mm2s_err, ethernet_s2mm_err : std_logic;
-- CSR registers
signal status, control, resets, SATA_status, uptime_seconds, uptime_nanoseconds,
trigger_interval, latched_trig_word : std_logic_vector(31 downto 0) := (others => '0');
alias trigger_enabled : std_logic is control(4);
alias soft_trig_toggle : std_logic is control(3);
alias trigger_source : std_logic_vector(1 downto 0) is control(2 downto 1);
signal trigger : std_logic;
begin
------------------------- clocking ------------------------------------------
sync_reflocked : entity work.synchronizer
port map ( rst => not(fpga_resetl), clk => clk_125, data_in => ref_locked, data_out => ref_locked_s );
-- need to reset SYS_MMCM on rising or falling edge of RefLocked
sys_mmcm_reset : process( mgt_clk_locked, clk_125 )
begin
if mgt_clk_locked = '0' then
sys_clk_mmcm_reset <= '1';
elsif rising_edge(clk_125) then
ref_locked_d <= ref_locked_s;
if (ref_locked_d xor ref_locked_s) = '1' then
sys_clk_mmcm_reset <= '1';
else
sys_clk_mmcm_reset <= '0';
end if;
end if;
end process ; -- sys_mmcm_reset
-- multiply reference clock up to 125 MHz
ref_mmmc_inst : entity work.REF_MMCM
port map (
CLK_REF => ref_fpga,
-- clock out ports
CLK_100MHZ => ref_125,
-- status and control signals
RESET => not fpga_resetl,
LOCKED => ref_locked
);
-- Create aligned 100 and 400 MHz clocks for SATA in/out logic
-- from either the 10 MHz reference or the 125 MHz sfp clock
sys_mmcm_inst : entity work.SYS_MMCM
port map
(
-- Clock in ports
REF_125MHZ_IN => ref_125,
CLK_125MHZ_IN => clk_125,
CLK_IN_SEL => ref_locked, -- choose ref_125 when HIGH
-- Clock out ports
CLK_100MHZ => clk_100,
CLK_400MHZ => clk_400,
-- Status and control signals
RESET => sys_clk_mmcm_reset,
LOCKED => sys_clk_mmcm_locked
);
-- create a skewed copy of the cfg_clk to meet bus timing
-- create a 100MHz clock for AXI
-- create a 200 MHz IODELAY reference calibration
cfg_clk_mmcm_inst : entity work.CCLK_MMCM
port map (
clk_100MHZ_in => cfg_clk,
clk_100MHZ_skewed => clk_100_skewed,
clk_100MHZ => clk_100_axi,
clk_200MHZ => clk_200,
reset => not fpga_resetl,
locked => cfg_clk_mmcm_locked
);
-- wire out status register bits
status(0) <= mgt_clk_locked; --if low we probably won't be able to read anyways
status(1) <= cfg_clk_mmcm_locked; --if low we probably won't be able to read anyways
status(2) <= ref_locked;
status(3) <= sys_clk_mmcm_locked;
status(4) <= sys_clk_mmcm_reset;
-------------------- SFP -------------------------------------------------------
-- force use of usused pins
sfp_scl <= '1' when
(fpga_resetl = '0' and (sfp_sda and sfp_fault and sfp_los and sfp_presl) = '1')
else '0';
-- reset SFP module for at least 100 ms when FPGA is reprogrammed or fpga_resetl is asserted
sfp_reset_pro : process(clk_125, mgt_clk_locked, sfp_presl)
variable reset_ct : unsigned(24 downto 0) := (others => '0');
begin
if mgt_clk_locked = '0' or sfp_presl = '1' then
reset_ct := to_unsigned(12_500_000, reset_ct'length); --100ms at 125MHz ignoring off-by-one issues
sfp_enh <= '0';
sfp_txdis <= '1';
elsif rising_edge(clk_125) then
if reset_ct(reset_ct'high) = '1' then
sfp_enh <= '1';
sfp_txdis <= '0';
else
reset_ct := reset_ct - 1;
end if;
end if;
end process;
---------------------------- resets -----------------------------------------
-- Reset sequencing:
-- 1. CFG clock is reset by FPGA_RESETL and everything waits on CFG clock to lock
-- 2. Once CFG clock is up release CPLD bridge to let APS Msg processor come up and PCS/PMA layer
-- 3. Wait ???? after ApsMsgProc released from reset to issue configuration read command
-- 3. Wait 100 ms after boot for SFP to come up (see above)
-- 4. Wait for cfg_reader_done with timeout of ??? to release rest of comms stack
-- 5. Release everything else
--Wait until cfg_clk_mmcm_locked so that we have 200MHz reference before deasserting pcs/pma and MIG reset
rst_pcs_pma <= not cfg_clk_mmcm_locked;
-- once we have CFG clock MMCM locked we have CPLD and AXI and we can talk to CPLD
reset_synchronizer_clk_100_axi : entity work.synchronizer
generic map(RESET_VALUE => '1')
port map(rst => not cfg_clk_mmcm_locked, clk => clk_100_axi, data_in => '0', data_out => rst_sync_clk_100_axi);
rst_cpld_bridge <= rst_sync_clk_100_axi;
rst_tcp_bridge <= rst_sync_clk_100_axi;
rstn_axi <= not rst_sync_clk_100_axi;
-- hold config reader in reset until after CPLD and AXI are ready and give another 100ms
-- for ApsMsgProc to startup and do it's reading of the MAC address
-- then wait for done with timeout of 100ms so we have IP and MAC before releasing comm statck
cfg_reader_wait : process(clk_100_axi)
variable reset_ct : unsigned(24 downto 0) := (others => '0');
variable wait_ct : unsigned(24 downto 0) := (others => '0');
type state_t is (WAIT_FOR_RESET, WAIT_FOR_DONE, FINISHED);
variable state : state_t;
begin
if rising_edge(clk_100_axi) then
if rst_sync_clk_100_axi = '1' then
state := WAIT_FOR_RESET;
reset_ct := to_unsigned(10_000_000, reset_ct'length); --100ms at 100 MHz ignoring off-by-one issues
wait_ct := to_unsigned(10_000_000, wait_ct'length); --100ms at 100 MHz ignoring off-by-one issues
rst_cfg_reader <= '1';
rst_comm_stack <= '1';
else
case( state ) is
when WAIT_FOR_RESET =>
if reset_ct(reset_ct'high) = '1' then
state := WAIT_FOR_DONE;
else
reset_ct := reset_ct - 1;
end if;
when WAIT_FOR_DONE =>
rst_cfg_reader <= '0';
if cfg_reader_done = '1' or wait_ct(wait_ct'high) = '1' then
state := FINISHED;
else
wait_ct := wait_ct - 1;
end if;
when FINISHED =>
rst_comm_stack <= '0';
end case;
end if;
end if;
end process;
-- synchronize comm stack reset to 125 MHz ethernet clock domain
reset_synchronizer_clk_125Mhz : entity work.synchronizer
generic map(RESET_VALUE => '1')
port map(rst => rst_comm_stack, clk => clk_125, data_in => '0', data_out => rst_sync_clk125);
rst_udp_responder <= rst_sync_clk125;
rst_comblock <= rst_sync_clk125;
rst_eth_mac <= rst_sync_clk125;
-- hold SATA in reset until we have system clock and cfg_clk for 200MHz reference
reset_synchronizer_clk_100 : entity work.synchronizer
generic map(RESET_VALUE => '1')
port map(rst => not (sys_clk_mmcm_locked and cfg_clk_mmcm_locked), clk => clk_100, data_in => '0', data_out => rst_sync_clk100);
rst_sata <= rst_sync_clk100;
------------------ front panel LEDs ------------------------
status_leds_inst : entity work.status_leds
port map (
clk => clk_100_axi,
rst => rst_comm_stack,
link_established => link_established,
comms_active => comms_active,
comms_error => ethernet_mm2s_err or ethernet_s2mm_err,
inputs_latched => ext_valid_re,
trigger_enabled => trigger_enabled,
leds => dbg(7 downto 4)
);
dbg(3 downto 0) <= (others => '0');
-- Send output status to LEDs for checking
-- TODO
led <= (others => '0');
--------------------------- comparator inputs ----------------------------------
CBF1 : for i in 0 to 7 generate
-- External trigger input from LVDS comparator. Must be differentially termianted
IBX : IBUFDS
generic map
(
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
)
port map
(
O => CMP(i), -- Drive the LED output
I => TRG_CMPP(i), -- Diff_p buffer input (connect directly to top-level port)
IB => TRG_CMPN(i) -- Diff_n buffer input (connect directly to top-level port)
);
PWMX : entity work.PWMA8
port map
(
CLK => clk_100,
RESET => rst_sata,
DIN => x"52", -- Fix at 0.8V for now. Eventually drive from a status register
PWM_OUT => THR(i)
);
end generate;
------------------------- SATA connections ------------------------------------
-- basic logic to broadcast input triggers to all output triggers
-- VALID on rising edge of CMP(7) or internal trigger
-- sync external valid on CLK_100MHZ
sync_valid : entity work.synchronizer
port map ( rst => rst_sata, clk => clk_100, data_in => CMP(7), data_out => ext_valid );
-- DATA is CMP(6 downto 0) except when internal trigger fires, in which case we send 0xFE
ext_valid_re <= ext_valid and not ext_valid_d;
process(clk_100)
begin
if rising_edge(clk_100) then
ext_valid_d <= ext_valid;
if trigger = '1' then
-- magic symbol of 0xFE indicates a system trigger to slave modules
TrigOutDat <= (others => x"fe");
else
TrigOutDat <= (others => '0' & CMP(6 downto 0));
end if;
if rst_sata = '1' then
TrigWr <= (others => '0');
else
TrigWr <= (others => ext_valid_re or trigger);
end if;
end if;
end process;
TO1 : for i in 0 to 8 generate
-- Externally, cable routing requires a non sequential JTx to TOx routing.
-- The cables are routed from the PCB connectors to the front panel as shown below.
-- The mapping is performed by changing the pin definitions in the XDC file.
--
-- TO1 = JT0
-- TO2 = JT2
-- TO3 = JT4
-- TO4 = JT6
-- TO5 = JC01
-- TO6 = JT3
-- TO7 = JT1
-- TO8 = JT5
-- TO9 = JT7
-- TAUX = JT8
TOLX : entity work.TriggerOutLogic
port map
(
-- These clocks are driven by SYS_MMCM, and thus are locked to the 10 MHz
-- reference (if present), or the SFP clock.
CLK_100MHZ => clk_100,
CLK_400MHZ => CLK_400,
RESET => rst_sata,
TRIG_TX => TrigOutDat(i),
TRIG_VALID => TrigWr(i),
TRIG_CLKP => trgclk_outp(i),
TRIG_CLKN => trgclk_outn(i),
TRIG_DATP => trgdat_outp(i),
TRIG_DATN => trgdat_outn(i)
);
end generate;
-- Instantiate LVDS 8:1 logic on auxiliary SATA port
TIL1 : entity work.TriggerInLogic
port map
(
USER_CLK => clk_100,
CLK_200MHZ => clk_200,
RESET => rst_sata,
TRIG_CLKP => trig_ctrlp(0),
TRIG_CLKN => trig_ctrln(0),
TRIG_DATP => trig_ctrlp(1),
TRIG_DATN => trig_ctrln(1),
TRIG_NEXT => TrigInRd, -- Always read data when it is available
TRIG_LOCKED => TrigLocked,
TRIG_ERR => TrigClkErr,
TRIG_RX => TrigInDat,
TRIG_OVFL => TrigOvflErr,
TRIG_READY => TrigInReady
);
-- Continually drain the input FIFO
TrigInRd <= TrigInReady;
-- internal trigger generator
IntTrig : entity work.InternalTrig
port map (
RESET => not trigger_enabled,
CLK => clk_100,
triggerInterval => trigger_interval,
triggerSource => trigger_source(1),
softTrigToggle => soft_trig_toggle,
trigger => trigger
);
-- wire out status registers
SATA_status(8 downto 0) <= TrigWr;
SATA_status(17 downto 9) <= (others => '0');
SATA_status(20) <= ext_valid;
SATA_status(24) <= TrigLocked;
SATA_status(25) <= TrigClkErr;
SATA_status(26) <= TrigOvflErr;
-- store latched trigger words in a shift register that we report in a status register
process (clk_100)
begin
if rising_edge(clk_100) then
if rst_sync_clk100 = '1' then
latched_trig_word <= (others => '0');
elsif TrigWr(0) = '1' then
latched_trig_word <= latched_trig_word(23 downto 0) & TrigOutDat(0);
end if;
end if;
end process;
------------------------ wrap the main block design ----------------------------
main_bd_inst : entity work.main_bd
port map (
--configuration constants
gateway_ip_addr => GATEWAY_IP_ADDR,
subnet_mask => SUBNET_MASK,
tcp_port => TCP_PORT,
udp_port => UDP_PORT,
pcs_pma_an_adv_config_vector => PCS_PMA_AN_ADV_CONFIG_VECTOR,
pcs_pma_configuration_vector => PCS_PMA_CONFIGURATION_VECTOR,
--clocks
clk_125 => clk_125,
clk_axi => clk_100_axi,
clk_ref_200 => clk_200,
sfp_mgt_clk_clk_n => sfp_mgt_clkn,
sfp_mgt_clk_clk_p => sfp_mgt_clkp,
--resets
rst_pcs_pma => rst_pcs_pma,
rst_eth_mac => rst_eth_mac,
rst_cpld_bridge => rst_cpld_bridge,
rst_cfg_reader => rst_cfg_reader,
rst_comblock => rst_comblock,
rst_tcp_bridge => rst_tcp_bridge,
rst_udp_responder => rst_udp_responder,
rstn_axi => rstn_axi,
cfg_reader_done => cfg_reader_done,
--SFP
pcs_pma_mmcm_locked => mgt_clk_locked,
pcs_pma_status_vector => pcs_pma_status_vector,
sfp_rxn => sfp_rxn,
sfp_rxp => sfp_rxp,
sfp_txn => sfp_txn,
sfp_txp => sfp_txp,
comms_active => comms_active,
ethernet_mm2s_err => ethernet_mm2s_err,
ethernet_s2mm_err => ethernet_s2mm_err,
--CPLD interface
cfg_act => cfg_act,
cfg_clk => clk_100_skewed,
cfg_err => cfg_err,
cfg_rdy => cfg_rdy,
cfgd => cfgd(15 downto 0),
fpga_cmdl => fpga_cmdl,
fpga_rdyl => fpga_rdyl,
stat_oel => stat_oel,
-- XADC Pins
XADC_Vp_Vn_v_n => vn,
XADC_Vp_Vn_v_p => vp,
-- CSR registers
status => status,
control => control,
resets => resets,
trigger_interval => trigger_interval,
SATA_status => SATA_status,
build_timestamp => BUILD_TIMESTAMP,
git_sha1 => GIT_SHA1,
tdm_version => TDM_VERSION,
trigger_word => latched_trig_word,
uptime_nanoseconds => uptime_nanoseconds,
uptime_seconds => uptime_seconds
);
--up time registers
up_time_counters : process(clk_100_axi)
constant CLKS_PER_SEC : natural := 100_000_000;
constant NS_PER_CLK : natural := 10;
variable roll_over_ct : unsigned(31 downto 0);
variable seconds_ct : unsigned(31 downto 0);
variable nanoseconds_ct : unsigned(31 downto 0);
begin
if rising_edge(clk_100_axi) then
if rst_sync_clk_100_axi = '1' then
roll_over_ct := to_unsigned(CLKS_PER_SEC-2, 32);
seconds_ct := (others => '0');
nanoseconds_ct := (others => '0');
uptime_seconds <= (others => '0');
uptime_nanoseconds <= (others => '0');
else
--Output registers
uptime_seconds <= std_logic_vector(seconds_ct);
uptime_nanoseconds <= std_logic_vector(nanoseconds_ct);
--Check for roll-over
if roll_over_ct(roll_over_ct'high) = '1' then
roll_over_ct := to_unsigned(CLKS_PER_SEC-2, 32);
seconds_ct := seconds_ct + 1;
nanoseconds_ct := (others => '0');
else
nanoseconds_ct := nanoseconds_ct + NS_PER_CLK;
--Count down
roll_over_ct := roll_over_ct - 1;
end if;
end if;
end if;
end process;
end behavior;
| mpl-2.0 |
BBN-Q/VHDL-Components | test/PCG_XSH_RR_tb.vhd | 1 | 2737 | -- test bench for the PCG pseudorandom number generator
--
-- Original author: Blake Johnson
-- Copyright 2017 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PCG_XSH_RR_tb is
end;
architecture bench of PCG_XSH_RR_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '0';
constant clock_period : time := 4.0 ns;
signal stop_the_clock : boolean := false;
signal checking_finished : boolean := false;
constant LATENCY : natural := 3;
signal seed : std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(1234, 64));
signal rand_out : std_logic_vector(31 downto 0);
signal valid : std_logic;
type rand_array is array(0 to 7) of std_logic_vector(31 downto 0);
signal rand_outs : rand_array := (others => (others => '0'));
-- expected outs computed using PCG.jl:
-- julia> include("PCG.jl")
-- julia> using PCG
-- julia> g = PCG(1234)
-- julia> [rand(g) for _ in 1:8]
signal expected_outs : rand_array := (
0 => x"00000000",
1 => x"cb267ac2",
2 => x"035401a4",
3 => x"3db8c0ea",
4 => x"45b49a87",
5 => x"42f4a7aa",
6 => x"d6016e1c",
7 => x"3922cc67"
);
type TestBenchState_t is (RESET, TEST_RAND, FINISHED);
signal test_bench_state : TestBenchState_t;
begin
uut: entity work.PCG_XSH_RR
port map (
clk => clk,
rst => rst,
seed => seed,
rand => rand_out,
valid => valid
);
clk <= not clk after clock_period / 2 when not stop_the_clock;
stimulus : process
begin
---------------------------
test_bench_state <= RESET;
rst <= '1';
wait for 20 ns;
wait until rising_edge(clk);
rst <= '0';
test_bench_state <= TEST_RAND;
for ct in rand_outs'range loop
wait until rising_edge(valid);
rand_outs(ct) <= rand_out;
end loop;
test_bench_state <= FINISHED;
wait for 100 ns;
stop_the_clock <= true;
wait;
end process;
checking : process
begin
wait until rising_edge(clk) and test_bench_state = FINISHED;
for ct in rand_outs'range loop
-- compare against a known result
assert rand_outs(ct) = expected_outs(ct) report "PCG output error: expected " &
integer'image( to_integer( unsigned(expected_outs(ct) ) )) & " but got " &
integer'image( to_integer( unsigned(rand_outs(ct) ) ));
end loop;
report "FINISHED PCG output checking";
checking_finished <= true;
end process;
end;
| mpl-2.0 |
nxt4hll/roccc-2.0 | roccc-compiler/src/llvm-2.3/include/rocccLibrary/BurstAddressGen.vhdl | 1 | 6930 | library IEEE ;
use IEEE.STD_LOGIC_1164.all ;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use work.HelperFunctions.all;
use work.HelperFunctions_Unsigned.all;
use work.HelperFunctions_Signed.all;
entity BurstAddressGen is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--input burst data
base_address_in : in STD_LOGIC_VECTOR(31 downto 0);
burst_size_in : in STD_LOGIC_VECTOR(31 downto 0);
burst_valid_in : in STD_LOGIC;
--burst_address_read_out : out STD_LOGIC;
burst_stall_out : out STD_LOGIC;
--output addresses
address_valid_out : out STD_LOGIC;
address_out : out STD_LOGIC_VECTOR(31 downto 0);
address_stall_in : in STD_LOGIC
);
end BurstAddressGen;
architecture Behavioral of BurstAddressGen is
--used when reading from an external BRAM
--type BRAM_STATE_TYPE is (S_EMPTY, S_READY, S_READ, S_STALL);
--signal bram_state : BRAM_STATE_TYPE;
--signal micro_valid_in : STD_LOGIC;
--signal micro_data_in : STD_LOGIC_VECTOR(63 downto 0);
--signal micro_full_out : STD_LOGIC;
signal base_value : STD_LOGIC_VECTOR(31 downto 0);
signal burst_value : STD_LOGIC_VECTOR(31 downto 0);
signal micro_read_enable_in : STD_LOGIC;
signal micro_empty_out : STD_LOGIC;
component MicroFifo is
generic (
ADDRESS_WIDTH : POSITIVE;
DATA_WIDTH : POSITIVE;
ALMOST_FULL_COUNT : NATURAL;
ALMOST_EMPTY_COUNT : NATURAL
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
valid_in : in STD_LOGIC;
full_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
read_enable_in : in STD_LOGIC;
empty_out : out STD_LOGIC
);
end component;
--type state_STATE_TYPE is (S_READY, S_READ, S_PROCESSING) ;
type state_STATE_TYPE is (S_READY, S_READ, S_PROCESSING, S_PROCESSING_LAST) ;
signal state : state_STATE_TYPE ;
signal cur_address : STD_LOGIC_VECTOR(31 downto 0);
signal end_address : STD_LOGIC_VECTOR(31 downto 0);
begin
--used when reading from an external BRAM
--process(clk, rst)
--begin
-- if( rst = '1' ) then
-- burst_address_read_out <= '0';
-- micro_valid_in <= '0';
-- micro_data_in <= (others=>'0');
-- bram_state <= S_EMPTY;
-- elsif( clk'event and clk = '1' ) then
-- burst_address_read_out <= '0';
-- micro_valid_in <= '0';
-- case bram_state is
-- when S_EMPTY =>
-- if( burst_valid_in = '1' and micro_full_out = '0' ) then
-- burst_address_read_out <= '1';
-- bram_state <= S_READY;
-- end if;
-- when S_READY =>
-- burst_address_read_out <= '1';
-- bram_state <= S_READ;
-- when S_READ =>
-- --read
-- micro_valid_in <= '1';
-- micro_data_in(31 downto 0) <= base_address_in;
-- micro_data_in(63 downto 32) <= burst_size_in;
-- if( burst_valid_in = '1' and micro_full_out = '0' ) then
-- burst_address_read_out <= '1';
-- elsif( micro_full_out = '1' ) then
-- bram_state <= S_STALL;
-- else
-- bram_state <= S_EMPTY;
-- end if;
-- when S_STALL =>
-- --read
-- micro_valid_in <= '1';
-- micro_data_in(31 downto 0) <= base_address_in;
-- micro_data_in(63 downto 32) <= burst_size_in;
-- bram_state <= S_EMPTY;
-- end case;
-- end if;
--end process;
micro : MicroFifo
generic map(
ADDRESS_WIDTH => 4,
DATA_WIDTH => 64,
ALMOST_FULL_COUNT => 3,
ALMOST_EMPTY_COUNT => 0
)
port map(
clk => clk,
rst => rst,
data_in(31 downto 0) => base_address_in,
data_in(63 downto 32) => burst_size_in,
valid_in => burst_valid_in,
full_out => burst_stall_out,
--used when reading from an external BRAM
-- data_in => micro_data_in,
-- valid_in => micro_valid_in,
-- full_out => micro_full_out,
data_out(31 downto 0) => base_value,
data_out(63 downto 32) => burst_value,
read_enable_in => micro_read_enable_in,
empty_out => micro_empty_out
);
--process(clk, rst)
--begin
-- if( rst = '1' ) then
-- address_valid_out <= '0';
-- address_out <= (others=>'0');
-- cur_address <= (others=>'0');
-- end_address <= (others=>'0');
-- micro_read_enable_in <= '0';
-- state <= S_READY;
-- elsif( clk'event and clk = '1' ) then
-- address_valid_out <= '0';
-- micro_read_enable_in <= '0';
-- case state is
-- when S_READY =>
-- if( micro_empty_out = '0' ) then
-- state <= S_READ;
-- micro_read_enable_in <= '1';
-- end if;
-- when S_READ =>
-- state <= S_PROCESSING;
-- --micro_read_enable_in <= '1';
-- cur_address <= base_value;
-- end_address <=
-- ROCCCSUB(
-- ROCCCADD(
-- base_value,
-- burst_value,
-- 32),
-- "00000000000000000000000000000001",
-- 32);
-- when S_PROCESSING =>
-- if( address_stall_in = '0' ) then
-- address_valid_out <= '1';
-- address_out <= cur_address;
-- if( ROCCC_UGTE(cur_address, end_address, 32) ) then
-- state <= S_READY;
-- if( micro_empty_out = '0' ) then
-- state <= S_READ;
-- micro_read_enable_in <= '1';
-- end if;
-- end if;
-- --else
-- cur_address <=
-- ROCCCADD(
-- cur_address,
-- "00000000000000000000000000000001",
-- 32);
-- --end if;
-- end if;
-- end case;
-- end if;
--end process;
process(clk, rst)
begin
if( rst = '1' ) then
address_valid_out <= '0';
address_out <= (others=>'0');
cur_address <= (others=>'0');
end_address <= (others=>'0');
micro_read_enable_in <= '0';
state <= S_READY;
elsif( clk'event and clk = '1' ) then
address_valid_out <= '0';
micro_read_enable_in <= '0';
case state is
when S_READY =>
if( micro_empty_out = '0' ) then
state <= S_READ;
micro_read_enable_in <= '1';
end if;
when S_READ =>
state <= S_PROCESSING;
--micro_read_enable_in <= '1';
cur_address <= base_value;
end_address <=
ROCCCSUB(
ROCCCADD(
base_value,
burst_value,
32),
"00000000000000000000000000000001",
32);
when S_PROCESSING =>
if( address_stall_in = '0' ) then
address_valid_out <= '1';
address_out <= cur_address;
if( cur_address = end_address ) then
state <= S_READY;
if( micro_empty_out = '0' ) then
state <= S_READ;
micro_read_enable_in <= '1';
end if;
elsif( ROCCCADD(cur_address,"00000000000000000000000000000001",32) = end_address ) then
state <= S_PROCESSING;
if( micro_empty_out = '0' ) then
state <= S_PROCESSING_LAST;
micro_read_enable_in <= '1';
end if;
end if;
cur_address <=
ROCCCADD(
cur_address,
"00000000000000000000000000000001",
32);
end if;
when S_PROCESSING_LAST =>
if( address_stall_in = '0' ) then
address_valid_out <= '1';
address_out <= cur_address;
state <= S_PROCESSING;
cur_address <= base_value;
end_address <=
ROCCCSUB(
ROCCCADD(
base_value,
burst_value,
32),
"00000000000000000000000000000001",
32);
end if;
end case;
end if;
end process;
end Behavioral;
| epl-1.0 |
gtarciso/INE5406 | decodificador2x4.vhd | 1 | 635 | library ieee;
use ieee.std_logic_1164.all;
entity decodificador2x4 is
port(
inpt: in std_logic_vector(1 downto 0);
enable: in std_logic;
outp: out std_logic_vector(3 downto 0)
);
end decodificador2x4;
architecture decoder of decodificador2x4 is
begin
process(inpt, enable)
begin
if enable='1' then
case inpt is
when "00" =>
outp <= "0001";
when "01" =>
outp <= "0010";
when "10" =>
outp <= "0100";
when others =>
outp <= "1000";
end case;
else
outp <= "0000";
end if;
end process;
end decoder;
| cc0-1.0 |
jwalsh/mal | vhdl/types.vhdl | 17 | 13485 | library STD;
use STD.textio.all;
package types is
procedure debugline(l: inout line);
procedure debug(str: in string);
procedure debug(ch: in character);
procedure debug(i: in integer);
type mal_type_tag is (mal_nil, mal_true, mal_false, mal_number,
mal_symbol, mal_string, mal_keyword,
mal_list, mal_vector, mal_hashmap,
mal_atom, mal_nativefn, mal_fn);
-- Forward declarations
type mal_val;
type mal_seq;
type mal_func;
type env_record;
type mal_val_ptr is access mal_val;
type mal_seq_ptr is access mal_seq;
type mal_func_ptr is access mal_func;
type env_ptr is access env_record;
type mal_val is record
val_type: mal_type_tag;
number_val: integer; -- For types: number
string_val: line; -- For types: symbol, string, keyword, nativefn
seq_val: mal_seq_ptr; -- For types: list, vector, hashmap, atom
func_val: mal_func_ptr; -- For fn
meta_val: mal_val_ptr;
end record mal_val;
type mal_seq is array (natural range <>) of mal_val_ptr;
type mal_func is record
f_body: mal_val_ptr;
f_args: mal_val_ptr;
f_env: env_ptr;
f_is_macro: boolean;
end record mal_func;
type env_record is record
outer: env_ptr;
data: mal_val_ptr;
end record env_record;
procedure new_nil(obj: out mal_val_ptr);
procedure new_true(obj: out mal_val_ptr);
procedure new_false(obj: out mal_val_ptr);
procedure new_boolean(b: in boolean; obj: out mal_val_ptr);
procedure new_number(v: in integer; obj: out mal_val_ptr);
procedure new_symbol(name: in string; obj: out mal_val_ptr);
procedure new_symbol(name: inout line; obj: out mal_val_ptr);
procedure new_string(name: in string; obj: out mal_val_ptr);
procedure new_string(name: inout line; obj: out mal_val_ptr);
procedure new_keyword(name: in string; obj: out mal_val_ptr);
procedure new_keyword(name: inout line; obj: out mal_val_ptr);
procedure new_nativefn(name: in string; obj: out mal_val_ptr);
procedure new_fn(body_ast: inout mal_val_ptr; args: inout mal_val_ptr; env: inout env_ptr; obj: out mal_val_ptr);
procedure new_seq_obj(seq_type: in mal_type_tag; seq: inout mal_seq_ptr; obj: out mal_val_ptr);
procedure new_one_element_list(val: inout mal_val_ptr; obj: out mal_val_ptr);
procedure new_empty_hashmap(obj: out mal_val_ptr);
procedure new_atom(val: inout mal_val_ptr; obj: out mal_val_ptr);
procedure hashmap_copy(hashmap: inout mal_val_ptr; obj: out mal_val_ptr);
procedure hashmap_get(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: out mal_val_ptr);
procedure hashmap_contains(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; ok: out boolean);
procedure hashmap_put(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure hashmap_delete(hashmap: inout mal_val_ptr; key: inout mal_val_ptr);
procedure seq_drop_prefix(src: inout mal_val_ptr; prefix_length: in integer; result: out mal_val_ptr);
function is_sequential_type(t: in mal_type_tag) return boolean;
procedure equal_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean);
end package types;
package body types is
procedure debugline(l: inout line) is
variable l2: line;
begin
l2 := new string(1 to 7 + l'length);
l2(1 to l2'length) := "DEBUG: " & l.all;
writeline(output, l2);
end procedure debugline;
procedure debug(str: in string) is
variable d: line;
begin
write(d, str);
debugline(d);
end procedure debug;
procedure debug(ch: in character) is
variable d: line;
begin
write(d, ch);
debugline(d);
end procedure debug;
procedure debug(i: in integer) is
variable d: line;
begin
write(d, i);
debugline(d);
end procedure debug;
procedure new_nil(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_nil, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_nil;
procedure new_true(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_true, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_true;
procedure new_false(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_false, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_false;
procedure new_boolean(b: in boolean; obj: out mal_val_ptr) is
begin
if b then
new_true(obj);
else
new_false(obj);
end if;
end procedure new_boolean;
procedure new_number(v: in integer; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_number, number_val => v, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_number;
procedure new_symbol(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_symbol, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_symbol;
procedure new_symbol(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_symbol, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_symbol;
procedure new_string(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_string, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_string;
procedure new_string(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_string, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_string;
procedure new_keyword(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_keyword, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_keyword;
procedure new_keyword(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_keyword, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_keyword;
procedure new_nativefn(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_nativefn, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_nativefn;
procedure new_fn(body_ast: inout mal_val_ptr; args: inout mal_val_ptr; env: inout env_ptr; obj: out mal_val_ptr) is
variable f: mal_func_ptr;
begin
f := new mal_func'(f_body => body_ast, f_args => args, f_env => env, f_is_macro => false);
obj := new mal_val'(val_type => mal_fn, number_val => 0, string_val => null, seq_val => null, func_val => f, meta_val => null);
end procedure new_fn;
procedure new_seq_obj(seq_type: in mal_type_tag; seq: inout mal_seq_ptr; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => seq_type, number_val => 0, string_val => null, seq_val => seq, func_val => null, meta_val => null);
end procedure new_seq_obj;
procedure new_one_element_list(val: inout mal_val_ptr; obj: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to 0);
seq(0) := val;
new_seq_obj(mal_list, seq, obj);
end procedure new_one_element_list;
procedure new_empty_hashmap(obj: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to -1);
new_seq_obj(mal_hashmap, seq, obj);
end procedure new_empty_hashmap;
procedure new_atom(val: inout mal_val_ptr; obj: out mal_val_ptr) is
variable atom_seq: mal_seq_ptr;
begin
atom_seq := new mal_seq(0 to 0);
atom_seq(0) := val;
new_seq_obj(mal_atom, atom_seq, obj);
end procedure new_atom;
procedure hashmap_copy(hashmap: inout mal_val_ptr; obj: out mal_val_ptr) is
variable new_seq: mal_seq_ptr;
begin
new_seq := new mal_seq(hashmap.seq_val'range);
new_seq(new_seq'range) := hashmap.seq_val(hashmap.seq_val'range);
new_seq_obj(mal_hashmap, new_seq, obj);
end procedure hashmap_copy;
procedure hashmap_get(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: out mal_val_ptr) is
variable i: natural;
variable curr_key: mal_val_ptr;
begin
i := 0;
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
val := hashmap.seq_val(i + 1);
return;
end if;
i := i + 2;
end loop;
val := null;
end procedure hashmap_get;
procedure hashmap_contains(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; ok: out boolean) is
variable val: mal_val_ptr;
begin
hashmap_get(hashmap, key, val);
if val = null then
ok := false;
else
ok := true;
end if;
end procedure hashmap_contains;
procedure hashmap_put(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
variable i: natural;
variable curr_key: mal_val_ptr;
variable new_seq: mal_seq_ptr;
begin
i := 0;
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
hashmap.seq_val(i + 1) := val;
return;
end if;
i := i + 2;
end loop;
-- Not found so far, need to extend the seq
new_seq := new mal_seq(0 to hashmap.seq_val'length + 1);
for i in hashmap.seq_val'range loop
new_seq(i) := hashmap.seq_val(i);
end loop;
new_seq(new_seq'length - 2) := key;
new_seq(new_seq'length - 1) := val;
deallocate(hashmap.seq_val);
hashmap.seq_val := new_seq;
end procedure hashmap_put;
procedure hashmap_delete(hashmap: inout mal_val_ptr; key: inout mal_val_ptr) is
variable i, dst_i: natural;
variable curr_key: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable found: boolean;
begin
hashmap_contains(hashmap, key, found);
if not found then
return;
end if;
i := 0;
dst_i := 0;
new_seq := new mal_seq(0 to hashmap.seq_val'high - 2);
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
i := i + 2;
else
new_seq(dst_i to dst_i + 1) := hashmap.seq_val(i to i + 1);
dst_i := dst_i + 2;
i := i + 2;
end if;
end loop;
deallocate(hashmap.seq_val);
hashmap.seq_val := new_seq;
end procedure hashmap_delete;
procedure seq_drop_prefix(src: inout mal_val_ptr; prefix_length: in integer; result: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to src.seq_val'length - 1 - prefix_length);
for i in seq'range loop
seq(i) := src.seq_val(i + prefix_length);
end loop;
new_seq_obj(src.val_type, seq, result);
end procedure seq_drop_prefix;
function is_sequential_type(t: in mal_type_tag) return boolean is
begin
return t = mal_list or t = mal_vector;
end function is_sequential_type;
procedure equal_seq_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
variable i: integer;
variable is_element_equal: boolean;
begin
if a.seq_val'length = b.seq_val'length then
for i in a.seq_val'range loop
equal_q(a.seq_val(i), b.seq_val(i), is_element_equal);
if not is_element_equal then
result := false;
return;
end if;
end loop;
result := true;
else
result := false;
end if;
end procedure equal_seq_q;
procedure equal_hashmap_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
variable i: integer;
variable is_value_equal: boolean;
variable b_val: mal_val_ptr;
begin
if a.seq_val'length = b.seq_val'length then
i := 0;
while i < a.seq_val'length loop
hashmap_get(b, a.seq_val(i), b_val);
if b_val = null then
result := false;
return;
else
equal_q(a.seq_val(i + 1), b_val, is_value_equal);
if not is_value_equal then
result := false;
return;
end if;
end if;
i := i + 2;
end loop;
result := true;
else
result := false;
end if;
end procedure equal_hashmap_q;
procedure equal_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
begin
if is_sequential_type(a.val_type) and is_sequential_type(b.val_type) then
equal_seq_q(a, b, result);
elsif a.val_type = b.val_type then
case a.val_type is
when mal_nil | mal_true | mal_false =>
result := true;
when mal_number =>
result := a.number_val = b.number_val;
when mal_symbol | mal_string | mal_keyword =>
result := a.string_val.all = b.string_val.all;
when mal_hashmap =>
equal_hashmap_q(a, b, result);
when mal_atom =>
equal_q(a.seq_val(0), b.seq_val(0), result);
when others =>
result := false;
end case;
else
result := false;
end if;
end procedure equal_q;
end package body types;
| mpl-2.0 |
jwalsh/mal | vhdl/step5_tco.vhdl | 17 | 6767 | entity step5_tco is
end entity step5_tco;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step5_tco is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
eval_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable dummy_val, err: mal_val_ptr;
variable outer, repl_env: env_ptr;
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 |
xdsopl/vhdl | max10_10M08E144_eval_test3.vhd | 1 | 3089 | -- test3 - post pll clock divider controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity max10_10M08E144_eval_test3 is
generic (
NUM_LEDS : positive := 5
);
port (
clock : in std_logic;
reset_n : in std_logic;
rotary_n : in std_logic_vector (1 downto 0);
leds_n : out std_logic_vector (NUM_LEDS-1 downto 0);
oclock : out std_logic
);
end max10_10M08E144_eval_test3;
architecture rtl of max10_10M08E144_eval_test3 is
attribute chip_pin : string;
attribute chip_pin of clock : signal is "27";
attribute chip_pin of oclock : signal is "64";
attribute chip_pin of reset_n : signal is "121";
attribute chip_pin of rotary_n : signal is "70, 69"; -- need to enable weak pullup resistor
attribute chip_pin of leds_n : signal is "132, 134, 135, 140, 141";
signal reset : std_logic;
signal rotary : std_logic_vector (1 downto 0);
signal leds : std_logic_vector (NUM_LEDS-1 downto 0);
signal divider : std_logic_vector (NUM_LEDS-1 downto 0);
signal scanclk : std_logic;
signal scanclkena : std_logic;
signal scandata : std_logic;
signal scandataout : std_logic;
signal areset : std_logic;
signal configupdate : std_logic;
signal update : std_logic;
signal position : integer range 0 to 144 := 0;
signal transfer : boolean := false;
signal high_count : std_logic_vector (7 downto 0);
signal low_count : std_logic_vector (7 downto 0);
begin
reset <= not reset_n;
rotary <= not rotary_n;
leds_n <= not leds;
leds <= divider;
scanclk <= clock;
scandata <= high_count(62-position) when 55 <= position and position <= 62 else
low_count(71-position) when 64 <= position and position <= 71 else
scandataout;
process (reset, clock)
begin
if reset = '1' then
transfer <= false;
areset <= '1';
scanclkena <= '0';
configupdate <= '0';
elsif falling_edge(clock) then
areset <= '0';
configupdate <= '0';
if update = '1' and not transfer then
transfer <= true;
scanclkena <= '1';
position <= 144;
high_count <= "000" & divider;
low_count <= "000" & divider;
end if;
if transfer then
if position = 0 then
transfer <= false;
scanclkena <= '0';
configupdate <= '1';
else
position <= position - 1;
end if;
end if;
end if;
end process;
test3_inst : entity work.test3
generic map (NUM_LEDS)
port map (clock, reset, rotary, divider, update);
pll_inst : entity work.altera_pll_var
port map (areset => areset, inclk0 => clock, c0 => oclock,
scanclk => scanclk, scandata => scandata, scanclkena => scanclkena,
configupdate => configupdate, scandataout => scandataout);
end rtl;
| cc0-1.0 |
ahammer/MySaasa | server/src/main/webapp/ace/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| agpl-3.0 |
JimLewis/OSVVM | demo/AlertLog_Demo_Hierarchy.vhd | 2 | 8410 | --
-- File Name: AlertLog_Demo_Hierarchy.vhd
-- Design Unit Name: AlertLog_Demo_Hierarchy
-- Revision: STANDARD VERSION, 2015.01
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis email: jim@synthworks.com
--
-- Description:
-- Demo showing use of hierarchy in AlertLogPkg
-- Both TB and CPU use sublevels of hierarchy
-- UART does not use sublevels of hierarchy
-- Usage of block statements emulates a separate entity/architecture
--
-- Developed for:
-- SynthWorks Design Inc.
-- Training Courses
-- 11898 SW 128th Ave.
-- Tigard, Or 97223
-- http://www.SynthWorks.com
--
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.01 Refining tests
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use std.textio.all ;
use ieee.std_logic_textio.all ;
library osvvm ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.AlertLogPkg.all ;
entity AlertLog_Demo_Hierarchy is
end AlertLog_Demo_Hierarchy ;
architecture hierarchy of AlertLog_Demo_Hierarchy is
signal Clk : std_logic := '0';
begin
Clk <= not Clk after 10 ns ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Testbench_1 : block
constant TB_AlertLogID : AlertLogIDType := GetAlertLogID("Testbench_1") ;
begin
TbP0 : process
variable ClkNum : integer := 0 ;
begin
wait until Clk = '1' ;
ClkNum := ClkNum + 1 ;
print(LF & "Clock Number " & to_string(ClkNum)) ;
end process TbP0 ;
------------------------------------------------------------
TbP1 : process
constant TB_P1_ID : AlertLogIDType := GetAlertLogID("TB P1", TB_AlertLogID) ;
variable TempID : AlertLogIDType ;
begin
-- Uncomment this line to use a log file rather than OUTPUT
-- TranscriptOpen("./Demo_Hierarchy.txt") ;
-- Uncomment this line and the simulation will stop after 15 errors
-- SetAlertStopCount(ERROR, 15) ;
SetAlertLogName("AlertLog_Demo_Hierarchy") ;
wait for 0 ns ; -- make sure all processes have elaborated
SetLogEnable(DEBUG, TRUE) ; -- Enable DEBUG Messages for all levels of the hierarchy
TempID := GetAlertLogID("CPU_1") ; -- Get The CPU AlertLogID
SetLogEnable(TempID, DEBUG, FALSE) ; -- turn off DEBUG messages in CPU
SetLogEnable(TempID, INFO, TRUE) ; -- turn on INFO messages in CPU
-- Uncomment this line to justify alert and log reports
-- SetAlertLogJustify ;
for i in 1 to 5 loop
wait until Clk = '1' ;
if i = 4 then SetLogEnable(DEBUG, FALSE) ; end if ; -- DEBUG Mode OFF
wait for 1 ns ;
Alert(TB_P1_ID, "Tb.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log (TB_P1_ID, "Tb.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait until Clk = '1' ;
wait until Clk = '1' ;
wait for 1 ns ;
-- Report Alerts without expected errors
ReportAlerts ;
print("") ;
-- Report Alerts with expected errors expressed as a negative ExternalErrors value
ReportAlerts(Name => "AlertLog_Demo_Hierarchy with expected errors", ExternalErrors => -(FAILURE => 0, ERROR => 20, WARNING => 15)) ;
TranscriptClose ;
print(LF & "The following is brought to you by std.env.stop:") ;
std.env.stop ;
wait ;
end process TbP1 ;
------------------------------------------------------------
TbP2 : process
constant TB_P2_ID : AlertLogIDType := GetAlertLogID("TB P2", TB_AlertLogID) ;
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 2 ns ;
Alert(TB_P2_ID, "Tb.P2.E alert " & to_string(i) & " of 5", ERROR) ;
-- example of a log that is not enabled, so it does not print
Log (TB_P2_ID, "Tb.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait until Clk = '1' ;
wait for 2 ns ;
-- Uncomment this line to and the simulation will stop here
-- Alert(TB_P2_ID, "Tb.P2.F Message 1 of 1", FAILURE) ;
wait ;
end process TbP2 ;
------------------------------------------------------------
TbP3 : process
constant TB_P3_ID : AlertLogIDType := GetAlertLogID("TB P3", TB_AlertLogID) ;
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 3 ns ;
Alert(TB_P3_ID, "Tb.P3.W alert " & to_string(i) & " of 5", WARNING) ;
end loop ;
wait ;
end process TbP3 ;
end block Testbench_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Cpu_1 : block
constant CPU_AlertLogID : AlertLogIDType := GetAlertLogID("CPU_1") ;
begin
------------------------------------------------------------
CpuP1 : process
constant CPU_P1_ID : AlertLogIDType := GetAlertLogID("CPU P1", CPU_AlertLogID) ;
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 5 ns ;
Alert(CPU_P1_ID, "Cpu.P1.E Message " & to_string(i) & " of 5", ERROR) ;
Log (CPU_P1_ID, "Cpu.P1.D log " & to_string(i) & " of 5", DEBUG) ;
Log (CPU_P1_ID, "Cpu.P1.F log " & to_string(i) & " of 5", FINAL) ; -- disabled
end loop ;
wait ;
end process CpuP1 ;
------------------------------------------------------------
CpuP2 : process
constant CPU_P2_ID : AlertLogIDType := GetAlertLogID("CPU P2", CPU_AlertLogID) ;
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 6 ns ;
Alert(CPU_P2_ID, "Cpu.P2.W Message " & to_string(i) & " of 5", WARNING) ;
Log (CPU_P2_ID, "Cpu.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait ;
end process CpuP2 ;
end block Cpu_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Uart_1 : block
constant UART_AlertLogID : AlertLogIDType := GetAlertLogID("UART_1") ;
begin
-- Enable FINAL logs for every level
-- Note it is expected that most control of alerts will occur only in the testbench block
-- Note that this does not turn on FINAL messages for CPU - see global for settings that impact CPU
SetLogEnable(UART_AlertLogID, FINAL, TRUE) ; -- Runs once at initialization time
------------------------------------------------------------
UartP1 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 10 ns ;
Alert(UART_AlertLogID, "Uart.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log (UART_AlertLogID, "UART.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait ;
end process UartP1 ;
------------------------------------------------------------
UartP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 11 ns ;
Alert(UART_AlertLogID, "Uart.P2.W alert " & to_string(i) & " of 5", WARNING) ;
-- Info not enabled
Log (UART_AlertLogID, "UART.P2.I log " & to_string(i) & " of 5", INFO) ;
Log (UART_AlertLogID, "UART.P2.F log " & to_string(i) & " of 5", FINAL) ;
end loop ;
wait ;
end process UartP2 ;
end block Uart_1 ;
end hierarchy ; | artistic-2.0 |
dh1dm/q27 | src/vhdl/top/xilinx/s3sk_queens_uart.vhdl | 1 | 5228 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity s3sk_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 9;
COUNT_CYCLES : boolean := false;
CLK_FREQ : positive := 50000000;
CLK_MUL : positive := 23;
CLK_DIV : positive := 13;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clkx : in std_logic;
rstx : in std_logic;
rx : in std_logic;
tx : out std_logic;
seg7_sg : out std_logic_vector(7 downto 0);
seg7_an : out std_logic_vector(3 downto 0);
leds : out std_logic_vector(7 downto 0)
);
end s3sk_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl of s3sk_queens_uart is
-- Global Control
signal clk : std_logic;
signal rst : std_logic;
-- Solver Status
signal snap : std_logic_vector(3 downto 0);
signal avail : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clk_u : std_logic; -- Unbuffered Synthesized Clock
signal rst_s : std_logic_vector(1 downto 0) := (others => '0');
begin
-- Clock Generation
DCM1 : DCM
generic map (
CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ),
CLKIN_DIVIDE_BY_2 => FALSE,
PHASE_SHIFT => 0,
CLKFX_MULTIPLY => CLK_MUL,
CLKFX_DIVIDE => CLK_DIV,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE", -- only using clkfx
DLL_FREQUENCY_MODE => "LOW",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
STARTUP_WAIT => TRUE -- Delay until DCM LOCK
)
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => clk_u,
CLKFX180 => open,
LOCKED => open,
PSDONE => open,
STATUS => open,
CLKFB => open,
CLKIN => clkx,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => '0'
);
clk_buf : BUFG
port map (
I => clk_u,
O => clk
);
-- Reset Synchronization
process(clk)
begin
if rising_edge(clk) then
rst_s <= rstx & rst_s(rst_s'left downto 1);
end if;
end process;
rst <= rst_s(0);
end block blkGlobal;
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk,
rst => rst,
rx => rx,
tx => tx,
snap => snap,
avail => avail
);
----------------------------------------------------------------------------
-- Basic Status Output
with snap select seg7_sg(6 downto 0) <=
"0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0110000" when "1111",
(others => 'X') when others;
seg7_sg(7) <= avail;
seg7_an <= x"E";
leds <= std_logic_vector(to_unsigned(SOLVERS, leds'length));
end rtl;
| agpl-3.0 |
dh1dm/q27 | src/vhdl/PoC/common/my_config_KC705.vhdl | 2 | 1751 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "KC705"; -- KC705 - Xilinx Kintex 7 reference design board: XC7K325T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
| agpl-3.0 |
dh1dm/q27 | src/vhdl/PoC/common/my_config_VC707.vhdl | 2 | 1750 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "VC707"; -- VC707 - Xilinx Virtex 7 reference design board: XC7V485T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := true;
end package;
| agpl-3.0 |
UnofficialRepos/OSVVM | AlertLogPkg.vhd | 1 | 300689 | --
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
-- Rob Gaddi Highland Technology. Inspired SetAlertLogPrefix / Suffix
--
--
-- Description:
-- Alert handling and log filtering (verbosity control)
-- Alert handling provides a method to count failures, errors, and warnings
-- To accumlate counts, a data structure is created in a shared variable
-- It is of type AlertLogStructPType which is defined in AlertLogBasePkg
-- Log filtering provides verbosity control for logs (display or do not display)
-- AlertLogPkg provides a simplified interface to the shared variable
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 SetAlertPrintCount and GetAlertPrintCount
-- Added NewID with ReportMode, PrintParent
-- Updated Alert s.t. on StopCount prints WriteAlertSummaryYaml and WriteAlertYaml
-- 01/2022 2022.01 For AlertIfEqual and AffirmIfEqual, all arrays of std_ulogic use to_hxstring
-- Updated return value for PathTail
-- 10/2021 2021.10 Moved EndOfTestSummary to ReportPkg
-- 09/2021 2021.09 Added EndOfTestSummary and CreateYamlReport - Experimental Release
-- 07/2021 2021.07 When printing time value from GetOsvvmDefaultTimeUnits is used.
-- 06/2021 2021.06 FindAlertLogID updated to allow an ID name to match the name set by SetAlertLogName (ALERTLOG_BASE_ID)
-- 12/2020 2020.12 Added MetaMatch to AffirmIfEqual and AffirmIfNotEqual for std_logic family to use MetaMatch
-- Added AffirmIfEqual for boolean
-- 10/2020 2020.10 Added MetaMatch.
-- Updated AlertIfEqual and AlertIfNotEqual for std_logic family to use MetaMatch
-- 08/2020 2020.08 Alpha Test Release of Specification Tracking - Changes are provisional and subject to change
-- Added Passed Goals - reported with ReportAlerts and ReportRequirements.
-- Added WriteAlerts - CSV format of the information in ReportAlerts
-- Tests fail when requirements are not met and FailOnRequirementErrors is true (default TRUE).
-- Set using: SetAlertLogOptions(FailOnRequirementErrors => TRUE)
-- Turn on requirements printing in summary and details with PrintRequirements (default FALSE,
-- Turn on requirements printing in summary with PrintIfHaveRequirements (Default TRUE)
-- Added Requirements Bin, ReadSpecification, GetReqID, SetPassedGoal
-- Added AffirmIf("Req ID 1", ...) -- will work even if ID not set by GetReqID or ReadSpecification
-- Added ReportRequirements, WriteRequirements, and ReadRequirements (to merge results of multiple tests)
-- Added WriteTestSummary, ReadTestSummaries, ReportTestSummaries, and WriteTestSummaries.
-- 05/2020 2020.05 Added internal variables AlertCount (W, E, F) and ErrorCount (integer)
-- that hold the error state. These can be displayed in wave windows
-- in simulation to track number of errors.
-- Calls to std.env.stop now return ErrorCount
-- Updated calls to check for valid AlertLogIDs
-- Added affirmation count for each level.
-- Turn off reporting with SetAlertLogOptions (PrintAffirmations => TRUE) ;
-- Disabled Alerts now handled in separate bins and reported separately.
-- Turn off reporting with SetAlertLogOptions (PrintDisabledAlerts => TRUE) ;
-- 01/2020 2020.01 Updated Licenses to Apache
-- 10/2018 2018.10 Added pragmas to allow alerts, logs, and affirmations in RTL code
-- Added local variable to mirror top level ErrorCount and display in simulator
-- Added prefix and suffix
-- Debug printing with number of errors as prefix
-- 04/2018 2018.04 Fix to PathTail. Prep to change AlertLogIDType to a type.
-- 05/2017 2017.05 AffirmIfEqual, AffirmIfDiff,
-- GetAffirmCount (deprecates GetAffirmCheckCount), IncAffirmCount (deprecates IncAffirmCheckCount),
-- IsAlertEnabled (alias), IsLogEnabled (alias)
-- 02/2016 2016.02 Fixed IsLogEnableType (for PASSED), AffirmIf (to pass AlertLevel)
-- Created LocalInitialize
-- 07/2015 2016.01 Fixed AlertLogID issue with > 32 IDs
-- 05/2015 2015.06 Added IncAlertCount, AffirmIf
-- 03/2015 2015.03 Added: AlertIfEqual, AlertIfNotEqual, AlertIfDiff, PathTail,
-- ReportNonZeroAlerts, ReadLogEnables
-- 01/2015 2015.01 Initial revision
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
use work.OsvvmGlobalPkg.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package AlertLogPkg is
-- type AlertLogIDType is range integer'low to integer'high ; -- next revision
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType is array (AlertIndexType) of integer ;
type AlertEnableType is array(AlertIndexType) of boolean ;
type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType
subtype LogIndexType is LogType range DEBUG to PASSED ;
type LogEnableType is array (LogIndexType) of boolean ;
type AlertLogReportModeType is (DISABLED, ENABLED, NONZERO) ;
type AlertLogPrintParentType is (PRINT_NAME, PRINT_NAME_AND_PARENT) ;
constant REPORTS_DIRECTORY : string := "" ;
-- constant REPORTS_DIRECTORY : string := "./reports/" ;
constant ALERTLOG_BASE_ID : AlertLogIDType := 0 ; -- Careful as some code may assume this is 0.
constant ALERTLOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_BASE_ID + 1 ;
constant OSVVM_ALERTLOG_ID : AlertLogIDType := ALERTLOG_BASE_ID + 2 ; -- reporting for packages
constant REQUIREMENT_ALERTLOG_ID : AlertLogIDType := ALERTLOG_BASE_ID + 3 ;
-- May have its own ID or OSVVM_ALERTLOG_ID as default - most scoreboards allocate their own ID
constant OSVVM_SCOREBOARD_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
constant OSVVM_COV_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-- Same as ALERTLOG_DEFAULT_ID
constant ALERT_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant LOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant ALERTLOG_ID_NOT_FOUND : AlertLogIDType := -1 ; -- alternately integer'right
constant ALERTLOG_ID_NOT_ASSIGNED : AlertLogIDType := -1 ;
constant MIN_NUM_AL_IDS : AlertLogIDType := 32 ; -- Number IDs initially allocated
------------------------------------------------------------
-- Alert always goes to the transcript file
procedure Alert(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) ;
procedure Alert( Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
procedure IncAlertCount( -- A silent form of alert
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) ;
procedure IncAlertCount( Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Similar to assert, except condition is positive
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- Direct replacement for assert
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- overloading for common functionality
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Simple Diff for file comparisons
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
ReceivedMessage : string ;
ExpectedMessage : string ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) ;
procedure AffirmError( Message : string ) ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE );
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ;
-- Without AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
procedure AffirmIfNotDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfNotDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfNotDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfNotDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
-- Deprecated as they are misnamed - should be AffirmIfNotDiff
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
-- Support for Specification / Requirements Tracking
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
procedure SetAlertLogJustify (Enable : boolean := TRUE) ;
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) ;
procedure ReportRequirements ;
procedure ReportAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (others => 0) ;
ReportAll : Boolean := FALSE
) ;
procedure ReportNonZeroAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (others => 0)
) ;
procedure WriteAlertYaml (
FileName : string ;
ExternalErrors : AlertCountType := (0,0,0) ;
Prefix : string := "" ;
PrintSettings : boolean := TRUE ;
PrintChildren : boolean := TRUE ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure WriteAlertSummaryYaml (FileName : string := "" ; ExternalErrors : AlertCountType := (0,0,0)) ;
procedure CreateYamlReport (ExternalErrors : AlertCountType := (0,0,0)) ; -- Deprecated. Use WriteAlertSummaryYaml.
-- impure function EndOfTestReports (
-- ReportAll : boolean := FALSE ;
-- ExternalErrors : AlertCountType := (0,0,0)
-- ) return integer ;
--
-- procedure EndOfTestReports (
-- ReportAll : boolean := FALSE ;
-- ExternalErrors : AlertCountType := (0,0,0) ;
-- Stop : boolean := FALSE
-- ) ;
--
-- alias EndOfTestSummary is EndOfTestReports[boolean, AlertCountType return integer] ;
-- alias EndOfTestSummary is EndOfTestReports[boolean, AlertCountType, boolean] ;
procedure WriteTestSummary (
FileName : string ;
OpenKind : File_Open_Kind := APPEND_MODE ;
Prefix : string := "" ;
Suffix : string := "" ;
ExternalErrors : AlertCountType := (0,0,0) ;
WriteFieldName : boolean := FALSE
) ;
procedure WriteTestSummaries ( FileName : string ; OpenKind : File_Open_Kind := WRITE_MODE ) ;
procedure ReportTestSummaries ;
procedure WriteAlerts (
FileName : string ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure WriteRequirements (
FileName : string ;
AlertLogID : AlertLogIDType := REQUIREMENT_ALERTLOG_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure ReadSpecification (FileName : string ; PassedGoal : integer := -1) ;
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean := FALSE
) ;
procedure ReadTestSummaries (FileName : string) ;
procedure ClearAlerts ;
procedure ClearAlertStopCounts ;
procedure ClearAlertCounts ;
function "ABS" (L : AlertCountType) return AlertCountType ;
function "+" (L, R : AlertCountType) return AlertCountType ;
function "-" (L, R : AlertCountType) return AlertCountType ;
function "-" (R : AlertCountType) return AlertCountType ;
impure function SumAlertCount(AlertCount: AlertCountType) return integer ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount return integer ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer ;
------------------------------------------------------------
-- log filtering for verbosity control, optionally has a separate file parameter
procedure Log(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) ;
------------------------------------------------------------
-- Alert Enables
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
impure function GetAlertEnable(Level : AlertType) return boolean ;
alias IsAlertEnabled is GetAlertEnable[AlertLogIDType, AlertType return boolean] ;
alias IsAlertEnabled is GetAlertEnable[AlertType return boolean] ;
-- Log Enables
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
impure function GetLogEnable(Level : LogType) return boolean ;
alias IsLogEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as GetLogEnable
alias IsLogEnabled is GetLogEnable [LogType return boolean] ; -- same as GetLogEnable
procedure ReportLogEnables ;
procedure SetAlertLogName(Name : string ) ;
-- synthesis translate_off
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string ;
-- synthesis translate_on
procedure DeallocateAlertLogStruct ;
procedure InitializeAlertLogStruct ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function NewID(
Name : string ;
ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ;
ReportMode : AlertLogReportModeType := ENABLED ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT ;
CreateHierarchy : boolean := TRUE
) return AlertLogIDType ;
impure function GetReqID(Name : string ; PassedGoal : integer := -1 ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ;
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) ;
-- synthesis translate_off
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string ;
-- synthesis translate_on
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) ;
-- synthesis translate_off
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string ;
-- synthesis translate_on
------------------------------------------------------------
-- Accessor Methods
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) ;
impure function GetAffirmCount return natural ;
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) ;
impure function GetAffirmPassedCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
procedure SetAlertStopCount(Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
impure function GetAlertStopCount(Level : AlertType) return integer ;
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
procedure SetAlertPrintCount( Level : AlertType ; Count : integer) ;
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
impure function GetAlertPrintCount( Level : AlertType) return integer ;
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Count : AlertCountType) ;
procedure SetAlertPrintCount( Count : AlertCountType) ;
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType) return AlertCountType ;
impure function GetAlertPrintCount return AlertCountType ;
procedure SetAlertLogPrintParent(AlertLogID : AlertLogIDType ; PrintParent : AlertLogPrintParentType) ;
procedure SetAlertLogPrintParent( PrintParent : AlertLogPrintParentType) ;
impure function GetAlertLogPrintParent(AlertLogID : AlertLogIDType) return AlertLogPrintParentType ;
impure function GetAlertLogPrintParent return AlertLogPrintParentType ;
procedure SetAlertLogReportMode(AlertLogID : AlertLogIDType ; ReportMode : AlertLogReportModeType) ;
procedure SetAlertLogReportMode( ReportMode : AlertLogReportModeType) ;
impure function GetAlertLogReportMode(AlertLogID : AlertLogIDType) return AlertLogReportModeType ;
impure function GetAlertLogReportMode return AlertLogReportModeType ;
------------------------------------------------------------
procedure SetAlertLogOptions (
FailOnWarning : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
FailOnRequirementErrors : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertErrorCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogErrorCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintPassed : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintAffirmations : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintDisabledAlerts : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintRequirements : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintIfHaveRequirements : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
DefaultPassedGoal : integer := integer'left ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT ;
IdSeparator : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ReportAlertLogOptions ;
-- synthesis translate_off
impure function GetAlertLogFailOnWarning return OsvvmOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return OsvvmOptionsType ;
impure function GetAlertLogFailOnRequirementErrors return OsvvmOptionsType ;
impure function GetAlertLogReportHierarchy return OsvvmOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertErrorCount return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertLevel return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertName return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertTime return OsvvmOptionsType ;
impure function GetAlertLogWriteLogErrorCount return OsvvmOptionsType ;
impure function GetAlertLogWriteLogLevel return OsvvmOptionsType ;
impure function GetAlertLogWriteLogName return OsvvmOptionsType ;
impure function GetAlertLogWriteLogTime return OsvvmOptionsType ;
impure function GetAlertLogPrintPassed return OsvvmOptionsType ;
impure function GetAlertLogPrintAffirmations return OsvvmOptionsType ;
impure function GetAlertLogPrintDisabledAlerts return OsvvmOptionsType ;
impure function GetAlertLogPrintRequirements return OsvvmOptionsType ;
impure function GetAlertLogPrintIfHaveRequirements return OsvvmOptionsType ;
impure function GetAlertLogDefaultPassedGoal return integer ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
-- File Reading Utilities
function IsLogEnableType (Name : String) return boolean ;
procedure ReadLogEnables (file AlertLogInitFile : text) ;
procedure ReadLogEnables (FileName : string) ;
-- String Helper Functions -- This should be in a more general string package
function PathTail (A : string) return string ;
------------------------------------------------------------
-- MetaMatch
-- Similar to STD_MATCH, except
-- it returns TRUE for U=U, X=X, Z=Z, and W=W
-- All other values are consistent with STD_MATCH
-- MetaMatch, BooleanTableType, and MetaMatchTable are derivatives
-- of STD_MATCH from IEEE.Numeric_Std copyright by IEEE.
-- Numeric_Std is also released under the Apache License, Version 2.0.
-- Coding Styles were updated to match OSVVM
------------------------------------------------------------
function MetaMatch (l, r : std_ulogic) return boolean ;
function MetaMatch (L, R : std_ulogic_vector) return boolean ;
function MetaMatch (L, R : unresolved_unsigned) return boolean ;
function MetaMatch (L, R : unresolved_signed) return boolean ;
------------------------------------------------------------
-- Helper function for NewID in data structures
function ResolvePrintParent (
------------------------------------------------------------
UniqueParent : boolean ;
PrintParent : AlertLogPrintParentType
) return AlertLogPrintParentType ;
-- synthesis translate_on
-- ------------------------------------------------------------
-- Deprecated
--
-- See NewID - consistency and parameter update. DoNotReport replaced by ReportMode
impure function GetAlertLogID(Name : string; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) return AlertLogIDType ;
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType ; -- := PASSED
AlertLevel : AlertType := ERROR
) ;
procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) ;
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) ;
procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) ;
alias IncAffirmCheckCount is IncAffirmCount [AlertLogIDType] ;
alias GetAffirmCheckCount is GetAffirmCount [return natural] ;
alias IsLoggingEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as IsLogEnabled
alias IsLoggingEnabled is GetLogEnable [LogType return boolean] ; -- same as IsLogEnabled
end AlertLogPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
use work.NamePkg.all ;
package body AlertLogPkg is
-- synthesis translate_off
-- instead of justify(to_upper(to_string())), just look up the upper case, left justified values
type AlertNameType is array(AlertType) of string(1 to 7) ;
constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER "
type LogNameType is array(LogType) of string(1 to 7) ;
constant LOG_NAME : LogNameType := (DEBUG => "DEBUG ", FINAL => "FINAL ", INFO => "INFO ", ALWAYS => "ALWAYS ", PASSED => "PASSED ") ; -- , NEVER => "NEVER "
------------------------------------------------------------
-- Package Local
function LeftJustify(A : String; Amount : integer) return string is
------------------------------------------------------------
constant Spaces : string(1 to maximum(1, Amount)) := (others => ' ') ;
begin
if A'length >= Amount then
return A ;
else
return A & Spaces(1 to Amount - A'length) ;
end if ;
end function LeftJustify ;
type AlertLogStructPType is protected
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) ;
------------------------------------------------------------
procedure IncAlertCount ( AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) ;
procedure SetJustify (
Enable : boolean := TRUE ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID
) ;
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) ;
procedure ReportRequirements ;
procedure ReportAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (0,0,0) ;
ReportAll : boolean := FALSE ;
ReportWhenZero : boolean := TRUE
) ;
procedure WriteAlertYaml (
FileName : string ;
ExternalErrors : AlertCountType := (0,0,0) ;
Prefix : string := "" ;
PrintSettings : boolean := TRUE ;
PrintChildren : boolean := TRUE ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure WriteTestSummary (
FileName : string ;
OpenKind : File_Open_Kind ;
Prefix : string ;
Suffix : string ;
ExternalErrors : AlertCountType ;
WriteFieldName : boolean
) ;
procedure WriteTestSummaries ( FileName : string ; OpenKind : File_Open_Kind ) ;
procedure ReportTestSummaries ;
procedure WriteAlerts (
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) ;
procedure WriteRequirements (
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) ;
procedure ReadSpecification (FileName : string ; PassedGoal : integer ) ;
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean ;
TestSummary : boolean
) ;
procedure ClearAlerts ;
procedure ClearAlertStopCounts ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
------------------------------------------------------------
-- FILE IO Controls
-- procedure SetTranscriptEnable (A : boolean := TRUE) ;
-- impure function IsTranscriptEnabled return boolean ;
-- procedure MirrorTranscript (A : boolean := TRUE) ;
-- impure function IsTranscriptMirrored return boolean ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) ;
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function NewID(
Name : string ;
ParentID : AlertLogIDType ;
ReportMode : AlertLogReportModeType ;
PrintParent : AlertLogPrintParentType ;
CreateHierarchy : boolean
) return AlertLogIDType ;
-- impure function GetAlertLogID(Name : string; ParentID : AlertLogIDType; CreateHierarchy : Boolean; DoNotReport : Boolean) return AlertLogIDType ;
impure function GetReqID(Name : string ; PassedGoal : integer ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ;
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) ;
procedure DeallocateAlertLogStruct ;
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) ;
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string ;
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) ;
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCount(AlertLogID : AlertLogIDType) ;
impure function GetAffirmCount return natural ;
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType) ;
impure function GetAffirmPassedCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Count : AlertCountType) ;
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType) return AlertCountType ;
procedure SetAlertLogPrintParent(AlertLogID : AlertLogIDType ; PrintParent : AlertLogPrintParentType) ;
impure function GetAlertLogPrintParent(AlertLogID : AlertLogIDType) return AlertLogPrintParentType ;
procedure SetAlertLogReportMode(AlertLogID : AlertLogIDType ; ReportMode : AlertLogReportModeType) ;
impure function GetAlertLogReportMode(AlertLogID : AlertLogIDType) return AlertLogReportModeType ;
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
procedure ReportLogEnables ;
------------------------------------------------------------
-- Reporting Accessor
procedure SetAlertLogOptions (
FailOnWarning : OsvvmOptionsType ;
FailOnDisabledErrors : OsvvmOptionsType ;
FailOnRequirementErrors : OsvvmOptionsType ;
ReportHierarchy : OsvvmOptionsType ;
WriteAlertErrorCount : OsvvmOptionsType ;
WriteAlertLevel : OsvvmOptionsType ;
WriteAlertName : OsvvmOptionsType ;
WriteAlertTime : OsvvmOptionsType ;
WriteLogErrorCount : OsvvmOptionsType ;
WriteLogLevel : OsvvmOptionsType ;
WriteLogName : OsvvmOptionsType ;
WriteLogTime : OsvvmOptionsType ;
PrintPassed : OsvvmOptionsType ;
PrintAffirmations : OsvvmOptionsType ;
PrintDisabledAlerts : OsvvmOptionsType ;
PrintRequirements : OsvvmOptionsType ;
PrintIfHaveRequirements : OsvvmOptionsType ;
DefaultPassedGoal : integer ;
AlertPrefix : string ;
LogPrefix : string ;
ReportPrefix : string ;
DoneName : string ;
PassName : string ;
FailName : string ;
IdSeparator : string
) ;
procedure ReportAlertLogOptions ;
impure function GetAlertLogFailOnWarning return OsvvmOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return OsvvmOptionsType ;
impure function GetAlertLogFailOnRequirementErrors return OsvvmOptionsType ;
impure function GetAlertLogReportHierarchy return OsvvmOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertErrorCount return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertLevel return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertName return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertTime return OsvvmOptionsType ;
impure function GetAlertLogWriteLogErrorCount return OsvvmOptionsType ;
impure function GetAlertLogWriteLogLevel return OsvvmOptionsType ;
impure function GetAlertLogWriteLogName return OsvvmOptionsType ;
impure function GetAlertLogWriteLogTime return OsvvmOptionsType ;
impure function GetAlertLogPrintPassed return OsvvmOptionsType ;
impure function GetAlertLogPrintAffirmations return OsvvmOptionsType ;
impure function GetAlertLogPrintDisabledAlerts return OsvvmOptionsType ;
impure function GetAlertLogPrintRequirements return OsvvmOptionsType ;
impure function GetAlertLogPrintIfHaveRequirements return OsvvmOptionsType ;
impure function GetAlertLogDefaultPassedGoal return integer ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
end protected AlertLogStructPType ;
--- ///////////////////////////////////////////////////////////////////////////
type AlertLogStructPType is protected body
variable GlobalAlertEnabledVar : boolean := TRUE ; -- Allows turn off and on
variable AffirmCheckCountVar : natural := 0 ;
variable PassedCountVar : natural := 0 ;
variable ErrorCount : integer := 0 ;
variable AlertCount : AlertCountType := (0, 0, 0) ;
------------------------------------------------------------
type AlertLogRecType is record
------------------------------------------------------------
Name : Line ;
NameLower : Line ;
Prefix : Line ;
Suffix : Line ;
ParentID : AlertLogIDType ;
ParentIDSet : Boolean ;
SiblingID : AlertLogIDType ;
ChildID : AlertLogIDType ;
ChildIDLast : AlertLogIDType ;
AlertCount : AlertCountType ;
DisabledAlertCount : AlertCountType ;
PassedCount : Integer ;
AffirmCount : Integer ;
PassedGoal : Integer ;
PassedGoalSet : Boolean ;
AlertStopCount : AlertCountType ;
AlertPrintCount : AlertCountType ;
AlertEnabled : AlertEnableType ;
LogEnabled : LogEnableType ;
ReportMode : AlertLogReportModeType ;
PrintParent : AlertLogPrintParentType ;
-- Used only by ReadTestSummaries
TotalErrors : integer ;
AffirmPassedCount : integer ;
-- IsRequirment : boolean ;
end record AlertLogRecType ;
------------------------------------------------------------
-- Basis for AlertLog Data Structure
variable NumAlertLogIDsVar : AlertLogIDType := 0 ; -- defined by initialize
variable NumAllocatedAlertLogIDsVar : AlertLogIDType := 0 ;
type AlertLogRecPtrType is access AlertLogRecType ;
type AlertLogArrayType is array (AlertLogIDType range <>) of AlertLogRecPtrType ;
type AlertLogArrayPtrType is access AlertLogArrayType ;
variable AlertLogPtr : AlertLogArrayPtrType ;
------------------------------------------------------------
-- Report formatting settings, with defaults
variable PrintPassedVar : boolean := TRUE ;
variable PrintAffirmationsVar : boolean := FALSE ;
variable PrintDisabledAlertsVar : boolean := FALSE ;
variable PrintRequirementsVar : boolean := FALSE ;
variable HasRequirementsVar : boolean := FALSE ;
variable PrintIfHaveRequirementsVar : boolean := TRUE ;
variable DefaultPassedGoalVar : integer := 1 ;
variable FailOnWarningVar : boolean := TRUE ;
variable FailOnDisabledErrorsVar : boolean := TRUE ;
variable FailOnRequirementErrorsVar : boolean := TRUE ;
variable ReportHierarchyVar : boolean := TRUE ;
variable FoundReportHierVar : boolean := FALSE ;
variable FoundAlertHierVar : boolean := FALSE ;
variable WriteAlertErrorCountVar : boolean := FALSE ;
variable WriteAlertLevelVar : boolean := TRUE ;
variable WriteAlertNameVar : boolean := TRUE ;
variable WriteAlertTimeVar : boolean := TRUE ;
variable WriteLogErrorCountVar : boolean := FALSE ;
variable WriteLogLevelVar : boolean := TRUE ;
variable WriteLogNameVar : boolean := TRUE ;
variable WriteLogTimeVar : boolean := TRUE ;
variable AlertPrefixVar : NamePType ;
variable LogPrefixVar : NamePType ;
variable ReportPrefixVar : NamePType ;
variable DoneNameVar : NamePType ;
variable PassNameVar : NamePType ;
variable FailNameVar : NamePType ;
variable IdSeparatorVar : NamePType ;
variable AlertLogJustifyAmountVar : integer := 0 ;
variable ReportJustifyAmountVar : integer := 0 ;
------------------------------------------------------------
-- PT Local
impure function VerifyID(
AlertLogID : AlertLogIDType ;
LowestID : AlertLogIDType := ALERTLOG_BASE_ID ;
InvalidID : AlertLogIDType := ALERTLOG_DEFAULT_ID
) return AlertLogIDType is
------------------------------------------------------------
begin
if AlertLogID < LowestID or AlertLogID > NumAlertLogIDsVar then
Alert("Invalid AlertLogID") ;
return InvalidID ;
else
return AlertLogID ;
end if ;
end function VerifyID ;
------------------------------------------------------------
procedure IncAffirmCount(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).AffirmCount := AlertLogPtr(localAlertLogID).AffirmCount + 1 ;
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmCount ;
------------------------------------------------------------
impure function GetAffirmCount return natural is
------------------------------------------------------------
begin
return AffirmCheckCountVar ;
end function GetAffirmCount ;
------------------------------------------------------------
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).PassedCount := AlertLogPtr(localAlertLogID).PassedCount + 1 ;
PassedCountVar := PassedCountVar + 1 ;
AlertLogPtr(localAlertLogID).AffirmCount := AlertLogPtr(localAlertLogID).AffirmCount + 1 ;
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmPassedCount ;
------------------------------------------------------------
impure function GetAffirmPassedCount return natural is
------------------------------------------------------------
begin
return PassedCountVar ;
end function GetAffirmPassedCount ;
------------------------------------------------------------
-- PT Local
procedure IncrementAlertCount(
------------------------------------------------------------
constant AlertLogID : in AlertLogIDType ;
constant Level : in AlertType ;
variable StopDueToCount : inout boolean ;
variable IncrementByAmount : in integer := 1
) is
begin
if AlertLogPtr(AlertLogID).AlertEnabled(Level) then
AlertLogPtr(AlertLogID).AlertCount(Level) := AlertLogPtr(AlertLogID).AlertCount(Level) + IncrementByAmount ;
-- Exceeded Stop Count at this level?
if AlertLogPtr(AlertLogID).AlertCount(Level) >= AlertLogPtr(AlertLogID).AlertStopCount(Level) then
StopDueToCount := TRUE ;
end if ;
-- Propagate counts to parent(s) -- Ascend Hierarchy
if AlertLogID /= ALERTLOG_BASE_ID then
IncrementAlertCount(AlertLogPtr(AlertLogID).ParentID, Level, StopDueToCount, IncrementByAmount) ;
end if ;
else
-- Disabled, increment disabled count
AlertLogPtr(AlertLogID).DisabledAlertCount(Level) := AlertLogPtr(AlertLogID).DisabledAlertCount(Level) + IncrementByAmount ;
end if ;
end procedure IncrementAlertCount ;
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) is
variable buf : Line ;
-- constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
variable ParentID : AlertLogIDType ;
begin
-- Only write and count when GlobalAlertEnabledVar is enabled
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
-- Write when Alert is Enabled
if AlertLogPtr(localAlertLogID).AlertEnabled(Level) and (AlertLogPtr(localAlertLogID).AlertCount(Level) < AlertLogPtr(localAlertLogID).AlertPrintCount(Level)) then
-- Print %% Alert (nominally)
-- write(buf, AlertPrefix) ;
write(buf, AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ) ;
-- Debug Mode
if WriteAlertErrorCountVar then
write(buf, ' ' & justify(to_string(ErrorCount + 1), RIGHT, 2));
end if ;
-- Level Name, when enabled (default)
if WriteAlertLevelVar then
write(buf, " " & ALERT_NAME(Level)) ; -- uses constant lookup
end if ;
-- AlertLog Name
if FoundAlertHierVar and WriteAlertNameVar then
if AlertLogPtr(localAlertLogID).PrintParent = PRINT_NAME then
write(buf, " in " & LeftJustify(AlertLogPtr(localAlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
else
ParentID := AlertLogPtr(localAlertLogID).ParentID ;
write(buf, " in " & LeftJustify(AlertLogPtr(ParentID).Name.all & ResolveOsvvmIdSeparator(IdSeparatorVar.GetOpt) &
AlertLogPtr(localAlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
end if ;
end if ;
-- Prefix
if AlertLogPtr(localAlertLogID).Prefix /= NULL then
write(buf, ' ' & AlertLogPtr(localAlertLogID).Prefix.all) ;
end if ;
-- Message
write(buf, " " & Message) ;
-- Suffix
if AlertLogPtr(localAlertLogID).Suffix /= NULL then
write(buf, ' ' & AlertLogPtr(localAlertLogID).Suffix.all) ;
end if ;
-- Time
if WriteAlertTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end if ;
-- Always Count
IncrementAlertCount(localAlertLogID, Level, StopDueToCount) ;
AlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount;
ErrorCount := SumAlertCount(AlertCount);
if StopDueToCount then
-- write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
write(buf, LF & AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(localAlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportWhenZero => TRUE) ;
if FileExists("OsvvmRun.yml") then
-- work.ReportPkg.EndOfTestReports ; -- creates circular package issues
WriteAlertSummaryYaml(
FileName => "OsvvmRun.yml"
) ;
WriteAlertYaml (
FileName => REPORTS_DIRECTORY & GetAlertLogName(ALERTLOG_BASE_ID) & "_alerts.yml"
) ;
end if ;
std.env.stop(ErrorCount) ;
end if ;
end if ;
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
level : AlertType := ERROR
) is
variable buf : Line ;
-- constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
IncrementAlertCount(localAlertLogID, Level, StopDueToCount) ;
AlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount;
ErrorCount := SumAlertCount(AlertCount);
if StopDueToCount then
-- write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
write(buf, LF & AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(localAlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportWhenZero => TRUE) ;
std.env.stop(ErrorCount) ;
end if ;
end if ;
end procedure IncAlertCount ;
------------------------------------------------------------
-- PT Local
impure function CalcJustify (AlertLogID : AlertLogIDType; CurrentLength : integer; IndentAmount : integer; IdSeparatorLength : integer) return integer_vector is
------------------------------------------------------------
variable ResultValues, LowerLevelValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented
variable CurID, ParentID : AlertLogIDType ;
variable ParentNameLen : integer ;
begin
ResultValues(1) := CurrentLength + 1 ; -- AlertLogJustifyAmountVar
ResultValues(2) := CurrentLength + IndentAmount ; -- ReportJustifyAmountVar
if AlertLogPtr(AlertLogID).PrintParent = PRINT_NAME_AND_PARENT then
ParentID := AlertLogPtr(AlertLogID).ParentID ;
ParentNameLen := AlertLogPtr(ParentID).Name'length ;
ResultValues(1) := IdSeparatorLength + ParentNameLen + ResultValues(1) ; -- AlertLogJustifyAmountVar
-- ResultValues(2) := IdSeparatorLength + ParentNameLen + ResultValues(2) ; -- ReportJustifyAmountVar
end if ;
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
LowerLevelValues := CalcJustify(CurID, AlertLogPtr(CurID).Name'length, IndentAmount + 2, IdSeparatorLength) ;
ResultValues(1) := maximum(ResultValues(1), LowerLevelValues(1)) ;
if AlertLogPtr(AlertLogID).ReportMode /= DISABLED then
ResultValues(2) := maximum(ResultValues(2), LowerLevelValues(2)) ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
return ResultValues ;
end function CalcJustify ;
------------------------------------------------------------
procedure SetJustify (
------------------------------------------------------------
Enable : boolean := TRUE ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID
) is
constant Separator : string := ResolveOsvvmIdSeparator(IdSeparatorVar.GetOpt) ;
begin
if Enable then
(AlertLogJustifyAmountVar, ReportJustifyAmountVar) := CalcJustify(AlertLogID, 0, 0, Separator'length) ;
else
AlertLogJustifyAmountVar := 0 ;
ReportJustifyAmountVar := 0 ;
end if;
end procedure SetJustify ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertCount ;
end function GetAlertCount ;
------------------------------------------------------------
-- Local
impure function RemoveNonFailingWarnings(A : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType ;
begin
Count := A ;
if not FailOnWarningVar then
Count(WARNING) := 0 ;
end if ;
return Count ;
end function RemoveNonFailingWarnings ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
variable Count : AlertCountType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return RemoveNonFailingWarnings( AlertLogPtr(localAlertLogID).AlertCount ) ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType := (others => 0) ;
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Count := Count + AlertLogPtr(i).DisabledAlertCount ;
--? Should excluded warnings get counted as disabled errors?
--? if not FailOnWarningVar then
--? Count(WARNING) := Count(WARNING) + AlertLogPtr(i).AlertCount(WARNING) ;
--? end if ;
end loop ;
return Count ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function LocalGetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType ;
variable CurID : AlertLogIDType ;
begin
Count := AlertLogPtr(AlertLogID).DisabledAlertCount ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
Count := Count + LocalGetDisabledAlertCount(CurID) ; -- Recursively descend into children
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
return Count ;
end function LocalGetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return LocalGetDisabledAlertCount(localAlertLogID) ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
-- Local GetRequirementsCount
-- Each bin contains a separate requirement
-- RequirementsGoal = # of bins with PassedGoal > 0
-- RequirementsPassed = # bins with PassedGoal > 0 and PassedCount > PassedGoal
procedure GetRequirementsCount(
AlertLogID : AlertLogIDType;
RequirementsPassed : out integer ;
RequirementsGoal : out integer
) is
------------------------------------------------------------
variable ChildRequirementsPassed, ChildRequirementsGoal : integer ;
variable CurID : AlertLogIDType ;
begin
RequirementsPassed := 0 ;
RequirementsGoal := 0 ;
if AlertLogPtr(AlertLogID).PassedGoal > 0 then
RequirementsGoal := 1 ;
if AlertLogPtr(AlertLogID).PassedCount >= AlertLogPtr(AlertLogID).PassedGoal then
RequirementsPassed := 1 ;
end if ;
end if ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
GetRequirementsCount(CurID, ChildRequirementsPassed, ChildRequirementsGoal) ;
RequirementsPassed := RequirementsPassed + ChildRequirementsPassed ;
RequirementsGoal := RequirementsGoal + ChildRequirementsGoal ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure GetRequirementsCount ;
------------------------------------------------------------
-- Only used at top level and superceded by variables PassedCountVar AffirmCheckCountVar
-- Local
procedure GetPassedAffirmCount(
AlertLogID : AlertLogIDType;
PassedCount : out integer ;
AffirmCount : out integer
) is
------------------------------------------------------------
variable ChildPassedCount, ChildAffirmCount : integer ;
variable CurID : AlertLogIDType ;
begin
PassedCount := AlertLogPtr(AlertLogID).PassedCount ;
AffirmCount := AlertLogPtr(AlertLogID).AffirmCount ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
GetPassedAffirmCount(CurID, ChildPassedCount, ChildAffirmCount) ;
PassedCount := PassedCount + ChildPassedCount ;
AffirmCount := AffirmCount + ChildAffirmCount ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure GetPassedAffirmCount ;
------------------------------------------------------------
-- Local
procedure CalcTopTotalErrors (
------------------------------------------------------------
constant ExternalErrors : in AlertCountType ;
variable TotalErrors : out integer ;
variable TotalAlertCount : out AlertCountType ;
variable TotalRequirementsPassed : out integer ;
variable TotalRequirementsCount : out integer
) is
variable DisabledAlertCount : AlertCountType ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementErrors : integer ;
begin
TotalAlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount + ExternalErrors ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(TotalAlertCount)) ;
TotalErrors := TotalAlertErrors ;
DisabledAlertCount := GetDisabledAlertCount(ALERTLOG_BASE_ID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
if FailOnDisabledErrorsVar then
TotalAlertCount := TotalAlertCount + DisabledAlertCount ;
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
end if ;
-- Perspective, 1 requirement per bin
GetRequirementsCount(ALERTLOG_BASE_ID, TotalRequirementsPassed, TotalRequirementsCount) ;
TotalRequirementErrors := TotalRequirementsCount - TotalRequirementsPassed ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
-- Set AffirmCount for top level
AlertLogPtr(ALERTLOG_BASE_ID).PassedCount := PassedCountVar ;
AlertLogPtr(ALERTLOG_BASE_ID).AffirmCount := AffirmCheckCountVar ;
end procedure CalcTopTotalErrors ;
------------------------------------------------------------
-- Local
impure function CalcTotalErrors (AlertLogID : AlertLogIDType) return integer is
------------------------------------------------------------
variable TotalErrors : integer ;
variable TotalAlertCount, DisabledAlertCount : AlertCountType ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsCount : integer ;
begin
TotalAlertCount := AlertLogPtr(AlertLogID).AlertCount ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(TotalAlertCount)) ;
TotalErrors := TotalAlertErrors ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
end if ;
-- Perspective, 1 requirement per bin
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsCount) ;
TotalRequirementErrors := TotalRequirementsCount - TotalRequirementsPassed ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
return TotalErrors ;
end function CalcTotalErrors ;
------------------------------------------------------------
-- PT Local
procedure PrintTopAlerts (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Name : string ;
ExternalErrors : AlertCountType ;
variable HasDisabledAlerts : inout Boolean ;
variable TestFailed : inout Boolean
) is
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
-- constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
-- constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
-- constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
variable TotalErrors : integer ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsGoal, TotalRequirementErrors : integer ;
variable AlertCountVar, DisabledAlertCount : AlertCountType ;
variable PassedCount, AffirmCheckCount : integer ;
begin
--!!
--!! Update to use CalcTopTotalErrors
--!!
AlertCountVar := AlertLogPtr(AlertLogID).AlertCount + ExternalErrors ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(AlertCountVar)) ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
HasDisabledAlerts := TotalDisabledAlertErrors /= 0 ;
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsGoal) ;
TotalRequirementErrors := TotalRequirementsGoal - TotalRequirementsPassed ;
TotalErrors := TotalAlertErrors ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
end if ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
TestFailed := TotalErrors /= 0 ;
GetPassedAffirmCount(AlertLogID, PassedCount, AffirmCheckCount) ;
if not TestFailed then
-- write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ; -- PASSED
write(buf,
ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & -- ReportPrefix
ResolveOsvvmDoneName(DoneNameVar.GetOpt) & " " & -- DoneName
ResolveOsvvmPassName(PassNameVar.GetOpt) & " " & -- PassName
Name
) ;
else
-- write(buf, ReportPrefix & DoneName & " " & FailName & " " & Name) ; -- FAILED
write(buf,
ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & -- ReportPrefix
ResolveOsvvmDoneName(DoneNameVar.GetOpt) & " " & -- DoneName
ResolveOsvvmFailName(FailNameVar.GetOpt) & " " & -- FailName
Name
) ;
end if ;
--? Also print when warnings exist and are hidden by FailOnWarningVar=FALSE
if TestFailed then
write(buf, " Total Error(s) = " & to_string(TotalErrors) ) ;
write(buf, " Failures: " & to_string(AlertCountVar(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCountVar(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCountVar(WARNING) ) ) ;
end if ;
if HasDisabledAlerts or PrintDisabledAlertsVar then -- print if exist or enabled
write(buf, " Total Disabled Error(s) = " & to_string(TotalDisabledAlertErrors)) ;
end if ;
if (HasDisabledAlerts and FailOnDisabledErrorsVar) or PrintDisabledAlertsVar then -- print if enabled
write(buf, " Failures: " & to_string(DisabledAlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(DisabledAlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(DisabledAlertCount(WARNING) ) ) ;
end if ;
if PrintPassedVar or (AffirmCheckCount /= 0) or PrintAffirmationsVar then -- Print if passed or printing affirmations
write(buf, " Passed: " & to_string(PassedCount)) ;
end if;
if (AffirmCheckCount /= 0) or PrintAffirmationsVar then
write(buf, " Affirmations Checked: " & to_string(AffirmCheckCount)) ;
end if ;
if PrintRequirementsVar or
(PrintIfHaveRequirementsVar and HasRequirementsVar) or
(FailOnRequirementErrorsVar and TotalRequirementErrors /= 0)
then
write(buf, " Requirements Passed: " & to_string(TotalRequirementsPassed) &
" of " & to_string(TotalRequirementsGoal) ) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
end procedure PrintTopAlerts ;
------------------------------------------------------------
-- PT Local
procedure PrintOneChild(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportWhenZero : boolean ;
HasErrors : boolean ;
HasDisabledErrors : boolean
) is
variable buf : line ;
alias CurID : AlertLogIDType is AlertLogID ;
begin
if ReportWhenZero or HasErrors then
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(CurID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
write(buf, " Failures: " & to_string(AlertLogPtr(CurID).AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(CurID).AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(CurID).AlertCount(WARNING) ) ) ;
if (HasDisabledErrors and FailOnDisabledErrorsVar) or PrintDisabledAlertsVar then
write(buf, " Disabled Failures: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(WARNING) ) ) ;
end if ;
if PrintPassedVar or PrintRequirementsVar then
write(buf, " Passed: " & to_string(AlertLogPtr(CurID).PassedCount)) ;
end if;
if PrintRequirementsVar then
write(buf, " of " & to_string(AlertLogPtr(CurID).PassedGoal) ) ;
end if ;
if PrintAffirmationsVar then
write(buf, " Affirmations: " & to_string(AlertLogPtr(CurID).AffirmCount ) ) ;
end if ;
WriteLine(buf) ;
end if ;
end procedure PrintOneChild ;
------------------------------------------------------------
-- PT Local
procedure IterateAndPrintChildren(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportWhenZero : boolean ;
HasDisabledErrors : boolean
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
variable HasErrors : boolean ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
-- Don't print requirements if there no requirements
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
HasErrors :=
(SumAlertCount(AlertLogPtr(CurID).AlertCount) > 0) or
(FailOnDisabledErrorsVar and (SumAlertCount(AlertLogPtr(CurID).DisabledAlertCount) > 0)) or
(FailOnRequirementErrorsVar and (AlertLogPtr(CurID).PassedCount < AlertLogPtr(CurID).PassedGoal)) ;
if AlertLogPtr(CurID).ReportMode = ENABLED or (AlertLogPtr(CurID).ReportMode = NONZERO and HasErrors) then
PrintOneChild(
AlertLogID => CurID,
Prefix => Prefix,
IndentAmount => IndentAmount,
ReportWhenZero => ReportWhenZero,
HasErrors => HasErrors,
HasDisabledErrors => HasDisabledErrors
) ;
IterateAndPrintChildren(
AlertLogID => CurID,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2,
ReportWhenZero => ReportWhenZero,
HasDisabledErrors => HasDisabledErrors
) ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure IterateAndPrintChildren ;
------------------------------------------------------------
procedure ReportAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (0,0,0) ;
ReportAll : boolean := FALSE ;
ReportWhenZero : boolean := TRUE
) is
------------------------------------------------------------
variable TestFailed, HasDisabledErrors : boolean ;
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
variable TurnedOnJustify : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
if IsOsvvmStringSet(Name) then
PrintTopAlerts (
AlertLogID => localAlertLogID,
Name => Name,
ExternalErrors => ExternalErrors,
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
else
PrintTopAlerts (
AlertLogID => localAlertLogID,
Name => AlertLogPtr(localAlertLogID).Name.all,
ExternalErrors => ExternalErrors,
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
end if ;
--Print Hierarchy when enabled and test failed
if ReportAll or (FoundReportHierVar and ReportHierarchyVar and TestFailed) then
-- (NumErrors /= 0 or (NumDisabledErrors /=0 and FailOnDisabledErrorsVar)) then
IterateAndPrintChildren(
AlertLogID => localAlertLogID,
-- Prefix => ReportPrefix & " ",
Prefix => ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & " ",
IndentAmount => 2,
ReportWhenZero => ReportAll or ReportWhenZero,
HasDisabledErrors => HasDisabledErrors -- NumDisabledErrors /= 0
) ;
end if ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportRequirements is
------------------------------------------------------------
variable TestFailed, HasDisabledErrors : boolean ;
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
variable TurnedOnJustify : boolean := FALSE ;
variable SavedPrintRequirementsVar : boolean ;
begin
SavedPrintRequirementsVar := PrintRequirementsVar ;
PrintRequirementsVar := TRUE ;
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
PrintTopAlerts (
AlertLogID => ALERTLOG_BASE_ID,
Name => AlertLogPtr(ALERTLOG_BASE_ID).Name.all,
ExternalErrors => (0,0,0),
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
IterateAndPrintChildren(
AlertLogID => REQUIREMENT_ALERTLOG_ID,
-- Prefix => ReportPrefix & " ",
Prefix => ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & " ",
IndentAmount => 2,
ReportWhenZero => TRUE,
HasDisabledErrors => HasDisabledErrors -- NumDisabledErrors /= 0
) ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
PrintRequirementsVar := SavedPrintRequirementsVar ;
end procedure ReportRequirements ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) is
------------------------------------------------------------
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
-- constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
-- constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
-- constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
variable NumErrors : integer ;
begin
NumErrors := SumAlertCount(AlertCount) ;
if NumErrors = 0 then
-- Passed
-- write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ;
write(buf,
ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) & -- ReportPrefix
ResolveOsvvmDoneName(DoneNameVar.GetOpt) & " " & -- DoneName
ResolveOsvvmPassName(PassNameVar.GetOpt) & " " & -- PassName
Name
) ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
else
-- Failed
-- write(buf, ReportPrefix & DoneName & " " & FailName & " "& Name) ;
write(buf,
ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) & -- ReportPrefix
ResolveOsvvmDoneName(DoneNameVar.GetOpt) & " " & -- DoneName
ResolveOsvvmFailName(FailNameVar.GetOpt) & " " & -- FailName
Name
) ;
write(buf, " Total Error(s) = " & to_string(NumErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
writeLine(buf) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
-- pt local
procedure WriteOneAlertYaml (
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType ;
TotalErrors : integer ;
RequirementsPassed : integer ;
RequirementsGoal : integer ;
FirstPrefix : string := "" ;
Prefix : string := ""
) is
variable buf : line ;
constant DELIMITER : string := ", " ;
begin
Write(buf,
FirstPrefix & "Name: " & '"' & AlertLogPtr(AlertLogID).Name.all & '"' & LF &
Prefix & "Status: " & IfElse(TotalErrors=0, "PASSED", "FAILED") & LF &
Prefix & "Results: {" &
"TotalErrors: " & to_string( TotalErrors ) & DELIMITER &
"AlertCount: {" &
"Failure: " & to_string( AlertLogPtr(AlertLogID).AlertCount(FAILURE) ) & DELIMITER &
"Error: " & to_string( AlertLogPtr(AlertLogID).AlertCount(ERROR) ) & DELIMITER &
"Warning: " & to_string( AlertLogPtr(AlertLogID).AlertCount(WARNING) ) &
"}" & DELIMITER &
"PassedCount: " & to_string( AlertLogPtr(AlertLogID).PassedCount ) & DELIMITER &
"AffirmCount: " & to_string( AlertLogPtr(AlertLogID).AffirmCount ) & DELIMITER &
"RequirementsPassed: " & to_string( RequirementsPassed ) & DELIMITER &
"RequirementsGoal: " & to_string( RequirementsGoal ) & DELIMITER &
"DisabledAlertCount: {" &
"Failure: " & to_string( AlertLogPtr(AlertLogID).DisabledAlertCount(FAILURE) ) & DELIMITER &
"Error: " & to_string( AlertLogPtr(AlertLogID).DisabledAlertCount(ERROR) ) & DELIMITER &
"Warning: " & to_string( AlertLogPtr(AlertLogID).DisabledAlertCount(WARNING) ) &
"}" &
"}"
) ;
WriteLine(TestFile, buf) ;
end procedure WriteOneAlertYaml ;
------------------------------------------------------------
-- PT Local
procedure IterateAndWriteChildrenYaml(
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType ;
Prefix : string
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
variable RequirementsPassed, RequirementsGoal : integer ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
if CurID >= ALERTLOG_BASE_ID then
-- Write "Children:" at current level
Write(buf, Prefix & "Children: " ) ;
WriteLine(TestFile, buf) ;
while CurID > ALERTLOG_BASE_ID loop
-- Don't print requirements if there no requirements
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
if AlertLogPtr(CurID).PassedGoalSet and (RequirementsGoal > 0) then
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
else
RequirementsPassed := 0 ;
RequirementsGoal := 0 ;
end if ;
if AlertLogPtr(AlertLogID).ReportMode /= DISABLED then
WriteOneAlertYaml(
TestFile => TestFile,
AlertLogID => CurID,
TotalErrors => CalcTotalErrors(CurID),
RequirementsPassed => RequirementsPassed,
RequirementsGoal => RequirementsGoal,
FirstPrefix => Prefix & " - ",
Prefix => Prefix & " "
) ;
IterateAndWriteChildrenYaml(
TestFile => TestFile,
AlertLogID => CurID,
Prefix => Prefix & " "
) ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
else
-- No Children, Print Empty List
Write(buf, Prefix & "Children: {}" ) ;
WriteLine(TestFile, buf) ;
end if ;
end procedure IterateAndWriteChildrenYaml ;
------------------------------------------------------------
-- pt local
procedure WriteSettingsYaml (
------------------------------------------------------------
file TestFile : text ;
ExternalErrors : AlertCountType ;
Prefix : string := ""
) is
variable buf : line ;
constant DELIMITER : string := ", " ;
begin
Write(buf,
Prefix & "Settings: {" &
"ExternalErrors: {" &
"Failure: " & '"' & to_string( ExternalErrors(FAILURE) ) & '"' & DELIMITER &
"Error: " & '"' & to_string( ExternalErrors(ERROR) ) & '"' & DELIMITER &
"Warning: " & '"' & to_string( ExternalErrors(WARNING) ) & '"' &
"}" & DELIMITER &
"FailOnDisabledErrors: " & '"' & to_string( FailOnDisabledErrorsVar ) & '"' & DELIMITER &
"FailOnRequirementErrors: " & '"' & to_string( FailOnRequirementErrorsVar ) & '"' & DELIMITER &
"FailOnWarning: " & '"' & to_string( FailOnWarningVar ) & '"' &
"}"
) ;
WriteLine(TestFile, buf) ;
end procedure WriteSettingsYaml ;
------------------------------------------------------------
-- pt local
procedure WriteAlertYaml (
------------------------------------------------------------
file TestFile : text ;
ExternalErrors : AlertCountType ;
Prefix : string ;
PrintSettings : boolean ;
PrintChildren : boolean
) is
-- Format: Action Count min1 max1 min2 max2
variable TotalErrors : integer ;
variable TotalAlertCount : AlertCountType ;
variable TotalRequirementsPassed, TotalRequirementsCount : integer ;
begin
CalcTopTotalErrors (
ExternalErrors => ExternalErrors ,
TotalErrors => TotalErrors ,
TotalAlertCount => TotalAlertCount ,
TotalRequirementsPassed => TotalRequirementsPassed,
TotalRequirementsCount => TotalRequirementsCount
) ;
WriteOneAlertYaml (
TestFile => TestFile,
AlertLogID => ALERTLOG_BASE_ID,
TotalErrors => TotalErrors,
RequirementsPassed => TotalRequirementsPassed,
RequirementsGoal => TotalRequirementsCount,
FirstPrefix => Prefix,
Prefix => Prefix
) ;
if PrintSettings then
WriteSettingsYaml(
TestFile => TestFile,
ExternalErrors => ExternalErrors,
Prefix => Prefix
) ;
end if ;
if PrintChildren then
IterateAndWriteChildrenYaml(
TestFile => TestFile,
AlertLogID => ALERTLOG_BASE_ID,
Prefix => Prefix
) ;
end if ;
end procedure WriteAlertYaml ;
------------------------------------------------------------
procedure WriteAlertYaml (
------------------------------------------------------------
FileName : string ;
ExternalErrors : AlertCountType := (0,0,0) ;
Prefix : string := "" ;
PrintSettings : boolean := TRUE ;
PrintChildren : boolean := TRUE ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
file FileID : text ;
variable status : file_open_status ;
begin
file_open(status, FileID, FileName, OpenKind) ;
if status = OPEN_OK then
WriteAlertYaml(FileID, ExternalErrors, Prefix, PrintSettings, PrintChildren) ;
file_close(FileID) ;
else
Alert("WriteAlertYaml, File: " & FileName & " did not open for " & to_string(OpenKind)) ;
end if ;
end procedure WriteAlertYaml ;
------------------------------------------------------------
-- PT Local
impure function IsRequirement(AlertLogID : AlertLogIDType) return boolean is
------------------------------------------------------------
begin
if AlertLogID = REQUIREMENT_ALERTLOG_ID then
return TRUE ;
elsif AlertLogID <= ALERTLOG_BASE_ID then
return FALSE ;
else
return IsRequirement(AlertLogPtr(AlertLogID).ParentID) ;
end if ;
end function IsRequirement ;
------------------------------------------------------------
-- pt local
procedure WriteOneTestSummary (
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType ;
RequirementsGoal : integer ;
RequirementsPassed : integer ;
TotalErrors : integer ;
AlertCount : AlertCountType ;
AffirmCount : integer ;
PassedCount : integer ;
Delimiter : string ;
Prefix : string := "" ;
Suffix : string := "" ;
WriteFieldName : boolean := FALSE
) is
variable buf : line ;
begin
-- Should disabled errors be included here?
-- In the previous step, we counted DisabledErrors as a regular error if FailOnDisabledErrorsVar (default TRUE)
Write(buf,
Prefix &
IfElse(WriteFieldName, "Status: " & IfElse(TotalErrors=0, "PASSED", "FAILED") & LF, "") &
IfElse(WriteFieldName, Prefix & "Results: {Name: ", "") &
AlertLogPtr(AlertLogID).Name.all & Delimiter &
IfElse(WriteFieldName, "RequirementsGoal: ", "") &
to_string( RequirementsGoal ) & Delimiter &
IfElse(WriteFieldName, "RequirementsPassed: ", "") &
to_string( RequirementsPassed ) & Delimiter &
IfElse(WriteFieldName, "TotalErrors: ", "") &
to_string( TotalErrors ) & Delimiter &
IfElse(WriteFieldName, "Failure: ", "") &
to_string( AlertCount(FAILURE) ) & Delimiter &
IfElse(WriteFieldName, "Error: ", "") &
to_string( AlertCount(ERROR) ) & Delimiter &
IfElse(WriteFieldName, "Warning: ", "") &
to_string( AlertCount(WARNING) ) & Delimiter &
IfElse(WriteFieldName, "AffirmCount: ", "") &
to_string( AffirmCount ) & Delimiter &
IfElse(WriteFieldName, "PassedCount: ", "") &
to_string( PassedCount ) &
IfElse(WriteFieldName, "}", "") &
Suffix
) ;
-- ## Write(buf,
-- ## Prefix &
-- ## IfElse(WriteFieldName, "Status: " & IfElse(TotalErrors=0, "PASSED", "FAILED") & Delimiter, "") &
-- ## IfElse(WriteFieldName, "Name: ", "") &
-- ## AlertLogPtr(AlertLogID).Name.all & Delimiter &
-- ## IfElse(WriteFieldName, "RequirementsGoal: ", "") &
-- ## to_string( RequirementsGoal ) & Delimiter &
-- ## IfElse(WriteFieldName, "RequirementsPassed: ", "") &
-- ## to_string( RequirementsPassed ) & Delimiter &
-- ## IfElse(WriteFieldName, "TotalErrors: ", "") &
-- ## to_string( TotalErrors ) & Delimiter &
-- ## IfElse(WriteFieldName, "Failure: ", "") &
-- ## to_string( AlertCount(FAILURE) ) & Delimiter &
-- ## IfElse(WriteFieldName, "Error: ", "") &
-- ## to_string( AlertCount(ERROR) ) & Delimiter &
-- ## IfElse(WriteFieldName, "Warning: ", "") &
-- ## to_string( AlertCount(WARNING) ) & Delimiter &
-- ## IfElse(WriteFieldName, "AffirmCount: ", "") &
-- ## to_string( AffirmCount ) & Delimiter &
-- ## IfElse(WriteFieldName, "PassedCount: ", "") &
-- ## to_string( PassedCount ) & Suffix
-- ## ) ;
WriteLine(TestFile, buf) ;
end procedure WriteOneTestSummary ;
------------------------------------------------------------
-- pt local
procedure WriteTestSummary (
------------------------------------------------------------
file TestFile : text ;
Prefix : string := "" ;
Suffix : string := "" ;
ExternalErrors : AlertCountType := (0,0,0) ;
WriteFieldName : boolean := FALSE
) is
-- Format: Action Count min1 max1 min2 max2
variable TotalErrors : integer ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsGoal : integer ;
variable TotalRequirementErrors : integer ;
variable TotalAlertCount, DisabledAlertCount : AlertCountType ;
constant AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
variable PassedCount, AffirmCount : integer ;
constant DELIMITER : string := ", " ;
begin
--!!
--!! Update to use CalcTopTotalErrors
--!!
TotalAlertCount := AlertLogPtr(AlertLogID).AlertCount + ExternalErrors ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(TotalAlertCount)) ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsGoal) ;
TotalRequirementErrors := TotalRequirementsGoal - TotalRequirementsPassed ;
TotalErrors := TotalAlertErrors ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
TotalAlertCount := TotalAlertCount + DisabledAlertCount ;
end if ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
GetPassedAffirmCount(AlertLogID, PassedCount, AffirmCount) ;
WriteOneTestSummary(
TestFile => TestFile,
AlertLogID => AlertLogID,
RequirementsGoal => TotalRequirementsGoal,
RequirementsPassed => TotalRequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => TotalAlertCount,
AffirmCount => AffirmCount,
PassedCount => PassedCount,
Delimiter => DELIMITER,
Prefix => Prefix,
Suffix => Suffix,
WriteFieldName => WriteFieldName
) ;
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummary (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind ;
Prefix : string ;
Suffix : string ;
ExternalErrors : AlertCountType ;
WriteFieldName : boolean
) is
-- Format: Action Count min1 max1 min2 max2
file TestFile : text open OpenKind is FileName ;
begin
WriteTestSummary(TestFile => TestFile, Prefix => Prefix, Suffix => Suffix, ExternalErrors => ExternalErrors, WriteFieldName => WriteFieldName) ;
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummaries ( -- PT Local
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType
) is
variable CurID : AlertLogIDType ;
variable TotalErrors, RequirementsGoal, RequirementsPassed : integer ;
begin
-- Descend from WriteRequirements
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
TotalErrors := AlertLogPtr(CurID).TotalErrors ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
if AlertLogPtr(CurID).AffirmCount <= 0 and FailOnRequirementErrorsVar and
(RequirementsGoal > RequirementsPassed) then
-- Add errors for tests that did not run.
TotalErrors := RequirementsGoal - RequirementsPassed ;
end if ;
WriteOneTestSummary(
TestFile => TestFile,
AlertLogID => CurID,
RequirementsGoal => RequirementsGoal,
RequirementsPassed => RequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => AlertLogPtr(CurID).AlertCount,
AffirmCount => AlertLogPtr(CurID).AffirmCount,
PassedCount => AlertLogPtr(CurID).AffirmPassedCount,
Delimiter => ","
) ;
WriteTestSummaries(TestFile, CurID) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure WriteTestSummaries (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file TestFile : text open OpenKind is FileName ;
begin
WriteTestSummaries(
TestFile => TestFile,
AlertLogID => REQUIREMENT_ALERTLOG_ID
) ;
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure ReportOneTestSummary ( -- PT Local
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
RequirementsGoal : integer ;
RequirementsPassed : integer ;
TotalErrors : integer ;
AlertCount : AlertCountType ;
AffirmCount : integer ;
PassedCount : integer ;
Delimiter : string
) is
variable buf : line ;
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
-- constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
-- constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
begin
-- write(buf, ReportPrefix & " ") ;
write(buf, ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & " ") ;
if (AffirmCount > 0) and (TotalErrors = 0) then
-- write(buf, PassName) ;
write(buf, ResolveOsvvmPassName(PassNameVar.GetOpt)) ;
elsif TotalErrors > 0 then
-- write(buf, FailName) ;
write(buf, ResolveOsvvmFailName(FailNameVar.GetOpt)) ;
else
write(buf, string'("ReportTestSummaries Warning: No checking done. ")) ;
end if ;
write(buf, " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar)) ;
write(buf, " Total Error(s) = " & to_string(TotalErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
write(buf, " Affirmations Passed: " & to_string(PassedCount) &
" of " & to_string(AffirmCount)) ;
write(buf, " Requirements Passed: " & to_string(RequirementsPassed) &
" of " & to_string(RequirementsGoal) ) ;
WriteLine(buf) ;
end procedure ReportOneTestSummary ;
------------------------------------------------------------
procedure ReportTestSummaries ( -- PT Local
------------------------------------------------------------
AlertLogID : AlertLogIDType
) is
variable CurID : AlertLogIDType ;
variable TotalErrors, RequirementsGoal, RequirementsPassed : integer ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
TotalErrors := AlertLogPtr(CurID).TotalErrors ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
if AlertLogPtr(CurID).AffirmCount <= 0 and FailOnRequirementErrorsVar and
(RequirementsGoal > RequirementsPassed) then
-- Add errors for tests that did not run.
TotalErrors := RequirementsGoal - RequirementsPassed ;
end if ;
ReportOneTestSummary(
AlertLogID => CurID,
RequirementsGoal => RequirementsGoal,
RequirementsPassed => RequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => AlertLogPtr(CurID).AlertCount,
AffirmCount => AlertLogPtr(CurID).AffirmCount,
PassedCount => AlertLogPtr(CurID).AffirmPassedCount,
Delimiter => ","
) ;
ReportTestSummaries(
AlertLogID => CurID
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure ReportTestSummaries is
------------------------------------------------------------
variable IgnoredValue, OldReportJustifyAmount : integer ;
constant Separator : string := ResolveOsvvmIdSeparator(IdSeparatorVar.GetOpt) ;
begin
OldReportJustifyAmount := ReportJustifyAmountVar ;
(IgnoredValue, ReportJustifyAmountVar) := CalcJustify(REQUIREMENT_ALERTLOG_ID, 0, 0, Separator'length) ;
ReportTestSummaries(AlertLogID => REQUIREMENT_ALERTLOG_ID) ;
ReportJustifyAmountVar := OldReportJustifyAmount ;
end procedure ReportTestSummaries ;
------------------------------------------------------------
-- pt local
procedure WriteAlerts ( -- pt local
file AlertsFile : text ;
AlertLogID : AlertLogIDType
) is
------------------------------------------------------------
-- Format: Name, PassedGoal, #Passed, #TotalErrors, FAILURE, ERROR, WARNING, Affirmations
variable buf : line ;
variable AlertCountVar : AlertCountType ;
constant DELIMITER : character := ',' ;
variable CurID : AlertLogIDType ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
write(buf, AlertLogPtr(CurID).Name.all) ;
write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedGoal)) ;
-- Handling for PassedCount > PassedGoal done in ReadRequirements
write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedCount)) ;
AlertCountVar := AlertLogPtr(CurID).AlertCount ;
if FailOnDisabledErrorsVar then
AlertCountVar := AlertCountVar + AlertLogPtr(CurID).DisabledAlertCount ;
end if;
-- TotalErrors
write(buf, DELIMITER & to_string( SumAlertCount(RemoveNonFailingWarnings(AlertCountVar)))) ;
write(buf, DELIMITER & to_string( AlertCountVar(FAILURE) )) ;
write(buf, DELIMITER & to_string( AlertCountVar(ERROR) )) ;
write(buf, DELIMITER & to_string( AlertCountVar(WARNING) )) ;
write(buf, DELIMITER & to_string( AlertLogPtr(CurID).AffirmCount )) ;
-- write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedCount)) ; -- redundancy intentional, for reading WriteTestSummary
WriteLine(AlertsFile, buf) ;
WriteAlerts(AlertsFile, CurID) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure WriteAlerts ;
------------------------------------------------------------
procedure WriteRequirements (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file RequirementsFile : text open OpenKind is FileName ;
variable LocalAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
WriteTestSummary(RequirementsFile) ;
if IsRequirement(localAlertLogID) then
WriteAlerts(RequirementsFile, localAlertLogID) ;
else
Alert("WriteRequirements: Called without a Requirement") ;
WriteAlerts(RequirementsFile, REQUIREMENT_ALERTLOG_ID) ;
end if ;
end procedure WriteRequirements ;
------------------------------------------------------------
procedure WriteAlerts (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file AlertsFile : text open OpenKind is FileName ;
variable LocalAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
WriteTestSummary(AlertsFile) ;
WriteAlerts(AlertsFile, localAlertLogID) ;
end procedure WriteAlerts ;
------------------------------------------------------------
procedure ReadSpecification (file SpecificationFile : text ; PassedGoalIn : integer ) is -- PT Local
------------------------------------------------------------
variable buf,Name,Description : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable PassedGoal : integer ;
variable PassedGoalSet : boolean ;
variable Char : character ;
constant DELIMITER : character := ',' ;
variable AlertLogID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
-- Format: Spec Name, [Spec Description = "",] [Requirement Goal = 0]
ReadFileLoop : while not EndFile(SpecificationFile) loop
ReadLoop : loop
ReadLine(SpecificationFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadFileLoop when Empty ;
-- defaults
PassedGoal := DefaultPassedGoalVar ;
PassedGoalSet := FALSE ;
-- Read Name and Remove delimiter
ReadUntilDelimiterOrEOL(buf, Name, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading Name", FAILURE) ;
-- If rest of line is blank or comment, then skip it.
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ReadLoop when Empty ;
-- Optional: Read Description
ReadUntilDelimiterOrEOL(buf, Description, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading Description", FAILURE) ;
if IsNumber(Description.all) then
read(Description, PassedGoal, ReadValid) ;
deallocate(Description) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading PassedGoal (while skipping Description)", FAILURE) ;
PassedGoalSet := TRUE ;
else
-- If rest of line is blank or comment, then skip it.
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ReadLoop when Empty ;
-- Read PassedGoal
read(buf, PassedGoal, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading PassedGoal", FAILURE) ;
PassedGoalSet := TRUE ;
end if ;
exit ReadLoop ;
end loop ReadLoop ;
-- AlertLogID := GetReqID(Name.all) ; -- For new items, sets DefaultPassedGoalVar and PassedGoalSet = FALSE.
AlertLogID := GetReqID(Name => Name.all, PassedGoal => -1, ParentID=> ALERTLOG_ID_NOT_ASSIGNED, CreateHierarchy => TRUE) ;
deallocate(Name) ;
deallocate(Description) ; -- not used
-- Implementation 1: Just put the values in
-- If Override values specified, then use them.
if PassedGoalIn >= 0 then
PassedGoal := PassedGoalIn ;
PassedGoalSet := TRUE ;
end if ;
if PassedGoalSet then
-- Is there a goal to update?
if AlertLogPtr(AlertLogID).PassedGoalSet then
-- Merge Old and New
AlertLogPtr(AlertLogID).PassedGoal := maximum(PassedGoal, AlertLogPtr(AlertLogID).PassedGoal) ;
else
-- No Old, Just use New
AlertLogPtr(AlertLogID).PassedGoal := PassedGoal ;
end if ;
AlertLogPtr(AlertLogID).PassedGoalSet := TRUE ;
end if ;
end loop ReadFileLoop ;
end procedure ReadSpecification ;
------------------------------------------------------------
procedure ReadSpecification (FileName : string ; PassedGoal : integer ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file SpecificationFile : text open READ_MODE is FileName ;
begin
ReadSpecification(SpecificationFile, PassedGoal) ;
end procedure ReadSpecification ;
------------------------------------------------------------
-- PT Local
procedure ReadRequirements ( -- PT Local
file RequirementsFile : text ;
ThresholdPassed : boolean ;
TestSummary : boolean
) is
------------------------------------------------------------
constant DELIMITER : character := ',' ;
variable buf,Name : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable StopDueToCount : boolean := FALSE ;
-- variable ReadFailed : boolean := TRUE ;
variable Found : boolean ;
variable ReqPassedGoal : integer ;
variable ReqPassedCount : integer ;
variable TotalErrorCount : integer ;
variable AlertCount : AlertCountType ;
variable AffirmCount : integer ;
variable AffirmPassedCount : integer ;
variable AlertLogID : AlertLogIDType ;
begin
if not TestSummary then
-- For requirements, skip the first line that has the test summary
ReadLine(RequirementsFile, buf) ;
end if ;
ReadFileLoop : while not EndFile(RequirementsFile) loop
ReadLoop : loop
ReadLine(RequirementsFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadFileLoop when Empty ;
-- defaults
-- ReadFailed := TRUE ;
ReqPassedGoal := 0 ;
ReqPassedCount := 0 ;
TotalErrorCount := 0 ;
AlertCount := (0, 0, 0) ;
AffirmCount := 0 ;
AffirmPassedCount := 0 ;
-- Read Name. Remove delimiter
ReadUntilDelimiterOrEOL(buf, Name, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading Name", FAILURE) ;
-- Read ReqPassedGoal
read(buf, ReqPassedGoal, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading PassedGoal", FAILURE) ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedGoal", FAILURE) ;
-- Read ReqPassedCount
read(buf, ReqPassedCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading PassedCount", FAILURE) ;
AffirmPassedCount := ReqPassedGoal ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedCount", FAILURE) ;
-- Read TotalErrorCount
read(buf, TotalErrorCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading TotalErrorCount", FAILURE) ;
AlertCount := (0, TotalErrorCount, 0) ; -- Default
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedCount", FAILURE) ;
-- Read AlertCount
for i in AlertType'left to AlertType'right loop
read(buf, AlertCount(i), ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading " &
"AlertCount(" & to_string(i) & ")", FAILURE) ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading " &
"AlertCount(" & to_string(i) & ")", FAILURE) ;
end loop ;
-- Read AffirmCount
read(buf, AffirmCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading AffirmCount", FAILURE) ;
if TestSummary then
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading AffirmCount", FAILURE) ;
-- Read AffirmPassedCount
read(buf, AffirmPassedCount, ReadValid) ;
if not ReadValid then
AffirmPassedCount := ReqPassedGoal ;
Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadRequirements: Failed while reading AffirmPassedCount", FAILURE) ;
exit ReadFileLoop ;
end if ;
end if ;
exit ReadLoop ;
end loop ReadLoop ;
-- AlertLogID := GetReqID(Name.all) ;
AlertLogID := GetReqID(Name => Name.all, PassedGoal => -1, ParentID=> ALERTLOG_ID_NOT_ASSIGNED, CreateHierarchy => TRUE) ; --! GHDL
deallocate(Name) ;
-- if Merge then
-- Passed Goal
if AlertLogPtr(AlertLogID).PassedGoalSet then
AlertLogPtr(AlertLogID).PassedGoal := maximum(AlertLogPtr(AlertLogID).PassedGoal, ReqPassedGoal) ;
else
AlertLogPtr(AlertLogID).PassedGoal := ReqPassedGoal ;
end if ;
-- Requirements Passed Count
if ThresholdPassed then
ReqPassedCount := minimum(ReqPassedCount, ReqPassedGoal) ;
end if ;
AlertLogPtr(AlertLogID).PassedCount := AlertLogPtr(AlertLogID).PassedCount + ReqPassedCount ;
AlertLogPtr(AlertLogID).TotalErrors := AlertLogPtr(AlertLogID).TotalErrors + TotalErrorCount ;
-- AlertCount
IncrementAlertCount(AlertLogID, FAILURE, StopDueToCount, AlertCount(FAILURE)) ;
IncrementAlertCount(AlertLogID, ERROR, StopDueToCount, AlertCount(ERROR)) ;
IncrementAlertCount(AlertLogID, WARNING, StopDueToCount, AlertCount(WARNING)) ;
-- AffirmCount
AlertLogPtr(AlertLogID).AffirmCount := AlertLogPtr(AlertLogID).AffirmCount + AffirmCount ;
AlertLogPtr(AlertLogID).AffirmPassedCount := AlertLogPtr(AlertLogID).AffirmPassedCount + AffirmPassedCount ;
-- else
-- AlertLogPtr(AlertLogID).PassedGoal := ReqPassedGoal ;
-- AlertLogPtr(AlertLogID).PassedCount := ReqPassedCount ;
--
-- IncrementAlertCount(AlertLogID, FAILURE, StopDueToCount, AlertCount(FAILURE)) ;
-- IncrementAlertCount(AlertLogID, ERROR, StopDueToCount, AlertCount(ERROR)) ;
-- IncrementAlertCount(AlertLogID, WARNING, StopDueToCount, AlertCount(WARNING)) ;
--
-- AlertLogPtr(AlertLogID).AffirmCount := ReqPassedCount + TotalErrorCount ;
-- end if;
AlertLogPtr(AlertLogID).PassedGoalSet := TRUE ;
end loop ReadFileLoop ;
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean ;
TestSummary : boolean
) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file RequirementsFile : text open READ_MODE is FileName ;
begin
ReadRequirements(RequirementsFile, ThresholdPassed, TestSummary) ;
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
AffirmCheckCountVar := 0 ;
PassedCountVar := 0 ;
AlertCount := (0, 0, 0) ;
ErrorCount := 0 ;
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertCount := (0, 0, 0) ;
AlertLogPtr(i).DisabledAlertCount := (0, 0, 0) ;
AlertLogPtr(i).AffirmCount := 0 ;
AlertLogPtr(i).PassedCount := 0 ;
AlertLogPtr(i).PassedGoal := 0 ;
end loop ;
end procedure ClearAlerts ;
------------------------------------------------------------
procedure ClearAlertStopCounts is
------------------------------------------------------------
begin
AlertLogPtr(ALERTLOG_BASE_ID).AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
for i in ALERTLOG_BASE_ID + 1 to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ;
end loop ;
end procedure ClearAlertStopCounts ;
------------------------------------------------------------
-- PT Local
procedure LocalLog (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType
) is
variable buf : line ;
variable ParentID : AlertLogIDType ;
-- constant LogPrefix : string := LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
begin
-- Print %% log (nominally)
-- write(buf, LogPrefix) ;
write(buf, LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) ;
-- Debug Mode
if WriteLogErrorCountVar then
if WriteAlertErrorCountVar then
if ErrorCount > 0 then
write(buf, ' ' & justify(to_string(ErrorCount), RIGHT, 2)) ;
else
swrite(buf, " ") ;
end if ;
end if ;
end if ;
-- Level Name, when enabled (default)
if WriteLogLevelVar then
write(buf, " " & LOG_NAME(Level) ) ;
end if ;
-- AlertLog Name
if FoundAlertHierVar and WriteLogNameVar then
if AlertLogPtr(AlertLogID).PrintParent = PRINT_NAME then
write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
else
ParentID := AlertLogPtr(AlertLogID).ParentID ;
write(buf, " in " & LeftJustify(AlertLogPtr(ParentID).Name.all & ResolveOsvvmIdSeparator(IdSeparatorVar.GetOpt) &
AlertLogPtr(AlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
end if ;
end if ;
-- Prefix
if AlertLogPtr(AlertLogID).Prefix /= NULL then
write(buf, ' ' & AlertLogPtr(AlertLogID).Prefix.all) ;
end if ;
-- Message
write(buf, " " & Message) ;
-- Suffix
if AlertLogPtr(AlertLogID).Suffix /= NULL then
write(buf, ' ' & AlertLogPtr(AlertLogID).Suffix.all) ;
end if ;
-- Time
if WriteLogTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end procedure LocalLog ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if Level = ALWAYS or Enable then
LocalLog(localAlertLogID, Message, Level) ;
elsif AlertLogPtr(localAlertLogID).LogEnabled(Level) then
LocalLog(localAlertLogID, Message, Level) ;
end if ;
if Level = PASSED then
IncAffirmPassedCount(AlertLogID) ; -- count the passed and affirmation
end if ;
end procedure log ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
Deallocate(AlertLogPtr(ALERTLOG_BASE_ID).Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).Name := new string'(Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).NameLower := new string'(to_lower(NAME)) ;
end procedure SetAlertLogName ;
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Name.all ;
end function GetAlertLogName ;
------------------------------------------------------------
-- PT Local
procedure DeQueueID(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable ParentID, CurID : AlertLogIDType ;
begin
ParentID := AlertLogPtr(AlertLogID).ParentID ;
CurID := AlertLogPtr(ParentID).ChildID ;
-- Found at top of list
if AlertLogPtr(ParentID).ChildID = AlertLogID then
AlertLogPtr(ParentID).ChildID := AlertLogPtr(AlertLogID).SiblingID ;
else
-- Find among Siblings
loop
if AlertLogPtr(CurID).SiblingID = AlertLogID then
AlertLogPtr(CurID).SiblingID := AlertLogPtr(AlertLogID).SiblingID ;
exit ;
end if ;
if AlertLogPtr(CurID).SiblingID <= ALERTLOG_BASE_ID then
Alert("DeQueueID: AlertLogID not found") ;
exit ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure DeQueueID ;
------------------------------------------------------------
-- PT Local
procedure EnQueueID(AlertLogID, ParentID : AlertLogIDType ; ParentIDSet : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).ParentIDSet := ParentIDSet ;
AlertLogPtr(AlertLogID).ParentID := ParentID ;
AlertLogPtr(AlertLogID).SiblingID := ALERTLOG_ID_NOT_ASSIGNED ;
if AlertLogPtr(ParentID).ChildID < ALERTLOG_BASE_ID then
AlertLogPtr(ParentID).ChildID := AlertLogID ;
else
CurID := AlertLogPtr(ParentID).ChildIDLast ;
AlertLogPtr(CurID).SiblingID := AlertLogID ;
end if ;
AlertLogPtr(ParentID).ChildIDLast := AlertLogID ;
end procedure EnQueueID ;
------------------------------------------------------------
-- PT Local
procedure NewAlertLogRec(AlertLogID : AlertLogIDType ; iName : string ; ParentID : AlertLogIDType; ReportMode : AlertLogReportModeType := ENABLED; PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT) is
------------------------------------------------------------
variable AlertEnabled : AlertEnableType ;
variable AlertStopCount : AlertCountType ;
variable LogEnabled : LogEnableType ;
begin
AlertLogPtr(AlertLogID) := new AlertLogRecType ;
if AlertLogID = ALERTLOG_BASE_ID then
AlertEnabled := (TRUE, TRUE, TRUE) ;
LogEnabled := (others => FALSE) ;
AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
EnQueueID(AlertLogID, ALERTLOG_BASE_ID, TRUE) ;
else
if ParentID < ALERTLOG_BASE_ID then
AlertEnabled := AlertLogPtr(ALERTLOG_BASE_ID).AlertEnabled ;
LogEnabled := AlertLogPtr(ALERTLOG_BASE_ID).LogEnabled ;
EnQueueID(AlertLogID, ALERTLOG_BASE_ID, FALSE) ;
else
AlertEnabled := AlertLogPtr(ParentID).AlertEnabled ;
LogEnabled := AlertLogPtr(ParentID).LogEnabled ;
EnQueueID(AlertLogID, ParentID, TRUE) ;
end if ;
AlertStopCount := (FAILURE | ERROR | WARNING => integer'right) ;
end if ;
AlertLogPtr(AlertLogID).Name := new string'(iName) ;
AlertLogPtr(AlertLogID).NameLower := new string'(to_lower(iName)) ;
AlertLogPtr(AlertLogID).AlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).DisabledAlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).AffirmCount := 0 ;
AlertLogPtr(AlertLogID).PassedCount := 0 ;
AlertLogPtr(AlertLogID).PassedGoal := 0 ;
AlertLogPtr(AlertLogID).AlertEnabled := AlertEnabled ;
AlertLogPtr(AlertLogID).AlertStopCount := AlertStopCount ;
AlertLogPtr(AlertLogID).AlertPrintCount := (FAILURE | ERROR | WARNING => integer'right) ;
AlertLogPtr(AlertLogID).LogEnabled := LogEnabled ;
AlertLogPtr(AlertLogID).ReportMode := ReportMode ;
-- Update PrintParent
if ParentID > ALERTLOG_BASE_ID then
AlertLogPtr(AlertLogID).PrintParent := PrintParent ;
else
AlertLogPtr(AlertLogID).PrintParent := PRINT_NAME ;
end if ;
-- Set ChildID, ChildIDLast, SiblingID to ALERTLOG_ID_NOT_ASSIGNED
AlertLogPtr(AlertLogID).SiblingID := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).ChildID := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).ChildIDLast := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).TotalErrors := 0 ;
AlertLogPtr(AlertLogID).AffirmPassedCount := 0 ;
end procedure NewAlertLogRec ;
------------------------------------------------------------
-- PT Local
-- Construct initial data structure
procedure LocalInitialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
if NumAllocatedAlertLogIDsVar /= 0 then
Alert(ALERT_DEFAULT_ID, "AlertLogPkg: Initialize, data structure already initialized", FAILURE) ;
return ;
end if ;
-- Initialize Pointer
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to ALERTLOG_BASE_ID + NewNumAlertLogIDs) ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
-- Create BASE AlertLogID (if it differs from DEFAULT
NewAlertLogRec(ALERTLOG_BASE_ID, "AlertLogTop", ALERTLOG_BASE_ID) ;
-- Create DEFAULT AlertLogID
NewAlertLogRec(ALERT_DEFAULT_ID, "Default", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := ALERT_DEFAULT_ID ;
-- Create OSVVM AlertLogID (if it differs from DEFAULT
if OSVVM_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(OSVVM_ALERTLOG_ID, "OSVVM", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if REQUIREMENT_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(REQUIREMENT_ALERTLOG_ID, "Requirements", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if OSVVM_SCOREBOARD_ALERTLOG_ID /= OSVVM_ALERTLOG_ID then
NewAlertLogRec(OSVVM_SCOREBOARD_ALERTLOG_ID, "OSVVM Scoreboard", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
end procedure LocalInitialize ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
LocalInitialize(NewNumAlertLogIDs) ;
end procedure Initialize ;
------------------------------------------------------------
-- PT Local
-- Constructs initial data structure using constant below
impure function LocalInitialize return boolean is
------------------------------------------------------------
begin
LocalInitialize(MIN_NUM_AL_IDS) ;
return TRUE ;
end function LocalInitialize ;
constant CONSTRUCT_ALERT_DATA_STRUCTURE : boolean := LocalInitialize ;
------------------------------------------------------------
procedure DeallocateAlertLogStruct is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Deallocate(AlertLogPtr(i).Name) ;
Deallocate(AlertLogPtr(i)) ;
end loop ;
deallocate(AlertLogPtr) ;
-- Free up space used by protected types within AlertLogPkg
AlertPrefixVar.Deallocate ;
LogPrefixVar.Deallocate ;
ReportPrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
-- Restore variables to their initial state
PrintPassedVar := TRUE ;
PrintAffirmationsVar := FALSE ;
PrintDisabledAlertsVar := FALSE ;
PrintRequirementsVar := FALSE ;
PrintIfHaveRequirementsVar := TRUE ;
DefaultPassedGoalVar := 1 ;
NumAlertLogIDsVar := 0 ;
NumAllocatedAlertLogIDsVar := 0 ;
GlobalAlertEnabledVar := TRUE ; -- Allows turn off and on
AffirmCheckCountVar := 0 ;
PassedCountVar := 0 ;
FailOnWarningVar := TRUE ;
FailOnDisabledErrorsVar := TRUE ;
FailOnRequirementErrorsVar := TRUE ;
ReportHierarchyVar := TRUE ;
FoundReportHierVar := FALSE ;
FoundAlertHierVar := FALSE ;
WriteAlertErrorCountVar := FALSE ;
WriteAlertLevelVar := TRUE ;
WriteAlertNameVar := TRUE ;
WriteAlertTimeVar := TRUE ;
WriteLogErrorCountVar := FALSE ;
WriteLogLevelVar := TRUE ;
WriteLogNameVar := TRUE ;
WriteLogTimeVar := TRUE ;
end procedure DeallocateAlertLogStruct ;
------------------------------------------------------------
-- PT Local.
procedure GrowAlertStructure (NewNumAlertLogIDs : AlertLogIDType) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NumAllocatedAlertLogIDsVar = 0 then
Initialize (NewNumAlertLogIDs) ; -- Construct initial structure
else
oldAlertLogPtr := AlertLogPtr ;
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to NewNumAlertLogIDs) ;
AlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) := oldAlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) ;
deallocate(oldAlertLogPtr) ;
end if ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
end procedure GrowAlertStructure ;
------------------------------------------------------------
-- Sets a AlertLogPtr to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy in autosizes.
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NewNumAlertLogIDs) ;
end if;
end procedure SetNumAlertLogIDs ;
------------------------------------------------------------
-- PT Local
impure function GetNextAlertLogID return AlertLogIDType is
------------------------------------------------------------
variable NewNumAlertLogIDs : AlertLogIDType ;
begin
NewNumAlertLogIDs := NumAlertLogIDsVar + 1 ;
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NumAllocatedAlertLogIDsVar + MIN_NUM_AL_IDS) ;
end if ;
NumAlertLogIDsVar := NewNumAlertLogIDs ;
return NumAlertLogIDsVar ;
end function GetNextAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
constant NameLower : string := to_lower(Name) ;
begin
for i in ALERTLOG_BASE_ID+1 to NumAlertLogIDsVar loop
if NameLower = AlertLogPtr(i).NameLower.all then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end function FindAlertLogID ;
------------------------------------------------------------
-- PT Local
impure function LocalFindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
constant NameLower : string := to_lower(Name) ;
begin
if ParentID = ALERTLOG_ID_NOT_ASSIGNED then
return FindAlertLogID(Name) ;
else
for i in ALERTLOG_BASE_ID+1 to NumAlertLogIDsVar loop
if NameLower = AlertLogPtr(i).NameLower.all and
(AlertLogPtr(i).ParentID = ParentID or AlertLogPtr(i).ParentIDSet = FALSE)
then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end if ;
end function LocalFindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable localParentID : AlertLogIDType ;
begin
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED) ;
return LocalFindAlertLogID(Name, localParentID) ;
end function FindAlertLogID ;
------------------------------------------------------------
-- PT Local
procedure AdjustID(AlertLogID, ParentID : AlertLogIDType ; ParentIDSet : boolean := TRUE) is
------------------------------------------------------------
begin
if IsRequirement(AlertLogID) and not IsRequirement(ParentID) then
Alert(AlertLogID, "GetAlertLogID/GetReqID: Parent of a Requirement must be a Requirement") ;
else
if ParentID /= AlertLogPtr(AlertLogID).ParentID then
DeQueueID(AlertLogID) ;
EnQueueID(AlertLogID, ParentID, ParentIDSet) ;
else
AlertLogPtr(AlertLogID).ParentIDSet := ParentIDSet ;
end if ;
end if ;
end procedure AdjustID ;
------------------------------------------------------------
impure function NewID(
Name : string ;
ParentID : AlertLogIDType ;
ReportMode : AlertLogReportModeType ;
PrintParent : AlertLogPrintParentType ;
CreateHierarchy : boolean
) return AlertLogIDType is
-- impure function GetAlertLogID(Name : string; ParentID : AlertLogIDType; CreateHierarchy : Boolean; DoNotReport : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
variable localParentID : AlertLogIDType ;
begin
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED, ALERTLOG_ID_NOT_ASSIGNED) ;
ResultID := LocalFindAlertLogID(Name, localParentID) ;
if ResultID = ALERTLOG_ID_NOT_FOUND then
-- Create a new ID
ResultID := GetNextAlertLogID ;
NewAlertLogRec(ResultID, Name, localParentID, ReportMode, PrintParent) ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy and ReportMode /= DISABLED then
FoundReportHierVar := TRUE ;
end if ;
AlertLogPtr(ResultID).PassedGoal := 0 ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
else
-- Found existing ID. Update it.
if AlertLogPtr(ResultID).ParentIDSet = FALSE then
if localParentID /= ALERTLOG_ID_NOT_ASSIGNED then
-- Update ParentID and potentially relocate in the structure
AdjustID(ResultID, localParentID, TRUE) ;
-- Update PrintParent
if localParentID /= ALERTLOG_BASE_ID then
AlertLogPtr(ResultID).PrintParent := PrintParent ;
else
AlertLogPtr(ResultID).PrintParent := PRINT_NAME ;
end if ;
-- else -- do not update as ParentIDs are either same or input localParentID = ALERTLOG_ID_NOT_ASSIGNED
end if ;
end if ;
end if ;
return ResultID ;
end function NewID ;
------------------------------------------------------------
impure function GetReqID(Name : string ; PassedGoal : integer ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
variable localParentID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED, ALERTLOG_ID_NOT_ASSIGNED) ;
ResultID := LocalFindAlertLogID(Name, localParentID) ;
if ResultID = ALERTLOG_ID_NOT_FOUND then
-- Create a new ID
ResultID := GetNextAlertLogID ;
if localParentID = ALERTLOG_ID_NOT_ASSIGNED then
NewAlertLogRec(ResultID, Name, REQUIREMENT_ALERTLOG_ID, ENABLED, PRINT_NAME) ;
AlertLogPtr(ResultID).ParentIDSet := FALSE ;
else
-- May want just PRINT_NAME here as PRINT_NAME_AND_PARENT is not backward compatible
-- NewAlertLogRec(ResultID, Name, localParentID, ENABLED, PRINT_NAME_AND_PARENT) ;
NewAlertLogRec(ResultID, Name, localParentID, ENABLED, PRINT_NAME) ;
end if ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy then
FoundReportHierVar := TRUE ;
end if ;
if PassedGoal >= 0 then
AlertLogPtr(ResultID).PassedGoal := PassedGoal ;
AlertLogPtr(ResultID).PassedGoalSet := TRUE ;
else
AlertLogPtr(ResultID).PassedGoal := DefaultPassedGoalVar ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
else
-- Found existing ID. Update it.
if AlertLogPtr(ResultID).ParentIDSet = FALSE then
if localParentID /= ALERTLOG_ID_NOT_ASSIGNED then
AdjustID(ResultID, localParentID, TRUE) ;
if localParentID /= REQUIREMENT_ALERTLOG_ID then
-- May want just PRINT_NAME here as PRINT_NAME_AND_PARENT is not backward compatible
-- AlertLogPtr(ResultID).PrintParent := PRINT_NAME_AND_PARENT ;
AlertLogPtr(ResultID).PrintParent := PRINT_NAME ;
else
AlertLogPtr(ResultID).PrintParent := PRINT_NAME ;
end if ;
else
-- Update if originally set by NewID/GetAlertLogID
AdjustID(ResultID, REQUIREMENT_ALERTLOG_ID, FALSE) ;
end if ;
end if ;
if AlertLogPtr(ResultID).PassedGoalSet = FALSE then
if PassedGoal >= 0 then
AlertLogPtr(ResultID).PassedGoal := PassedGoal ;
AlertLogPtr(ResultID).PassedGoalSet := TRUE ;
else
AlertLogPtr(ResultID).PassedGoal := DefaultPassedGoalVar ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
end if ;
end if ;
return ResultID ;
end function GetReqID ;
------------------------------------------------------------
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
localAlertLogID := VerifyID(AlertLogID) ;
if PassedGoal >= 0 then
AlertLogPtr(localAlertLogID).PassedGoal := PassedGoal ;
else
AlertLogPtr(localAlertLogID).PassedGoal := DefaultPassedGoalVar ;
end if ;
end procedure SetPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).ParentID ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Prefix) ;
if Name'length > 0 then
AlertLogPtr(localAlertLogID).Prefix := new string'(Name) ;
end if ;
end procedure SetAlertLogPrefix ;
------------------------------------------------------------
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Prefix) ;
end procedure UnSetAlertLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Prefix.all ;
end function GetAlertLogPrefix ;
------------------------------------------------------------
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Suffix) ;
if Name'length > 0 then
AlertLogPtr(localAlertLogID).Suffix := new string'(Name) ;
end if ;
end procedure SetAlertLogSuffix ;
------------------------------------------------------------
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Suffix) ;
end procedure UnSetAlertLogSuffix ;
------------------------------------------------------------
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Suffix.all ;
end function GetAlertLogSuffix ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
GlobalAlertEnabledVar := A ;
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
begin
return GlobalAlertEnabledVar ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
-- PT LOCAL
procedure SetOneStopCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType ;
Count : integer
) is
begin
if AlertLogPtr(AlertLogID).AlertStopCount(Level) = integer'right then
AlertLogPtr(AlertLogID).AlertStopCount(Level) := Count ;
else
AlertLogPtr(AlertLogID).AlertStopCount(Level) :=
AlertLogPtr(AlertLogID).AlertStopCount(Level) + Count ;
end if ;
end procedure SetOneStopCount ;
------------------------------------------------------------
-- PT Local
procedure LocalSetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
SetOneStopCount(AlertLogID, Level, Count) ;
if AlertLogID /= ALERTLOG_BASE_ID then
LocalSetAlertStopCount(AlertLogPtr(AlertLogID).ParentID, Level, Count) ;
end if ;
end procedure LocalSetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetAlertStopCount(localAlertLogID, Level, Count) ;
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertStopCount(Level) ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).AlertPrintCount(Level) := Count ;
end procedure SetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertPrintCount(Level) ;
end function GetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Count : AlertCountType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).AlertPrintCount(FAILURE) := Count(FAILURE) ;
AlertLogPtr(localAlertLogID).AlertPrintCount(ERROR) := Count(ERROR) ;
AlertLogPtr(localAlertLogID).AlertPrintCount(WARNING) := Count(WARNING) ;
end procedure SetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertPrintCount ;
end function GetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertLogPrintParent(AlertLogID : AlertLogIDType ; PrintParent : AlertLogPrintParentType) is
------------------------------------------------------------
variable localAlertLogID, ParentID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
ParentID := AlertLogPtr(localAlertLogID).ParentID ;
if (ParentID = ALERTLOG_BASE_ID or ParentID = REQUIREMENT_ALERTLOG_ID) then
AlertLogPtr(localAlertLogID).PrintParent := PRINT_NAME ;
else
AlertLogPtr(localAlertLogID).PrintParent := PrintParent ;
end if ;
end procedure SetAlertLogPrintParent ;
------------------------------------------------------------
impure function GetAlertLogPrintParent(AlertLogID : AlertLogIDType) return AlertLogPrintParentType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).PrintParent ;
end function GetAlertLogPrintParent ;
------------------------------------------------------------
procedure SetAlertLogReportMode(AlertLogID : AlertLogIDType ; ReportMode : AlertLogReportModeType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).ReportMode := ReportMode ;
end procedure SetAlertLogReportMode ;
------------------------------------------------------------
impure function GetAlertLogReportMode(AlertLogID : AlertLogIDType) return AlertLogReportModeType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).ReportMode ;
end function GetAlertLogReportMode ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertEnabled(Level) := Enable ;
end loop ;
end procedure SetAlertEnable ;
------------------------------------------------------------
-- PT Local
procedure LocalSetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).AlertEnabled(Level) := Enable ;
if DescendHierarchy then
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
LocalSetAlertEnable(CurID, Level, Enable, DescendHierarchy) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure LocalSetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetAlertEnable(localAlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertEnabled(Level) ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).LogEnabled(Level) := Enable ;
end loop ;
end procedure SetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure LocalSetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).LogEnabled(Level) := Enable ;
if DescendHierarchy then
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
LocalSetLogEnable(CurID, Level, Enable, DescendHierarchy) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure LocalSetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetLogEnable(localAlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if Level = ALWAYS then
return TRUE ;
else
return AlertLogPtr(localAlertLogID).LogEnabled(Level) ;
end if ;
end function GetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure PrintLogLevels(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
begin
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
for i in LogIndexType loop
if AlertLogPtr(AlertLogID).LogEnabled(i) then
-- write(buf, " " & to_string(AlertLogPtr(AlertLogID).LogEnabled(i)) ) ;
write(buf, " " & to_string(i)) ;
end if ;
end loop ;
WriteLine(buf) ;
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
-- Always print requirements
-- if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
-- CurID := AlertLogPtr(CurID).SiblingID ;
-- next ;
-- end if ;
PrintLogLevels(
AlertLogID => CurID,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure PrintLogLevels ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
variable TurnedOnJustify : boolean := FALSE ;
begin
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
PrintLogLevels(ALERTLOG_BASE_ID, "", 0) ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
end procedure ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : OsvvmOptionsType ;
FailOnDisabledErrors : OsvvmOptionsType ;
FailOnRequirementErrors : OsvvmOptionsType ;
ReportHierarchy : OsvvmOptionsType ;
WriteAlertErrorCount : OsvvmOptionsType ;
WriteAlertLevel : OsvvmOptionsType ;
WriteAlertName : OsvvmOptionsType ;
WriteAlertTime : OsvvmOptionsType ;
WriteLogErrorCount : OsvvmOptionsType ;
WriteLogLevel : OsvvmOptionsType ;
WriteLogName : OsvvmOptionsType ;
WriteLogTime : OsvvmOptionsType ;
PrintPassed : OsvvmOptionsType ;
PrintAffirmations : OsvvmOptionsType ;
PrintDisabledAlerts : OsvvmOptionsType ;
PrintRequirements : OsvvmOptionsType ;
PrintIfHaveRequirements : OsvvmOptionsType ;
DefaultPassedGoal : integer ;
AlertPrefix : string ;
LogPrefix : string ;
ReportPrefix : string ;
DoneName : string ;
PassName : string ;
FailName : string ;
IdSeparator : string
) is
begin
if FailOnWarning /= OPT_INIT_PARM_DETECT then
FailOnWarningVar := IsEnabled(FailOnWarning) ;
end if ;
if FailOnDisabledErrors /= OPT_INIT_PARM_DETECT then
FailOnDisabledErrorsVar := IsEnabled(FailOnDisabledErrors) ;
end if ;
if FailOnRequirementErrors /= OPT_INIT_PARM_DETECT then
FailOnRequirementErrorsVar := IsEnabled(FailOnRequirementErrors) ;
end if ;
if ReportHierarchy /= OPT_INIT_PARM_DETECT then
ReportHierarchyVar := IsEnabled(ReportHierarchy) ;
end if ;
if WriteAlertErrorCount /= OPT_INIT_PARM_DETECT then
WriteAlertErrorCountVar := IsEnabled(WriteAlertErrorCount) ;
end if ;
if WriteAlertLevel /= OPT_INIT_PARM_DETECT then
WriteAlertLevelVar := IsEnabled(WriteAlertLevel) ;
end if ;
if WriteAlertName /= OPT_INIT_PARM_DETECT then
WriteAlertNameVar := IsEnabled(WriteAlertName) ;
end if ;
if WriteAlertTime /= OPT_INIT_PARM_DETECT then
WriteAlertTimeVar := IsEnabled(WriteAlertTime) ;
end if ;
if WriteLogErrorCount /= OPT_INIT_PARM_DETECT then
WriteLogErrorCountVar := IsEnabled(WriteLogErrorCount) ;
end if ;
if WriteLogLevel /= OPT_INIT_PARM_DETECT then
WriteLogLevelVar := IsEnabled(WriteLogLevel) ;
end if ;
if WriteLogName /= OPT_INIT_PARM_DETECT then
WriteLogNameVar := IsEnabled(WriteLogName) ;
end if ;
if WriteLogTime /= OPT_INIT_PARM_DETECT then
WriteLogTimeVar := IsEnabled(WriteLogTime) ;
end if ;
if PrintPassed /= OPT_INIT_PARM_DETECT then
PrintPassedVar := IsEnabled(PrintPassed) ;
end if ;
if PrintAffirmations /= OPT_INIT_PARM_DETECT then
PrintAffirmationsVar := IsEnabled(PrintAffirmations) ;
end if ;
if PrintDisabledAlerts /= OPT_INIT_PARM_DETECT then
PrintDisabledAlertsVar := IsEnabled(PrintDisabledAlerts) ;
end if ;
if PrintRequirements /= OPT_INIT_PARM_DETECT then
PrintRequirementsVar := IsEnabled(PrintRequirements) ;
end if ;
if PrintIfHaveRequirements /= OPT_INIT_PARM_DETECT then
PrintIfHaveRequirementsVar := IsEnabled(PrintIfHaveRequirements) ;
end if ;
if DefaultPassedGoal > 0 then
DefaultPassedGoalVar := DefaultPassedGoal ;
end if ;
if AlertPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
AlertPrefixVar.Set(AlertPrefix) ;
end if ;
if LogPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
LogPrefixVar.Set(LogPrefix) ;
end if ;
if ReportPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
ReportPrefixVar.Set(ReportPrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
if IdSeparator /= OSVVM_STRING_INIT_PARM_DETECT then
IdSeparatorVar.Set(FailName) ;
end if ;
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
variable buf : line ;
begin
-- Boolean Values
swrite(buf, "ReportAlertLogOptions" & LF ) ;
swrite(buf, "---------------------" & LF ) ;
swrite(buf, "FailOnWarningVar: " & to_string(FailOnWarningVar ) & LF ) ;
swrite(buf, "FailOnDisabledErrorsVar: " & to_string(FailOnDisabledErrorsVar ) & LF ) ;
swrite(buf, "FailOnRequirementErrorsVar: " & to_string(FailOnRequirementErrorsVar ) & LF ) ;
swrite(buf, "ReportHierarchyVar: " & to_string(ReportHierarchyVar ) & LF ) ;
swrite(buf, "FoundReportHierVar: " & to_string(FoundReportHierVar ) & LF ) ; -- Not set by user
swrite(buf, "FoundAlertHierVar: " & to_string(FoundAlertHierVar ) & LF ) ; -- Not set by user
swrite(buf, "WriteAlertErrorCountVar: " & to_string(WriteAlertErrorCountVar ) & LF ) ;
swrite(buf, "WriteAlertLevelVar: " & to_string(WriteAlertLevelVar ) & LF ) ;
swrite(buf, "WriteAlertNameVar: " & to_string(WriteAlertNameVar ) & LF ) ;
swrite(buf, "WriteAlertTimeVar: " & to_string(WriteAlertTimeVar ) & LF ) ;
swrite(buf, "WriteLogErrorCountVar: " & to_string(WriteLogErrorCountVar ) & LF ) ;
swrite(buf, "WriteLogLevelVar: " & to_string(WriteLogLevelVar ) & LF ) ;
swrite(buf, "WriteLogNameVar: " & to_string(WriteLogNameVar ) & LF ) ;
swrite(buf, "WriteLogTimeVar: " & to_string(WriteLogTimeVar ) & LF ) ;
swrite(buf, "PrintPassedVar: " & to_string(PrintPassedVar ) & LF ) ;
swrite(buf, "PrintAffirmationsVar: " & to_string(PrintAffirmationsVar ) & LF ) ;
swrite(buf, "PrintDisabledAlertsVar: " & to_string(PrintDisabledAlertsVar ) & LF ) ;
swrite(buf, "PrintRequirementsVar: " & to_string(PrintRequirementsVar ) & LF ) ;
swrite(buf, "PrintIfHaveRequirementsVar: " & to_string(PrintIfHaveRequirementsVar ) & LF ) ;
-- String
swrite(buf, "AlertPrefixVar: " & string'(AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX)) & LF ) ;
swrite(buf, "LogPrefixVar: " & string'(LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) & LF ) ;
swrite(buf, "ReportPrefixVar: " & ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & LF ) ;
swrite(buf, "DoneNameVar: " & ResolveOsvvmDoneName(DoneNameVar.GetOpt) & LF ) ;
swrite(buf, "PassNameVar: " & ResolveOsvvmPassName(PassNameVar.GetOpt) & LF ) ;
swrite(buf, "FailNameVar: " & ResolveOsvvmFailName(FailNameVar.GetOpt) & LF ) ;
writeline(buf) ;
end procedure ReportAlertLogOptions ;
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnWarningVar) ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnDisabledErrorsVar) ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogFailOnRequirementErrors return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnRequirementErrorsVar) ;
end function GetAlertLogFailOnRequirementErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(ReportHierarchyVar) ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return FoundReportHierVar ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return FoundAlertHierVar ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertErrorCount return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertErrorCountVar) ;
end function GetAlertLogWriteAlertErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertLevelVar) ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertNameVar) ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertTimeVar) ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogErrorCount return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogErrorCountVar) ;
end function GetAlertLogWriteLogErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogLevelVar) ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogNameVar) ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogTimeVar) ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogPrintPassed return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintPassedVar) ;
end function GetAlertLogPrintPassed ;
------------------------------------------------------------
impure function GetAlertLogPrintAffirmations return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintAffirmationsVar) ;
end function GetAlertLogPrintAffirmations ;
------------------------------------------------------------
impure function GetAlertLogPrintDisabledAlerts return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintDisabledAlertsVar) ;
end function GetAlertLogPrintDisabledAlerts ;
------------------------------------------------------------
impure function GetAlertLogPrintRequirements return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintRequirementsVar) ;
end function GetAlertLogPrintRequirements ;
------------------------------------------------------------
impure function GetAlertLogPrintIfHaveRequirements return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintIfHaveRequirementsVar) ;
end function GetAlertLogPrintIfHaveRequirements ;
------------------------------------------------------------
impure function GetAlertLogDefaultPassedGoal return integer is
------------------------------------------------------------
begin
return DefaultPassedGoalVar ;
end function GetAlertLogDefaultPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return ResolveOsvvmDoneName(DoneNameVar.GetOpt) ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return ResolveOsvvmPassName(PassNameVar.GetOpt) ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return ResolveOsvvmFailName(FailNameVar.GetOpt) ;
end function GetAlertLogFailName ;
end protected body AlertLogStructPType ;
shared variable AlertLogStruct : AlertLogStructPType ;
-- synthesis translate_on
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
procedure Alert(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) is
begin
-- synthesis translate_off
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
-- synthesis translate_on
end procedure alert ;
------------------------------------------------------------
procedure Alert( Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
-- synthesis translate_on
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) is
begin
-- synthesis translate_off
AlertLogStruct.IncAlertCount(AlertLogID, Level) ;
-- synthesis translate_on
end procedure IncAlertCount ;
------------------------------------------------------------
procedure IncAlertCount( Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAlertCount(ALERT_DEFAULT_ID, Level) ;
-- synthesis translate_on
end procedure IncAlertCount ;
------------------------------------------------------------
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID , Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
-- useful in a loop: exit when AlertIf( not ReadValid, failure, "Read Failed") ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
-- synthesis translate_on
return condition ;
end function AlertIf ;
------------------------------------------------------------
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
return condition ;
end function AlertIf ;
------------------------------------------------------------
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AlertIfNot( not ReadValid, failure, "Read Failed") ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
-- synthesis translate_on
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
-- AlertIfEqual with AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, GetOsvvmDefaultTimeUnits)
& " R = " & to_string(R, GetOsvvmDefaultTimeUnits), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
-- AlertIfEqual without AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, GetOsvvmDefaultTimeUnits)
& " R = " & to_string(R, GetOsvvmDefaultTimeUnits), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
-- AlertIfNotEqual with AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, GetOsvvmDefaultTimeUnits) &
" R = " & to_string(R, GetOsvvmDefaultTimeUnits), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
-- AlertIfNotEqual without AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, GetOsvvmDefaultTimeUnits) &
" R = " & to_string(R, GetOsvvmDefaultTimeUnits), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
-- Local
function LocalDiff (Line1, Line2 : string) return boolean is
-- Simple diff. Move to string handling functions?
------------------------------------------------------------
alias aLine1 : string (1 to Line1'length) is Line1 ;
alias aLine2 : string (1 to Line2'length) is Line2 ;
variable EndLine1 : integer := Line1'length;
variable EndLine2 : integer := Line2'length;
begin
-- Strip off any windows or unix end of line characters
for i in Line1'length downto 1 loop
exit when aLine1(i) /= LF and aLine1(i) /= CR ;
EndLine1 := i - 1;
end loop ;
for i in Line2'length downto 1 loop
exit when aLine2(i) /= LF and aLine2(i) /= CR ;
EndLine2 := i - 1;
end loop ;
return aLine1(1 to EndLine1) /= aLine2(1 to EndLine2) ;
end function LocalDiff ;
------------------------------------------------------------
-- Local
procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string ; Level : AlertType ; Valid : out boolean ) is
------------------------------------------------------------
variable Buf1, Buf2 : line ;
variable File1Done, File2Done : boolean ;
variable LineCount : integer := 0 ;
begin
-- synthesis translate_off
ReadLoop : loop
File1Done := EndFile(File1) ;
File2Done := EndFile(File2) ;
exit ReadLoop when File1Done or File2Done ;
ReadLine(File1, Buf1) ;
ReadLine(File2, Buf2) ;
LineCount := LineCount + 1 ;
-- if Buf1.all /= Buf2.all then -- fails when use Windows file in Unix
if LocalDiff(Buf1.all, Buf2.all) then
AlertLogStruct.Alert(AlertLogID , Message & " File miscompare on line " & to_string(LineCount), Level) ;
exit ReadLoop ;
end if ;
end loop ReadLoop ;
if File1Done /= File2Done then
if not File1Done then
AlertLogStruct.Alert(AlertLogID , Message & " File1 longer than File2 " & to_string(LineCount), Level) ;
end if ;
if not File2Done then
AlertLogStruct.Alert(AlertLogID , Message & " File2 longer than File1 " & to_string(LineCount), Level) ;
end if ;
end if;
if File1Done and File2Done then
Valid := TRUE ;
else
Valid := FALSE ;
end if ;
-- synthesis translate_on
end procedure LocalAlertIfDiff ;
------------------------------------------------------------
-- Local
procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string ; Level : AlertType ; Valid : out boolean ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
file FileID1, FileID2 : text ;
variable status1, status2 : file_open_status ;
begin
-- synthesis translate_off
Valid := FALSE ;
file_open(status1, FileID1, Name1, READ_MODE) ;
file_open(status2, FileID2, Name2, READ_MODE) ;
if status1 = OPEN_OK and status2 = OPEN_OK then
LocalAlertIfDiff (AlertLogID, FileID1, FileID2, Message & " " & Name1 & " /= " & Name2 & ", ", Level, Valid) ;
else
if status1 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name1 & ", did not open", Level) ;
end if ;
if status2 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name2 & ", did not open", Level) ;
end if ;
end if;
-- synthesis translate_on
end procedure LocalAlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, Level, Valid) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, Level, Valid) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, Level, Valid ) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, Level, Valid ) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
ReceivedMessage : string ;
ExpectedMessage : string ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, ReceivedMessage, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, ReceivedMessage & ' ' & ExpectedMessage, ERROR) ;
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, Message, ERROR) ;
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIf;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIf( ID, not ReadValid, "Read Failed") ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, Message, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, Message, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, TRUE, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmPassed ;
------------------------------------------------------------
procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, TRUE, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmPassed ;
------------------------------------------------------------
procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, FALSE, Message, FALSE) ;
-- synthesis translate_on
end procedure AffirmError ;
------------------------------------------------------------
procedure AffirmError( Message : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, FALSE, Message, FALSE) ;
-- synthesis translate_on
end procedure AffirmError ;
-- With AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received, 4),
"= Expected : " & to_string(Expected, 4),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & Received,
"= Expected : " & Expected,
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received, GetOsvvmDefaultTimeUnits),
"= Expected : " & to_string(Expected, GetOsvvmDefaultTimeUnits),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
-- Without AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received, 4),
"= Expected : " & to_string(Expected, 4),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & Received,
"= Expected : " & Expected,
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received, GetOsvvmDefaultTimeUnits),
"= Expected : " & to_string(Expected, GetOsvvmDefaultTimeUnits),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfNotDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
-- Open files and call AffirmIfNotDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, ERROR, Valid) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message & " " & Name1 & " = " & Name2, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfNotDiff ;
------------------------------------------------------------
procedure AffirmIfNotDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfNotDiff(ALERT_DEFAULT_ID, Name1, Name2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNotDiff ;
------------------------------------------------------------
procedure AffirmIfNotDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, ERROR, Valid ) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfNotDiff ;
------------------------------------------------------------
procedure AffirmIfNotDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfNotDiff(ALERT_DEFAULT_ID, File1, File2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNotDiff ;
------------------------------------------------------------
-- DEPRECATED - naming polarity is incorrect. Should be AffirmIfNotDiff
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
-- Open files and call AffirmIfDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, ERROR, Valid) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message & " " & Name1 & " = " & Name2, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
-- DEPRECATED - naming polarity is incorrect. Should be AffirmIfNotDiff
procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfDiff(ALERT_DEFAULT_ID, Name1, Name2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
-- DEPRECATED - naming polarity is incorrect. Should be AffirmIfNotDiff
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, ERROR, Valid ) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
-- DEPRECATED - naming polarity is incorrect. Should be AffirmIfNotDiff
procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfDiff(ALERT_DEFAULT_ID, File1, File2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
-- Support for Specification / Requirements Tracking
------------------------------------------------------------
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
--?? Set Goal to 1? Should the ID already exist?
AffirmIf(GetReqID(RequirementsIDName), condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
--?? Set Goal to 1? Should the ID already exist?
AffirmIf(GetReqID(RequirementsIDName), condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure SetAlertLogJustify (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetJustify(Enable) ;
-- synthesis translate_on
end procedure SetAlertLogJustify ;
------------------------------------------------------------
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertCount) ;
-- synthesis translate_on
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportRequirements is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportRequirements ;
-- synthesis translate_on
end procedure ReportRequirements ;
------------------------------------------------------------
procedure ReportAlerts (
------------------------------------------------------------
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (others => 0) ;
ReportAll : Boolean := FALSE
) is
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, ReportAll, TRUE) ;
-- synthesis translate_on
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportNonZeroAlerts (
------------------------------------------------------------
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (others => 0)
) is
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, FALSE, FALSE) ;
-- synthesis translate_on
end procedure ReportNonZeroAlerts ;
------------------------------------------------------------
procedure WriteAlertYaml (
------------------------------------------------------------
FileName : string ;
ExternalErrors : AlertCountType := (0,0,0) ;
Prefix : string := "" ;
PrintSettings : boolean := TRUE ;
PrintChildren : boolean := TRUE ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteAlertYaml(FileName, ExternalErrors, Prefix, PrintSettings, PrintChildren, OpenKind) ;
-- synthesis translate_on
end procedure WriteAlertYaml ;
------------------------------------------------------------
procedure WriteAlertSummaryYaml (FileName : string := "" ; ExternalErrors : AlertCountType := (0,0,0)) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", "OsvvmRun.yml", FileName) ;
begin
-- synthesis translate_off
WriteAlertYaml(FileName => RESOLVED_FILE_NAME, ExternalErrors => ExternalErrors, Prefix => " ", PrintSettings => FALSE, PrintChildren => FALSE, OpenKind => APPEND_MODE) ;
-- WriteTestSummary(FileName => "OsvvmRun.yml", OpenKind => APPEND_MODE, Prefix => " ", Suffix => "", ExternalErrors => ExternalErrors, WriteFieldName => TRUE) ;
-- synthesis translate_on
end procedure WriteAlertSummaryYaml ;
------------------------------------------------------------
-- Deprecated. Use WriteAlertSummaryYaml Instead.
procedure CreateYamlReport (ExternalErrors : AlertCountType := (0,0,0)) is
begin
-- synthesis translate_off
WriteAlertSummaryYaml(ExternalErrors => ExternalErrors) ;
-- synthesis translate_on
end procedure CreateYamlReport ;
------------------------------------------------------------
procedure WriteTestSummary (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind := APPEND_MODE ;
Prefix : string := "" ;
Suffix : string := "" ;
ExternalErrors : AlertCountType := (0,0,0) ;
WriteFieldName : boolean := FALSE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteTestSummary(FileName, OpenKind, Prefix, Suffix, ExternalErrors, WriteFieldName) ;
-- synthesis translate_on
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummaries (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteTestSummaries(FileName, OpenKind) ;
-- synthesis translate_on
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure ReportTestSummaries is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportTestSummaries ;
-- synthesis translate_on
end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure WriteAlerts (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteAlerts(FileName, AlertLogID, OpenKind) ;
-- synthesis translate_on
end procedure WriteAlerts ;
------------------------------------------------------------
procedure WriteRequirements (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType := REQUIREMENT_ALERTLOG_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteRequirements(FileName, AlertLogID, OpenKind) ;
-- synthesis translate_on
end procedure WriteRequirements ;
------------------------------------------------------------
procedure ReadSpecification (FileName : string ; PassedGoal : integer := -1 ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReadSpecification(FileName, PassedGoal) ;
-- synthesis translate_on
end procedure ReadSpecification ;
------------------------------------------------------------
procedure ReadRequirements (
------------------------------------------------------------
FileName : string ;
ThresholdPassed : boolean := FALSE
) is
begin
-- synthesis translate_off
AlertLogStruct.ReadRequirements(FileName, ThresholdPassed, TestSummary => FALSE) ;
-- synthesis translate_on
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ReadTestSummaries (FileName : string) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReadRequirements(FileName, ThresholdPassed => FALSE, TestSummary => TRUE) ;
-- synthesis translate_on
end procedure ReadTestSummaries ;
-- ------------------------------------------------------------
-- procedure ReportTestSummaries (FileName : string) is
-- ------------------------------------------------------------
-- begin
-- -- synthesis translate_off
-- AlertLogStruct.ReadRequirements(FileName, ThresholdPassed => FALSE, TestSummary => TRUE) ;
-- -- synthesis translate_on
-- end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlerts ;
-- synthesis translate_on
end procedure ClearAlerts ;
------------------------------------------------------------
procedure ClearAlertStopCounts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlertStopCounts ;
-- synthesis translate_on
end procedure ClearAlertStopCounts ;
------------------------------------------------------------
procedure ClearAlertCounts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlerts ;
AlertLogStruct.ClearAlertStopCounts ;
-- synthesis translate_on
end procedure ClearAlertCounts ;
------------------------------------------------------------
function "ABS" (L : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := ABS( L(FAILURE) ) ;
Result(ERROR) := ABS( L(ERROR) ) ;
Result(WARNING) := ABS( L(WARNING) );
-- synthesis translate_on
return Result ;
end function "ABS" ;
------------------------------------------------------------
function "+" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := L(FAILURE) + R(FAILURE) ;
Result(ERROR) := L(ERROR) + R(ERROR) ;
Result(WARNING) := L(WARNING) + R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "+" ;
------------------------------------------------------------
function "-" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := L(FAILURE) - R(FAILURE) ;
Result(ERROR) := L(ERROR) - R(ERROR) ;
Result(WARNING) := L(WARNING) - R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "-" ;
------------------------------------------------------------
function "-" (R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := - R(FAILURE) ;
Result(ERROR) := - R(ERROR) ;
Result(WARNING) := - R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "-" ;
------------------------------------------------------------
impure function SumAlertCount(AlertCount: AlertCountType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
-- Using ABS ensures correct expected error handling.
result := abs(AlertCount(FAILURE)) + abs(AlertCount(ERROR)) + abs(AlertCount(WARNING)) ;
-- synthesis translate_on
return result ;
end function SumAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetEnabledAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetEnabledAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetDisabledAlertCount ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetDisabledAlertCount) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetDisabledAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetDisabledAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
procedure Log(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
AlertLogStruct.Log(AlertLogID, Message, Level, Enable) ;
-- synthesis translate_on
end procedure log ;
------------------------------------------------------------
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Log(LOG_DEFAULT_ID, Message, Level, Enable) ;
-- synthesis translate_on
end procedure log ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertEnable(Level, Enable) ;
-- synthesis translate_on
end procedure SetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
-- synthesis translate_on
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertEnable(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(Level : AlertType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertEnable(ALERT_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetLogEnable(Level, Enable) ;
-- synthesis translate_on
end procedure SetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetLogEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
-- synthesis translate_on
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetLogEnable(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(Level : LogType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetLogEnable ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportLogEnables ;
-- synthesis translate_on
end ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogName(Name) ;
-- synthesis translate_on
end procedure SetAlertLogName ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogName(AlertLogID) ;
end GetAlertLogName ;
-- synthesis translate_on
------------------------------------------------------------
procedure DeallocateAlertLogStruct is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.DeallocateAlertLogStruct ;
-- synthesis translate_on
end procedure DeallocateAlertLogStruct ;
------------------------------------------------------------
procedure InitializeAlertLogStruct is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Initialize ;
-- synthesis translate_on
end procedure InitializeAlertLogStruct ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.FindAlertLogID(Name) ;
-- synthesis translate_on
return result ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.FindAlertLogID(Name, ParentID) ;
-- synthesis translate_on
return result ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function NewID(
------------------------------------------------------------
Name : string ;
ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED;
ReportMode : AlertLogReportModeType := ENABLED ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT ;
CreateHierarchy : boolean := TRUE
) return AlertLogIDType is
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.NewID(Name, ParentID, ReportMode, PrintParent, CreateHierarchy) ;
-- synthesis translate_on
return result ;
end function NewID ;
------------------------------------------------------------
impure function GetAlertLogID(Name : string; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
variable ReportMode : AlertLogReportModeType := ENABLED ;
begin
-- synthesis translate_off
if DoNotReport then
ReportMode := DISABLED ;
end if;
-- PrintParent PRINT_NAME_AND_PARENT is not backward compatible with PRINT_NAME of the past
result := AlertLogStruct.NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
-- result := AlertLogStruct.GetAlertLogID(Name, ParentID, CreateHierarchy, DoNotReport) ;
-- synthesis translate_on
return result ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetReqID(Name : string ; PassedGoal : integer := -1 ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetReqID(Name, PassedGoal, ParentID, CreateHierarchy) ;
-- synthesis translate_on
return result ;
end function GetReqID ;
------------------------------------------------------------
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetPassedGoal(AlertLogID, PassedGoal) ;
-- synthesis translate_on
end procedure SetPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogParentID(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogPrefix(AlertLogID, Name) ;
-- synthesis translate_on
end procedure SetAlertLogPrefix ;
------------------------------------------------------------
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.UnSetAlertLogPrefix(AlertLogID) ;
-- synthesis translate_on
end procedure UnSetAlertLogPrefix ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrefix(AlertLogID) ;
end function GetAlertLogPrefix ;
-- synthesis translate_on
------------------------------------------------------------
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogSuffix(AlertLogID, Name) ;
-- synthesis translate_on
end procedure SetAlertLogSuffix ;
------------------------------------------------------------
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.UnSetAlertLogSuffix(AlertLogID) ;
-- synthesis translate_on
end procedure UnSetAlertLogSuffix ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogSuffix(AlertLogID) ;
end function GetAlertLogSuffix ;
-- synthesis translate_on
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetGlobalAlertEnable(A) ;
-- synthesis translate_on
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
-- Set using constant. Set before code runs.
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetGlobalAlertEnable(A) ;
-- synthesis translate_on
return A ;
end function SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetGlobalAlertEnable ;
-- synthesis translate_on
return result ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
procedure IncAffirmCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAffirmCount(AlertLogID) ;
-- synthesis translate_on
end procedure IncAffirmCount ;
------------------------------------------------------------
impure function GetAffirmCount return natural is
------------------------------------------------------------
variable result : natural ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAffirmCount ;
-- synthesis translate_on
return result ;
end function GetAffirmCount ;
------------------------------------------------------------
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAffirmPassedCount(AlertLogID) ;
-- synthesis translate_on
end procedure IncAffirmPassedCount ;
------------------------------------------------------------
impure function GetAffirmPassedCount return natural is
------------------------------------------------------------
variable result : natural ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAffirmPassedCount ;
-- synthesis translate_on
return result ;
end function GetAffirmPassedCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertStopCount(AlertLogID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertStopCount(ALERTLOG_BASE_ID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertStopCount(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertStopCount(ALERTLOG_BASE_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertPrintCount(AlertLogID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertPrintCount(ALERTLOG_DEFAULT_ID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertPrintCount(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertPrintCount(ALERTLOG_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Count : AlertCountType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertPrintCount(AlertLogID, Count) ;
-- synthesis translate_on
end procedure SetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(Count : AlertCountType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertPrintCount(ALERTLOG_DEFAULT_ID, Count) ;
-- synthesis translate_on
end procedure SetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertPrintCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertPrintCount(ALERTLOG_DEFAULT_ID) ;
-- synthesis translate_on
return result ;
end function GetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertLogPrintParent(AlertLogID : AlertLogIDType ; PrintParent : AlertLogPrintParentType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogPrintParent(AlertLogID, PrintParent) ;
-- synthesis translate_on
end procedure SetAlertLogPrintParent ;
------------------------------------------------------------
procedure SetAlertLogPrintParent( PrintParent : AlertLogPrintParentType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogPrintParent(ALERTLOG_DEFAULT_ID, PrintParent) ;
-- synthesis translate_on
end procedure SetAlertLogPrintParent ;
------------------------------------------------------------
impure function GetAlertLogPrintParent(AlertLogID : AlertLogIDType) return AlertLogPrintParentType is
------------------------------------------------------------
variable result : AlertLogPrintParentType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogPrintParent(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogPrintParent ;
------------------------------------------------------------
impure function GetAlertLogPrintParent return AlertLogPrintParentType is
------------------------------------------------------------
variable result : AlertLogPrintParentType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogPrintParent(ALERTLOG_DEFAULT_ID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogPrintParent ;
------------------------------------------------------------
procedure SetAlertLogReportMode(AlertLogID : AlertLogIDType ; ReportMode : AlertLogReportModeType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogReportMode(AlertLogID, ReportMode) ;
-- synthesis translate_on
end procedure SetAlertLogReportMode ;
------------------------------------------------------------
procedure SetAlertLogReportMode( ReportMode : AlertLogReportModeType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogReportMode(ALERTLOG_DEFAULT_ID, ReportMode) ;
-- synthesis translate_on
end procedure SetAlertLogReportMode ;
------------------------------------------------------------
impure function GetAlertLogReportMode(AlertLogID : AlertLogIDType) return AlertLogReportModeType is
------------------------------------------------------------
variable result : AlertLogReportModeType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogReportMode(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogReportMode ;
------------------------------------------------------------
impure function GetAlertLogReportMode return AlertLogReportModeType is
------------------------------------------------------------
variable result : AlertLogReportModeType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogReportMode(ALERTLOG_DEFAULT_ID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogReportMode ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
FailOnRequirementErrors : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertErrorCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogErrorCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintPassed : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintAffirmations : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintDisabledAlerts : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintRequirements : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintIfHaveRequirements : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
DefaultPassedGoal : integer := integer'left ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT ;
IdSeparator : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogOptions (
FailOnWarning => FailOnWarning,
FailOnDisabledErrors => FailOnDisabledErrors,
FailOnRequirementErrors => FailOnRequirementErrors,
ReportHierarchy => ReportHierarchy,
WriteAlertErrorCount => WriteAlertErrorCount,
WriteAlertLevel => WriteAlertLevel,
WriteAlertName => WriteAlertName,
WriteAlertTime => WriteAlertTime,
WriteLogErrorCount => WriteLogErrorCount,
WriteLogLevel => WriteLogLevel,
WriteLogName => WriteLogName,
WriteLogTime => WriteLogTime,
PrintPassed => PrintPassed,
PrintAffirmations => PrintAffirmations,
PrintDisabledAlerts => PrintDisabledAlerts,
PrintRequirements => PrintRequirements,
PrintIfHaveRequirements => PrintIfHaveRequirements,
DefaultPassedGoal => DefaultPassedGoal,
AlertPrefix => AlertPrefix,
LogPrefix => LogPrefix,
ReportPrefix => ReportPrefix,
DoneName => DoneName,
PassName => PassName,
FailName => FailName,
IdSeparator => IdSeparator
);
-- synthesis translate_on
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlertLogOptions ;
-- synthesis translate_on
end procedure ReportAlertLogOptions ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnWarning ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnDisabledErrors ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogFailOnRequirementErrors return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnRequirementErrors ;
end function GetAlertLogFailOnRequirementErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportHierarchy ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundReportHier ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundAlertHier ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertErrorCount return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertErrorCount ;
end function GetAlertLogWriteAlertErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertLevel ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertName ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertTime ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogErrorCount return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogErrorCount ;
end function GetAlertLogWriteLogErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogLevel ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogName ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogTime ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogPrintPassed return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintPassed ;
end function GetAlertLogPrintPassed ;
------------------------------------------------------------
impure function GetAlertLogPrintAffirmations return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintAffirmations ;
end function GetAlertLogPrintAffirmations ;
------------------------------------------------------------
impure function GetAlertLogPrintDisabledAlerts return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintDisabledAlerts ;
end function GetAlertLogPrintDisabledAlerts ;
------------------------------------------------------------
impure function GetAlertLogPrintRequirements return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintRequirements ;
end function GetAlertLogPrintRequirements ;
------------------------------------------------------------
impure function GetAlertLogPrintIfHaveRequirements return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintIfHaveRequirements ;
end function GetAlertLogPrintIfHaveRequirements ;
------------------------------------------------------------
impure function GetAlertLogDefaultPassedGoal return integer is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDefaultPassedGoal ;
end function GetAlertLogDefaultPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogAlertPrefix ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogLogPrefix ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportPrefix ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDoneName ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPassName ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailName ;
end function GetAlertLogFailName ;
------------------------------------------------------------
-- Package Local
procedure ToLogLevel(LogLevel : out LogType; Name : in String; LogValid : out boolean) is
------------------------------------------------------------
-- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER
begin
if Name = "PASSED" then
LogLevel := PASSED ;
LogValid := TRUE ;
elsif Name = "DEBUG" then
LogLevel := DEBUG ;
LogValid := TRUE ;
elsif Name = "FINAL" then
LogLevel := FINAL ;
LogValid := TRUE ;
elsif Name = "INFO" then
LogLevel := INFO ;
LogValid := TRUE ;
else
LogLevel := ALWAYS ;
LogValid := FALSE ;
end if ;
end procedure ToLogLevel ;
------------------------------------------------------------
function IsLogEnableType (Name : String) return boolean is
------------------------------------------------------------
-- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER
begin
if Name = "PASSED" then return TRUE ;
elsif Name = "DEBUG" then return TRUE ;
elsif Name = "FINAL" then return TRUE ;
elsif Name = "INFO" then return TRUE ;
end if ;
return FALSE ;
end function IsLogEnableType ;
------------------------------------------------------------
procedure ReadLogEnables (file AlertLogInitFile : text) is
-- Preferred Read format
-- Line 1: instance1_name log_enable log_enable log_enable
-- Line 2: instance2_name log_enable log_enable log_enable
-- when reading multiple log_enables on a line, they must be separated by a space
--
--- Also supports alternate format from Lyle/....
-- Line 1: instance1_name
-- Line 2: log enable
-- Line 3: instance2_name
-- Line 4: log enable
--
------------------------------------------------------------
type ReadStateType is (GET_ID, GET_ENABLE) ;
variable ReadState : ReadStateType := GET_ID ;
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable Name : string(1 to 80) ;
variable NameLen : integer ;
variable AlertLogID : AlertLogIDType ;
variable ReadAnEnable : boolean ;
variable LogValid : boolean ;
variable LogLevel : LogType ;
begin
ReadState := GET_ID ;
ReadLineLoop : while not EndFile(AlertLogInitFile) loop
ReadLine(AlertLogInitFile, buf) ;
if ReadAnEnable then
-- Read one or more enable values, next line read AlertLog name
-- Note that any newline with ReadAnEnable TRUE will result in
-- searching for another AlertLogID name - this includes multi-line comments.
ReadState := GET_ID ;
end if ;
ReadNameLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadLineLoop when Empty ;
case ReadState is
when GET_ID =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
AlertLogID := GetAlertLogID(Name(1 to NameLen), ALERTLOG_ID_NOT_ASSIGNED) ;
ReadState := GET_ENABLE ;
ReadAnEnable := FALSE ;
when GET_ENABLE =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
ReadAnEnable := TRUE ;
-- if not IsLogEnableType(Name(1 to NameLen)) then
-- Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadLogEnables: Found Invalid LogEnable: " & Name(1 to NameLen)) ;
-- exit ReadNameLoop ;
-- end if ;
---- Log(OSVVM_ALERTLOG_ID, "SetLogEnable(OSVVM_ALERTLOG_ID, " & Name(1 to NameLen) & ", TRUE) ;", DEBUG) ;
-- LogLevel := LogType'value("" & Name(1 to NameLen)) ; -- "" & added for RivieraPro 2020.10
ToLogLevel(LogLevel, Name(1 to NameLen), LogValid) ;
exit ReadNameLoop when not LogValid ;
SetLogEnable(AlertLogID, LogLevel, TRUE) ;
end case ;
end loop ReadNameLoop ;
end loop ReadLineLoop ;
end procedure ReadLogEnables ;
------------------------------------------------------------
procedure ReadLogEnables (FileName : string) is
------------------------------------------------------------
file AlertLogInitFile : text open READ_MODE is FileName ;
begin
ReadLogEnables(AlertLogInitFile) ;
end procedure ReadLogEnables ;
------------------------------------------------------------
function PathTail (A : string) return string is
------------------------------------------------------------
alias aA : string(1 to A'length) is A ;
variable LenA : integer := A'length ;
variable Result : string(1 to A'length) ;
begin
if aA(LenA) = ':' then
LenA := LenA - 1 ;
end if ;
for i in LenA downto 1 loop
if aA(i) = ':' then
--!! GHDL Issue
-- return (1 to LenA - i => aA(i+1 to LenA)) ;
Result(1 to LenA - i) := aA(i+1 to LenA) ;
return Result(1 to LenA - i) ;
end if ;
end loop ;
return aA(1 to LenA) ;
end function PathTail ;
------------------------------------------------------------
-- MetaMatch
-- Similar to STD_MATCH, except
-- it returns TRUE for U=U, X=X, Z=Z, and W=W
-- All other values are consistent with STD_MATCH
-- MetaMatch, BooleanTableType, and MetaMatchTable are derivatives
-- of STD_MATCH from IEEE.Numeric_Std copyright by IEEE.
-- Numeric_Std is also released under the Apache License, Version 2.0.
-- Coding Styles were updated to match OSVVM
------------------------------------------------------------
type BooleanTableType is array(std_ulogic, std_ulogic) of boolean;
constant MetaMatchTable : BooleanTableType := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | U |
(FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | X |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | 0 |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | 1 |
(FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE), -- | Z |
(FALSE, FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, TRUE), -- | W |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | L |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | H |
(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE) -- | - |
);
function MetaMatch (l, r : std_ulogic) return boolean is
begin
return MetaMatchTable(l, r);
end function MetaMatch;
function MetaMatch (L, R : std_ulogic_vector) return boolean is
alias aL : std_ulogic_vector(1 to L'length) is L;
alias aR : std_ulogic_vector(1 to R'length) is R;
begin
if aL'length /= aR'length then
--! log(OSVVM_ALERTLOG_ID, "AlertLogPkg.MetaMatch: Length Mismatch", DEBUG) ;
return FALSE;
else
for i in aL'range loop
if not (MetaMatchTable(aL(i), aR(i))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end function MetaMatch;
function MetaMatch (L, R : unresolved_unsigned) return boolean is
begin
return MetaMatch( std_ulogic_vector(L), std_ulogic_vector(R)) ;
end function MetaMatch;
function MetaMatch (L, R : unresolved_signed) return boolean is
begin
return MetaMatch( std_ulogic_vector(L), std_ulogic_vector(R)) ;
end function MetaMatch;
------------------------------------------------------------
-- Helper function for NewID in data structures
function ResolvePrintParent (
------------------------------------------------------------
UniqueParent : boolean ;
PrintParent : AlertLogPrintParentType
) return AlertLogPrintParentType is
variable result : AlertLogPrintParentType ;
begin
if (not UniqueParent) and PrintParent = PRINT_NAME_AND_PARENT then
result := PRINT_NAME ;
else
result := PrintParent ;
end if ;
return result ;
end function ResolvePrintParent ;
-- synthesis translate_on
-- ------------------------------------------------------------
-- Deprecated
--
------------------------------------------------------------
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
begin
-- synthesis translate_off
AlertIf( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
-- deprecated
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertIf( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
return result ;
end function AlertIf ;
------------------------------------------------------------
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
begin
-- synthesis translate_off
AlertIfNot( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
-- deprecated
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertIfNot( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
return result ;
end function AlertIfNot ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType ; -- := PASSED
AlertLevel : AlertType := ERROR
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, Message, LogLevel) ; -- call log
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, Message, AlertLevel) ; -- signal failure
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) is
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, Message, PASSED, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) is
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, LogLevel, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) is
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, PASSED, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf;
end package body AlertLogPkg ; | artistic-2.0 |
UnofficialRepos/OSVVM | VendorCovApiPkg_Aldec.vhd | 2 | 4020 | --
-- File Name: VendorCovApiPkg_Aldec.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: ALDEC VERSION
--
-- Maintainer:
--
-- Package Defines
-- A set of foreign procedures that link OSVVM's CoveragePkg
-- coverage model creation and coverage capture with the
-- built-in capability of a simulator.
--
--
-- Revision History: For more details, see CoveragePkg_release_notes.pdf
-- Date Version Description
-- 11/2016: 2016.11 Initial revision
-- 12/2016 2016.11a Fixed an issue with attributes
-- 1/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2016 - 2020 by Aldec
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
package VendorCovApiPkg is
subtype VendorCovHandleType is integer;
-- Types for how coverage bins are represented. Matches OSVVM types.
type VendorCovRangeType is record
min: integer;
max: integer;
end record;
type VendorCovRangeArrayType is array ( integer range <> ) of VendorCovRangeType;
-- Create Initial Data Structure for Point/Item Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovPointCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovPointCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CvpCreate";
-- Create Initial Data Structure for Cross Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovCrossCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovCrossCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CrCreate";
-- Sets/Updates the name of the Coverage Model.
-- Should not be called until the data structure is created by VendorCovPointCreate or VendorCovCrossCreate.
-- Replaces name that was set by VendorCovPointCreate or VendorCovCrossCreate.
procedure VendorCovSetName( obj: VendorCovHandleType; name: string );
attribute foreign of VendorCovSetName[ VendorCovHandleType, string ]: procedure is "VHPI systf; cvg_SetCoverName";
-- Add a bin or set of bins to either a Point/Item or Cross Functional Coverage Model
-- Checking for sizing that is different from original sizing already done in OSVVM CoveragePkg
-- It is important to maintain an index that corresponds to the order the bins were entered as
-- that is used when coverage is recorded.
procedure VendorCovBinAdd( obj: VendorCovHandleType; bins: VendorCovRangeArrayType; Action: integer; atleast: integer; name: string );
attribute foreign of VendorCovBinAdd[ VendorCovHandleType, VendorCovRangeArrayType, integer, integer, string ]: procedure is "VHPI systf; cvg_CvpCrBinCreate";
-- Increment the coverage of bin identified by index number.
-- Index ranges from 1 to Number of Bins.
-- Index corresponds to the order the bins were entered (starting from 1)
procedure VendorCovBinInc( obj: VendorCovHandleType; index: integer );
attribute foreign of VendorCovBinInc[ VendorCovHandleType, integer ]: procedure is "VHPI systf; cvg_CvpCrBinIncr";
-- Action (integer):
-- constant COV_COUNT : integer := 1;
-- constant COV_IGNORE : integer := 0;
-- constant COV_ILLEGAL : integer := -1;
end package;
package body VendorCovApiPkg is
-- Replace any existing package body for this package
end package body VendorCovApiPkg ;
| artistic-2.0 |
UnofficialRepos/OSVVM | ScoreboardPkg_slv_c.vhd | 1 | 137840 | --
-- File Name: ScoreBoardPkg_slv.vhd
-- Design Unit Name: ScoreBoardPkg_slv
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis email: jim@synthworks.com
--
--
-- Description:
-- Defines types and methods to implement a FIFO based Scoreboard
-- Defines type ScoreBoardPType
-- Defines methods for putting values the scoreboard
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 03/2022 2022.03 Removed deprecated SetAlertLogID in Singleton API
-- 02/2022 2022.02 Added WriteScoreboardYaml and GotScoreboards. Updated NewID with ParentID,
-- ReportMode, Search, PrintParent. Supports searching for Scoreboard models..
-- 01/2022 2022.01 Added CheckExpected. Added SetCheckCountZero to ScoreboardPType
-- 08/2021 2021.08 Removed SetAlertLogID from singleton public interface - set instead by NewID
-- 06/2021 2021.06 Updated Data Structure, IDs for new use model, and Wrapper Subprograms
-- 10/2020 2020.10 Added Peek
-- 05/2020 2020.05 Updated calls to IncAffirmCount
-- Overloaded Check with functions that return pass/fail (T/F)
-- Added GetFifoCount. Added GetPushCount which is same as GetItemCount
-- 01/2020 2020.01 Updated Licenses to Apache
-- 04/2018 2018.04 Made Pop Functions Visible. Prep for AlertLogIDType being a type.
-- 05/2017 2017.05 First print Actual then only print Expected if mis-match
-- 11/2016 2016.11 Released as part of OSVVM
-- 06/2015 2015.06 Added Alerts, SetAlertLogID, Revised LocalPush, GetDropCount,
-- Deprecated SetFinish and ReportMode - REPORT_NONE, FileOpen
-- Deallocate, Initialized, Function SetName
-- 09/2013 2013.09 Added file handling, Check Count, Finish Status
-- Find, Flush
-- 08/2013 2013.08 Generics: to_string replaced write, Match replaced check
-- Added Tags - Experimental
-- Added Array of Scoreboards
-- 08/2012 2012.08 Added Type and Subprogram Generics
-- 05/2012 2012.05 Changed FIFO to store pointers to ExpectedType
-- Allows usage of unconstrained arrays
-- 08/2010 2010.08 Added Tailpointer
-- 12/2006 2006.12 Initial revision
--
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
use work.AlertLogPkg.all ;
use work.NamePkg.all ;
use work.NameStorePkg.all ;
use work.ResolutionPkg.all ;
package ScoreBoardPkg_slv is
-- generic (
-- type ExpectedType ;
-- type ActualType ;
-- function Match(Actual : ActualType ; -- defaults
-- Expected : ExpectedType) return boolean ; -- is "=" ;
-- function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
-- function actual_to_string (A : ActualType) return string -- is to_string ;
-- ) ;
-- -- For a VHDL-2002 package, comment out the generics and
-- -- uncomment the following, it replaces a generic instance of the package.
-- -- As a result, you will have multiple copies of the entire package.
-- -- Inconvenient, but ok as it still works the same.
subtype ExpectedType is std_ulogic_vector ;
subtype ActualType is std_ulogic_vector ;
alias Match is work.AlertLogPkg.MetaMatch [std_ulogic_vector, std_ulogic_vector return boolean] ; -- for std_logic_vector
alias expected_to_string is to_hstring [std_logic_vector return string]; -- VHDL-2008
alias actual_to_string is to_hstring [std_logic_vector return string]; -- VHDL-2008
-- ScoreboardReportType is deprecated
-- Replaced by Affirmations. ERROR is the default. ALL turns on PASSED flag
type ScoreboardReportType is (REPORT_ERROR, REPORT_ALL, REPORT_NONE) ; -- replaced by affirmations
type ScoreboardIdType is record
Id : integer_max ;
end record ScoreboardIdType ;
type ScoreboardIdArrayType is array (integer range <>) of ScoreboardIdType ;
type ScoreboardIdMatrixType is array (integer range <>, integer range <>) of ScoreboardIdType ;
-- Preparation for refactoring - if that ever happens.
subtype FifoIdType is ScoreboardIdType ;
subtype FifoIdArrayType is ScoreboardIdArrayType ;
subtype FifoIdMatrixType is ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) ; -- Deletes all allocated items
procedure Initialize (
constant ID : in ScoreboardIDType
) ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType ;
type ScoreBoardPType is protected
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Emulate arrays of scoreboards
procedure SetArrayIndex(L, R : integer) ; -- supports integer indices
procedure SetArrayIndex(R : natural) ; -- indicies 1 to R
impure function GetArrayIndex return integer_vector ;
impure function GetArrayLength return natural ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Push (
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Push (
constant Index : in integer ;
constant Item : in ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Push (
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Push items into the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Push (Item : ExpectedType) return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Push (
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Push (
-- constant Index : in integer ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Push (
-- constant Index : in integer ;
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ; -- for chaining of operations
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) ;
-- Simple Tagged Scoreboard
procedure Check (
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Array of Scoreboards, no tag
procedure Check (
constant Index : in integer ;
constant ActualData : in ActualType
) ;
-- Array of Tagged Scoreboards
procedure Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Scoreboards, no tag
impure function Check (
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Tagged Scoreboards
impure function Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-------------------------------
-- Array of Tagged Scoreboards
impure function CheckExpected (
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Pop (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Pop (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType ;
-- Array of Tagged Scoreboards
impure function Pop (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Array of Tagged Scoreboards
procedure Peek (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Peek (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Peek (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Array of Tagged Scoreboards
impure function Peek (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Peek (
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
impure function Empty return boolean ; -- Simple
impure function Empty (Tag : String) return boolean ; -- Simple, Tagged
impure function Empty (Index : integer) return boolean ; -- Array
impure function Empty (Index : integer; Tag : String) return boolean ; -- Array, Tagged
------------------------------------------------------------
-- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
-- ReportMode := ENABLED when not DoNotReport else DISABLED ;
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
-- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) ;
procedure SetAlertLogID (A : AlertLogIDType) ;
impure function GetAlertLogID(Index : Integer) return AlertLogIDType ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
-- Set a scoreboard name.
-- Used when scoreboard AlertLogID is shared between different sources.
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
impure function GetName (DefaultName : string := "Scoreboard") return string ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount return integer ; -- Simple, with or without tags
impure function GetItemCount (Index : integer) return integer ; -- Arrays, with or without tags
impure function GetPushCount return integer ; -- Simple, with or without tags
impure function GetPushCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (Index : integer) return integer ;
impure function GetPopCount return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (Index : integer) return integer ;
impure function GetFifoCount return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount return integer ; -- Simple, with or without tags
impure function GetCheckCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount return integer ; -- Simple, with or without tags
impure function GetDropCount (Index : integer) return integer ; -- Arrays, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
-- Array of Simple Scoreboards
impure function Find (
constant Index : in integer ;
constant ActualData : in ActualType
) return integer ;
-- Array of Tagged Scoreboards
impure function Find (
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboard
procedure Flush (
constant ItemNumber : in integer
) ;
-- Tagged Scoreboard - only removes items that also match the tag
procedure Flush (
constant Tag : in string ;
constant ItemNumber : in integer
) ;
-- Array of Simple Scoreboards
procedure Flush (
constant Index : in integer ;
constant ItemNumber : in integer
) ;
-- Array of Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate ; -- Deletes all allocated items
procedure Initialize ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Use alerts directly instead.
-- AlertIF(SB.GetCheckCount < 10, ....) ;
-- AlertIf(Not SB.Empty, ...) ;
------------------------------------------------------------
-- Set alerts if scoreboard not empty or if CheckCount <
-- Use if need to check empty or CheckCount for a specific scoreboard.
-- Simple Scoreboards, with or without tag
procedure CheckFinish (
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
-- Array of Scoreboards, with or without tag
procedure CheckFinish (
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Simple Scoreboards, with or without tag
impure function GetErrorCount return integer ;
-- Array of Scoreboards, with or without tag
impure function GetErrorCount(Index : integer) return integer ;
------------------------------------------------------------
-- Error count manipulation
-- IncErrorCount - not recommended, use alerts instead - may be deprecated in the future
procedure IncErrorCount ; -- Simple, with or without tags
procedure IncErrorCount (Index : integer) ; -- Arrays, with or without tags
-- Clear error counter. Caution does not change AlertCounts, must also use AlertLogPkg.ClearAlerts
procedure SetErrorCountZero ; -- Simple, with or without tags
procedure SetErrorCountZero (Index : integer) ; -- Arrays, with or without tags
-- Clear check counter. Caution does not change AffirmationCounters
procedure SetCheckCountZero ; -- Simple, with or without tags
procedure SetCheckCountZero (Index : integer) ; -- Arrays, with or without tags
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Names changed. Maintained for backward compatibility - would prefer an alias
------------------------------------------------------------
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) ; -- Replaced by TranscriptPkg.TranscriptOpen
procedure PutExpectedData (ExpectedData : ExpectedType) ; -- Replaced by push
procedure CheckActualData (ActualData : ActualType) ; -- Replaced by Check
impure function GetItemNumber return integer ; -- Replaced by GetItemCount
procedure SetMessage (MessageIn : String) ; -- Replaced by SetName
impure function GetMessage return string ; -- Replaced by GetName
-- Deprecated and may be deleted in a future revision
procedure SetFinish ( -- Replaced by CheckFinish
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
procedure SetFinish ( -- Replaced by CheckFinish
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (ReportModeIn : ScoreboardReportType) ;
impure function GetReportMode return ScoreboardReportType ;
------------------------------------------------------------
------------------------------------------------------------
-- -- Deprecated Interface to NewID
-- impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- -- Vector: 1 to Size
-- impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Vector: X(X'Left) to X(X'Right)
-- impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Matrix: 1 to X, 1 to Y
-- impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
-- impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end protected ScoreBoardPType ;
------------------------------------------------------------
-- Deprecated Interface to NewID
impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- Vector: 1 to Size
impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end ScoreBoardPkg_slv ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body ScoreBoardPkg_slv is
type ScoreBoardPType is protected body
type ExpectedPointerType is access ExpectedType ;
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
ItemNumber : integer ;
TagPtr : line ;
ExpectedPtr : ExpectedPointerType ;
NextPtr : ListPointerType ;
end record ;
--!! Replace the following with
-- type ScoreboardRecType is record
-- HeadPointer : ListPointerType ;
-- TailPointer : ListPointerType ;
-- PopListPointer : ListPointerType ;
--
-- ErrCnt : integer ;
-- DropCount : integer ;
-- ItemNumber : integer ;
-- PopCount : integer ;
-- CheckCount : integer ;
-- AlertLogID : AlertLogIDType ;
-- Name : NameStoreIDType ;
-- ReportMode : ScoreboardReportType ;
-- end record ScoreboardRecType ;
--
-- type ScoreboardRecArrayType is array (integer range <>) of ScoreboardRecType ;
-- type ScoreboardRecArrayPointerType is access ScoreboardRecArrayType ;
-- variable ScoreboardPointer : ScoreboardRecArrayPointerType ;
--
-- -- Alas unfortunately aliases don't word as follows:
-- -- alias HeadPointer(I) is ScoreboardPointer(I).HeadPointer ;
type ListArrayType is array (integer range <>) of ListPointerType ;
type ListArrayPointerType is access ListArrayType ;
variable ArrayLengthVar : integer := 1 ;
-- Original Code
-- variable HeadPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
--
-- Legal, but crashes simulator more thoroughly
-- variable HeadPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- Working work around for QS 2020.04 and 2021.02
variable Template : ListArrayType(1 to 1) ; -- Work around for QS 2020.04 and 2021.02
variable HeadPointer : ListArrayPointerType := new ListArrayType'(Template) ;
variable TailPointer : ListArrayPointerType := new ListArrayType'(Template) ;
-- PopListPointer needed for Pop to be a function - alternately need 2019 features
variable PopListPointer : ListArrayPointerType := new ListArrayType'(Template) ;
type IntegerArrayType is array (integer range <>) of Integer ;
type IntegerArrayPointerType is access IntegerArrayType ;
type AlertLogIDArrayType is array (integer range <>) of AlertLogIDType ;
type AlertLogIDArrayPointerType is access AlertLogIDArrayType ;
variable ErrCntVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable DropCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable ItemNumberVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable PopCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable CheckCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable AlertLogIDVar : AlertLogIDArrayPointerType := new AlertLogIDArrayType'(1 => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
variable NameVar : NamePType ;
variable ReportModeVar : ScoreboardReportType ;
variable FirstIndexVar : integer := 1 ;
variable PrintIndexVar : boolean := TRUE ;
variable CalledNewID : boolean := FALSE ;
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Used by ScoreboardStore
variable NumItems : integer := 0 ;
constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
-- constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
------------------------------------------------------------
procedure SetPrintIndex (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
PrintIndexVar := Enable ;
end procedure SetPrintIndex ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
constant MinNumItems : in integer
) is
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
if NewNumItems > HeadPointer'length then
SetArrayIndex(1, NormalizeArraySize(NewNumItems, MinNumItems)) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
-- Local/Private to package
impure function LocalNewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable NameID : integer ;
begin
NameID := LocalNameStore.find(Name, ParentID, Search) ;
-- Share the scoreboards if they match
if NameID /= ID_NOT_FOUND.ID then
return ScoreboardIDType'(ID => NameID) ;
else
-- Resize Data Structure as necessary
GrowNumberItems(NumItems, GrowAmount => 1, MinNumItems => MIN_NUM_ITEMS) ;
-- Create AlertLogID
AlertLogIDVar(NumItems) := NewID(Name, ParentID, ReportMode, PrintParent, CreateHierarchy => FALSE) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, Search) ;
AlertIfNotEqual(AlertLogIDVar(NumItems), NameID, NumItems, "ScoreboardPkg: Index of LocalNameStore /= ScoreboardID") ;
return ScoreboardIDType'(ID => NumItems) ;
end if ;
end function LocalNewID ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
return LocalNewID(Name, ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector. Assumes valid range (done by NewID)
impure function LocalNewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
variable Result : ScoreboardIDArrayType(X(X'left) to X(X'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in Result'range loop
Result(i) := LocalNewID(Name & "(" & to_string(i) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1, Size) , ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Array parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Array parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
return LocalNewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix. Assumes valid indices (done by NewID)
impure function LocalNewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable Result : ScoreboardIdMatrixType(X(X'left) to X(X'right), Y(Y'left) to Y(Y'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ;
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in X(X'left) to X(X'right) loop
for j in Y(Y'left) to Y(Y'right) loop
Result(i, j) := LocalNewID(Name & "(" & to_string(i) & ", " & to_string(j) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1,X), (1,Y), ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Matrix parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, Y'length /= 2, "ScoreboardPkg.NewID Matrix parameter Y has " & to_string(Y'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Matrix parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
AlertIf(ParentID, Y(Y'Left) > Y(Y'right), "ScoreboardPkg.NewID Matrix parameter Y(Y'left): " & to_string(Y'Left) & " must be <= Y(Y'right): " & to_string(Y(Y'right)), FAILURE) ;
return LocalNewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName (DefaultName : string := "Scoreboard") return string is
------------------------------------------------------------
begin
return NameVar.Get(DefaultName) ;
end function GetName ;
------------------------------------------------------------
procedure SetReportMode (ReportModeIn : ScoreboardReportType) is
------------------------------------------------------------
begin
ReportModeVar := ReportModeIn ;
if ReportModeVar = REPORT_ALL then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: To turn off REPORT_ALL, use osvvm.AlertLogPkg.SetLogEnable(PASSED, FALSE)", WARNING) ;
for i in AlertLogIDVar'range loop
SetLogEnable(AlertLogIDVar(i), PASSED, TRUE) ;
end loop ;
end if ;
if ReportModeVar = REPORT_NONE then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: ReportMode REPORT_NONE has been deprecated and will be removed in next revision. Please contact OSVVM architect Jim Lewis if you need this capability.", WARNING) ;
end if ;
end procedure SetReportMode ;
------------------------------------------------------------
impure function GetReportMode return ScoreboardReportType is
------------------------------------------------------------
begin
return ReportModeVar ;
end function GetReportMode ;
------------------------------------------------------------
procedure SetArrayIndex(L, R : integer) is
------------------------------------------------------------
variable OldHeadPointer, OldTailPointer, OldPopListPointer : ListArrayPointerType ;
variable OldErrCnt, OldDropCount, OldItemNumber, OldPopCount, OldCheckCount : IntegerArrayPointerType ;
variable OldAlertLogIDVar : AlertLogIDArrayPointerType ;
variable Min, Max, Len, OldLen, OldMax : integer ;
begin
Min := minimum(L, R) ;
Max := maximum(L, R) ;
OldLen := ArrayLengthVar ;
OldMax := Min + ArrayLengthVar - 1 ;
Len := Max - Min + 1 ;
ArrayLengthVar := Len ;
if Len >= OldLen then
FirstIndexVar := Min ;
OldHeadPointer := HeadPointer ;
HeadPointer := new ListArrayType(Min to Max) ;
if OldHeadPointer /= NULL then
HeadPointer(Min to OldMax) := OldHeadPointer.all ; -- (OldHeadPointer'range) ;
Deallocate(OldHeadPointer) ;
end if ;
OldTailPointer := TailPointer ;
TailPointer := new ListArrayType(Min to Max) ;
if OldTailPointer /= NULL then
TailPointer(Min to OldMax) := OldTailPointer.all ;
Deallocate(OldTailPointer) ;
end if ;
OldPopListPointer := PopListPointer ;
PopListPointer := new ListArrayType(Min to Max) ;
if OldPopListPointer /= NULL then
PopListPointer(Min to OldMax) := OldPopListPointer.all ;
Deallocate(OldPopListPointer) ;
end if ;
OldErrCnt := ErrCntVar ;
ErrCntVar := new IntegerArrayType'(Min to Max => 0) ;
if OldErrCnt /= NULL then
ErrCntVar(Min to OldMax) := OldErrCnt.all ;
Deallocate(OldErrCnt) ;
end if ;
OldDropCount := DropCountVar ;
DropCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldDropCount /= NULL then
DropCountVar(Min to OldMax) := OldDropCount.all ;
Deallocate(OldDropCount) ;
end if ;
OldItemNumber := ItemNumberVar ;
ItemNumberVar := new IntegerArrayType'(Min to Max => 0) ;
if OldItemNumber /= NULL then
ItemNumberVar(Min to OldMax) := OldItemNumber.all ;
Deallocate(OldItemNumber) ;
end if ;
OldPopCount := PopCountVar ;
PopCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldPopCount /= NULL then
PopCountVar(Min to OldMax) := OldPopCount.all ;
Deallocate(OldPopCount) ;
end if ;
OldCheckCount := CheckCountVar ;
CheckCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldCheckCount /= NULL then
CheckCountVar(Min to OldMax) := OldCheckCount.all ;
Deallocate(OldCheckCount) ;
end if ;
OldAlertLogIDVar := AlertLogIDVar ;
AlertLogIDVar := new AlertLogIDArrayType'(Min to Max => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
if OldAlertLogIDVar /= NULL then
AlertLogIDVar(Min to OldMax) := OldAlertLogIDVar.all ;
Deallocate(OldAlertLogIDVar) ;
end if ;
elsif Len < OldLen then
report "ScoreboardGenericPkg: SetArrayIndex, new array Length <= current array length"
severity failure ;
end if ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure SetArrayIndex(R : natural) is
------------------------------------------------------------
begin
SetArrayIndex(1, R) ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
variable CurListPtr, LastListPtr : ListPointerType ;
begin
for Index in HeadPointer'range loop
-- Deallocate contents in the scoreboards
CurListPtr := HeadPointer(Index) ;
while CurListPtr /= Null loop
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
LastListPtr := CurListPtr ;
CurListPtr := CurListPtr.NextPtr ;
Deallocate(LastListPtr) ;
end loop ;
end loop ;
for Index in PopListPointer'range loop
-- Deallocate PopListPointer - only has single element
CurListPtr := PopListPointer(Index) ;
if CurListPtr /= NULL then
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
deallocate(CurListPtr) ;
end if ;
end loop ;
-- Deallocate arrays of pointers
Deallocate(HeadPointer) ;
Deallocate(TailPointer) ;
Deallocate(PopListPointer) ;
-- Deallocate supporting arrays
Deallocate(ErrCntVar) ;
Deallocate(DropCountVar) ;
Deallocate(ItemNumberVar) ;
Deallocate(PopCountVar) ;
Deallocate(CheckCountVar) ;
Deallocate(AlertLogIDVar) ;
-- Deallocate NameVar - NamePType
NameVar.Deallocate ;
ArrayLengthVar := 0 ;
NumItems := 0 ;
CalledNewID := FALSE ;
end procedure Deallocate ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize is
------------------------------------------------------------
begin
SetArrayIndex(1, 1) ;
end procedure Initialize ;
------------------------------------------------------------
impure function GetArrayIndex return integer_vector is
------------------------------------------------------------
begin
return (1 => HeadPointer'left, 2 => HeadPointer'right) ;
end function GetArrayIndex ;
------------------------------------------------------------
impure function GetArrayLength return natural is
------------------------------------------------------------
begin
return ArrayLengthVar ; -- HeadPointer'length ;
end function GetArrayLength ;
------------------------------------------------------------
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(Index) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(FirstIndexVar) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Index : Integer) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(Index) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(FirstIndexVar) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function LocalOutOfRange(
------------------------------------------------------------
constant Index : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_SCOREBOARD_ALERTLOG_ID, Index < HeadPointer'Low or Index > HeadPointer'High,
GetName & " " & Name & " Index: " & to_string(Index) &
"is not in the range (" & to_string(HeadPointer'Low) &
"to " & to_string(HeadPointer'High) & ")",
FAILURE ) ;
end function LocalOutOfRange ;
------------------------------------------------------------
procedure LocalPush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
ItemNumberVar(Index) := ItemNumberVar(Index) + 1 ;
ExpectedPtr := new ExpectedType'(Item) ;
TagPtr := new string'(Tag) ;
if HeadPointer(Index) = NULL then
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- HeadPointer(Index) := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
HeadPointer(Index) := new ListType ;
HeadPointer(Index).ItemNumber := ItemNumberVar(Index) ;
HeadPointer(Index).TagPtr := TagPtr ;
HeadPointer(Index).ExpectedPtr := ExpectedPtr ;
HeadPointer(Index).NextPtr := NULL ;
TailPointer(Index) := HeadPointer(Index) ;
else
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- TailPointer(Index).NextPtr := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
TailPointer(Index).NextPtr := new ListType ;
TailPointer(Index).NextPtr.ItemNumber := ItemNumberVar(Index) ;
TailPointer(Index).NextPtr.TagPtr := TagPtr ;
TailPointer(Index).NextPtr.ExpectedPtr := ExpectedPtr ;
TailPointer(Index).NextPtr.NextPtr := NULL ;
TailPointer(Index) := TailPointer(Index).NextPtr ;
end if ;
end procedure LocalPush ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) is
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Push (Item : ExpectedType) return ExpectedType is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Local Only
-- Pops highest element matching Tag into PopListPointer(Index)
procedure LocalPop (Index : integer ; Tag : string; Name : string) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Pop/Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during " & Name, FAILURE) ;
return ;
end if ;
PopCountVar(Index) := PopCountVar(Index) + 1 ;
-- deallocate previous pointer
if PopListPointer(Index) /= NULL then
deallocate(PopListPointer(Index).TagPtr) ;
deallocate(PopListPointer(Index).ExpectedPtr) ;
deallocate(PopListPointer(Index)) ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
PopListPointer(Index) := HeadPointer(Index) ;
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Pop/Check (" & Name & "), tag: " & Tag & " not found", FAILURE) ;
exit ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
PopListPointer(Index) := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
if CurPtr.NextPtr = NULL then
TailPointer(Index) := CurPtr ;
end if ;
exit ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end procedure LocalPop ;
------------------------------------------------------------
-- Local Only
procedure LocalCheck (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType ;
variable FoundError : inout boolean ;
constant ExpectedInFIFO : in boolean := TRUE
) is
variable ExpectedPtr : ExpectedPointerType ;
variable CurrentItem : integer ;
variable WriteBuf : line ;
variable PassedFlagEnabled : boolean ;
begin
CheckCountVar(Index) := CheckCountVar(Index) + 1 ;
ExpectedPtr := PopListPointer(Index).ExpectedPtr ;
CurrentItem := PopListPointer(Index).ItemNumber ;
PassedFlagEnabled := GetLogEnable(AlertLogIDVar(Index), PASSED) ;
if not Match(ActualData, ExpectedPtr.all) then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
FoundError := TRUE ;
IncAffirmCount(AlertLogIDVar(Index)) ;
else
FoundError := FALSE ;
if not PassedFlagEnabled then
IncAffirmPassedCount(AlertLogIDVar(Index)) ;
end if ;
end if ;
-- IncAffirmCount(AlertLogIDVar(Index)) ;
-- if FoundError or ReportModeVar = REPORT_ALL then
if FoundError or PassedFlagEnabled then
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 and PrintIndexVar then
write(WriteBuf, " (" & to_string(Index) & ") ") ;
end if ;
if ExpectedInFIFO then
write(WriteBuf, " Received: " & actual_to_string(ActualData)) ;
if FoundError then
write(WriteBuf, " Expected: " & expected_to_string(ExpectedPtr.all)) ;
end if ;
else
write(WriteBuf, " Received: " & expected_to_string(ExpectedPtr.all)) ;
if FoundError then
write(WriteBuf, " Expected: " & actual_to_string(ActualData)) ;
end if ;
end if ;
if PopListPointer(Index).TagPtr.all /= "" then
write(WriteBuf, " Tag: " & PopListPointer(Index).TagPtr.all) ;
end if;
write(WriteBuf, " Item Number: " & to_string(CurrentItem)) ;
if FoundError then
if ReportModeVar /= REPORT_NONE then
-- Affirmation Failed
Alert(AlertLogIDVar(Index), WriteBuf.all, ERROR) ;
else
-- Affirmation Failed, but silent, unless in DEBUG mode
Log(AlertLogIDVar(Index), "ERROR " & WriteBuf.all, DEBUG) ;
IncAlertCount(AlertLogIDVar(Index)) ; -- Silent Counted Alert
end if ;
else
-- Affirmation passed, PASSED flag increments AffirmCount
Log(AlertLogIDVar(Index), WriteBuf.all, PASSED) ;
end if ;
deallocate(WriteBuf) ;
end if ;
end procedure LocalCheck ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Scoreboard Store. Index. Tag.
impure function CheckExpected (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ExpectedData, FoundError, ExpectedInFIFO => FALSE) ;
return not FoundError ;
end function CheckExpected ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Pop (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, Tag, "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType is
------------------------------------------------------------
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, "", "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Pop (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Local Only similar to LocalPop
-- Returns a pointer to the highest element matching Tag
impure function LocalPeek (Index : integer ; Tag : string) return ListPointerType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
--!! LocalPeek does this, but so do each of the indexed calls
--!! if LocalOutOfRange(Index, "Peek") then
--!! return NULL ; -- error reporting in LocalOutOfRange
--!! end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during Peek", FAILURE) ;
return NULL ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
return CurPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Peek, tag: " & Tag & " not found", FAILURE) ;
return NULL ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
return CurPtr ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end function LocalPeek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Peek (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Peek (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Empty (Index : integer; Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := HeadPointer(Index) ;
while CurPtr /= NULL loop
if CurPtr.TagPtr.all = Tag then
return FALSE ; -- Found Tag
end if ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return TRUE ; -- Tag not found
end function Empty ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Empty (Index : integer) return boolean is
------------------------------------------------------------
begin
return HeadPointer(Index) = NULL ;
end function Empty ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Empty (Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
return Empty(FirstIndexVar, Tag) ;
end function Empty ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Empty return boolean is
------------------------------------------------------------
begin
return HeadPointer(FirstIndexVar) = NULL ;
end function Empty ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
variable EmptyError : Boolean ;
variable WriteBuf : line ;
begin
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
if WriteBuf.all /= "" then
swrite(WriteBuf, " ") ;
end if ;
write(WriteBuf, "Index(" & to_string(Index) & "), ") ;
else
if WriteBuf.all /= "" then
swrite(WriteBuf, ", ") ;
end if ;
end if ;
if FinishEmpty then
AffirmIf(AlertLogIDVar(Index), Empty(Index), WriteBuf.all & "Checking Empty: " & to_string(Empty(Index)) &
" FinishEmpty: " & to_string(FinishEmpty)) ;
if not Empty(Index) then
-- Increment internal count on FinishEmpty Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
end if ;
AffirmIf(AlertLogIDVar(Index), CheckCountVar(Index) >= FinishCheckCount, WriteBuf.all &
"Checking CheckCount: " & to_string(CheckCountVar(Index)) &
" >= Expected: " & to_string(FinishCheckCount)) ;
if not (CheckCountVar(Index) >= FinishCheckCount) then
-- Increment internal count on FinishCheckCount Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
deallocate(WriteBuf) ;
end procedure CheckFinish ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
for AlertLogID in AlertLogIDVar'range loop
CheckFinish(AlertLogID, FinishCheckCount, FinishEmpty) ;
end loop ;
end procedure CheckFinish ;
------------------------------------------------------------
impure function GetErrorCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ErrCntVar(Index) ;
end function GetErrorCount ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable TotalErrorCount : integer := 0 ;
begin
for Index in AlertLogIDVar'range loop
TotalErrorCount := TotalErrorCount + GetErrorCount(Index) ;
end loop ;
return TotalErrorCount ;
end function GetErrorCount ;
------------------------------------------------------------
procedure IncErrorCount (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
IncAlertCount(AlertLogIDVar(Index), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure IncErrorCount is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := ErrCntVar(FirstIndexVar) + 1 ;
IncAlertCount(AlertLogIDVar(FirstIndexVar), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure SetErrorCountZero (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := 0;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetErrorCountZero is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := 0 ;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero (Index : integer) is
------------------------------------------------------------
begin
CheckCountVar(Index) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero is
------------------------------------------------------------
begin
CheckCountVar(FirstIndexVar) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
impure function GetItemCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetPushCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPushCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPopCount (Index : integer) return integer is
------------------------------------------------------------
begin
return PopCountVar(Index) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetPopCount return integer is
------------------------------------------------------------
begin
return PopCountVar(FirstIndexVar) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetFifoCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) - PopCountVar(Index) - DropCountVar(Index) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetFifoCount return integer is
------------------------------------------------------------
begin
return GetFifoCount(FirstIndexVar) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetCheckCount (Index : integer) return integer is
------------------------------------------------------------
begin
return CheckCountVar(Index) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetCheckCount return integer is
------------------------------------------------------------
begin
return CheckCountVar(FirstIndexVar) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetDropCount (Index : integer) return integer is
------------------------------------------------------------
begin
return DropCountVar(Index) ;
end function GetDropCount ;
------------------------------------------------------------
impure function GetDropCount return integer is
------------------------------------------------------------
begin
return DropCountVar(FirstIndexVar) ;
end function GetDropCount ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
Alert(AlertLogIDVar(Index), "OSVVM.ScoreboardGenericPkg.SetFinish: Deprecated and removed. See CheckFinish", ERROR) ;
end procedure SetFinish ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
SetFinish(FirstIndexVar, FCheckCount, FEmpty, FStatus) ;
end procedure SetFinish ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Find Element with Matching Tag and ActualData
-- Returns integer'left if no match found
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return integer'left ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Failed to find it
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
if Tag /= "" then
Alert(AlertLogIDVar(Index),
GetName & " Did not find Tag: " & Tag & " and Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
else
Alert(AlertLogIDVar(Index),
GetName & " Did not find Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
end if ;
return integer'left ;
elsif CurPtr.TagPtr.all = Tag and
Match(ActualData, CurPtr.ExpectedPtr.all) then
-- Found it. Return Index.
return CurPtr.ItemNumber ;
else -- Descend
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end function Find ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return integer is
begin
return Find(Index, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Simple Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
variable CurPtr, RemovePtr, LastPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
LastPtr := NULL ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif CurPtr.TagPtr.all = Tag then
if ItemNumber >= CurPtr.ItemNumber then
-- remove it
RemovePtr := CurPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := LastPtr ;
end if ;
if CurPtr = HeadPointer(Index) then
HeadPointer(Index) := CurPtr.NextPtr ;
else -- if LastPtr /= NULL then
LastPtr.NextPtr := LastPtr.NextPtr.NextPtr ;
end if ;
CurPtr := CurPtr.NextPtr ;
-- LastPtr := LastPtr ; -- no change
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(RemovePtr.TagPtr) ;
deallocate(RemovePtr.ExpectedPtr) ;
deallocate(RemovePtr) ;
else
-- Done
return ;
end if ;
else
-- Descend
LastPtr := CurPtr ;
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant ItemNumber : in integer
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif ItemNumber >= CurPtr.ItemNumber then
-- Descend, Check Tail, Deallocate
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := NULL ;
end if ;
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(CurPtr.TagPtr) ;
deallocate(CurPtr.ExpectedPtr) ;
deallocate(CurPtr) ;
CurPtr := HeadPointer(Index) ;
else
-- Done
return ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Simple Scoreboard
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
impure function GotScoreboards return boolean is
------------------------------------------------------------
begin
return CalledNewID ;
end function GotScoreboards ;
------------------------------------------------------------
-- pt local
procedure WriteScoreboardYaml (Index : integer; file CovYamlFile : text) is
------------------------------------------------------------
variable buf : line ;
constant NAME_PREFIX : string := " " ;
begin
write(buf, NAME_PREFIX & "- Name: " & '"' & string'(GetAlertLogName(AlertLogIDVar(Index))) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemCount: " & '"' & to_string(ItemNumberVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ErrorCount: " & '"' & to_string(ErrCntVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsChecked: " & '"' & to_string(CheckCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsPopped: " & '"' & to_string(PopCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsDropped: " & '"' & to_string(DropCountVar(Index)) & '"' & LF) ;
writeline(CovYamlFile, buf) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_sb.yml", FileName) ;
file SbYamlFile : text open OpenKind is RESOLVED_FILE_NAME ;
variable buf : line ;
begin
if AlertLogIDVar = NULL or AlertLogIDVar'length <= 0 then
Alert("Scoreboard.WriteScoreboardYaml: no scoreboards defined ", ERROR) ;
return ;
end if ;
swrite(buf, "Version: 1.0" & LF) ;
swrite(buf, "TestCase: " & '"' & GetAlertLogName & '"' & LF) ;
swrite(buf, "Scoreboards: ") ;
writeline(SbYamlFile, buf) ;
if CalledNewID then
-- Used by singleton
for i in 1 to NumItems loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
else
-- Used by PT method, but not singleton
for i in AlertLogIDVar'range loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
end if ;
file_close(SbYamlFile) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
------------------------------------------------------------
-- Remaining Deprecated.
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
-- Use TranscriptPkg.TranscriptOpen
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
-- WriteFileInit := TRUE ;
-- file_open( WriteFile , FileName , OpenKind );
TranscriptOpen(FileName, OpenKind) ;
end procedure FileOpen ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure PutExpectedData (ExpectedData : ExpectedType) is
------------------------------------------------------------
begin
Push(ExpectedData) ;
end procedure PutExpectedData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure CheckActualData (ActualData : ActualType) is
------------------------------------------------------------
begin
Check(ActualData) ;
end procedure CheckActualData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetItemNumber return integer is
------------------------------------------------------------
begin
return GetItemCount(FirstIndexVar) ;
end GetItemNumber ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure SetMessage (MessageIn : String) is
------------------------------------------------------------
begin
-- deallocate(Message) ;
-- Message := new string'(MessageIn) ;
SetName(MessageIn) ;
end procedure SetMessage ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetMessage return string is
------------------------------------------------------------
begin
-- return Message.all ;
return GetName("Scoreboard") ;
end function GetMessage ;
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: 1 to Size
--!! impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, (1, Size) , ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: X(X'Left) to X(X'Right)
--!! impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: 1 to X, 1 to Y
--!! impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
--!! impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
end protected body ScoreBoardPType ;
shared variable ScoreboardStore : ScoreBoardPType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, Size, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (
------------------------------------------------------------
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Item) ;
end procedure Push ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, ActualData) ;
end procedure Check ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end procedure Check ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, ActualData) ;
end function Check ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end function Check ;
-------------
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end procedure CheckExpected ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end procedure CheckExpected ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end function CheckExpected ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end function CheckExpected ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Item) ;
end procedure Pop ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Tag, Item) ;
end procedure Pop ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID) ;
end function Pop ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID, Tag) ;
end function Pop ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Tag, Item) ;
end procedure Peek ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Item) ;
end procedure Peek ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
-- return ScoreboardStore.Peek(Tag) ;
log("Issues compiling return later");
return ScoreboardStore.Peek(Index => ID.ID, Tag => Tag) ;
end function Peek ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Peek(Index => ID.ID) ;
end function Peek ;
------------------------------------------------------------
-- ScoreboardEmpty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function ScoreboardEmpty ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function ScoreboardEmpty ;
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function Empty ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function Empty ;
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, Name, ParentID, CreateHierarchy, DoNotReport) ;
--!! end procedure SetAlertLogID ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, A) ;
--!! end procedure SetAlertLogID ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType is
begin
return ScoreboardStore.GetAlertLogID(ID.ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetItemCount(ID.ID) ;
end function GetItemCount ;
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPushCount(ID.ID) ;
end function GetPushCount ;
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPopCount(ID.ID) ;
end function GetPopCount ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetFifoCount(ID.ID) ;
end function GetFifoCount ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetCheckCount(ID.ID) ;
end function GetCheckCount ;
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetDropCount(ID.ID) ;
end function GetDropCount ;
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, ActualData) ;
end function Find ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, ItemNumber) ;
end procedure Flush ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Scoreboard YAML Reports
impure function GotScoreboards return boolean is
begin
return ScoreboardStore.GotScoreboards ;
end function GotScoreboards ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
begin
ScoreboardStore.WriteScoreboardYaml(FileName, OpenKind) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Deallocate ;
end procedure Deallocate ;
procedure Initialize (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Initialize ;
end procedure Initialize ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer is
begin
return GetAlertCount(ScoreboardStore.GetAlertLogID(ID.ID)) ;
end function GetErrorCount ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
ScoreboardStore.CheckFinish(ID.ID, FinishCheckCount, FinishEmpty) ;
end procedure CheckFinish ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) is
begin
-- ScoreboardStore.SetReportMode(ID.ID, ReportModeIn) ;
ScoreboardStore.SetReportMode(ReportModeIn) ;
end procedure SetReportMode ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType is
begin
-- return ScoreboardStore.GetReportMode(ID.ID) ;
return ScoreboardStore.GetReportMode ;
end function GetReportMode ;
--==========================================================
--!! Deprecated Subprograms
--==========================================================
------------------------------------------------------------
-- Deprecated interface to NewID
impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, Size, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
end ScoreBoardPkg_slv ; | artistic-2.0 |
hterkelsen/mal | vhdl/reader.vhdl | 10 | 10133 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package reader is
procedure read_str(s: in string; result: out mal_val_ptr; err: out mal_val_ptr);
end package reader;
package body reader is
type token_list is array(natural range <>) of line;
type token_list_ptr is access token_list;
function is_eol_char(c: in character) return boolean is
begin
case c is
when LF | CR => return true;
when others => return false;
end case;
end function is_eol_char;
function is_separator_char(c: in character) return boolean is
begin
case c is
when LF | CR | ' ' | '[' | ']' | '{' | '}' | '(' | ')' |
''' | '"' | '`' | ',' | ';' => return true;
when others => return false;
end case;
end function is_separator_char;
procedure next_token(str: in string; pos: in positive; token: inout line; next_start_pos: out positive; ok: out boolean) is
variable ch: character;
variable tmppos: positive;
begin
token := new string'("");
if pos > str'length then
ok := false;
return;
end if;
ch := str(pos);
case ch is
when ' ' | ',' | LF | CR | HT =>
next_start_pos := pos + 1;
token := new string'("");
ok := true;
return;
when '[' | ']' | '{' | '}' | '(' | ')' | ''' | '`' | '^' | '@' =>
next_start_pos := pos + 1;
token := new string'("" & ch);
ok := true;
return;
when '~' =>
if str(pos + 1) = '@' then
next_start_pos := pos + 2;
token := new string'("~@");
else
next_start_pos := pos + 1;
token := new string'("~");
end if;
ok := true;
return;
when ';' =>
tmppos := pos + 1;
while tmppos <= str'length and not is_eol_char(str(tmppos)) loop
tmppos := tmppos + 1;
end loop;
next_start_pos := tmppos;
token := new string'("");
ok := true;
return;
when '"' =>
tmppos := pos + 1;
while tmppos < str'length and str(tmppos) /= '"' loop
if str(tmppos) = '\' then
tmppos := tmppos + 2;
else
tmppos := tmppos + 1;
end if;
end loop;
token := new string(1 to (tmppos - pos + 1));
token(1 to (tmppos - pos + 1)) := str(pos to tmppos);
next_start_pos := tmppos + 1;
ok := true;
return;
when others =>
tmppos := pos;
while tmppos <= str'length and not is_separator_char(str(tmppos)) loop
tmppos := tmppos + 1;
end loop;
token := new string(1 to (tmppos - pos));
token(1 to (tmppos - pos)) := str(pos to tmppos - 1);
next_start_pos := tmppos;
ok := true;
return;
end case;
ok := false;
end procedure next_token;
function tokenize(str: in string) return token_list_ptr is
variable next_pos: positive := 1;
variable ok: boolean := true;
variable tokens: token_list_ptr;
variable t: line;
begin
while ok loop
next_token(str, next_pos, t, next_pos, ok);
if t'length > 0 then
if tokens = null then
tokens := new token_list(0 to 0);
tokens(0) := t;
else
tokens := new token_list'(tokens.all & t);
end if;
end if;
end loop;
return tokens;
end function tokenize;
type reader_class is record
tokens: token_list_ptr;
pos: natural;
end record reader_class;
procedure reader_new(r: inout reader_class; a_tokens: inout token_list_ptr) is
begin
r := (tokens => a_tokens, pos => 0);
end procedure reader_new;
procedure reader_peek(r: inout reader_class; token: out line) is
begin
if r.pos < r.tokens'length then
token := r.tokens(r.pos);
else
token := null;
end if;
end procedure reader_peek;
procedure reader_next(r: inout reader_class; token: out line) is
begin
reader_peek(r, token);
r.pos := r.pos + 1;
end procedure reader_next;
-- Forward declaration
procedure read_form(r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr);
function is_digit(c: in character) return boolean is
begin
case c is
when '0' to '9' => return true;
when others => return false;
end case;
end function is_digit;
function unescape_char(c: in character) return character is
begin
case c is
when 'n' => return LF;
when others => return c;
end case;
end function unescape_char;
procedure unescape_string_token(token: inout line; result: out line) is
variable s: line;
variable src_i, dst_i: integer;
begin
s := new string(1 to token'length);
dst_i := 0;
src_i := 2; -- skip the initial quote
while src_i <= token'length - 1 loop
dst_i := dst_i + 1;
if token(src_i) = '\' then
s(dst_i) := unescape_char(token(src_i + 1));
src_i := src_i + 2;
else
s(dst_i) := token(src_i);
src_i := src_i + 1;
end if;
end loop;
result := new string'(s(1 to dst_i));
deallocate(s);
end procedure unescape_string_token;
procedure read_atom(r: inout reader_class; result: out mal_val_ptr) is
variable token, s: line;
variable num: integer;
variable ch: character;
begin
reader_next(r, token);
if token.all = "nil" then
new_nil(result);
elsif token.all = "true" then
new_true(result);
elsif token.all = "false" then
new_false(result);
else
ch := token(1);
case ch is
when '-' =>
if token'length > 1 and is_digit(token(2)) then
read(token, num);
new_number(num, result);
else
new_symbol(token, result);
end if;
when '0' to '9' =>
read(token, num);
new_number(num, result);
when ':' =>
s := new string(1 to token'length - 1);
s(1 to s'length) := token(2 to token'length);
new_keyword(s, result);
when '"' =>
unescape_string_token(token, s);
new_string(s, result);
when others =>
new_symbol(token, result);
end case;
end if;
end procedure read_atom;
procedure read_sequence(list_type: in mal_type_tag; end_ch: in string; r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr) is
variable token: line;
variable element, sub_err: mal_val_ptr;
variable seq: mal_seq_ptr;
begin
reader_next(r, token); -- Consume the open paren
reader_peek(r, token);
seq := new mal_seq(0 to -1);
while token /= null and token.all /= end_ch loop
read_form(r, element, sub_err);
if sub_err /= null then
err := sub_err;
result := null;
return;
end if;
seq := new mal_seq'(seq.all & element);
reader_peek(r, token);
end loop;
if token = null then
new_string("expected '" & end_ch & "', got EOF", err);
result := null;
return;
end if;
reader_next(r, token); -- Consume the close paren
new_seq_obj(list_type, seq, result);
end procedure read_sequence;
procedure reader_macro(r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr; sym_name: in string) is
variable token, sym_line: line;
variable seq: mal_seq_ptr;
variable rest, rest_err: mal_val_ptr;
begin
reader_next(r, token);
seq := new mal_seq(0 to 1);
sym_line := new string'(sym_name);
new_symbol(sym_line, seq(0));
read_form(r, rest, rest_err);
if rest_err /= null then
err := rest_err;
result := null;
return;
end if;
seq(1) := rest;
new_seq_obj(mal_list, seq, result);
end procedure reader_macro;
procedure with_meta_reader_macro(r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr) is
variable token, sym_line: line;
variable seq: mal_seq_ptr;
variable meta, rest, rest_err: mal_val_ptr;
begin
reader_next(r, token);
seq := new mal_seq(0 to 2);
sym_line := new string'("with-meta");
new_symbol(sym_line, seq(0));
read_form(r, meta, rest_err);
if rest_err /= null then
err := rest_err;
result := null;
return;
end if;
read_form(r, rest, rest_err);
if rest_err /= null then
err := rest_err;
result := null;
return;
end if;
seq(1) := rest;
seq(2) := meta;
new_seq_obj(mal_list, seq, result);
end procedure with_meta_reader_macro;
procedure read_form(r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr) is
variable token: line;
variable ch: character;
begin
reader_peek(r, token);
ch := token(1);
case ch is
when ''' => reader_macro(r, result, err, "quote");
when '`' => reader_macro(r, result, err, "quasiquote");
when '~' =>
if token'length = 1 then
reader_macro(r, result, err, "unquote");
else
if token(2) = '@' then
reader_macro(r, result, err, "splice-unquote");
else
new_string("Unknown token", err);
end if;
end if;
when '^' => with_meta_reader_macro(r, result, err);
when '@' => reader_macro(r, result, err, "deref");
when '(' => read_sequence(mal_list, ")", r, result, err);
when ')' => new_string("unexcepted ')'", err);
when '[' => read_sequence(mal_vector, "]", r, result, err);
when ']' => new_string("unexcepted ']'", err);
when '{' => read_sequence(mal_hashmap, "}", r, result, err);
when '}' => new_string("unexcepted '}'", err);
when others => read_atom(r, result);
end case;
end procedure read_form;
procedure read_str(s: in string; result: out mal_val_ptr; err: out mal_val_ptr) is
variable tokens: token_list_ptr;
variable r: reader_class;
begin
tokens := tokenize(s);
if tokens = null or tokens'length = 0 then
result := null;
err := null;
return;
end if;
reader_new(r, tokens);
read_form(r, result, err);
end procedure read_str;
end package body reader;
| mpl-2.0 |
cite-sa/xwcps | xwcps-parser-ui/libs/ace/ace_all/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| agpl-3.0 |
foresterre/mal | vhdl/reader.vhdl | 10 | 10133 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package reader is
procedure read_str(s: in string; result: out mal_val_ptr; err: out mal_val_ptr);
end package reader;
package body reader is
type token_list is array(natural range <>) of line;
type token_list_ptr is access token_list;
function is_eol_char(c: in character) return boolean is
begin
case c is
when LF | CR => return true;
when others => return false;
end case;
end function is_eol_char;
function is_separator_char(c: in character) return boolean is
begin
case c is
when LF | CR | ' ' | '[' | ']' | '{' | '}' | '(' | ')' |
''' | '"' | '`' | ',' | ';' => return true;
when others => return false;
end case;
end function is_separator_char;
procedure next_token(str: in string; pos: in positive; token: inout line; next_start_pos: out positive; ok: out boolean) is
variable ch: character;
variable tmppos: positive;
begin
token := new string'("");
if pos > str'length then
ok := false;
return;
end if;
ch := str(pos);
case ch is
when ' ' | ',' | LF | CR | HT =>
next_start_pos := pos + 1;
token := new string'("");
ok := true;
return;
when '[' | ']' | '{' | '}' | '(' | ')' | ''' | '`' | '^' | '@' =>
next_start_pos := pos + 1;
token := new string'("" & ch);
ok := true;
return;
when '~' =>
if str(pos + 1) = '@' then
next_start_pos := pos + 2;
token := new string'("~@");
else
next_start_pos := pos + 1;
token := new string'("~");
end if;
ok := true;
return;
when ';' =>
tmppos := pos + 1;
while tmppos <= str'length and not is_eol_char(str(tmppos)) loop
tmppos := tmppos + 1;
end loop;
next_start_pos := tmppos;
token := new string'("");
ok := true;
return;
when '"' =>
tmppos := pos + 1;
while tmppos < str'length and str(tmppos) /= '"' loop
if str(tmppos) = '\' then
tmppos := tmppos + 2;
else
tmppos := tmppos + 1;
end if;
end loop;
token := new string(1 to (tmppos - pos + 1));
token(1 to (tmppos - pos + 1)) := str(pos to tmppos);
next_start_pos := tmppos + 1;
ok := true;
return;
when others =>
tmppos := pos;
while tmppos <= str'length and not is_separator_char(str(tmppos)) loop
tmppos := tmppos + 1;
end loop;
token := new string(1 to (tmppos - pos));
token(1 to (tmppos - pos)) := str(pos to tmppos - 1);
next_start_pos := tmppos;
ok := true;
return;
end case;
ok := false;
end procedure next_token;
function tokenize(str: in string) return token_list_ptr is
variable next_pos: positive := 1;
variable ok: boolean := true;
variable tokens: token_list_ptr;
variable t: line;
begin
while ok loop
next_token(str, next_pos, t, next_pos, ok);
if t'length > 0 then
if tokens = null then
tokens := new token_list(0 to 0);
tokens(0) := t;
else
tokens := new token_list'(tokens.all & t);
end if;
end if;
end loop;
return tokens;
end function tokenize;
type reader_class is record
tokens: token_list_ptr;
pos: natural;
end record reader_class;
procedure reader_new(r: inout reader_class; a_tokens: inout token_list_ptr) is
begin
r := (tokens => a_tokens, pos => 0);
end procedure reader_new;
procedure reader_peek(r: inout reader_class; token: out line) is
begin
if r.pos < r.tokens'length then
token := r.tokens(r.pos);
else
token := null;
end if;
end procedure reader_peek;
procedure reader_next(r: inout reader_class; token: out line) is
begin
reader_peek(r, token);
r.pos := r.pos + 1;
end procedure reader_next;
-- Forward declaration
procedure read_form(r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr);
function is_digit(c: in character) return boolean is
begin
case c is
when '0' to '9' => return true;
when others => return false;
end case;
end function is_digit;
function unescape_char(c: in character) return character is
begin
case c is
when 'n' => return LF;
when others => return c;
end case;
end function unescape_char;
procedure unescape_string_token(token: inout line; result: out line) is
variable s: line;
variable src_i, dst_i: integer;
begin
s := new string(1 to token'length);
dst_i := 0;
src_i := 2; -- skip the initial quote
while src_i <= token'length - 1 loop
dst_i := dst_i + 1;
if token(src_i) = '\' then
s(dst_i) := unescape_char(token(src_i + 1));
src_i := src_i + 2;
else
s(dst_i) := token(src_i);
src_i := src_i + 1;
end if;
end loop;
result := new string'(s(1 to dst_i));
deallocate(s);
end procedure unescape_string_token;
procedure read_atom(r: inout reader_class; result: out mal_val_ptr) is
variable token, s: line;
variable num: integer;
variable ch: character;
begin
reader_next(r, token);
if token.all = "nil" then
new_nil(result);
elsif token.all = "true" then
new_true(result);
elsif token.all = "false" then
new_false(result);
else
ch := token(1);
case ch is
when '-' =>
if token'length > 1 and is_digit(token(2)) then
read(token, num);
new_number(num, result);
else
new_symbol(token, result);
end if;
when '0' to '9' =>
read(token, num);
new_number(num, result);
when ':' =>
s := new string(1 to token'length - 1);
s(1 to s'length) := token(2 to token'length);
new_keyword(s, result);
when '"' =>
unescape_string_token(token, s);
new_string(s, result);
when others =>
new_symbol(token, result);
end case;
end if;
end procedure read_atom;
procedure read_sequence(list_type: in mal_type_tag; end_ch: in string; r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr) is
variable token: line;
variable element, sub_err: mal_val_ptr;
variable seq: mal_seq_ptr;
begin
reader_next(r, token); -- Consume the open paren
reader_peek(r, token);
seq := new mal_seq(0 to -1);
while token /= null and token.all /= end_ch loop
read_form(r, element, sub_err);
if sub_err /= null then
err := sub_err;
result := null;
return;
end if;
seq := new mal_seq'(seq.all & element);
reader_peek(r, token);
end loop;
if token = null then
new_string("expected '" & end_ch & "', got EOF", err);
result := null;
return;
end if;
reader_next(r, token); -- Consume the close paren
new_seq_obj(list_type, seq, result);
end procedure read_sequence;
procedure reader_macro(r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr; sym_name: in string) is
variable token, sym_line: line;
variable seq: mal_seq_ptr;
variable rest, rest_err: mal_val_ptr;
begin
reader_next(r, token);
seq := new mal_seq(0 to 1);
sym_line := new string'(sym_name);
new_symbol(sym_line, seq(0));
read_form(r, rest, rest_err);
if rest_err /= null then
err := rest_err;
result := null;
return;
end if;
seq(1) := rest;
new_seq_obj(mal_list, seq, result);
end procedure reader_macro;
procedure with_meta_reader_macro(r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr) is
variable token, sym_line: line;
variable seq: mal_seq_ptr;
variable meta, rest, rest_err: mal_val_ptr;
begin
reader_next(r, token);
seq := new mal_seq(0 to 2);
sym_line := new string'("with-meta");
new_symbol(sym_line, seq(0));
read_form(r, meta, rest_err);
if rest_err /= null then
err := rest_err;
result := null;
return;
end if;
read_form(r, rest, rest_err);
if rest_err /= null then
err := rest_err;
result := null;
return;
end if;
seq(1) := rest;
seq(2) := meta;
new_seq_obj(mal_list, seq, result);
end procedure with_meta_reader_macro;
procedure read_form(r: inout reader_class; result: out mal_val_ptr; err: out mal_val_ptr) is
variable token: line;
variable ch: character;
begin
reader_peek(r, token);
ch := token(1);
case ch is
when ''' => reader_macro(r, result, err, "quote");
when '`' => reader_macro(r, result, err, "quasiquote");
when '~' =>
if token'length = 1 then
reader_macro(r, result, err, "unquote");
else
if token(2) = '@' then
reader_macro(r, result, err, "splice-unquote");
else
new_string("Unknown token", err);
end if;
end if;
when '^' => with_meta_reader_macro(r, result, err);
when '@' => reader_macro(r, result, err, "deref");
when '(' => read_sequence(mal_list, ")", r, result, err);
when ')' => new_string("unexcepted ')'", err);
when '[' => read_sequence(mal_vector, "]", r, result, err);
when ']' => new_string("unexcepted ']'", err);
when '{' => read_sequence(mal_hashmap, "}", r, result, err);
when '}' => new_string("unexcepted '}'", err);
when others => read_atom(r, result);
end case;
end procedure read_form;
procedure read_str(s: in string; result: out mal_val_ptr; err: out mal_val_ptr) is
variable tokens: token_list_ptr;
variable r: reader_class;
begin
tokens := tokenize(s);
if tokens = null or tokens'length = 0 then
result := null;
err := null;
return;
end if;
reader_new(r, tokens);
read_form(r, result, err);
end procedure read_str;
end package body reader;
| mpl-2.0 |
sdenel/An-N-bits-pipelined-addsub-using-VHDL | src/fullAdderWithRegisters.vhd | 1 | 2177 | library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity fullAdderWithRegisters is
-- fullAdderWithRegisters
-- Prend a, b, en entrée
-- Prend c NREGSBEFORE coups d'horloge après
-- Rend s au bout de NREGSBEFORE+NREGSAFTER+1 coups d'horloge
-- NREGSBEFORE+NREGSAFTER+1
generic (
NREGSBEFORE: natural := 0;
NREGSAFTER : natural := 0;
ISCREG : natural := 0;
ISRESET : std_logic := '0'
);
port (
clk, rst : in std_logic;
a, b, c : in std_logic;
r, s : out std_logic
);
end entity fullAdderWithRegisters;
architecture rtl of fullAdderWithRegisters is
--signal Ar, Br, S, C, Bc: bit_vector(NBITS-1 downto 0);
signal Ar_B, Br_B: std_logic_vector(NREGSBEFORE downto 0);
signal Cr : std_logic_vector(ISCREG downto 0);
signal Sr_A : std_logic_vector(NREGSAFTER downto 0);
signal st : std_logic;
component fullAdder
port(
a, b, c : in std_logic;
r, s : out std_logic
);
end component fullAdder;
begin
G0: if ISCREG = 1 generate
process (clk)
begin
if clk'event and clk = '1' then
Cr(0) <= Cr(1);
end if;
end process;
end generate G0;
G1: if NREGSBEFORE > 0 generate
process (clk, rst)
begin
if ISRESET= '1' and rst = '1' then
Ar_B(NREGSBEFORE-1 downto 0) <= (others => '0');
Br_B(NREGSBEFORE-1 downto 0) <= (others => '0');
elsif clk'event and clk = '1' then
Ar_B(NREGSBEFORE-1 downto 0) <= Ar_B(NREGSBEFORE downto 1);
Br_B(NREGSBEFORE-1 downto 0) <= Br_B(NREGSBEFORE downto 1);
end if;
end process;
end generate G1;
G2: if NREGSAFTER > 0 generate
process (clk, rst)
begin
if ISRESET= '1' and rst = '1' then
Sr_A(NREGSAFTER-1 downto 0) <= (others => '0');
elsif clk'event and clk = '1' then
for i in 0 to NREGSAFTER-1 loop
Sr_A(NREGSAFTER-1 downto 0) <= Sr_A(NREGSAFTER downto 1);
end loop;
end if;
end process;
Sr_A(NREGSAFTER) <= st;
s <= Sr_A(0);
end generate G2;
G3: if NREGSAFTER = 0 generate
s <= st;
end generate G3;
Cr(ISCREG) <= c;
Ar_B(NREGSBEFORE) <= a;
Br_B(NREGSBEFORE) <= b;
inst: fullAdder port map(a=>Ar_B(0), b=>Br_B(0), c=>Cr(0), r=>r, s=>st);
end rtl;
| mit |
Zunth5/LED-CLOCK | LEDgrid/DATA_CONSTRUCT.vhd | 1 | 3617 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DATA_CONSTRUCT is
port ( CLKin : in std_logic; --system clock
UPDATEin : in std_logic; --uart update signal
UARTin : in std_logic_vector(7 downto 0); --uart data in
COLOR_out : out std_logic_vector(14 downto 0); --color data
PIXSEL_out : out std_logic_vector(4 downto 0); --super pixel select
PIXRAM_out : out std_logic_vector(15 downto 0); --ram location select
UARTFOR_out : out std_logic_vector(7 downto 0); --uart data forward
MODE_out : out std_logic_vector(1 downto 0); --mode output
RAMCON_out : out std_logic; --controls write to sram
UPDAFOR_out : out std_logic; --uart update forward
UARTUPD_out : out std_logic; --uart send control
UARTDAT_out : out std_logic_vector(7 downto 0) --uart send data
);
end DATA_CONSTRUCT;
architecture Behavioral of DATA_CONSTRUCT is
---------------------------------------------------------------------------
signal UARTDAT : std_logic_vector(7 downto 0);
signal COLOR1 : std_logic_vector(7 downto 0);
signal PIXSEL : std_logic_vector(4 downto 0);
signal ENABLE : std_logic:='0';
signal ENABLE2 : std_logic:='1';
signal CLK2 : std_logic:='0';
signal COUNT : integer:= 0;
signal COUNT2 : integer:= 0;
signal CLKCOUNT : integer:= 0;
signal STATE : integer:= 0;
signal MODE : std_logic_vector(1 downto 0):= "11";
signal REACH : integer:= 0;
signal COLOR : std_logic_vector(14 downto 0) := (others => '0');
signal PIXRAM : std_logic_vector(7 downto 0) := (others => '0');
----------------------------------------------------------------------------
begin
----------------------------------------------------------
UARTMANIP : process (CLKin)
begin
--COLOR_out <= COLOR;
--PIXRAM_out <= PIXRAM;
--MODE_out <= MODE;
--UARTDAT_out <= UARTDAT;
--PIXSEL_out <= PIXSEL;
if rising_edge(CLKin) then
if STATE = 3 or STATE = 134 or STATE = 137 then
if COUNT < 899 and ENABLE = '1' then
COUNT <= COUNT + 1;
UARTUPD_out <= '1';
else
UARTUPD_out <= '0';
COUNT <= 0;
ENABLE <= '0';
end if;
else
ENABLE <= '1';
UARTUPD_out <= '0';
end if;
if STATE = 0 then
UPDAFOR_out <= '1';
else
UPDAFOR_out <= '0';
end if;
if STATE >= 69 and STATE <= 132 then
RAMCON_out <= '1';
else
RAMCON_out <= '0';
end if;
end if;
if rising_edge(UPDATEin) then
case STATE is
when 0 =>
if UARTin = x"61" then
STATE <= 3;
MODE_out<="01";
UARTDAT_out <= x"41";
elsif UARTin = x"62" then
STATE <= 134;
MODE_out<="10";
UARTDAT_out <= x"42";
elsif UARTin = x"63" then
STATE <= 137;
MODE_out<="11";
UARTDAT_out <= x"43";
else
MODE_out<="00";
end if;
when 3 =>
PIXRAM <= UARTin;
STATE <= STATE + 1;
when 4 =>
PIXRAM_out <= UARTin & PIXRAM;
STATE <= STATE + 1;
when 5 to 68 =>
COLOR1 <= UARTin;
STATE <= STATE + 64;
when 69 to 131 =>
COLOR_out <= COLOR1(6 downto 0) & UARTin;
STATE <= STATE - 63;
when 132 =>
COLOR_out <= COLOR1(6 downto 0) & UARTin;
STATE <= 0;
when 134 =>
PIXRAM <= UARTin;
STATE <= STATE + 1;
when 135 =>
PIXRAM_out <= UARTin & PIXRAM;
STATE <= STATE + 1;
when 136 =>
PIXSEL_out <= UARTin(4 downto 0);
STATE <= 0;
when 137 to 171 =>
UARTFOR_out <= UARTin;
STATE <= STATE + 1;
when 172 =>
UARTFOR_out <= UARTin;
STATE <= 0;
when others =>
STATE <= 0;
end case;
end if;
end process UARTMANIP;
----------------------------------------------------------
end Behavioral;
| mit |
fkmclane/AutoPidact | vhdl/ClockGenerator.vhd | 1 | 596 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ClockGenerator is
generic(
count : natural := 50000000
);
port(
clk : in std_logic;
rst : in std_logic;
q : out std_logic
);
end entity ClockGenerator;
architecture RTL of ClockGenerator is
begin
process(clk, rst)
variable value : integer range 0 to count := 0;
begin
if (rst = '0') then
value := 0;
elsif (clk'event) and (clk = '1') then
value := value + 1;
end if;
if (value = count) then
value := 0;
q <= '1';
else
q <= '0';
end if;
end process;
end architecture RTL;
| mit |
Zunth5/LED-CLOCK | LEDgrid/ipcore_dir/CHAR_ROM/simulation/bmg_stim_gen.vhd | 1 | 12571 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (6 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0):= hex_to_std_logic_vector("0",7);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(6 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"CHAR_ROM.mif",
DEFAULT_DATA,
7,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit |
FearlessJojo/COPproject | project/main.vhd | 1 | 15307 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:24:26 11/18/2016
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port ( --FLASH_A : out STD_LOGIC_VECTOR (22 downto 0);
--FLASH_D : inout STD_LOGIC_VECTOR (15 downto 0);
--FPGA_KEY : in STD_LOGIC_VECTOR (3 downto 0);
CLK2 : in STD_LOGIC;
--CLK1 : in STD_LOGIC;
--LCD_CS1 : out STD_LOGIC;
--LCD_CS2 : out STD_LOGIC;
--LCD_DB : inout STD_LOGIC_VECTOR (7 downto 0);
--LCD_E : out STD_LOGIC;
--LCD_RESET : out STD_LOGIC;
--LCD_RS : out STD_LOGIC;
--LCD_RW : out STD_LOGIC;
--VGA_R : out STD_LOGIC_VECTOR (2 downto 0);
--VGA_G : out STD_LOGIC_VECTOR (2 downto 0);
--VGA_B : out STD_LOGIC_VECTOR (2 downto 0);
--VGA_HHYNC : out STD_LOGIC;
--VGA_VHYNC : out STD_LOGIC;
--PS2KB_CLOCK : out STD_LOGIC;
--PS2KB_DATA : in STD_LOGIC;
RAM1DATA : inout STD_LOGIC_VECTOR (15 downto 0);
--SW_DIP : in STD_LOGIC_VECTOR (15 downto 0);
--FLASH_BYTE : out STD_LOGIC;
--FLASH_CE : out STD_LOGIC;
--FLASH_CE1 : out STD_LOGIC;
--FLASH_CE2 : out STD_LOGIC;
--FLASH_OE : out STD_LOGIC;
--FLASH_RP : out STD_LOGIC;
--FLASH_STS : out STD_LOGIC;
--FLASH_VPEN : out STD_LOGIC;
--FLASH_WE : out STD_LOGIC;
--U_RXD : out STD_LOGIC;
--U_TXD : out STD_LOGIC;
RAM2DATA : inout STD_LOGIC_VECTOR (15 downto 0);
RAM1EN : out STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1WE : out STD_LOGIC;
L : out STD_LOGIC_VECTOR (15 downto 0);
RAM2EN : out STD_LOGIC;
RAM2OE : out STD_LOGIC;
RAM2WE : out STD_LOGIC;
RAM1ADDR : out STD_LOGIC_VECTOR (17 downto 0);
RAM2ADDR : out STD_LOGIC_VECTOR (17 downto 0);
--DYP0 : out STD_LOGIC_VECTOR (6 downto 0);
--DYP1 : out STD_LOGIC_VECTOR (6 downto 0);
--CLK_FROM_KEY : in STD_LOGIC;
RESET : in STD_LOGIC;
rdn: out STD_LOGIC;
wrn: out STD_LOGIC;
data_ready: in STD_LOGIC;
tbre: in STD_LOGIC;
tsre: in STD_LOGIC
);
end main;
architecture Behavioral of main is
component ALU is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ALUIN1 : in STD_LOGIC_VECTOR (15 downto 0);
ALUIN2 : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component ALUMUX1 is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
ALUctrl1 : in STD_LOGIC_VECTOR (1 downto 0);
ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component ALUMUX2 is
Port ( B : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
ALUctrl2 : in STD_LOGIC_VECTOR (1 downto 0);
ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component control is
Port ( Inst : in STD_LOGIC_VECTOR (15 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
Imm : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC;
NPC : in STD_LOGIC_VECTOR (15 downto 0);
OP : out STD_LOGIC_VECTOR (3 downto 0);
PCctrl : out STD_LOGIC_VECTOR (1 downto 0);
RFctrl : out STD_LOGIC_VECTOR (2 downto 0);
Immctrl : out STD_LOGIC_VECTOR (3 downto 0);
Rs : out STD_LOGIC_VECTOR (3 downto 0);
Rt : out STD_LOGIC_VECTOR (3 downto 0);
Rd : out STD_LOGIC_VECTOR (3 downto 0);
AccMEM : out STD_LOGIC;
memWE : out STD_LOGIC;
regWE : out STD_LOGIC;
DataIN : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0);
newT : out STD_LOGIC;
TE : out STD_LOGIC);
end component;
component EXE_MEM is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
EXE_ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
EXE_Rd : in STD_LOGIC_VECTOR (3 downto 0);
EXE_AccMEM : in STD_LOGIC;
EXE_memWE : in STD_LOGIC;
EXE_regWE : in STD_LOGIC;
EXE_DataIN : in STD_LOGIC_VECTOR (15 downto 0);
MEM_ALUOUT : out STD_LOGIC_VECTOR (15 downto 0);
MEM_Rd : out STD_LOGIC_VECTOR (3 downto 0);
MEM_AccMEM : out STD_LOGIC;
MEM_memWE : out STD_LOGIC;
MEM_regWE : out STD_LOGIC;
MEM_DataIN : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC
);
end component;
component Forwarding is
Port ( ID_Rs : in STD_LOGIC_VECTOR (3 downto 0);
ID_Rt : in STD_LOGIC_VECTOR (3 downto 0);
ID_EXE_Rd : in STD_LOGIC_VECTOR (3 downto 0);
ID_EXE_regWE : in STD_LOGIC;
ID_EXE_AccMEM : in STD_LOGIC;
EXE_MEM_Rd : in STD_LOGIC_VECTOR (3 downto 0);
EXE_MEM_regWE : in STD_LOGIC;
PCReg_enable : out STD_LOGIC;
IF_ID_enable : out STD_LOGIC;
ID_EXE_enable : out STD_LOGIC;
ID_EXE_bubble : out STD_LOGIC;
ALUctrl1 : out STD_LOGIC_VECTOR (1 downto 0);
ALUctrl2 : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
component ID_EXE is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
bubble : in STD_LOGIC;
ID_ALUIN1 : in STD_LOGIC_VECTOR (15 downto 0);
ID_ALUIN2 : in STD_LOGIC_VECTOR (15 downto 0);
ID_OP : in STD_LOGIC_VECTOR (3 downto 0);
ID_Rd : in STD_LOGIC_VECTOR (3 downto 0);
ID_AccMEM : in STD_LOGIC;
ID_memWE : in STD_LOGIC;
ID_regWE : in STD_LOGIC;
ID_DataIN : in STD_LOGIC_VECTOR (15 downto 0);
EXE_ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0);
EXE_ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0);
EXE_OP : out STD_LOGIC_VECTOR (3 downto 0);
EXE_Rd : out STD_LOGIC_VECTOR (3 downto 0);
EXE_AccMEM : out STD_LOGIC;
EXE_memWE : out STD_LOGIC;
EXE_regWE : out STD_LOGIC;
EXE_DataIN : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2 : in STD_LOGIC
);
end component;
component IF_ID is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
IF_Inst : in STD_LOGIC_VECTOR (15 downto 0);
IF_NPC : in STD_LOGIC_VECTOR(15 DOWNTO 0);
ID_Inst : out STD_LOGIC_VECTOR (15 downto 0);
ID_NPC : out STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_RAM2 : in STD_LOGIC
);
end component;
component IM is
Port ( PC : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
--stateclk : in STD_LOGIC;
rst : in STD_LOGIC;
Ram2OE : out STD_LOGIC;
Ram2WE : out STD_LOGIC;
Ram2EN : out STD_LOGIC;
Ram2Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram2Data : inout STD_LOGIC_VECTOR (15 downto 0);
Inst : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC;
MEM_ACCMEM: in STD_LOGIC;
MEM_ALUOUT:in STD_LOGIC_VECTOR (15 downto 0);
MEM_DATAIN: in STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component Imm is
Port ( Immctrl : in STD_LOGIC_VECTOR (3 downto 0);
Inst : in STD_LOGIC_VECTOR (10 downto 0);
Imm : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component MEM_WB is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
MEM_MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEM_Rd : in STD_LOGIC_VECTOR (3 downto 0);
MEM_regWE : in STD_LOGIC;
WB_MEMOUT : out STD_LOGIC_VECTOR (15 downto 0);
WB_Rd : out STD_LOGIC_VECTOR (3 downto 0);
WB_regWE : out STD_LOGIC
);
end component;
component MEMMUX is
Port ( ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
DataOUT : in STD_LOGIC_VECTOR (15 downto 0);
ACCMEM : in STD_LOGIC;
MEMOUT : out STD_LOGIC_VECTOR (15 downto 0);
IMOUT: in STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2:in STD_LOGIC);
end component;
component PCMUX is
Port ( NPC : in STD_LOGIC_VECTOR (15 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
adderOUT : in STD_LOGIC_VECTOR (15 downto 0);
PCctrl : in STD_LOGIC_VECTOR (1 downto 0);
PCIN : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component PCReg is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
NPC : in STD_LOGIC_VECTOR (15 downto 0);
PC : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC;
L:out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component RAM_UART is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ACCMEM : in STD_LOGIC;
MEM_WE : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (15 downto 0);
data : in STD_LOGIC_VECTOR (15 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0);
Ram1Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram1Data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1OE : out STD_LOGIC;
Ram1WE : out STD_LOGIC;
Ram1EN : out STD_LOGIC;
wrn : out STD_LOGIC;
rdn : out STD_LOGIC;
data_ready : in STD_LOGIC;
tbre : in STD_LOGIC;
tsre : in STD_LOGIC;
MEM_RAM2: in STD_LOGIC);
end component;
component RF is
Port ( regWE : in STD_LOGIC;
RFctrl : in STD_LOGIC_VECTOR (2 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
Rd : in STD_LOGIC_VECTOR (3 downto 0);
Inst : in STD_LOGIC_VECTOR (5 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (15 downto 0);
B : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component T is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
T_in : in STD_LOGIC;
T_reg : out STD_LOGIC);
end component;
component Adder is
Port (
NPC : in STD_LOGIC_VECTOR(15 downto 0);
Imm : in STD_LOGIC_VECTOR(15 downto 0);
RPC : out STD_LOGIC_VECTOR(15 downto 0));
end component;
component PC_Adder is
Port (
PC : in STD_LOGIC_VECTOR(15 downto 0);
NPC : out STD_LOGIC_VECTOR(15 downto 0));
end component;
signal MEM_RAM2,ID_T,ID_AccMEM,ID_memWE,ID_regWE,ID_newT,ID_TE,EXE_AccMEM,EXE_memWE,EXE_regWE,MEM_AccMEM,MEM_memWE,MEM_regWE,PCReg_enable,IF_ID_enable,ID_EXE_enable,ID_EXE_bubble,WB_regWE : STD_LOGIC:='0';
signal ALUctrl1,ALUctrl2,PCctrl :STD_LOGIC_VECTOR(1 DOWNTO 0);
signal RFctrl :STD_LOGIC_VECTOR(2 DOWNTO 0);
signal ID_OP,EXE_OP,Immctrl,ID_Rs,ID_Rt,ID_Rd,EXE_Rd,MEM_Rd,WB_Rd :STD_LOGIC_VECTOR(3 DOWNTO 0);
signal EXE_ALUOUT,EXE_ALUIN1,EXE_ALUIN2,ID_A0,ID_B0,MEM_MEMOUT,ID_A,ID_B,ID_Inst,ID_DataIN,ID_ALUIN1,ID_ALUIN2,EXE_DataIN,MEM_ALUOUT,MEM_DataIN,IF_Inst,IF_NPC,ID_NPC,ID_Imm,WB_MEMOUT,DataOUT,adderOUT,PCIN,PC :STD_LOGIC_VECTOR(15 downto 0):="1111111111111111";
signal state0, state1, CLK0, CLK1 : STD_LOGIC := '0';
begin
ALU_module:ALU PORT MAP(EXE_OP,EXE_ALUIN1,EXE_ALUIN2,EXE_ALUOUT);
ALUMUX1_module:ALUMUX1 PORT MAP(ID_A0,EXE_ALUOUT,MEM_MEMOUT,ALUctrl1,ID_A);
ALUMUX2_module:ALUMUX2 PORT MAP(ID_B0,EXE_ALUOUT,MEM_MEMOUT,ALUctrl2,ID_B);
control_module:control PORT MAP(ID_Inst,ID_A,ID_B,ID_Imm,ID_T,ID_NPC,ID_OP,PCctrl,RFctrl,Immctrl,ID_Rs,ID_Rt,ID_Rd,ID_AccMEM,ID_memWE,ID_regWE,ID_DataIN,ID_ALUIN1,ID_ALUIN2,ID_newT,ID_TE);
EXE_MEM_module:EXE_MEM PORT MAP(CLK0,RESET,'1',EXE_ALUOUT,EXE_Rd,EXE_AccMEM,EXE_memWE,EXE_regWE,EXE_DataIN,MEM_ALUOUT,MEM_Rd,MEM_AccMEM,MEM_memWE,MEM_regWE,MEM_DataIN,MEM_RAM2);
Forwarding_module:Forwarding PORT MAP(ID_Rs ,ID_Rt ,EXE_Rd ,EXE_regWE ,EXE_AccMEM ,MEM_Rd ,MEM_regWE ,PCReg_enable ,IF_ID_enable ,ID_EXE_enable ,ID_EXE_bubble ,ALUctrl1 ,ALUctrl2);
ID_EXE_module:ID_EXE PORT MAP(CLK0 ,RESET ,ID_EXE_enable ,ID_EXE_bubble ,ID_ALUIN1 ,ID_ALUIN2 ,ID_OP ,ID_Rd ,ID_AccMEM ,ID_memWE ,ID_regWE ,ID_DataIN ,EXE_ALUIN1 ,EXE_ALUIN2 ,EXE_OP ,EXE_Rd ,EXE_AccMEM ,EXE_memWE ,EXE_regWE ,EXE_DataIN,MEM_RAM2);
IF_ID_module:IF_ID PORT MAP(CLK0 ,RESET ,IF_ID_enable ,IF_Inst ,IF_NPC ,ID_Inst ,ID_NPC,MEM_RAM2);
IM_module:IM PORT MAP(PC ,CLK1 , RESET ,RAM2OE ,RAM2WE ,RAM2EN ,RAM2ADDR ,RAM2DATA ,IF_Inst,MEM_RAM2,MEM_AccMEM,MEM_ALUOUT,MEM_DataIN);
Imm_module:Imm PORT MAP(Immctrl,ID_Inst(10 downto 0),ID_Imm);
MEM_WB_module:MEM_WB PORT MAP(CLK0 ,RESET ,'1' ,MEM_MEMOUT ,MEM_Rd ,MEM_regWE ,WB_MEMOUT ,WB_Rd ,WB_regWE);
MEMMUX_module:MEMMUX PORT MAP(MEM_ALUOUT ,DataOUT ,MEM_AccMEM ,MEM_MEMOUT,IF_Inst,MEM_RAM2);
PCMUX_module:PCMUX PORT MAP(IF_NPC ,ID_A ,adderOUT ,PCctrl ,PCIN);
PCReg_module:PCReg PORT MAP(CLK0 ,RESET ,PCReg_enable ,PCIN ,PC,MEM_RAM2,L);
RAM_UART_module:RAM_UART PORT MAP(CLK1 ,RESET,MEM_AccMEM ,MEM_memWE ,MEM_ALUOUT ,MEM_DataIN ,DataOUT,RAM1ADDR ,RAM1DATA ,RAM1OE ,RAM1WE ,RAM1EN ,wrn ,rdn,data_ready,tbre,tsre,MEM_RAM2);
RF_module:RF PORT MAP(WB_regWE ,RFctrl ,WB_MEMOUT ,WB_Rd ,ID_Inst(10 downto 5) ,CLK0 ,RESET ,ID_A0 ,ID_B0);
T_module:T PORT MAP(CLK0,RESET, ID_TE, ID_newT,ID_T);
Adder_module:Adder PORT MAP(ID_NPC, ID_Imm,adderOUT);
PC_Adder_module:PC_Adder PORT MAP(PC,IF_NPC);
process(MEM_ALUOUT,MEM_ACCMEM,MEM_MEMWE)
begin
if (MEM_ALUOUT(15) = '0')and(MEM_ALUOUT(14) = '1')and((MEM_ACCMEM = '1')or(MEM_MEMWE = '1')) then
MEM_RAM2 <= '1';
else
MEM_RAM2 <= '0';
end if;
end process;
process(CLK1)
begin
if (CLK1'event and CLK1 = '1') then
if (state0 = '0') then
CLK0 <= '1';
else
CLK0 <= '0';
end if;
state0 <= not state0;
end if;
end process;
--process(CLK2)
--begin
-- if (CLK2'event and CLK2 = '1') then
-- if (state1 = '0') then
-- CLK1 <= '1';
-- else
-- CLK1 <= '0';
-- end if;
-- state1 <= not state1;
-- end if;
--end process;
CLK1 <= CLK2;
end Behavioral;
| mit |
corywalker/vhdl_fft | cap_controller.vhd | 3 | 4363 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cap_controller is
generic (
N : positive := 16;
ADDRWIDTH : positive := 10;
SIZE : positive := 64;
SIZELOG : positive := 6;
INT_EXT_SEL: std_logic;
SPI_2X_CLK_DIV: positive;
DA_RESET_DELAY: positive
);
port(
CLK1: in std_logic;
start: in std_logic;
busy: out std_logic := '0';
wea : out std_logic_vector(0 DOWNTO 0);
addr : out std_logic_vector(ADDRWIDTH-1 DOWNTO 0);
dout : out std_logic_vector(N-1 DOWNTO 0);
adc_conv: out std_logic;
adc_sck: out std_logic;
adc_miso: in std_logic;
rst: in std_logic
);
end cap_controller;
architecture Behavioral of cap_controller is
signal slower_spi_clock: std_logic := '0';
signal gated_spi_clock: std_logic := '0';
signal determ_spi_sck: std_logic;
signal determ_conv: std_logic;
signal determ_spi_miso: std_logic;
signal spi_sck: std_logic;
signal conv: std_logic;
signal thebusy: std_logic;
signal spi_miso: std_logic;
signal sm_data_buf: std_logic_vector (N-1 downto 0);
signal sm_state_dbg: std_logic_vector (3 downto 0);
signal sm_valid: std_logic;
signal theaddress : integer range SIZE-1 downto 0 := 0;
signal addr_vect : std_logic_vector(ADDRWIDTH-1 DOWNTO 0);
begin
da1: entity work.determ_adc
generic map (
N => N,
DA_RESET_DELAY => DA_RESET_DELAY
)
port map (
CLK1 => CLK1,
spi_sck_i => determ_spi_sck,
conv_i => determ_conv,
spi_miso_o => determ_spi_miso
);
smux1: entity work.spi_mux
port map (
sck_a_o => determ_spi_sck,
sck_b_o => adc_sck,
sck_i => spi_sck,
conv_a_o => determ_conv,
conv_b_o => adc_conv,
conv_i => conv,
miso_a_i => determ_spi_miso,
miso_b_i => adc_miso,
miso_o => spi_miso,
-- '0' for determ_adc, '1' for external.
sel_i => INT_EXT_SEL
);
sm1: entity work.spi_master
generic map (
N => N,
SPI_2X_CLK_DIV => SPI_2X_CLK_DIV
)
port map (
sclk_i => gated_spi_clock,
pclk_i => gated_spi_clock,
rst_i => rst,
wren_i => '1',
do_o => sm_data_buf,
do_valid_o => sm_valid,
spi_sck_o => spi_sck,
spi_miso_i => spi_miso,
state_dbg_o => sm_state_dbg
);
busy <= thebusy;
-- Only write if the SPI master out is valid and we are currently capturing
wea(0) <= sm_valid and thebusy;
conv <= '0' when sm_state_dbg = "0001" else '1';
addr_vect <= std_logic_vector(to_unsigned(theaddress, addr'length));
-- gen: for i in 0 to SIZELOG-1 generate
-- addr(i) <= addr_vect(SIZELOG-i-1);
-- end generate;
addr(SIZELOG-1 downto 0) <= addr_vect(SIZELOG-1 downto 0);
addr(ADDRWIDTH-1 downto SIZELOG) <= (others=>'0');
dout <= "0" & sm_data_buf(14 downto 8) & "00000000";
process(CLK1)
variable address : integer range SIZE-1 downto 0 := 0;
variable is_busy: std_logic := '0';
variable already_stepped : std_logic := '0';
begin
if rising_edge(CLK1) then
slower_spi_clock <= not slower_spi_clock;
if is_busy = '1' then
if sm_valid = '1' and already_stepped = '0' then
already_stepped := '1';
if address = SIZE-1 then
is_busy := '0';
address := 0;
else
address := address + 1;
end if;
elsif sm_valid = '0' then
already_stepped := '0';
end if;
else
if start = '1' then
is_busy := '1';
end if;
end if;
thebusy <= is_busy;
theaddress <= address;
gated_spi_clock <= is_busy and (not slower_spi_clock);
end if;
end process;
end Behavioral;
| mit |
corywalker/vhdl_fft | ft_controller_tb.vhd | 3 | 3130 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:26:21 10/22/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/ft_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ft_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ft_controller_tb IS
END ft_controller_tb;
ARCHITECTURE behavior OF ft_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ft_controller
generic (
SIZE : positive;
SIZELOG : positive;
DELAY : positive;
INT_EXT_SEL: std_logic;
SPI_2X_CLK_DIV: positive;
DA_RESET_DELAY: positive
);
PORT(
CLK1 : IN std_logic;
rst : IN std_logic;
adc_miso : IN std_logic;
start_i : IN std_logic;
busy_o : OUT std_logic;
sck_i : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK1 : std_logic := '0';
signal rst : std_logic := '0';
signal start : std_logic := '0';
signal busy : std_logic;
signal sck : std_logic := '0';
-- Clock period definitions
constant CLK1_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ft_controller
generic map (
SIZE => 512,
SIZELOG => 9,
DELAY => 300,
INT_EXT_SEL => '0',
SPI_2X_CLK_DIV => 2,
DA_RESET_DELAY => 200
)
PORT MAP (
CLK1 => CLK1,
rst => rst,
start_i => start,
busy_o => busy,
sck_i => sck,
adc_miso => '0'
);
-- Clock process definitions
CLK1_process :process
begin
CLK1 <= '0';
wait for CLK1_period/2;
CLK1 <= '1';
wait for CLK1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
loop
start <= '1';
wait for 30 ns;
start <= '0';
wait for CLK1_period*10;
wait until busy = '0';
wait for 1us;
for I in 0 to 512*16 loop
sck <= '1';
wait for 30 ns;
sck <= '0';
wait for 30 ns;
end loop;
wait for 10us;
end loop;
wait;
end process;
END;
| mit |
FearlessJojo/COPproject | project/maintester.vhd | 1 | 3919 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:53:20 11/25/2016
-- Design Name:
-- Module Name: Z:/Documents/COP/COPproject/project/maintester.vhd
-- Project Name: project
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: main
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY maintester IS
END maintester;
ARCHITECTURE behavior OF maintester IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT main
PORT(
CLK0 : IN std_logic;
CLK1 : IN std_logic;
RAM1DATA : INOUT std_logic_vector(15 downto 0);
RAM2DATA : INOUT std_logic_vector(15 downto 0);
RAM1EN : OUT std_logic;
RAM1OE : OUT std_logic;
RAM1WE : OUT std_logic;
RAM2EN : OUT std_logic;
RAM2OE : OUT std_logic;
RAM2WE : OUT std_logic;
RAM1ADDR : OUT std_logic_vector(17 downto 0);
RAM2ADDR : OUT std_logic_vector(17 downto 0);
RESET : IN std_logic;
rdn : OUT std_logic;
wrn : OUT std_logic;
data_ready : IN std_logic;
tbre : IN std_logic;
tsre : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK0 : std_logic := '0';
signal CLK1 : std_logic := '0';
signal RESET : std_logic := '1';
signal data_ready : std_logic := '0';
signal tbre : std_logic := '0';
signal tsre : std_logic := '0';
--BiDirs
signal RAM1DATA : std_logic_vector(15 downto 0);
signal RAM2DATA : std_logic_vector(15 downto 0);
--Outputs
signal RAM1EN : std_logic;
signal RAM1OE : std_logic;
signal RAM1WE : std_logic;
signal RAM2EN : std_logic;
signal RAM2OE : std_logic;
signal RAM2WE : std_logic;
signal RAM1ADDR : std_logic_vector(17 downto 0);
signal RAM2ADDR : std_logic_vector(17 downto 0);
signal rdn : std_logic;
signal wrn : std_logic;
-- Clock period definitions
constant CLK0_period : time := 1 sec;
constant CLK1_period : time := 1 sec;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: main PORT MAP (
CLK0 => CLK0,
CLK1 => CLK1,
RAM1DATA => RAM1DATA,
RAM2DATA => RAM2DATA,
RAM1EN => RAM1EN,
RAM1OE => RAM1OE,
RAM1WE => RAM1WE,
RAM2EN => RAM2EN,
RAM2OE => RAM2OE,
RAM2WE => RAM2WE,
RAM1ADDR => RAM1ADDR,
RAM2ADDR => RAM2ADDR,
RESET => RESET,
rdn => rdn,
wrn => wrn,
data_ready => data_ready,
tbre => tbre,
tsre => tsre
);
-- Clock process definitions
CLK0_process :process
begin
CLK0 <= '0';
wait for CLK0_period/2;
CLK0 <= '1';
wait for CLK0_period/2;
end process;
CLK1 <= '1';
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK0_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit |
Hyvok/KittLights | kitt_lights_top.vhd | 1 | 1484 | library ieee;
library work;
use ieee.std_logic_1164.all;
entity kitt_lights_top is
generic
(
LIGHTS_N : positive := 8;
ADVANCE_VAL : positive := 5000000;
PWM_BITS_N : positive := 8;
DECAY_VAL : positive := 52000
);
port
(
clk_in : in std_logic;
reset_in : in std_logic;
lights_out : out std_logic_vector(LIGHTS_N - 1 downto 0)
);
end entity;
architecture rtl of kitt_lights_top is
signal reset : std_logic;
signal lights : std_logic_vector(LIGHTS_N - 1 downto 0);
begin
-- Synchronize reset signal to clock and invert it
sync_reset_p: process(clk_in, reset)
begin
if rising_edge(clk_in) then
if reset_in = '0' then
reset <= '1';
else
reset <= '0';
end if;
end if;
end process;
-- Invert signal for LEDs
lights_out <= not lights;
kitt_lights_p: entity work.kitt_lights(rtl)
generic map
(
LIGHTS_N => LIGHTS_N,
ADVANCE_VAL => ADVANCE_VAL,
PWM_BITS_N => PWM_BITS_N,
DECAY_VAL => DECAY_VAL
)
port map
(
clk => clk_in,
reset => reset,
lights_out => lights
);
end;
| mit |
jchromik/hpi-vhdl-2016 | pue4/Audio/audio_scancode_to_divisor.vhd | 1 | 1582 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:51:13 07/09/2016
-- Design Name:
-- Module Name: audio_scancode_to_divisor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity audio_scancode_to_divisor is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
clock_divisor : out INTEGER);
end audio_scancode_to_divisor;
architecture Behavioral of audio_scancode_to_divisor is
begin
process(scancode)
begin
case scancode is
when "00100011" => clock_divisor <= 3367000; -- 297 Hz (d')
when "00100100" => clock_divisor <= 30303000; -- 330 Hz (e')
when "00101011" => clock_divisor <= 284091000; -- 352 Hz (f')
when "00110100" => clock_divisor <= 25252; -- 396 Hz (g')
when "00011100" => clock_divisor <= 22727; -- 440 Hz (a')
when "00110011" => clock_divisor <= 2020; -- 495 Hz (h')
when others => clock_divisor <= 378788; -- 264 Hz (c');
end case;
end process;
end Behavioral;
| mit |
mjpatter88/fundamentals | 01-logic_gates/xor/myXor2_tb.vhdl | 1 | 1029 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myXor2_tb is
end myXor2_tb;
architecture behavorial of myXor2_tb is
component myXor2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
signal s1: std_logic;
signal s2: std_logic;
signal o1: std_logic;
begin
myXor2_1: myXor2 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= '0';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "0 xor 0 should be 0" severity error;
s1 <= '0';
s2 <= '1';
wait for 1 ns;
assert o1 = '1' report "0 xor 1 should be 1" severity error;
s1 <= '1';
s2 <= '0';
wait for 1 ns;
assert o1 = '1' report "1 xor 0 should be 1" severity error;
s1 <= '1';
s2 <= '1';
wait for 1 ns;
assert o1 = '0' report "1 xor 1 should be 0" severity error;
assert false report "Tests complete" severity note;
wait;
end process;
end behavorial;
| mit |
mjpatter88/fundamentals | 01-logic_gates/and/myAnd2_tb.vhdl | 1 | 1111 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myAnd2_tb is
end myAnd2_tb;
architecture behavioral of myAnd2_tb is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
-- signals used for testing
signal s1: std_logic;
signal s2: std_logic;
signal o1: std_logic;
begin
-- component instantiation
myAnd2_1: myAnd2 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= '0';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "and('0', '0') was not '0'" severity error;
s1 <= '0';
s2 <= '1';
wait for 1 ns;
assert o1 = '0' report "and('0', '1') was not '0'" severity error;
s1 <= '1';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "and('1', '0') was not '0'" severity error;
s1 <= '1';
s2 <= '1';
wait for 1 ns;
assert o1 = '1' report "and('1', '1') was not '1'" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
| mit |
mjpatter88/fundamentals | 01-logic_gates/not/myNot.vhdl | 1 | 389 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myNot is
port(a: in std_logic; s: out std_logic);
end myNot;
architecture behavioral of myNot is
component myNand2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
signal one: std_logic;
begin
one <= '1';
myNand2_1: myNand2 port map(a => a, b => '1', s => s);
end behavioral;
| mit |
mjpatter88/fundamentals | 01-logic_gates/or/myOr16_tb.vhdl | 1 | 1361 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myOr16_tb is
end myOr16_tb;
architecture behavioral of myOr16_tb is
component myOr16
port(a: in std_logic_vector(15 downto 0); b: in std_logic_vector(15 downto 0); s: out std_logic_vector(15 downto 0));
end component;
-- signals used for testing
signal s1: std_logic_vector(15 downto 0);
signal s2: std_logic_vector(15 downto 0);
signal o1: std_logic_vector(15 downto 0);
begin
-- component instantiation
myOr16_1: myOr16 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= "0000000000000000";
s2 <= "0000000000000000";
wait for 1 ns;
assert o1 = "0000000000000000" report "or('0000000000000000', '0000000000000000') was not '0000000000000000'" severity error;
s1 <= "1111111100000000";
s2 <= "0000000011111111";
wait for 1 ns;
assert o1 = "1111111111111111" report "or('1111111100000000', '0000000011111111') was not '1111111111111111'" severity error;
s1 <= "0000111100001111";
s2 <= "0000111111110000";
wait for 1 ns;
assert o1 = "0000111111111111" report "or('0000111100001111', '0000111111110000') was not '0000111111111111'" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
| mit |
mjpatter88/fundamentals | 01-logic_gates/mux/myMux2_tb.vhdl | 1 | 1797 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myMux2_tb is
end myMux2_tb;
architecture behavioral of myMux2_tb is
component myMux2
port(a: in std_logic; b: in std_logic; sel: in std_logic; s: out std_logic);
end component;
-- signals used for testing
signal s1: std_logic;
signal s2: std_logic;
signal sel: std_logic;
signal o1: std_logic;
begin
-- component instantiation
myMux2_1: myMux2 port map(a => s1, b => s2, sel => sel, s => o1);
process
begin
s1 <= '0';
s2 <= '0';
sel <= '0';
wait for 1 ns;
assert o1 = '0' report "0,0,0 was not 0" severity error;
s1 <= '0';
s2 <= '1';
sel <= '0';
wait for 1 ns;
assert o1 = '0' report "0,1,0 was not 0" severity error;
s1 <= '1';
s2 <= '0';
sel <= '0';
wait for 1 ns;
assert o1 = '1' report "1,0,0 was not 1" severity error;
s1 <= '1';
s2 <= '1';
sel <= '0';
wait for 1 ns;
assert o1 = '1' report "1,1,0 was not 1" severity error;
s1 <= '0';
s2 <= '0';
sel <= '1';
wait for 1 ns;
assert o1 = '0' report "0,0,1 was not 0" severity error;
s1 <= '0';
s2 <= '1';
sel <= '1';
wait for 1 ns;
assert o1 = '1' report "0,1,1 was not 1" severity error;
s1 <= '1';
s2 <= '0';
sel <= '1';
wait for 1 ns;
assert o1 = '0' report "1,0,1 was not 0" severity error;
s1 <= '1';
s2 <= '1';
sel <= '1';
wait for 1 ns;
assert o1 = '1' report "1,1,1 was not 1" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
| mit |
GSimas/EEL5105 | AULA6/reg4.vhd | 3 | 406 | library ieee;
use ieee.std_logic_1164.all;
entity D_4FF is port (
CLK, RST: in std_logic;
EN: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end D_4FF;
architecture behv of D_4FF is
begin
process(CLK, D, RST)
begin
if RST = '0' then
Q <= "0000";
elsif (CLK'event and CLK = '1') then
if EN = '0' then
Q <= D;
end if;
end if;
end process;
end behv; | mit |
bertuccio/ARQ | Practica3/procesador.vhd | 1 | 13702 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity procesador is
port(
Clk : in std_logic;
Reset : in std_logic;
-- Instruction memory
I_Addr : out std_logic_vector(31 downto 0);
I_RdStb : out std_logic;
I_WrStb : out std_logic;
I_AddrStb : out std_logic;
I_DataOut : out std_logic_vector(31 downto 0);
I_Rdy : in std_logic;
I_DataIn : in std_logic_vector(31 downto 0);
-- Data memory
D_Addr : out std_logic_vector(31 downto 0);
D_RdStb : out std_logic;
D_WrStb : out std_logic;
D_AddrStb : out std_logic;
D_DataOut : out std_logic_vector(31 downto 0);
D_Rdy : in std_logic;
D_DataIn : in std_logic_vector(31 downto 0)
);
end procesador;
architecture procesador_arq of procesador is
------------------------
------COMPONENTES-------
------------------------
component tabla_registros PORT
( CLK : in STD_LOGIC;
Reset : in STD_LOGIC;
EscrReg : in STD_LOGIC;
reg_lec1 : in STD_LOGIC_VECTOR (4 downto 0);
reg_lec2 : in STD_LOGIC_VECTOR (4 downto 0);
reg_escr: in STD_LOGIC_VECTOR (4 downto 0);
dato_escr : in STD_LOGIC_VECTOR (31 downto 0);
dato_leido1 : out STD_LOGIC_VECTOR (31 downto 0);
dato_leido2 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component ALU PORT
( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
control : in STD_LOGIC_VECTOR (3 downto 0);
resultado : out STD_LOGIC_VECTOR (31 downto 0);
igual : out STD_LOGIC);
end component;
component ForwardingUnit Port
( ID_EX_RS : in STD_LOGIC_VECTOR (4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR (4 downto 0);
EX_MEM_ESCREG : in STD_LOGIC;
MEM_WB_ESCREG : in STD_LOGIC;
EX_MEM_RD : in STD_LOGIC_VECTOR (4 downto 0);
MEM_WB_RD : in STD_LOGIC_VECTOR (4 downto 0);
AnticipaA : out STD_LOGIC_VECTOR (1 downto 0);
AnticipaB : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component HAZARD
Port ( PC_Write : out STD_LOGIC;
IFID_Write : out STD_LOGIC;
IDEX_Memread : in STD_LOGIC;
MUX_sel : out STD_LOGIC;
IDEX_Rt : in STD_LOGIC_VECTOR (4 downto 0);
IFID_Rs : in STD_LOGIC_VECTOR (4 downto 0);
IFID_Rt : in STD_LOGIC_VECTOR (4 downto 0));
end component;
------------------
-----SEÑALES------
------------------
signal PC_IN : STD_LOGIC_VECTOR (31 downto 0);
signal PC_IN1 : STD_LOGIC_VECTOR (31 downto 0);
signal addResultIN : STD_LOGIC_VECTOR (31 downto 0);
signal addResultOUT : STD_LOGIC_VECTOR (31 downto 0);
signal MemMux1 : STD_LOGIC_VECTOR (31 downto 0);
signal MemMux2 : STD_LOGIC_VECTOR (31 downto 0);
-------ALU-----------------------------------------
signal OpA : STD_LOGIC_VECTOR (31 downto 0);
signal OpAPosible : STD_LOGIC_VECTOR (31 downto 0);
signal OpB : STD_LOGIC_VECTOR (31 downto 0);
signal mux1OpB: STD_LOGIC_VECTOR (31 downto 0);
signal mux1OpBPosible : STD_LOGIC_VECTOR (31 downto 0);
signal mux2OpB: STD_LOGIC_VECTOR (31 downto 0);
signal AluControl : STD_LOGIC_VECTOR (5 downto 0);
signal ALUctr : STD_LOGIC_VECTOR (3 downto 0);
signal Zero : STD_LOGIC;
signal AluResultIN : STD_LOGIC_VECTOR (31 downto 0);
signal AluResultOUT : STD_LOGIC_VECTOR (31 downto 0);
---------------------------------------------------
--------------CONTROL----------------------------
signal Control: STD_LOGIC_VECTOR (5 downto 0);
------EX------------
signal EXctr : std_logic_vector(3 downto 0);
signal EXHAZARD : std_logic_vector(3 downto 0);
signal RegDst: STD_LOGIC;
signal ALUOp: STD_LOGIC_VECTOR (1 downto 0);
signal AluSrc : STD_LOGIC;
-------M------------
signal Mctr : std_logic_vector(2 downto 0);
signal MHAZARD : std_logic_vector(2 downto 0);
signal Mctr1 : std_logic_vector(2 downto 0);
signal Mctr2 : std_logic_vector(2 downto 0);
signal PCSrc : STD_LOGIC;
------WB------------
signal WEctr : std_logic_vector(1 downto 0);
signal WEHAZARD : std_logic_vector(1 downto 0);
signal WEctr1 : std_logic_vector(1 downto 0);
signal WEctr2 : std_logic_vector(1 downto 0);
signal EscrReg : STD_LOGIC;
signal MemToReg : STD_LOGIC;
---------------------------------------------------
signal signo_extend: STD_LOGIC_VECTOR (31 downto 0);
signal reg_lect1IF : STD_LOGIC_VECTOR (4 downto 0);
signal reg_lect2IF : STD_LOGIC_VECTOR (4 downto 0);
signal rdInstCarg : STD_LOGIC_VECTOR (4 downto 0);
signal rdInstALU : STD_LOGIC_VECTOR (4 downto 0);
signal reg_escr: STD_LOGIC_VECTOR (4 downto 0);
signal reg_escrIN: STD_LOGIC_VECTOR (4 downto 0);
signal dato_leido1 : STD_LOGIC_VECTOR (31 downto 0);
signal dato_leido2 : STD_LOGIC_VECTOR (31 downto 0);
signal dato_escr : STD_LOGIC_VECTOR (31 downto 0);
signal RegEscribir1 : STD_LOGIC_VECTOR (4 downto 0);
signal RegEscribir2 : STD_LOGIC_VECTOR (4 downto 0);
signal mux_aux1 : STD_LOGIC_VECTOR (4 downto 0);
signal mux_aux2 : STD_LOGIC_VECTOR (4 downto 0);
---------FORWARDINGUNIT-----------
signal ID_EX_RS : STD_LOGIC_VECTOR (4 downto 0);
signal ID_EX_RT : STD_LOGIC_VECTOR (4 downto 0);
signal EX_MEM_ESCREG : STD_LOGIC;
signal MEM_WB_ESCREG : STD_LOGIC;
signal EX_MEM_RD : STD_LOGIC_VECTOR (4 downto 0);
signal MEM_WB_RD : STD_LOGIC_VECTOR (4 downto 0);
signal AnticipaA : STD_LOGIC_VECTOR (1 downto 0);
signal AnticipaB : STD_LOGIC_VECTOR (1 downto 0);
signal PC_Write : STD_LOGIC;
signal IFID_Write : STD_LOGIC;
signal IDEX_Memread : STD_LOGIC;
signal MUX_sel : STD_LOGIC;
signal IDEX_Rt : STD_LOGIC_VECTOR (4 downto 0);
signal IFID_Rs : STD_LOGIC_VECTOR (4 downto 0);
signal IFID_Rt : STD_LOGIC_VECTOR (4 downto 0);
begin
-----------------
----PORT-MAPS----
-----------------
--BANCO REGISTROS--
BANCO: tabla_registros port map(
CLK => Clk,
Reset => Reset,
EscrReg => EscrReg,
reg_lec1 => reg_lect1IF,
reg_lec2 => reg_lect2IF,
reg_escr => reg_escr,
dato_escr => dato_escr,
dato_leido1 => dato_leido1,
dato_leido2 => dato_leido2);
--ALU--
UAL : ALU port map(
A => OpA,
B => OpB,
control => ALUctr,
resultado => AluResultIN,
igual => Zero);
UnitForward: ForwardingUnit port map(
ID_EX_RS =>ID_EX_RS,
ID_EX_RT =>ID_EX_RT,
EX_MEM_ESCREG => EX_MEM_ESCREG,
MEM_WB_ESCREG =>MEM_WB_ESCREG,
EX_MEM_RD => EX_MEM_RD,
MEM_WB_RD => MEM_WB_RD,
AnticipaA => AnticipaA,
AnticipaB => AnticipaB);
HazardUnit: HAZARD port map(
PC_Write=>PC_Write,
IFID_Write=> IFID_Write,
IDEX_Memread=>IDEX_Memread,
MUX_sel=>MUX_sel,
IDEX_Rt=>IDEX_Rt,
IFID_Rs=>IFID_Rs,
IFID_Rt=>IFID_Rt);
I_RdStb<='1';
I_WrStb<='0';
I_AddrStb<='1';
D_AddrStb<='1';
I_Addr<=PC_IN;
I_DataOut<=x"00000000";
------------------------------
----CONTADOR DE PROGRAMA------
------------------------------
process(Clk,Reset)
begin
if Reset='1' then
PC_IN<=x"00000000";
else
if rising_edge(Clk) then
if PC_Write='1' then
if (PCSrc='1') then
PC_IN<=addResultOUT;
else
PC_IN<=PC_IN+4;
end if;
end if;
end if;
end if;
end process;
-----------------------
---PRIMER PIPE (IF)----
-----------------------
process (Clk,Reset)
begin
if (Reset='1')or (PcSrc='1') then
PC_IN1<=x"00000000";
Control<= "111111";
reg_lect1IF<="00000";
reg_lect2IF<="00000";
rdInstCarg<= "00000";
rdInstALU<= "00000";
signo_extend<=x"00000000";
IFID_Rs<="00000";
IFID_Rt<="00000";
else
if rising_edge(Clk) then
if (IFID_Write='1') then
PC_IN1<=PC_IN;
Control <= I_DataIn(31 downto 26);
reg_lect1IF <=I_DataIn(25 downto 21);
reg_lect2IF <=I_DataIn(20 downto 16);
rdInstCarg <= I_DataIn(20 downto 16);
rdInstALU <= I_DataIn(15 downto 11);
if I_DataIn(15)='1' then
signo_extend<=x"FFFF"&I_DataIn(15 downto 0);
else
signo_extend<=x"0000"&I_DataIn(15 downto 0);
end if;
end if;
end if;
end if;
end process;
IFID_Rs<=reg_lect1IF;
IFID_Rt<=reg_lect2IF;
IDEX_Rt<=mux_aux1;
IDEX_Memread<=Mctr1(1);
-----------------------
---SEGUNDO PIPE (EX)--
-----------------------
process (Clk,Reset)
begin
if (Reset='1')or (PcSrc='1') then
WEctr1<="00";
Mctr1<="000";
ALUOp<="00";
ALUcontrol<="000000";
OpAPosible<=x"00000000";
mux1OpBPosible<=x"00000000";
mux2OpB<=x"00000000";
mux_aux1<="00000";
mux_aux2<="00000";
addResultIN<=x"00000000";
AluSrc<='0';
RegDst<='0';
ID_EX_RS<="00000";
ID_EX_RT<="00000";
IDEX_Rt<="00000";
else
if rising_edge(Clk) then
if (PcSrc='1') then
WEctr1<="00";
Mctr1<="000";
ALUOp<="00";
ALUcontrol<="000000";
OpAPosible<=x"00000000";
mux1OpBPosible<=x"00000000";
mux2OpB<=x"00000000";
mux_aux1<="00000";
mux_aux2<="00000";
addResultIN<=x"00000000";
AluSrc<='0';
RegDst<='0';
ID_EX_RS<="00000";
ID_EX_RT<="00000";
IDEX_Rt<="00000";
else
WEctr1<=WEctr;
Mctr1<=Mctr;
ALUcontrol<=signo_extend(5 downto 0);
mux2OpB<=signo_extend;
addResultIN<=signo_extend(29 downto 0)&"00"+PC_IN1;
OpAPosible<=dato_leido1;
mux1OpBPosible<=dato_leido2;
mux_aux1<=rdInstCarg;
mux_aux2<=rdInstALU;
RegDst<=EXctr(3);
ALUOp<=EXctr(2 downto 1);
AluSrc<=EXctr(0);
ID_EX_RS<=reg_lect1IF;
ID_EX_RT<=reg_lect2IF;
end if;
end if;
end if;
end process;
----------MULTIPLEXORES--------------
WITH AluSrc SELECT
OpB <=mux1OpB WHEN '0',
mux2OpB WHEN OTHERS;
WITH RegDst SELECT
regEscribir1 <=mux_aux1 WHEN '0',
mux_aux2 WHEN OTHERS;
WITH MemToReg SELECT
dato_escr <=MemMux2 WHEN '0',
MemMux1 WHEN OTHERS;
------------------------------------
--MULTIPLEXOR PARA ELEGIR LA ENTRADA A LA ALU DEL OPERANDO A
process (OpAPosible, AnticipaA, dato_escr, aluResultOUT)
begin
if( AnticipaA= "00" )then
OpA <= OpAPosible;
elsif( AnticipaA="01" ) then
OpA <= dato_escr;
elsif( AnticipaA="10" ) then
OpA <= aluResultOUT;--when AnticipaA="10"
end if;
end process;
--MULTIPLEXOR PARA ELEGIR LA ENTRADA POSIBLE DEL OPERANDO B
process (mux1OpB, AnticipaB, dato_escr, aluResultOUT)
begin
if( AnticipaB= "00" )then
mux1OpB <= mux1OpBPosible;
elsif( AnticipaB="01" ) then
mux1OpB <= dato_escr;
elsif( AnticipaB="10" ) then
mux1OpB <= aluResultOUT;
end if;
end process;
-----------------------
---TERCER PIPE (MEM)--
-----------------------
process (Clk,Reset)
begin
if (Reset='1') then
addResultOUT<=x"00000000";
D_WrStb<='0';--memwrite
D_RdStb<='0';--memread
PCSrc<='0';
D_DataOut<=x"00000000";
aluResultOUT<=x"00000000";
WEctr2<="00";
regEscribir2<="00000";
D_Addr<=x"00000000";
EX_MEM_ESCREG<='0';
IDEX_Memread <= '0';
EX_MEM_RD<="00000";
else
if rising_edge(Clk) then
if (PcSrc='1') then
addResultOUT<=x"00000000";
D_WrStb<='0';--memwrite
D_RdStb<='0';--memread
PCSrc<='0';
D_DataOut<=x"00000000";
aluResultOUT<=x"00000000";
WEctr2<="00";
regEscribir2<="00000";
D_Addr<=x"00000000";
EX_MEM_ESCREG<='0';
IDEX_Memread <= '0';
EX_MEM_RD<="00000";
else
WEctr2<=WEctr1;
addResultOUT<=addResultIN;
D_WrStb<=Mctr1(0);--memwrite
D_RdStb<=Mctr1(1);--memread
PCSrc<=Mctr1(2) and Zero;
EX_MEM_RD<=regEscribir1;
D_Addr<=AluResultIN;
aluResultOUT<=AluResultIN;
D_DataOut<=mux1OpB;
regEscribir2<=regEscribir1;
EX_MEM_ESCREG<=WEctr1(1);
end if;
end if;
end if;
end process;
-------------------
----REGISTRO 4-----
-------------------
process (Clk,Reset) begin
if (Reset='1')or (PcSrc='1') then
MemMux1<=x"00000000";
MemMux2<=x"00000000";
reg_escr<="00000";
MemToReg<='0';
EscrReg<='0';
MEM_WB_ESCREG<='0';
else
if rising_edge(Clk) then
MemMux1<=D_DataIn;
MemMux2<=aluResultOUT;
reg_escr<=regEscribir2;
MemToReg<=WEctr2(0);
EscrReg<=WEctr2(1);
MEM_WB_ESCREG<=WEctr2(1);
MEM_WB_RD<=regEscribir2;
end if;
end if;
end process;
process (ALUOp, ALUcontrol) begin
case ALUOp is
when "10"=>--REG_A_REG
case ALUcontrol is
when "100000"=>--ADD
ALUctr<="0011";
when "100010"=>--SUB
ALUctr<="1000";
when "100100"=>--AND
ALUctr<="0000";
when "100101"=>--OR
ALUctr<="0001";
when "100110"=>--XOR
ALUctr<="0010";
when "101010"=>--SLT
ALUctr<="1010";
when others =>
ALUctr<="1111";
end case;
when "00"=>--LW ó SW
ALUctr<="0011";--ADD PARA CONSEGUIR LA DIRECCION DE MEMORIA
when "01"=>--BEQ
ALUctr<="0010";--XOR PARA VER SI RS Y RT SON IGUALES
when "11"=>--LIU
ALUctr<="1001";
when others =>
ALUctr<="1111";
end case;
end process;
process (Control) begin
case Control is
when "000000"=> --SPECIAL (R)
EXHAZARD<="1100";
MHAZARD<="000";
WEHAZARD<="10";
when "100011"=> --LW
EXHAZARD<="0001";
MHAZARD<="010";
WEHAZARD<="11";
when "101011"=> --SW
EXHAZARD<="0001";
MHAZARD<="001";
WEHAZARD<="00";
when "001111"=> --LIU
EXHAZARD<="0110";
MHAZARD<="000";
WEHAZARD<="10";
when "000100"=> --BE
EXHAZARD<="0010";
MHAZARD<="100";
WEHAZARD<="00";
when others =>
EXHAZARD<="0000";
MHAZARD<="000";
WEHAZARD<="00";
end case;
end process;
process (MUX_Sel, WEHAZARD,MHAZARD,EXHAZARD)
begin
if MUX_Sel='1' then
WEctr<="00";
Mctr<="000";
EXctr<="0000";
elsif MUX_Sel='0' then
WEctr<=WEHAZARD;
Mctr<=MHAZARD;
EXctr<=EXHAZARD;
end if;
end process;
end procesador_arq;
| mit |
GSimas/EEL5105 | PROJETO-EEL5105/Projeto/FSM_control.vhd | 1 | 1900 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--FSM de controle de estados do jogo
entity FSM_control is port(
CLK, RESET, END_BONUS, END_TIME, ENTER, TARGET: in std_logic;
SEL_DISP: out std_logic_vector(1 downto 0);
STATESS: out std_logic_vector(4 downto 0);
SEL_LED, SET_ROLL, EN_TIME, RST: out std_logic
);
end FSM_control;
--Definir arquitetura
architecture bhv of FSM_control is
type states is (E0, E1, E2, E3);
signal EA, PE: states;
begin
--Processo 1 para Clock e Reset
P1: process(CLK, RESET)
begin
if RESET = '0' then
EA <= E0;
elsif CLK'event and CLK = '1' then
EA <= PE;
end if;
end process;
--Processo 2 para estados
P2: process(EA, TARGET, ENTER, END_TIME, END_BONUS)
begin
case EA is
--ESTADO INIT
when E0 => STATESS <= "00000";
SEL_LED <= '0';
SEL_DISP <= "10";
SET_ROLL <= '0';
EN_TIME <= '0';
RST <= '0';
if ENTER = '0' then
PE <= E1;
elsif ENTER = '1' then
PE <= E0;
end if;
--ESTADO SETUP
when E1 => STATESS <= "00001";
SEL_LED <= '0';
SEL_DISP <= "01";
SET_ROLL <= '0';
EN_TIME <= '0';
RST <= '1';
if ENTER = '0' then
PE <= E2;
elsif ENTER = '1' then
PE <= E1;
end if;
--ESTADO GAME
when E2 => STATESS <= "00010";
SEL_LED <= '1';
SEL_DISP <= "00";
SET_ROLL <= '1';
EN_TIME <= '1';
RST <= '1';
if TARGET = '1' or END_TIME = '1' or END_BONUS = '1' then
PE <= E3;
else
PE <= E2;
end if;
--ESTADO END
when E3 => STATESS <= "00011";
SEL_LED <= '0';
SEL_DISP <= "11";
SET_ROLL <= '0';
EN_TIME <= '0';
RST <= '1';
if ENTER = '0' then
PE <= E0;
elsif ENTER = '1' then
PE <= E3;
end if;
end case;
end process;
end bhv;
| mit |
UVVM/uvvm_vvc_framework | uvvm_vvc_framework/src_target_dependent/td_queue_pkg.vhd | 3 | 2199 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
--===============================================================================================
-- td_cmd_queue_pkg
-- - Target dependent command queue package
--===============================================================================================
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_generic_queue_pkg;
use work.vvc_cmd_pkg.all;
package td_cmd_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg
generic map (t_generic_element => t_vvc_cmd_record);
--===============================================================================================
-- td_result_queue_pkg
-- - Target dependent result queue package
--===============================================================================================
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_generic_queue_pkg;
use work.vvc_cmd_pkg.all;
package td_result_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg
generic map (t_generic_element => t_vvc_result_queue_element);
| mit |
UVVM/uvvm_vvc_framework | bitvis_vip_sbi/src/vvc_cmd_pkg.vhd | 3 | 6948 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
WRITE, READ, CHECK, POLL_UNTIL);
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
max_polls : integer;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
operation => NO_OPERATION, -- Default unless overwritten by a common operation
addr => (others => '0'),
data => (others => '0'),
max_polls => 1,
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - These are used for storing the result of the read/receive BFM commands issued by the VVC,
-- - so that the result can be transported from the VVC to the sequencer via a
-- a fetch_result() call as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result matches the return value of read/receive procedure in the BFM.
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit |
UVVM/uvvm_vvc_framework | bitvis_vip_gpio/src/vvc_cmd_pkg.vhd | 3 | 6886 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--========================================================================================================================
-- t_operation
-- - VVC and BFM operations
--========================================================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
SET, GET, CHECK, EXPECT
);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION, -- Default unless overwritten by a common operation
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET,
-- VVC dedicated fields
data => (others => '0'),
data_exp => (others => '0')
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - These are used for storing the result of the read/receive BFM commands issued by the VVC,
-- - so that the result can be transported from the VVC to the sequencer via a
-- a fetch_result() call as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result matches the return value of read/receive procedure in the BFM.
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit |
UVVM/uvvm_vvc_framework | xConstrRandFuncCov/src/SortListPkg_int.vhd | 3 | 13743 | --
-- File Name: SortListPkg_int.vhd
-- Design Unit Name: SortListPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
-- Description:
-- Sorting utility for array of scalars
-- Uses protected type so as to shrink and expand the data structure
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2008: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009: 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/16/2010 1.2 Added EraseList parameter to to_array
-- 3/2011 2.0 added inside as non protected type
-- 6/2011 2.1 added sort as non protected type
-- 4/2013 2013.04 No Changes
-- 5/2013 2013.05 No changes of substance.
-- Deleted extra variable declaration in procedure remove
-- 1/2014 2014.01 Added RevSort. Added AllowDuplicate paramter to Add procedure
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 11/2016 2016.11 Revised Add. When AllowDuplicate, add a matching value last.
--
--
--
-- Copyright (c) 2008 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.std_logic_textio.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
package SortListPkg_int is
-- with VHDL-2008, convert package to generic package
-- convert subtypes ElementType and ArrayofElementType to generics
-- package SortListGenericPkg is
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector ;
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType ;
type SortListPType is protected
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) ;
procedure add ( constant A : in ArrayofElementType ) ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) ;
procedure add ( variable A : inout SortListPType ) ;
-- Count items in list
impure function count return integer ;
impure function find_index ( constant A : ElementType) return integer ;
impure function inside (constant A : ElementType) return boolean ;
procedure insert ( constant A : in ElementType; constant index : in integer := 1 ) ;
impure function get ( constant index : in integer := 1 ) return ElementType ;
procedure erase ;
impure function Empty return boolean ;
procedure print ;
procedure remove ( constant A : in ElementType ) ;
procedure remove ( constant A : in ArrayofElementType ) ;
procedure remove ( variable A : inout SortListPType ) ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
end protected SortListPType ;
end SortListPkg_int ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body SortListPkg_int is
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop
if E = A(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
type SortListPType is protected body
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
A : ElementType ;
-- item_num : integer ;
NextPtr : ListPointerType ;
-- PrevPtr : ListPointerType ;
end record ;
variable HeadPointer : ListPointerType := NULL ;
-- variable TailPointer : ListPointerType := NULL ;
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
HeadPointer := new ListType'(A, NULL) ;
elsif A = HeadPointer.A then -- ignore duplicates
if AllowDuplicate then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
end if ;
elsif A < HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
AddLoop : loop
exit AddLoop when CurPtr.NextPtr = NULL ;
exit AddLoop when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
-- if AllowDuplicate then -- changed s.t. insert at after match rather than before
-- exit AddLoop ; -- insert
-- else
if not AllowDuplicate then
return ; -- return without insert
end if;
end if ;
CurPtr := CurPtr.NextPtr ;
end loop AddLoop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
add(A(i)) ;
end loop ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) is
begin
for i in A'range loop
if A(i) >= Min and A(i) <= Max then
add(A(i)) ;
end if ;
end loop ;
end procedure add ;
procedure add ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
add(A.Get(i)) ;
end loop ;
end procedure add ;
-- Count items in list
impure function count return integer is
variable result : positive := 1 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function count ;
impure function find_index (constant A : ElementType) return integer is
variable result : positive := 2 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
elsif A <= HeadPointer.A then
return 1 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A <= CurPtr.NextPtr.A ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function find_index ;
impure function inside (constant A : ElementType) return boolean is
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return FALSE ;
end if ;
if A = HeadPointer.A then
return TRUE ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
return TRUE ; -- exit
end if;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
return FALSE ;
end function inside ;
procedure insert( constant A : in ElementType; constant index : in integer := 1 ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if index <= 1 then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
for i in 3 to index loop
exit when CurPtr.NextPtr = NULL ; -- end of list
CurPtr := CurPtr.NextPtr ;
end loop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if;
end procedure insert ;
impure function get ( constant index : in integer := 1 ) return ElementType is
variable CurPtr : ListPointerType ;
begin
if index > Count then
Alert(OSVVM_ALERTLOG_ID, "SortLIstPkg_int.get index out of range", FAILURE) ;
return ElementType'left ;
elsif HeadPointer = NULL then
return ElementType'left ;
elsif index <= 1 then
return HeadPointer.A ;
else
CurPtr := HeadPointer ;
for i in 2 to index loop
CurPtr := CurPtr.NextPtr ;
end loop ;
return CurPtr.A ;
end if;
end function get ;
procedure erase (variable CurPtr : inout ListPointerType ) is
begin
if CurPtr.NextPtr /= NULL then
erase (CurPtr.NextPtr) ;
end if ;
deallocate (CurPtr) ;
end procedure erase ;
procedure erase is
begin
if HeadPointer /= NULL then
erase(HeadPointer) ;
-- deallocate (HeadPointer) ;
HeadPointer := NULL ;
end if;
end procedure erase ;
impure function Empty return boolean is
begin
return HeadPointer = NULL ;
end Empty ;
procedure print is
variable buf : line ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
write (buf, string'("( )")) ;
else
CurPtr := HeadPointer ;
write (buf, string'("(")) ;
loop
write (buf, CurPtr.A) ;
exit when CurPtr.NextPtr = NULL ;
write (buf, string'(", ")) ;
CurPtr := CurPtr.NextPtr ;
end loop ;
write (buf, string'(")")) ;
end if ;
writeline(OUTPUT, buf) ;
end procedure print ;
procedure remove ( constant A : in ElementType ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return ;
elsif A = HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := HeadPointer.NextPtr ;
deallocate (tempPtr) ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
if A = CurPtr.NextPtr.A then
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
deallocate (tempPtr) ;
exit ;
end if ;
exit when A < CurPtr.NextPtr.A ;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
end procedure remove ;
procedure remove ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
remove(A(i)) ;
end loop ;
end procedure remove ;
procedure remove ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
remove(A.Get(i)) ;
end loop ;
end procedure remove ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(1 to Count) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_array ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(Count downto 1) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_rev_array ;
end protected body SortListPType ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_array(EraseList => TRUE) ;
end function sort ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_rev_array(EraseList => TRUE) ;
end function revsort ;
end SortListPkg_int ;
| mit |
UVVM/uvvm_vvc_framework | bitvis_vip_clock_generator/src/clock_generator_vvc.vhd | 1 | 16223 | --========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--========================================================================================================================
entity clock_generator_vvc is
generic (
GC_INSTANCE_IDX : natural;
GC_CLOCK_NAME : string;
GC_CLOCK_PERIOD : time;
GC_CLOCK_HIGH_TIME : time;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
clk : out std_logic
);
begin
assert (GC_CLOCK_NAME'length <= 20) report "Clock name is too long (max 30 characters)" severity ERROR;
end entity clock_generator_vvc;
--========================================================================================================================
--========================================================================================================================
architecture behave of clock_generator_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
signal clock_ena : boolean := false;
-- Instantiation of the element dedicated executor
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_clock_generator_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_clock_generator_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_clock_generator_transaction_info(GC_INSTANCE_IDX);
alias clock_name : string is vvc_config.clock_name;
alias clock_period : time is vvc_config.clock_period;
alias clock_high_time : time is vvc_config.clock_high_time;
impure function get_clock_name
return string is
begin
return clock_name(1 to pos_of_leftmost(NUL, clock_name, clock_name'length));
end function;
begin
--========================================================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--========================================================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, C_VOID_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--========================================================================================================================
--========================================================================================================================
-- Config initializer
-- - Set up the VVC specific config fields
--========================================================================================================================
config_initializer : process
begin
loop
wait for 0 ns;
exit when shared_uvvm_state = PHASE_B;
end loop;
clock_name := (others => NUL);
clock_name(1 to GC_CLOCK_NAME'length) := GC_CLOCK_NAME;
clock_period := GC_CLOCK_PERIOD;
clock_high_time := GC_CLOCK_HIGH_TIME;
wait;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--========================================================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the executor if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
-- Await completion of all commands in the cmd_executor executor
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command executor
-- - Fetch and execute the commands
--========================================================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when START_CLOCK =>
if clock_ena then
tb_error("Clock " & clock_name & " already running. " & format_msg(v_cmd), C_SCOPE);
else
clock_ena <= true;
wait for 0 ns;
log(ID_CLOCK_GEN, "Clock " & clock_name & " started", C_SCOPE);
end if;
when STOP_CLOCK =>
if not clock_ena then
tb_error("Clock " & clock_name & " already stopped. " & format_msg(v_cmd), C_SCOPE);
else
clock_ena <= false;
if clk then
wait until not clk;
end if;
log(ID_CLOCK_GEN, "Clock" & clock_name & " stopped", C_SCOPE);
end if;
when SET_CLOCK_PERIOD =>
clock_period := v_cmd.clock_period;
log(ID_CLOCK_GEN, "Clock " & clock_name & " period set to " & to_string(clock_period), C_SCOPE);
when SET_CLOCK_HIGH_TIME =>
clock_high_time := v_cmd.clock_high_time;
log(ID_CLOCK_GEN, "Clock " & clock_name & " high time set to " & to_string(clock_high_time), C_SCOPE);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--========================================================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--========================================================================================================================
--========================================================================================================================
-- Clock Generator process
-- - Process that generates the clock signal
--========================================================================================================================
clock_generator : process
variable v_clock_period : time;
variable v_clock_high_time : time;
begin
wait for 0 ns; -- wait for clock_ena to be set
loop
-- Clock period is sampled so it won't change during a clock cycle and potentialy introduce negative time in
-- last wait statement
v_clock_period := clock_period;
v_clock_high_time := clock_high_time;
if v_clock_high_time >= v_clock_period then
tb_error(clock_name & ": clock period must be larger than clock high time; clock period: " & to_string(v_clock_period) & ", clock high time: " & to_string(clock_high_time), C_SCOPE);
end if;
if not clock_ena then
clk <= '0';
wait until clock_ena;
end if;
clk <= '1';
wait for v_clock_high_time;
clk <= '0';
wait for (v_clock_period - v_clock_high_time);
end loop;
end process;
--========================================================================================================================
end architecture behave;
| mit |
UVVM/uvvm_vvc_framework | uvvm_vvc_framework/src/ti_vvc_framework_support_pkg.vhd | 1 | 22598 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_vvc_framework_support_pkg is
constant C_VVC_NAME_MAX_LENGTH : natural := 20;
------------------------------------------------------------------------
-- Common support types for UVVM
------------------------------------------------------------------------
type t_immediate_or_queued is (NO_command_type, IMMEDIATE, QUEUED);
type t_flag_record is record
set : std_logic;
reset : std_logic;
is_active : std_logic;
end record;
type t_uvvm_state is (IDLE, PHASE_A, PHASE_B, INIT_COMPLETED);
type t_lastness is (LAST, NOT_LAST);
type t_broadcastable_cmd is (NO_CMD, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, INSERT_DELAY, AWAIT_COMPLETION, TERMINATE_CURRENT_COMMAND);
constant C_BROADCAST_CMD_STRING_MAX_LENGTH : natural := 300;
type t_vvc_broadcast_cmd_record is record
operation : t_broadcastable_cmd;
msg_id : t_msg_id;
msg : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
proc_call : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
quietness : t_quietness;
delay : time;
timeout : time;
gen_integer : integer;
end record;
constant C_VVC_BROADCAST_CMD_DEFAULT : t_vvc_broadcast_cmd_record := (
operation => NO_CMD,
msg_id => NO_ID,
msg => (others => NUL),
proc_call => (others => NUL),
quietness => NON_QUIET,
delay => 0 ns,
timeout => 0 ns,
gen_integer => -1
);
------------------------------------------------------------------------
-- Common signals for acknowledging a pending command
------------------------------------------------------------------------
shared variable shared_vvc_broadcast_cmd : t_vvc_broadcast_cmd_record := C_VVC_BROADCAST_CMD_DEFAULT;
signal VVC_BROADCAST : std_logic := 'L';
------------------------------------------------------------------------
-- Common signal for signalling between VVCs, used during await_any_completion()
-- Default (when not active): Z
-- Awaiting: 1:
-- Completed: 0
-- This signal is a vector to support multiple sequencers calling await_any_completion simultaneously:
-- - When calling await_any_completion, each sequencer specifies which bit in this global signal the VVCs shall use.
------------------------------------------------------------------------
signal global_awaiting_completion : std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0); -- ACK on global triggers
------------------------------------------------------------------------
-- Shared variables for UVVM framework
------------------------------------------------------------------------
shared variable shared_cmd_idx : integer := 0;
shared variable shared_uvvm_state : t_uvvm_state := IDLE;
-------------------------------------------
-- flag_handler
-------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
);
-------------------------------------------
-- set_flag
-------------------------------------------
-- Sets reset and is_active to 'Z' and pulses set_flag
procedure set_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- reset_flag
-------------------------------------------
-- Sets set and is_active to 'Z' and pulses reset_flag
procedure reset_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- await_uvvm_initialization
-------------------------------------------
-- Waits until uvvm has been initialized
procedure await_uvvm_initialization(
constant dummy : in t_void
);
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Converts the command index to string, enclused by
-- C_CMD_IDX_PREFIX and C_CMD_IDX_SUFFIX
impure function format_command_idx(
command_idx : integer
) return string;
--***********************************************
-- BROADCAST COMMANDS
--***********************************************
-------------------------------------------
-- enable_log_msg (Broadcast)
-------------------------------------------
-- Enables a log message for all VVCs
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET
);
-------------------------------------------
-- disable_log_msg (Broadcast)
-------------------------------------------
-- Disables a log message for all VVCs
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET
);
-------------------------------------------
-- flush_command_queue (Broadcast)
-------------------------------------------
-- Flushes the command queue for all VVCs
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as number of clock cycles)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as time)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion (Broadcast)
-------------------------------------------
-- Wait for all VVCs to finish (specified as time)
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_current_command (Broadcast)
-------------------------------------------
-- terminates all current tasks
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_all_commands (Broadcast)
-------------------------------------------
-- terminates all tasks
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
);
-------------------------------------------
-- transmit_broadcast
-------------------------------------------
-- Common broadcast transmission routine
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit
);
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Inputs vvc_name and channel are truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH
-- are to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string;
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Input vvc_name is truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH
-- is to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string;
end package ti_vvc_framework_support_pkg;
package body ti_vvc_framework_support_pkg is
------------------------------------------------------------------------
--
------------------------------------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.set <= 'Z';
flag.is_active <= '0';
wait until flag.set = '1';
flag.is_active <= '1';
wait until flag.reset = '1';
flag.is_active <= '0';
end procedure;
procedure set_flag(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.set, 0 ns, "set flag");
end procedure;
procedure reset_flag(
signal flag : inout t_flag_record
) is
begin
flag.set <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.reset, 0 ns, "reset flag", C_TB_SCOPE_DEFAULT, ID_NEVER);
end procedure;
-- This procedure checks the shared_uvvm_state on each delta cycle
procedure await_uvvm_initialization(
constant dummy : in t_void) is
begin
while (shared_uvvm_state /= INIT_COMPLETED) loop
wait for 0 ns;
end loop;
end procedure;
impure function format_command_idx(
command_idx : integer
) return string is
begin
return C_CMD_IDX_PREFIX & to_string(command_idx) & C_CMD_IDX_SUFFIX;
end;
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, ENABLE_LOG_MSG, proc_call, msg_id, msg, quietness);
end procedure;
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, DISABLE_LOG_MSG, proc_call, msg_id, msg, quietness);
end procedure;
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, NON_QUIET, 0 ns, delay);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, INSERT_DELAY, proc_call, NO_ID, msg, NON_QUIET, delay);
end procedure;
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := ""
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, AWAIT_COMPLETION, proc_call, NO_ID, msg, NON_QUIET, 0 ns, -1, timeout);
end procedure;
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, TERMINATE_CURRENT_COMMAND, proc_call, NO_ID, msg);
end procedure;
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
) is
constant proc_name : string := "terminate_all_commands";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
flush_command_queue(VVC_BROADCAST, msg);
terminate_current_command(VVC_BROADCAST, msg);
end procedure;
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit) is
begin
await_semaphore_in_delta_cycles(protected_semaphore);
shared_vvc_broadcast_cmd.operation := operation;
shared_vvc_broadcast_cmd.msg_id := msg_id;
shared_vvc_broadcast_cmd.msg := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.msg(1 to msg'length) := msg;
shared_vvc_broadcast_cmd.quietness := quietness;
shared_vvc_broadcast_cmd.timeout := timeout;
shared_vvc_broadcast_cmd.delay := delay;
shared_vvc_broadcast_cmd.gen_integer := delay_int;
shared_vvc_broadcast_cmd.proc_call := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.proc_call(1 to proc_call'length) := proc_call;
if VVC_BROADCAST /= 'L' then
-- a VVC is waiting for example in await_completion
wait until VVC_BROADCAST = 'L';
end if;
-- Trigger the broadcast
VVC_BROADCAST <= '1';
wait for 0 ns;
-- set back to 'L' and wait until all VVCs have set it back
VVC_BROADCAST <= 'L';
wait until VVC_BROADCAST = 'L' for timeout; -- Wait for executor
if not (VVC_BROADCAST'event) and VVC_BROADCAST /= 'L' then -- Indicates timeout
tb_error("Timeout while waiting for the broadcast command to be ACK'ed", C_SCOPE);
else
log(ID_UVVM_CMD_ACK, "ACK received for broadcast command", C_SCOPE);
end if;
shared_vvc_broadcast_cmd := C_VVC_BROADCAST_CMD_DEFAULT;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
release_semaphore(protected_semaphore);
end procedure;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_CHANNEL_STR : string := to_upper(to_string(channel));
constant C_SCOPE_LENGTH : natural := vvc_name'length + C_INSTANCE_IDX_STR'length + C_CHANNEL_STR'length + 2; -- +2 because of the two added commas
variable v_vvc_name_truncation_value : integer;
variable v_channel_truncation_value : integer;
variable v_vvc_name_truncation_idx : integer;
variable v_channel_truncation_idx : integer;
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_MINIMUM_CHANNEL_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 2) > C_LOG_SCOPE_WIDTH then -- +2 because of the two added commas
alert(TB_WARNING, "The combined width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH cannot be greather than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 2.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If C_SCOPE_LENGTH is greater than allowed width
-- Check if vvc_name is greater than minimum width to truncate
elsif vvc_name'length <= C_MINIMUM_VVC_NAME_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to (C_CHANNEL_STR'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)));
-- Check if channel is greater than minimum width to truncate
elsif C_CHANNEL_STR'length <= C_MINIMUM_CHANNEL_SCOPE_WIDTH then
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If both vvc_name and channel is to be truncated
else
-- Calculate linear scaling of truncation between vvc_name and channel: (a*x)/(a+b), (b*x)/(a+b)
v_vvc_name_truncation_idx := integer(round(real(vvc_name'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
v_channel_truncation_value := integer(round(real(C_CHANNEL_STR'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
-- In case division ended with .5 and both rounded up
if (v_vvc_name_truncation_idx + v_channel_truncation_value) > (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH) then
v_channel_truncation_value := v_channel_truncation_value - 1;
end if;
-- Character index to truncate
v_vvc_name_truncation_idx := vvc_name'length - v_vvc_name_truncation_idx;
v_channel_truncation_idx := C_CHANNEL_STR'length - v_channel_truncation_value;
-- If bellow minimum name width
while v_vvc_name_truncation_idx < C_MINIMUM_VVC_NAME_SCOPE_WIDTH loop
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx + 1;
v_channel_truncation_idx := v_channel_truncation_idx - 1;
end loop;
-- If bellow minimum channel width
while v_channel_truncation_idx < C_MINIMUM_CHANNEL_SCOPE_WIDTH loop
v_channel_truncation_idx := v_channel_truncation_idx + 1;
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx - 1;
end loop;
return vvc_name(1 to v_vvc_name_truncation_idx) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to v_channel_truncation_idx);
end if;
end function;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_SCOPE_LENGTH : integer := vvc_name'length + C_INSTANCE_IDX_STR'length + 1; -- +1 because of the added comma
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 1) > C_LOG_SCOPE_WIDTH then -- +1 because of the added comma
alert(TB_WARNING, "The width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH cannot be greather than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 1.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR;
-- If C_SCOPE_LENGTH is greater than allowed width truncate vvc_name
else
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR;
end if;
end function;
end package body ti_vvc_framework_support_pkg;
| mit |
UVVM/uvvm_vvc_framework | uvvm_vvc_framework/src/ti_data_queue_pkg.vhd | 2 | 26776 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_data_queue_pkg is
-- Declaration of storage
subtype t_data_buffer is std_logic_vector(C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1 downto 0);
shared variable shared_data_buffer : t_data_buffer;
type t_buffer_natural_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of natural;
type t_buffer_boolean_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of boolean;
type t_data_queue is protected
------------------------------------------
-- init_queue
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the queue.
--
-- - Parameters:
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
-- - Returns: The index of the initiated queue (natural).
-- Returns 0 on error.
--
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural;
------------------------------------------
-- init_queue
------------------------------------------
-- This procedure allocates space in the buffer at the given queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be initialized.
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
);
------------------------------------------
-- flush
------------------------------------------
-- This procedure empties the queue given
-- by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be flushed.
--
procedure flush(
queue_idx : natural
);
------------------------------------------
-- push_back
------------------------------------------
-- This procedure pushes data to the end of a queue.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the queue size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure push_back(
queue_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- peek_front
------------------------------------------
-- This function returns the data from the front
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- peek_back
------------------------------------------
-- This function returns the data from the back
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_back
------------------------------------------
-- This function returns the data from the back
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_front
------------------------------------------
-- This function returns the data from the front
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The number of elements occupying the queue (natural).
--
--
impure function get_count(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_count_max
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the queue (natural).
--
--
impure function get_queue_count_max(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_is_full
------------------------------------------
-- This function returns a boolean indicating if the
-- queue is full or not.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: TRUE if queue is full, FALSE if not.
--
--
impure function get_queue_is_full(
queue_idx : natural
) return boolean;
------------------------------------------
-- deallocate_buffer
------------------------------------------
-- This procedure resets the entire std_logic_vector and all
-- variable arrays related to the buffer, effectively removing all queues.
--
-- - Parameters:
-- - dummy - VOID
--
--
procedure deallocate_buffer(
dummy : t_void
);
end protected;
end package ti_data_queue_pkg;
package body ti_data_queue_pkg is
type t_data_queue is protected body
-- Internal variables for the data queue
-- The buffer is one large std_logic_vector of size C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER.
-- There are several queues that can be instantiated in the slv.
-- There is one set of variables per queue.
variable v_queue_initialized : t_buffer_boolean_array := (others => false);
variable v_queue_size_in_bits : t_buffer_natural_array := (others => 0);
variable v_count : t_buffer_natural_array := (others => 0);
-- min_idx/max idx: These variables set the upper and lower limit of each queue in the buffer.
-- This is how the large slv buffer is divided into several smaller queues.
-- After a queue has been instantiated, all queue operations in the buffer
-- for a given idx will happen within the v_min_idx and v_max_idx boundary.
-- These variables will be set when a queue is instantiated, and will not
-- change afterwards.
variable v_min_idx : t_buffer_natural_array := (others => 0);
variable v_max_idx : t_buffer_natural_array := (others => 0);
variable v_next_available_idx : natural := 0; -- Where the v_min_idx of the next queue initialized shall be set.
-- first_idx/last_idx: These variables set the current indices within a queue, i.e., within
-- the min_idx/max_idx boundary. These variables will change every time
-- a given queue has data pushed or popped.
variable v_first_idx : t_buffer_natural_array := (others => 0);
variable v_last_idx : t_buffer_natural_array := (others => 0);
type t_string_pointer is access string;
variable v_scope : t_string_pointer := NULL;
------------------------------------------
-- init_queue
------------------------------------------
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural is
variable vr_queue_idx : natural;
variable vr_queue_idx_found : boolean := false;
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not check_value(v_next_available_idx < C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER, TB_ERROR,
"init_queue called, but no more space in buffer!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Find first available queue
-- and tag as initialized
for i in t_buffer_boolean_array'range loop
if not v_queue_initialized(i) then
-- Save queue idx
vr_queue_idx := i;
vr_queue_idx_found := true;
-- Tag this queue as initialized
v_queue_initialized(vr_queue_idx) := true;
exit; -- exit loop
end if;
end loop;
-- Verify that an available queue idx was found, else trigger alert and return 0
if not check_value(vr_queue_idx_found, TB_ERROR,
"init_queue called, but all queues have already been initialized!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(vr_queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(vr_queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(vr_queue_idx) := v_next_available_idx;
v_max_idx(vr_queue_idx) := v_min_idx(vr_queue_idx) + v_queue_size_in_bits(vr_queue_idx) - 1;
v_first_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_last_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_next_available_idx := v_max_idx(vr_queue_idx) + 1;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(vr_queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(vr_queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(vr_queue_idx);
-- Return the index of the buffer
return vr_queue_idx;
end function;
------------------------------------------
-- init_queue
------------------------------------------
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
) is
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not v_queue_initialized(queue_idx) then
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(queue_idx) := v_next_available_idx;
v_max_idx(queue_idx) := v_min_idx(queue_idx) + v_queue_size_in_bits(queue_idx) - 1;
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_next_available_idx := v_max_idx(queue_idx) + 1;
-- Tag this buffer as initialized
v_queue_initialized(queue_idx) := true;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(queue_idx);
else
alert(TB_ERROR, "init_queue called, but the desired buffer index is already in use! No action taken.", v_scope.all);
return;
end if;
end procedure;
------------------------------------------
-- push_back
------------------------------------------
procedure push_back(
queue_idx : natural;
data : std_logic_vector
) is
alias a_data : std_logic_vector(data'length - 1 downto 0) is data;
begin
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"push_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
for i in a_data'right to a_data'left loop -- From right to left since LSB shall be first in the queue.
shared_data_buffer(v_last_idx(queue_idx)) := a_data(i);
if v_last_idx(queue_idx) /= v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_last_idx(queue_idx) + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) + 1;
end loop;
log(ID_UVVM_DATA_QUEUE, "Data " & to_string(data, HEX) & " pushed to back of queue " & to_string(queue_idx) & " (index " & to_string(v_last_idx(queue_idx)) & "). Fill level is " & to_string(v_count(queue_idx)) & "/" & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
end if;
end procedure;
------------------------------------------
-- flush
------------------------------------------
procedure flush(
queue_idx : natural
) is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "flush called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
shared_data_buffer(v_max_idx(queue_idx) downto v_min_idx(queue_idx)) := (others => '0');
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_count(queue_idx) := 0;
end procedure;
------------------------------------------
-- peek_front
------------------------------------------
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_front() called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_front() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
v_current_idx := v_first_idx(queue_idx);
-- Generate return value
for i in 0 to v_return_entry'length - 1 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- peek_back
------------------------------------------
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_back called, but queue not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_back() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_last_idx(queue_idx) > 0 then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Generate return value
for i in v_return_entry'length - 1 downto 0 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- pop_back
------------------------------------------
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "pop_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_queue_initialized(queue_idx) then
v_return_entry := peek_back(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
if v_last_idx(queue_idx) > v_min_idx(queue_idx) then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
-- Set last idx
if v_current_idx < v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_current_idx + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
end if;
end if;
return v_return_entry;
end function;
------------------------------------------
-- pop_front
------------------------------------------
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural := v_first_idx(queue_idx);
begin
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"pop_front called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
v_return_entry := peek_front(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
-- v_first_idx points to the idx PREVIOUS to the first element in the buffer.
-- Therefore must correct if at max_idx.
v_current_idx := v_first_idx(queue_idx);
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
v_first_idx(queue_idx) := v_current_idx;
end if;
return v_return_entry;
end if;
v_return_entry := (others => '0');
return v_return_entry;
end function;
------------------------------------------
-- get_count
------------------------------------------
impure function get_count(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_count called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_count(queue_idx);
end function;
------------------------------------------
-- get_queue_count_max
------------------------------------------
impure function get_queue_count_max(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_count_max called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_queue_size_in_bits(queue_idx);
end function;
------------------------------------------
-- get_queue_is_full
------------------------------------------
impure function get_queue_is_full(
queue_idx : natural
) return boolean is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_is_full called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
if v_count(queue_idx) >= v_queue_size_in_bits(queue_idx) then
return true;
else
return false;
end if;
end function;
------------------------------------------
-- deallocate_buffer
------------------------------------------
procedure deallocate_buffer(
dummy : t_void
) is
begin
shared_data_buffer := (others => '0');
v_queue_initialized := (others => false);
v_queue_size_in_bits := (others => 0);
v_count := (others => 0);
v_min_idx := (others => 0);
v_max_idx := (others => 0);
v_first_idx := (others => 0);
v_last_idx := (others => 0);
v_next_available_idx := 0;
log(ID_UVVM_DATA_QUEUE, "Buffer has been deallocated, i.e., all queues removed.", v_scope.all);
end procedure;
end protected body;
end package body ti_data_queue_pkg;
| mit |
UVVM/uvvm_vvc_framework | xConstrRandFuncCov/src/MessagePkg.vhd | 2 | 5845 | --
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-line name/message to be associated with a data structure.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Latest standard version available at:
-- http://www.SynthWorks.com/downloads
--
-- Revision History:
-- Date Version Description
-- 06/2010: 0.1 Initial revision
-- 07/2014: 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- 07/2014: 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 01/2015: 2015.01 Removed initialized parameter from Get
-- 04/2018: 2018.04 Minor updates to alert message
--
--
-- Copyright (c) 2010 - 2018 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
package MessagePkg is
type MessagePType is protected
procedure Set (MessageIn : String) ;
impure function Get (ItemNumber : integer) return string ;
impure function GetCount return integer ;
impure function IsSet return boolean ;
procedure Clear ; -- clear message
procedure Deallocate ; -- clear message
end protected MessagePType ;
end package MessagePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body MessagePkg is
-- Local Data Structure Types
type LineArrayType is array (natural range <>) of line ;
type LineArrayPtrType is access LineArrayType ;
type MessagePType is protected body
variable MessageCount : integer := 0 ;
constant INITIAL_ITEM_COUNT : integer := 16 ;
variable MaxMessageCount : integer := 0 ;
variable MessagePtr : LineArrayPtrType ;
------------------------------------------------------------
procedure Set (MessageIn : String) is
------------------------------------------------------------
variable NamePtr : line ;
variable OldMaxMessageCount : integer ;
variable OldMessagePtr : LineArrayPtrType ;
begin
MessageCount := MessageCount + 1 ;
if MessageCount > MaxMessageCount then
OldMaxMessageCount := MaxMessageCount ;
MaxMessageCount := MaxMessageCount + INITIAL_ITEM_COUNT ;
OldMessagePtr := MessagePtr ;
MessagePtr := new LineArrayType(1 to MaxMessageCount) ;
for i in 1 to OldMaxMessageCount loop
MessagePtr(i) := OldMessagePtr(i) ;
end loop ;
Deallocate( OldMessagePtr ) ;
end if ;
MessagePtr(MessageCount) := new string'(MessageIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ItemNumber : integer) return string is
------------------------------------------------------------
begin
if MessageCount > 0 then
if ItemNumber >= 1 and ItemNumber <= MessageCount then
return MessagePtr(ItemNumber).all ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get input value out of range", FAILURE) ;
return "" ; -- error if this happens
end if ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get message is not set", FAILURE) ;
return "" ; -- error if this happens
end if ;
end function Get ;
------------------------------------------------------------
impure function GetCount return integer is
------------------------------------------------------------
begin
return MessageCount ;
end function GetCount ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return MessageCount > 0 ;
end function IsSet ;
------------------------------------------------------------
procedure Deallocate is -- clear message
------------------------------------------------------------
variable CurPtr : LineArrayPtrType ;
begin
for i in 1 to MessageCount loop
deallocate( MessagePtr(i) ) ;
end loop ;
MessageCount := 0 ;
MaxMessageCount := 0 ;
deallocate( MessagePtr ) ;
end procedure Deallocate ;
------------------------------------------------------------
procedure Clear is -- clear
------------------------------------------------------------
begin
Deallocate ;
end procedure Clear ;
end protected body MessagePType ;
end package body MessagePkg ; | mit |
UVVM/uvvm_vvc_framework | bitvis_irqc/src/irqc_pif_pkg.vhd | 3 | 3063 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif_pkg
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package irqc_pif_pkg is
-- Change this to a generic when generic in packages is allowed (VHDL 2008)
constant C_NUM_SOURCES : integer := 6; -- 1 <= C_NUM_SOURCES <= Data width
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_IRR : integer := 0;
constant C_ADDR_IER : integer := 1;
constant C_ADDR_ITR : integer := 2;
constant C_ADDR_ICR : integer := 3;
constant C_ADDR_IPR : integer := 4;
constant C_ADDR_IRQ2CPU_ENA : integer := 5;
constant C_ADDR_IRQ2CPU_DISABLE : integer := 6;
constant C_ADDR_IRQ2CPU_ALLOWED : integer := 7;
-- Signals from pif to core
type t_p2c is record
rw_ier : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_itr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_icr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_irq2cpu_ena : std_logic;
awt_irq2cpu_disable : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_irr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_ipr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_irq2cpu_allowed : std_logic;
end record t_c2p;
end package irqc_pif_pkg;
| mit |