repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringlengths 1
8
| size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
ptracton/Picoblaze | Picoblaze/UART_and_PicoTerm/uart_tx6.vhd | 1 | 15872 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_tx6 is
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_tx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_tx6
--
architecture low_level_definition of uart_tx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_tx6
--
-------------------------------------------------------------------------------------------
--
signal store_data : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sm_value : std_logic_vector(3 downto 0);
signal sm : std_logic_vector(3 downto 0);
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal lsb_data : std_logic;
signal msb_data : std_logic;
signal last_bit : std_logic;
signal serial_data : std_logic;
signal next_value : std_logic;
signal next_bit : std_logic;
signal buffer_read_value : std_logic;
signal buffer_read : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_tx6_1";
attribute hblknm of pointer3_flop : label is "uart_tx6_1";
attribute hblknm of pointer2_lut : label is "uart_tx6_1";
attribute hblknm of pointer2_flop : label is "uart_tx6_1";
attribute hblknm of pointer01_lut : label is "uart_tx6_1";
attribute hblknm of pointer1_flop : label is "uart_tx6_1";
attribute hblknm of pointer0_flop : label is "uart_tx6_1";
attribute hblknm of data_present_lut : label is "uart_tx6_1";
attribute hblknm of data_present_flop : label is "uart_tx6_1";
--
attribute hblknm of sm0_lut : label is "uart_tx6_2";
attribute hblknm of sm0_flop : label is "uart_tx6_2";
attribute hblknm of sm1_lut : label is "uart_tx6_2";
attribute hblknm of sm1_flop : label is "uart_tx6_2";
attribute hblknm of sm2_lut : label is "uart_tx6_2";
attribute hblknm of sm2_flop : label is "uart_tx6_2";
attribute hblknm of sm3_lut : label is "uart_tx6_2";
attribute hblknm of sm3_flop : label is "uart_tx6_2";
--
attribute hblknm of div01_lut : label is "uart_tx6_3";
attribute hblknm of div23_lut : label is "uart_tx6_3";
attribute hblknm of div0_flop : label is "uart_tx6_3";
attribute hblknm of div1_flop : label is "uart_tx6_3";
attribute hblknm of div2_flop : label is "uart_tx6_3";
attribute hblknm of div3_flop : label is "uart_tx6_3";
attribute hblknm of next_lut : label is "uart_tx6_3";
attribute hblknm of next_flop : label is "uart_tx6_3";
attribute hblknm of read_flop : label is "uart_tx6_3";
--
attribute hblknm of lsb_data_lut : label is "uart_tx6_4";
attribute hblknm of msb_data_lut : label is "uart_tx6_4";
attribute hblknm of serial_lut : label is "uart_tx6_4";
attribute hblknm of serial_flop : label is "uart_tx6_4";
attribute hblknm of full_lut : label is "uart_tx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_tx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_tx6_5";
attribute hblknm of storage_flop : label is "uart_tx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data_in(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => store_data(i) );
storage_flop: FD
port map ( D => store_data(i),
Q => data(i),
C => clk);
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
lsb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => data(3),
I4 => sm(0),
I5 => sm(1),
O => lsb_data);
msb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => data(7),
I4 => sm(0),
I5 => sm(1),
O => msb_data);
serial_lut: LUT6_2
generic map (INIT => X"CFAACC0F0FFFFFFF")
port map( I0 => lsb_data,
I1 => msb_data,
I2 => sm(1),
I3 => sm(2),
I4 => sm(3),
I5 => '1',
O5 => last_bit,
O6 => serial_data);
serial_flop: FD
port map ( D => serial_data,
Q => serial_out,
C => clk);
sm0_lut: LUT6
generic map (INIT => X"85500000AAAAAAAA")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(0));
sm0_flop: FD
port map ( D => sm_value(0),
Q => sm(0),
C => clk);
sm1_lut: LUT6
generic map (INIT => X"26610000CCCCCCCC")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(1));
sm1_flop: FD
port map ( D => sm_value(1),
Q => sm(1),
C => clk);
sm2_lut: LUT6
generic map (INIT => X"88700000F0F0F0F0")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(2));
sm2_flop: FD
port map ( D => sm_value(2),
Q => sm(2),
C => clk);
sm3_lut: LUT6
generic map (INIT => X"87440000FF00FF00")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(3));
sm3_flop: FD
port map ( D => sm_value(3),
Q => sm(3),
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => '1',
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"7F80FF007878F0F0")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
next_lut: LUT6_2
generic map (INIT => X"0000000080000000")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => last_bit,
O5 => next_value,
O6 => buffer_read_value);
next_flop: FD
port map ( D => next_value,
Q => next_bit,
C => clk);
read_flop: FD
port map ( D => buffer_read_value,
Q => buffer_read,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end low_level_definition;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_tx6.vhd
--
-------------------------------------------------------------------------------------------
| mit |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/src/spwlink.vhd | 2 | 10334 | --
-- SpaceWire Exchange Level Controller.
--
-- This entity implements exchange level aspects of the SpaceWire protocol.
-- It handles connection setup, error detection and flow control.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwlink is
generic (
-- Reset time expressed in system clock cycles.
-- Should be 6.4 us (5.82 us .. 7.2 us) according to the standard.
reset_time: integer
);
port (
-- System clock.
clk: in std_logic;
-- Synchronous reset (active-high).
-- Disconnects, resets error conditions, puts the link state machine
-- in state ErrorReset.
rst: in std_logic;
-- Link level inputs.
linki: in spw_link_in_type;
-- Link level outputs.
linko: out spw_link_out_type;
-- Receiver enable signal to spwrecv.
rxen: out std_logic;
-- Output signals from spwrecv.
recvo: in spw_recv_out_type;
-- Input signals for spwxmit.
xmiti: out spw_xmit_in_type;
-- Output signals from spwxmit.
xmito: in spw_xmit_out_type
);
end entity spwlink;
architecture spwlink_arch of spwlink is
-- Convert boolean to std_logic.
type bool_to_logic_type is array(boolean) of std_ulogic;
constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
-- State machine.
type state_type is (
S_ErrorReset, S_ErrorWait, S_Ready, S_Started, S_Connecting, S_Run );
-- Registers
type regs_type is record
-- state machine
state: state_type;
-- credit accounting
tx_credit: unsigned(5 downto 0);
rx_credit: unsigned(5 downto 0);
errcred: std_ulogic;
-- reset timer
timercnt: unsigned(10 downto 0);
timerdone: std_ulogic;
-- signal to transmitter
xmit_fct_in: std_ulogic;
end record;
-- Initial state
constant regs_reset: regs_type := (
state => S_ErrorReset,
tx_credit => "000000",
rx_credit => "000000",
errcred => '0',
timercnt => to_unsigned(reset_time, 11),
timerdone => '0',
xmit_fct_in => '0' );
signal r: regs_type := regs_reset;
signal rin: regs_type;
begin
-- Combinatorial process
process (r, rst, linki, recvo, xmito) is
variable v: regs_type;
variable v_timerrst: std_logic;
begin
v := r;
v_timerrst := '0';
-- State machine.
case r.state is
when S_ErrorReset =>
-- Wait for timer.
if r.timercnt = 0 then
v.state := S_ErrorWait;
v_timerrst := '1';
end if;
v.errcred := '0';
v.xmit_fct_in := '0';
when S_ErrorWait =>
-- Wait for 2 timer periods.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then
-- Note: spwrecv will never issue errpar, erresc, gotfct,
-- tick_out or rxchar before the first NULL has been seen.
-- Therefore it's ok here to bail on those conditions
-- without explicitly testing got_null.
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif r.timercnt = 0 then
if r.timerdone = '1' then
v.state := S_Ready;
v_timerrst := '1';
end if;
end if;
when S_Ready =>
-- Wait for link start.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif (linki.linkdis = '0') and (r.xmit_fct_in = '1') and
((linki.linkstart or (linki.autostart and recvo.gotnull)) = '1') then
v.state := S_Started; -- link enabled; start sending NULL
v_timerrst := '1';
end if;
when S_Started =>
-- Wait for NULL.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') or
((r.timercnt = 0) and r.timerdone = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif recvo.gotnull = '1' then
v.state := S_Connecting; -- received null, continue
v_timerrst := '1';
end if;
when S_Connecting =>
-- Wait for FCT.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.tick_out or recvo.rxchar) = '1') or
((r.timercnt = 0) and r.timerdone = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif recvo.gotfct = '1' then
v.state := S_Run; -- got FCT, init completed
end if;
when S_Run =>
-- All is well.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
(r.errcred = '1') or
(linki.linkdis = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
end if;
when others =>
v.state := S_ErrorReset; -- recover from invalid state
v_timerrst := '1';
end case;
-- Update credit counters.
if r.state = S_ErrorReset then
-- reset credit
v.tx_credit := to_unsigned(0, v.tx_credit'length);
v.rx_credit := to_unsigned(0, v.rx_credit'length);
else
-- update TX credit
if recvo.gotfct = '1' then
-- just received a FCT token
v.tx_credit := v.tx_credit + to_unsigned(8, v.tx_credit'length);
if r.tx_credit > 48 then
-- received too many FCT tokens
v.errcred := '1';
end if;
end if;
if xmito.txack = '1' then
-- just sent one byte
v.tx_credit := v.tx_credit - to_unsigned(1, v.tx_credit'length);
end if;
-- update RX credit after sending FCT
if xmito.fctack = '1' then
-- just sent a FCT token
v.rx_credit := v.rx_credit + to_unsigned(8, v.rx_credit'length);
end if;
-- decide about sending FCT tokens
v.xmit_fct_in := bool_to_logic( (v.rx_credit <= 48) and
(v.rx_credit + to_unsigned(8, v.rx_credit'length) <= unsigned(linki.rxroom)) );
-- update RX credit after receiving character
if recvo.rxchar = '1' then
-- just received a character
v.rx_credit := v.rx_credit - to_unsigned(1, v.rx_credit'length);
if r.rx_credit = 0 then
-- remote transmitter violated its credit
v.errcred := '1';
end if;
end if;
end if;
-- Update the initializaton reset timer.
if v_timerrst = '1' then
v.timercnt := to_unsigned(reset_time, v.timercnt'length);
v.timerdone := '0';
else
if r.timercnt = 0 then
v.timercnt := to_unsigned(reset_time, v.timercnt'length);
v.timerdone := '1';
else
v.timercnt := r.timercnt - 1;
end if;
end if;
-- Reset
if rst = '1' then
v := regs_reset;
end if;
-- Drive link level outputs.
linko.started <= bool_to_logic(r.state = S_Started);
linko.connecting <= bool_to_logic(r.state = S_Connecting);
linko.running <= bool_to_logic(r.state = S_Run);
linko.errdisc <= recvo.errdisc and bool_to_logic(r.state = S_Run);
linko.errpar <= recvo.errpar and bool_to_logic(r.state = S_Run);
linko.erresc <= recvo.erresc and bool_to_logic(r.state = S_Run);
linko.errcred <= r.errcred;
linko.txack <= xmito.txack;
linko.tick_out <= recvo.tick_out and bool_to_logic(r.state = S_Run);
linko.ctrl_out <= recvo.ctrl_out;
linko.time_out <= recvo.time_out;
linko.rxchar <= recvo.rxchar and bool_to_logic(r.state = S_Run);
linko.rxflag <= recvo.rxflag;
linko.rxdata <= recvo.rxdata;
-- Drive receiver inputs.
rxen <= bool_to_logic(r.state /= S_ErrorReset);
-- Drive transmitter input signals.
xmiti.txen <= bool_to_logic(r.state = S_Started or
r.state = S_Connecting or
r.state = S_Run);
xmiti.stnull <= bool_to_logic(r.state = S_Started);
xmiti.stfct <= bool_to_logic(r.state = S_Connecting);
xmiti.fct_in <= r.xmit_fct_in;
xmiti.tick_in <= linki.tick_in and bool_to_logic(r.state = S_Run);
xmiti.ctrl_in <= linki.ctrl_in;
xmiti.time_in <= linki.time_in;
xmiti.txwrite <= linki.txwrite and bool_to_logic(r.tx_credit /= 0);
xmiti.txflag <= linki.txflag;
xmiti.txdata <= linki.txdata;
-- Update registers.
rin <= v;
end process;
-- Update registers.
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwlink_arch;
| mit |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Filter_Top_Level.vhd | 1 | 8396 | ---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:05 05/05/2015
-- Design Name:
-- Module Name: Filter_Top_Level - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Top_Level is
Port(slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
CLK_48 : in std_logic;
RST : in std_logic;
SAMPLE_TRIG : in std_logic;
sample_trigger_en : in std_logic;
HP_SW : in std_logic;
BP_SW : in std_logic;
LP_SW : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- sample_trig : in STD_LOGIC;
-- Audio_in : in STD_LOGIC_VECTOR (23 downto 0);
-- filter_done : in STD_LOGIC;
-- Audio_out : in STD_LOGIC_VECTOR (23 downto 0)
);
end Filter_Top_Level;
architecture RTL of Filter_Top_Level is
Component IIR_Biquad_II_v3 is
Port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end Component;
signal IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L : std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L : std_logic_vector(23 downto 0);
signal sample_trigger_safe : STD_LOGIC := '0';
signal val : std_logic_vector(2 downto 0);
begin
sample_trigger_safe <= SAMPLE_TRIG or (not sample_trigger_en);
val <= HP_SW & BP_SW & LP_SW;
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L; -- & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R; -- & X"00";
---this process controls each individual filter and the final output of the filter.
MUX_filters: process(IIR_BP_Y_Out_L, IIR_BP_Y_Out_R, IIR_HP_Y_Out_L, IIR_HP_Y_Out_R, IIR_LP_Y_Out_L, IIR_LP_Y_Out_R, val, RST)
begin
if rst = '1' then
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
else
case VAL is
when "000" =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when "001" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_HP_Y_Out_R;
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R + IIR_BP_Y_Out_R;
when "111" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
end case;
end if;
end process;
IIR_LP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
end RTL;
| mit |
ObKo/USBCore | Extra/blk_ep_in_ctl.vhdl | 1 | 6039 | --
-- USB Full-Speed/Hi-Speed Device Controller core - blk_ep_in_ctl.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity blk_ep_in_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_in_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
axis_tdata : in std_logic_vector(7 downto 0);
axis_tvalid : in std_logic;
axis_tready : out std_logic;
axis_tlast : in std_logic
);
end blk_ep_in_ctl;
architecture blk_ep_in_ctl of blk_ep_in_ctl is
component blk_in_fifo
port (
m_aclk : in std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tlast : in std_logic;
axis_prog_full : out std_logic
);
end component;
type MACHINE is (S_Idle, S_Xfer);
signal state : MACHINE := S_Idle;
signal s_axis_tvalid : std_logic;
signal s_axis_tready : std_logic;
signal s_axis_tdata : std_logic_vector(7 downto 0);
signal s_axis_tlast : std_logic;
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tdata : std_logic_vector(7 downto 0);
signal m_axis_tlast : std_logic;
signal prog_full : std_logic;
signal was_last_usb : std_logic;
signal was_last : std_logic;
signal was_last_d : std_logic;
signal was_last_dd : std_logic;
begin
FSM: process(usb_clk) is
begin
if rst = '1' then
state <= S_Idle;
blk_xfer_in_has_data <= '0';
elsif rising_edge(usb_clk) then
case state is
when S_Idle =>
if was_last_usb = '1' OR prog_full = '1' then
blk_xfer_in_has_data <= '1';
end if;
if blk_in_xfer = '1' then
state <= S_Xfer;
end if;
when S_Xfer =>
if blk_in_xfer = '0' then
blk_xfer_in_has_data <= '0';
state <= S_Idle;
end if;
end case;
end if;
end process;
ASYNC: if USE_ASYNC_FIFO generate
-- 3 of data clk => axis_clk < 180 MHz if usb_clk = 60 MHz
was_last_usb <= was_last OR was_last_d OR was_last_dd;
FIFO: blk_in_fifo
port map (
m_aclk => usb_clk,
s_aclk => axis_clk,
s_aresetn => NOT rst,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
axis_prog_full => prog_full
);
end generate;
SYNC: if not USE_ASYNC_FIFO generate
was_last_usb <= was_last;
FIFO: sync_fifo
generic map (
FIFO_WIDTH => 8,
FIFO_DEPTH => 1024,
PROG_FULL_VALUE => 64
)
port map (
clk => usb_clk,
rst => rst,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
prog_full => prog_full
);
end generate;
WAS_LAST_LATCHER: process(axis_clk) is
begin
if rst = '1' then
was_last <= '0';
was_last_d <= '0';
was_last_dd <= '0';
elsif rising_edge(axis_clk) then
if s_axis_tvalid = '1' AND s_axis_tready = '1' AND s_axis_tlast = '1' then
was_last <= '1';
elsif s_axis_tvalid = '1' AND s_axis_tready = '1' AND s_axis_tlast = '0' then
was_last <= '0';
end if;
was_last_d <= was_last;
was_last_dd <= was_last_d;
end if;
end process;
s_axis_tdata <= axis_tdata;
s_axis_tvalid <= axis_tvalid;
axis_tready <= s_axis_tready;
s_axis_tlast <= axis_tlast;
blk_xfer_in_data <= m_axis_tdata;
blk_xfer_in_data_valid <= m_axis_tvalid;
m_axis_tready <= blk_xfer_in_data_ready;
blk_xfer_in_data_last <= m_axis_tlast;
end blk_ep_in_ctl; | mit |
ObKo/USBCore | Extra/extra_pkg.vhdl | 1 | 3447 | --
-- USB Full-Speed/Hi-Speed Device Controller core - extra_pkg.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
package USBExtra is
component blk_ep_out_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
axis_tdata : out std_logic_vector(7 downto 0);
axis_tvalid : out std_logic;
axis_tready : in std_logic;
axis_tlast : out std_logic
);
end component;
component blk_ep_in_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_in_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
axis_tdata : in std_logic_vector(7 downto 0);
axis_tvalid : in std_logic;
axis_tready : out std_logic;
axis_tlast : in std_logic
);
end component;
component sync_fifo
generic (
constant FIFO_WIDTH : positive;
constant FIFO_DEPTH : positive;
constant PROG_FULL_VALUE: positive
);
port (
clk : in std_logic;
rst : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tlast : out std_logic;
prog_full : out std_logic
);
end component;
end USBExtra; | mit |
timtian090/Playground | UVM/UVMExamples/mod01_sv_for_vhdlers/SystemVerilog_for_VHDL_Engineers_Primer/primer_examples/datatypes/width_depth/width_depth_rtl.vhd | 1 | 616 | --
-- VHDL Architecture width_depth.width_depth.rtl
--
-- Created:
-- by - Ray.UNKNOWN (WRITINGMACHINE)
-- at - 07:46:00 05/ 4/2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY width_depth IS
END ENTITY width_depth;
--
ARCHITECTURE rtl OF width_depth IS
signal halfbyte : std_logic_vector( 3 downto 0 ) ;
type reversebits_mem_type is array (7 downto 0) of std_logic_vector(1 to 8);
signal reversebits_mem: reversebits_mem_type;
BEGIN
END ARCHITECTURE rtl;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/input_output.vhd | 3 | 5695 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity input_output is
PORT ( CLK_I : in std_logic;
ADR_I : in std_logic_vector( 7 downto 0);
CYC_I : in std_logic;
STB_I : in std_logic;
ACK_O : out std_logic;
RST_O : out STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
HALT : in STD_LOGIC;
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
-- temperature
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- input/output
IO : in std_logic;
WE_I : in std_logic;
IO_RDAT : out std_logic_vector( 7 downto 0);
IO_WDAT : in std_logic_vector( 7 downto 0);
INT : out STD_LOGIC
);
end input_output;
architecture Behavioral of input_output is
COMPONENT temperature
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
TEMP_SPO : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic
);
END COMPONENT;
COMPONENT uart_baudgen
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
RD : IN std_logic;
WR : IN std_logic;
TX_DATA : IN std_logic_vector(7 downto 0);
RX_SERIN : IN std_logic;
TX_SEROUT : OUT std_logic;
RX_DATA : OUT std_logic_vector(7 downto 0);
RX_READY : OUT std_logic;
TX_BUSY : OUT std_logic
);
END COMPONENT;
signal IO_RD_SERIAL : std_logic;
signal IO_WR_SERIAL : std_logic;
signal RX_READY : std_logic;
signal TX_BUSY : std_logic;
signal RX_DATA : std_logic_vector(7 downto 0);
signal TEMP_DO : std_logic_vector(7 downto 0);
signal SERDAT : std_logic;
signal LCLR : std_logic;
signal C1_N, C2_N : std_logic; -- switch debounce, active low
signal RX_INT_ENABLED : std_logic;
signal TX_INT_ENABLED : std_logic;
signal TIM_INT_ENABLED : std_logic;
signal TIMER_INT : std_logic;
signal TIMER : std_logic_vector(15 downto 0);
signal CLK_COUNT : std_logic_vector(16 downto 0);
signal CLK_COUNT_EN : std_logic;
signal CLK_HALT_MSK : std_logic;
signal CLK_HALT_VAL : std_logic;
begin
tempr: temperature
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
DATA_OUT => TEMP_DO,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
uart: uart_baudgen
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
RD => IO_RD_SERIAL,
WR => IO_WR_SERIAL,
TX_DATA => IO_WDAT,
TX_SEROUT => SER_OUT,
RX_SERIN => SER_IN,
RX_DATA => RX_DATA,
RX_READY => RX_READY,
TX_BUSY => TX_BUSY
);
RST_O <= LCLR;
INT <= (RX_INT_ENABLED and RX_READY)
or (TX_INT_ENABLED and not TX_BUSY)
or (TIM_INT_ENABLED and TIMER_INT);
SERDAT <= (IO and CYC_I) when (ADR_I = X"00") else '0';
IO_RD_SERIAL <= SERDAT and not WE_I;
IO_WR_SERIAL <= SERDAT and WE_I;
ACK_O <= STB_I;
-- IO read process
--
process(ADR_I, RX_DATA, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
RX_INT_ENABLED, RX_READY, TEMP_DO, SWITCH, CLK_COUNT)
begin
case ADR_I is
when X"00" => IO_RDAT <= RX_DATA;
when X"01" => IO_RDAT <= '0'
& (TIM_INT_ENABLED and TIMER_INT)
& (TX_INT_ENABLED and not TX_BUSY)
& (RX_INT_ENABLED and RX_READY)
& '0'
& TIMER_INT
& TX_BUSY
& RX_READY;
when X"02" => IO_RDAT <= TEMP_DO;
when X"03" => IO_RDAT <= SWITCH(7 downto 0);
when X"05" => IO_RDAT <= CLK_COUNT(8 downto 1);
when others => IO_RDAT <= CLK_COUNT(16 downto 9);
end case;
end process;
-- IO write and timer process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LCLR = '1') then
LED <= X"00";
RX_INT_ENABLED <= '0';
TX_INT_ENABLED <= '0';
TIM_INT_ENABLED <= '0';
TIMER_INT <= '0';
TIMER <= X"0000";
else
if (IO = '1' and CYC_I = '1' and WE_I = '1') then
case ADR_I is
when X"00" => -- handled by uart
when X"01" => -- handled by uart
when X"02" => LED <= IO_WDAT;
when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
TX_INT_ENABLED <= IO_WDAT(1);
TIM_INT_ENABLED <= IO_WDAT(2);
when X"04" => TIMER_INT <= '0';
when X"05" => CLK_COUNT_EN <= '1';
CLK_COUNT <= '0' & X"0000";
CLK_HALT_VAL <= IO_WDAT(0);
CLK_HALT_MSK <= IO_WDAT(1);
when X"06" => CLK_COUNT_EN <= '0';
when others =>
end case;
end if;
if (TIMER = 39999) then -- 1 ms at 40 MHz
TIMER_INT <= '1';
TIMER <= X"0000";
else
TIMER <= TIMER + 1;
end if;
if (CLK_COUNT_EN = '1' and
(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
CLK_COUNT <= CLK_COUNT + 1;
end if;
end if;
end if;
end process;
-- reset debounce process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
-- switch debounce
if (SWITCH(8) = '1' or SWITCH(9) = '1') then
LCLR <= '1';
C2_N <= '0';
C1_N <= '0';
else
LCLR <= not C2_N;
C2_N <= C1_N;
C1_N <= '1';
end if;
end if;
end process;
end Behavioral;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/input_output.vhd | 3 | 5695 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity input_output is
PORT ( CLK_I : in std_logic;
ADR_I : in std_logic_vector( 7 downto 0);
CYC_I : in std_logic;
STB_I : in std_logic;
ACK_O : out std_logic;
RST_O : out STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
HALT : in STD_LOGIC;
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
-- temperature
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- input/output
IO : in std_logic;
WE_I : in std_logic;
IO_RDAT : out std_logic_vector( 7 downto 0);
IO_WDAT : in std_logic_vector( 7 downto 0);
INT : out STD_LOGIC
);
end input_output;
architecture Behavioral of input_output is
COMPONENT temperature
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
TEMP_SPO : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic
);
END COMPONENT;
COMPONENT uart_baudgen
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
RD : IN std_logic;
WR : IN std_logic;
TX_DATA : IN std_logic_vector(7 downto 0);
RX_SERIN : IN std_logic;
TX_SEROUT : OUT std_logic;
RX_DATA : OUT std_logic_vector(7 downto 0);
RX_READY : OUT std_logic;
TX_BUSY : OUT std_logic
);
END COMPONENT;
signal IO_RD_SERIAL : std_logic;
signal IO_WR_SERIAL : std_logic;
signal RX_READY : std_logic;
signal TX_BUSY : std_logic;
signal RX_DATA : std_logic_vector(7 downto 0);
signal TEMP_DO : std_logic_vector(7 downto 0);
signal SERDAT : std_logic;
signal LCLR : std_logic;
signal C1_N, C2_N : std_logic; -- switch debounce, active low
signal RX_INT_ENABLED : std_logic;
signal TX_INT_ENABLED : std_logic;
signal TIM_INT_ENABLED : std_logic;
signal TIMER_INT : std_logic;
signal TIMER : std_logic_vector(15 downto 0);
signal CLK_COUNT : std_logic_vector(16 downto 0);
signal CLK_COUNT_EN : std_logic;
signal CLK_HALT_MSK : std_logic;
signal CLK_HALT_VAL : std_logic;
begin
tempr: temperature
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
DATA_OUT => TEMP_DO,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
uart: uart_baudgen
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
RD => IO_RD_SERIAL,
WR => IO_WR_SERIAL,
TX_DATA => IO_WDAT,
TX_SEROUT => SER_OUT,
RX_SERIN => SER_IN,
RX_DATA => RX_DATA,
RX_READY => RX_READY,
TX_BUSY => TX_BUSY
);
RST_O <= LCLR;
INT <= (RX_INT_ENABLED and RX_READY)
or (TX_INT_ENABLED and not TX_BUSY)
or (TIM_INT_ENABLED and TIMER_INT);
SERDAT <= (IO and CYC_I) when (ADR_I = X"00") else '0';
IO_RD_SERIAL <= SERDAT and not WE_I;
IO_WR_SERIAL <= SERDAT and WE_I;
ACK_O <= STB_I;
-- IO read process
--
process(ADR_I, RX_DATA, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
RX_INT_ENABLED, RX_READY, TEMP_DO, SWITCH, CLK_COUNT)
begin
case ADR_I is
when X"00" => IO_RDAT <= RX_DATA;
when X"01" => IO_RDAT <= '0'
& (TIM_INT_ENABLED and TIMER_INT)
& (TX_INT_ENABLED and not TX_BUSY)
& (RX_INT_ENABLED and RX_READY)
& '0'
& TIMER_INT
& TX_BUSY
& RX_READY;
when X"02" => IO_RDAT <= TEMP_DO;
when X"03" => IO_RDAT <= SWITCH(7 downto 0);
when X"05" => IO_RDAT <= CLK_COUNT(8 downto 1);
when others => IO_RDAT <= CLK_COUNT(16 downto 9);
end case;
end process;
-- IO write and timer process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LCLR = '1') then
LED <= X"00";
RX_INT_ENABLED <= '0';
TX_INT_ENABLED <= '0';
TIM_INT_ENABLED <= '0';
TIMER_INT <= '0';
TIMER <= X"0000";
else
if (IO = '1' and CYC_I = '1' and WE_I = '1') then
case ADR_I is
when X"00" => -- handled by uart
when X"01" => -- handled by uart
when X"02" => LED <= IO_WDAT;
when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
TX_INT_ENABLED <= IO_WDAT(1);
TIM_INT_ENABLED <= IO_WDAT(2);
when X"04" => TIMER_INT <= '0';
when X"05" => CLK_COUNT_EN <= '1';
CLK_COUNT <= '0' & X"0000";
CLK_HALT_VAL <= IO_WDAT(0);
CLK_HALT_MSK <= IO_WDAT(1);
when X"06" => CLK_COUNT_EN <= '0';
when others =>
end case;
end if;
if (TIMER = 39999) then -- 1 ms at 40 MHz
TIMER_INT <= '1';
TIMER <= X"0000";
else
TIMER <= TIMER + 1;
end if;
if (CLK_COUNT_EN = '1' and
(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
CLK_COUNT <= CLK_COUNT + 1;
end if;
end if;
end if;
end process;
-- reset debounce process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
-- switch debounce
if (SWITCH(8) = '1' or SWITCH(9) = '1') then
LCLR <= '1';
C2_N <= '0';
C1_N <= '0';
else
LCLR <= not C2_N;
C2_N <= C1_N;
C1_N <= '1';
end if;
end if;
end process;
end Behavioral;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/ds1722.vhd | 3 | 3623 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DS1722 is
Port( CLK_I: in std_logic;
RST_I: in std_logic;
DATA_IN: in std_logic_vector(7 downto 0);
DATA_OUT: out std_logic_vector(7 downto 0);
ADDRESS: in std_logic_vector(7 downto 0);
START: in std_logic;
DONE: out std_logic;
TEMP_SPI: out STD_LOGIC; -- Physical interfaes
TEMP_SPO: in STD_LOGIC;
TEMP_CE: out STD_LOGIC;
TEMP_SCLK: out STD_LOGIC
);
end DS1722;
architecture DS1722_arch of DS1722 is
signal counter : std_logic_vector(7 downto 0);
signal data_latch : std_logic_vector(7 downto 0);
type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
NEXT_TO_LAST_ONE, LAST_ONE);
signal state : BIG_STATE;
signal bit_count: INTEGER range 0 to 7;
signal Write: std_logic;
begin
-- divide CLK_I by 256
--
process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then counter <= "00000000";
else counter <= counter + "00000001";
end if;
end if;
end process;
DONE <= START when (state = LAST_ONE) else '0';
DATA_OUT <= data_latch;
Write <= ADDRESS(7);
-- convert byte commands to SPI and SPI to byte.
--
process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
state <= SET_CE;
TEMP_CE <= '0';
TEMP_SCLK <= '0';
bit_count <= 0;
elsif (counter = "11111111" and START = '1') then
case state is
when SET_CE =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= LATCH_ADD;
bit_count <= 0;
when LATCH_ADD =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= ADD_OUT_1;
data_latch <= ADDRESS;
when ADD_OUT_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= ADD_OUT_2;
TEMP_SPI <= data_latch(7);
when ADD_OUT_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= ADD_OUT_1;
bit_count <= bit_count + 1;
else
state <= DATA;
bit_count <= 0;
end if;
when DATA =>
data_latch <= DATA_IN;
TEMP_SCLK <= '0';
TEMP_CE <= '1';
if Write = '0' then
state <= READ_DATA_1;
else
state <= WRITE_DATA_1;
end if;
when WRITE_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= WRITE_DATA_2;
TEMP_SPI <= data_latch(7);
when WRITE_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= WRITE_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when READ_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= READ_DATA_2;
when READ_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & TEMP_SPO;
if bit_count < 7 then
state <= READ_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when NEXT_TO_LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= LAST_ONE;
when LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= SET_CE;
end case;
end if;
end if;
end process;
end DS1722_arch;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/cpu_engine.vhd | 1 | 12526 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_engine is
PORT( -- WISHBONE interface
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0);
DAT_O : out std_logic_vector( 7 downto 0);
RST_I : in std_logic;
ACK_I : in std_logic;
ADR_O : out std_logic_vector(15 downto 0);
CYC_O : out std_logic;
STB_O : out std_logic;
TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
WE_O : out std_logic;
INT : in std_logic;
HALT : out std_logic;
-- debug signals
--
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end cpu_engine;
architecture Behavioral of cpu_engine is
-- Unfortunately, the on-chip memory needs a clock to read data.
-- Therefore we cannot make it wishbone compliant without a speed penalty.
-- We avoid this problem by making the on-chip memory part of the CPU.
-- However, as a consequence, you cannot DMA to the on-chip memory.
--
-- The on-chip memory is 8K, so that you can run a test SoC without external
-- memory. For bigger applications, you should use external ROM and RAM and
-- remove the internal memory entirely (setting EXTERN accordingly).
--
COMPONENT memory
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CE : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
ADR : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
WDAT : IN std_logic_vector(7 downto 0);
OPC : OUT std_logic_vector(7 downto 0);
RDAT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT opcode_fetch
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
PC_OP : IN std_logic_vector(2 downto 0);
JDATA : IN std_logic_vector(15 downto 0);
RR : IN std_logic_vector(15 downto 0);
RDATA : IN std_logic_vector(7 downto 0);
PC : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT opcode_decoder
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : in std_logic_vector(7 downto 0);
OP_CYC : in cycle;
INT : in std_logic;
RRZ : in std_logic;
OP_CAT : out op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic;
HLT : out std_logic
);
END COMPONENT;
COMPONENT data_core
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
IMM : in std_logic_vector(15 downto 0); -- immediate data
RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
ADR : out std_logic_vector(15 downto 0); -- memory/IO address
MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
-- global signals
signal CE : std_logic;
signal T2 : std_logic;
-- memory signals
signal WDAT : std_logic_vector(7 downto 0);
signal RDAT : std_logic_vector(7 downto 0);
signal M_PC : std_logic_vector(15 downto 0);
signal M_OPC : std_logic_vector(7 downto 0);
-- decoder signals
--
signal D_CAT : op_category;
signal D_OPC : std_logic_vector(7 downto 0);
signal D_CYC : cycle;
signal D_PC : std_logic_vector(15 downto 0); -- debug signal
signal D_PC_OP : std_logic_vector( 2 downto 0);
signal D_LAST_M : std_logic;
signal D_IO : std_logic;
-- select signals
signal D_SX : std_logic_vector(1 downto 0);
signal D_SY : std_logic_vector(3 downto 0);
signal D_OP : std_logic_vector(4 downto 0);
signal D_SA : std_logic_vector(4 downto 0);
signal D_SMQ : std_logic;
-- write enable/select signals
signal D_WE_RR : std_logic;
signal D_WE_LL : std_logic;
signal D_WE_SP : SP_OP;
signal D_RD_O : std_logic;
signal D_WE_O : std_logic;
signal D_LOCK : std_logic; -- first cycle
signal LM_WE : std_logic;
-- core signals
--
signal C_IMM : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(15 downto 0);
signal C_CYC : cycle; -- debug signal
signal C_PC : std_logic_vector(15 downto 0); -- debug signal
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
signal C_RR : std_logic_vector(15 downto 0);
signal RRZ : std_logic;
signal OC_JD : std_logic_vector(15 downto 0);
-- select signals
signal C_SX : std_logic_vector(1 downto 0);
signal C_SY : std_logic_vector(3 downto 0);
signal C_OP : std_logic_vector(4 downto 0);
signal C_SA : std_logic_vector(4 downto 0);
signal C_SMQ : std_logic;
signal C_WE_RR : std_logic;
signal C_WE_LL : std_logic;
signal C_WE_SP : SP_OP;
signal XM_OPC : std_logic_vector(7 downto 0);
signal LM_OPC : std_logic_vector(7 downto 0);
signal LM_RDAT : std_logic_vector(7 downto 0);
signal XM_RDAT : std_logic_vector(7 downto 0);
signal C_IO : std_logic;
signal C_RD_O : std_logic;
signal C_WE_O : std_logic;
-- signals to remember, whether the previous read cycle
-- addressed internal memory or external memory
--
signal OPCS : std_logic; -- '1' if opcode from external memory
signal RDATS : std_logic; -- '1' if data from external memory
signal EXTERN : std_logic; -- '1' if opcode or data from external memory
begin
memo: memory
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
-- read in T1
PC => M_PC,
OPC => LM_OPC,
-- read or written in T2
ADR => ADR,
WR => LM_WE,
WDAT => WDAT,
RDAT => LM_RDAT
);
ocf: opcode_fetch
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
PC_OP => D_PC_OP,
JDATA => OC_JD,
RR => C_RR,
RDATA => RDAT,
PC => M_PC
);
opdec: opcode_decoder
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
OPCODE => D_OPC,
OP_CYC => D_CYC,
INT => INT,
RRZ => RRZ,
OP_CAT => D_CAT,
-- select signals
D_SX => D_SX,
D_SY => D_SY,
D_OP => D_OP,
D_SA => D_SA,
D_SMQ => D_SMQ,
-- write enable/select signal
D_WE_RR => D_WE_RR,
D_WE_LL => D_WE_LL,
D_WE_SP => D_WE_SP,
D_RD_O => D_RD_O,
D_WE_O => D_WE_O,
D_LOCK => D_LOCK,
D_IO => D_IO,
PC_OP => D_PC_OP,
LAST_M => D_LAST_M,
HLT => HALT
);
dcore: data_core
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
-- select signals
SX => C_SX,
SY => C_SY,
OP => C_OP,
PC => C_PC,
QU => C_OPC(3 downto 0),
SA => C_SA,
SMQ => C_SMQ,
-- write enable/select signal
WE_RR => C_WE_RR,
WE_LL => C_WE_LL,
WE_SP => C_WE_SP,
IMM => C_IMM,
RDAT => RDAT,
ADR => ADR,
MQ => WDAT,
Q_RR => C_RR,
Q_LL => Q_LL,
Q_SP => Q_SP
);
CE <= ACK_I or not EXTERN;
TGA_O(0) <= T2 and C_IO;
WE_O <= T2 and C_WE_O;
STB_O <= EXTERN;
CYC_O <= EXTERN;
Q_RR <= C_RR;
RRZ <= '1' when (C_RR = X"0000") else '0';
OC_JD <= M_OPC & C_IMM(7 downto 0);
Q_PC <= C_PC;
Q_OPC <= C_OPC;
Q_CYC <= C_CYC;
Q_IMM <= C_IMM;
-- select signals
Q_SX <= C_SX;
Q_SY <= C_SY;
Q_OP <= C_OP;
Q_SA <= C_SA;
Q_SMQ <= C_SMQ;
-- write enable/select signal (debug)
Q_WE_RR <= C_WE_RR;
Q_WE_LL <= C_WE_LL;
Q_WE_SP <= C_WE_SP;
DAT_O <= WDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then T2 <= '0';
else T2 <= not T2;
end if;
end if;
end process;
process(T2, M_PC, ADR, C_IO, C_RD_O, C_WE_O)
begin
if (T2 = '0') then -- opcode fetch
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
-- B EXTERN <= '1'; -- no internal memory
else -- data or I/O
EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
-- B EXTERN <= ('1' or -- no internal memory
C_IO) and (C_RD_O or C_WE_O);
end if;
end process;
-- remember whether access is to internal or to external (incl I/O) memory.
-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
OPCS <= EXTERN;
XM_OPC <= DAT_I;
else
RDATS <= EXTERN;
XM_RDAT <= DAT_I;
end if;
end if;
end process;
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
ADR_O <= M_PC when (T2 = '0') else ADR;
RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
begin
if (RST_I = '1') then
C_PC <= X"0000";
C_OPC <= X"01";
C_CYC <= M1;
C_SX <= "00";
C_SY <= "0000";
C_OP <= "00000";
C_SA <= "00000";
C_SMQ <= '0';
C_WE_RR <= '0';
C_WE_LL <= '0';
C_WE_SP <= SP_NOP;
C_IO <= '0';
C_RD_O <= '0';
C_WE_O <= '0';
LM_WE <= '0';
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
C_CYC <= D_CYC;
Q_CAT <= D_CAT;
C_PC <= D_PC;
C_OPC <= D_OPC;
C_SX <= D_SX;
C_SY <= D_SY;
C_OP <= D_OP;
C_SA <= D_SA;
C_SMQ <= D_SMQ;
C_WE_RR <= D_WE_RR;
C_WE_LL <= D_WE_LL;
C_WE_SP <= D_WE_SP;
C_IO <= D_IO;
C_RD_O <= D_RD_O;
C_WE_O <= D_WE_O;
LM_WE <= D_WE_O and not D_IO;
end if;
end process;
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
begin
if (RST_I = '1') then
D_PC <= X"0000";
D_OPC <= X"01";
D_CYC <= M1;
C_IMM <= X"FFFF";
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
if (D_LAST_M = '1') then -- D goes to M1
-- signals valid for entire opcode... PORTATO FUORI
D_OPC <= M_OPC;
D_PC <= M_PC;
D_CYC <= M1;
else
case D_CYC is
when M1 => D_CYC <= M2; -- C goes to M1
C_IMM <= X"00" & M_OPC;
when M2 => D_CYC <= M3;
C_IMM(15 downto 8) <= M_OPC;
when M3 => D_CYC <= M4;
when M4 => D_CYC <= M5;
when M5 => D_CYC <= M1;
end case;
end if;
end if;
end process;
end Behavioral;
| mit |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_never_unknown_rtl.vhd | 1 | 5190 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_never_unknown is
constant assert_name : string := "OVL_NEVER_UNKNOWN";
constant path : string := "";
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
constant cover_sanity : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_SANITY);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal qualifier_x01 : std_logic;
signal test_expr_x01 : std_logic_vector(width - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
begin
qualifier_x01 <= to_x01(qualifier);
test_expr_x01 <= to_x01(test_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
-- No 2-state assertion for this checker.
fire(0) <= '0';
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_EXPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif ((qualifier_x01 = '1') and ovl_is_x(test_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end if;
end process ovl_xcheck_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_EXPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and (cover_basic or cover_sanity)) generate
ovl_cover_p : process (clk)
variable prev_test_expr : std_logic_vector(width - 1 downto 0);
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (qualifier_x01 = '1') then
if (cover_basic) then
fire(2) <= '1';
ovl_cover_proc("qualifier covered", assert_name, path, controls, cover_count);
end if;
if (cover_sanity) then
if ((test_expr_x01 /= prev_test_expr) and not ovl_is_x(test_expr_x01) and not ovl_is_x(prev_test_expr)) then
fire(2) <= '1';
ovl_cover_proc("test_expr_change covered", assert_name, path, controls, cover_count);
end if;
prev_test_expr := test_expr_x01;
end if;
else
fire(2) <= '0';
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or not(cover_basic or cover_sanity)) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_cycle_sequence_rtl.vhd | 1 | 10459 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_cycle_sequence is
constant assert_name : string := "OVL_CYCLE_SEQUENCE";
constant path : string := "";
constant trig_on_most_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_MOST_PIPE);
constant trig_on_first_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_PIPE);
constant trig_on_first_nopipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_NOPIPE);
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal event_sequence_x01 : std_logic_vector(num_cks - 1 downto 0);
signal seq_queue : std_logic_vector(num_cks - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
begin
event_sequence_x01 <= to_x01(event_sequence);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Shared logic --
------------------------------------------------------------------------------
ovl_seq_queue_gen : if (ovl_2state_is_on(controls, property_type) or
((controls.cover_ctrl = OVL_ON) and (coverage_level_ctrl /= OVL_COVER_NONE))) generate
ovl_seq_queue_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
seq_queue <= (others => '0');
else
if (trig_on_first_nopipe) then
seq_queue(num_cks - 1) <= not(or_reduce(seq_queue(num_cks - 1 downto 1))) and
event_sequence_x01(num_cks - 1);
else
seq_queue(num_cks - 1) <= event_sequence_x01(num_cks - 1);
end if;
seq_queue(num_cks - 2 downto 0) <= seq_queue(num_cks - 1 downto 1) and
event_sequence_x01(num_cks - 2 downto 0);
end if;
end if;
end process ovl_seq_queue_p;
end generate ovl_seq_queue_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
else
fire(0) <= '0';
if (trig_on_first_pipe or trig_on_first_nopipe) then
if (and_reduce((seq_queue(num_cks -1 downto 1) and event_sequence_x01(num_cks - 2 downto 0)) or
not(seq_queue(num_cks -1 downto 1))) = '0') then
fire(0) <= '1';
ovl_error_proc("First event occured but it is not followed by the rest of the events in sequence",
severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count);
end if;
else -- trig_on_most_pipe
if ((not(seq_queue(1)) or (seq_queue(1) and event_sequence_x01(0))) = '0') then
fire(0) <= '1';
ovl_error_proc("First num_cks-1 events occured but they are not followed by the last event in sequence",
severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
end if; -- reset_n = '0'
end if; -- rising_edge(clk)
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
function init_valid_sequence_gate return std_logic_vector is
variable set : std_logic_vector(num_cks - 2 downto 0);
begin
if (num_cks > 2) then
set(num_cks - 2 downto 1) := (others => '1');
end if;
if (trig_on_most_pipe) then set(0) := '0'; else set(0) := '1'; end if;
return set;
end function init_valid_sequence_gate;
variable valid_first_event : std_logic;
variable valid_sequence : std_logic;
variable valid_last_event : std_logic;
constant valid_sequence_gate : std_logic_vector(num_cks - 2 downto 0) := init_valid_sequence_gate;
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
valid_first_event := event_sequence_x01(num_cks - 1);
valid_last_event := seq_queue(1) and event_sequence_x01(0);
valid_sequence := xor_reduce(seq_queue(num_cks - 1 downto 1) and event_sequence_x01(num_cks - 2 downto 0) and
valid_sequence_gate);
if (reset_n = '0') then
fire(1) <= '0';
else
fire(1) <= '0';
if (ovl_is_x(valid_first_event)) then
if (trig_on_most_pipe or trig_on_first_pipe) then
fire(1) <= '1';
ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
elsif (not(or_reduce(seq_queue(num_cks - 1 downto 1))) = '1') then
fire(1) <= '1';
ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
if (ovl_is_x(valid_sequence)) then
if (trig_on_first_pipe or trig_on_first_nopipe) then
fire(1) <= '1';
ovl_error_proc("Subsequent events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '1';
ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
if (trig_on_most_pipe) then
if (ovl_is_x(valid_last_event)) then
if (seq_queue(1) = '1') then
fire(1) <= '1';
ovl_error_proc("Last event in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '1';
ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
end if;
end if; -- reset_n = '0'
end if; -- rising_edge(clk)
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and cover_basic) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (((trig_on_first_pipe or trig_on_first_nopipe) and (event_sequence_x01(num_cks - 1) = '1')) or
(trig_on_most_pipe and (seq_queue(1) = '1'))) then
fire(2) <= '1';
ovl_cover_proc("sequence_trigger covered", assert_name, path, controls, cover_count);
else
fire(2) <= '0';
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or not cover_basic) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/opcode_fetch.vhd | 1 | 1454 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_fetch is
Port( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
PC_OP : in std_logic_vector( 2 downto 0);
JDATA : in std_logic_vector(15 downto 0);
RR : in std_logic_vector(15 downto 0);
RDATA : in std_logic_vector( 7 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end opcode_fetch;
architecture Behavioral of opcode_fetch is
signal LPC : std_logic_vector(15 downto 0);
signal LRET : std_logic_vector( 7 downto 0);
begin
PC <= LPC;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
LPC <= X"0000";
elsif (CE = '1' and T2 = '1') then
case PC_OP is
when PC_NEXT => LPC <= LPC + 1; -- next address
when PC_JMP => LPC <= JDATA; -- jump address
when PC_RETL => LRET <= RDATA; -- return address L
LPC <= LPC + 1;
when PC_RETH => LPC <= RDATA & LRET; -- return address H
when PC_JPRR => LPC <= RR;
when PC_WAIT =>
when others => LPC <= X"0008"; -- interrupt
end case;
end if;
end if;
end process;
end Behavioral;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/uart._baudgen.vhd | 3 | 2497 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_baudgen is
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
RD : in std_logic;
WR : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_SEROUT : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_READY : out std_logic;
TX_BUSY : out std_logic
);
end uart_baudgen;
architecture Behavioral of uart_baudgen is
COMPONENT baudgen
Generic(bg_clock_freq : integer; bg_baud_rate : integer);
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
CE_16 : OUT std_logic
);
END COMPONENT;
COMPONENT uart
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
CE_16 : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_FLAG : in std_logic;
TX_SEROUT : out std_logic;
TX_FLAGQ : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_FLAG : out std_logic
);
END COMPONENT;
signal CE_16 : std_logic;
signal RX_FLAG : std_logic;
signal RX_OLD_FLAG : std_logic;
signal TX_FLAG : std_logic;
signal TX_FLAGQ : std_logic;
signal LTX_DATA : std_logic_vector(7 downto 0);
signal LRX_READY : std_logic;
begin
RX_READY <= LRX_READY;
TX_BUSY <= TX_FLAG xor TX_FLAGQ;
baud: baudgen
GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
PORT MAP(
CLK_I => CLK_I,
RST_I => RST_I,
CE_16 => CE_16
);
urt: uart
PORT MAP( CLK_I => CLK_I,
RST_I => RST_I,
CE_16 => CE_16,
TX_DATA => LTX_DATA,
TX_FLAG => TX_FLAG,
TX_SEROUT => TX_SEROUT,
TX_FLAGQ => TX_FLAGQ,
RX_SERIN => RX_SERIN,
RX_DATA => RX_DATA,
RX_FLAG => RX_FLAG
);
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
TX_FLAG <= '0';
LTX_DATA <= X"33";
else
if (RD = '1') then -- read Rx data
LRX_READY <= '0';
end if;
if (WR = '1') then -- write Tx data
TX_FLAG <= not TX_FLAG;
LTX_DATA <= TX_DATA;
end if;
if (RX_FLAG /= RX_OLD_FLAG) then
LRX_READY <= '1';
end if;
RX_OLD_FLAG <= RX_FLAG;
end if;
end if;
end process;
end Behavioral;
| mit |
bluemurder/chaotic-rngs | rng07-vhdl/chaoticMap.vhd | 2 | 1546 | -- This block describes the chaotic map used for the random generator --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.randgen_package.all;
entity chaoticMap is
Port ( clk : in std_logic;
reset : in std_logic;
output : out std_logic);
end chaoticMap;
architecture Behavioral of chaoticMap is
-- Supposing 2 integer bits and two's complement, the constants
-- correspond to zero, one and minus one values
constant zero : signed(N_BIT-1 downto 0) := (others => '0');
constant one : signed(N_BIT-1 downto 0) := (N_BIT-2 => '1', others => '0');
constant minusone : signed(N_BIT-1 downto 0) := (N_BIT-1 => '1', N_BIT-2 => '1', others => '0');
-- Stores the current state
signal reg : signed(N_BIT-1 downto 0);
begin
-- update map
proc_map: process(clk,reset)
begin
if reset = '0' then
if rising_edge(clk) then
-- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3)
if (reg < zero) then
-- reg = 1.875 * reg + 1
reg <= (( reg(N_BIT-2 downto 0) & '0' ) - ( "111" & reg(N_BIT-1 downto 3) )) + one;
else
-- reg = 1.875 * reg - 1
reg <= (( reg(N_BIT-2 downto 0)&'0' ) - ( "000" & reg(N_BIT-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= X0;
end if;
end process;
output <= reg(N_BIT-1);
end Behavioral;
| mit |
bluemurder/chaotic-rngs | rng02-vhdl/CaosAlAl.vhd | 1 | 1808 | ----------------------------------------------------------------------------------
-- Company: University of Genova
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CaosAlAl is
generic (nbit : integer := 32);
Port ( ck : in STD_LOGIC;
res : in STD_LOGIC;
out0 : out STD_LOGIC);
end CaosAlAl;
architecture Behavioral of CaosAlAl is
signal reg : signed(nbit-1 downto 0);
-- Supposing 2 integer bits and two's complement, one and minus one values
constant zero : signed(nbit-1 downto 0) := "00000000000000000000000000000000";
constant one : signed(nbit-1 downto 0) := "01000000000000000000000000000000";
constant minusone : signed(nbit-1 downto 0) := "11000000000000000000000000000000";
constant x0 : signed(nbit-1 downto 0) := "00100000000000000000000000000000";
begin
out0 <= reg(nbit-1);
main:process(ck,res)
begin
if res = '0' then
if (ck'event and ck ='1') then
if (reg < zero) then
reg <= (( reg(nbit-2 downto 0) & '0' ) - ( "111" & reg(nbit-1 downto 3) )) + one;
else
reg <= (( reg(nbit-2 downto 0)&'0' ) - ( "000" & reg(nbit-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= x0;
end if;
end process;
end Behavioral; | mit |
bluemurder/chaotic-rngs | rng06-vhdl/test_randgen.vhd | 2 | 1675 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
LIBRARY std;
use STD.textio.all;
use work.randgen_package.all;
ENTITY test_randgen IS
END test_randgen;
ARCHITECTURE behavior OF test_randgen IS
-- Component Declaration for the Unit Under Test (UUT)
component randgen is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
ready : out STD_LOGIC;
output : out STD_LOGIC);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal output : std_logic;
signal ready : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: randgen PORT MAP (
clk => clk,
reset => reset,
ready => ready,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <='0';
-- write a single line
wait;
end process;
-- Write bigregister process
write_file: process (clk) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_output_line : LINE;
begin
if rising_edge(clk) then
if ready = '1' and reset = '0' then
write(my_output_line,output);
writeline(my_output, my_output_line);
end if;
end if;
end process write_file;
END;
| mit |
bluemurder/chaotic-rngs | rng08-vhdl/testCaosComb.vhd | 1 | 2587 | --------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 16:27:59 10/06/2011
-- Design Name:
-- Module Name: testCaosComb.vhd
-- Project Name: Caos
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CaosComb
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
LIBRARY std;
use STD.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testCaosComb IS
END testCaosComb;
ARCHITECTURE behavior OF testCaosComb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CaosComb
PORT(
res : IN std_logic;
out0 : OUT std_logic
);
END COMPONENT;
--Inputs
signal ck : std_logic := '0';
signal res : std_logic := '0';
--Outputs
signal out0 : std_logic;
constant ck_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CaosComb PORT MAP (
res => res,
out0 => out0
);
-- Clock process definitions
ck_process :process
begin
ck <= '0';
wait for ck_period/2;
ck <= '1';
wait for ck_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
res <= '1';
wait for 100 ns;
res<='0';
-- write a single line
wait;
end process;
-- Write bigregister process
write_file: process (ck) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_output_line : LINE;
begin
if rising_edge(ck) then
if res = '0' then
write(my_output_line,out0);
writeline(my_output, my_output_line);
end if;
end if;
end process write_file;
END;
| mit |
bluemurder/chaotic-rngs | rng08-vhdl/test.vhd | 1 | 3060 | --------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 15:44:18 09/19/2011
-- Design Name:
-- Module Name: test.vhd
-- Project Name: NewCaos
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: newCaoticGen2
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
LIBRARY std;
USE std.textio.all;
use ieee.std_logic_textio.all;
--use ieee.Signed_to_Bit.all;
use work.variable_Caos.all ;
use STD.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT newCaoticGen2
PORT(
Clk : IN std_logic;
reset : IN std_logic;
X_out : OUT signed(numbit-1 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal X_out : signed(numbit-1 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: newCaoticGen2 PORT MAP (
Clk => Clk,
reset => reset,
X_out => X_out
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*100;
reset <='1';
wait for Clk_period;
reset <='0';
wait for Clk_period*100;
wait;
end process;
process (clk)
variable wrbuf :line;
begin
if (Clk'event and Clk ='1') then
write(wrbuf, conv_std_logic_vector( X_out,numBit));
-- write(wrbuf, string'("; lfsr_2: ")); write(wrbuf, conv_integer(lfsr_2));
writeline(output, wrbuf);
end if;
end process;
-- Write file process
write_file: process (Clk) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_line : LINE;
variable my_output_line : LINE;
begin
if rising_edge(Clk) then
write(my_output_line,X_out(numBit-1));--std_logic_vector(X_out));
writeline(my_output, my_output_line);
end if;
end process write_file;
END;
| mit |
bluemurder/chaotic-rngs | rng06-vhdl/vonNeumannCorrector.vhd | 2 | 1603 | -- This block performs a Von Neumann correction --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.randgen_package.all;
entity vonNeumannCorrector is
Port ( clk : in std_logic;
reset : in std_logic;
data_in : in std_logic;
ready_in : in std_logic;
data_out : out std_logic;
ready_out : out std_logic);
end vonNeumannCorrector;
architecture Behavioral of vonNeumannCorrector is
signal counter : integer range 0 to 1;
signal reg : std_logic_vector(1 downto 0);
signal reg_xor : std_logic;
begin
proc_load_register : process(clk,reset)
begin
if reset = '1' then
reg <= (others => '0');
elsif rising_edge(clk) and ready_in = '1' then
reg(counter) <= data_in;
end if;
end process;
proc_counter : process(clk,reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clk) and ready_in = '1' then
if counter = 0 then
counter <= 1;
else
counter <= 0;
end if;
end if;
end process;
-- Xor between the two bits of reg
reg_xor <= reg(0) xor reg(1);
-- If the block is disabled, data_out equals data_in else
-- it is the first bit of the sequence of two bits
data_out <= data_in when ENABLE_VON_NEUMANN = false else
reg(0);
ready_out <= ready_in when ENABLE_VON_NEUMANN = false else
'1' when (counter = 1 and reg_xor = '1') else
'0';
end Behavioral;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/a27f5e107e0af35c/ila_0_sim_netlist.vhdl | 1 | 4901485 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/f5a61c81241cd760/srio_gen2_0_stub.vhdl | 1 | 6142 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Oct 18 11:58:34 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.vhdl
-- Design : srio_gen2_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
sys_clkp : in STD_LOGIC;
sys_clkn : in STD_LOGIC;
sys_rst : in STD_LOGIC;
log_clk_out : out STD_LOGIC;
phy_clk_out : out STD_LOGIC;
gt_clk_out : out STD_LOGIC;
gt_pcs_clk_out : out STD_LOGIC;
drpclk_out : out STD_LOGIC;
refclk_out : out STD_LOGIC;
clk_lock_out : out STD_LOGIC;
cfg_rst_out : out STD_LOGIC;
log_rst_out : out STD_LOGIC;
buf_rst_out : out STD_LOGIC;
phy_rst_out : out STD_LOGIC;
gt_pcs_rst_out : out STD_LOGIC;
gt0_qpll_clk_out : out STD_LOGIC;
gt0_qpll_out_refclk_out : out STD_LOGIC;
srio_rxn0 : in STD_LOGIC;
srio_rxp0 : in STD_LOGIC;
srio_txn0 : out STD_LOGIC;
srio_txp0 : out STD_LOGIC;
s_axis_iotx_tvalid : in STD_LOGIC;
s_axis_iotx_tready : out STD_LOGIC;
s_axis_iotx_tlast : in STD_LOGIC;
s_axis_iotx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_iotx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_iotx_tuser : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_iorx_tvalid : out STD_LOGIC;
m_axis_iorx_tready : in STD_LOGIC;
m_axis_iorx_tlast : out STD_LOGIC;
m_axis_iorx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_iorx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_iorx_tuser : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rst : in STD_LOGIC;
s_axi_maintr_awvalid : in STD_LOGIC;
s_axi_maintr_awready : out STD_LOGIC;
s_axi_maintr_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_wvalid : in STD_LOGIC;
s_axi_maintr_wready : out STD_LOGIC;
s_axi_maintr_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_bvalid : out STD_LOGIC;
s_axi_maintr_bready : in STD_LOGIC;
s_axi_maintr_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_maintr_arvalid : in STD_LOGIC;
s_axi_maintr_arready : out STD_LOGIC;
s_axi_maintr_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rvalid : out STD_LOGIC;
s_axi_maintr_rready : in STD_LOGIC;
s_axi_maintr_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
sim_train_en : in STD_LOGIC;
force_reinit : in STD_LOGIC;
phy_mce : in STD_LOGIC;
phy_link_reset : in STD_LOGIC;
phy_rcvd_mce : out STD_LOGIC;
phy_rcvd_link_reset : out STD_LOGIC;
phy_debug : out STD_LOGIC_VECTOR ( 223 downto 0 );
gtrx_disperr_or : out STD_LOGIC;
gtrx_notintable_or : out STD_LOGIC;
port_error : out STD_LOGIC;
port_timeout : out STD_LOGIC_VECTOR ( 23 downto 0 );
srio_host : out STD_LOGIC;
port_decode_error : out STD_LOGIC;
deviceid : out STD_LOGIC_VECTOR ( 15 downto 0 );
idle2_selected : out STD_LOGIC;
phy_lcl_master_enable_out : out STD_LOGIC;
buf_lcl_response_only_out : out STD_LOGIC;
buf_lcl_tx_flow_control_out : out STD_LOGIC;
buf_lcl_phy_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_next_fm_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_last_ack_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_rewind_out : out STD_LOGIC;
phy_lcl_phy_rcvd_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_maint_only_out : out STD_LOGIC;
port_initialized : out STD_LOGIC;
link_initialized : out STD_LOGIC;
idle_selected : out STD_LOGIC;
mode_1x : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "srio_gen2_v4_0_5,Vivado 2015.1.0";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/33e25e2781fab1df/srio_gen2_0_sim_netlist.vhdl | 1 | 8383546 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/678f058b09cf6220/srio_gen2_0_sim_netlist.vhdl | 1 | 8140888 | null | mit |
superboy0712/MIPS | MIPS_main_controller_sincle_cycle_redesign.vhd | 1 | 6128 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:30:31 10/19/2014
-- Design Name:
-- Module Name: MIPS_main_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MIPS_main_controller is
Port ( proc_en : in std_logic;
clk : in std_logic;
Opcode : in STD_LOGIC_VECTOR (31 downto 26);
PC_en : out STD_LOGIC;
IF_en : out STD_LOGIC; -- instruction register enable
ALUOp : out STD_LOGIC_VECTOR (1 downto 0);
RegDst : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
Branch : out STD_LOGIC;
Jump : out STD_LOGIC;
RF_WriteSrc : OUT std_logic
);
end MIPS_main_controller;
architecture Behavioral of MIPS_main_controller is
type state_type is (IDLE, IFCH, ID, EX, MEM, WB);
signal state : state_type := IDLE;
begin
decoder_and_output : process(state, Opcode) -- using asynchronous or synchronous ? the control signals for function units are mostly synchronous
variable PC_en_tmp, IF_en_tmp, regdst_tmp, alusrc_tmp, memtoreg_tmp, regwrite_tmp, memread_tmp, memwrite_tmp, branch_tmp, jump_tmp, rf_writesrc_tmp : std_logic := '0';
variable aluop_tmp : std_logic_vector ( 1 downto 0 ) := "00";
begin
decode : case Opcode is
-- R format
when "000000" =>
regdst_tmp := '1'; alusrc_tmp := '0'; memtoreg_tmp := '0';
regwrite_tmp := '1'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '0'; jump_tmp := '0';
aluop_tmp := "10"; rf_writesrc_tmp := '0';
-- LW
when "100011" =>
regdst_tmp := '0'; alusrc_tmp := '1'; memtoreg_tmp := '1';
regwrite_tmp := '1'; memread_tmp := '1'; memwrite_tmp := '0';
branch_tmp := '0'; jump_tmp := '0'; rf_writesrc_tmp := '0';
aluop_tmp := "00";
-- SW
when "101011" =>
regdst_tmp := '-'; alusrc_tmp := '1'; memtoreg_tmp := '-';
regwrite_tmp := '0'; memread_tmp := '0'; memwrite_tmp := '1';
branch_tmp := '0'; jump_tmp := '0'; rf_writesrc_tmp := '0';
aluop_tmp := "00";
-- BEQ
when "000100" =>
regdst_tmp := '-'; alusrc_tmp := '0'; memtoreg_tmp := '-';
regwrite_tmp := '0'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '1'; jump_tmp := '0'; rf_writesrc_tmp := '0';
aluop_tmp := "01";
-- JUMP
when "000010" =>
regdst_tmp := '-'; alusrc_tmp := '-'; memtoreg_tmp := '-';
regwrite_tmp := '0'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '-'; jump_tmp := '1'; rf_writesrc_tmp := '0';
aluop_tmp := "--";
-- LUI
when "001111" =>
regdst_tmp := '-'; alusrc_tmp := '-'; memtoreg_tmp := '-';
regwrite_tmp := '1'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '0'; jump_tmp := '0'; -- PC add 1
rf_writesrc_tmp := '1';
aluop_tmp := "--";
-- EXCEPTION
when others =>
regdst_tmp := '0'; alusrc_tmp := '0'; memtoreg_tmp := '0';
regwrite_tmp := '0'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '0'; jump_tmp := '0'; rf_writesrc_tmp := '0';
aluop_tmp := "00";
end case;
output : case state is
when IDLE =>
PC_en <= '0';
IF_en <= '0';
regdst <= '0';
alusrc <= '0';
memtoreg <= '0';
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= '0';
Jump <= '0';
RF_WriteSrc <= '0';
ALUOp <= "00";
when IFCH =>
PC_en <= '0';
IF_en <= '1';
regdst <= '0';
alusrc <= '0';
memtoreg <= '0';
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= '0';
Jump <= '0';
RF_WriteSrc <= '0';
ALUOp <= "00";
when ID =>
PC_en <= '0';
IF_en <= '0';
regdst <= regdst_tmp;
alusrc <= alusrc_tmp;
memtoreg <= memtoreg_tmp;
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= branch_tmp;
Jump <= jump_tmp;
RF_WriteSrc <= rf_writesrc_tmp;
ALUOp <= "00";
when EX =>
PC_en <= '0';
IF_en <= '0';
regdst <= regdst_tmp;
alusrc <= alusrc_tmp;
memtoreg <= memtoreg_tmp;
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= branch_tmp;
Jump <= jump_tmp;
RF_WriteSrc <= rf_writesrc_tmp;
ALUOp <= aluop_tmp;
when MEM =>
PC_en <= '0';
IF_en <= '0';
regdst <= regdst_tmp;
alusrc <= alusrc_tmp;
memtoreg <= memtoreg_tmp;
regwrite <= '0';
memread <= memread_tmp;
memwrite <= memwrite_tmp;
branch <= branch_tmp;
Jump <= jump_tmp;
RF_WriteSrc <= rf_writesrc_tmp;
ALUOp <= aluop_tmp;
when WB =>
PC_en <= '1';
IF_en <= '0';
regdst <= regdst_tmp;
alusrc <= alusrc_tmp;
memtoreg <= memtoreg_tmp;
regwrite <= regwrite_tmp;
memread <= memread_tmp;
memwrite <= memwrite_tmp;
branch <= branch_tmp;
Jump <= jump_tmp;
RF_WriteSrc <= rf_writesrc_tmp;
ALUOp <= aluop_tmp;
when others =>
PC_en <= '0';
IF_en <= '0';
regdst <= '0';
alusrc <= '0';
memtoreg <= '0';
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= '0';
Jump <= '0';
RF_WriteSrc <= '0';
ALUOp <= "00";
end case;
end process;
next_state: process(clk)
begin
if rising_edge(clk) then
if(proc_en = '0') then state <= IDLE;
elsif proc_en = '1' then
if state = IDLE then state <= IFCH;
elsif state = IFCH then state <= ID;
elsif state = ID then state <= EX;
elsif state = EX then state <= MEM;
elsif state = MEM then state <= WB;
elsif state = WB then state <= IFCH; -- don't forget
end if;
end if;
end if;
end process;
end Behavioral;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/7b44e6d6f6ec9fee/dbg_ila_stub.vhdl | 1 | 2721 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 25 13:52:36 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[0:0],probe21[31:0],probe22[31:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
| mit |
superboy0712/MIPS | pipeline files/MEMWB_register.vhd | 1 | 1883 | library ieee;
use ieee.std_logic_1164.all;
entity EXMEM_register is
port(Clk, reset : in std_logic;
ALU_ressult_i, data_mem_i: in std_logic_vector(31 downto 0);
ALU_ressult_o, data_mem_o: out std_logic_vector(31 downto 0);
register_address_i: in std_logic_vector(4 downto 0);
register_address_o: out std_logic_vector(4 downto 0);
MemtoReg_i, RegWrite_i: in std_logic;
MemtoReg_o, RegWrite_o: out std_logic);
end EXMEM_register;
architecture EXMEM_register_a of EXMEM_register is
type tmp_array is array (0 to 1) of std_logic_vector(31 downto 0);
type tmp_array_short is array (0 to 1) of std_logic_vector(4 downto 0);
type tmp_array_logic is array (0 to 1) of std_logic;
signal data_mem_tmp, ALU_ressult_tmp: tmp_array;
signal register_address_tmp: tmp_array_short;
signal MemtoReg_tmp, RegWrite_tmp: tmp_array_logic;
begin
process (Clk)
begin
if (reset = '1') then
data_mem_tmp(1) <= (others => '0');
register_address_tmp(1) <= (others => '0');
ALU_ressult_tmp(1) <= (others => '0');
MemtoReg_tmp(1) <= '0';
RegWrite_tmp(1) <= '0';
elsif (rising_edge(clk)) then
data_mem_tmp(0) <= data_mem_tmp(1);
register_address_tmp(0) <= register_address_tmp(1);
ALU_ressult_tmp(0) <= ALU_ressult_tmp(1);
MemtoReg_tmp(0) <= MemtoReg_tmp(1);
RegWrite_tmp(0) <= RegWrite_tmp(1);
data_mem_tmp(1) <= data_mem_i;
register_address_tmp(1) <= register_address_i;
ALU_ressult_tmp(1) <= ALU_ressult_i;
MemtoReg_tmp(1) <= MemtoReg_i;
RegWrite_tmp(1) <= RegWrite_i;
end if;
end process;
data_mem_o <= data_mem_tmp(0);
register_address_o <= register_address_tmp(0);
ALU_ressult_o <= ALU_ressult_tmp(0);
MemtoReg_o <= MemtoReg_tmp(0);
RegWrite_o <= RegWrite_tmp(0);
end EXMEM_register_a; | mit |
GOOD-Stuff/srio_test | srio_test.ip_user_files/ip/srio_gen2_0/srio_gen2_0_stub.vhdl | 1 | 6019 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:31:45 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/srio_gen2_0/srio_gen2_0_stub.vhdl
-- Design : srio_gen2_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity srio_gen2_0 is
Port (
sys_clkp : in STD_LOGIC;
sys_clkn : in STD_LOGIC;
sys_rst : in STD_LOGIC;
log_clk_out : out STD_LOGIC;
phy_clk_out : out STD_LOGIC;
gt_clk_out : out STD_LOGIC;
gt_pcs_clk_out : out STD_LOGIC;
drpclk_out : out STD_LOGIC;
refclk_out : out STD_LOGIC;
clk_lock_out : out STD_LOGIC;
cfg_rst_out : out STD_LOGIC;
log_rst_out : out STD_LOGIC;
buf_rst_out : out STD_LOGIC;
phy_rst_out : out STD_LOGIC;
gt_pcs_rst_out : out STD_LOGIC;
gt0_qpll_clk_out : out STD_LOGIC;
gt0_qpll_out_refclk_out : out STD_LOGIC;
srio_rxn0 : in STD_LOGIC;
srio_rxp0 : in STD_LOGIC;
srio_txn0 : out STD_LOGIC;
srio_txp0 : out STD_LOGIC;
s_axis_iotx_tvalid : in STD_LOGIC;
s_axis_iotx_tready : out STD_LOGIC;
s_axis_iotx_tlast : in STD_LOGIC;
s_axis_iotx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_iotx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_iotx_tuser : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_iorx_tvalid : out STD_LOGIC;
m_axis_iorx_tready : in STD_LOGIC;
m_axis_iorx_tlast : out STD_LOGIC;
m_axis_iorx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_iorx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_iorx_tuser : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rst : in STD_LOGIC;
s_axi_maintr_awvalid : in STD_LOGIC;
s_axi_maintr_awready : out STD_LOGIC;
s_axi_maintr_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_wvalid : in STD_LOGIC;
s_axi_maintr_wready : out STD_LOGIC;
s_axi_maintr_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_bvalid : out STD_LOGIC;
s_axi_maintr_bready : in STD_LOGIC;
s_axi_maintr_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_maintr_arvalid : in STD_LOGIC;
s_axi_maintr_arready : out STD_LOGIC;
s_axi_maintr_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rvalid : out STD_LOGIC;
s_axi_maintr_rready : in STD_LOGIC;
s_axi_maintr_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
sim_train_en : in STD_LOGIC;
force_reinit : in STD_LOGIC;
phy_mce : in STD_LOGIC;
phy_link_reset : in STD_LOGIC;
phy_rcvd_mce : out STD_LOGIC;
phy_rcvd_link_reset : out STD_LOGIC;
phy_debug : out STD_LOGIC_VECTOR ( 223 downto 0 );
gtrx_disperr_or : out STD_LOGIC;
gtrx_notintable_or : out STD_LOGIC;
port_error : out STD_LOGIC;
port_timeout : out STD_LOGIC_VECTOR ( 23 downto 0 );
srio_host : out STD_LOGIC;
port_decode_error : out STD_LOGIC;
deviceid : out STD_LOGIC_VECTOR ( 15 downto 0 );
idle2_selected : out STD_LOGIC;
phy_lcl_master_enable_out : out STD_LOGIC;
buf_lcl_response_only_out : out STD_LOGIC;
buf_lcl_tx_flow_control_out : out STD_LOGIC;
buf_lcl_phy_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_next_fm_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_last_ack_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_rewind_out : out STD_LOGIC;
phy_lcl_phy_rcvd_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_maint_only_out : out STD_LOGIC;
port_initialized : out STD_LOGIC;
link_initialized : out STD_LOGIC;
idle_selected : out STD_LOGIC;
mode_1x : out STD_LOGIC
);
end srio_gen2_0;
architecture stub of srio_gen2_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "srio_gen2_v4_0_5,Vivado 2015.1.0";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/4768f0820c8fb678/fifo_generator_rx_inst_stub.vhdl | 1 | 1927 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 13:10:43 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[9:0],wr_data_count[8:0],prog_full,prog_empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_2,Vivado 2016.3";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/335f9682d9b26dcb/ila_0_sim_netlist.vhdl | 1 | 3666186 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/4768f0820c8fb678/fifo_generator_rx_inst_sim_netlist.vhdl | 1 | 309175 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 13:10:43 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => dout(34 downto 27),
DOBDO(23 downto 16) => dout(25 downto 18),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => dout(35),
DOPBDOP(2) => dout(26),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\,
DOBDO(30 downto 24) => dout(27 downto 21),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\,
DOBDO(22 downto 16) => dout(20 downto 14),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14 downto 8) => dout(13 downto 7),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6 downto 0) => dout(6 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
comp1 : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0020"
)
port map (
I0 => comp2,
I1 => \out\,
I2 => wr_en,
I3 => wr_rst_busy,
I4 => comp1,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair8";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => \plusOp__0\(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
begin
\rd_dc_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0),
Q => rd_data_count(0)
);
\rd_dc_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1),
Q => rd_data_count(1)
);
\rd_dc_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2),
Q => rd_data_count(2)
);
\rd_dc_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3),
Q => rd_data_count(3)
);
\rd_dc_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4),
Q => rd_data_count(4)
);
\rd_dc_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5),
Q => rd_data_count(5)
);
\rd_dc_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6),
Q => rd_data_count(6)
);
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7),
Q => rd_data_count(7)
);
\rd_dc_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8),
Q => rd_data_count(8)
);
\rd_dc_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9),
Q => rd_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
port (
prog_empty : out STD_LOGIC;
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
signal \gdiff.diff_pntr_pad_reg_n_0_[10]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[1]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[2]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[3]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[4]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[5]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[6]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[7]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[8]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[9]\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_1_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_3_n_0\ : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
begin
prog_empty <= \^prog_empty\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => \gdiff.diff_pntr_pad_reg_n_0_[10]\
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => \gdiff.diff_pntr_pad_reg_n_0_[1]\
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => \gdiff.diff_pntr_pad_reg_n_0_[2]\
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => \gdiff.diff_pntr_pad_reg_n_0_[3]\
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => \gdiff.diff_pntr_pad_reg_n_0_[4]\
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => \gdiff.diff_pntr_pad_reg_n_0_[5]\
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => \gdiff.diff_pntr_pad_reg_n_0_[6]\
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => \gdiff.diff_pntr_pad_reg_n_0_[7]\
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => \gdiff.diff_pntr_pad_reg_n_0_[8]\
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => \gdiff.diff_pntr_pad_reg_n_0_[9]\
);
\gpe1.prog_empty_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8B8BBB8B"
)
port map (
I0 => \^prog_empty\,
I1 => \out\,
I2 => \gpe1.prog_empty_i_i_2_n_0\,
I3 => \gpe1.prog_empty_i_i_3_n_0\,
I4 => \gdiff.diff_pntr_pad_reg_n_0_[7]\,
O => \gpe1.prog_empty_i_i_1_n_0\
);
\gpe1.prog_empty_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[9]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[10]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[8]\,
O => \gpe1.prog_empty_i_i_2_n_0\
);
\gpe1.prog_empty_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7FFFFFFFFFFF"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[3]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[4]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[6]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[2]\,
I4 => \gdiff.diff_pntr_pad_reg_n_0_[1]\,
I5 => \gdiff.diff_pntr_pad_reg_n_0_[5]\,
O => \gpe1.prog_empty_i_i_3_n_0\
);
\gpe1.prog_empty_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gpe1.prog_empty_i_i_1_n_0\,
PRE => AR(0),
Q => \^prog_empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
\wr_data_count_i_reg[9]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gdiff.diff_pntr_pad_reg[10]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\wr_data_count_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gdiff.diff_pntr_pad_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gdiff.diff_pntr_pad_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d1_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_1\ : label is "soft_lutpair13";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gic0.gc0.count_d1_reg[9]_0\(9 downto 0) <= \^gic0.gc0.count_d1_reg[9]_0\(9 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(4),
O => \plusOp__1\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(4),
I5 => \^gic0.gc0.count_d1_reg[9]_0\(5),
O => \plusOp__1\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => \^gic0.gc0.count_d1_reg[9]_0\(6),
O => \plusOp__1\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B4"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(7),
O => \plusOp__1\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => \^gic0.gc0.count_d1_reg[9]_0\(7),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(8),
O => \plusOp__1\(8)
);
\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(8),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(7),
I2 => \gic0.gc0.count[9]_i_2_n_0\,
I3 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(9),
O => \plusOp__1\(9)
);
\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(5),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I5 => \^gic0.gc0.count_d1_reg[9]_0\(4),
O => \gic0.gc0.count[9]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(3),
Q => \^q\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(4),
Q => \^q\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(5),
Q => \^q\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(6),
Q => \^q\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(7),
Q => \^q\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(8),
Q => \^q\(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(9),
Q => p_13_out(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^gic0.gc0.count_d1_reg[9]_0\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^gic0.gc0.count_d1_reg[9]_0\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^gic0.gc0.count_d1_reg[9]_0\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^gic0.gc0.count_d1_reg[9]_0\(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(4),
Q => \^gic0.gc0.count_d1_reg[9]_0\(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(5),
Q => \^gic0.gc0.count_d1_reg[9]_0\(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(6),
Q => \^gic0.gc0.count_d1_reg[9]_0\(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(7),
Q => \^gic0.gc0.count_d1_reg[9]_0\(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(8),
Q => \^gic0.gc0.count_d1_reg[9]_0\(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(9),
Q => \^gic0.gc0.count_d1_reg[9]_0\(9)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
I2 => RD_PNTR_WR(8),
I3 => \^q\(8),
O => v1_reg(0)
);
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I1 => RD_PNTR_WR(7),
O => \wr_data_count_i_reg[7]\(3)
);
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => RD_PNTR_WR(6),
O => \wr_data_count_i_reg[7]\(2)
);
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I1 => RD_PNTR_WR(5),
O => \wr_data_count_i_reg[7]\(1)
);
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => RD_PNTR_WR(4),
O => \wr_data_count_i_reg[7]\(0)
);
\minusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I1 => RD_PNTR_WR(9),
O => \wr_data_count_i_reg[9]\(1)
);
\minusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => RD_PNTR_WR(8),
O => \wr_data_count_i_reg[9]\(0)
);
minusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I1 => RD_PNTR_WR(3),
O => S(3)
);
minusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => RD_PNTR_WR(2),
O => S(2)
);
minusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => RD_PNTR_WR(1),
O => S(1)
);
minusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => RD_PNTR_WR(0),
O => S(0)
);
\plusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => RD_PNTR_WR(7),
O => \gdiff.diff_pntr_pad_reg[8]\(3)
);
\plusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => RD_PNTR_WR(6),
O => \gdiff.diff_pntr_pad_reg[8]\(2)
);
\plusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => RD_PNTR_WR(5),
O => \gdiff.diff_pntr_pad_reg[8]\(1)
);
\plusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => RD_PNTR_WR(4),
O => \gdiff.diff_pntr_pad_reg[8]\(0)
);
\plusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
O => \gdiff.diff_pntr_pad_reg[10]\(1)
);
\plusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => RD_PNTR_WR(8),
O => \gdiff.diff_pntr_pad_reg[10]\(0)
);
plusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => RD_PNTR_WR(3),
O => \gdiff.diff_pntr_pad_reg[4]\(3)
);
plusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => RD_PNTR_WR(2),
O => \gdiff.diff_pntr_pad_reg[4]\(2)
);
plusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => RD_PNTR_WR(1),
O => \gdiff.diff_pntr_pad_reg[4]\(1)
);
plusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => RD_PNTR_WR(0),
O => \gdiff.diff_pntr_pad_reg[4]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
port (
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
signal \minusOp_carry__0_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_n_1\ : STD_LOGIC;
signal \minusOp_carry__0_n_2\ : STD_LOGIC;
signal \minusOp_carry__0_n_3\ : STD_LOGIC;
signal \minusOp_carry__0_n_4\ : STD_LOGIC;
signal \minusOp_carry__0_n_5\ : STD_LOGIC;
signal \minusOp_carry__0_n_6\ : STD_LOGIC;
signal \minusOp_carry__0_n_7\ : STD_LOGIC;
signal \minusOp_carry__1_n_3\ : STD_LOGIC;
signal \minusOp_carry__1_n_6\ : STD_LOGIC;
signal \minusOp_carry__1_n_7\ : STD_LOGIC;
signal minusOp_carry_n_0 : STD_LOGIC;
signal minusOp_carry_n_1 : STD_LOGIC;
signal minusOp_carry_n_2 : STD_LOGIC;
signal minusOp_carry_n_3 : STD_LOGIC;
signal minusOp_carry_n_4 : STD_LOGIC;
signal minusOp_carry_n_5 : STD_LOGIC;
signal minusOp_carry_n_6 : STD_LOGIC;
signal NLW_minusOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_minusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
minusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => minusOp_carry_n_0,
CO(2) => minusOp_carry_n_1,
CO(1) => minusOp_carry_n_2,
CO(0) => minusOp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[8]\(3 downto 0),
O(3) => minusOp_carry_n_4,
O(2) => minusOp_carry_n_5,
O(1) => minusOp_carry_n_6,
O(0) => NLW_minusOp_carry_O_UNCONNECTED(0),
S(3 downto 0) => S(3 downto 0)
);
\minusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => minusOp_carry_n_0,
CO(3) => \minusOp_carry__0_n_0\,
CO(2) => \minusOp_carry__0_n_1\,
CO(1) => \minusOp_carry__0_n_2\,
CO(0) => \minusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[8]\(7 downto 4),
O(3) => \minusOp_carry__0_n_4\,
O(2) => \minusOp_carry__0_n_5\,
O(1) => \minusOp_carry__0_n_6\,
O(0) => \minusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d2_reg[7]\(3 downto 0)
);
\minusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \minusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \minusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \gic0.gc0.count_d2_reg[8]\(8),
O(3 downto 2) => \NLW_minusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \minusOp_carry__1_n_6\,
O(0) => \minusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d2_reg[9]\(1 downto 0)
);
\wr_data_count_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_6,
Q => wr_data_count(0)
);
\wr_data_count_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_5,
Q => wr_data_count(1)
);
\wr_data_count_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_4,
Q => wr_data_count(2)
);
\wr_data_count_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_7\,
Q => wr_data_count(3)
);
\wr_data_count_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_6\,
Q => wr_data_count(4)
);
\wr_data_count_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_5\,
Q => wr_data_count(5)
);
\wr_data_count_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_4\,
Q => wr_data_count(6)
);
\wr_data_count_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_7\,
Q => wr_data_count(7)
);
\wr_data_count_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_6\,
Q => wr_data_count(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
port (
prog_full : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gpf1.prog_full_i_i_1_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_2_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_3_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_1\ : STD_LOGIC;
signal \plusOp_carry__0_n_2\ : STD_LOGIC;
signal \plusOp_carry__0_n_3\ : STD_LOGIC;
signal \plusOp_carry__0_n_4\ : STD_LOGIC;
signal \plusOp_carry__0_n_5\ : STD_LOGIC;
signal \plusOp_carry__0_n_6\ : STD_LOGIC;
signal \plusOp_carry__0_n_7\ : STD_LOGIC;
signal \plusOp_carry__1_n_3\ : STD_LOGIC;
signal \plusOp_carry__1_n_6\ : STD_LOGIC;
signal \plusOp_carry__1_n_7\ : STD_LOGIC;
signal plusOp_carry_n_0 : STD_LOGIC;
signal plusOp_carry_n_1 : STD_LOGIC;
signal plusOp_carry_n_2 : STD_LOGIC;
signal plusOp_carry_n_3 : STD_LOGIC;
signal plusOp_carry_n_4 : STD_LOGIC;
signal plusOp_carry_n_5 : STD_LOGIC;
signal plusOp_carry_n_6 : STD_LOGIC;
signal plusOp_carry_n_7 : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal \NLW_plusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_6\,
Q => diff_pntr(9)
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_7,
Q => diff_pntr(0)
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_6,
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_5,
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_4,
Q => diff_pntr(3)
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_7\,
Q => diff_pntr(4)
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_6\,
Q => diff_pntr(5)
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_5\,
Q => diff_pntr(6)
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_4\,
Q => diff_pntr(7)
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_7\,
Q => diff_pntr(8)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF004F0000004F"
)
port map (
I0 => \gpf1.prog_full_i_i_2_n_0\,
I1 => diff_pntr(6),
I2 => \gpf1.prog_full_i_i_3_n_0\,
I3 => wr_rst_busy,
I4 => ram_full_fb_i_reg,
I5 => \^prog_full\,
O => \gpf1.prog_full_i_i_1_n_0\
);
\gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => diff_pntr(2),
I1 => diff_pntr(3),
I2 => diff_pntr(0),
I3 => diff_pntr(1),
I4 => diff_pntr(5),
I5 => diff_pntr(4),
O => \gpf1.prog_full_i_i_2_n_0\
);
\gpf1.prog_full_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => diff_pntr(9),
I1 => diff_pntr(8),
I2 => diff_pntr(7),
O => \gpf1.prog_full_i_i_3_n_0\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gpf1.prog_full_i_i_1_n_0\,
PRE => \out\,
Q => \^prog_full\
);
plusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => plusOp_carry_n_0,
CO(2) => plusOp_carry_n_1,
CO(1) => plusOp_carry_n_2,
CO(0) => plusOp_carry_n_3,
CYINIT => E(0),
DI(3 downto 0) => Q(3 downto 0),
O(3) => plusOp_carry_n_4,
O(2) => plusOp_carry_n_5,
O(1) => plusOp_carry_n_6,
O(0) => plusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\plusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => plusOp_carry_n_0,
CO(3) => \plusOp_carry__0_n_0\,
CO(2) => \plusOp_carry__0_n_1\,
CO(1) => \plusOp_carry__0_n_2\,
CO(0) => \plusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \plusOp_carry__0_n_4\,
O(2) => \plusOp_carry__0_n_5\,
O(1) => \plusOp_carry__0_n_6\,
O(0) => \plusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d1_reg[7]\(3 downto 0)
);
\plusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_plusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_carry__1_n_6\,
O(0) => \plusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d1_reg[9]\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
E(0) => E(0),
din(27 downto 0) => din(27 downto 0),
dout(27 downto 0) => dout(27 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\rd_dc_i_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : in STD_LOGIC;
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal bin2gray : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gdiff.diff_pntr_pad[10]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[10]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_6_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out_0 : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_6_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \rd_dc_i[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[9]_i_1_n_3\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
RD_PNTR_WR(9 downto 0) <= \^rd_pntr_wr\(9 downto 0);
\gdiff.diff_pntr_pad[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \gdiff.diff_pntr_pad[10]_i_2_n_0\
);
\gdiff.diff_pntr_pad[10]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \gdiff.diff_pntr_pad[4]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \gdiff.diff_pntr_pad[4]_i_4_n_0\
);
\gdiff.diff_pntr_pad[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \gdiff.diff_pntr_pad[4]_i_5_n_0\
);
\gdiff.diff_pntr_pad[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \gdiff.diff_pntr_pad[8]_i_2_n_0\
);
\gdiff.diff_pntr_pad[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \gdiff.diff_pntr_pad[8]_i_3_n_0\
);
\gdiff.diff_pntr_pad[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \gdiff.diff_pntr_pad[8]_i_4_n_0\
);
\gdiff.diff_pntr_pad[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gdiff.diff_pntr_pad_reg[10]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => D(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \gdiff.diff_pntr_pad[10]_i_2_n_0\,
S(0) => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\,
CYINIT => p_0_out,
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => D(3 downto 0),
S(3) => \gdiff.diff_pntr_pad[4]_i_3_n_0\,
S(2) => \gdiff.diff_pntr_pad[4]_i_4_n_0\,
S(1) => \gdiff.diff_pntr_pad[4]_i_5_n_0\,
S(0) => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(3) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => D(7 downto 4),
S(3) => \gdiff.diff_pntr_pad[8]_i_2_n_0\,
S(2) => \gdiff.diff_pntr_pad[8]_i_3_n_0\,
S(1) => \gdiff.diff_pntr_pad[8]_i_4_n_0\,
S(0) => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
I2 => p_22_out(1),
I3 => Q(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => \gc0.count_reg[9]\(0),
I2 => p_22_out(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_d1_reg[7]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_d1_reg[7]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_reg[9]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_reg[9]\(1),
O => v1_reg_2(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
I2 => p_22_out(3),
I3 => Q(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => \gc0.count_reg[9]\(2),
I2 => p_22_out(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(2),
I1 => \gic0.gc0.count_d1_reg[7]\(2),
I2 => \^rd_pntr_wr\(3),
I3 => \gic0.gc0.count_d1_reg[7]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(2),
I1 => \gic0.gc0.count_reg[9]\(2),
I2 => \^rd_pntr_wr\(3),
I3 => \gic0.gc0.count_reg[9]\(3),
O => v1_reg_2(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
I2 => p_22_out(5),
I3 => Q(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => \gc0.count_reg[9]\(4),
I2 => p_22_out(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(4),
I1 => \gic0.gc0.count_d1_reg[7]\(4),
I2 => \^rd_pntr_wr\(5),
I3 => \gic0.gc0.count_d1_reg[7]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(4),
I1 => \gic0.gc0.count_reg[9]\(4),
I2 => \^rd_pntr_wr\(5),
I3 => \gic0.gc0.count_reg[9]\(5),
O => v1_reg_2(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
I2 => p_22_out(7),
I3 => Q(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => \gc0.count_reg[9]\(6),
I2 => p_22_out(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(6),
I1 => \gic0.gc0.count_d1_reg[7]\(6),
I2 => \^rd_pntr_wr\(7),
I3 => \gic0.gc0.count_d1_reg[7]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(6),
I1 => \gic0.gc0.count_reg[9]\(6),
I2 => \^rd_pntr_wr\(7),
I3 => \gic0.gc0.count_reg[9]\(7),
O => v1_reg_2(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
I2 => p_22_out(9),
I3 => Q(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => \gc0.count_reg[9]\(8),
I2 => p_22_out(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(8),
I1 => \gic0.gc0.count_reg[9]\(8),
I2 => \^rd_pntr_wr\(9),
I3 => \gic0.gc0.count_reg[9]\(9),
O => v1_reg_2(4)
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
Q(9 downto 0) => rd_pntr_gc(9 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8) => p_0_out_0,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(7 downto 0) => gray2bin(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_5_out(9),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[8]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
\out\(0) => p_6_out(9),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
Q => \^rd_pntr_wr\(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
Q => \^rd_pntr_wr\(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => \^rd_pntr_wr\(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => \^rd_pntr_wr\(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
Q => \^rd_pntr_wr\(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => \^rd_pntr_wr\(5)
);
\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
Q => \^rd_pntr_wr\(6)
);
\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
Q => \^rd_pntr_wr\(7)
);
\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
Q => \^rd_pntr_wr\(8)
);
\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(9),
Q => \^rd_pntr_wr\(9)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => rd_pntr_gc(9)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(4),
Q => p_22_out(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(5),
Q => p_22_out(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(6),
Q => p_22_out(6)
);
\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(7),
Q => p_22_out(7)
);
\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out_0,
Q => p_22_out(8)
);
\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_5_out(9),
Q => p_22_out(9)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(0),
I1 => \gic0.gc0.count_d2_reg[9]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(1),
I1 => \gic0.gc0.count_d2_reg[9]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(2),
I1 => \gic0.gc0.count_d2_reg[9]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(3),
I1 => \gic0.gc0.count_d2_reg[9]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(4),
I1 => \gic0.gc0.count_d2_reg[9]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(5),
I1 => \gic0.gc0.count_d2_reg[9]\(6),
O => bin2gray(5)
);
\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(6),
I1 => \gic0.gc0.count_d2_reg[9]\(7),
O => bin2gray(6)
);
\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(7),
I1 => \gic0.gc0.count_d2_reg[9]\(8),
O => bin2gray(7)
);
\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(8),
I1 => \gic0.gc0.count_d2_reg[9]\(9),
O => bin2gray(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(5),
Q => wr_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(6),
Q => wr_pntr_gc(6)
);
\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(7),
Q => wr_pntr_gc(7)
);
\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(8),
Q => wr_pntr_gc(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[9]\(9),
Q => wr_pntr_gc(9)
);
\rd_dc_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \rd_dc_i[3]_i_2_n_0\
);
\rd_dc_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \rd_dc_i[3]_i_3_n_0\
);
\rd_dc_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \rd_dc_i[3]_i_4_n_0\
);
\rd_dc_i[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \rd_dc_i[7]_i_2_n_0\
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \rd_dc_i[7]_i_3_n_0\
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \rd_dc_i[7]_i_4_n_0\
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \rd_dc_i[9]_i_2_n_0\
);
\rd_dc_i[9]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \rd_dc_i[9]_i_3_n_0\
);
\rd_dc_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[3]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[3]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[3]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => \rd_dc_i_reg[9]\(3 downto 0),
S(3) => \rd_dc_i[3]_i_2_n_0\,
S(2) => \rd_dc_i[3]_i_3_n_0\,
S(1) => \rd_dc_i[3]_i_4_n_0\,
S(0) => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[3]_i_1_n_0\,
CO(3) => \rd_dc_i_reg[7]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => \rd_dc_i_reg[9]\(7 downto 4),
S(3) => \rd_dc_i[7]_i_2_n_0\,
S(2) => \rd_dc_i[7]_i_3_n_0\,
S(1) => \rd_dc_i[7]_i_4_n_0\,
S(0) => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i_reg[9]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_1_n_0\,
CO(3 downto 1) => \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \rd_dc_i_reg[9]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \rd_dc_i_reg[9]\(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \rd_dc_i[9]_i_2_n_0\,
S(0) => \rd_dc_i[9]_i_3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\out\ => ram_empty_fb_i,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
\gdiff.diff_pntr_pad[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
O => p_0_out
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
port (
full : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
signal c2_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0),
v1_reg_0(0) => v1_reg_0(0)
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_fb_i_reg => c2_n_0,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
E(0) => E(0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
E(0) => E(0),
din(27 downto 0) => din(63 downto 36),
dout(27 downto 0) => dout(63 downto 36),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
prog_empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \gras.rsts_n_2\ : STD_LOGIC;
signal \^out\ : STD_LOGIC;
begin
\out\ <= \^out\;
\gras.gpe.rdpe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
port map (
AR(0) => AR(0),
D(9 downto 0) => D(9 downto 0),
\out\ => \^out\,
prog_empty => prog_empty,
rd_clk => rd_clk
);
\gras.grdc1.rdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
port map (
AR(0) => AR(0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0),
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0)
);
\gras.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \gras.rsts_n_2\,
empty => empty,
\out\ => \^out\,
p_0_out => p_0_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \gras.rsts_n_2\,
Q(9 downto 0) => Q(9 downto 0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
\gic0.gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal \gwas.wsts_n_1\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
signal wpntr_n_12 : STD_LOGIC;
signal wpntr_n_13 : STD_LOGIC;
signal wpntr_n_23 : STD_LOGIC;
signal wpntr_n_24 : STD_LOGIC;
signal wpntr_n_25 : STD_LOGIC;
signal wpntr_n_26 : STD_LOGIC;
signal wpntr_n_27 : STD_LOGIC;
signal wpntr_n_28 : STD_LOGIC;
signal wpntr_n_29 : STD_LOGIC;
signal wpntr_n_30 : STD_LOGIC;
signal wpntr_n_31 : STD_LOGIC;
signal wpntr_n_32 : STD_LOGIC;
signal wpntr_n_33 : STD_LOGIC;
signal wpntr_n_34 : STD_LOGIC;
signal wpntr_n_35 : STD_LOGIC;
signal wpntr_n_36 : STD_LOGIC;
signal wpntr_n_37 : STD_LOGIC;
signal wpntr_n_38 : STD_LOGIC;
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
E(0) <= \^e\(0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gwas.gpf.wrpf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(8) => p_13_out(8),
Q(7 downto 0) => \^q\(7 downto 0),
S(3) => wpntr_n_35,
S(2) => wpntr_n_36,
S(1) => wpntr_n_37,
S(0) => wpntr_n_38,
\gic0.gc0.count_d1_reg[7]\(3) => wpntr_n_27,
\gic0.gc0.count_d1_reg[7]\(2) => wpntr_n_28,
\gic0.gc0.count_d1_reg[7]\(1) => wpntr_n_29,
\gic0.gc0.count_d1_reg[7]\(0) => wpntr_n_30,
\gic0.gc0.count_d1_reg[9]\(1) => wpntr_n_12,
\gic0.gc0.count_d1_reg[9]\(0) => wpntr_n_13,
\out\ => \out\,
prog_full => prog_full,
ram_full_fb_i_reg => \gwas.wsts_n_1\,
wr_clk => wr_clk,
wr_rst_busy => wr_rst_busy
);
\gwas.gwdc0.wdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
port map (
AR(0) => AR(0),
S(3) => wpntr_n_31,
S(2) => wpntr_n_32,
S(1) => wpntr_n_33,
S(0) => wpntr_n_34,
\gic0.gc0.count_d2_reg[7]\(3) => wpntr_n_23,
\gic0.gc0.count_d2_reg[7]\(2) => wpntr_n_24,
\gic0.gc0.count_d2_reg[7]\(1) => wpntr_n_25,
\gic0.gc0.count_d2_reg[7]\(0) => wpntr_n_26,
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8 downto 0),
\gic0.gc0.count_d2_reg[9]\(1) => wpntr_n_0,
\gic0.gc0.count_d2_reg[9]\(0) => wpntr_n_1,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0)
);
\gwas.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0),
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\out\ => \gwas.wsts_n_1\,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(0) => \c1/v1_reg\(4),
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0),
E(0) => \^e\(0),
Q(8) => p_13_out(8),
Q(7 downto 0) => \^q\(7 downto 0),
RD_PNTR_WR(9 downto 0) => RD_PNTR_WR(9 downto 0),
S(3) => wpntr_n_31,
S(2) => wpntr_n_32,
S(1) => wpntr_n_33,
S(0) => wpntr_n_34,
\gdiff.diff_pntr_pad_reg[10]\(1) => wpntr_n_12,
\gdiff.diff_pntr_pad_reg[10]\(0) => wpntr_n_13,
\gdiff.diff_pntr_pad_reg[4]\(3) => wpntr_n_35,
\gdiff.diff_pntr_pad_reg[4]\(2) => wpntr_n_36,
\gdiff.diff_pntr_pad_reg[4]\(1) => wpntr_n_37,
\gdiff.diff_pntr_pad_reg[4]\(0) => wpntr_n_38,
\gdiff.diff_pntr_pad_reg[8]\(3) => wpntr_n_27,
\gdiff.diff_pntr_pad_reg[8]\(2) => wpntr_n_28,
\gdiff.diff_pntr_pad_reg[8]\(1) => wpntr_n_29,
\gdiff.diff_pntr_pad_reg[8]\(0) => wpntr_n_30,
\gic0.gc0.count_d1_reg[9]_0\(9 downto 0) => \gic0.gc0.count_d1_reg[9]\(9 downto 0),
v1_reg(0) => \c1/v1_reg\(4),
wr_clk => wr_clk,
\wr_data_count_i_reg[7]\(3) => wpntr_n_23,
\wr_data_count_i_reg[7]\(2) => wpntr_n_24,
\wr_data_count_i_reg[7]\(1) => wpntr_n_25,
\wr_data_count_i_reg[7]\(0) => wpntr_n_26,
\wr_data_count_i_reg[9]\(1) => wpntr_n_0,
\wr_data_count_i_reg[9]\(0) => wpntr_n_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gras.rsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gwas.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_23_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 10 downto 1 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(9 downto 0) => plusOp(10 downto 1),
Q(9 downto 0) => p_0_out_0(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => p_13_out(7 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\gic0.gc0.count_reg[9]\(9 downto 0) => wr_pntr_plus2(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
p_0_out => p_0_out,
rd_clk => rd_clk,
\rd_dc_i_reg[9]\(9 downto 0) => minusOp(9 downto 0),
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
v1_reg_1(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
v1_reg_2(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(9 downto 0) => plusOp(10 downto 1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out_0(9 downto 0),
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
empty => empty,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => minusOp(9 downto 0),
\out\ => p_2_out,
p_0_out => p_0_out,
prog_empty => prog_empty,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_12_out(9 downto 0),
E(0) => p_18_out,
Q(7 downto 0) => p_13_out(7 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
full => full,
\gic0.gc0.count_d1_reg[9]\(9 downto 0) => wr_pntr_plus2(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
\out\ => rst_full_ff_i,
prog_full => prog_full,
v1_reg(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0),
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
E(0) => p_18_out,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out_0(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 956;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 957;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 65;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 956;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 957;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 65;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 64;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => prog_empty,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => prog_full,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/31a2bbcb305771f0/fifo_generator_rx_inst_sim_netlist.vhdl | 1 | 179161 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 26 17:01:25 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 6) => \gc0.count_d1_reg[7]\(7 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 6) => Q(7 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => din(31 downto 0),
DIBDI(31 downto 0) => din(63 downto 32),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => dout(31 downto 0),
DOBDO(31 downto 0) => dout(63 downto 32),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\,
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => \out\(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => E(0),
WEBWE(6) => E(0),
WEBWE(5) => E(0),
WEBWE(4) => E(0),
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 6 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[7]_i_2\ : label is "soft_lutpair1";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \^q\(3),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \gc0.count[7]_i_2_n_0\,
I1 => \^q\(4),
I2 => \^q\(5),
I3 => rd_pntr_plus1(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \gc0.count[7]_i_2_n_0\,
I1 => rd_pntr_plus1(6),
I2 => \^q\(5),
I3 => \^q\(4),
I4 => rd_pntr_plus1(7),
O => plusOp(7)
);
\gc0.count[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \gc0.count[7]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(6),
Q => rd_pntr_plus1(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(7),
Q => rd_pntr_plus1(7)
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"90090000"
)
port map (
I0 => rd_pntr_plus1(7),
I1 => \gcc0.gc0.count_d1_reg[7]\(1),
I2 => rd_pntr_plus1(6),
I3 => \gcc0.gc0.count_d1_reg[7]\(0),
I4 => rd_en,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\gc0.count_d1[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg_0,
PRE => AR(0),
Q => ram_empty_i
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
ram_full_comb : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_reg[7]\ : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
\gc0.count_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gcc0.gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_empty_fb_i_i_10_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_7_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_8_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_9_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_3_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_6_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ram_full_fb_i_i_6 : label is "soft_lutpair5";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(4),
I1 => p_12_out(2),
I2 => p_12_out(0),
I3 => p_12_out(1),
I4 => p_12_out(3),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \gcc0.gc0.count[7]_i_2_n_0\,
I1 => p_12_out(4),
I2 => p_12_out(5),
I3 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \gcc0.gc0.count[7]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(5),
I3 => p_12_out(4),
I4 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \gcc0.gc0.count[7]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(5),
Q => \^q\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(6),
Q => \^q\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(7),
Q => \^q\(7)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => p_12_out(7)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFEFEFCF000000"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => \out\,
I2 => wr_en,
I3 => \gc0.count_reg[7]\,
I4 => ram_empty_fb_i_i_4_n_0,
I5 => ram_empty_fb_i_reg_0,
O => ram_empty_i_reg
);
ram_empty_fb_i_i_10: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(1),
I1 => \gc0.count_reg[5]\(1),
I2 => \^q\(0),
I3 => \gc0.count_reg[5]\(0),
O => ram_empty_fb_i_i_10_n_0
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => ram_empty_fb_i_i_5_n_0,
I1 => ram_empty_fb_i_i_6_n_0,
I2 => ram_empty_fb_i_i_7_n_0,
I3 => ram_empty_fb_i_i_8_n_0,
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8200008200000000"
)
port map (
I0 => ram_empty_fb_i_i_9_n_0,
I1 => \^q\(5),
I2 => \gc0.count_reg[5]\(5),
I3 => \^q\(4),
I4 => \gc0.count_reg[5]\(4),
I5 => ram_empty_fb_i_i_10_n_0,
O => ram_empty_fb_i_i_4_n_0
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(5),
I1 => \gc0.count_d1_reg[7]\(5),
I2 => \^q\(4),
I3 => \gc0.count_d1_reg[7]\(4),
O => ram_empty_fb_i_i_5_n_0
);
ram_empty_fb_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[7]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[7]\(7),
O => ram_empty_fb_i_i_6_n_0
);
ram_empty_fb_i_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => \^q\(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => ram_empty_fb_i_i_7_n_0
);
ram_empty_fb_i_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => \^q\(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => ram_empty_fb_i_i_8_n_0
);
ram_empty_fb_i_i_9: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(3),
I1 => \gc0.count_reg[5]\(3),
I2 => \^q\(2),
I3 => \gc0.count_reg[5]\(2),
O => ram_empty_fb_i_i_9_n_0
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"C000EEEEC000C000"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => ram_empty_fb_i_reg,
I2 => ram_full_fb_i_i_3_n_0,
I3 => ram_full_fb_i_i_4_n_0,
I4 => wr_rst_busy,
I5 => \out\,
O => ram_full_comb
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000090090000"
)
port map (
I0 => \gc0.count_d1_reg[7]\(7),
I1 => p_12_out(7),
I2 => \gc0.count_d1_reg[7]\(6),
I3 => p_12_out(6),
I4 => wr_en,
I5 => \out\,
O => ram_full_fb_i_i_3_n_0
);
ram_full_fb_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8200008200000000"
)
port map (
I0 => ram_full_fb_i_i_5_n_0,
I1 => p_12_out(5),
I2 => \gc0.count_d1_reg[7]\(5),
I3 => p_12_out(4),
I4 => \gc0.count_d1_reg[7]\(4),
I5 => ram_full_fb_i_i_6_n_0,
O => ram_full_fb_i_i_4_n_0
);
ram_full_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => p_12_out(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => ram_full_fb_i_i_5_n_0
);
ram_full_fb_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => p_12_out(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => ram_full_fb_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal p_7_out : STD_LOGIC;
begin
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
AR(0) => AR(0),
E(0) => p_7_out,
clk => clk,
empty => empty,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg_0,
rd_en => rd_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0),
E(0) => p_7_out,
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[7]\(1 downto 0) => \gcc0.gc0.count_d1_reg[7]\(1 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
rd_en => rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => rd_rst_reg(0),
I1 => rd_en,
I2 => ram_empty_fb_i_reg,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_reg[7]\ : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
\gc0.count_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gwss.wsts_n_0\ : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\out\ => \gwss.wsts_n_0\,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gc0.count_reg[5]\(5 downto 0) => \gc0.count_reg[5]\(5 downto 0),
\gc0.count_reg[7]\ => \gc0.count_reg[7]\,
\out\ => \gwss.wsts_n_0\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg_0,
ram_empty_i_reg => ram_empty_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_8\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_17_out : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0) => p_0_out(7 downto 0),
Q(5 downto 0) => rd_pntr_plus1(5 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[7]\(1 downto 0) => p_11_out(7 downto 6),
\out\ => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.rd_n_9\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_8\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_1\,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_17_out,
Q(7 downto 0) => p_11_out(7 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[7]\(7 downto 0) => p_0_out(7 downto 0),
\gc0.count_reg[5]\(5 downto 0) => rd_pntr_plus1(5 downto 0),
\gc0.count_reg[7]\ => \gntv_or_sync_fifo.gl0.rd_n_9\,
\out\ => rst_full_ff_i,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_8\,
ram_empty_fb_i_reg_0 => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_1\,
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
E(0) => p_17_out,
Q(7 downto 0) => p_11_out(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => p_0_out(7 downto 0),
\out\(0) => rd_rst_i(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 254;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 253;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 254;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 253;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(7 downto 0) => NLW_U0_data_count_UNCONNECTED(7 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(7 downto 0) => B"00000000",
prog_empty_thresh_assert(7 downto 0) => B"00000000",
prog_empty_thresh_negate(7 downto 0) => B"00000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(7 downto 0) => B"00000000",
prog_full_thresh_assert(7 downto 0) => B"00000000",
prog_full_thresh_negate(7 downto 0) => B"00000000",
rd_clk => '0',
rd_data_count(7 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(7 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(7 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(7 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_atanlut.vhd | 10 | 165265 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ATANLUT.VHD ***
--*** ***
--*** Function: ArcTangent Look Up Table ***
--*** (Generated by MATLAB Utility) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_atanlut IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_atanlut;
ARCHITECTURE rtl OF fp_atanlut IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "0000000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(255,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(262058,18);
WHEN "0000000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(511,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261461,18);
WHEN "0000000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(767,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259840,18);
WHEN "0000000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1023,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256682,18);
WHEN "0000000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251477,18);
WHEN "0000000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1535,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243713,18);
WHEN "0000000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232877,18);
WHEN "0000001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218459,18);
WHEN "0000001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2303,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199947,18);
WHEN "0000001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2559,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176830,18);
WHEN "0000001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148596,18);
WHEN "0000001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114736,18);
WHEN "0000001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3327,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74739,18);
WHEN "0000001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3583,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(28094,18);
WHEN "0000001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3838,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236436,18);
WHEN "0000010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4094,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174967,18);
WHEN "0000010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105322,18);
WHEN "0000010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(26992,18);
WHEN "0000010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201613,18);
WHEN "0000010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5117,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104389,18);
WHEN "0000010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5372,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259100,18);
WHEN "0000010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5628,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140951,18);
WHEN "0000010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11580,18);
WHEN "0000011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6139,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132624,18);
WHEN "0000011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6394,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241434,18);
WHEN "0000011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6650,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75361,18);
WHEN "0000011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6905,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158188,18);
WHEN "0000011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(227268,18);
WHEN "0000011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7416,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19954,18);
WHEN "0000011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7671,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60030,18);
WHEN "0000011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7926,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84851,18);
WHEN "0000100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8181,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93916,18);
WHEN "0000100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8436,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86725,18);
WHEN "0000100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8691,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62776,18);
WHEN "0000100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8946,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21573,18);
WHEN "0000100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9200,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224760,18);
WHEN "0000100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9455,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(147552,18);
WHEN "0000100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9710,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51596,18);
WHEN "0000100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9964,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198541,18);
WHEN "0000101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10219,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(63603,18);
WHEN "0000101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10473,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170578,18);
WHEN "0000101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10727,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256827,18);
WHEN "0000101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59715,18);
WHEN "0000101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11236,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(103038,18);
WHEN "0000101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11490,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124162,18);
WHEN "0000101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11744,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122599,18);
WHEN "0000101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97859,18);
WHEN "0000110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12252,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49456,18);
WHEN "0000110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12505,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239047,18);
WHEN "0000110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12759,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(141859,18);
WHEN "0000110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19553,18);
WHEN "0000110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133790,18);
WHEN "0000110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13519,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(221944,18);
WHEN "0000110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13773,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21390,18);
WHEN "0000110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14026,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(55937,18);
WHEN "0000111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62963,18);
WHEN "0000111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14532,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41991,18);
WHEN "0000111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14784,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254689,18);
WHEN "0000111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15037,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176296,18);
WHEN "0000111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68480,18);
WHEN "0000111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15542,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192916,18);
WHEN "0000111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15795,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24844,18);
WHEN "0000111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88083,18);
WHEN "0001000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16299,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120021,18);
WHEN "0001000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120191,18);
WHEN "0001000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16803,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88130,18);
WHEN "0001000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23371,18);
WHEN "0001000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17306,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187599,18);
WHEN "0001000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56063,18);
WHEN "0001000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17809,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152592,18);
WHEN "0001000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18060,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214584,18);
WHEN "0001001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241584,18);
WHEN "0001001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233135,18);
WHEN "0001001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18813,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188785,18);
WHEN "0001001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108082,18);
WHEN "0001001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19314,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252719,18);
WHEN "0001001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97960,18);
WHEN "0001001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167646,18);
WHEN "0001001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20065,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199187,18);
WHEN "0001010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192140,18);
WHEN "0001010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146062,18);
WHEN "0001010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60512,18);
WHEN "0001010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197196,18);
WHEN "0001010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21314,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31389,18);
WHEN "0001010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21563,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86943,18);
WHEN "0001010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21812,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101281,18);
WHEN "0001010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22061,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73969,18);
WHEN "0001011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22310,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4579,18);
WHEN "0001011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154826,18);
WHEN "0001011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22806,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(262139,18);
WHEN "0001011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(63948,18);
WHEN "0001011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23303,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84120,18);
WHEN "0001011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60088,18);
WHEN "0001011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23798,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253578,18);
WHEN "0001011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24046,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(139883,18);
WHEN "0001100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24293,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242876,18);
WHEN "0001100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24541,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37856,18);
WHEN "0001100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24788,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48697,18);
WHEN "0001100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25035,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(12847,18);
WHEN "0001100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25281,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192040,18);
WHEN "0001100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25528,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61583,18);
WHEN "0001100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25774,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145360,18);
WHEN "0001100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(180824,18);
WHEN "0001101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167574,18);
WHEN "0001101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105213,18);
WHEN "0001101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(255489,18);
WHEN "0001101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27003,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93717,18);
WHEN "0001101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27248,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143796,18);
WHEN "0001101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27493,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143189,18);
WHEN "0001101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27738,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91508,18);
WHEN "0001101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250512,18);
WHEN "0001110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28227,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95529,18);
WHEN "0001110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28471,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150463,18);
WHEN "0001110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28715,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152791,18);
WHEN "0001110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102135,18);
WHEN "0001110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260263,18);
WHEN "0001110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29446,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102513,18);
WHEN "0001110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29689,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152801,18);
WHEN "0001110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148615,18);
WHEN "0001111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30175,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89586,18);
WHEN "0001111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30417,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237492,18);
WHEN "0001111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30660,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67684,18);
WHEN "0001111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104088,18);
WHEN "0001111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31144,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84201,18);
WHEN "0001111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31386,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7666,18);
WHEN "0001111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31627,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136273,18);
WHEN "0001111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31868,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207526,18);
WHEN "0010000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32109,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(221074,18);
WHEN "0010000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176570,18);
WHEN "0010000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32591,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73668,18);
WHEN "0010000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32831,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174167,18);
WHEN "0010000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215584,18);
WHEN "0010000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197579,18);
WHEN "0010000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119815,18);
WHEN "0010000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33790,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244102,18);
WHEN "0010001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45819,18);
WHEN "0010001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34269,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48923,18);
WHEN "0010001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253089,18);
WHEN "0010001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34746,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133701,18);
WHEN "0010001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214724,18);
WHEN "0010001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233694,18);
WHEN "0010001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35460,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(190291,18);
WHEN "0010001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35698,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84200,18);
WHEN "0010010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(177249,18);
WHEN "0010010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36172,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206983,18);
WHEN "0010010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36409,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173093,18);
WHEN "0010010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36646,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75271,18);
WHEN "0010010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36882,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175356,18);
WHEN "0010010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210901,18);
WHEN "0010010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37354,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181607,18);
WHEN "0010010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37590,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87173,18);
WHEN "0010011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37825,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(189450,18);
WHEN "0010011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38060,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226000,18);
WHEN "0010011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38295,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196531,18);
WHEN "0010011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38530,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(100754,18);
WHEN "0010011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200528,18);
WHEN "0010011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233423,18);
WHEN "0010011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39232,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199158,18);
WHEN "0010011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97454,18);
WHEN "0010100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39699,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(190176,18);
WHEN "0010100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214908,18);
WHEN "0010100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40165,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171374,18);
WHEN "0010100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40398,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59307,18);
WHEN "0010100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40630,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140580,18);
WHEN "0010100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40862,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152786,18);
WHEN "0010100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41094,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95661,18);
WHEN "0010100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41325,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(231088,18);
WHEN "0010101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41557,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34520,18);
WHEN "0010101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41788,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29989,18);
WHEN "0010101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42018,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217242,18);
WHEN "0010101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42249,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(71738,18);
WHEN "0010101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42479,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117517,18);
WHEN "0010101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42709,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92187,18);
WHEN "0010101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257648,18);
WHEN "0010101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43168,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89371,18);
WHEN "0010110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111402,18);
WHEN "0010110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43626,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61360,18);
WHEN "0010110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43854,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201155,18);
WHEN "0010110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6265,18);
WHEN "0010110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(747,18);
WHEN "0010110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44538,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184374,18);
WHEN "0010110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44766,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32631,18);
WHEN "0010110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44993,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69583,18);
WHEN "0010111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45220,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32865,18);
WHEN "0010111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45446,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184401,18);
WHEN "0010111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45672,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261830,18);
WHEN "0010111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45899,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2795,18);
WHEN "0010111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46124,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193515,18);
WHEN "0010111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47349,18);
WHEN "0010111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88377,18);
WHEN "0010111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46800,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54250,18);
WHEN "0011000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206908,18);
WHEN "0011000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47249,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21864,18);
WHEN "0011000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47473,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23207,18);
WHEN "0011000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47696,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210741,18);
WHEN "0011000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47920,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59984,18);
WHEN "0011000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48143,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95032,18);
WHEN "0011000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48366,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(53554,18);
WHEN "0011000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48588,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197504,18);
WHEN "0011001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48811,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2412,18);
WHEN "0011001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254526,18);
WHEN "0011001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49254,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167234,18);
WHEN "0011001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49476,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2502,18);
WHEN "0011001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49697,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22299,18);
WHEN "0011001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49917,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226451,18);
WHEN "0011001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50138,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(90499,18);
WHEN "0011001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50358,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(138562,18);
WHEN "0011010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50578,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108329,18);
WHEN "0011010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50797,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261779,18);
WHEN "0011010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51017,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74462,18);
WHEN "0011010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51236,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70506,18);
WHEN "0011010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51454,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249754,18);
WHEN "0011010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87760,18);
WHEN "0011010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51891,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108660,18);
WHEN "0011010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52109,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50158,18);
WHEN "0011011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52326,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174249,18);
WHEN "0011011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52543,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218642,18);
WHEN "0011011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52760,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183192,18);
WHEN "0011011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52977,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67756,18);
WHEN "0011011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53193,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134338,18);
WHEN "0011011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53409,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120655,18);
WHEN "0011011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(26571,18);
WHEN "0011011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53840,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114096,18);
WHEN "0011100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120953,18);
WHEN "0011100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54270,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47013,18);
WHEN "0011100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154291,18);
WHEN "0011100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54698,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(180519,18);
WHEN "0011100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54912,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125572,18);
WHEN "0011100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55125,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251472,18);
WHEN "0011100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33813,18);
WHEN "0011100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258909,18);
WHEN "0011101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140212,18);
WHEN "0011101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55976,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201898,18);
WHEN "0011101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181710,18);
WHEN "0011101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56400,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79540,18);
WHEN "0011101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56611,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157424,18);
WHEN "0011101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153114,18);
WHEN "0011101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57033,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(66506,18);
WHEN "0011101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57243,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(159643,18);
WHEN "0011110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57453,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170281,18);
WHEN "0011110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57663,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98325,18);
WHEN "0011110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57872,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205822,18);
WHEN "0011110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58081,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230535,18);
WHEN "0011110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172373,18);
WHEN "0011110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58499,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31247,18);
WHEN "0011110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58707,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69214,18);
WHEN "0011110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58915,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24044,18);
WHEN "0011111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59122,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157797,18);
WHEN "0011111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59329,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208248,18);
WHEN "0011111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59536,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175318,18);
WHEN "0011111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59743,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58929,18);
WHEN "0011111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59949,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(121149,18);
WHEN "0011111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60155,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(99760,18);
WHEN "0011111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60360,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256834,18);
WHEN "0011111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60566,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68012,18);
WHEN "0100000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60771,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57516,18);
WHEN "0100000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60975,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225277,18);
WHEN "0100000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61180,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46944,18);
WHEN "0100000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61384,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46741,18);
WHEN "0100000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61587,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224608,18);
WHEN "0100000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56198,18);
WHEN "0100000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61994,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(65741,18);
WHEN "0100000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62196,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253182,18);
WHEN "0100001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62399,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94178,18);
WHEN "0100001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62601,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112967,18);
WHEN "0100001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62803,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47353,18);
WHEN "0100001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63004,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(159433,18);
WHEN "0100001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63205,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187015,18);
WHEN "0100001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63406,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130055,18);
WHEN "0100001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250654,18);
WHEN "0100001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24481,18);
WHEN "0100010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237930,18);
WHEN "0100010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64206,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104530,18);
WHEN "0100010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64405,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148532,18);
WHEN "0100010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64604,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107758,18);
WHEN "0100010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244320,18);
WHEN "0100010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65001,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33897,18);
WHEN "0100010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(747,18);
WHEN "0100010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65396,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144844,18);
WHEN "0100011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65593,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(204016,18);
WHEN "0100011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65790,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178238,18);
WHEN "0100011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65987,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67488,18);
WHEN "0100011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66183,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133888,18);
WHEN "0100011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66379,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115273,18);
WHEN "0100011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11625,18);
WHEN "0100011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66770,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(85072,18);
WHEN "0100011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66965,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73455,18);
WHEN "0100100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67159,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(238902,18);
WHEN "0100100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67354,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57115,18);
WHEN "0100100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52371,18);
WHEN "0100100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67741,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224661,18);
WHEN "0100100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49688,18);
WHEN "0100100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51735,18);
WHEN "0100100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68320,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230798,18);
WHEN "0100100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68513,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62585,18);
WHEN "0100101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68705,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(71382,18);
WHEN "0100101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68896,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257190,18);
WHEN "0100101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69088,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95722,18);
WHEN "0100101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111268,18);
WHEN "0100101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69470,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41689,18);
WHEN "0100101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69660,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149135,18);
WHEN "0100101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69850,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171468,18);
WHEN "0100101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70040,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108696,18);
WHEN "0100110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70229,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222974,18);
WHEN "0100110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70418,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252170,18);
WHEN "0100110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70607,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196294,18);
WHEN "0100110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(55362,18);
WHEN "0100110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91533,18);
WHEN "0100110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71172,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42680,18);
WHEN "0100110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71359,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170964,18);
WHEN "0100110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71546,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214261,18);
WHEN "0100111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71733,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172591,18);
WHEN "0100111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71920,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45977,18);
WHEN "0100111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72106,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(96586,18);
WHEN "0100111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72292,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62298,18);
WHEN "0100111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72477,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205284,18);
WHEN "0100111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72663,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1281,18);
WHEN "0100111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72847,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236752,18);
WHEN "0100111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125293,18);
WHEN "0101000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73216,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191223,18);
WHEN "0101000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73400,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172431,18);
WHEN "0101000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73584,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68949,18);
WHEN "0101000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73767,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(142957,18);
WHEN "0101000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73950,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132346,18);
WHEN "0101000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74133,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37152,18);
WHEN "0101000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119559,18);
WHEN "0101000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74497,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117461,18);
WHEN "0101001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74679,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30899,18);
WHEN "0101001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74860,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122058,18);
WHEN "0101001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128837,18);
WHEN "0101001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51281,18);
WHEN "0101001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151578,18);
WHEN "0101001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75582,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167630,18);
WHEN "0101001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75762,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(99484,18);
WHEN "0101001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75941,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(209334,18);
WHEN "0101010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76120,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235084,18);
WHEN "0101010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76299,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176784,18);
WHEN "0101010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76478,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34487,18);
WHEN "0101010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70389,18);
WHEN "0101010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76834,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22400,18);
WHEN "0101010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77011,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152718,18);
WHEN "0101010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199256,18);
WHEN "0101010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77365,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162070,18);
WHEN "0101011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77542,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41217,18);
WHEN "0101011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77718,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98901,18);
WHEN "0101011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77894,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73038,18);
WHEN "0101011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78069,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225832,18);
WHEN "0101011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78245,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33058,18);
WHEN "0101011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78420,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19065,18);
WHEN "0101011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78594,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183917,18);
WHEN "0101011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78769,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3392,18);
WHEN "0101100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1843,18);
WHEN "0101100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79116,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179336,18);
WHEN "0101100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11651,18);
WHEN "0101100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79463,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23144,18);
WHEN "0101100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79635,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213885,18);
WHEN "0101100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59656,18);
WHEN "0101100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79980,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84815,18);
WHEN "0101100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80152,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(27291,18);
WHEN "0101101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80323,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149301,18);
WHEN "0101101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80494,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188773,18);
WHEN "0101101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80665,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145784,18);
WHEN "0101101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20408,18);
WHEN "0101101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74865,18);
WHEN "0101101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81176,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47089,18);
WHEN "0101101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81345,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199302,18);
WHEN "0101101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7293,18);
WHEN "0101110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81683,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257575,18);
WHEN "0101110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81852,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163796,18);
WHEN "0101110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250325,18);
WHEN "0101110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(255100,18);
WHEN "0101110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82356,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178203,18);
WHEN "0101110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82524,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19719,18);
WHEN "0101110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82691,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41874,18);
WHEN "0101110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82857,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244755,18);
WHEN "0101111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104158,18);
WHEN "0101111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83190,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144458,18);
WHEN "0101111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83356,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(103598,18);
WHEN "0101111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83521,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243810,18);
WHEN "0101111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83687,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(40895,18);
WHEN "0101111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83852,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19229,18);
WHEN "0101111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84016,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178903,18);
WHEN "0101111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84180,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257864,18);
WHEN "0110000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84344,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256201,18);
WHEN "0110000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84508,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174008,18);
WHEN "0110000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84672,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11377,18);
WHEN "0110000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84835,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30546,18);
WHEN "0110000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84997,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(231607,18);
WHEN "0110000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(90368,18);
WHEN "0110000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85322,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131213,18);
WHEN "0110000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92091,18);
WHEN "0110001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85645,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235245,18);
WHEN "0110001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36483,18);
WHEN "0110001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20191,18);
WHEN "0110001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(186467,18);
WHEN "0110001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86289,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11121,18);
WHEN "0110001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86449,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(18541,18);
WHEN "0110001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86608,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208828,18);
WHEN "0110001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86768,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57793,18);
WHEN "0110010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89826,18);
WHEN "0110010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87086,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42884,18);
WHEN "0110010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87244,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179213,18);
WHEN "0110010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236772,18);
WHEN "0110010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87560,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215665,18);
WHEN "0110010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87718,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115995,18);
WHEN "0110010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87875,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200010,18);
WHEN "0110010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205672,18);
WHEN "0110011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88189,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133084,18);
WHEN "0110011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88345,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244498,18);
WHEN "0110011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15731,18);
WHEN "0110011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88657,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233323,18);
WHEN "0110011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88813,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(110948,18);
WHEN "0110011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173002,18);
WHEN "0110011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89123,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157449,18);
WHEN "0110011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89278,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64397,18);
WHEN "0110100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89432,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156101,18);
WHEN "0110100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89586,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170525,18);
WHEN "0110100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89740,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107780,18);
WHEN "0110100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230119,18);
WHEN "0110100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(13365,18);
WHEN "0110100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244062,18);
WHEN "0110100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90352,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(135889,18);
WHEN "0110100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90504,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213247,18);
WHEN "0110101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214103,18);
WHEN "0110101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(138570,18);
WHEN "0110101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248907,18);
WHEN "0110101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91111,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20937,18);
WHEN "0110101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91261,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241208,18);
WHEN "0110101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91412,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123401,18);
WHEN "0110101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191920,18);
WHEN "0110101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91712,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184734,18);
WHEN "0110110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91862,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101960,18);
WHEN "0110110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92011,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205858,18);
WHEN "0110110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234399,18);
WHEN "0110110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92309,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187700,18);
WHEN "0110110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92458,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(65877,18);
WHEN "0110110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131192,18);
WHEN "0110110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92754,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(121618,18);
WHEN "0110110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37273,18);
WHEN "0110111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93049,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140418,18);
WHEN "0110111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93196,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(169029,18);
WHEN "0110111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93343,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123223,18);
WHEN "0110111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93490,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3119,18);
WHEN "0110111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70981,18);
WHEN "0110111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93782,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64784,18);
WHEN "0110111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(246792,18);
WHEN "0110111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94073,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92836,18);
WHEN "0111000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94218,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(127326,18);
WHEN "0111000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94363,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88237,18);
WHEN "0111000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237834,18);
WHEN "0111000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51950,18);
WHEN "0111000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54995,18);
WHEN "0111000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94939,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247090,18);
WHEN "0111000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104069,18);
WHEN "0111000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95226,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150342,18);
WHEN "0111001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95369,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123886,18);
WHEN "0111001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24825,18);
WHEN "0111001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95654,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115424,18);
WHEN "0111001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133663,18);
WHEN "0111001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79665,18);
WHEN "0111001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96079,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215697,18);
WHEN "0111001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17594,18);
WHEN "0111001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96362,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9768,18);
WHEN "0111010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192343,18);
WHEN "0111010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41154,18);
WHEN "0111010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80615,18);
WHEN "0111010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96923,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48704,18);
WHEN "0111010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97062,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207691,18);
WHEN "0111010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33412,18);
WHEN "0111010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50281,18);
WHEN "0111010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97479,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258422,18);
WHEN "0111011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133671,18);
WHEN "0111011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97756,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200444,18);
WHEN "0111011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97894,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196720,18);
WHEN "0111011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122625,18);
WHEN "0111011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98169,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240430,18);
WHEN "0111011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98307,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(25971,18);
WHEN "0111011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98444,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3664,18);
WHEN "0111011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173633,18);
WHEN "0111100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98717,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11717,18);
WHEN "0111100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98853,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42330,18);
WHEN "0111100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98989,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3456,18);
WHEN "0111100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99124,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157363,18);
WHEN "0111100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99259,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242035,18);
WHEN "0111100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99394,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257599,18);
WHEN "0111100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99529,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(204180,18);
WHEN "0111100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99664,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81908,18);
WHEN "0111101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99798,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153051,18);
WHEN "0111101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155593,18);
WHEN "0111101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100066,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89662,18);
WHEN "0111101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217528,18);
WHEN "0111101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100333,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15031,18);
WHEN "0111101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6586,18);
WHEN "0111101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100598,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192320,18);
WHEN "0111101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100731,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48074,18);
WHEN "0111110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100863,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98261,18);
WHEN "0111110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100995,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80868,18);
WHEN "0111110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101126,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258163,18);
WHEN "0111110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101258,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105988,18);
WHEN "0111110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101389,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148759,18);
WHEN "0111110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101520,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124458,18);
WHEN "0111110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101651,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33214,18);
WHEN "0111110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101781,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137298,18);
WHEN "0111111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101911,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174695,18);
WHEN "0111111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145532,18);
WHEN "0111111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102171,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49937,18);
WHEN "0111111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102300,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150182,18);
WHEN "0111111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102429,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184251,18);
WHEN "0111111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152273,18);
WHEN "0111111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102687,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54374,18);
WHEN "0111111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152827,18);
WHEN "1000000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(185617,18);
WHEN "1000000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152870,18);
WHEN "1000000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54715,18);
WHEN "1000000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103326,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153425,18);
WHEN "1000000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103453,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(186982,18);
WHEN "1000000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155515,18);
WHEN "1000000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103707,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59152,18);
WHEN "1000000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103833,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160165,18);
WHEN "1000001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196538,18);
WHEN "1000001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(168399,18);
WHEN "1000001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75875,18);
WHEN "1000001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104336,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181239,18);
WHEN "1000001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104461,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222475,18);
WHEN "1000001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104586,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199709,18);
WHEN "1000001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104711,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113070,18);
WHEN "1000001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104835,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224830,18);
WHEN "1000010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104960,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10829,18);
WHEN "1000010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257625,18);
WHEN "1000010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105207,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178916,18);
WHEN "1000010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105331,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36971,18);
WHEN "1000010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105454,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94064,18);
WHEN "1000010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105577,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88176,18);
WHEN "1000010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105700,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19436,18);
WHEN "1000010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150116,18);
WHEN "1000011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105944,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218198,18);
WHEN "1000011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106066,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(223809,18);
WHEN "1000011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167077,18);
WHEN "1000011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106310,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48129,18);
WHEN "1000011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106431,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(129236,18);
WHEN "1000011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106552,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148382,18);
WHEN "1000011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105692,18);
WHEN "1000011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106794,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1293,18);
WHEN "1000100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106914,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97458,18);
WHEN "1000100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107034,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132167,18);
WHEN "1000100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107154,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105548,18);
WHEN "1000100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107274,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17728,18);
WHEN "1000100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107393,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130976,18);
WHEN "1000100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183276,18);
WHEN "1000100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107631,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174753,18);
WHEN "1000100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107750,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105533,18);
WHEN "1000101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107868,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237887,18);
WHEN "1000101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107987,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47653,18);
WHEN "1000101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108105,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59244,18);
WHEN "1000101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108223,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10643,18);
WHEN "1000101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108340,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(164119,18);
WHEN "1000101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108457,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257653,18);
WHEN "1000101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29228,18);
WHEN "1000101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108692,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3255,18);
WHEN "1000110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179862,18);
WHEN "1000110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108925,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34885,18);
WHEN "1000110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92737,18);
WHEN "1000110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109157,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91399,18);
WHEN "1000110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109273,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30995,18);
WHEN "1000110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173795,18);
WHEN "1000110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109503,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257779,18);
WHEN "1000110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109619,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20928,18);
WHEN "1000111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109733,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249798,18);
WHEN "1000111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109848,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158081,18);
WHEN "1000111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109963,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8045,18);
WHEN "1000111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110077,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61959,18);
WHEN "1000111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110191,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57801,18);
WHEN "1000111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110304,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257841,18);
WHEN "1000111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110418,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137913,18);
WHEN "1000111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110531,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222429,18);
WHEN "1001000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110644,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249369,18);
WHEN "1001000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218855,18);
WHEN "1001000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110870,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131010,18);
WHEN "1001000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248102,18);
WHEN "1001000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111095,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45965,18);
WHEN "1001000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111207,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49010,18);
WHEN "1001000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111318,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257360,18);
WHEN "1001000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111430,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146848,18);
WHEN "1001001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111541,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241886,18);
WHEN "1001001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111653,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(18306,18);
WHEN "1001001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(520,18);
WHEN "1001001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111874,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188648,18);
WHEN "1001001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111985,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58525,18);
WHEN "1001001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112095,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134560,18);
WHEN "1001001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112205,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154730,18);
WHEN "1001001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119156,18);
WHEN "1001010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112425,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(27960,18);
WHEN "1001010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112534,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143406,18);
WHEN "1001010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203471,18);
WHEN "1001010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112752,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208276,18);
WHEN "1001010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157941,18);
WHEN "1001010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52586,18);
WHEN "1001010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113078,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154475,18);
WHEN "1001010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113186,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201584,18);
WHEN "1001011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113294,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(194033,18);
WHEN "1001011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131941,18);
WHEN "1001011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113510,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15429,18);
WHEN "1001011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113617,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106759,18);
WHEN "1001011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113724,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143905,18);
WHEN "1001011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113831,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126988,18);
WHEN "1001011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56126,18);
WHEN "1001011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114044,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193581,18);
WHEN "1001100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114151,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15184,18);
WHEN "1001100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114257,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45342,18);
WHEN "1001100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114363,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22027,18);
WHEN "1001100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114468,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207502,18);
WHEN "1001100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114574,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77597,18);
WHEN "1001100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114679,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156717,18);
WHEN "1001100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114784,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182836,18);
WHEN "1001100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114889,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156070,18);
WHEN "1001101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114994,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(76538,18);
WHEN "1001101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115098,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206498,18);
WHEN "1001101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21782,18);
WHEN "1001101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115307,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46791,18);
WHEN "1001101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115411,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19500,18);
WHEN "1001101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115514,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202167,18);
WHEN "1001101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70622,18);
WHEN "1001101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115721,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149267,18);
WHEN "1001110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115824,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176075,18);
WHEN "1001110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151160,18);
WHEN "1001110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74638,18);
WHEN "1001110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116132,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208767,18);
WHEN "1001110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116235,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29375,18);
WHEN "1001110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116337,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60864,18);
WHEN "1001110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116439,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41205,18);
WHEN "1001110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116540,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232655,18);
WHEN "1001111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116642,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111041,18);
WHEN "1001111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116743,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200765,18);
WHEN "1001111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116844,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239796,18);
WHEN "1001111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116945,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(228248,18);
WHEN "1001111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117046,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(166234,18);
WHEN "1001111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117147,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(53867,18);
WHEN "1001111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117247,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153404,18);
WHEN "1001111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202814,18);
WHEN "1010000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117447,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202209,18);
WHEN "1010000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117547,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151701,18);
WHEN "1010000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117647,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51403,18);
WHEN "1010000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117746,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163571,18);
WHEN "1010000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117845,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226171,18);
WHEN "1010000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117944,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239317,18);
WHEN "1010000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118043,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203118,18);
WHEN "1010000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117687,18);
WHEN "1010001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118240,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(245278,18);
WHEN "1010001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61714,18);
WHEN "1010001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118437,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91393,18);
WHEN "1010001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118535,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(72282,18);
WHEN "1010001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118633,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4490,18);
WHEN "1010001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118730,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150272,18);
WHEN "1010001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118827,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247594,18);
WHEN "1010001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118925,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34421,18);
WHEN "1010010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119022,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(35150,18);
WHEN "1010010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249890,18);
WHEN "1010010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119215,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154463,18);
WHEN "1010010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119312,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11120,18);
WHEN "1010010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119408,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82116,18);
WHEN "1010010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119504,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105413,18);
WHEN "1010010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119600,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81120,18);
WHEN "1010010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119696,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9344,18);
WHEN "1010011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152339,18);
WHEN "1010011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119886,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248066,18);
WHEN "1010011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34490,18);
WHEN "1010011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120077,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36005,18);
WHEN "1010011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120171,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252718,18);
WHEN "1010011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160448,18);
WHEN "1010011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120361,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21445,18);
WHEN "1010011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120455,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97961,18);
WHEN "1010100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120549,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(127955,18);
WHEN "1010100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111535,18);
WHEN "1010100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120737,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48807,18);
WHEN "1010100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120830,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202019,18);
WHEN "1010100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120924,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46988,18);
WHEN "1010100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121017,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108109,18);
WHEN "1010100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121110,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123341,18);
WHEN "1010100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92789,18);
WHEN "1010101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121296,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(16558,18);
WHEN "1010101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156895,18);
WHEN "1010101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121480,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251761,18);
WHEN "1010101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121573,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39116,18);
WHEN "1010101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121665,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(43350,18);
WHEN "1010101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2424,18);
WHEN "1010101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121848,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178584,18);
WHEN "1010101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121940,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47646,18);
WHEN "1010110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122031,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134000,18);
WHEN "1010110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122122,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175604,18);
WHEN "1010110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122213,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172562,18);
WHEN "1010110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122304,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124974,18);
WHEN "1010110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122395,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32943,18);
WHEN "1010110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122485,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158715,18);
WHEN "1010110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240246,18);
WHEN "1010110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122666,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15495,18);
WHEN "1010111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122756,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8850,18);
WHEN "1010111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122845,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(220412,18);
WHEN "1010111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125994,18);
WHEN "1010111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249984,18);
WHEN "1010111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123114,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68194,18);
WHEN "1010111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105012,18);
WHEN "1010111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123292,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98395,18);
WHEN "1010111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123381,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48441,18);
WHEN "1011000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123469,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217394,18);
WHEN "1011000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81065,18);
WHEN "1011000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123646,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163841,18);
WHEN "1011000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123734,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203676,18);
WHEN "1011000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200670,18);
WHEN "1011000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123910,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154921,18);
WHEN "1011000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(66526,18);
WHEN "1011000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197727,18);
WHEN "1011001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124173,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24335,18);
WHEN "1011001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124260,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70734,18);
WHEN "1011001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74878,18);
WHEN "1011001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124434,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36865,18);
WHEN "1011001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124520,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218933,18);
WHEN "1011001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124607,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(96893,18);
WHEN "1011001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124693,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195129,18);
WHEN "1011001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124779,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251593,18);
WHEN "1011010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124866,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4237,18);
WHEN "1011010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124951,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239588,18);
WHEN "1011010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125037,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171311,18);
WHEN "1011010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125123,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61644,18);
WHEN "1011010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172827,18);
WHEN "1011010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125293,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242811,18);
WHEN "1011010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125379,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9546,18);
WHEN "1011010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125463,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259559,18);
WHEN "1011011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206512,18);
WHEN "1011011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125633,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112644,18);
WHEN "1011011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125717,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240192,18);
WHEN "1011011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64962,18);
WHEN "1011011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125886,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111335,18);
WHEN "1011011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117261,18);
WHEN "1011011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126054,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82832,18);
WHEN "1011011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126138,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8142,18);
WHEN "1011100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155428,18);
WHEN "1011100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126305,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(492,18);
WHEN "1011100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67717,18);
WHEN "1011100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126471,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95050,18);
WHEN "1011100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126554,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82582,18);
WHEN "1011100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126637,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30405,18);
WHEN "1011100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126719,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200755,18);
WHEN "1011100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69435,18);
WHEN "1011101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160824,18);
WHEN "1011101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126966,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(212868,18);
WHEN "1011101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127048,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225659,18);
WHEN "1011101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127130,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199286,18);
WHEN "1011101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127212,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133839,18);
WHEN "1011101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127294,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29409,18);
WHEN "1011101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127375,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148230,18);
WHEN "1011101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127456,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(228246,18);
WHEN "1011110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127538,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7403,18);
WHEN "1011110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127619,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10079,18);
WHEN "1011110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127699,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236362,18);
WHEN "1011110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127780,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162053,18);
WHEN "1011110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49384,18);
WHEN "1011110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127941,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160588,18);
WHEN "1011110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128021,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233609,18);
WHEN "1011110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128102,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6390,18);
WHEN "1011111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128182,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3308,18);
WHEN "1011111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128261,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224450,18);
WHEN "1011111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145614,18);
WHEN "1011111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128421,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29034,18);
WHEN "1011111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128500,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136938,18);
WHEN "1011111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128579,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207270,18);
WHEN "1011111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128658,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240116,18);
WHEN "1011111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128737,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235563,18);
WHEN "1100000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128816,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193696,18);
WHEN "1100000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128895,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114602,18);
WHEN "1100000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128973,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260510,18);
WHEN "1100000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129052,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107217,18);
WHEN "1100000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129130,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179097,18);
WHEN "1100000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214091,18);
WHEN "1100000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129286,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(212284,18);
WHEN "1100000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173760,18);
WHEN "1100001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129442,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98604,18);
WHEN "1100001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129519,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249044,18);
WHEN "1100001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129597,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(100876,18);
WHEN "1100001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129674,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178473,18);
WHEN "1100001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129751,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(219772,18);
WHEN "1100001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129828,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224859,18);
WHEN "1100001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129905,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193817,18);
WHEN "1100001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126728,18);
WHEN "1100010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130059,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23675,18);
WHEN "1100010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130135,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146885,18);
WHEN "1100010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234296,18);
WHEN "1100010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130288,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23847,18);
WHEN "1100010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39908,18);
WHEN "1100010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20417,18);
WHEN "1100010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(227599,18);
WHEN "1100010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130591,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137248,18);
WHEN "1100011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130667,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11588,18);
WHEN "1100011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130742,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112847,18);
WHEN "1100011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130817,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178959,18);
WHEN "1100011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130892,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210006,18);
WHEN "1100011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130967,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206068,18);
WHEN "1100011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131042,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167226,18);
WHEN "1100011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131117,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93560,18);
WHEN "1100011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131191,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247293,18);
WHEN "1100100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104218,18);
WHEN "1100100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131340,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188702,18);
WHEN "1100100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131414,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(238680,18);
WHEN "1100100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131488,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254231,18);
WHEN "1100100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235435,18);
WHEN "1100100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182370,18);
WHEN "1100100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131710,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95115,18);
WHEN "1100100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235893,18);
WHEN "1100101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131857,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80492,18);
WHEN "1100101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131930,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153280,18);
WHEN "1100101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132003,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192190,18);
WHEN "1100101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132076,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197300,18);
WHEN "1100101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132149,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(168687,18);
WHEN "1100101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106429,18);
WHEN "1100101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132295,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10602,18);
WHEN "1100101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132367,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143428,18);
WHEN "1100110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132439,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242839,18);
WHEN "1100110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46768,18);
WHEN "1100110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132584,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79578,18);
WHEN "1100110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79203,18);
WHEN "1100110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132728,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45718,18);
WHEN "1100110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132799,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241342,18);
WHEN "1100110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132871,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(141864,18);
WHEN "1100110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9502,18);
WHEN "1100111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133014,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106476,18);
WHEN "1100111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170717,18);
WHEN "1100111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133156,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202300,18);
WHEN "1100111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133227,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201300,18);
WHEN "1100111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133298,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167790,18);
WHEN "1100111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133369,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101845,18);
WHEN "1100111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3539,18);
WHEN "1100111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133510,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(135090,18);
WHEN "1101000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234429,18);
WHEN "1101000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133651,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39483,18);
WHEN "1101000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133721,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74615,18);
WHEN "1101000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77754,18);
WHEN "1101000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48973,18);
WHEN "1101000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133930,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250488,18);
WHEN "1101000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134000,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158085,18);
WHEN "1101000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134070,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33979,18);
WHEN "1101001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134139,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140388,18);
WHEN "1101001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215238,18);
WHEN "1101001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134277,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258603,18);
WHEN "1101001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8409,18);
WHEN "1101001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134415,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251160,18);
WHEN "1101001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200497,18);
WHEN "1101001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134553,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(118633,18);
WHEN "1101001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134622,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(5640,18);
WHEN "1101010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123732,18);
WHEN "1101010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134758,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210837,18);
WHEN "1101010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134827,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4881,18);
WHEN "1101010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134895,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30222,18);
WHEN "1101010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134963,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24786,18);
WHEN "1101010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250788,18);
WHEN "1101010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135098,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184008,18);
WHEN "1101010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135166,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86662,18);
WHEN "1101011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135233,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(220961,18);
WHEN "1101011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135301,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62688,18);
WHEN "1101011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135368,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136199,18);
WHEN "1101011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135435,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179420,18);
WHEN "1101011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192419,18);
WHEN "1101011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135569,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175264,18);
WHEN "1101011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128025,18);
WHEN "1101011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135703,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50768,18);
WHEN "1101100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135769,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205708,18);
WHEN "1101100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68622,18);
WHEN "1101100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163868,18);
WHEN "1101100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(229368,18);
WHEN "1101100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136035,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3045,18);
WHEN "1101100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136101,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9256,18);
WHEN "1101100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136166,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248067,18);
WHEN "1101100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136232,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195258,18);
WHEN "1101101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136298,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113037,18);
WHEN "1101101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1473,18);
WHEN "1101101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136429,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122776,18);
WHEN "1101101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136494,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214867,18);
WHEN "1101101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136560,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15669,18);
WHEN "1101101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49536,18);
WHEN "1101101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54389,18);
WHEN "1101101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136755,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30294,18);
WHEN "1101110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136819,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239461,18);
WHEN "1101110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157665,18);
WHEN "1101110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136949,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47117,18);
WHEN "1101110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170026,18);
WHEN "1101110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137078,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2168,18);
WHEN "1101110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67895,18);
WHEN "1101110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137206,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105128,18);
WHEN "1101110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137270,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113931,18);
WHEN "1101111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137334,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94369,18);
WHEN "1101111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137398,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46504,18);
WHEN "1101111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137461,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232546,18);
WHEN "1101111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137525,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128269,18);
WHEN "1101111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137588,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258024,18);
WHEN "1101111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97588,18);
WHEN "1101111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137715,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171311,18);
WHEN "1101111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137778,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217112,18);
WHEN "1110000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137841,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235053,18);
WHEN "1110000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137904,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225198,18);
WHEN "1110000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137967,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187609,18);
WHEN "1110000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122349,18);
WHEN "1110000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138093,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29478,18);
WHEN "1110000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138155,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171204,18);
WHEN "1110000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138218,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23299,18);
WHEN "1110000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138280,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(110115,18);
WHEN "1110001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138342,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(169567,18);
WHEN "1110001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138404,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201718,18);
WHEN "1110001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206629,18);
WHEN "1110001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138528,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184361,18);
WHEN "1110001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138590,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134974,18);
WHEN "1110001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58530,18);
WHEN "1110001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138713,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217232,18);
WHEN "1110001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138775,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86854,18);
WHEN "1110010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191743,18);
WHEN "1110010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138898,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7673,18);
WHEN "1110010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58989,18);
WHEN "1110010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(83609,18);
WHEN "1110010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139081,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81593,18);
WHEN "1110010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52999,18);
WHEN "1110010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260030,18);
WHEN "1110010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139263,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178459,18);
WHEN "1110011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139324,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70488,18);
WHEN "1110011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139384,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198320,18);
WHEN "1110011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139445,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37726,18);
WHEN "1110011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139505,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113052,18);
WHEN "1110011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162212,18);
WHEN "1110011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(185266,18);
WHEN "1110011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139685,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182271,18);
WHEN "1110011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139745,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153286,18);
WHEN "1110100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139805,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98367,18);
WHEN "1110100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139865,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17573,18);
WHEN "1110100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139924,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173106,18);
WHEN "1110100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(40734,18);
WHEN "1110100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140043,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144803,18);
WHEN "1110100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140102,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(223226,18);
WHEN "1110100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140162,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(13916,18);
WHEN "1110100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41217,18);
WHEN "1110101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140280,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(43044,18);
WHEN "1110101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19451,18);
WHEN "1110101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232640,18);
WHEN "1110101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140456,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158378,18);
WHEN "1110101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58866,18);
WHEN "1110101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140573,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196304,18);
WHEN "1110101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140632,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46459,18);
WHEN "1110101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133676,18);
WHEN "1110110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140748,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195865,18);
WHEN "1110110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140806,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233082,18);
WHEN "1110110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140864,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(245382,18);
WHEN "1110110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140922,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232821,18);
WHEN "1110110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140980,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195453,18);
WHEN "1110110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141038,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133334,18);
WHEN "1110110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141096,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46517,18);
WHEN "1110110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141153,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197201,18);
WHEN "1110111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61153,18);
WHEN "1110111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141268,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162716,18);
WHEN "1110111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141325,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239798,18);
WHEN "1110111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141383,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30311,18);
WHEN "1110111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58595,18);
WHEN "1110111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141497,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62561,18);
WHEN "1110111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141554,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42262,18);
WHEN "1110111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141610,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259896,18);
WHEN "1111000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141667,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191228,18);
WHEN "1111000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141724,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98455,18);
WHEN "1111000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141780,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243774,18);
WHEN "1111000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141837,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102950,18);
WHEN "1111000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200324,18);
WHEN "1111000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141950,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11660,18);
WHEN "1111000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61299,18);
WHEN "1111000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142062,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87149,18);
WHEN "1111001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89262,18);
WHEN "1111001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142174,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67691,18);
WHEN "1111001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142230,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22487,18);
WHEN "1111001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142285,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215847,18);
WHEN "1111001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123533,18);
WHEN "1111001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7742,18);
WHEN "1111001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142452,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130668,18);
WHEN "1111001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230220,18);
WHEN "1111010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142563,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(44304,18);
WHEN "1111010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97259,18);
WHEN "1111010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126992,18);
WHEN "1111010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142728,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133554,18);
WHEN "1111010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(116996,18);
WHEN "1111010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142838,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77368,18);
WHEN "1111010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(14720,18);
WHEN "1111010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142947,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191247,18);
WHEN "1111011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143002,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82710,18);
WHEN "1111011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143056,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213448,18);
WHEN "1111011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143111,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59223,18);
WHEN "1111011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143165,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144372,18);
WHEN "1111011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143219,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206801,18);
WHEN "1111011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143273,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(246559,18);
WHEN "1111011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143328,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1553,18);
WHEN "1111011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143381,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258262,18);
WHEN "1111100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143435,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230304,18);
WHEN "1111100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143489,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179872,18);
WHEN "1111100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143543,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107014,18);
WHEN "1111100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143597,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11781,18);
WHEN "1111100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143650,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156363,18);
WHEN "1111100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143704,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(16522,18);
WHEN "1111100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(116595,18);
WHEN "1111100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143810,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(194484,18);
WHEN "1111101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143863,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250238,18);
WHEN "1111101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143917,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21762,18);
WHEN "1111101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33391,18);
WHEN "1111101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144023,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23028,18);
WHEN "1111101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144075,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252866,18);
WHEN "1111101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198664,18);
WHEN "1111101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144181,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122614,18);
WHEN "1111101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144234,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24761,18);
WHEN "1111110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144286,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167299,18);
WHEN "1111110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(25984,18);
WHEN "1111110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144391,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125154,18);
WHEN "1111110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144443,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202709,18);
WHEN "1111110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144495,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258698,18);
WHEN "1111110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31022,18);
WHEN "1111110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144600,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(44016,18);
WHEN "1111110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(35582,18);
WHEN "1111111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144704,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(5766,18);
WHEN "1111111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144755,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(216758,18);
WHEN "1111111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144317,18);
WHEN "1111111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144859,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50632,18);
WHEN "1111111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144910,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197892,18);
WHEN "1111111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144962,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61856,18);
WHEN "1111111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(145013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(166857,18);
WHEN "1111111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(145064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250795,18);
WHEN others =>
data(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_exp2_s5.vhd | 10 | 180176 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_s5
-- VHDL created on Fri Apr 5 13:35:21 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (5 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (22 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(32 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(11 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(2 downto 0);
signal memoryC0_uid123_exp2TabGen_q : std_logic_vector(27 downto 0);
signal memoryC1_uid125_exp2TabGen_q : std_logic_vector(20 downto 0);
signal memoryC2_uid127_exp2TabGen_q : std_logic_vector(11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (9 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (10 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q : std_logic_vector (6 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (22 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (5 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (22 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (7 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (28 downto 0);
signal ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (24 downto 0);
signal ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (20 downto 0);
signal ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (30 downto 0);
signal ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (29 downto 0);
signal ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q : std_logic_vector (32 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q : std_logic_vector (6 downto 0);
signal ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(13 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(13 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (13 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(13 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(13 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (13 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (23 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (22 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (8 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (5 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (10 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b : std_logic_vector (23 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(32 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(34 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(34 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (34 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (33 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (15 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (15 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (8 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (5 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (7 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (7 downto 0);
signal RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (28 downto 0);
signal RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (24 downto 0);
signal RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (20 downto 0);
signal lowRangeB_uid131_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid131_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid132_exp2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid132_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid137_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid137_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid138_exp2PolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid138_exp2PolyEval_b : std_logic_vector (21 downto 0);
signal RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (31 downto 0);
signal RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (30 downto 0);
signal RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (29 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (32 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (9 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (22 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (22 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (32 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (32 downto 0);
signal yT1_uid129_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid129_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid133_exp2PolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid139_exp2PolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (22 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (6 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (16 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal s1_uid131_uid134_exp2PolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid137_uid140_exp2PolyEval_q : std_logic_vector (30 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (28 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (23 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (22 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (22 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable(LOGICAL,342)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q <= not ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,343)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top(CONSTANT,339)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q <= "011";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp(LOGICAL,340)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q <= "1" when ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a = ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b else "0";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg(REG,341)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,344)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,345)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(31 downto 31);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,187)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(22 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(22 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,184)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((32 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((34 downto 33 => onesCmpFxpIn_uid35_fpExp2Test_q(32)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(33 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(32 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(32 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 32);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,278)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000";
--rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((2 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 3, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,256)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000";
--rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((11 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 12, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((32 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 33, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,151)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 16);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,150)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,149)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "100001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(30 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(30 downto 23);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000111";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(8 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(5 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(5 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,196)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,147)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((10 downto 9 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(8)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(11);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,148)@1
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 12);
--ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,266)@2
ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= cstZeroWE_uid13_fpExp2Test_q;
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 8);
--ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,262)@2
ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 4);
--ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,258)@2
ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,153)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(3 downto 0);
rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a(DELAY,319)@1
ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,152)@2
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 3);
--ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,284)@3
ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 2);
--ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,280)@3
ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@1
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,277)@2
ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xout => ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 1);
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@3
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q & RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b;
--ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d(DELAY,289)@3
ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, xout => ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,155)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(1 downto 0);
rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in(1 downto 0);
--ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a(DELAY,321)@1
ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,154)@3
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(32 downto 23);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,156)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(9)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(10 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(7 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(7 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,238)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "00000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,233)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@0
InvSignX_uid62_fpExp2Test_a <= signX_uid7_fpExp2Test_b;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(8 downto 8);
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@0
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_b;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,230)@0
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,212)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,157)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(10)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(13);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,213)@0
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--posInf_uid67_fpExp2Test(LOGICAL,66)@0
posInf_uid67_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,228)@0
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,218)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@0
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_b;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= signX_uid7_fpExp2Test_b;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,217)@0
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(10)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(13);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,159)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (expRPostExc_uid78_fpExp2Test_s, en, cstZeroWE_uid13_fpExp2Test_q, ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, cstAllOWE_uid16_fpExp2Test_q, cstAllOWE_uid16_fpExp2Test_q)
BEGIN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,333)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt(COUNTER,335)
-- every=1, low=0, high=3, step=1, init=1
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i,2));
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg(REG,336)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux(MUX,337)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux: PROCESS (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s, ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q, ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,334)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 2,
numwords_a => 4,
width_b => 8,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(7 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "00000000000000000000001";
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q(22 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(22 downto 0);
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(22 downto 16);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0(REG,160)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid127_exp2TabGen(LOOKUP,126)@5
memoryC2_uid127_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid127_exp2TabGen_q <= "001111011001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q) IS
WHEN "0000000" => memoryC2_uid127_exp2TabGen_q <= "001111011001";
WHEN "0000001" => memoryC2_uid127_exp2TabGen_q <= "001111100010";
WHEN "0000010" => memoryC2_uid127_exp2TabGen_q <= "001111100110";
WHEN "0000011" => memoryC2_uid127_exp2TabGen_q <= "001111101011";
WHEN "0000100" => memoryC2_uid127_exp2TabGen_q <= "001111110000";
WHEN "0000101" => memoryC2_uid127_exp2TabGen_q <= "001111110111";
WHEN "0000110" => memoryC2_uid127_exp2TabGen_q <= "001111111100";
WHEN "0000111" => memoryC2_uid127_exp2TabGen_q <= "010000000001";
WHEN "0001000" => memoryC2_uid127_exp2TabGen_q <= "010000000110";
WHEN "0001001" => memoryC2_uid127_exp2TabGen_q <= "010000001101";
WHEN "0001010" => memoryC2_uid127_exp2TabGen_q <= "010000010010";
WHEN "0001011" => memoryC2_uid127_exp2TabGen_q <= "010000010111";
WHEN "0001100" => memoryC2_uid127_exp2TabGen_q <= "010000011101";
WHEN "0001101" => memoryC2_uid127_exp2TabGen_q <= "010000100011";
WHEN "0001110" => memoryC2_uid127_exp2TabGen_q <= "010000101001";
WHEN "0001111" => memoryC2_uid127_exp2TabGen_q <= "010000101101";
WHEN "0010000" => memoryC2_uid127_exp2TabGen_q <= "010000110011";
WHEN "0010001" => memoryC2_uid127_exp2TabGen_q <= "010000111010";
WHEN "0010010" => memoryC2_uid127_exp2TabGen_q <= "010001000000";
WHEN "0010011" => memoryC2_uid127_exp2TabGen_q <= "010001000101";
WHEN "0010100" => memoryC2_uid127_exp2TabGen_q <= "010001001011";
WHEN "0010101" => memoryC2_uid127_exp2TabGen_q <= "010001010010";
WHEN "0010110" => memoryC2_uid127_exp2TabGen_q <= "010001010110";
WHEN "0010111" => memoryC2_uid127_exp2TabGen_q <= "010001011011";
WHEN "0011000" => memoryC2_uid127_exp2TabGen_q <= "010001100101";
WHEN "0011001" => memoryC2_uid127_exp2TabGen_q <= "010001101001";
WHEN "0011010" => memoryC2_uid127_exp2TabGen_q <= "010001110011";
WHEN "0011011" => memoryC2_uid127_exp2TabGen_q <= "010001110111";
WHEN "0011100" => memoryC2_uid127_exp2TabGen_q <= "010001111011";
WHEN "0011101" => memoryC2_uid127_exp2TabGen_q <= "010010000011";
WHEN "0011110" => memoryC2_uid127_exp2TabGen_q <= "010010001001";
WHEN "0011111" => memoryC2_uid127_exp2TabGen_q <= "010010001101";
WHEN "0100000" => memoryC2_uid127_exp2TabGen_q <= "010010010110";
WHEN "0100001" => memoryC2_uid127_exp2TabGen_q <= "010010011101";
WHEN "0100010" => memoryC2_uid127_exp2TabGen_q <= "010010100011";
WHEN "0100011" => memoryC2_uid127_exp2TabGen_q <= "010010101001";
WHEN "0100100" => memoryC2_uid127_exp2TabGen_q <= "010010101111";
WHEN "0100101" => memoryC2_uid127_exp2TabGen_q <= "010010110100";
WHEN "0100110" => memoryC2_uid127_exp2TabGen_q <= "010010111100";
WHEN "0100111" => memoryC2_uid127_exp2TabGen_q <= "010011000011";
WHEN "0101000" => memoryC2_uid127_exp2TabGen_q <= "010011001001";
WHEN "0101001" => memoryC2_uid127_exp2TabGen_q <= "010011001110";
WHEN "0101010" => memoryC2_uid127_exp2TabGen_q <= "010011010111";
WHEN "0101011" => memoryC2_uid127_exp2TabGen_q <= "010011011100";
WHEN "0101100" => memoryC2_uid127_exp2TabGen_q <= "010011100011";
WHEN "0101101" => memoryC2_uid127_exp2TabGen_q <= "010011101001";
WHEN "0101110" => memoryC2_uid127_exp2TabGen_q <= "010011110011";
WHEN "0101111" => memoryC2_uid127_exp2TabGen_q <= "010011110111";
WHEN "0110000" => memoryC2_uid127_exp2TabGen_q <= "010011111101";
WHEN "0110001" => memoryC2_uid127_exp2TabGen_q <= "010100001001";
WHEN "0110010" => memoryC2_uid127_exp2TabGen_q <= "010100001111";
WHEN "0110011" => memoryC2_uid127_exp2TabGen_q <= "010100010110";
WHEN "0110100" => memoryC2_uid127_exp2TabGen_q <= "010100011110";
WHEN "0110101" => memoryC2_uid127_exp2TabGen_q <= "010100100101";
WHEN "0110110" => memoryC2_uid127_exp2TabGen_q <= "010100101010";
WHEN "0110111" => memoryC2_uid127_exp2TabGen_q <= "010100110000";
WHEN "0111000" => memoryC2_uid127_exp2TabGen_q <= "010100110110";
WHEN "0111001" => memoryC2_uid127_exp2TabGen_q <= "010100111111";
WHEN "0111010" => memoryC2_uid127_exp2TabGen_q <= "010101000101";
WHEN "0111011" => memoryC2_uid127_exp2TabGen_q <= "010101001101";
WHEN "0111100" => memoryC2_uid127_exp2TabGen_q <= "010101010101";
WHEN "0111101" => memoryC2_uid127_exp2TabGen_q <= "010101011011";
WHEN "0111110" => memoryC2_uid127_exp2TabGen_q <= "010101100101";
WHEN "0111111" => memoryC2_uid127_exp2TabGen_q <= "010101101101";
WHEN "1000000" => memoryC2_uid127_exp2TabGen_q <= "010101110100";
WHEN "1000001" => memoryC2_uid127_exp2TabGen_q <= "010101111010";
WHEN "1000010" => memoryC2_uid127_exp2TabGen_q <= "010110000001";
WHEN "1000011" => memoryC2_uid127_exp2TabGen_q <= "010110001001";
WHEN "1000100" => memoryC2_uid127_exp2TabGen_q <= "010110010001";
WHEN "1000101" => memoryC2_uid127_exp2TabGen_q <= "010110011000";
WHEN "1000110" => memoryC2_uid127_exp2TabGen_q <= "010110100011";
WHEN "1000111" => memoryC2_uid127_exp2TabGen_q <= "010110101001";
WHEN "1001000" => memoryC2_uid127_exp2TabGen_q <= "010110110000";
WHEN "1001001" => memoryC2_uid127_exp2TabGen_q <= "010110111001";
WHEN "1001010" => memoryC2_uid127_exp2TabGen_q <= "010111000010";
WHEN "1001011" => memoryC2_uid127_exp2TabGen_q <= "010111001000";
WHEN "1001100" => memoryC2_uid127_exp2TabGen_q <= "010111001111";
WHEN "1001101" => memoryC2_uid127_exp2TabGen_q <= "010111011011";
WHEN "1001110" => memoryC2_uid127_exp2TabGen_q <= "010111100001";
WHEN "1001111" => memoryC2_uid127_exp2TabGen_q <= "010111100111";
WHEN "1010000" => memoryC2_uid127_exp2TabGen_q <= "010111110100";
WHEN "1010001" => memoryC2_uid127_exp2TabGen_q <= "010111111010";
WHEN "1010010" => memoryC2_uid127_exp2TabGen_q <= "011000000010";
WHEN "1010011" => memoryC2_uid127_exp2TabGen_q <= "011000001010";
WHEN "1010100" => memoryC2_uid127_exp2TabGen_q <= "011000010011";
WHEN "1010101" => memoryC2_uid127_exp2TabGen_q <= "011000011100";
WHEN "1010110" => memoryC2_uid127_exp2TabGen_q <= "011000100011";
WHEN "1010111" => memoryC2_uid127_exp2TabGen_q <= "011000101101";
WHEN "1011000" => memoryC2_uid127_exp2TabGen_q <= "011000110101";
WHEN "1011001" => memoryC2_uid127_exp2TabGen_q <= "011000111111";
WHEN "1011010" => memoryC2_uid127_exp2TabGen_q <= "011001000110";
WHEN "1011011" => memoryC2_uid127_exp2TabGen_q <= "011001001101";
WHEN "1011100" => memoryC2_uid127_exp2TabGen_q <= "011001011001";
WHEN "1011101" => memoryC2_uid127_exp2TabGen_q <= "011001100000";
WHEN "1011110" => memoryC2_uid127_exp2TabGen_q <= "011001101001";
WHEN "1011111" => memoryC2_uid127_exp2TabGen_q <= "011001110010";
WHEN "1100000" => memoryC2_uid127_exp2TabGen_q <= "011001111001";
WHEN "1100001" => memoryC2_uid127_exp2TabGen_q <= "011010000011";
WHEN "1100010" => memoryC2_uid127_exp2TabGen_q <= "011010001100";
WHEN "1100011" => memoryC2_uid127_exp2TabGen_q <= "011010011001";
WHEN "1100100" => memoryC2_uid127_exp2TabGen_q <= "011010100000";
WHEN "1100101" => memoryC2_uid127_exp2TabGen_q <= "011010101000";
WHEN "1100110" => memoryC2_uid127_exp2TabGen_q <= "011010110010";
WHEN "1100111" => memoryC2_uid127_exp2TabGen_q <= "011010111011";
WHEN "1101000" => memoryC2_uid127_exp2TabGen_q <= "011011000100";
WHEN "1101001" => memoryC2_uid127_exp2TabGen_q <= "011011001101";
WHEN "1101010" => memoryC2_uid127_exp2TabGen_q <= "011011011001";
WHEN "1101011" => memoryC2_uid127_exp2TabGen_q <= "011011100001";
WHEN "1101100" => memoryC2_uid127_exp2TabGen_q <= "011011101001";
WHEN "1101101" => memoryC2_uid127_exp2TabGen_q <= "011011110010";
WHEN "1101110" => memoryC2_uid127_exp2TabGen_q <= "011011111111";
WHEN "1101111" => memoryC2_uid127_exp2TabGen_q <= "011100000111";
WHEN "1110000" => memoryC2_uid127_exp2TabGen_q <= "011100010010";
WHEN "1110001" => memoryC2_uid127_exp2TabGen_q <= "011100011100";
WHEN "1110010" => memoryC2_uid127_exp2TabGen_q <= "011100100110";
WHEN "1110011" => memoryC2_uid127_exp2TabGen_q <= "011100110000";
WHEN "1110100" => memoryC2_uid127_exp2TabGen_q <= "011100111001";
WHEN "1110101" => memoryC2_uid127_exp2TabGen_q <= "011101000011";
WHEN "1110110" => memoryC2_uid127_exp2TabGen_q <= "011101001110";
WHEN "1110111" => memoryC2_uid127_exp2TabGen_q <= "011101011000";
WHEN "1111000" => memoryC2_uid127_exp2TabGen_q <= "011101100001";
WHEN "1111001" => memoryC2_uid127_exp2TabGen_q <= "011101101001";
WHEN "1111010" => memoryC2_uid127_exp2TabGen_q <= "011101111000";
WHEN "1111011" => memoryC2_uid127_exp2TabGen_q <= "011110000001";
WHEN "1111100" => memoryC2_uid127_exp2TabGen_q <= "011110001010";
WHEN "1111101" => memoryC2_uid127_exp2TabGen_q <= "011110010110";
WHEN "1111110" => memoryC2_uid127_exp2TabGen_q <= "011110100010";
WHEN "1111111" => memoryC2_uid127_exp2TabGen_q <= "011110101011";
WHEN OTHERS =>
memoryC2_uid127_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,200)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(15 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(15 downto 0);
--yT1_uid129_exp2PolyEval(BITSELECT,128)@5
yT1_uid129_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid129_exp2PolyEval_b <= yT1_uid129_exp2PolyEval_in(15 downto 4);
--reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0(REG,161)@5
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q <= yT1_uid129_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid142_pT1_uid130_exp2PolyEval(MULT,141)@6
prodXY_uid142_pT1_uid130_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid142_pT1_uid130_exp2PolyEval_a),13)) * SIGNED(prodXY_uid142_pT1_uid130_exp2PolyEval_b);
prodXY_uid142_pT1_uid130_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_a <= (others => '0');
prodXY_uid142_pT1_uid130_exp2PolyEval_b <= (others => '0');
prodXY_uid142_pT1_uid130_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_a <= reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q;
prodXY_uid142_pT1_uid130_exp2PolyEval_b <= memoryC2_uid127_exp2TabGen_q;
prodXY_uid142_pT1_uid130_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid142_pT1_uid130_exp2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid142_pT1_uid130_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_q <= prodXY_uid142_pT1_uid130_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval(BITSELECT,142)@9
prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in <= prodXY_uid142_pT1_uid130_exp2PolyEval_q;
prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in(23 downto 11);
--highBBits_uid132_exp2PolyEval(BITSELECT,131)@9
highBBits_uid132_exp2PolyEval_in <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b;
highBBits_uid132_exp2PolyEval_b <= highBBits_uid132_exp2PolyEval_in(12 downto 1);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a(DELAY,293)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid125_exp2TabGen(LOOKUP,124)@8
memoryC1_uid125_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid125_exp2TabGen_q <= "001011000101110010001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q) IS
WHEN "0000000" => memoryC1_uid125_exp2TabGen_q <= "001011000101110010001";
WHEN "0000001" => memoryC1_uid125_exp2TabGen_q <= "001011001001101000011";
WHEN "0000010" => memoryC1_uid125_exp2TabGen_q <= "001011001101100000100";
WHEN "0000011" => memoryC1_uid125_exp2TabGen_q <= "001011010001011010000";
WHEN "0000100" => memoryC1_uid125_exp2TabGen_q <= "001011010101010100101";
WHEN "0000101" => memoryC1_uid125_exp2TabGen_q <= "001011011001010000100";
WHEN "0000110" => memoryC1_uid125_exp2TabGen_q <= "001011011101001110001";
WHEN "0000111" => memoryC1_uid125_exp2TabGen_q <= "001011100001001100111";
WHEN "0001000" => memoryC1_uid125_exp2TabGen_q <= "001011100101001101010";
WHEN "0001001" => memoryC1_uid125_exp2TabGen_q <= "001011101001001110101";
WHEN "0001010" => memoryC1_uid125_exp2TabGen_q <= "001011101101010001101";
WHEN "0001011" => memoryC1_uid125_exp2TabGen_q <= "001011110001010110001";
WHEN "0001100" => memoryC1_uid125_exp2TabGen_q <= "001011110101011011111";
WHEN "0001101" => memoryC1_uid125_exp2TabGen_q <= "001011111001100011001";
WHEN "0001110" => memoryC1_uid125_exp2TabGen_q <= "001011111101101011101";
WHEN "0001111" => memoryC1_uid125_exp2TabGen_q <= "001100000001110110000";
WHEN "0010000" => memoryC1_uid125_exp2TabGen_q <= "001100000110000001100";
WHEN "0010001" => memoryC1_uid125_exp2TabGen_q <= "001100001010001110011";
WHEN "0010010" => memoryC1_uid125_exp2TabGen_q <= "001100001110011100110";
WHEN "0010011" => memoryC1_uid125_exp2TabGen_q <= "001100010010101100110";
WHEN "0010100" => memoryC1_uid125_exp2TabGen_q <= "001100010110111110010";
WHEN "0010101" => memoryC1_uid125_exp2TabGen_q <= "001100011011010000111";
WHEN "0010110" => memoryC1_uid125_exp2TabGen_q <= "001100011111100101100";
WHEN "0010111" => memoryC1_uid125_exp2TabGen_q <= "001100100011111011100";
WHEN "0011000" => memoryC1_uid125_exp2TabGen_q <= "001100101000010010011";
WHEN "0011001" => memoryC1_uid125_exp2TabGen_q <= "001100101100101011100";
WHEN "0011010" => memoryC1_uid125_exp2TabGen_q <= "001100110001000101100";
WHEN "0011011" => memoryC1_uid125_exp2TabGen_q <= "001100110101100001101";
WHEN "0011100" => memoryC1_uid125_exp2TabGen_q <= "001100111001111111100";
WHEN "0011101" => memoryC1_uid125_exp2TabGen_q <= "001100111110011110011";
WHEN "0011110" => memoryC1_uid125_exp2TabGen_q <= "001101000010111110111";
WHEN "0011111" => memoryC1_uid125_exp2TabGen_q <= "001101000111100001011";
WHEN "0100000" => memoryC1_uid125_exp2TabGen_q <= "001101001100000100110";
WHEN "0100001" => memoryC1_uid125_exp2TabGen_q <= "001101010000101010001";
WHEN "0100010" => memoryC1_uid125_exp2TabGen_q <= "001101010101010001000";
WHEN "0100011" => memoryC1_uid125_exp2TabGen_q <= "001101011001111001101";
WHEN "0100100" => memoryC1_uid125_exp2TabGen_q <= "001101011110100011110";
WHEN "0100101" => memoryC1_uid125_exp2TabGen_q <= "001101100011001111110";
WHEN "0100110" => memoryC1_uid125_exp2TabGen_q <= "001101100111111101000";
WHEN "0100111" => memoryC1_uid125_exp2TabGen_q <= "001101101100101011111";
WHEN "0101000" => memoryC1_uid125_exp2TabGen_q <= "001101110001011100101";
WHEN "0101001" => memoryC1_uid125_exp2TabGen_q <= "001101110110001111001";
WHEN "0101010" => memoryC1_uid125_exp2TabGen_q <= "001101111011000010110";
WHEN "0101011" => memoryC1_uid125_exp2TabGen_q <= "001101111111111000110";
WHEN "0101100" => memoryC1_uid125_exp2TabGen_q <= "001110000100110000000";
WHEN "0101101" => memoryC1_uid125_exp2TabGen_q <= "001110001001101001001";
WHEN "0101110" => memoryC1_uid125_exp2TabGen_q <= "001110001110100011011";
WHEN "0101111" => memoryC1_uid125_exp2TabGen_q <= "001110010011100000010";
WHEN "0110000" => memoryC1_uid125_exp2TabGen_q <= "001110011000011110100";
WHEN "0110001" => memoryC1_uid125_exp2TabGen_q <= "001110011101011101110";
WHEN "0110010" => memoryC1_uid125_exp2TabGen_q <= "001110100010011111100";
WHEN "0110011" => memoryC1_uid125_exp2TabGen_q <= "001110100111100010111";
WHEN "0110100" => memoryC1_uid125_exp2TabGen_q <= "001110101100100111111";
WHEN "0110101" => memoryC1_uid125_exp2TabGen_q <= "001110110001101110110";
WHEN "0110110" => memoryC1_uid125_exp2TabGen_q <= "001110110110110111101";
WHEN "0110111" => memoryC1_uid125_exp2TabGen_q <= "001110111100000010010";
WHEN "0111000" => memoryC1_uid125_exp2TabGen_q <= "001111000001001110101";
WHEN "0111001" => memoryC1_uid125_exp2TabGen_q <= "001111000110011100011";
WHEN "0111010" => memoryC1_uid125_exp2TabGen_q <= "001111001011101100100";
WHEN "0111011" => memoryC1_uid125_exp2TabGen_q <= "001111010000111110001";
WHEN "0111100" => memoryC1_uid125_exp2TabGen_q <= "001111010110010001100";
WHEN "0111101" => memoryC1_uid125_exp2TabGen_q <= "001111011011100111000";
WHEN "0111110" => memoryC1_uid125_exp2TabGen_q <= "001111100000111101111";
WHEN "0111111" => memoryC1_uid125_exp2TabGen_q <= "001111100110010111000";
WHEN "1000000" => memoryC1_uid125_exp2TabGen_q <= "001111101011110001111";
WHEN "1000001" => memoryC1_uid125_exp2TabGen_q <= "001111110001001111000";
WHEN "1000010" => memoryC1_uid125_exp2TabGen_q <= "001111110110101101110";
WHEN "1000011" => memoryC1_uid125_exp2TabGen_q <= "001111111100001110011";
WHEN "1000100" => memoryC1_uid125_exp2TabGen_q <= "010000000001110000111";
WHEN "1000101" => memoryC1_uid125_exp2TabGen_q <= "010000000111010101011";
WHEN "1000110" => memoryC1_uid125_exp2TabGen_q <= "010000001100111011011";
WHEN "1000111" => memoryC1_uid125_exp2TabGen_q <= "010000010010100100000";
WHEN "1001000" => memoryC1_uid125_exp2TabGen_q <= "010000011000001110011";
WHEN "1001001" => memoryC1_uid125_exp2TabGen_q <= "010000011101111010101";
WHEN "1001010" => memoryC1_uid125_exp2TabGen_q <= "010000100011101000101";
WHEN "1001011" => memoryC1_uid125_exp2TabGen_q <= "010000101001011001001";
WHEN "1001100" => memoryC1_uid125_exp2TabGen_q <= "010000101111001011100";
WHEN "1001101" => memoryC1_uid125_exp2TabGen_q <= "010000110100111111010";
WHEN "1001110" => memoryC1_uid125_exp2TabGen_q <= "010000111010110101110";
WHEN "1001111" => memoryC1_uid125_exp2TabGen_q <= "010001000000101110011";
WHEN "1010000" => memoryC1_uid125_exp2TabGen_q <= "010001000110101000001";
WHEN "1010001" => memoryC1_uid125_exp2TabGen_q <= "010001001100100100110";
WHEN "1010010" => memoryC1_uid125_exp2TabGen_q <= "010001010010100011011";
WHEN "1010011" => memoryC1_uid125_exp2TabGen_q <= "010001011000100011111";
WHEN "1010100" => memoryC1_uid125_exp2TabGen_q <= "010001011110100110100";
WHEN "1010101" => memoryC1_uid125_exp2TabGen_q <= "010001100100101011001";
WHEN "1010110" => memoryC1_uid125_exp2TabGen_q <= "010001101010110010001";
WHEN "1010111" => memoryC1_uid125_exp2TabGen_q <= "010001110000111011000";
WHEN "1011000" => memoryC1_uid125_exp2TabGen_q <= "010001110111000110000";
WHEN "1011001" => memoryC1_uid125_exp2TabGen_q <= "010001111101010011001";
WHEN "1011010" => memoryC1_uid125_exp2TabGen_q <= "010010000011100010110";
WHEN "1011011" => memoryC1_uid125_exp2TabGen_q <= "010010001001110100100";
WHEN "1011100" => memoryC1_uid125_exp2TabGen_q <= "010010010000000111111";
WHEN "1011101" => memoryC1_uid125_exp2TabGen_q <= "010010010110011110000";
WHEN "1011110" => memoryC1_uid125_exp2TabGen_q <= "010010011100110110010";
WHEN "1011111" => memoryC1_uid125_exp2TabGen_q <= "010010100011010000100";
WHEN "1100000" => memoryC1_uid125_exp2TabGen_q <= "010010101001101101011";
WHEN "1100001" => memoryC1_uid125_exp2TabGen_q <= "010010110000001100001";
WHEN "1100010" => memoryC1_uid125_exp2TabGen_q <= "010010110110101101001";
WHEN "1100011" => memoryC1_uid125_exp2TabGen_q <= "010010111101010000000";
WHEN "1100100" => memoryC1_uid125_exp2TabGen_q <= "010011000011110101111";
WHEN "1100101" => memoryC1_uid125_exp2TabGen_q <= "010011001010011110000";
WHEN "1100110" => memoryC1_uid125_exp2TabGen_q <= "010011010001001000001";
WHEN "1100111" => memoryC1_uid125_exp2TabGen_q <= "010011010111110100101";
WHEN "1101000" => memoryC1_uid125_exp2TabGen_q <= "010011011110100011101";
WHEN "1101001" => memoryC1_uid125_exp2TabGen_q <= "010011100101010100110";
WHEN "1101010" => memoryC1_uid125_exp2TabGen_q <= "010011101100001000000";
WHEN "1101011" => memoryC1_uid125_exp2TabGen_q <= "010011110010111110001";
WHEN "1101100" => memoryC1_uid125_exp2TabGen_q <= "010011111001110110101";
WHEN "1101101" => memoryC1_uid125_exp2TabGen_q <= "010100000000110001011";
WHEN "1101110" => memoryC1_uid125_exp2TabGen_q <= "010100000111101110000";
WHEN "1101111" => memoryC1_uid125_exp2TabGen_q <= "010100001110101101110";
WHEN "1110000" => memoryC1_uid125_exp2TabGen_q <= "010100010101101111101";
WHEN "1110001" => memoryC1_uid125_exp2TabGen_q <= "010100011100110011111";
WHEN "1110010" => memoryC1_uid125_exp2TabGen_q <= "010100100011111010110";
WHEN "1110011" => memoryC1_uid125_exp2TabGen_q <= "010100101011000100000";
WHEN "1110100" => memoryC1_uid125_exp2TabGen_q <= "010100110010001111111";
WHEN "1110101" => memoryC1_uid125_exp2TabGen_q <= "010100111001011110010";
WHEN "1110110" => memoryC1_uid125_exp2TabGen_q <= "010101000000101110111";
WHEN "1110111" => memoryC1_uid125_exp2TabGen_q <= "010101001000000010010";
WHEN "1111000" => memoryC1_uid125_exp2TabGen_q <= "010101001111011000001";
WHEN "1111001" => memoryC1_uid125_exp2TabGen_q <= "010101010110110000111";
WHEN "1111010" => memoryC1_uid125_exp2TabGen_q <= "010101011110001011010";
WHEN "1111011" => memoryC1_uid125_exp2TabGen_q <= "010101100101101001000";
WHEN "1111100" => memoryC1_uid125_exp2TabGen_q <= "010101101101001001010";
WHEN "1111101" => memoryC1_uid125_exp2TabGen_q <= "010101110100101011110";
WHEN "1111110" => memoryC1_uid125_exp2TabGen_q <= "010101111100010001000";
WHEN "1111111" => memoryC1_uid125_exp2TabGen_q <= "010110000011111001010";
WHEN OTHERS =>
memoryC1_uid125_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid133_exp2PolyEval(ADD,132)@9
sumAHighB_uid133_exp2PolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid125_exp2TabGen_q(20)) & memoryC1_uid125_exp2TabGen_q);
sumAHighB_uid133_exp2PolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid132_exp2PolyEval_b(11)) & highBBits_uid132_exp2PolyEval_b);
sumAHighB_uid133_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid133_exp2PolyEval_a) + SIGNED(sumAHighB_uid133_exp2PolyEval_b));
sumAHighB_uid133_exp2PolyEval_q <= sumAHighB_uid133_exp2PolyEval_o(21 downto 0);
--lowRangeB_uid131_exp2PolyEval(BITSELECT,130)@9
lowRangeB_uid131_exp2PolyEval_in <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b(0 downto 0);
lowRangeB_uid131_exp2PolyEval_b <= lowRangeB_uid131_exp2PolyEval_in(0 downto 0);
--s1_uid131_uid134_exp2PolyEval(BITJOIN,133)@9
s1_uid131_uid134_exp2PolyEval_q <= sumAHighB_uid133_exp2PolyEval_q & lowRangeB_uid131_exp2PolyEval_b;
--reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1(REG,164)@9
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q <= s1_uid131_uid134_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor(LOGICAL,354)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a or ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg(REG,352)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena(REG,355)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd(LOGICAL,356)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0(REG,163)@5
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q <= yPPolyEval_uid48_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg(DELAY,346)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q, xout => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt(COUNTER,348)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg(REG,349)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux(MUX,350)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem(DUALMEM,347)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid145_pT2_uid136_exp2PolyEval(MULT,144)@10
prodXY_uid145_pT2_uid136_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid145_pT2_uid136_exp2PolyEval_a),17)) * SIGNED(prodXY_uid145_pT2_uid136_exp2PolyEval_b);
prodXY_uid145_pT2_uid136_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_a <= (others => '0');
prodXY_uid145_pT2_uid136_exp2PolyEval_b <= (others => '0');
prodXY_uid145_pT2_uid136_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_a <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q;
prodXY_uid145_pT2_uid136_exp2PolyEval_b <= reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q;
prodXY_uid145_pT2_uid136_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid145_pT2_uid136_exp2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid145_pT2_uid136_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_q <= prodXY_uid145_pT2_uid136_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval(BITSELECT,145)@13
prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in <= prodXY_uid145_pT2_uid136_exp2PolyEval_q;
prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in(38 downto 15);
--highBBits_uid138_exp2PolyEval(BITSELECT,137)@13
highBBits_uid138_exp2PolyEval_in <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b;
highBBits_uid138_exp2PolyEval_b <= highBBits_uid138_exp2PolyEval_in(23 downto 2);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor(LOGICAL,367)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top(CONSTANT,363)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q <= "0100";
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp(LOGICAL,364)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q <= "1" when ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a = ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b else "0";
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg(REG,365)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena(REG,368)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd(LOGICAL,369)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg(DELAY,357)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt(COUNTER,359)
-- every=1, low=0, high=4, step=1, init=1
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i = 3 THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i - 4;
ELSE
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i,3));
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg(REG,360)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux(MUX,361)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux: PROCESS (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s, ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q, ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s IS
WHEN "0" => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q;
WHEN "1" => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem(DUALMEM,358)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0(REG,165)@11
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid123_exp2TabGen(LOOKUP,122)@12
memoryC0_uid123_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid123_exp2TabGen_q <= "0100000000000000000000000100";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q) IS
WHEN "0000000" => memoryC0_uid123_exp2TabGen_q <= "0100000000000000000000000100";
WHEN "0000001" => memoryC0_uid123_exp2TabGen_q <= "0100000001011000111101101111";
WHEN "0000010" => memoryC0_uid123_exp2TabGen_q <= "0100000010110010011010010100";
WHEN "0000011" => memoryC0_uid123_exp2TabGen_q <= "0100000100001100010101111110";
WHEN "0000100" => memoryC0_uid123_exp2TabGen_q <= "0100000101100110110000111001";
WHEN "0000101" => memoryC0_uid123_exp2TabGen_q <= "0100000111000001101011001111";
WHEN "0000110" => memoryC0_uid123_exp2TabGen_q <= "0100001000011101000101001010";
WHEN "0000111" => memoryC0_uid123_exp2TabGen_q <= "0100001001111000111110110111";
WHEN "0001000" => memoryC0_uid123_exp2TabGen_q <= "0100001011010101011000011111";
WHEN "0001001" => memoryC0_uid123_exp2TabGen_q <= "0100001100110010010010001111";
WHEN "0001010" => memoryC0_uid123_exp2TabGen_q <= "0100001110001111101100010001";
WHEN "0001011" => memoryC0_uid123_exp2TabGen_q <= "0100001111101101100110110000";
WHEN "0001100" => memoryC0_uid123_exp2TabGen_q <= "0100010001001100000001111000";
WHEN "0001101" => memoryC0_uid123_exp2TabGen_q <= "0100010010101010111101110100";
WHEN "0001110" => memoryC0_uid123_exp2TabGen_q <= "0100010100001010011010110000";
WHEN "0001111" => memoryC0_uid123_exp2TabGen_q <= "0100010101101010011000110110";
WHEN "0010000" => memoryC0_uid123_exp2TabGen_q <= "0100010111001010111000010011";
WHEN "0010001" => memoryC0_uid123_exp2TabGen_q <= "0100011000101011111001010010";
WHEN "0010010" => memoryC0_uid123_exp2TabGen_q <= "0100011010001101011011111111";
WHEN "0010011" => memoryC0_uid123_exp2TabGen_q <= "0100011011101111100000100101";
WHEN "0010100" => memoryC0_uid123_exp2TabGen_q <= "0100011101010010000111010000";
WHEN "0010101" => memoryC0_uid123_exp2TabGen_q <= "0100011110110101010000001101";
WHEN "0010110" => memoryC0_uid123_exp2TabGen_q <= "0100100000011000111011100110";
WHEN "0010111" => memoryC0_uid123_exp2TabGen_q <= "0100100001111101001001101000";
WHEN "0011000" => memoryC0_uid123_exp2TabGen_q <= "0100100011100001111010100000";
WHEN "0011001" => memoryC0_uid123_exp2TabGen_q <= "0100100101000111001110011000";
WHEN "0011010" => memoryC0_uid123_exp2TabGen_q <= "0100100110101101000101011110";
WHEN "0011011" => memoryC0_uid123_exp2TabGen_q <= "0100101000010011011111111101";
WHEN "0011100" => memoryC0_uid123_exp2TabGen_q <= "0100101001111010011110000001";
WHEN "0011101" => memoryC0_uid123_exp2TabGen_q <= "0100101011100001111111111000";
WHEN "0011110" => memoryC0_uid123_exp2TabGen_q <= "0100101101001010000101101110";
WHEN "0011111" => memoryC0_uid123_exp2TabGen_q <= "0100101110110010101111101110";
WHEN "0100000" => memoryC0_uid123_exp2TabGen_q <= "0100110000011011111110000111";
WHEN "0100001" => memoryC0_uid123_exp2TabGen_q <= "0100110010000101110001000011";
WHEN "0100010" => memoryC0_uid123_exp2TabGen_q <= "0100110011110000001000110001";
WHEN "0100011" => memoryC0_uid123_exp2TabGen_q <= "0100110101011011000101011100";
WHEN "0100100" => memoryC0_uid123_exp2TabGen_q <= "0100110111000110100111010010";
WHEN "0100101" => memoryC0_uid123_exp2TabGen_q <= "0100111000110010101110011111";
WHEN "0100110" => memoryC0_uid123_exp2TabGen_q <= "0100111010011111011011010001";
WHEN "0100111" => memoryC0_uid123_exp2TabGen_q <= "0100111100001100101101110101";
WHEN "0101000" => memoryC0_uid123_exp2TabGen_q <= "0100111101111010100110010111";
WHEN "0101001" => memoryC0_uid123_exp2TabGen_q <= "0100111111101001000101000101";
WHEN "0101010" => memoryC0_uid123_exp2TabGen_q <= "0101000001011000001010001101";
WHEN "0101011" => memoryC0_uid123_exp2TabGen_q <= "0101000011000111110101111010";
WHEN "0101100" => memoryC0_uid123_exp2TabGen_q <= "0101000100111000001000011100";
WHEN "0101101" => memoryC0_uid123_exp2TabGen_q <= "0101000110101001000001111111";
WHEN "0101110" => memoryC0_uid123_exp2TabGen_q <= "0101001000011010100010110010";
WHEN "0101111" => memoryC0_uid123_exp2TabGen_q <= "0101001010001100101011000000";
WHEN "0110000" => memoryC0_uid123_exp2TabGen_q <= "0101001011111111011010111001";
WHEN "0110001" => memoryC0_uid123_exp2TabGen_q <= "0101001101110010110010101011";
WHEN "0110010" => memoryC0_uid123_exp2TabGen_q <= "0101001111100110110010100010";
WHEN "0110011" => memoryC0_uid123_exp2TabGen_q <= "0101010001011011011010101101";
WHEN "0110100" => memoryC0_uid123_exp2TabGen_q <= "0101010011010000101011011010";
WHEN "0110101" => memoryC0_uid123_exp2TabGen_q <= "0101010101000110100100110111";
WHEN "0110110" => memoryC0_uid123_exp2TabGen_q <= "0101010110111101000111010010";
WHEN "0110111" => memoryC0_uid123_exp2TabGen_q <= "0101011000110100010010111001";
WHEN "0111000" => memoryC0_uid123_exp2TabGen_q <= "0101011010101100000111111011";
WHEN "0111001" => memoryC0_uid123_exp2TabGen_q <= "0101011100100100100110100111";
WHEN "0111010" => memoryC0_uid123_exp2TabGen_q <= "0101011110011101101111001001";
WHEN "0111011" => memoryC0_uid123_exp2TabGen_q <= "0101100000010111100001110010";
WHEN "0111100" => memoryC0_uid123_exp2TabGen_q <= "0101100010010001111110110000";
WHEN "0111101" => memoryC0_uid123_exp2TabGen_q <= "0101100100001101000110010001";
WHEN "0111110" => memoryC0_uid123_exp2TabGen_q <= "0101100110001000111000100101";
WHEN "0111111" => memoryC0_uid123_exp2TabGen_q <= "0101101000000101010101111001";
WHEN "1000000" => memoryC0_uid123_exp2TabGen_q <= "0101101010000010011110011110";
WHEN "1000001" => memoryC0_uid123_exp2TabGen_q <= "0101101100000000010010100001";
WHEN "1000010" => memoryC0_uid123_exp2TabGen_q <= "0101101101111110110010010011";
WHEN "1000011" => memoryC0_uid123_exp2TabGen_q <= "0101101111111101111110000010";
WHEN "1000100" => memoryC0_uid123_exp2TabGen_q <= "0101110001111101110101111110";
WHEN "1000101" => memoryC0_uid123_exp2TabGen_q <= "0101110011111110011010010110";
WHEN "1000110" => memoryC0_uid123_exp2TabGen_q <= "0101110101111111101011011010";
WHEN "1000111" => memoryC0_uid123_exp2TabGen_q <= "0101111000000001101001011000";
WHEN "1001000" => memoryC0_uid123_exp2TabGen_q <= "0101111010000100010100100001";
WHEN "1001001" => memoryC0_uid123_exp2TabGen_q <= "0101111100000111101101000100";
WHEN "1001010" => memoryC0_uid123_exp2TabGen_q <= "0101111110001011110011010010";
WHEN "1001011" => memoryC0_uid123_exp2TabGen_q <= "0110000000010000100111011001";
WHEN "1001100" => memoryC0_uid123_exp2TabGen_q <= "0110000010010110001001101010";
WHEN "1001101" => memoryC0_uid123_exp2TabGen_q <= "0110000100011100011010010110";
WHEN "1001110" => memoryC0_uid123_exp2TabGen_q <= "0110000110100011011001101011";
WHEN "1001111" => memoryC0_uid123_exp2TabGen_q <= "0110001000101011000111111010";
WHEN "1010000" => memoryC0_uid123_exp2TabGen_q <= "0110001010110011100101010101";
WHEN "1010001" => memoryC0_uid123_exp2TabGen_q <= "0110001100111100110010001010";
WHEN "1010010" => memoryC0_uid123_exp2TabGen_q <= "0110001111000110101110101010";
WHEN "1010011" => memoryC0_uid123_exp2TabGen_q <= "0110010001010001011011000111";
WHEN "1010100" => memoryC0_uid123_exp2TabGen_q <= "0110010011011100110111110000";
WHEN "1010101" => memoryC0_uid123_exp2TabGen_q <= "0110010101101001000100110111";
WHEN "1010110" => memoryC0_uid123_exp2TabGen_q <= "0110010111110110000010101100";
WHEN "1010111" => memoryC0_uid123_exp2TabGen_q <= "0110011010000011110001100000";
WHEN "1011000" => memoryC0_uid123_exp2TabGen_q <= "0110011100010010010001100101";
WHEN "1011001" => memoryC0_uid123_exp2TabGen_q <= "0110011110100001100011001011";
WHEN "1011010" => memoryC0_uid123_exp2TabGen_q <= "0110100000110001100110100011";
WHEN "1011011" => memoryC0_uid123_exp2TabGen_q <= "0110100011000010011011111111";
WHEN "1011100" => memoryC0_uid123_exp2TabGen_q <= "0110100101010100000011110001";
WHEN "1011101" => memoryC0_uid123_exp2TabGen_q <= "0110100111100110011110001001";
WHEN "1011110" => memoryC0_uid123_exp2TabGen_q <= "0110101001111001101011011001";
WHEN "1011111" => memoryC0_uid123_exp2TabGen_q <= "0110101100001101101011110100";
WHEN "1100000" => memoryC0_uid123_exp2TabGen_q <= "0110101110100010011111101010";
WHEN "1100001" => memoryC0_uid123_exp2TabGen_q <= "0110110000111000000111001110";
WHEN "1100010" => memoryC0_uid123_exp2TabGen_q <= "0110110011001110100010110010";
WHEN "1100011" => memoryC0_uid123_exp2TabGen_q <= "0110110101100101110010101000";
WHEN "1100100" => memoryC0_uid123_exp2TabGen_q <= "0110110111111101110111000001";
WHEN "1100101" => memoryC0_uid123_exp2TabGen_q <= "0110111010010110110000010000";
WHEN "1100110" => memoryC0_uid123_exp2TabGen_q <= "0110111100110000011110101000";
WHEN "1100111" => memoryC0_uid123_exp2TabGen_q <= "0110111111001011000010011011";
WHEN "1101000" => memoryC0_uid123_exp2TabGen_q <= "0111000001100110011011111011";
WHEN "1101001" => memoryC0_uid123_exp2TabGen_q <= "0111000100000010101011011100";
WHEN "1101010" => memoryC0_uid123_exp2TabGen_q <= "0111000110011111110001010000";
WHEN "1101011" => memoryC0_uid123_exp2TabGen_q <= "0111001000111101101101101001";
WHEN "1101100" => memoryC0_uid123_exp2TabGen_q <= "0111001011011100100000111011";
WHEN "1101101" => memoryC0_uid123_exp2TabGen_q <= "0111001101111100001011011001";
WHEN "1101110" => memoryC0_uid123_exp2TabGen_q <= "0111010000011100101101010111";
WHEN "1101111" => memoryC0_uid123_exp2TabGen_q <= "0111010010111110000111000110";
WHEN "1110000" => memoryC0_uid123_exp2TabGen_q <= "0111010101100000011000111011";
WHEN "1110001" => memoryC0_uid123_exp2TabGen_q <= "0111011000000011100011001010";
WHEN "1110010" => memoryC0_uid123_exp2TabGen_q <= "0111011010100111100110000101";
WHEN "1110011" => memoryC0_uid123_exp2TabGen_q <= "0111011101001100100010000001";
WHEN "1110100" => memoryC0_uid123_exp2TabGen_q <= "0111011111110010010111010001";
WHEN "1110101" => memoryC0_uid123_exp2TabGen_q <= "0111100010011001000110001001";
WHEN "1110110" => memoryC0_uid123_exp2TabGen_q <= "0111100101000000101110111110";
WHEN "1110111" => memoryC0_uid123_exp2TabGen_q <= "0111100111101001010010000011";
WHEN "1111000" => memoryC0_uid123_exp2TabGen_q <= "0111101010010010101111101101";
WHEN "1111001" => memoryC0_uid123_exp2TabGen_q <= "0111101100111101001000001111";
WHEN "1111010" => memoryC0_uid123_exp2TabGen_q <= "0111101111101000011100000000";
WHEN "1111011" => memoryC0_uid123_exp2TabGen_q <= "0111110010010100101011010010";
WHEN "1111100" => memoryC0_uid123_exp2TabGen_q <= "0111110101000001110110011011";
WHEN "1111101" => memoryC0_uid123_exp2TabGen_q <= "0111110111101111111101110000";
WHEN "1111110" => memoryC0_uid123_exp2TabGen_q <= "0111111010011111000001100101";
WHEN "1111111" => memoryC0_uid123_exp2TabGen_q <= "0111111101001111000010001111";
WHEN OTHERS =>
memoryC0_uid123_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid139_exp2PolyEval(ADD,138)@13
sumAHighB_uid139_exp2PolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => memoryC0_uid123_exp2TabGen_q(27)) & memoryC0_uid123_exp2TabGen_q);
sumAHighB_uid139_exp2PolyEval_b <= STD_LOGIC_VECTOR((28 downto 22 => highBBits_uid138_exp2PolyEval_b(21)) & highBBits_uid138_exp2PolyEval_b);
sumAHighB_uid139_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid139_exp2PolyEval_a) + SIGNED(sumAHighB_uid139_exp2PolyEval_b));
sumAHighB_uid139_exp2PolyEval_q <= sumAHighB_uid139_exp2PolyEval_o(28 downto 0);
--lowRangeB_uid137_exp2PolyEval(BITSELECT,136)@13
lowRangeB_uid137_exp2PolyEval_in <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b(1 downto 0);
lowRangeB_uid137_exp2PolyEval_b <= lowRangeB_uid137_exp2PolyEval_in(1 downto 0);
--s2_uid137_uid140_exp2PolyEval(BITJOIN,139)@13
s2_uid137_uid140_exp2PolyEval_q <= sumAHighB_uid139_exp2PolyEval_q & lowRangeB_uid137_exp2PolyEval_b;
--peOR_uid50_fpExp2Test(BITSELECT,49)@13
peOR_uid50_fpExp2Test_in <= s2_uid137_uid140_exp2PolyEval_q(28 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(28 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@13
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(22 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(22 downto 0);
--ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b(DELAY,235)@7
ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 6 )
PORT MAP ( xin => excREnc_uid70_fpExp2Test_q, xout => ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid74_fpExp2Test(MUX,73)@13
fracRPostExc_uid74_fpExp2Test_s <= ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, fracR_uid52_fpExp2Test_b, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= fracR_uid52_fpExp2Test_b;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@13
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@13
q <= RExp2_uid79_fpExp2Test_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_sgn_mul3s.vhd | 10 | 5383 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SGN_MUL3S.VHD ***
--*** ***
--*** Function: Signed Multiplier - 3 Pipe ***
--*** Stages ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_sgn_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_sgn_mul3s;
ARCHITECTURE SYN OF fp_sgn_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fpc_library_sv.vhd | 10 | 100780 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/dp_lnlutpow.vhd | 10 | 230947 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_lnlutpow;
ARCHITECTURE rtl OF dp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
WHEN "0000000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "0000000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1023,11);
WHEN "0000000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6526370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7976716,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6617222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(58241350,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6708074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108505984,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6798926,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158770618,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6889778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209035252,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6980630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259299886,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7071483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41129064,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7162335,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91393698,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7253187,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141658332,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7344039,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191922966,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7434891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(242187600,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7525744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(24016777,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7616596,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74281411,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7707448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124546045,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7798300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174810679,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7889152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225075313,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7980005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6904491,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8070857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57169125,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8161709,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107433759,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8252561,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157698393,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8343413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207963027,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8434265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(258227661,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8525118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(40056839,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8615970,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(90321473,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8706822,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140586107,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8797674,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190850741,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8888526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241115374,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8979379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22944552,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9070231,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(73209186,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9161083,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123473820,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9251935,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173738454,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9342787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224003088,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9433640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5832266,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9524492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56096900,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9615344,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106361534,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9706196,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156626168,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9797048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206890802,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9887900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257155436,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9978753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38984614,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10069605,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(89249248,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10160457,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139513882,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10251309,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(189778515,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10342161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240043149,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10433014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21872327,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10523866,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72136961,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10614718,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122401595,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10705570,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172666229,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10796422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222930863,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10887275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4760041,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10978127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55024675,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11068979,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105289309,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11159831,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155553943,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11250683,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205818577,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11341535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256083211,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11432388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37912389,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11523240,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88177023,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11614092,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138441657,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11704944,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188706290,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11795796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238970924,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11886649,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20800102,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11977501,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71064736,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12068353,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(121329370,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12159205,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171594004,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12250057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221858638,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12340910,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3687816,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12431762,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53952450,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12522614,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104217084,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12613466,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(154481718,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12704318,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204746352,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12795170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255010986,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12886023,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36840164,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12976875,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87104798,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13067727,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137369431,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13158579,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187634065,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13249431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237898699,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13340284,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19727877,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13431136,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69992511,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13521988,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120257145,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13612840,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170521779,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13703692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220786413,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13794545,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2615591,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13885397,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52880225,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13976249,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103144859,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14067101,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153409493,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14157953,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203674127,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14248805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253938761,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14339658,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35767939,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14430510,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86032572,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14521362,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136297206,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14612214,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186561840,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14703066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236826474,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14793919,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18655652,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14884771,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68920286,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14975623,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119184920,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15066475,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(169449554,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15157327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219714188,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15248180,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1543366,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15339032,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51808000,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15429884,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102072634,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15520736,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152337268,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15611588,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202601902,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15702440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252866536,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15793293,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34695713,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15884145,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84960347,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15974997,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135224981,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16065849,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(185489615,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16156701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235754249,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16247554,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17583427,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16338406,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67848061,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16429258,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118112695,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16520110,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168377329,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16610962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218641963,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16701815,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(471141,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159585615,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(53151,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184717932,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(98577,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209850249,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(144003,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234982566,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(189429,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260114883,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(234856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(16811744,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(280282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41944061,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(325708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67076378,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(371134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92208695,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(416560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117341012,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(461986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142473329,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(507412,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167605646,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(552838,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192737963,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(598264,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217870280,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(643690,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243002597,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(689116,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268134914,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(734543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(24831775,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(779969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49964092,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(825395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75096409,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(870821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100228726,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(916247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125361043,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(961673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150493360,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1007099,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175625677,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1052525,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(200757994,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1097951,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225890311,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1143377,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251022628,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1188804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7719489,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1234230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32851805,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1279656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57984122,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1325082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83116439,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1370508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108248756,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1415934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133381073,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1461360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158513390,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1506786,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183645707,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1552212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208778024,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1597638,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233910341,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1643064,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259042658,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1688491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15739519,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1733917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(40871836,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1779343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66004153,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1824769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91136470,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1870195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116268787,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1915621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141401104,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1961047,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166533421,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2006473,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191665738,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2051899,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(216798055,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2097325,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241930372,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2142751,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267062689,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2188178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(23759550,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2233604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48891867,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2279030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74024184,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2324456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99156501,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2369882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124288818,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2415308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149421135,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2460734,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174553452,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2506160,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199685769,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2551586,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224818086,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2597012,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249950403,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2642439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6647263,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2687865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(31779580,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2733291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56911897,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2778717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82044214,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2824143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107176531,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2869569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132308848,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2914995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157441165,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2960421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182573482,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3005847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207705799,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3051273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232838116,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3096699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257970433,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3142126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14667294,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3187552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(39799611,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3232978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64931928,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3278404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(90064245,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3323830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115196562,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3369256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140328879,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3414682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165461196,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3460108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190593513,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3505534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215725830,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3550960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240858147,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3596386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265990464,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3641813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22687325,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3687239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47819642,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3732665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72951959,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3778091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98084276,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3823517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123216593,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3868943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148348910,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3914369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173481227,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3959795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198613544,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4005221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(223745860,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4050647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248878177,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4096074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5575038,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4141500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30707355,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4186926,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55839672,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4232352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80971989,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4277778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106104306,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4323204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131236623,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4368630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156368940,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4414056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181501257,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4459482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206633574,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4504908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231765891,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4550334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256898208,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4595761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13595069,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4641187,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38727386,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4686613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63859703,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4732039,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88992020,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4777465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114124337,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4822891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139256654,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4868317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164388971,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4913743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(189521288,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4959169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214653605,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5004595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239785922,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5050021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264918239,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5095448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21615100,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5140874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46747417,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5186300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71879734,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5231726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97012051,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5277152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122144368,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5322578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147276685,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5368004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172409002,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5413430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197541318,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5458856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222673635,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5504282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247805952,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5549709,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4502813,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5595135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29635130,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5640561,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54767447,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5685987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79899764,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5731413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105032081,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5776839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130164398,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5822265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155296715,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5867691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180429032,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5913117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205561349,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5958543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230693666,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6003969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255825983,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6049396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12522844,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6094822,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37655161,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6140248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62787478,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6185674,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87919795,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6231100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113052112,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6276526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138184429,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6321952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163316746,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6367378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188449063,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6412804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213581380,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6458230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238713697,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN others =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_div_est.vhd | 10 | 6558 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_EST.VHD ***
--*** ***
--*** Function: Estimates 18 Bit Inverse ***
--*** ***
--*** Used by both single and double dividers ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Inverse of 18 bit header ***
--*** (not including leading '1') ***
--*** 2. Uses 20 bit precision tables - 18 bits ***
--*** drops a bit occasionally ***
--***************************************************
ENTITY fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
END fp_div_est;
ARCHITECTURE rtl OF fp_div_est IS
type twodelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type ziplutdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (20 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (17 DOWNTO 1);
signal one, two : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal oneaddff, zipaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal onelut, onelutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ziplut, ziplutff : STD_LOGIC_VECTOR (20 DOWNTO 1);
signal onetwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal twodelff : twodelfftype;
signal ziplutdelff : ziplutdelfftype;
signal invdivisorff : STD_LOGIC_VECTOR (20 DOWNTO 1);
component fp_div_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 17 GENERATE
zerovec(k) <= '0';
END GENERATE;
one <= divisor(18 DOWNTO 10);
two <= divisor(9 DOWNTO 1);
-- these register seperate to make the LUTs into memories
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 9 LOOP
oneaddff(k) <= '0';
zipaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
onelutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 20 LOOP
ziplutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oneaddff <= one;
zipaddff <= one;
onelutff <= onelut;
ziplutff <= ziplut;
END IF;
END IF;
END PROCESS;
upper: fp_div_lut1 PORT MAP (add=>oneaddff,data=>onelut);
lower: fp_div_lut0 PORT MAP (add=>zipaddff,data=>ziplut);
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
twodelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
ziplutdelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 20 LOOP
invdivisorff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
twodelff(1)(9 DOWNTO 1) <= two;
twodelff(2)(9 DOWNTO 1) <= twodelff(1)(9 DOWNTO 1);
ziplutdelff(1)(20 DOWNTO 1) <= ziplutff;
ziplutdelff(2)(20 DOWNTO 1) <= ziplutdelff(1)(20 DOWNTO 1);
invdivisorff <= ziplutdelff(2)(20 DOWNTO 1) -
(zerovec(9 DOWNTO 1) & onetwo);
END IF;
END IF;
END PROCESS;
mulcore: fp_fxmul
GENERIC MAP (widthaa=>11,widthbb=>9,widthcc=>11,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>onelutff,databb=>twodelff(2)(9 DOWNTO 1),
result=>onetwo);
invdivisor <= invdivisorff(20 DOWNTO 3);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_lsftpipe36.vhd | 10 | 4409 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE36.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftpipe36;
ARCHITECTURE rtl OF hcc_lsftpipe36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
signal levtwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 36 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/dotProduct64_safe_path_sv.vhd | 10 | 410 | -- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_normfp1x.vhd | 10 | 10480 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP1X.VHD ***
--*** ***
--*** Function: Normalize single precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/12/07 - divider target uses all of ***
--*** mantissa width ***
--*** 06/02/08 - fix divider norm ***
--*** 21/03/08 - fix add tree output norm ***
--*** ***
--***************************************************
-- normalize signed numbers (x input format) - for 1x multipliers
-- format signed32/36 bit mantissa, 10 bit exponent
-- unsigned numbers for divider (S,1,23 bit mantissa for divider)
-- divider packed into 32/36bit mantissa + exponent
ENTITY hcc_normfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp1x;
ARCHITECTURE rtl OF hcc_normfp1x IS
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
-- scale
signal aasatff, aazipff : STD_LOGIC;
signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1);
-- normalize
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exptopff, expbotff : expfftype;
signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_normsgn3236
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
component hcc_scmul3236
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
end component;
BEGIN
--********************************************************
--*** scale multiplier ***
--*** multiplier format [S][1][mantissa....] ***
--*** one clock latency ***
--********************************************************
-- make sure right format & adjust exponent
gsa: IF (inputnormalize = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
-- no rounding when scaling
sma: hcc_scmul3236
GENERIC MAP (mantissa=>mantissa)
PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11),
scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa);
ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa);
cc <= ccnode;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--********************************************************
--*** full normalization of input - 4 stages ***
--*** unlike double, no round required on output, as ***
--*** no information lost ***
--********************************************************
gna: IF (inputnormalize = 1) GENERATE -- normalize
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- if multiplier, "1" which is nominally in position 27, is shifted to position 31
-- add 4 to exponent when multiplier, 0 for adder
gxa: IF (target < 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
gxb: IF (target = 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
normfracff(k) <= '0';
normff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exptopff(1)(k) <= '0';
exptopff(2)(k) <= '0';
expbotff(1)(k) <= '0';
expbotff(2)(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
aasatdelff(k) <= '0';
aazipdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
normfracff <= normfracnode;
--might not get used
normff <= normnode;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust;
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign);
--might not get used
expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
aasatdelff(1) <= aasat;
aazipdelff(1) <= aazip;
FOR k IN 2 TO 5 LOOP -- 4&5 might not get used
aasatdelff(k) <= aasatdelff(k-1);
aazipdelff(k) <= aazipdelff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
nrmc: hcc_normsgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaff(mantissa+10 DOWNTO 11),
countout=>countsign, -- stage 1 or 2
fracout=>normfracnode); -- stage 2 or 3
gnb: IF (target = 1) GENERATE
gnc: FOR k IN 1 TO mantissa GENERATE
normsignnode(k) <= normfracff(k) XOR normfracff(mantissa);
END GENERATE;
normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) +
(zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa));
-- 06/02/08 make sure signbit is packed with the mantissa
normnode(mantissa) <= normfracff(mantissa);
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normff;
ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1);
ccsat <= aasatdelff(3+normspeed);
cczip <= aazipdelff(3+normspeed);
END GENERATE;
gnc: IF (target = 0) GENERATE
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normfracff;
gma: IF (normspeed = 1) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gmb: IF (normspeed > 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed);
cczip <= aazipdelff(2+normspeed);
END GENERATE;
gnd: IF (target = 2) GENERATE
gaa: IF (roundnormalize = 1) GENERATE
normnode <= (normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5)) +
(zerovec(mantissa-1 DOWNTO 1) & normfracff(4));
END GENERATE;
--*** OUTPUTS ***
gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX
ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5);
END GENERATE;
gac: IF (roundnormalize = 1) GENERATE
ccnode(mantissa+10 DOWNTO 11) <= normff;
END GENERATE;
gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gae: IF ((normspeed = 2 AND roundnormalize = 0) OR
(normspeed = 1 AND roundnormalize = 1)) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed+roundnormalize);
cczip <= aazipdelff(2+normspeed+roundnormalize);
END GENERATE;
cc <= ccnode;
END GENERATE;
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccexp <= ccnode(10 DOWNTO 1);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
| mit |
richjyoung/lfsr-package | src/LFSR/lfsr_components.vhd | 1 | 490 | library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
package lfsr_components is
component pulse is
generic (
G_lfsr_width : natural := 3;
G_period : natural := 7
);
port(
CLK : in std_logic;
RESET : in std_logic;
PULSE : out std_logic
);
end component;
end lfsr_components; | mit |
pedabraham/MDSM | crs/bitsToNumbers.vhd | 1 | 948 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bitsToNumbers is
port(
cadenaOriginalDeBits: IN STD_LOGIC_VECTOR(8 downto 0);
numero : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end bitsToNumbers;
architecture Behavioral of bitsToNumbers is
begin
process(cadenaOriginalDeBits)
begin
case cadenaOriginalDeBits is
when "100000000" => numero <= "0001";
when "010000000" => numero <= "0010";
when "001000000" => numero <= "0011";
when "000100000" => numero <= "0100";
when "000010000" => numero <= "0101";
when "000001000" => numero <= "0110";
when "000000100" => numero <= "0111";
when "000000010" => numero <= "1000";
when "000000001" => numero <= "1001";
when others => numero <= "0000";
end case;
end process;
end architecture;
| mit |
peteg944/music-fpga | Experimental/Zedboard UART/i2c.vhd | 3 | 2393 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c is
Port ( clk : in STD_LOGIC;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : out STD_LOGIC);
end i2c;
architecture Behavioral of i2c is
COMPONENT i3c2
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
inst_data : IN std_logic_vector(8 downto 0);
inputs : IN std_logic_vector(15 downto 0);
inst_address : OUT std_logic_vector(9 downto 0);
debug_sda : OUT std_logic;
debug_scl : OUT std_logic;
outputs : OUT std_logic_vector(15 downto 0);
reg_addr : OUT std_logic_vector(4 downto 0);
reg_data : OUT std_logic_vector(7 downto 0);
reg_write : OUT std_logic;
error : OUT std_logic
);
END COMPONENT;
COMPONENT adau1761_configuraiton_data
PORT(
clk : IN std_logic;
address : IN std_logic_vector(9 downto 0);
data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
signal inst_address : std_logic_vector(9 downto 0);
signal inst_data : std_logic_vector(8 downto 0);
signal debug_big : std_logic_vector(15 downto 0);
begin
Inst_adau1761_configuraiton_data: adau1761_configuraiton_data PORT MAP(
clk => clk,
address => inst_address,
data => inst_data
);
Inst_i3c2: i3c2 GENERIC MAP (
clk_divide => "01111000" -- 120 (48,000/120 = 400kHz I2C clock)
) PORT MAP(
clk => clk,
inst_address => inst_address,
inst_data => inst_data,
i2c_scl => i2c_scl,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
inputs => (others => '0'),
outputs => debug_big,
reg_addr => open,
reg_data => open,
reg_write => open,
debug_scl => open,
debug_sda => open,
error => open
);
end Behavioral; | mit |
thoralt/KCVGA | FPGA/ColorGenerator.vhd | 1 | 2392 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ColorGenerator IS PORT
(
SIGNAL pixel : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL r, g, b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ColorGenerator;
ARCHITECTURE Behavioral OF ColorGenerator IS
TYPE RGB_type IS RECORD R, G, B : STD_LOGIC_VECTOR(3 DOWNTO 0);
END RECORD;
TYPE COLORS_type IS ARRAY (0 TO 31) OF RGB_type;
CONSTANT COLORS : COLORS_type := (
-- "00xxx" => background, no highlight
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0111"), -- 1 blau
("0111", "0000", "0000"), -- 2 rot
("0111", "0000", "0111"), -- 3 purpur
("0000", "0111", "0000"), -- 4 grün
("0000", "0111", "0111"), -- 5 türkis
("0111", "0111", "0000"), -- 6 gelb
("0111", "0111", "0111"), -- 7 weiß
-- "01xxx" => undefined
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
-- "10xxx" => foreground, highlight
("0000", "0000", "0000"), -- 8 schwarz #000000
("0110", "0000", "1111"), -- 9 violett #5901FF
("1111", "0110", "0000"), -- A orange #FF5901
("1111", "0000", "1011"), -- B purpurrot #FF01B3
("0000", "1111", "0110"), -- C grünblau #01FF5A
("0000", "1000", "1111"), -- D blaugrün #0186FF
("1000", "1111", "0000"), -- E gelbgrün #86FF01
("1111", "1111", "1111"), -- F weiß #FFFFFF
-- "11xxx" => foreground, no highlight
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "1111"), -- 1 blau
("1111", "0000", "0000"), -- 2 rot
("1111", "0000", "1111"), -- 3 purpur
("0000", "1111", "0000"), -- 4 grün
("0000", "1111", "1111"), -- 5 türkis
("1111", "1111", "0000"), -- 6 gelb
("1111", "1111", "1111") -- 7 weiß
);
BEGIN
R <= COLORS(to_integer(unsigned(PIXEL))).R;
G <= COLORS(to_integer(unsigned(PIXEL))).G;
B <= COLORS(to_integer(unsigned(PIXEL))).B;
END Behavioral;
| mit |
migueljiarr/RV32I | src/left_XLEN_barrel_shifter.vhd | 1 | 1157 | library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity left_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end left_XLEN_barrel_shifter;
architecture structural of left_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= i (30 downto 0) & '0';
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= s1 (29 downto 0) & "00";
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= s2 (27 downto 0) & "0000";
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= s3 (23 downto 0) & "00000000";
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= s4 (15 downto 0) & "0000000000000000";
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
| mit |
ou-cse-378/vhdl-tetris | whypcore.vhd | 1 | 7449 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: Whypcore.vhd
-- // Date: 12/9/2004
-- // Description: WHYP Core
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity whypcore is
port (
p : out STD_LOGIC_VECTOR(15 downto 0);
destro : in STD_LOGIC_VECTOR(2 downto 0);
m : in STD_LOGIC_VECTOR(15 downto 0);
SW : in std_logic_vector(7 downto 0);
BTN4 : in std_logic;
b : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
digload : out STD_LOGIC;
ldload: out STD_LOGIC;
t : out STD_LOGIC_VECTOR(15 downto 0);
o_Clear_Lines : out std_logic
);
end whypcore;
architecture Behavioral of whypcore is
component mux2g
generic(width:positive);
Port (
a : in std_logic_vector(width-1 downto 0);
b : in std_logic_vector(width-1 downto 0);
sel : in std_logic;
y : out std_logic_vector(width-1 downto 0)
);
end component;
component PC
port (
d : in STD_LOGIC_VECTOR (15 downto 0);
clr : in STD_LOGIC;
clk : in STD_LOGIC;
inc : in STD_LOGIC;
pload : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component plus1a
Port ( input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end component;
component reg
generic(width: positive);
port (
d : in STD_LOGIC_VECTOR (width-1 downto 0);
load : in STD_LOGIC;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
component WC16C_control
port (
oClearLines : out std_logic;
icode : in STD_LOGIC_VECTOR (15 downto 0);
M : in STD_LOGIC_VECTOR (15 downto 0);
BTN4 : in std_logic;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
fcode : out STD_LOGIC_VECTOR (5 downto 0);
pinc : out STD_LOGIC;
pload : out STD_LOGIC;
tload : out STD_LOGIC;
nload : out STD_LOGIC;
digload : out STD_LOGIC;
iload : out STD_LOGIC;
dpush : out STD_LOGIC;
dpop : out STD_LOGIC;
tsel : out STD_LOGIC_VECTOR (2 downto 0);
nsel : out STD_LOGIC_VECTOR (1 downto 0);
ssel : out STD_LOGIC;
R : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC_VECTOR (15 downto 0);
rsel : out STD_LOGIC;
rload : out STD_LOGIC;
rdec : out STD_LOGIC;
rpush : out STD_LOGIC;
rpop : out STD_LOGIC;
ldload : out STD_LOGIC;
psel : out STD_LOGIC;
rinsel : out STD_LOGIC
);
end component;
component ReturnStack
Port ( Rin : in std_logic_vector(15 downto 0);
rsel : in std_logic;
rload : in std_logic;
rdec : in std_logic;
clr : in std_logic;
clk : in std_logic;
rpush : in std_logic;
rpop : in std_logic;
R : out std_logic_vector(15 downto 0));
end component;
component mux8g
generic(width:positive);
Port (
a : in std_logic_vector(width-1 downto 0);
b : in std_logic_vector(width-1 downto 0);
c : in std_logic_vector(width-1 downto 0);
d : in std_logic_vector(width-1 downto 0);
e : in std_logic_vector(width-1 downto 0);
f : in std_logic_vector(width-1 downto 0);
g : in std_logic_vector(width-1 downto 0);
h : in std_logic_vector(width-1 downto 0);
sel : in std_logic_vector(2 downto 0);
y : out std_logic_vector(width-1 downto 0)
);
end component;
component datastack
port (
TLoad : in std_logic;
y1 : in STD_LOGIC_VECTOR(15 downto 0);
nsel : in STD_LOGIC_VECTOR(1 downto 0);
nload : in STD_LOGIC;
ssel : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
dpush : in STD_LOGIC;
dpop : in STD_LOGIC;
Tin : in STD_LOGIC_VECTOR(15 downto 0);
T : out STD_LOGIC_VECTOR(15 downto 0);
N : out STD_LOGIC_VECTOR(15 downto 0);
N2 : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
component funit1
generic(width:positive);
port (
a : in STD_LOGIC_VECTOR(width-1 downto 0);
b : in STD_LOGIC_VECTOR(width-1 downto 0);
sel : in STD_LOGIC_VECTOR(5 downto 0);
y : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end component;
constant bus_width: positive := 16;
signal Y: std_logic_vector(15 downto 0);
signal tC : std_logic_vector(15 downto 0);
signal tE : std_logic_vector(15 downto 0);
signal Y1: std_logic_vector(15 downto 0);
signal T1: std_logic_vector(15 downto 0);
signal TIN: std_logic_vector(15 downto 0);
signal N: std_logic_vector(15 downto 0);
signal N2: std_logic_vector(15 downto 0);
signal ICODE: std_logic_vector(15 downto 0);
signal FCODE: std_logic_vector(5 downto 0);
signal ILOAD: std_logic;
signal R: std_logic_vector(15 downto 0);
signal E1: std_logic_vector(15 downto 0);
signal E2: std_logic_vector(15 downto 0);
signal PLOAD: std_logic;
signal TLOAD: std_logic;
signal NLOAD: std_logic;
signal PINC: std_logic;
signal NSEL: std_logic_vector(1 downto 0);
signal DPUSH: std_logic;
signal DPOP: std_logic;
signal TSEL: std_logic_vector(2 downto 0);
signal SSEL: std_logic;
signal Pin: std_logic_vector(15 downto 0);
signal PS: std_logic_vector(15 downto 0);
signal P1: std_logic_vector(15 downto 0);
signal Rin: std_logic_vector(15 downto 0);
signal rsel: std_logic;
signal rload: std_logic;
signal rdec: std_logic;
signal rpush: std_logic;
signal rpop: std_logic;
signal rinsel: std_logic;
signal psel: STD_LOGIC;
begin
T <= T1;
P <= PS;
tE <= "0000000000000" & destro(2) & destro(1) & destro(0);
tC <= "00000000" & SW;
SWpmux : mux2g generic map (width => bus_width) port map
( a => M, b => R, sel => psel, y => Pin );
SWpc : pc port map
( d => Pin, clr => CLR, clk => CLK, inc => PINC, pload => PLOAD, q => PS );
SWplus1a : plus1a port map
( input => PS, output => P1 );
SWir : reg generic map (width => bus_width) port map
( d => M, load => ILOAD, clr => CLR, clk => CLK, q => ICODE );
SWwc16ccontrol : WC16C_control port map
( R => R, icode => ICODE, oClearLines => o_Clear_Lines, BTN4 => BTN4, M => M, clr => CLR, clk => CLK, fcode => FCODE, pinc => PINC, pload => PLOAD, tload => TLOAD, nload => NLOAD, digload => DIGLOAD, iload => ILOAD, dpush => DPUSH, dpop => DPOP, tsel => TSEL, nsel => NSEL, ssel => SSEL, T => T1, ldload => ldload, rload => rload, rdec => rdec, rinsel => rinsel, rsel => rsel, rpush => rpush, rpop => rpop, psel => psel );
SWrmux : mux2g generic map (width => bus_width) port map
( a => P1, b => T1, sel => rinsel, y => Rin );
SWreturnstack : ReturnStack port map
( Rin => Rin, rsel => rsel, rload => rload, rdec => rdec, clr => clr, clk => clk, rpush => rpush, rpop => rpop, r => R );
SWtmux : mux8g generic map (width => bus_width) port map
( a => Y, b => M, c => tC , d => R, e => tE, f => "0000000000000000", g => N2, h => N, sel => TSEL, y => TIN );
SWdatastack : datastack port map
( Tload => TLOAD, y1 => Y1, nsel => NSEL, nload => NLOAD, ssel => SSEL, clk => CLK, clr => CLR, dpush => DPUSH, dpop => DPOP, tin => TIN, N => N, N2 => N2, T => T1 );
SWfunit1 : funit1 generic map (width => bus_width) port map
( a => T1, b => N, sel => FCODE, y => Y );
end behavioral; | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_mul5418s.vhd | 10 | 4973 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL5418S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** 54x18=54, 3 18x18 architecture, ***
--*** Stratix II/III, 3 or 4 pipeline, ***
--*** synthesizable ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 15/01/08 - outputs up to 72 bits now ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul5418s IS
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul5418s;
ARCHITECTURE rtl OF fp_mul5418s IS
signal zerovec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout, multwoout, multhrout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal aavec, bbvec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal lowff, lowdelff : STD_LOGIC_VECTOR (18 DOWNTO 1);
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_mul2s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 18 GENERATE
zerovec(k) <= '0';
END GENERATE;
mulone: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(18 DOWNTO 1),databb=>databb(18 DOWNTO 1),
result=>muloneout);
multwo: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(36 DOWNTO 19),databb=>databb(18 DOWNTO 1),
result=>multwoout);
multhr: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(54 DOWNTO 37),databb=>databb(18 DOWNTO 1),
result=>multhrout);
aavec <= multhrout & muloneout(36 DOWNTO 19);
bbvec <= zerovec(18 DOWNTO 1) & multwoout;
adder: dp_fxadd
GENERIC MAP (width=>54,pipes=>pipes-2,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aavec,bb=>bbvec,carryin=>'0',
cc=>resultnode(72 DOWNTO 19));
gda: IF (pipes = 3) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowff;
END GENERATE;
gdb: IF (pipes = 4) GENERATE
pdb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
lowdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
lowdelff <= lowff;
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowdelff;
END GENERATE;
result <= resultnode(72 DOWNTO 73-widthcc);
END rtl;
| mit |
Reiuiji/ECE368-Lab | Lab 3/Keyboard/keycode_to_ascii.vhd | 1 | 6905 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Keycode to ascii
---------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity KEYCODE_TO_ASCII is
port(
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
KEYCODE : in STD_LOGIC_VECTOR(7 downto 0);
VALID_SIGNAL : in STD_LOGIC;
-- Output
COMPLETE: out STD_LOGIC; -- Hit Key sucessfully
ASCII : out STD_LOGIC_VECTOR(7 downto 0)--;
--KEYBOARD_OUT : out STD_LOGIC_VECTOR(7 downto 0);
--WRITE_KEYBOARD: out STD_LOGIC;
);
end KEYCODE_TO_ASCII;
architecture dataflow of KEYCODE_TO_ASCII is
type StateType is (init, idle, READ_BREAKCODE, READ_EXTENDED, READ_KEYCODE,SEND_COMPLETE);--,SEND_CAPS);
signal STATE : StateType := init;
signal ASCII_LOWER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ASCII_UPPER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
shared variable Shift_Key : boolean := false;
shared variable Caps_Lock : boolean := false;
shared variable Extended : boolean := false;
begin
with KEYCODE select
ASCII_LOWER <=
-- Alphabet
x"61" when x"1C", -- a
x"62" when x"32", -- b
x"63" when x"21", -- c
x"64" when x"23", -- d
x"65" when x"24", -- e
x"6C" when x"2B", -- f
x"67" when x"34", -- g
x"68" when x"33", -- h
x"69" when x"43", -- i
x"6A" when x"3B", -- j
x"6B" when x"42", -- k
x"66" when x"4B", -- l
x"6D" when x"3A", -- m
x"6E" when x"31", -- n
x"6F" when x"44", -- o
x"70" when x"4D", -- p
x"71" when x"15", -- q
x"74" when x"2D", -- r
x"73" when x"1B", -- s
x"72" when x"2C", -- t
x"79" when x"3C", -- u
x"76" when x"2A", -- v
x"77" when x"1D", -- w
x"78" when x"22", -- x
x"75" when x"35", -- y
x"7A" when x"1A", -- z
--Top Row
x"60" when x"0E", -- `
x"31" when x"16", -- 1
x"32" when x"1E", -- 2
x"33" when x"26", -- 3
x"34" when x"25", -- 4
x"35" when x"2E", -- 5
x"36" when x"36", -- 6
x"37" when x"3D", -- 7
x"38" when x"3E", -- 8
x"39" when x"46", -- 9
x"30" when x"45", -- 0
x"2D" when x"4E", -- -
x"3D" when x"55", -- =
--Enter Corner
x"5B" when x"54", -- [
x"5D" when x"5B", -- ]
x"5C" when x"5D", -- \
x"3B" when x"4C", -- ;
x"27" when x"52", -- '
x"2C" when x"41", -- ,
x"2E" when x"49", -- .
x"2F" when x"4A", -- /
--Function Keys -- Based on the IBM PC Codes
x"1B" when x"76", -- Esc (Escape)
x"3B" when x"05", -- F1
x"3C" when x"06", -- F2
x"3D" when x"04", -- F3
x"3E" when x"0C", -- F4
x"3F" when x"03", -- F5
x"40" when x"0B", -- F6
x"41" when x"83", -- F7
x"42" when x"0A", -- F8
x"43" when x"01", -- F9
x"44" when x"09", -- F10
x"85" when x"78", -- F11
x"86" when x"07", -- F12
x"09" when x"0D", -- Tab (Horizontal Tab)
x"0D" when x"5A", -- Enter (Carriage Return)
--special characters -- taking up unneaded ascii codes for simplicity
x"05" when x"58", -- Caps Lock
x"06" when x"14", -- Ctrl
x"07" when x"11", -- Alt
x"08" when x"66", -- Back Space
x"20" when x"29", -- Space
--Direction Keys -- taking up unneaded ascii codes for simplicity
x"01" when x"75", -- Up
x"02" when x"72", -- Down
x"03" when x"6B", -- Left
x"04" when x"74", -- Right
--Unknown input
x"00" when OTHERS; -- Null
with KEYCODE select
ASCII_UPPER <=
-- Alphabet
x"41" when x"1C", -- A
x"42" when x"32", -- B
x"43" when x"21", -- C
x"44" when x"23", -- D
x"48" when x"24", -- E
x"46" when x"2B", -- F
x"47" when x"34", -- G
x"45" when x"33", -- H
x"49" when x"43", -- I
x"4A" when x"3B", -- J
x"4B" when x"42", -- K
x"4C" when x"4B", -- L
x"4D" when x"3A", -- M
x"4E" when x"31", -- N
x"4F" when x"44", -- O
x"50" when x"4D", -- P
x"51" when x"15", -- Q
x"52" when x"2D", -- R
x"54" when x"1B", -- S
x"53" when x"2C", -- T
x"55" when x"3C", -- U
x"56" when x"2A", -- V
x"57" when x"1D", -- W
x"58" when x"22", -- X
x"59" when x"35", -- Y
x"5A" when x"1A", -- Z
-- Special Upper case Characters (top left to bottom right)
-- Top Row
x"7E" when x"0E", -- ~
x"21" when x"16", -- !
x"40" when x"1E", -- @
x"23" when x"26", -- #
x"24" when x"25", -- $
x"25" when x"2E", -- %
x"5E" when x"36", -- ^
x"26" when x"3D", -- &
x"2A" when x"3E", -- *
x"28" when x"46", -- (
x"29" when x"45", -- )
x"5F" when x"4E", -- _
x"2B" when x"55", -- +
-- Enter Corner
x"7B" when x"54", -- {
x"7D" when x"5B", -- }
x"7C" when x"5D", -- |
x"3A" when x"4C", -- :
x"22" when x"52", -- "
x"3C" when x"41", -- <
x"3E" when x"49", -- >
x"3F" when x"4A", -- ?
-- Unknown Key
x"00" when OTHERS; -- Null
PROCESS (KEYCODE,CLK, RST)
BEGIN
if (RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '0' ) then
case STATE is
when init =>
ascii <= (OTHERS => '0');
COMPLETE <= '0';
state <= idle;
when idle =>
COMPLETE <= '0';
if VALID_SIGNAL= '1' then
Extended := false;
if keycode=x"E0" then
state <= READ_EXTENDED;
-- A Key was pressed
elsif keycode=x"F0" then
state <= READ_KEYCODE;
else
-- No break code yet
state <= idle;
end if;
-- Shift Key was press (on)
if (keycode=x"12" or keycode=x"54") then
Shift_Key := true;
end if;
end if;
when READ_EXTENDED =>
if VALID_SIGNAL= '1' then
Extended := true;
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_BREAKCODE =>
if VALID_SIGNAL= '1' then
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_KEYCODE =>
if VALID_SIGNAL= '1' then
-- Shift Key was released (off)
if (keycode=x"12" or keycode=x"54") then
Shift_Key := false;
elsif (keycode=x"46") then
if (Caps_Lock = false) then
Caps_Lock := true;
else
Caps_Lock := false;
end if;
--state <= SEND_CAPS;
else
if (Shift_Key = true or Caps_Lock = true) then
ascii <= ASCII_UPPER;
else
ascii <= ASCII_LOWER;
end if;
end if;
state <= SEND_COMPLETE;
end if;
when SEND_COMPLETE =>
COMPLETE <= '1';
state <= idle;
--when SEND_CAPS =>
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_mulufp54.vhd | 10 | 5016 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULUFP54.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** core (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulufp54 IS
GENERIC (synthesize : integer := 1); -- 0 = behavioral, 1 = instantiated
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulufp54;
ARCHITECTURE rtl OF hcc_mulufp54 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (5 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (5 DOWNTO 1);
component hcc_mul54usb
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54uss
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
-- 54 bit mantissa, signed normalized input
-- [S ][1 ][M...M]
-- [54][53][52..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..70][69][68..17][16..1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..71][70][69..18][17..1]
-- assume that result > 2
-- output [71..8] for 64 bit mantissa out
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000000";
bbexpff <= "0000000000000";
FOR k IN 1 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= "0000000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00000";
cczipff <= "00000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
FOR k IN 2 TO 5 LOOP
ccsatff(k) <= ccsatff(k-1);
END LOOP;
cczipff(1) <= aazipff OR bbzipff;
FOR k IN 2 TO 5 LOOP
cczipff(k) <= cczipff(k-1);
END LOOP;
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(13 DOWNTO 1) <= aaexpff + bbexpff - "0001111111111";
FOR k IN 1 TO 13 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
FOR k IN 3 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= expff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul54usb
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul54uss
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
ccman <= mulout;
ccexp <= expff(5)(13 DOWNTO 1);
ccsat <= ccsatff(5);
cczip <= cczipff(5);
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_clz23.vhd | 10 | 4166 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ23.VHD ***
--*** ***
--*** Function: 23 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz23 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_clz23;
ARCHITECTURE zzz of fp_clz23 IS
type positiontype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos51
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18);
zerogroup(2) <= mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12);
zerogroup(3) <= mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6);
zerogroup(4) <= mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
pone: fp_pos51
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(23 DOWNTO 18),position=>position(1)(5 DOWNTO 1));
ptwo: fp_pos51
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(17 DOWNTO 12),position=>position(2)(5 DOWNTO 1));
pthr: fp_pos51
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(11 DOWNTO 6),position=>position(3)(5 DOWNTO 1));
pfiv: fp_pos51
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mannode,position=>position(4)(5 DOWNTO 1));
mannode <= mantissa(5 DOWNTO 1) & '0';
gma: FOR k IN 1 TO 5 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 4 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(4)(5 DOWNTO 1);
END zzz;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_usgnpos_sv.vhd | 20 | 6063 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_USGNPOS.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small ***
--*** unsigned number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_usgnpos;
ARCHITECTURE rtl of hcc_usgnpos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/hcc_normfp2x.vhd | 10 | 13893 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
| mit |
Reiuiji/ECE368-Lab | Lab 2/ALU/alu_tb.vhd | 10 | 7649 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_TB
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ALU_tb_vhd IS
END ALU_tb_vhd;
ARCHITECTURE behavior OF ALU_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR(7 downto 0);
RB : in STD_LOGIC_VECTOR(7 downto 0);
OPCODE : in STD_LOGIC_VECTOR(3 downto 0);
CCR : out STD_LOGIC_VECTOR(3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0));
END COMPONENT;
--Inputs
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
--Outputs
SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0);
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
--Condition Codes
SIGNAL N : STD_LOGIC := '0';
SIGNAL Z : STD_LOGIC := '0';
SIGNAL V : STD_LOGIC := '0';
SIGNAL C : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP( CLK => CLK,
RA => RA,
RB => RB,
OPCODE => OPCODE,
CCR => CCR,
ALU_OUT => ALU_OUT,
LDST_OUT => LDST_OUT);
-- Assign condition code bits
N <= CCR(3); -- N - Negative
Z <= CCR(2); -- Z - Zero
V <= CCR(1); -- V - Overflow
C <= CCR(0); -- C - Carry/Borrow
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Start ALU Test Bench" severity NOTE;
----- Register-Register Arithmetic Tests -----
RA <= "00000101"; -- 5
RB <= "00000011"; -- 3
OPCODE <= "0000"; wait for period;
assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0001"; wait for period;
assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0010"; wait for period;
assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0011"; wait for period;
assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "01100100"; -- 100
RB <= "00110010"; -- 50
OPCODE <= "0000"; wait for period;
assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0001"; wait for period;
assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0010"; wait for period;
assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0011"; wait for period;
assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
----- END Arithmetic Tests -----
----- CCR Tests -----
RA <= "00000000";
RB <= "00000000";
OPCODE <= "0000"; wait for period;
assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "00000001";
RB <= "11111111";
OPCODE <= "0000"; wait for period;
assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "00000000";
RB <= "00000001";
OPCODE <= "0001"; wait for period;
assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "01111111";
RB <= "00000001";
OPCODE <= "0000"; wait for period;
assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "11111111";
RB <= "00000001";
OPCODE <= "0000"; wait for period;
assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
----- END CCR Tests -----
-- Mem Test --
OPCODE <= "1001"; wait for period;
assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= X"16";
OPCODE <= "1010"; wait for period;
assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "1001"; wait for period;
assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
-- END Mem Test --
report "Finish ALU Test Bench" severity NOTE;
wait; -- will wait forever
END PROCESS;
END;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/hcc_castytof.vhd | 10 | 3181 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOF.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** External Single ***
--*** ***
--*** 06/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytof IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32;
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytof;
ARCHITECTURE rtl OF hcc_castytof IS
signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
one: hcc_castytox
GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>midnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>midnode,aasat=>satnode,aazip=>zipnode,
cc=>cc);
END rtl;
| mit |
rtucker/nios_codebreaker | vhdl/lfsr_peripheral.vhd | 1 | 7660 | --************************** VHDL Source Code ****************************
--*************************************************************************
-- vim: set ts=2 sw=2 tw=78 et :
--
-- DESIGNER NAME: Ryan S. Tucker <rst7983@rit.edu>
--
-- LAB NAME: Lab 7: Game System
--
-- FILE NAME: lfsr_peripheral.vhd
--
---------------------------------------------------------------------------
--
-- DESCRIPTION
--
-- This design will implement a 16-bit Galois linear-feedback shift
-- register for pseudorandom number generation.
--
-- About LFSRs:
-- https://en.wikipedia.org/wiki/Linear_feedback_shift_register
--
-- Addresses of this component:
-- 0 status R bit 0: 1 if LFSR is seeded, 0 if not
-- bit 1: 1 if seed value is nonzero, 0 if zero
-- 1 control W bit 0: 1 to reseed LFSR from seed register
-- (note: status bit 1 MUST be 1 first)
-- 2 lfsr R current 16-bit LFSR value
-- 3 seed RW seed value for LFSR
--
---------------------------------------------------------------------------
--
-- REVISION HISTORY
--
-- ______________________________________________________________________
-- | DATE | USER | Ver | Description |
-- |==========+======+=====+==============================================
-- | | | |
-- | 04/21/13 | RST | 1.0 | Created
-- | | | |
-- |----------|------|-----|----------------------------------------------
--
--*************************************************************************
--*************************************************************************
library IEEE;
use IEEE.std_logic_1164.ALL;
--use IEEE.numeric_std.ALL;
--use IEEE.numeric_std_unsigned.ALL;
use IEEE.std_logic_unsigned.ALL;
entity lfsr_peripheral is
port (
-- inputs
clk : in std_logic;
reset_n : in std_logic;
we_n : in std_logic;
be_n : in std_logic_vector(1 downto 0);
a : in std_logic_vector(1 downto 0);
din : in std_logic_vector(15 downto 0);
-- outputs
dout : out std_logic_vector(15 downto 0)
);
end entity lfsr_peripheral;
architecture rtl of lfsr_peripheral is
-- constants
constant STAT_ADDR : std_logic_vector(1 downto 0) := "00";
constant CTRL_ADDR : std_logic_vector(1 downto 0) := "01";
constant LFSR_ADDR : std_logic_vector(1 downto 0) := "10";
constant SEED_ADDR : std_logic_vector(1 downto 0) := "11";
constant READ : std_logic := '1';
constant WRITE : std_logic := '0';
constant RESET : std_logic := '0';
constant BYTE_EN : std_logic := '0';
constant UNSEEDED : std_logic := '0';
constant SEEDED : std_logic := '1';
constant INVALID : std_logic := '0';
constant VALID : std_logic := '1';
constant NOTNOW : std_logic := '0';
constant DOITNOW : std_logic := '1';
constant ZEROS_8 : std_logic_vector := "00000000";
-- internal signals
signal din_h : std_logic_vector(7 downto 0);
signal din_l : std_logic_vector(7 downto 0);
signal be_n_h : std_logic;
signal be_n_l : std_logic;
-- registers
signal reg_seed_h : std_logic_vector(7 downto 0);
signal reg_seed_l : std_logic_vector(7 downto 0);
signal reg_lfsr : std_logic_vector(15 downto 0);
signal reg_stat : std_logic_vector(15 downto 0);
-- control and status flags
signal is_seeded : std_logic := UNSEEDED;
signal seed_valid : std_logic := INVALID;
signal ctrl_doseed : std_logic := NOTNOW;
begin
-- combinational logic: break down long signals into shorter ones, and
-- vice versa
din_h <= din(15 downto 8);
din_l <= din(7 downto 0);
be_n_h <= be_n(1);
be_n_l <= be_n(0);
-- test seed validity
seed_valid <= INVALID when (reg_seed_h = ZEROS_8 and reg_seed_l = ZEROS_8)
else VALID;
-- process: seed_register_p
-- handle writes to the seed register
-- control inputs: a, we_n, be_n_h
-- bus output: din
-- registers: reg_seed_h, reg_seed_l
seed_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
-- Reset seed register to zero
reg_seed_h <= (others => '0');
reg_seed_l <= (others => '0');
elsif (rising_edge(clk)) then
if (a = SEED_ADDR and we_n = WRITE and be_n_h = BYTE_EN) then
reg_seed_h <= din_h;
end if;
if (a = SEED_ADDR and we_n = WRITE and be_n_l = BYTE_EN) then
reg_seed_l <= din_l;
end if;
end if;
end process seed_register_p;
-- process: lfsr_register_p
-- implements the linear feedback shift register
-- control input: ctrl_doseed
-- status output: is_seeded
-- register: reg_lfsr
lfsr_register_p : process(clk, reset_n) is
variable carry_bit : std_logic;
variable new_lfsr : std_logic_vector(15 downto 0);
begin
if (reset_n = RESET) then
-- Reset LFSR register to all-ones
-- (as 0 is an invalid state)
reg_lfsr <= (others => '1');
is_seeded <= UNSEEDED;
elsif (rising_edge(clk)) then
if (ctrl_doseed = DOITNOW) then
-- replace our LFSR with the seed
reg_lfsr <= reg_seed_h & reg_seed_l;
is_seeded <= SEEDED;
else
-- recirculating shift right, with carry bit xor'd at
-- taps: 16, 14, 13, 11
carry_bit := reg_lfsr(0);
new_lfsr(15) := carry_bit;
new_lfsr(14) := reg_lfsr(15) ;
new_lfsr(13) := reg_lfsr(14) xor carry_bit;
new_lfsr(12) := reg_lfsr(13) xor carry_bit;
new_lfsr(11) := reg_lfsr(12);
new_lfsr(10) := reg_lfsr(11) xor carry_bit;
new_lfsr(9 downto 0) := reg_lfsr(10 downto 1);
-- update register
reg_lfsr <= new_lfsr;
end if;
end if;
end process lfsr_register_p;
-- process: ctrl_register_p
-- implements a write-only control register
-- control inputs: a, we_n, be_n_l, seed_valid
-- control output: ctrl_doseed
ctrl_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
ctrl_doseed <= NOTNOW;
elsif (rising_edge(clk)) then
if (a = CTRL_ADDR and we_n = WRITE and be_n_l = BYTE_EN
and seed_valid = VALID) then
ctrl_doseed <= DOITNOW;
else
ctrl_doseed <= NOTNOW;
end if;
end if;
end process ctrl_register_p;
-- process: stat_register_p
-- updates a read-only status register
-- status inputs: is_seeded, seed_valid
-- register: reg_stat
stat_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
reg_stat <= (others => '0');
elsif (rising_edge(clk)) then
reg_stat <= (others => '0');
reg_stat(0) <= is_seeded;
reg_stat(1) <= seed_valid;
end if;
end process stat_register_p;
-- process: register_read_p
-- selects requested register values to the dout bus
-- control input: a
-- bus output: dout
register_read_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
dout <= (others => '0');
elsif (rising_edge(clk)) then
case a is
when STAT_ADDR =>
dout <= reg_stat;
when LFSR_ADDR =>
dout <= reg_lfsr;
when SEED_ADDR =>
dout <= reg_seed_h & reg_seed_l;
when others =>
dout <= (others => '0');
end case;
end if;
end process register_read_p;
end architecture rtl;
| mit |
Reiuiji/ECE368-Lab | Lab 2/ALU/alu_toplevel.vhd | 7 | 2688 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/dp_lsftpipe64x64.vhd | 10 | 4921 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/dp_lsftpipe64x64.vhd | 10 | 4921 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_divfp2x.vhd | 10 | 22387 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVFP2X.VHD ***
--*** ***
--*** Function: Internal format double divide - ***
--*** unsigned mantissa ***
--*** ***
--*** Uses new multiplier based divider core ***
--*** from floating point library ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 23/04/09 - added NAN support ***
--*** 27/04/09 - added SIII/SIV support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 20 + 4*doublespeed + ***
--*** doublespeed*roundconvert (Y) ***
--*** Latency = 20 + 4*doublespeed (F) ***
--*** Latency = 20 + 4*doublespeed + ***
--*** roundconvert*(1+doublespeed) (ieee) ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 19 + 2*doublespeed + ***
--*** doublespeed*roundconvert (Y) ***
--*** Latency = 19 + 2*doublespeed (F) ***
--*** Latency = 19 + 2*doublespeed + ***
--*** roundconvert*(1+doublespeed) (ieee) ***
--***************************************************
ENTITY hcc_divfp2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- output to another multiplier or divider (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_divfp2x;
ARCHITECTURE rtl OF hcc_divfp2x IS
-- SII: div_core latency 19+4*doublespeed
-- SIII/IV: div_core latency 18+2*doublespeed
constant midlatency : positive := 18+4*doublespeed - device - 2*device*doublespeed;
type divinexpfftype IS ARRAY (midlatency DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type divexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- divider core interface
signal divinaaman, divinbbman : STD_LOGIC_VECTOR(53 DOWNTO 1);
signal divinaaexp, divinbbexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal divinaaexpff, divinbbexpff : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal divinaasat, divinaazip, divinaanan : STD_LOGIC;
signal divinbbsat, divinbbzip, divinbbnan : STD_LOGIC;
signal divinaasatff, divinaazipff, divinaananff : STD_LOGIC;
signal divinbbsatff, divinbbzipff, divinbbnanff : STD_LOGIC;
signal divinaasign, divinbbsign : STD_LOGIC;
signal divinaasignff, divinbbsignff : STD_LOGIC;
signal divinexpff : divinexpfftype;
signal divinsignff : STD_LOGIC_VECTOR (midlatency DOWNTO 1);
signal divinsatff, divinzipff, divinnanff : STD_LOGIC_VECTOR (midlatency DOWNTO 1);
signal dividend, divisor : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divmannode : STD_LOGIC_VECTOR (55 DOWNTO 1);
-- output section (x out)
signal signeddivmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divroundnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divmanout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divymanff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divyexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divysatbitff, divyzipbitff, divynanbitff : STD_LOGIC;
signal divexpplus : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divyexpdelff : divexpdelfftype;
signal divysatdelff, divyzipdelff, divynandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal divsatbase, divzipbase : STD_LOGIC;
-- output section (divout)
signal normmannode : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal divdivmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divdivexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divdivsatff, divdivzipff, divdivnanff : STD_LOGIC;
-- output section (ieeeout)
signal normsignff, normsatff, normzipff, normnanff : STD_LOGIC;
signal normalize : STD_LOGIC;
signal normalnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
-- SII: latency 19+4*doublespeed
-- SIII/IV: latency 18+2*doublespeed
component dp_div_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dividend : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
end component;
-- latency 1
component hcc_divnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
-- latency 2
component hcc_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
-- latency 3
component hcc_divrndpipe
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT THE SIGN BIT IS PACKED IN THE MSB OF ***
--*** THE MANTISSA ***
--********************************************************
divinaaman <= aa(66 DOWNTO 14);
divinaaexp <= aa(13 DOWNTO 1);
divinbbman <= bb(66 DOWNTO 14);
divinbbexp <= bb(13 DOWNTO 1);
divinaasat <= aasat;
divinbbsat <= bbsat;
divinaazip <= aazip;
divinbbzip <= bbzip;
divinaanan <= aanan;
divinbbnan <= bbnan;
-- signbits packed in MSB of mantissas
divinaasign <= aa(67);
divinbbsign <= bb(67);
--**************************************************
--*** ***
--*** Divider Section ***
--*** ***
--**************************************************
dividend <= divinaaman & '0';
divisor <= divinbbman & '0';
-- SII: latency 19+4*doublespeed
-- SIII/IV: latency 18+2*doublespeed
div: dp_div_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dividend=>dividend,divisor=>divisor,
quotient=>divmannode);
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
divinaaexpff(k) <= '0';
divinbbexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO midlatency LOOP
FOR j IN 1 TO 13 LOOP
divinexpff(k)(j) <= '0';
END LOOP;
END LOOP;
divinaasignff <= '0';
divinbbsignff <= '0';
divinaasatff <= '0';
divinbbsatff <= '0';
divinaazipff <= '0';
divinbbzipff <= '0';
divinaananff <= '0';
divinbbnanff <= '0';
FOR k IN 1 TO midlatency LOOP
divinsignff(k) <= '0';
divinsatff(k) <= '0';
divinzipff(k) <= '0';
divinnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divinaaexpff <= divinaaexp;
divinbbexpff <= divinbbexp;
divinexpff(1)(13 DOWNTO 1) <= divinaaexpff - divinbbexpff;
divinexpff(2)(13 DOWNTO 1) <= divinexpff(1)(13 DOWNTO 1) + "0001111111111";
FOR k IN 3 TO midlatency LOOP
divinexpff(k)(13 DOWNTO 1) <= divinexpff(k-1)(13 DOWNTO 1);
END LOOP;
divinaasignff <= divinaasign;
divinbbsignff <= divinbbsign;
divinsignff(1) <= divinaasignff XOR divinbbsignff;
FOR k IN 2 TO midlatency LOOP
divinsignff(k) <= divinsignff(k-1);
END LOOP;
divinaasatff <= divinaasat;
divinbbsatff <= divinbbsat;
divinaazipff <= divinaazip;
divinbbzipff <= divinbbzip;
divinaananff <= divinaanan;
divinbbnanff <= divinbbnan;
-- special condition: infinity = x/0
divinsatff(1) <= (divinaasatff OR divinbbsatff) OR
(NOT(divinaazipff) AND divinbbzipff);
divinzipff(1) <= divinaazipff;
-- 0/0 or infinity/infinity is invalid OP, NAN out
divinnanff(1) <= divinaananff OR divinbbnanff OR
(divinaazipff AND divinbbzipff) OR
(divinaasatff AND divinbbsatff);
FOR k IN 2 TO midlatency LOOP
divinsatff(k) <= divinsatff(k-1);
divinzipff(k) <= divinzipff(k-1);
divinnanff(k) <= divinnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goya: IF (xoutput = 1) GENERATE
-- output either "01XXXX..RR" (<1) or "1XXXX..RR" (>=1)
-- if <1, SSSSSS1'manSSSSS
-- if >1, SSSSS1'manSSSS
goyb: FOR k IN 1 TO 4 GENERATE
signeddivmannode(k) <= divinsignff(midlatency);
END GENERATE;
goyc: FOR k IN 1 TO 55 GENERATE
signeddivmannode(k+4) <= divmannode(k) XOR divinsignff(midlatency);
END GENERATE;
goyd: FOR k IN 60 TO 64 GENERATE
signeddivmannode(k) <= divinsignff(midlatency);
END GENERATE;
goye: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
goyf: IF (roundconvert = 0) GENERATE
divroundnode <= signeddivmannode;
END GENERATE;
goyg: IF (roundconvert = 1) GENERATE
divroundnode <= signeddivmannode + (zerovec(63 DOWNTO 1) & divinsignff(midlatency));
END GENERATE;
poxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
divymanff(k) <= '0';
END LOOP;
FOR j IN 1 TO 13 LOOP
divyexpff(j) <= '0';
END LOOP;
divysatbitff <= '0';
divyzipbitff <= '0';
divynanbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divymanff <= divroundnode;
divyexpff <= divinexpff(midlatency)(13 DOWNTO 1);
divysatbitff <= divinsatff(midlatency);
divyzipbitff <= divinzipff(midlatency);
divynanbitff <= divinnanff(midlatency);
END IF;
END IF;
END PROCESS;
cc(77 DOWNTO 14) <= divymanff;
cc(13 DOWNTO 1) <= divyexpff;
ccsat <= divysatbitff;
cczip <= divyzipbitff;
ccnan <= divynanbitff;
END GENERATE;
goyh: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
goyi: IF (synthesize = 0) GENERATE
rndaddone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signeddivmannode,bb=>zerovec(64 DOWNTO 1),carryin=>divinsignff(midlatency),
cc=>divmanout);
END GENERATE;
goyj: IF (synthesize = 1) GENERATE
rndaddtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signeddivmannode,bb=>zerovec(64 DOWNTO 1),carryin=>divinsignff(midlatency),
cc=>divmanout);
END GENERATE;
poxb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO 13 LOOP
divyexpdelff(1)(j) <= '0';
divyexpdelff(2)(j) <= '0';
END LOOP;
divysatdelff <= "00";
divyzipdelff <= "00";
divynandelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divyexpdelff(1)(13 DOWNTO 1) <= divinexpff(midlatency)(13 DOWNTO 1);
divyexpdelff(2)(13 DOWNTO 1) <= divyexpdelff(1)(13 DOWNTO 1);
divysatdelff(1) <= divinsatff(midlatency);
divysatdelff(2) <= divysatdelff(1);
divyzipdelff(1) <= divinzipff(midlatency);
divyzipdelff(2) <= divyzipdelff(1);
divynandelff(1) <= divinnanff(midlatency);
divynandelff(2) <= divynandelff(1);
END IF;
END IF;
END PROCESS;
cc(77 DOWNTO 14) <= divmanout;
cc(13 DOWNTO 1) <= divyexpdelff(2)(13 DOWNTO 1);
ccsat <= divysatdelff(2);
cczip <= divyzipdelff(2);
ccnan <= divynandelff(2);
END GENERATE;
END GENERATE;
--**************************************************
--*** if output to another multiplier or divider ***
--*** use output directly ***
--**************************************************
--*** NOTE: roundconvert options must still be added
gofa: IF (divoutput = 1) GENERATE
-- [55:1] output either "01XXXX..RR" (<1) or "1XXXX..RR" (>=1)
normalize <= NOT(divmannode(55));
gofb: FOR k IN 1 TO 53 GENERATE
normmannode(k) <= (divmannode(k+1) AND normalize) OR
(divmannode(k+2) AND NOT(normalize));
END GENERATE;
-- exp[54:1] always '1'manR
poda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
divdivmanff(k) <= '0';
END LOOP;
FOR j IN 1 TO 13 LOOP
divdivexpff(j) <= '0';
END LOOP;
divdivsatff <= '0';
divdivzipff <= '0';
divdivnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
divdivmanff <= divinsignff(midlatency) & normmannode;
-- 20/05/09 add normalize adjustement
divdivexpff <= divinexpff(midlatency)(13 DOWNTO 1) - (zerovec(12 DOWNTO 1) & normalize);
divdivsatff <= divinsatff(midlatency);
divdivzipff <= divinzipff(midlatency);
divdivnanff <= divinnanff(midlatency);
END IF;
END PROCESS;
cc(67 DOWNTO 14) <= divdivmanff;
cc(13 DOWNTO 1) <= divdivexpff;
ccsat <= divdivsatff;
cczip <= divdivzipff;
ccnan <= divdivnanff;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "01XXXX..RR" (<2) or "1XXXX..RR" (>=2), need to make output
-- 01XXXX
normalize <= NOT(divmannode(55));
goeb: FOR k IN 1 TO 54 GENERATE -- format "01"[52..1]R
normalnode(k) <= (divmannode(k+1) AND NOT(normalize)) OR
(divmannode(k) AND normalize);
END GENERATE;
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
normsignff <= '0';
normsatff <= '0';
normzipff <= '0';
normnanff <= '0';
FOR k IN 1 TO 54 LOOP
normalff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
normalexpff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normsignff <= divinsignff(midlatency);
normsatff <= divinsatff(midlatency);
normzipff <= divinzipff(midlatency);
normnanff <= divinnanff(midlatency);
normalff <= normalnode;
normalexpff <= divinexpff(midlatency)(13 DOWNTO 1) -
(zerovec(12 DOWNTO 1) & normalize);
END IF;
END IF;
END PROCESS;
goec: IF (roundconvert = 0) GENERATE
norndout: hcc_divnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
goed: IF ((roundconvert = 1) AND (doublespeed = 0)) GENERATE
rndout: hcc_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
goee: IF ((roundconvert = 1) AND (doublespeed = 1)) GENERATE
rndpipout: hcc_divrndpipe
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
END GENERATE;
END rtl;
| mit |
Reiuiji/ECE368-Lab | Lab 3/VGA Part 2/clk25MHz.vhd | 11 | 2102 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Pixel Clock
-- Output a 25Mhz clock for a vga controller
-- 50 Mhz to 25 Mhz
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity CLK_25MHZ is
port(CLK_IN: in std_logic;
CLK_OUT: inout std_logic);
end CLK_25MHZ;
architecture Behavioral of CLK_25MHZ is
component CLKDLL
generic (CLKDV_DIVIDE : real := 2.0;
DUTY_CYCLE_CORRECTION : Boolean := TRUE;
STARTUP_WAIT : boolean := FALSE);
port(CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
attribute CLKDV_DIVIDE : real;
attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
signal CLK_D: std_logic;
begin
CLKDLL_inst : CLKDLL
port map (
CLK0 => open, -- 0 degree DLL CLK ouptput
CLK180 => open, -- 180 degree DLL CLK output
CLK270 => open, -- 270 degree DLL CLK output
CLK2X => CLK_D, -- 2X DLL CLK output
CLK90 => open, -- 90 degree DLL CLK output
CLKDV => CLK_OUT, -- Divided DLL CLK out (CLKDV_DIVIDE)
LOCKED => open, -- DLL LOCK status output
CLKFB => CLK_D, -- DLL clock feedback
CLKIN => CLK_IN, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
end Behavioral;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_pos51.vhd | 10 | 6864 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_POS51.VHD ***
--*** ***
--*** Function: 5 Bit Count Leading Zeros ***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_pos51 IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_pos51;
ARCHITECTURE sss of fp_pos51 IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,5);
WHEN "000001" => position <= conv_std_logic_vector(start+5,5);
WHEN "000010" => position <= conv_std_logic_vector(start+4,5);
WHEN "000011" => position <= conv_std_logic_vector(start+4,5);
WHEN "000100" => position <= conv_std_logic_vector(start+3,5);
WHEN "000101" => position <= conv_std_logic_vector(start+3,5);
WHEN "000110" => position <= conv_std_logic_vector(start+3,5);
WHEN "000111" => position <= conv_std_logic_vector(start+3,5);
WHEN "001000" => position <= conv_std_logic_vector(start+2,5);
WHEN "001001" => position <= conv_std_logic_vector(start+2,5);
WHEN "001010" => position <= conv_std_logic_vector(start+2,5);
WHEN "001011" => position <= conv_std_logic_vector(start+2,5);
WHEN "001100" => position <= conv_std_logic_vector(start+2,5);
WHEN "001101" => position <= conv_std_logic_vector(start+2,5);
WHEN "001110" => position <= conv_std_logic_vector(start+2,5);
WHEN "001111" => position <= conv_std_logic_vector(start+2,5);
WHEN "010000" => position <= conv_std_logic_vector(start+1,5);
WHEN "010001" => position <= conv_std_logic_vector(start+1,5);
WHEN "010010" => position <= conv_std_logic_vector(start+1,5);
WHEN "010011" => position <= conv_std_logic_vector(start+1,5);
WHEN "010100" => position <= conv_std_logic_vector(start+1,5);
WHEN "010101" => position <= conv_std_logic_vector(start+1,5);
WHEN "010110" => position <= conv_std_logic_vector(start+1,5);
WHEN "010111" => position <= conv_std_logic_vector(start+1,5);
WHEN "011000" => position <= conv_std_logic_vector(start+1,5);
WHEN "011001" => position <= conv_std_logic_vector(start+1,5);
WHEN "011010" => position <= conv_std_logic_vector(start+1,5);
WHEN "011011" => position <= conv_std_logic_vector(start+1,5);
WHEN "011100" => position <= conv_std_logic_vector(start+1,5);
WHEN "011101" => position <= conv_std_logic_vector(start+1,5);
WHEN "011110" => position <= conv_std_logic_vector(start+1,5);
WHEN "011111" => position <= conv_std_logic_vector(start+1,5);
WHEN "100000" => position <= conv_std_logic_vector(start,5);
WHEN "100001" => position <= conv_std_logic_vector(start,5);
WHEN "100010" => position <= conv_std_logic_vector(start,5);
WHEN "100011" => position <= conv_std_logic_vector(start,5);
WHEN "100100" => position <= conv_std_logic_vector(start,5);
WHEN "100101" => position <= conv_std_logic_vector(start,5);
WHEN "100110" => position <= conv_std_logic_vector(start,5);
WHEN "100111" => position <= conv_std_logic_vector(start,5);
WHEN "101000" => position <= conv_std_logic_vector(start,5);
WHEN "101001" => position <= conv_std_logic_vector(start,5);
WHEN "101010" => position <= conv_std_logic_vector(start,5);
WHEN "101011" => position <= conv_std_logic_vector(start,5);
WHEN "101100" => position <= conv_std_logic_vector(start,5);
WHEN "101101" => position <= conv_std_logic_vector(start,5);
WHEN "101110" => position <= conv_std_logic_vector(start,5);
WHEN "101111" => position <= conv_std_logic_vector(start,5);
WHEN "110000" => position <= conv_std_logic_vector(start,5);
WHEN "110001" => position <= conv_std_logic_vector(start,5);
WHEN "110010" => position <= conv_std_logic_vector(start,5);
WHEN "110011" => position <= conv_std_logic_vector(start,5);
WHEN "110100" => position <= conv_std_logic_vector(start,5);
WHEN "110101" => position <= conv_std_logic_vector(start,5);
WHEN "110110" => position <= conv_std_logic_vector(start,5);
WHEN "110111" => position <= conv_std_logic_vector(start,5);
WHEN "111000" => position <= conv_std_logic_vector(start,5);
WHEN "111001" => position <= conv_std_logic_vector(start,5);
WHEN "111010" => position <= conv_std_logic_vector(start,5);
WHEN "111011" => position <= conv_std_logic_vector(start,5);
WHEN "111100" => position <= conv_std_logic_vector(start,5);
WHEN "111101" => position <= conv_std_logic_vector(start,5);
WHEN "111110" => position <= conv_std_logic_vector(start,5);
WHEN "111111" => position <= conv_std_logic_vector(start,5);
WHEN others => position <= conv_std_logic_vector(0,5);
END CASE;
END PROCESS;
END sss;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/fp_del_var.vhd | 10 | 3103 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_invsqr_core.vhd | 10 | 8541 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** FP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 36 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 17 ***
--***************************************************
ENTITY fp_invsqr_core IS
GENERIC (
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_invsqr_core;
ARCHITECTURE rtl OF fp_invsqr_core IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(36 DOWNTO 18),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 12 LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 12 LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>36,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone,databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
invroot <= multonethr(36 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fpc_library_sv.vhd | 10 | 100780 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
| mit |
ou-cse-378/vhdl-tetris | ctr2bit.vhd | 1 | 860 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: ctr2bit.vhd
-- // Date: 12/9/2004
-- // Description: Display component
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ctr2bit is
port (
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (1 downto 0)
);
end ctr2bit;
architecture ctr2bit_arch of ctr2bit is
begin
process (clk, clr)
variable COUNT: STD_LOGIC_VECTOR (1 downto 0);
begin
if clr = '1' then
COUNT := "00";
elsif clk'event and clk='1' then
COUNT := COUNT + 1;
end if;
q <= COUNT;
end process;
end ctr2bit_arch;
| mit |
danielcardoso/html-pages | example/All-Icons/file.vhdl | 12226531 | 0 | mit |
|
rflamino/StellaBlue | core/A6532/src/A6532.vhd | 1 | 7554 | -- A6532 RAM-I/O-Timer (RIOT)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end ram128x8;
architecture arch of ram128x8 is
type ram_type is array (0 to 127) of
std_logic_vector(7 downto 0);
signal ram: ram_type;
begin
process (clk, r, a)
begin
if (clk'event and clk = '1') then
if (r = '1') then
d_out <= ram(to_integer(unsigned(a)));
else
ram(to_integer(unsigned(a))) <= d_in;
end if;
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity A6532 is
port(clk: in std_logic;
r: in std_logic;
rs: in std_logic;
cs: in std_logic;
irq: out std_logic;
d: inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0);
pa7: in std_logic;
a: in std_logic_vector(6 downto 0));
end A6532;
architecture arch of A6532 is
component ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end component;
signal pa_reg: std_logic_vector(7 downto 0) := "00000000";
signal pb_reg: std_logic_vector(7 downto 0) := "00000000";
signal pa_ddr: std_logic_vector(7 downto 0) := "00000000";
signal pb_ddr: std_logic_vector(7 downto 0) := "00000000";
signal pa_in: std_logic_vector(7 downto 0);
signal pb_in: std_logic_vector(7 downto 0);
signal timer: std_logic_vector(7 downto 0) := "00000000";
signal timer_write: std_logic;
signal timer_read: std_logic;
signal timer_intr: std_logic := '0';
signal timer_intvl: std_logic_vector(1 downto 0) := "11";
signal timer_dvdr: std_logic_vector(10 downto 0) := "00000000001";
signal timer_inc: std_logic;
signal timer_irq_en: std_logic := '0';
signal edge_pol: std_logic := '0';
signal edge_irq_en: std_logic := '0';
signal edge_intr_lo: std_logic := '0';
signal edge_intr_hi: std_logic := '0';
signal edge_intr: std_logic;
signal intr_read: std_logic;
signal ram_d_out: std_logic_vector(7 downto 0);
signal ram_r: std_logic;
signal clk2: std_logic;
begin
-- This clock is phase shifted so that we can use Xilinx synchronous block RAM.
clk2 <= not clk;
io: for i in 0 to 7 generate
-- TEMPORARY FIX
--pa(i) <= pa_reg(i) when pa_ddr(i) = '1' else 'Z';
--pb(i) <= pb_reg(i) when pb_ddr(i) = '1' else 'Z';
pa(i) <= 'Z';
pb(i) <= 'Z';
pa_in(i) <= pa(i);
pb_in(i) <= pb(i) when pb_ddr(i) = '0' else pb_reg(i);
end generate;
ram: ram128x8 port map(clk2, ram_r, d, ram_d_out, a);
ram_r <= (not rs and r) or rs or not cs;
timer_write <= (not r) and rs and a(2) and a(4) and cs;
timer_read <= r and rs and a(2) and (not a(0)) and cs;
intr_read <= r and rs and a(0) and a(2) and cs;
irq <= not ((timer_intr and timer_irq_en) or (edge_intr and edge_irq_en));
edge_intr <= edge_intr_lo when edge_pol = '0' else edge_intr_hi;
process(clk, cs, r, rs, a, ram_d_out, pa_in, pa_ddr, pb_in, pb_ddr, timer, timer_intr, edge_intr)
begin
if r = '1' then
if (cs = '0') then
d <= "ZZZZZZZZ";
elsif rs = '0' then
d <= ram_d_out;
elsif a(2) = '0' then
case a(1 downto 0) is
when "00" =>
d <= pa_in;
when "01" =>
d <= pa_ddr;
when "10" =>
d <= pb_in;
when "11" =>
d <= pb_ddr;
when others =>
null;
end case;
elsif a(0) = '0' then
d <= timer;
elsif a(0) = '1' then
d <= timer_intr & edge_intr & "000000";
else
d <= "--------";
end if;
else
d <= "ZZZZZZZZ";
if (clk'event and clk = '1' and cs = '1') then
if (rs = '1') then
if a(2) = '0' then
case a(1 downto 0) is
when "00" =>
pa_reg <= d;
when "01" =>
pa_ddr <= d;
when "10" =>
pb_reg <= d;
when "11" =>
pb_ddr <= d;
when others =>
null;
end case;
elsif a(4) = '0' then
edge_pol <= a(0);
edge_irq_en <= a(1);
end if;
end if;
end if;
end if;
end process;
process(pa7, intr_read)
begin
if (intr_read = '1') then
edge_intr_lo <= '0';
elsif (pa7'event and pa7 = '1') then
edge_intr_lo <= '1';
end if;
if (intr_read = '1') then
edge_intr_hi <= '0';
elsif (pa7'event and pa7 = '0') then
edge_intr_hi <= '1';
end if;
end process;
with timer_intvl select timer_inc <=
timer_dvdr(0) when "00",
timer_dvdr(3) when "01",
timer_dvdr(6) when "10",
timer_dvdr(10) when "11",
'-' when others;
process(clk)
begin
if (clk'event and clk = '1') then
if (timer_inc = '1') then
timer_dvdr <= "00000000001";
else
timer_dvdr <= timer_dvdr + 1;
end if;
if (timer_write = '1') then
timer <= d;
timer_intvl <= a(1 downto 0);
timer_irq_en <= a(3);
timer_dvdr <= "00000000001";
elsif (timer_intr = '0') then
timer <= timer - timer_inc;
elsif (not (timer = X"00")) then
timer <= timer - 1;
end if;
if (timer = X"00" and timer_inc = '1' and timer_intr = '0' and timer_write = '0') then
timer_intr <= '1';
elsif (timer_read = '1' or timer_write = '1') then
timer_intr <= '0';
end if;
end if;
end process;
end arch;
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/single_rate.vhd | 2 | 370178 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
qvnP+TCG9SuXRvv7a3rmuAv2C6rsYM8jAKFPno/STh9idqR5n0FK43o3aY0omE0ZwrzY2ttHqnIj
3dqICvMRlw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
GBOodxVyVUrkAi59/KekQELXvq690plpxovv4wFnUwDONHz0YOQk6eJs/2bJDQJGejj9wuVDqsbg
95gtN/U6GB9hHLJIX9sliuWeFQwGDPNn3O236v9ZTpQMiWuuja0hofL/S999Mqgr3u0cbTNoYkdE
fs3C94VadzwBdg2guhU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Cp8sEszpVFNPLJPbdP65Nzx/o8LDk5SPLkg5C3O8IHenLI6lEcUl5CEFNcD+mQzHJLbB3ViDw5OZ
sgSNOhpwRRTqjSPTxsdLlccEWzLDsox0Z/Suhw56InB+FChiRoMvwza4YKAkrc0mjoslVnYYOLvY
03Q0eCkX+SSnInS439o1sjZOOOua09vETcssSw3+gamMWM8ikrd3CoLzo8+E3VpZu4xFZVyl2Ow6
cacHGQmFeanhwzkrMvbsmRFeT9LmjLq+lBUxpwJGJr2w9sAJ0MZFqUwo8xyUHzB8x4oZRQo2e/w7
cJ+zASBCZsksLQQ4k9p1S5COjfq4YudL0nH/bA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pa8yyOZJFNW+wentPuYPmJYKYoikN5fKHznWMzdv7L8didyyoHPytL8YzqL4fwRIBlRmogb/E98u
fBDEldyIabwfxetVJOoLC96J75pfn6s08GUEu50qfO6ne5nrYpXBm6rLgqcAlL7ZOYpNkrNXXTrv
zjq9I8LcvtMOD8N17Jk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HagCWHSO/Xsb1R5I+VaMowWwTeTXVdAudCC77O1kf7f5N8TsxigBkB7r1lAKxGgbrhJmGbCbdPPv
sc4tSQGz+l2hTPDz/7E/onmC8PZo3jnStfGPUiuN5D+kgfYW/Z9/1IyYWsoof3wsdjy+1CzG+vd0
uyMOeu+yCf2pLJxP1VcmeUT/ya+wVBaDRcPou33SroIYIPNIJRhTtxPOGkokQTIkDXStEKfhU2Wt
ZdVXorAtCb5O5KE16dibeZasxjhJkW1WqFfpcx0FM7z3ntCextcpI7pbpW0yrzGqITyOHwmCJiGe
Rs9RdBls7mIEhyC6sBY8Mdt/h0nfNqgp7VYi7w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 272288)
`protect data_block
PpNZ/e3KODH8af1haqCiAcrXGybbF7Uym0XDpYm/sBhNIq3hbnvm0dlevSxu6Xhq9JTv/ja+e617
J8kWSUTddKptqXsvpZbLkLFwNay+N0AWqyuFWUP1u+9H5ZwkG3uWgUrAVn92bHddKsn+Wt6vqZmL
uMZxCXLNBRLmSWCM6U9PhflDO7PQVKq2xyVDBotkFc9x1M42AuIGdPqILXugUZgdzq6j18KlgGyk
6l0nGQdEjASksHLZEzk5IjmftdH5/gWPx7TPxj1WGCBnsOoey9MOe/BQFd+eACHjaMZZn/dvy0X3
lwqwEs+RZikTmNHGVWPl2fXoOPW8cTocvHiFVHdqGuRHyBc0E5NwrWnQe3mK81gjIjg9tylrr3yT
qVTEtOC87rTfNip5aQOE7NyC+Qptc2pdODWCCGEVkGPOG5Dq6CiiMLAvaQuQU7klcnIvABK/1Eb1
M6i5btMBG3Sk1LdyNJNssBTiORO1bQStALo6fqVcZKbjDx5DVdfxsNlJbfXBJrjUvzHyjFIyxhVl
wbVMmWdk46rlDyGBoVIuSZEUDTJJohbSzlIauLs7YQnDAmvk73cclza2vJYbSh5VoQtH01pjZ0QX
UWg+rCGLKhgJYPduxLkFTQ24aMcZRc/1usRcgut7cfbcy1Eo5wCSSvN3/h2KEALpnnFwH19p9yPa
e8A5/I/5+dNsMcDWaRMN4u4H8jG9wOAEayfo2t70iq70+OOa3OUBVUS+HLclNtkEUC1hw1FOGmam
gk+I4iKbVHn3fcdV2ys2YXDetX812IZs24Hm8iqbFYzTMdSfJnVquq4ZmhZcjnWQDcUqHRX5IYVa
d0yEaCIvqFYJsLxGcdCqELXm2ZvvhAzA1Xh9si7mi1nbrb04wEK1HlHXw+s11Jm4E9wIHZdauRRf
o4Xs77Pzgv3TOPUcpSbht7ZN4h9tlLMiE9zFRJnONNMYADgLu88BkkKyYwln4iUc6syZYP6UlW1L
sdbzreCCz1jpTKF/502NkQ5HdAlAls5x4Jk+0w36bohlGvI8XxaK3KSkaYl5oSSZbrzb03EDNZWM
nQIv7Lj+EojGq52bAHHa9UQqYF2CklQUKu96sFT21NaFt6hOBMY/QON2uoBAKwcKLyf3jAOHiN/e
JmT768qjlZEpR3/paTbviNi77YEvyt4mxnHwGgotsqgdcjoFRXxEj92CZ/7AvhmWitSWDp2/rsx2
qKKwZSODMBtSthpJdYZuMad6gJXShRMyleQeRg4OTxuZvrRfXvehx+RpvCkW/uoVWv01/CWMOuJA
4zUZPPkrLOtW90ERQui5Zz5pGuycLzuLn/mjUH2JtegKipesLXQp5WIXNBolqpWT/t5PxjgAOiPY
/miAazNAPHjzdVJtGb0JbcTzm879GrcFrLZRiP1TzmqFQOwmjonYul7hY7x3JFM4XHn7cr8SwF3A
B5I72A1fluHdc2fw/Qj8X49PVC+oX83JAuW8BhRW6WJCF5YGglBHpMpXgRxAASp5NlsOhKFhrnhq
yyjIYFw7FB/7czMp6xNjii9KB+vhr/IvpDPnyS/uGo/Ty/lIbLur9f7mx+oRmHOhjgvour9EGWsi
3liu4P8fcD5sSPQiXWjCUqIdpA3czuvZUUG2WoFNp3494nId/qqZWsOXMgUqIB/Xkb0cXBTYl9nM
W2UTKY/IeOEPh/ccAwG8Urj3uPFWszuTa5mxYxOb/bRzIZBsE1BpMDmF0NT7PJQ3QSBUlOjU/D/h
c57mN995yxjgm/74vPIF/Dapwwy/wEBUMQmbWJ2Xujkgk9M/UlFgKTvLcRdV37GFl7WODuz7Utdw
iwi7yaAceHQ49oHeWH2g9yia+Q9/s7NLBvF+hJ9Trx3LFC/ZTJT6YouROGq/ZM+MtQe7tfS8Gm6e
EbrBBbGhKHJ+20dEslZDp22jAQ1sezg01MxeD6FoPIme6nh7woavT0DYfKDSn4V/waRWKU6uoNUn
hUcsP8k1jHukT3B8F8yjeH28AUH4JvqEgBRtWAq00lPmfPvDS9q1KuTmD+uxnnMc062ukeVpCGE1
WBz2VTmRrdvkjWAsWTnpYH3lxcMAw861AkO28Jpb2C0mM+n+/sEsMsmSzoJ930WxXWcU+muIi6t4
KYOVLvdejLFaU6uz3sLbh43HAPGbiOp8rfcQqeHSuJKV2TBb/wWDrBm+Px1OGhI+ZOn8YUhN6O/j
2O4bpM8Z2R6/R8kpxJBbCQWvMw5EYTBcBROOVuEBjB0vh7y1GGHFek5WBNiki+vsNoVyo5MZUvyT
dymmWI8yxCy/coGsTZLnGB6UwHD2uuS6P7PanKMSNTFcy1Mg1lNc9bOV0RMir17++2ouQBqoeyZ6
c5M6ITuz6+xBVWEZIc6h8SVYhbznB4EDGolHl7PJNEt7rgQbubNa+9iXCG/p4EPCGg7bkcwX/KRV
pyJgxAlyL7awtTygx2C1qHrl5C/qo5TPxq/uvU0fW3pbkMLDDvzXY8Kt+ZeGxg7J14WDCTPDyWVd
qzQGE1i48qK0TJOb+T3kkWZcTWJ4+5Au5Tl3YnGdr5lBzSawl4bIFKXYxxCBTuANkLeFnLt9HWsM
khmOIcilClWDvnTO4G6ZysEfcmg2MCFHZKmzSjKnQdNqtGtusO+ItFGIJEGDuQU1xbY9hy2d4dkk
0nFDZmfiPJ/PMZHQWMhIa+FFOWic9RJBGNS2gHdoVFcVv7kNM6QwAEX8mpcU0YWKkOLcKmCp/y1k
7m5bu1+2wbauGKHlygh0WdjiLz2IqxP2rNXdvFAN/BXp6mSZy7oLNuRLLllxOgpEwPmkNHjYvW3z
BQ3m2T5jjZOXA4vzwW6Lv5rmrabDfx+KxTreHBiIfra9mt6AQ1DF6LIUqVSKkNS8HWEivFgUCqne
CqHRGCrwJs/lkxT+4YkxLgHlgALtv1zeDZxlBQbXxw5Vh0t9MPL/YS1qjvZs9qOwne40pxjOs2I9
N//h6Q1HGC5MegAvqGpWMOMez/COBBn0+0xAxcFg9fjHjnDDMBACeL3T33Ez0Ec75SLoN2kOWlrC
HgvYEXW1/oPHKHvcukGlPsRrKmcLs/f1Tz5zdpU3pOMdQ5x6fCxfsdecSwEslhaStsE5E0v/B9qv
nvGvZhvh1WK0ca6ox39NpzAsm7NF/FtJfjYf9PbTUQg3e+Dqf1uCPrhzjGWtaVLWlTZYmsqZJU9h
AgWMDEGYZ6w1qaMBzytBs2AUjsRhFXPvqJQqDnLk9bEOEemcGdXVfdZKLE1cR7C3/ESyxh8N3GNq
tMDdHf0pQpk1o+vZGV0pJ2isABJT/+k4oZ5/M+9L6vsS4TlaVpjIvoz9vlVeagJSRNQ/eLF+vX8+
bYyu2dBGV0PjkG5ySdEV0+0/3jPHuKHwzyJiG6EHwsg8cRpAjt8w8BVu3GEql3dqMwuGwgcfdoU3
w9D1c2VZpOga8ID5j9PmeSVLEoNHajG6wilyu1pSINMAj7HnEbHku2xQ1BRyuG0taFRKS29mw1zF
yKaN75UW2vUEm7KCe56Gs6tu1fhKtUtVFCWVgxIcuZfJWh44iQEXupEaTPD/jqlO8g2AifoDdpP2
3vhgnqcwLDjOt8uZzZsMA4/JgzV6haCzJYZDwxZ/hCEKA+hxi+EqUXz+6FIeRgiMB9sq6rcNEFqE
wTpro+Us9hckcHm0nPAHT3aZRVBpixaejNfLjgFisDNTF9Q/PkRdUghRhtKfZGXmUTEyAzUIYCTH
BizFVvuqz0SCwtKfYChRhwtjm53XIVZk0lbcChahNwcaWrnFisZZ1nBRVmhql6peeHKWlYwgIeV5
2YmzHoEvpidTay0XUnioAZkC2VPmHpIrmnE/bwSmfDG5bJ76+4/9BmY17d1Tp50YVRSL2vVKBo/Y
Gkw4+4l9ke+rjWFpaIbvvcqj1taezl+dU9syKzTktZX7KYybHr4KahAfKEUbmGWUi9AlrDdf2VS5
5EtHT4vAen4S/4Jcr0ykckmNsr0sBOkFJempCep7SRgGSO29G8d5XhCm7X/bYrimsVayUCkgF3En
pKsE9mw8SHjcVjn1A30QM/LTjzwetJzbmaEUy2z6jd+lY43yPLxlU9g+TW/sx1kBpfuyR0LMEiWT
pnMS/xZrCl3q2Yql1tc0K6JjNtQAYLlBzW2r5tftIQdKvyLTrAnyPiXw21TxBTo2HFOQGq0CKfUY
fCFt0J4GfJ8Km/ghL2L1W8IhjJ0hq7NtrU3aGcc1FfovqVOmZkWNKjEjHciYZZHd2yhgfCcl0oCZ
UgDmpBOWVklm3XJd+QMySvADHWq9NyyAfwBjsN906tnHKmiFcbnsCS11mkM7FQRhoGrn/mjpl3EE
OJGPRMZobTgBmAcNdxdtGo3EAhN3e2WhZQxzkPe4/1CIlz2oM0neQ4UYJ48zTrOoBZ0Y/jSXzLJj
k+xf/4EnVLTwoUyZFi+xieeOZO6KykpWYZYtrqdACwEhVtB/2sVsVdiFl1iS2jiTvOwA2heRT98Z
Y7gfNt6N24BCRGvDjsJCuWAfWFniOYrFKLQ0RBBE56lzsH2Fn81D8sQz5wm4C1UJpVxKcPVg1Dnp
F97DPilV2NL2j6RoZ/VLisps+FbRFwkCZlEBdubjUYaT4N3s+ozCZCkISpCZY4nVwfn5Krjz2A7l
GK1ikxkxhZWXfzB5IDWcjr8PoekwL9cG94gl/6ria7AK8ZTr39mRTlMjYzFP2MlwIvfN/1A6YaYI
KhK7k+Ue/PzTx0/9p+iznJHTYV5X2Qk3V2nlqYG8q2jFlZ75xUF/qZZEBSxjt5NbV6zrHwB2+sJo
DGeedrA/RWnjBlEGc8H9UYf4Iut2dbcisZrdY0evbjl6tN+HiZORbSVcwKmDZP6pbg/877kW7fe/
Fo+hiLDOHMPkGPPuqmWyaEs6rccror/iN/zST0INrmRazpGXYDD8Jr8FtLNFC7Z+Bya1PU5xJsWe
HU86+vk++lVBgMA9DVGNjWGnD30xrAzvv2pbe526ZltnVMU6EyGtDV3C0nDi1uVxWnIPuoIr81J2
a0bfV7ZAY742nk9Jg9/KnzYTThsYmDXmAwWUKdOTDzbLxvBRn35H8ouIgoGIkKU1ZXez66PaXGqx
LpVYMfh7cpbrKKfs+6D2JxFYlGiS3rqQJCBZc3uZdMlAKJz1TJX9I0suGFqI/r+Jyi1GZ48Tcwhk
IDHFP/xJdNVZzvBpSdEDo2Ges1euUhWKyYX1pujez/AIfabHzzzl423E/aOc1WKtLa3a2f+XRROG
dJ7liSBYNENWIZD2DYFNtbWvslY9ZQWVIGhr6d+MMMwWTpEE2OrJ6StURVch2XFrYmACEPxsCBct
LpeAhf1OuhVi1jL0QHJ8tqND/80QdRBNGPcH2rJXl70c1zoouuz2IzvkV/VrFR3+CFq/01lC5xvO
XxOIqsvJQOwYIogOsldfQfYS4z35Ntrm/ABAe2Vkx5Sv8KVz/nkMtOlmHzt92VlUq9xGNdjVjfWs
qWRe7gcCEqyskenmCDviZkvaSB4niEn7ueM5mzmUuwRNaFMl7ndiIRF9lbyZANBzG141JycjUF76
NDoda1EEdYTbeFDQnV51FQaaA6MYqOWkuCP/3T9o4RNkNwYOmpyQYV4EuLw8taDPtRxdlPx3qFTt
/aHyTmi3RNP3aW58y9oeAZLO/QEEryh/bRowkVC5NsrxadPXnvOtb/WIY+zW04gFdJsvE1v1Av+L
Jaj3tP319DW8vqUoBi+4X4XHNwAjxJtQgl8vs72HR2ET0HPoTUdPWJOVDFSRRTi0aHHm4ulHEu4Z
rJz0MMkYJMKymDrXIEEbYmIWWAjrUvWlDguYoP3B3eYCknvJBASMUvXbWrnBY4A3fUYe2PqhUxRp
T18120nvLlVZR4efL0/fCDADdd1TsPwWCSY0AtzwjGPJ5qhY3b77p7WUr9wJaTv2CR/E9parBznJ
R08d6nJTWPbT1kkP3E4Tcj0VmpGoVkV8X9xJx4cpSHewoWPrRa++bE5AMPHwW4wRU/G9zk0Js8BD
EW3TfQdEWNU8fWzVlYb8BUcRflKRRvll8RsKmuSn1wOvaAMtP7Id7nMjBwPDZQKavJIq1pVqKgdk
G4tt+ir4U7TBN5EXbWfv7WnIuYQT42ns8YYk8HXkWt/JGfu/R8vsNl7GS7zruU6TX6S04clMyPkl
eFmsZj8VBVdNxrXiQI+5IBiveXPB/DVy1wNwx23Spx/qDSlmxBKWlOqOauLi1eIXrC55BbvHJqVN
RLWB43Rv9/NFqg3cJgKzMb/TU0WxA6pODO0xN9DUKUimykk4BCuORwEcmRyvc3eXEbMFwNvKj9BO
m1L0rFBon1YQHeQbyuI4qwBkQkM9kOJJjGfoFLShjWjjfXsgY/rXpHXEB1kgfdYR59h/nh7yJoNO
VhtILmnd54joXwctXj+cFyX3T5UublD1znCOX0Q1GUucar82RgwuBxKSZKnvXK+BlHCZt2G8ofD7
dKlQSkclI8U8mJt09KjyyQ3gGu4oQeGV9TWb9JbF38J1PQ8JmljzFFwtUX9mb1VSIWik2DqGwY8U
x8LknSge1dsFMp68KKnKQgHQjEvisJAKozw6OIhfAQXpG+5ybYi+GLcZxdciUwcn27G3+F2gsqf0
pXONR9/AYGjvetRI6K32fQ4xv85rxaWIC34zsw+ToWZ28b04+97g+OuNH/Tdn2RzFHiULSoCkEKH
OcEQmQ+7X+uAkGo4f35Lkf5oYKf7x9mUk5y/u/ayP+PCPL/fONAHwN8Tmip1+iiYG19jCzTk1T32
d6GNmoQ3EY3A8lysWutopjsyF6YpG0pumY1GikiO5eN8oRROREX9tZVZVaS8FaYnpc4Is8XkD87u
rMaGqHSeR+LsEcuXeZsLeJoYsHNMoVI6vaThA/lhW5jRapVgQibxRRZMJmy6VLqUbnFwNvpFNm3B
65BQjAxl9eRXI0+BJJ1GyhML/8Nvt1peIygwf/ns1pGtoEpKEbGj0+A7TnGfA5t25X4Fs8+OJwLn
PxXwNywHR2f349eEjYJuCQvEYsmBJbg+/wVTh2lMBWatywTBcHh3dL9dAw1dc4ODICJDc4GOKLy5
0quGTfOWinmRb9yi7V/sZSN+dmRk8KRlOTkfXgdOFrMXsl+ROTIoH4xDsw7wYO/dspCJG0bQx0d5
/KEX+pI/NUJdBoM0E8Jfaqqn3Ie9KD947msnvOuCGWbel1TN+u6eQSWnMES2urpoKRwfvSvpBzg2
sGV4atKYVt0932MesQ6hll+QGk7oCr1dq5RSXSibNFDmrPA7w+GTc7MswTnxmNvDaOOqI0nOYuXK
LPogBs4NQ/Ny07uHsbFXtfNt6OYwijo6HseHNl9307y7jN2gEHx4fBwuV0r99rNbGBvR8kPNCStJ
wHSu6hwIlEwhvGZpjVRoeFzomN7bQRF0cPdzfTHQQtLkwESfeJaUg2wVzpLZQCghAXDv9dQ0VxiX
fqYi49OcZCakT6hizABQ2hWxWcQAar+bYf3pbm8IYl2hOTxOh4TlmSPexQd1h2wJiOrmTCaADbVH
DhCCgWxx025LM5rmQ4EvzYDQGuq6jGiAY6SM3NBC+Sy1THkn6hd5lmxQGa7xc5SfWW1jb++YDLQg
jqpnfdAsMh336Nf0g+cBB0TL7QWkEQeUwQl8/dqm2iEV9ZaSKLvzs1P+ZsHqp+lEJftDtK+3AEZL
+dEqxTbIa5C1DmjEmS3mQmwrS7K91z/d6JwYRSbfSveHUEQ8cYmsv3Mrd/HaeFPprjvaqiz3FMWa
nh+aS1zXbw1j67fLuUnPNCSoITcngYebT5dYjnS/vD0D7Wc6pGEfrUX3Ug+PPgAEtVYOaJVfo2Wc
JPmU/vX8BNvM0jPQQGQsFzmNtwcNRP/omZ6NMFlNx0fOxZazuO8dRZZ/Z/VPtJdoqrUPgPYx2ZEA
Y5U2QDdX8ryyoTLBRYMqnjte9ptKp1nM58LK/znLjn1YVmeukb09MRV6PWi9Z1JWcYEQ7xM06T+S
5T5bFYcv92tsphGClPYNlJlTC/CW7QM/mAP/Ck2+kUcZvxkobkNUZmrhPb+0fP8+cujaOwbtt9r8
dWYwNI1WrpwvTwQGseZucM38BAwNZ+7nUy4uROB9zP3dsvdEenLcl3mf2wCSrYrsrVvmE2M8yWNw
3796Pfo9QUom8fwxIaXnT53S1tb+miN6xqUyPbnoHehc6O0ivOmc8eUGZA69ppoD3LJoGDT8dqMt
NdAoMfkayMozBj30vMIwxdZdw6a3bpDCaDdtVAGiVXcSOD8q/grzJ4wCqZP+JY/d54QZou34orzw
EFlbHzV6QkPR8YZ1swXJqdN3nDJpPN2fp193qDB+wB9+vJk+dBiz1HRke+prwJ8G548uxFZPaGdM
H6kGaEKfD4+5SnGS2dn4yMma3GBFOdLVlTM6f6zRI2bFwohSPljL2XaotZOQDQdwVCxUrXPdj3R2
9Osy5gnhhWM4ABz1Hkuu7NLD5ZP3Gf8f60zZJqraVK21C0Q56UqiXngaSl26iOv5W9JGM5CD/KB4
2AYL6zaRkXjaLeFVy7M/X5q8GBvN1QSqlTbO86KYnJyRyEP7HtECJCXuTH2+DiITh5upUGS5459Y
JbPnqnYcGYyuagrheUbbN7iCpGDeGPZUleMVIntNl+ZCUEW0v1CbftRtdpNfonGWU4ZRWs/D5kV7
criVMFzgt+8Xs3XVXmiHjdxs7+iaJsZZ5wCO2GDTmGwTBxg8lWO0E7K3t9BWAZ0XaVqf0HKKhwTI
TQZCoUkLsGLGr2LKMTnSkQHyIIMOxFa1nq+kcAg6EJNf8TBw03FU9etQURwJFd+K5kmWD+Xa8jTL
eJl1L4CEIe3tAKhITV13LIrQeiB72w8+bWkBKH8h07YmChNP9YfcUmOMYFedqNKttrNDqH1N/F9f
bnvpXRp91Ip1LpOJoHf8OLZDnczUqlXKrUDVK1lUqfBkrfY5+BqPM4ACNQ+LYwZU1WY+cJcIy+bF
kW92d5jwcjuviSCyyGHKj3IdPgjf4OEm3OkYRwB4tZhtp288ub1wiDAkJ8zRiTYG5tQf+itdEfNB
6Xt++9OmF2x53U82hSMOBmTjA0AgyeYuhdmSPON2eG7ZgzqJZTInRjDiK52zS1f8ZMp56UhKwzwX
zppdxwNUApyunkLqlhYRzwcf1W6079tC8+9IAbMJS6dEP+hnLbJbw/ul7GGWVw1jEazkZvMWefsv
0JuzfAITYm4Xy3NA75I656fgeIv4tDBAShitsFMpSn63uFBuv3gcizQpALHB8vk6qRhI94CQ0nS7
YuiAKAgBu09+lKo4b76c1pxB54SzR7ZiUO8p4qAo0/zLzsiyCQHF4fHrBNnXVtvE6dKuo1SZbS+X
wBl+gFRCMAE511+hdLFh4ypY+ddnAQH4bo5QIzfeRnRM3L3ofpu+td5dNlen63faHB0eojXw5cyk
tldcIgtjoXlE9mGLb6LqSiPXzrLq7it9FBipqGMzgHck89Uu1VoVPptPKUrJBiBj6DtKq+CKrytQ
ufB+LkBTn3o+SrfHDIQjy04pejcr6nTyKVEgMsIryGyT6sjlS//9UmF5uANsipmU7DfH/MYa43jq
kUbiDRy3tYEhP85NvtEVwZh7PtJOiNKX+ndOom72MXBjyPzmAV0d7HQCEu4yq5uSdX1a/FNb/Lvi
HHc3EZGA5MkNS1o7ty3i5bi9TtxeyExW/uGzReG0aZ8iqhJnzunYdGfJrO8zXUNw9VeZwBqJIMU9
c7ZZkbjCBVGrCmz+FVgbVRJgxyn2zooNkJxeCClAR6q2f+4yL8WbDHAjYGdqpSkPrpYEBIpmIXLa
PTv1Hb6BOFXTo2A7kWcYos0xPK80NKirfBfxuyTf1VlCaoAeqoY7z0YcATmkwGiQlwlgafqgsF+Y
TMCcbZM1Dkf7kwXnMDa4Wha2balizrAldc6GsPiAAbj1+mFluWMaPcDd/7j8NWqS6JDDk+RFYgkK
NgbT3Iv6ve74b3Y8ePzOcJWoh7jm3wSk0+TqZSQAv+uDu3oxvMamJP4UvGLtZydWmiTTlAMj0NXR
YWp9VhZL459fM4OrvZBZoNjc0uNILCQQUEl5OE4hPb7IC/NJ+Scu+cS56IrjH6bmh7c/VK9kXo2w
zM+C0KCzxSsnr/IBvJCQ8xgs6U/OGQD4LG86HUHwU92iVq1ZUJiYqKbQgFhiKAxeVlv+D8BW5IED
mifLmLpP/sb4R8vZBk8oWz5tseFmtIZAFlXT6sld8zhASkKPiz7lWX/EEOaeZfQIXu2Sc5R8JBqv
zyBQ/lAA7iGbANGTM+baP9gSJRuEZ+uzB1dsKSwyx0US+yoq9jVIwHn9O5tD2zSj5NjV862SCY83
uJyFZpQTFhpokwrgCPLop/8aEmlmxZCoZzxUnqGodjFjKi+WVR1/1+8bcAZFgSuMEJTdy77trn0r
N/q1EOTPm3nCgFBhWuyhxpgdEVm4l3KD4uiJ9yr+ERzqWlc3dnMt574vgvC7nLyAfoyr/6s7J8VX
apluf7vydKJpG0VJUC5/8BtnxrwjnPwBidSUcMD44w1IDsL46bFUBlYgyCD2iicw6++TIBGQfflx
PUE8Ra7KZyfVjwZLSjJbu7crXyn3+neCudaNkEAJHxm3iIQWhiyuTEGgonUta73v7If26haAWi8U
v1rrfBYMmKJAdaWm+iE1N+A/qsg45MQsPk8xyk6EIxWh/sQD79LLyi59vzw9x4SAHgHbHEWgycGp
ZnR6zl1vj4o25EeJde+X0P/OqF5E4Uw091OuEOmQuAndUL04yUu+w5gbL3btDo79zA2Eo57hcC6b
8xPf7AjLce0RPF9ppQ19PhiPeLfCZzfB8u8pFTzo4YuXotz4G9O6ky6zRZsB3QPVtaEBNeDxHPRc
Zu0SuzCoAk/wfkn3HNXjdb9p9OEdAprq5rrin0/ek6VfdkZbEiXfOFy+9I5QdzfRW/SK7f5Yl+Bd
Oup/+sivVDkcx08j9mLSBmKVXSS0ciYnZiUTvYotzuBqVlaXalRmMTmNKJ8cq522cEwWq1zQXRer
SUmmf9q5dRunPTR46HSDSRBQeD0tDC/+GSDL1DcR76JjgcXMeWrk2402mimC5vBe1tPcGSwzJ/3L
s38ttQkSgculGVsi3kLK9+TbJbIEnaMM3B9pt2IHpDZiOerUiJ0+NT+QGintVCecT9SZIRHzv20w
diXkEKKHGA4XJLOO87Btv+K0kvaX/+VeLZwj7ba10b9Dq+FFzQiRx3SOxlCu+0MAWnzjekImaHVY
xQgWJLk+bDDmwr8Hboec8AQ6fOV2FonQC49G5tD8oLNGv9qOYHCNQ1t1LNY9EzaTwlQqbi/YImQh
FRq7VFNgAGLw4pMlgGwYiSCam8sVbOracj/MoDmYuafAF5JDNx9UBvP2Ushs8HCmZU0+ppF8RAZA
0DRkHodKEbFwaLeiC4PdMAXwFLDwFe9PUpml6qihAmYcU5Hdsy4iTuGJizzMz5bokqVJZpXla8wq
DAbQdJ0WlDwb58d1XQPWIV0nIUTK90K46argPOmEjAR9uzlIMk9BkDEEZIz+zX62u89R+mUXBKuR
fEeYjY4X/7YMK9mU7/DiFgixYPBAHIdULif9bq+vECAGQXrOwXxA7UyiV9iXEyCd91O8pRPoYWby
DGU0AP51Y65WYjrnIkS01VLPcIXs6tcTJNS6TK5yRu5xB+l2m/+SGQGApcbaWNrVKLX3g6lyysk8
seR6hxrFWvteCr/EhpRrea2L5KLfIS11NEeg+cmuTm22oqG0dps6DqlmVicax191VFOVFX2ZEi8l
cpUthkcWrX9POR6qp+FeG67DA52E7aq7qhoE/NHaw8oP3U3kkuRLGWcHYkxW7PKKECCg1mjCwLXY
wRhjHXfRx3xV9aMsGWuuC1USTz4/l0x9cwTCm6dwDTSpThh8oU8VY+MDucVoLMf5sUd80qIlkTzX
I4Z6bVg1FT9eiEP3kDaVeJXRmrBXEM3Rp4UbbU/MOX4qiuuUkRcuwXs8ZgUCPaV5P1Gp0W3kZcqI
DytrlUoDAyWomus/e4qWZ4O9xDulA4SBH8TzxAWry7SBnt4cDhYUfwMfBm4hWILD6j/Jc6RgVgUY
YcvzVMyiD8UV3GkMo+83xF3JM98yuwu3XjdcBszcRuvoyzqWkhHZf062ahAtDM8eIB+16+FLgXvt
U8sXpP7iQsBOgwlDe44AQNl6ajd7qPcQqJSvLJ0GGpc+Lyn5HrqQpgg5HL1PqqXn0COpllPJcCKu
s3fAvBe7WaJswO4qxa6yjdqnxwyz5gYVEH39AP5RMDeeRhL3VMwAVD62Dj2oWlIMQcGe7zvH0CJ5
1yEJGmUJJ3BRvY2NPUv1wAZLNgNsgtj74o8CyotWXFO/VUGrnuqNgbfFkS5cEP6MA+/Pgklq/JGP
N02tKhad+uz6FVOaYWcqfnCXXKEqWZttgdYzfjSqCdXbLbT1ExMbhoIxZtJ9Q35MLMUlHCRLIJJN
3IoZeP/suR1wBnVaOQFcp6hSEQ4dn7RbHKyDAvNRa0dOBBP7TbUclRxJtvMOkP38b87ZD/E1oqfM
rQsKCJLaDpsK2c0VwJ2gr72WaQTJEL75Ws2OqLwHVrzJD6O/fmMtxwgX0zq55Mawqh533t/ml8bX
C+gKcGjlDOXsUoLjFPa8tfqLinNQjwAgRBsVGwC4d3TjCQ0PpxFoplqyc+akqn6UEOUP2e1l22+k
HhubU9xlp6TjIkFdzZwmuXSzYJ9+EjLsMnCoxeJprraFNhlx6ovkZfC9dLezfsv0Bkp1TleGVhD0
k14XrSGQPxbW0bGKG6Ndadk2fs6w+Kr3pNc0t5+FjjgSdQcLVLCFWfVMYa/iAGqBtZW1YBZeALuF
goff3YA8OQ52pdFwHthJyAHo6IhenabTFC51LAv0zyuI+W8oPfl/WTmRPW3vywtOft771oHKcygX
DuRmblMELYCjj6dgsKBhBcejhfvwvzUdmhfiYYr7EtO1D/esAmfWMSftiX7sx+BK9byc7eOhxfCV
opyE1LsiN6Z9FwUCxEAiKHui+LkEvBgcTOIFOQs04Dh+LVkYoJyK1wwUozb0TR0W54oMdz7qed57
g3423A1K03JRZUiJWMndzA5tcki/Xnk+ZmEk5oimBswLMVkvLBfP2zUp6QPrQ6Si2vLTyHGmOavH
hD0cIIMo0mARzyqyxWz06QIdgz7TsxELmsHS1FeJ6V/tZTFKD3/zXV1zX7WqvXCretJB/WAqJnFC
Ppz7it0QxbTeI5bUa9/wmWyB24EXDri++MxV01O2GhZEN0t5YvpLDN0FT7Q6JLq1wQJHxjZKnnZb
RnmjpHuXUYJggxobZ8qT1iVcHzsR0l6aUtwAqPgJgXhMno7OaNldiW8LdnbSw5fB2TjXnY+JClzw
55bKHkCG11cve27sUC/SOXtNtMXPThdVAZxJE1zupxtOmscldsTIBUtpYdUbRr3gjQuj3jvgVnBX
cZuio3I5XiRMNjK1crZDmnuo5lCUTQvdQWsywGW2GwWh68Ay6rkXrJraQB+agkpbf3KUm2KbGS38
u/UcEyztuie5GIAc2fW8c3Ia/8uuS4D3Fi20zNe32HgC8+DIPtZocMfEtn/d379yPy8xFoxcYej7
Eficq1tG8oi8pGuMhK2vrgPw7a2DTBy3o0mLEFxT5Wc0ubC+nmXgHWEzljFcTc1wX+kL8iRjITlJ
x03R/KyeF09FUIRySMgIBni67A/RPiNoDxYPOE+pLHYdRe9QyGP005dJqdnP99d7iKriwwVa8FA7
VLMoVJHG7XhfKaDZ1mms7dXgwVlXOP5Z78P8AsBAZE39XyQCsjSFHOWBR3Sx9931c2Pjxh2FLfjf
sOrG++SSUkq2TsaQgS0onbT9IC4fXwTZqVbQBILjl0WTMvC2UFoW0JP+ppi1eeUcEKHuLWY2kAUg
tnE2poa7xZiPJ4NEq/1i0WOFeoWxRgidr5ddBwkIrS1nWDJjnhnUfbmAGHkWlXoJBcXqdyTlh1rk
MEBHfYj4Y4wOabd8hPfGTgIU+v1/IOCT2O7KHhpBGsh70ySW/uxuUYpmDs+L7mQ/72ZvpnPSLRpV
/s7btX7aeQQKhBzjb+g56J7b2twLJt5O+/5iM6RK7X5ylHPvACLEFUlyHuiAaRjQpVra6amL74uf
VCME6mQliXOb2/GWlTjKJtIQ6BLS/paPrSqjM3vTqDsVerCiRHlbwwSiiMZOUPtt4kd3SmorQrT2
3K5QrJKD12WAtDYvhnQOnyteHqixrcl6RTqRfuW9CNAUWe0FwnzwHX/WDHcO+0rFQH0n4cx4Q7q4
1JNsBA0r6nSoDBULqfKt9Uqw31bD3ZMZK7dLrB0QkjR5ny2QEGiR5vhe/1i5yBxU5ZTsZwBpaH1I
57KXD707Nw5elV5MeXr/8RFkbfj+aaTEJxDiYV7ZLCHCnkoBnmYMpgOYESAiRF7xLmGzQY08oXgu
Ot+0rMwcFKvBt2ToJ2ssrJ0G5swdKHindx3ZPb1LU0BnrZAPCfAgsVAqHDec0K8KpKhFPfs6MpaY
NK5KVZdEeKw7ykNJKVMiXzTH7ygtZL9HHVOD3KFE8FAE4dj36O4WLJDdPiQZ/To5dvumP4vFfAw/
wc20lJc0jUdTj6fHWgoiN/rhXzsn+iVRlf9NG/dfEb8ZEL/rJZwaeo7GnN92ATWuU9w86OHqBb7x
XMbPLxofN8jtocm1lTlYf6+YO0yApztV51mbTJ27F9SYeWFpo6MRy3K6xv3pQ+da9G7gibFBiguW
XcOn32Q/6MAKK8hyZqryYDCxgtfJc+WzbhWopXTv02l3OjWOffZSt/4T34n5KwyKTzdjzyykp+4e
cuy2jSH9WL5L8BZQuS3eI6o0SqHYi+2J7xOKUkZpANO5kKFZZT53nunDWRDFPmKIjhoqRocTO14A
C4EKT+ebErX1dWeEQv5/GR5wWC14PMTSSTE0g01ow3aWz6YEfNPDfTtrHTk265oD52TA9xDOQxrk
uHwYdjS2rwn/1tS/BDhiOoHzd+Rc3DbVTfOwgEUAhA87H8hnKJdVgvzM4lwqO89uLXDWGM5JcUoI
M+f2ZRMuZu8dE1vNhC6BCZ9QI+L66s8WzDaV8mokJUmyPwZWOPXNkELzziBNY0pnXJtYuWDQmFFj
eI5tU3uNv1GzU1g7m7j/mtTY4hevdV7eaSdXzZXPAXlv76CVY64G9ZnmE75wq2CWnWjNXqTmA3h9
gzWu0loru2Dbc6UPHadV1WGJ2ig6MfvJP2OrpxrHhA2T7de9PHUCu1Hw7C8aYEF2WGzQn/gKRVg4
6HiJDTfujmiZWCLy36I8G3rk5M+PpkcB6h3DQMD+yxk9bOQyLMjuJaWh1I3z00SdKp60oTYe377r
7obzWft7jDbcgwgghOLUqkf404BN7UUhy5O8xtsIw4XVv6CknF2gZev1XieeP1cdm3t+m0i/PHLr
N9v558jfQOvZk7OlKHWCdNXKPDyUu+GLKKOVMyb7Ku9UWL3kqvwFeQnFgh1yrXyGHq+/51iG+c5U
+Cqx9HMlDN/owsckcZwyx4vXsVnC3fYDAyb0PaHtTKlTvAeaV2o3K0/aIy8+Gzg1HEo5QalFOPqA
VX9GOMspLpATF9bWsZppJfT4fB+LbG3uMSQdQWt8fgaKH/x/LSGWIgLFQpanRT29B0FTE/siMDJQ
bVInDTzr9R5cis82ryi+Dm6EFSL+x5b921hX5x46a6pCfdV1xfw9s9uoQxZHZYhbGcVyC3qjwCfI
qH3gGoiX2tN5Td8AYhOXbpQbyAvEzP4pFIvOP1lwxzcVgt4m9spsFsc3kNDhKcRcTu918Aqvs9FX
3bgWMJDX2lpwaEyKb8jX6h88TzIkg57C2uMFGLXJ9uOh4tMGFJuWhD74qdzqtyIwIciLTjpogzxB
JwCXm6Q3LI27Okw8t/87lk4hDhZJn4/xqMRzbu8K1T+/EkMiwlGnPypntMnYk5C2cVR0sEP6r68b
RTrr+nmUOVIl48nHA8Xy9fCjfzW/L+BSPsCEBImQIVKrpn04af8yvI+/cpak0ETgmnHDwsLke8gD
iCZPRIkoZHFnhkerr883jN4flS9mPM06JxMZ+O0M3/THWg3O5GaKTPBCcvh86KJuVpae0N5fyGyf
w/Z55o2+ta+77FRLGXLMDPhcHkMxOvwkiFrbBcPTlYHoHd68AkRGRo8283SfFtpKdwUs4ltbimNo
YLvUWzLSTgf23krIotq1Y9wc22Pn36p06KVut8oCs9V52NvcFBp4xVKvxILIpNUlJxIJYgi8BjL4
vhfbv34gG16VdYCpWQpTW7VI+40ACAanfMObAeQ/6jQPS0Y/+hBTaZQD5J1xt/eovGHRPOHh5quh
WEzH33Nhs/jykg09ukLROqpi0WMVYNCx/NStcB+a8NxeDEMW4GieeHw7KH0tHJH/kojQTPFRHs/f
6oJtFcvYB/q0w9Sr4/hzqehy4RBc0kxkz9NJe9galkyzVJvMfo48gFq6ltKfSqRpUh6Tnb24ZKef
+IxCAZDfZG7BnoiLYU9eP+maXKsMqZJlJOIx1jNKAxwxDGKeFSlCuQTv0at3dOJpJTp7q4sYHiVw
3CkIwIH4Ata9BQYizXN8mMzesI+ct7Vvsg1dthqpLGLk5SNomVYCZCNXgsc4UqOmg5nENAGgMLPk
8HSFFb9GASSFgUdFzy1FyFZjE1B8QRZJhPaySoIO8IeK8G/ABlN/k0/9+mGYUJVkxJXoERRfIQ4y
X1ldtdxurqr15PSzcrqwUAWx0py6UpzZRDNu7U64JeoXWmMhISfniL9TLgWGUEs36ShA1SY1+d9f
EjFBl/fzKt7+opMVfEGFOFt1YM/grz3peEE7XKUYgQN81hJZvK9DLqiZKiJexEMVzyzNpbDw2J2/
Q67O9ksQN/sncT6NTj8Gu0CZzKwfjzKeZYAt2MFiNdqUzAhw+hnfHpdtpPgfkzbBrisfLfbzwjGT
mtTCCysV3MpXQSx+7J+dvC/eqYR0rMJJAqtfS8UiHZwp9K0ZnGe6wXG8INNcuIJVhs1t7YwtL7/E
qgTXYskuHC7wMm4zLzc5d6GFWGfWr8/ufRMyY1iFVE0IMUJ2NtQIQtB7RKL37YihZeEQ4BJPdQ7y
410sxX8Dg8dLGWbkzNd/2rfdhAzjiSnxahlc9vR9WcVp/uBbzprys/AF762xTRNHgbGJ+kY2/Uox
PWlcEuyrPeHXKHiKPxSIBGyOalZ/WONSgJVemCf5tS43CZmiNiwPiL3X1Jk99NagV3YIWtUOxLYC
nOhGkD5vcyPikuJLA5sCnKVjFA/jtUh8PZizB3dRYXa4KEgSH5Jx4KT9oLo/Ixtr9FfTVLrEgYJQ
uZj1BnpALzYlqun81Pk9pD7UD/HIAbqB5hza4nch5RdMF46UOYfoNG5OhQLkd+tAgtJ7hHEUyB2+
KRn14cgUoRH/ZNJ+b55RhjhHTcZztSVQmzciAt8px61GZt99bYYMn6EVlVuoI9AUOAqsJ8YwSWe2
kGYHzGlxhBudcdtlrUqzWSvj6wfRK7LfSlyF9wApFp3CLMNZzEedF9GHXjS0Gxe75r02tHqmzi4V
O8bJYZEC/wVh2wexVruPeFdtEChcCPeZS3IrHzlvPyMh4+gqEfrArCdE8hC39Lc59S8JdeNM+uaG
200p1ME2NVndGLPrpARH5GTZW4qJivqrNO20ppv+n63Rizt9OaT6dd4zWud1a0BujyQWGOnFLmHH
9xsfXEmv2LBNkFRBMH2iRloYq5i4yeKrV8JXG8bTyoocH/CHGx7+JvRS3+022jf9nJjYOYkwLNsF
laWpgWbgvf19g4uWZxZXPAYPok+k9G/qUWL1F5AExQeZh/5neaPENF85xAjJbzEYm5MzxmjT9DhY
73nRaisyml7QFVge94tOJChmnlT8cUOkxvJgZTUrXJ144NR/gTufnt7AS/8EZBICgQdTOEeC46Zl
bpkwRWD2PhabTr/J+t+hP5j4jn0atBbKtQTR6KZyLBrdMtOb+iZCvy2d16PaAU6TEW+MsfdjGw6s
TRM6MQuiQ7kW/wv1U5BAlmk9bKBBhkwO4EtF4rfKHp2bIQTP8Ke6LrBgv7M84mbiIkV5Zg62dAg8
3NpZnBp0Xf+jBzT+m5CnY1v06Ma3EdCbNdpgpVeKgDVu3tR7rFHzaaPxbaRLqZdbgT+YaJbpFtJJ
cTwM6N/JS35EJ8tVw6+yMJzTYanO+PYiktossmywcC5z0dRX6DSvFBzDWK9z612SxzVfL2ErwpxE
wlU111T+YS6YRObstgKvlqYeSCacN7/PCmLJHDBBW3dvr3R9wDzYUOqN+2yvdNctGlSCJ39KchVV
ezg4Zia+OeiBgQpWIblXN7Zdb3IMiDLIH94SpomxYYkFZ9MqCvs3j9Io/SsU51QYl407zur13/D+
6g7gz9gT8//OA7cJW+1KfU+gt2ln6mJ+i6IE6alvjUS5c9r4kHvKSN2Jjv/9Sq+80mmg+Kd1fcrh
2tyCbWb3I+r7EPUZXaL1As8gMwEOMblrqg8m7edkKi6f6ARF9Rtr0sKG9ii428RkjsMnxIXUDDh/
DiEPcseJIlsjdngMrJk+4xxrfE9dTFu7PN28X5PV1WuP2VQLmXq8AAYQyQwbsIrKMgGdo00B7cup
ERXsO61/sSPfwo1X5GqUMs1vEfsasLbK3tpGW06u2XsUTNBdZKtO+8xIKQHjsljmsNvt7IKDReZT
MrGcdr9wHiU/CaDDBy/uWaHo3SZkp+/z/4hmtVNuDYInLpdTxMW5pubPuBDHcxNyaKCmQ26WurLv
GP/IZ78nxTIw3mEDygf7xikcVK4VdGJCVrHcaK5vR6J0gcdKzgeJWt2i1bbyEf9kMu6km3OMXEPK
KsKvCMl8mapW9wxmcmcDocZpKPgjntXMZQhtbnR4hfCsw7vmJ5R9Nh7zbMOv6MNRD5EF57JbMBSQ
Wt+dF5PtusF1VYCnnryd5KWuM5RQ/aV3jHqqB4YJ78yDq5LktN3PiNoDEIJA96nROPQ0Pc+xksDS
JcK9+ZH7ckmb8VOpN1dx3C04dd2Wq0Eq7LLIltpfPS67/fm8iknUuL5OqE8SCKRy6J9gVkWQvlpr
QmIXxV7bdyMraueTES6C4KzEz5HywTXsG8BOOqiv3ec6eEigE+PQ3tal4ZobnQIwM72dngcnyLzp
ZVTFqFXUUid7r8QK8VnIZqQYWZu0UB5zcexsm27+GYmnustlt5kJNBpKBCkA3u90ZWx9EjQ6uZEF
Eo9F5MGmD5G7cJ8rWgtA75Js1Y0aIwFR7FGkJUuDwpQA4MtSI+32f+fhroqFVER1IBiyJVBxyyzJ
Sic2EGsuJuUOR/hKvSiNQAoUGOUY4wrwozhkT9enGbLVqa+0uBRKWbE6AfMMNqamzyDzRmwEwhqt
EGhvyxMQq41eDReMeZ3bX/k/gxz1JL67AbtdpKoj26eOb3cFOsUQdLCZuSZ+tZVGZ5923n174YGC
q72EYwX6NJ6jiHLvZToMLHKQBZD4rOGCciCG5etf9SLKYf/LunsPnwo7epaGgOJjeWyUH5OGrRyx
zH5rB+cAHO7x1/KCpIgsN4TFG76hrk4BRPW679t0maUZ2bBhlDlAIJWiY8w36PFIz+c1JPmODsic
mq5UYu3e/t7Vw/Z2Xhq1h8Vju44lmvXxfWafzrL1a2Mxgvrx9REH7sVQDMEK0afW5kcUWxL22SHz
Z4hDbB20p5q31Y1psL62w5heBZKMuK34FSKGH5SdjBhl5WlSoqx22R+UhINDSuJ38mr7C6HZFJki
ZK5mx0fRL1+HHPENOpoyq8KNH3O43jDoGqKwYHdoguQKyNdtbbKXQdhVXa202mV4HIBEag+NWcJ4
hwqdMxsR23ZK9HifCSKVEWLsgtIZES2y6UJGFAXlfSQW5Dlg/5xrufGgB3bRlp59rtr3LHvngq67
oNtNZU/ZhnlZXh9QR8Si8khmxXD/L+L2lDrG5WsSSHSed9yFVZ1y2Ak2Vm60g77DziGs4U8BCluv
zi/C//kNl/sULL0Z1U+EQiUtDUNJfbT4vV3O1mYmHj0CySjBvqo030I3rGvi2rkD82OwJ034vvoI
aP+MHpdcXUIXj+RejRZp1AR0ZLaaomfyw8QtaY2QvCEvWNFPCbmt7pE3rb2Fs4/B/jMjGDfVSks4
+LakuIg9Fb0inMnC9C3jylmnHY3HoinwZXWTMMEuDsqF0YnBm/zumQ/DgDOyiCb9KJXckZ7sV/Vu
BiA7O2Zq8I92MxgChOWaYKtUmxJyXhHqg9yj8ds/BvX4Yx5Z57xAUlYv1fR4ntXkmaUFRjmh8thF
aCVR3QNWhzN7HOdWnZpSstMVtNhJNBjmkIepn2/mQVcnfnWL3juD9jkkCJQTKCtP9IPxWnwT1AfP
P1QvMViTVyyaBWiGb56PCMhTov5uRtrdfCWMZVVqEbiH9r8CPsQntOvRqbZUQGYZfYIXlbzMyEOx
VAxu+n9bakI5TjealChM1gUm41vGAWlCPgQLibtVhomTsUPHl+d9XM7wqtDyVKZWfxZPcQ5d2izL
r7xcxqe4BvSy13v7myPkNLf5aDmIB6fIE3j6HaUCxvDidO61CnlLLajNWmISUHNaownx6Y0zGAR2
BwFWhlv3V1i9crCq+jvD6r81FXKbnozB29NwvzqTZ1jg+FHQQu2cWR3XyNul9yeJova0KxbZ87ry
KJ9uLHGfewbCPQ1w0gjBa8KuD0nNsmBKW5vcWlG3NG7NdJag4ZojIiliVVnVMvDD+ERfavr8YokT
MhyOesWIT200vSj+AEP3WYtkKJlgejRu1S0t/XRi0ILJ1TzRYNjPn4Qf65xgqDGeGf4yDT+VB+g+
HOunfQyRTE8okPV4trFkIa9oq9YtricT52RPHHJ+FFszh5Fibpf+al7xfWSppj1BUHXkt2HaCA3i
Y/++q4msu6R4kQK2X6t1mRZtTK5MjyXmghCBFmH9cbiRuHfQF9+ZLnRjQ+6ccY42cRpnXpm25ndQ
rF2UQuTHy5VF6J9cWzxeQ4Vq7JCZ25B7j4AQTKhk28SWVMmRVWFMEKWJ0Gql9lcX52Qp8j+n/x/c
sBJq9giIpGLEMMjEeGuFX2qNPYV2hNyPiRzBATmDhEYryMsMFXK4jruNTSvenZLTxPwpDkCfSToR
Vt7l78rxDcjOMP57Zx4RDBl8BZzhAJ7A4hzk6I6upRj19r7Dh2rP4IxQiEv8lidVCtm48nU59hmy
A+twVT/D4odECjDa8BGEYxScQHi61w5kByt0pRlQCMa9uViZQ+l4044k9fISYesFmpmSyVZITDQf
bKcxAgOk0OpTnAx2iSwpVRdQwartLqzMztsmPsLtCd2uRlAMz3E/YlFI9o/b5opXm6wpc4i/6ZkI
2unvT0o6bqGZ8QfxXHT/7/cAkIFCtZKSTf3FfTx/IbePZoxyvgAIZd+XLQ7YZpxi5PIKk1V5re56
dzZbiOHSJQMEQSvOKBjKv48sGi16YfGdWH/HWVEMyy9yNKknza0dgGhXb5WI7ilJd2u7bIZoJ42r
ONttFQjlz/snqlu0+9JzkmICWj+2jCb8aThK4uNbJApggD4ZlMEIucR64wBKwOCLfW5sQ8FBsBXR
eYXSjVOTcnc/BqfRJIdyNE/HnZslDalovXS2pE0hAn01vL4uBmZXbqILb6p0hpO8TQIxiyUkzgyD
ShsbykSeHYUY2DnmIi055jzWy4rVLI+mHjuZ+0DGgt/tLUtdhDu7AjkfA5gK/U+xUv1hBfpM4w0d
lGc9pXSqaiLtBLd8pRVYEUhrEv5sg6IvDYXhyeh2hAqNyDKs6CXsn228Q2Jo8+4Oz8cS7hEOPoZ5
awyVq4XO/mEKcmgKUVEeEkpmPHsIOJcsG1FfWhTAGrNdEQOYALih0ycVW/yDprprA5yoF9EK2/J2
c/MD0Dh1rE7k2BCAJd/d53p397ibiHUxVk8X7w3LFA0q2ySbmYmQBl7CT9Yc7mfLhy80PgxbsYYO
JCy23xi4shUO+fsNe2pjDLFwKBlLa9fIfFLV9I8aQFZANEGMNtxnHt0wMCfKvlBXbDlRaufNjJHf
gVRFWoadziIszumYXGPAZiDG7ZfsAwP87uCQ3AhXV+my2mgGazCSKyeUASLH3gjDhQqpcabtGvEn
p4sMEEpLB01yHamLBDZCXwByDXhKQ5jwzXkGpP7XAwVwNR6UOmGMMXJPOdjUXxczqr2hUgqlkO7r
5a1Mo7EXiSneRAFP1UPIad3ILV9GszsKmMOopfF+dBfLFWJ7cHvxIt71moG+LVmhQ676v0/+Vtfy
kMPz2bsZv9EBwfZkezgcVt2fzXYfIAgsO13VYcVX1XenEPMU3A5p1poJUECzVhNdJUDF6q+FBaHV
OFgopWOzM2SThNp7BnbkgTCXw9s0Um/9B1MoKLuHv5IWuejjMcNMnpxJlCKZwqDfvVvYdiGyckW5
ldQueiDmB9Z7rb4jrqFOondbDeyHON+tsW/QqXhjJK0G61ggyd/6rx2Gpt3twHAHd4vg0ZQnNjbV
n58sY4F3Evrpjzm3ANfDrjLxWPbseP0N0UqISTRrWfhw6iLEDIbLifcIqYAM745sN1GXl7nGvi3U
Wul91EYt2zVzm1lpTJ/le+JCggCQOhrp+buo8Edd94fS1LPy+cmVNTb/eY8OjyAcjd93m55zRyzR
ofsni/n7VFKiyhaoqo5tgmIfzv8bDzPJYEpyOpfB0VjaX53X3KVrQP5Y3UUkkX3LUPpOaBGPWwjV
NEq7u3uSueAUzC6rCzUwzIMpfpu7/vkUV7NBhYq2T/Q0612GDj4qz1k0o1F4WWZN7gKH/iwA5vmX
Kv4P7tp5YHMbfcRud9KrB9rzO2iQeE+55EosSc3DO0R3YpfjFRPejkThovSmaeqFtNCGAHYRbIzi
DbwBEqQg2dXh7b1YL2SPlNvEhtG78f8f1ezm2cPhUa2m71CqpsQxeQ+FqiBnKe/ASdHOZN4lNCY0
Linh+clHCFii9vcFV1rc6Yzf9bRCev3CWLdaP9MgTtRQJMkBKpRY7SPx1bj75bhSObLQ0keWoUcK
wrfBuJaKLJq4YdRustBxWd38xdh6DjtaaU+MDamr+IJXlXq1i3bvVfMCt+YurFbbGq1INi1/v9SW
mYeGmV6z9bhSISNbvUevygjl/x+7V4gBzS4cxDZwx7or5qQLbFWwZeGuvR4vgSceGoGe0fjRe2Zl
zsDLlm4qxKocf2dqNm65A4R27yPqIQBr73YNhotPLTfDMgzdgvn+ulkKbZ3W/VIdyVRuVBXeBCYV
pxqtpsv3pHXapRZqhFA1Qsm4oHIQsWSD8HSdKiPWg5t6Vv60Q/ou3pvcvmkxEr6uV4BmPkeqflba
63CkCGCFdtJA13l3s4lv9OrCqyQsRBQMp1nLc0VAMLn8zCo3AqXlSnHLX/gyQqSZr4cZCd9IziHT
itpIJdo6VV8rJB2lDgGe3rta0SzIWWf4Ye92UYx1S7NkXhQ1OF3H9PFi0jOm8Jz3SFiP4vod55/z
QjZKE45epwnCbuB6NpYfyJEPiaxz0o4hrPBkwEoyX792CUEYzvTDxD7cCimadusgeBG2iDpi7T8w
3yYMFrOC3lpVH1VFXRYf7SFlJRr8HDv/WSMd10xS6YZ2LEvvDGnAfvW+fNptJBCML+qoZ3Qgm3MJ
/5h5tYXNub9IxOzJIT9rR2GV8J56kA/RhGOlE+2r0eli3Ud2C5Kt2i6cyDBriIZs1QQ0PeKftrsx
AS3qhwHg1Oz0Vhl1R20NmMjrWgIcnmgLJ2qLopADbuSVpQnGLQ/E1FStiGv4BT2Ad88OTmCqRJkB
jWgvlfK1xspx+obYcrNR32I6tRm/jZH7tHn5Zz3c45z5QNIBBCZrJ2J3aKXBPT94kqiInwdBN42c
sVi9RhPO6dlFl3CkI6RcZLvM6zWLmtonYD3mthDXtuHbm+kWoci6acbQdAlREhble3N0MPqjNUNF
a6iRy/AStHI1ysLU5DRhuqphOKWs1K58Tiv6Uw7v4sjU7RywV/o85of9K9oATRKt6OXqhow+HRrx
ctD9DonSYnQI1F2dDkgPR0mHtFs9RcOvxe+IN/Ue12fA+l4+z9GaC35VojZqHGLhQ7oPr56ifTIo
aImi4HZqo8WEK+aXw+h/X252m1ocW2c+93snsH2b1gOSecU6TZkbMuYt1WNwiw398wXTngI2a85j
LjZ2ez6TtfTifpKoGcYsqNFq9je64PXep2lY2+eVKi5Mn1vKCo1jeYaGP1haXczhOAV9XhjG3aIF
wEa9in8eQJKo/FJRjBSue4Rrh+pHL+dpwJ15ZtXEgUUKQkzkzOVZxJ5NmlIJNuQN/lA5MjqmxREJ
0SR5TgdZ5rV8jp9Vb/5/ar2HWYxQeVXvFJ0r4I5Te+V8tISGnWcLtX35JSB7wn2b9akFxylb8m0S
33vHtTK6H7qKB06PR/yw80VfTIGXmDe2AQIHLzITgv/hS9Sc6DI9ugTpuAKvjCJBFa+HkKf9+48L
zNpPU4RK/gGfKBUzRuqWVaCARBTLn/PmqS4F4YdmZK35W9A7brPRurtjfOCaoy6F7HlZGjxd0glz
41xDVgdq8uZ7PwOV4DMPuzIYqYi4fE+65VhIJAT0oeIorHrUzw8ZmoK5J3XlaokCzg0RsoFY5AfD
LhWH0BkYYtuXehcuG6mv/7CTiafQ0+09DA3d5h3wy69VivmvsTYDf6ZQv3VZ6w4dokPOg5IM0ovH
zmX1ZwOpwRGRgXMymoiHHFRg4r2gf7LZPsydUcPk046yx5ZTzGpqbm3AUeSke0HeZHRvqei1bQc6
0vm6F14GFM6+opJiAhua7IPQ2aMYWG0NxzKIT/oXQaqrWWfPnwFgOFfXqc2spP1fJk+wLcgKpku8
yliRnAzPymYseIrrkeum1YOJ2lklwOUAFieGMe/KpVqt6Zqm3flNi7uWe8uNlHMQSXjq3NGH2w2Z
5o/CWXu3WfitF7tsy1kOEQZZw0eGl6h1bwGKh465I5WPU2ndDHe7SUOYqIi6Cyyre8NucUviWX8y
f3Bn6XamCmqBnJFb7r12l5qm0hdyIAj5qUQCuw/9SxvvQdO3xFTo2JYj7sHG3GiKTrbFBDQGR9P3
uAc7ryhCEUaA3blozlZ8PyDEGV+9inIXgJiVvdQzvOKXPYmGIGFM/KCiRC8NYPcaLF3tKVt710Px
6JAGDUFNKuyy7i3blI72qEXuc+EsPhWu90CbSe9NC3K7pPYgZ/u9BJYYWAFgIdZ73gtwXRTJpZq4
3vwpe6CQPC9hx70yF7jkW3Mv7eL93zaHOMqdk3p26yEGDZUK7PWmuOzQEgliPEj7CPtWsC9rVZpy
U2wp43apDKSGTl7V0qhIAtBt3dkNRDiGKfQdzZ+siVODDMRrF9HUKKsjOMeAhf3NoKPk+Oa1LF2Y
41DbCAh36WfhP5MRLOMEuYsfo2lI/f6PG29OSLmdV4FTFD1+P9pruRPbaJ3Q8FGoCRva6F8YxwmB
jgikT/WBw8h3tnxsE4n24Rayx7rVLINAOzMpsGy1+EuX2s6KYz8J2AR9902P7P4sEbe1d3/+rxXk
aALLBv3vtMwwd3IefXgaU3lcnRDITQIHjjOJM+0RFZrkxEA2uJeyuBzidRpahjhO4LLjnx53fR/K
fhJvFzWhIlyPpW5aHKqE3eUeX+teBpYR1AO5nOiZjHXPZ85zXCKkNDSeAx4h7ZbDXNvxj70S3cPU
fl7cpPj1wSxZoXJPwIz+hyUiyGTAx9Z4bvuRJmg+5KuocAuP659hY+gOjZvL1aUkkribaR2gke0q
Zm34ho0duD+J+yl/L1webJvxfhGYjvnR8Nlr2chElxpt34U+uEbq2BagyNd56zHPMDVhVzTR+N5g
ZLA/6za/Hh1xxfq+ASR/dcWshawHff7DzMnYlpe/KfITRHZ1Me4L6Br30hXd7td2dz3KgtWp2nYk
407/QXpJKpKnzcDZEg7Ep8MUFrOhb6pn/R41rDNr1yprNRxiZNgd2RPh6RQHPyLm48gT1rHXUiPs
w023i/kCuZ6I+UndP/no9Fjc1JnNiU1ywBYw1CmHPMDiVk/fGSborfZH8MMEzd/pjGuBNynqa1sV
MKgil72hBgH4UR4cwLkewNw28GCuzipj7F7LkA1JuaA/CwAhVoYjEuyOxV3luLiKcEnIIde2OK+D
L9ddzvVQ1tBXY11NhTkRG3IzGI6iB0Ji6imY6SBgv8/temSD8AuVwpfZ8CGzXk/VrN/EIoUHR1o0
lpYMcML8GRUsYbQMc8tvbAEVKFO3G4sVluJuI//GrCWZuT5JIN9rg3beS0U/6Uh/FnpnIALCiCpT
/qtPUL1+lxsBVHgBwqCQrEW5TpZl/RAA9CoGHSPvwjhqM1Ce0prn6negFWOoSWLYAvHIcjupBi4R
dKAsNQJqf6Um+lsvWazlVcXVpqWx8SP9UB6yyS2vAFsoOPMnNQIK9JGg/CrTlgaLUl6Aylk+jLW5
50tTauciOMnl+158pNY/9I7Z/Jx+R3b2qWwdfZ2pserQPwzV9JaRhzn7qMuDoZdfATq8Rl1mpxYB
YhsYviTMdXQyOPHekzssc7Zf7JIerBFAnH7271+LV3GpSDM6oIO6ifH69o+v0c3GSdXsCnzrqE+h
XR45Q2xEkHlf6ycCv04IlbVnWW0vP3hC2x7UsReLsJmN9bqGFWg195PDK2PA3kFGUNmcgnaZWCdY
aVLVI/O/Fdt64E2liDpJk7+WOOJKen2ZyQrRWBnqcN8ooWlTGVCYATE1rUDqZ0wuTVvvqQ+Lavdp
pwh6V3FkJhpgTRTKImHSl4iQJCjgdJ+OYlSG/CgEOpkTcgcL2yipgr4HUeqmsgBn8zX6Xf4rjF5P
S2v+dBTTjRHoXAnFFntbqbInOy36RwfKjnI9rRI4Q5e1dh2bH2j+4ZuM9E3kN+fg6yRPTWTZa/jq
miBc/5RkqnyL6qPAAHLsNcPVZ2gJlJd54gLj1D1h7jhCdJqCPHl2ZIi0Fy7M1252P/DB+8v3LCRp
BRCe8g97fqTfPcSqlTmJ6drwvdqI07igOC7LZQhAOm6C4Gan/GQQ5SQldvlpRGUrEJN679gYLpQ7
V9McIkP0vklWiCPoB+RzuJKjjbVVp7Fl46Nn7GAQ+TnXGBH2IT1aRQ1PK6IRVDCRUfK6wd+5ax5K
Ba7Ga9eXi9+ewBIKJjn1u9kEfPKEmze49fNEvLNZSLg2tiT11XzA8emnGlGCS0erjp5ojcDDLDLV
bGKI3lxd1QjvvTMa3gaapoA/dRfTvi/8pd53wSTDIDoudENAx+UmIxoD6szU61SZfn5P6fl2nc/h
rdAzb68RLwhgtZB5SK+8JfVTxsupPUq/+trHiwYia1JtxIr3GBXm4dlJ6Au5qXpH/BgCUZbdNktH
T5tDNnsfh/9ym3/hu3F2b8miEGTZ237iRTIr1/z8UKwD7RTnlX4EGJFBILxmDqDFQSIBBG5VonpO
PbN/VtcrJTeJ5UwMT48DlcXEH9BVndQnnyUSAkKaHSvl7Q5AVVEjQMAQQsyy6gYvVRMq6YW4q5gi
IeoDSdkJzaFlBJ8qWTkPXFNASDCBvMV0W/ilqxj9n+gS9YRO/skXO/9dtrItGKJbXPFZOISD5V3h
Rpfsm/av6HE4rXxZXLrSz4HxPXOWajsoYAPEMYyJPNIZr69URNemVCXpLxunyx3BN0RATWfcJYDs
hdHuMOSoRHIleFgaaCRnRu59dB1C9jN+XHyLRw/a8g6I8XGC4HNoAIwTjMXyCWeFsUqpETvyL7eX
P0YBuGcRF9uTx6Err7mOGsqjdW+3Jvj3TZfEuLFQliZflTFF/Syj7lDvDpP1APHYlP3APZpoQD0a
PRGA7ltGHcnjychxG0dKrlkzlwTAeVM2aJ0Ym3To9QP8qzVJPagHDgR0PnQ7z3QcP7uTRldEpwgF
IzjDgfRS66NwiVOvs9QjgW6CjN0qhEr2jy6aOH370Nsr9gogO8lj6DSTgkuSgWdg2tLFrkOJzGR4
+okpCAqSaNA99zZjrelQtCG+HvZ5wMnCncZpmFb/VdZ3cEOzM+Er86hK8lh7Wjsvwj3Q5KELDp0/
ctoWBQD2KpfIgNtL7J/efQbzGO7AgIAXxDRU6fCb/LZk4fXYUKeMUM9i1YgVTN0kHv9R6BZeJ9I/
zu6MI9fsY/NJn223q4ZPLOUG4BRCP4ojDdKWO7kdhSTK9rXj2G/N44CIU3xzBSkD463UeR9Cwang
TPvqR2rVbTeYqIRrkvKNxrfkjDwrLwnP0wLjBXmMNo/ydF+gTHzkoaIYuWBv6Vqr+YCopRw3WJBi
mJFc/39aanxNefkolWCTZBzCj6sVrVUPr3EbnqLvFxg5vMSHZj6yjWO5p94njCpTF8pAc56lUnd7
WLRfWRUHwqgf20bpoxQJ1vqX8Knre+xIrNtrrz4EmrgXfFpkpw3fZoJa6bK8Xp1w0SaQY3sxJtUY
s0pB3sRkAkHQIR9n3CWu0Nb+Nkbp+3jTFriutoLOYRcbHRX6wvAm1kmO5XtsbGM1jckeRFgIKWed
CpKkYeoaAbFbBaDlzlYLUViE6cdwXknErPqwm0QjKvV8vwOJYYgrP1j/AlFtJdObS/Q7lgv0je/m
g9FXl5uO15f/K2+fkzg674nlkafpe5AcdS2PnVNr+6/DdT7hY2waoQmHp/Y+9U8RrL8bLeCZLzVM
f7ELSoVTilDmmkmG8JWPsEo/nge0M/dIRsQcil5BrKKPZJLpGcD9RFTTM2TXIcMib+DfGQKRRZA/
oulAtH3YBAMl9WFE00fLpKqlryrjxvSgTg1GZzXNleakXJuYwpEoE0mCM8j+0uR6vLYmBsDRwTQl
kRhy/nQ0qtlI+/btLaXBLpI6SR+HUO/SNZ6/U9kTO/EA7GcyhBNb4uyNnvHCL/7VKxcQHAmapKSR
dA8u8bjYr3AA/2Ir8rcltfMlOtibqfY0ph1RA1X3fGTUBsT52Y+VtnmLTz7JQ7wI71Y96FBEbR0L
Mbvm1AI2voAO00mHHlL1ZEJ11AIa9VBIhXoiJuLGB7MOHIgwup6NIjIMQXDVTkUCgC1FyWgrIBmB
xAQr5crwF+E0kFueOxyQs+NyiucBqyubp6OVyvALktVVMFJ4UD01/rkq37e6M800ZVrimbp62hB3
ixoN5RxhbDa1pfVxkkoMtPoHU/IYS5vEf6iU5+xQ36BB5vqxXfSeJmCJ2GJ23MUc/Ej8K9ymZSK4
h67O9U3Qo8kY/XDNMIKpKU+wWsSsSDs20T/cthAJWRTHye325zxR14ZmPRU4hpBMcy13xRPSDqUz
J3K4R4akMinKdJU7QJfuLZli1uMGjvsRFMMgfelPlm5dA9keqdZ5M50eRDqXqrUriAoeJ1DoAgsN
CBGCygcZ3Hjnjn2Oix1wLnv4OVilAstmMZL+/I0Eho5Cd5p1vYA3RpMy8ELLE4q0Gxhmn8LHZB5V
wcchrEi2wYxbYBot3uZBTEAU/AIwt+tq5X4IeBdE8UgMkXJpEYr8Neeqs7kUoO0JmmFs9GOjhMZp
IYvxsqTaN+ns/lx5Ifz/2Y1oawUQ4Avu6MQ1JwP44IMouoHrLUd9iSMKNemqPlDwyscrCC9e9YCr
xiHWipXJmAwPSl6x2EVi6q+B3dk4pRmTUnApOIchhQTmhLpUxC1Zp4JOY4v8E62nzWSWNpw+gZj/
c3vSJbuU8qYd+OmBEmCwTqtV3+VhXV9OtNbaEw7B5y+PbHMr8xVxPXwqJ/WoT35Vhn1iuYCsEjRz
KFBLuRigFAJLSCy9dhHklNDEH8NtMYdKLCe2BPEls0Z6nUjrwYMFQlsnDV89H0Uq6vhfx6+lpNjW
AXyymOf4HUtQHHTeaOG8ifK84iGNmspRX6BbaMlGM02JGiZQeqNayP3cNZSqVgbTmBMYHnje8dK3
O32MJLPEWtWjh4Rsp561xG6ooa/+nTQBKI8Y2ilkmPbA+REWhO3Z02ScKB4ROpcTJsEhSwDs5o1K
kbwMumEApXTGQ8vJPeadQUglJ4SzYUPoeefewD2dk3eB0sZdQ/dA49MHjyxj79QkKOt/a4Fe7X1B
AM8ABKYUXOw1MFxRzPnsE3JVyRy13V/t6io/f+TR7Fiw/d6Jqz6v+ImtzlofRmkJBaqTQRJAblPO
Rejk09AjmoWDnbvEWARtOjsAEEW6fz0l+bK/DeLqqErsP/2Zu9v837vAPUsGMdhaoHgsKOv9c7Fm
KT78fKdMd2J5QxoBF3lfU/QFpk8BlLiCMvgknrl9Dp6gapVnp8sRQhiL/p0/ORTLe69QfTJobUPE
h28Punw6rb8FSwe9JWXrFs521CmDz/0XdIr/VnLKTAjgDqtH5sqZfaTCJlG/XnpP+Eqf08NFlvqt
vkj6cWJ3U+FPvjpQ6rUqNN0axxDpnAcsEKSANjB4I7hy+aq3Ap58goMK8sVv7lLkZGdZ2ckBs6+2
CUNwkQ82ckN55MaaLALKeslnVd5XqBhjeEHe90mfn8qRoT0ITNxlsgJ6np0Z05vsMsedlW3yONBz
j1VUhNQFZMR96vXREWBajDkzIYNY4gge6PrFPxXpnDI1pUAYQEWBnQXG9OWDLDEsfmSmYj2ksaQi
UPvCHUhyVWb59vjxz7yHBr47sNUM5reNw+/6xdv4CwA/p/rhsrwTg2T7TZkPp1rqEgLbPibmNOc7
wovThXDmrtlVKT4T4Iv34Y0KZl4Mv+bMoZDTkDSDbbVrEjjfo6vs1fPxCU4mHHPaql9cql9h0xEn
0hHzj/LXW0GZHsb6rzoTyi9RcxeMviheRV5uptI/gXMcEma4dkvNFARbEVOqq+S9SvlQcwFejHS1
TBdtAVTLVX1HcSy03Ev3RGsKc27y10ePkXMXyIp6c4RfF3Hbc2oLzYg4OHfNCra5huEuhrnDFMpn
BjTSPTGmpfFXyQ8a3dfxI9ViL0fQkfJxp9iLa9Vmo53ad3WbSPbuDBZ0oiXyoPamqY1gfay4NZ3A
SnSIXP+uMNM/rjf436NZVi1DneEe0Y+0Jy3p1rSyBOfHNXPY9B9xwdJ88oy45DJq85OqN3j5y2Cn
Up9lo9NT+HduQyE7z5DQcEjzkXInKw69oL/XHipQOgNzBp/ZKX90Jlix7ODtkSK0Uco5L8LYMhaO
QpyxTFU06VAuOU0vx8qUgJ8XTfnemQkdVFPPtFb1kp2Hxdaqzc52QCeH8Be+tUtVYhgd4k9/sClh
zrGHqmKKrQBde/JQDWZrUUzxiu0RBneudbRYyko+9Izi0BE9aUErSOUpCTMab0lrAWGjXU9ClS1X
mQOQLDkzPK3+QzCXrlnW4bWLqaKKwZINdcAddncp7O8o8UatCMVNYXzq7ktdVuqN4HT/UmNk9jOX
JNTCIgmpprg3kxIt90FLV9+6fWlSNaEDoV934vsVhLtAiiRlMXVrfpLLwpECr6Eq0x0UM6HmI7R+
cPvlFz1MTuUgg5C3/ePBesWlKaAqo5tU/aAYlwJlR1Vl73JgDL/Rb/byIG5IkXzOnJTLmJLPKzph
JURsYohV+ZZ6RBQ0e6bNOjooEWe+0o1i8VZCGtJX2v3xpeZE189lS0UnMjkHagrKUM/PP/R6UbVz
Of0w6t8l0+yVl+9x01fVsjmhQsCyE5s830C8YrS1oGAR2ZB9KzaJv7sSCnW5+C75a2MzLdnVA/Zi
9Fqda1IPZSPPeMLtMO19hZyMTwu/4zeyWd4MR5agMzGseb6/8drlIzKwUbjViY0xg05+tDeewUAw
LylsffWMrh++RUfz56UU/8GyoOog6ad/mqeQL+7qL4SgxHuwQqployM5CBcAImnmSic+AyCXL2y5
rDOX8tYrWbzp6H0VTbWt/4rrKSyDzQdnIqVniIFyzbSo0Vd2GWeo9ywFFhRQnsWiddZzhyYZqJIy
wMpyRdLo9fJH9eRHES0qeQHbb4FhiRgWZJSDh+Imjair5cBdXHrK0CjoVHCZk4AiAGAaoxt40OD1
LcEZpOe+HO0zbbEk63RChJp0Wu69Xmw8YMC0XfPSEoHmdrFRHGYOPGB/5SV5ch4eOe+LXjULw2Vi
rzhDMAY7YM85u1RFXzcRGD5TdMolGxBbTo2SBZsS5oNbWZYm1dFvWeitoXyTPFfHsB6NzylEXMo/
Ac+trQ5ZboN1HdVXtiGjNrafNMAa0Hbe6ApoO1CirlHufsiNxBEfYQRuMubiwfuSBvPVlnFygl/J
jrEpT0DFLA1iHPjgdYkqYB09OmyGTLkmra+0orBxr0LkhG95Snv0g8mHfzcuzjCAoJd34XpjrYz8
BlzaMUGzc8XmlR3yoyqA65L5Rq45pn1OXny3AySFOROuDOzAJ9FiXFrwxDUI7lJSWIeUaYuAmHwj
EiVcCB2mv2gkNaiEg6cILehlhi9hc33uoGd99OHP73xP9OFFSZ2HAk9UtBhC62uz+EwAKYfe7S3Q
7cDcsJUEZMluko87X3HIWZP0uK7lQhyRl/zliaw7crNS9KUf2mAMFQgI7dOSGPr9NLXoYBqz7hMP
7mH+/ZyrrvwUTeH9MArYC0A1xFlMjJxhEf+JT1oI5A/Vo2I2nFUHB7yzRTHYvueWxbm7CC16rSyk
9xy08gm7Pk7TTwZyQTL/7l+Utx0yBf0YucI5fj4GQ6RvCaxR8fKCpvLNJJryZUA+cXaDFp+ao6IC
SVoxtaqExa5vXC9HCUVoDILTp8pkThaW+FVhM9AEBuxpYjXsJtgXz+xn7j6Z/bl3XjCH0/ldvENM
mqiWOBtBXagIAcVP//sdwOHVr3+EDbPEawD3ACP/Xim7kuz+2cc7/O8Ib/mxe1C4Tid8i0dHe+sq
e81M6PC5UlhFI7/nlTj7CEoGrqTEQxBqiZoMrIKVDJwvtQXB6JipY+trfz5oZ3l5XePmvzcJij+9
mH8aJmHLdh3hyqCpwgCq4HwTk914FIoSN+DUJlb+Nd8uB+V6BwDKmSNusFv9QLYKahyaVooPd76R
xxxG4woz5ZZjhPXLNtHlTKxV4VMaFJlrCinnvMGLd2h3Jk0X1lw9857mxAZlee451x4wed3Ebsh7
we0M1qkdoJJK6n6mjDnnXgPLs8wXpkv04gY7ShIza8QDT2YUgqJ1YhPe8ZSTTViREz3zoSVSz+2r
cHYKuktahrb29myYXBx1jVlndSMchTYUVDlQFqKn3HX4LFtjLFodT+88XaEiZCf1vLBPIufqIL/0
iIYu8aq0Mh6acLCnlsCq/Oe5K4VwqTeeAa81nNbN6cv83XPLR69xajisSqYL3SlzaRb0RZORygd8
IfybcnTPjI2cK/ub8cfp7Pq4soc8iZTDsSis2TOOKeOnr7hguwQ1c2Zrn3GLLjJI9N/+tYqdnjAH
oTJdMGLrmpmIDPTQvy19jryZ4HhU3rbzYhAPRlDwYL2W05PXGaE7Nnxd6IWPdac17MEUUCqsMloN
A0AHIXjm1paYNFha5mQYUyxcF61SINlzrsWDS3pqeO351u/PHAz7oZd1eWnA7dIjkhLTRu4XC442
siCkxtG4AC4jNzKp7gxyiMcV5yw+Tw9cBxGGMq/Jl5pzzYFbveLdhpp08GStSkRPsoYZCEj8xl3a
GKXFwVCxTIMIsEJ9x5Y36R9UrREtap4pMkkpx4DB+ND7DRUQdBWpmCSMcAbHykErDLGqKSjy/J2I
oS66j60Briud4cxwYfR/EMeRNap4mlrGiJcJvubc3/sYzkkE3eRnMVzNSW/scSrOIDwI35k554va
/2NuQDUYlVBXICh9vJ4JyMcGGsx0E5fP2MY6RxLwLk5F0xLOAXNQLo6vyEYVQUFvAlQx3nKjlb7c
diprgue80ZaMBn8ZABYtUiMCruHadl2K3pwa0Nk5dA7h3fzCVMQ598c2z3i3EzCCZOO6k2df+yDR
3dgs8mjcdD0z4qeVMLcJCYNrNSkoWBLMxjvZCmnSi/BiY2bPWhJMBb7FKbTRN19yX9JK9MMIZbTt
Z79PRl9eTAeqYP45FRmaCf3KW02y9J4Api9yb8BXqXlQ3LlymsKk9Pgphce65t+bVeliD6yMOU8z
rFSxaEjjUTtmteZOQXKUtCmmfadYQVFCuOskPpyanbjU1fsXh4JTmg+RZmxeC4HDkqnpAgtEu0xV
5TpLcJnggHDJeCanEk1NPEC18rYJZQtCVRRoJUs5DwqWQwtyfDjK8YQ4GaiF/eJAiuf9VBy/SELn
iaIvnTg5h42H2TE/ZJil1SuweMr5LmRxfLQLioJQ+hR78t/+i03XfTAKQOQhZnQyMWapJ3uQLZIH
PLGB2ug2cjyGaOehDvwt+k2id0I+NcJdaMAHaEaEjOiwEni7pMAMZPlK3GcYxYhGm73zcBa8kk5U
hKrS6mH5OhGEuhjoMfqubvqB3cND3nxGwYS27Y6sSP3Hnpk6Q7BNhlIFUbjtcn9RfG8IjsaNIcmM
EzP9o1gfGr6uxG8zRAt82uh8D+IjWZ1+l3beVzMOsqCB6t/n3fVar04we/8hVruwySXREPbm2Itd
U7ERgdpigRjz0mcgIhOElYyxoP5oZCzYDFPxVQivCvkriIiQ3JzFNIGPm8vqYGs9wpbOjJpwF131
jubIMhRwqyFGY/QK9zdW9fazV5+sY/1TRB4sLo4ZkVAUCSo8eJd49YQMePaWvSJMDuWo8io/y8tm
wDHitj+/LtEHTTP5Y+K/oHfRhY6FYN15GasUmFxfk/jczzx5+8jPDraMQti6GPADWfYx0YmdJqm5
+k944wVZIrX8TOBs+bSI9cwljhum6yDkUjW9wnFvIeUY6wGPVjZ0GlvuhzjS0DX41HbgJOQGw++h
8FZecT4/3LcjRdPe4xehB7x8N9/z1Wt/CYJHViFYmTP4gXp6ha8oEFFdrvs2srIKlIWpQALTKHM0
qC6znULxQWIchllRqgfpA7tXJvNWUALL5UNOWzbZdgv8TEpZxZtIEtFLaZoDAYGBPpO+xMRy0BWd
kkjzWRlABFbJi2gxtYO1ss6C9hCJ5z65n6o17vKKMpQv4/X3UJKge4hBObHzzPnc8rrqGm2ZyJoN
eNwfRpO6EEZ7iO25hNW6b0Wns/2Rj/BmQIEGXZKrbRaYEvIPgV8Ckm1yulk9YsFa8wBLQEWmnmlg
VIfJtCseZV2r1UHxx5LZ0YpvYFQOKNFJRHqEQaGjT465cWz+z1Wjgv0zPZF91j49MY8lhYzP2SyI
KvLTIKnNjd6TqlSaqqkDvtDOMPwaR2sKAyp5tUGmPHPrKiwqMPNH+/n9iftRQ6HAORjGCMjYSUoO
dys0sGwCzvxNRi5lXhu3aT8+hEr0Tyzkxr/r43D/ZKWXPEREpDTiSbdcC7jM7bBoxH9JFCRTJwqa
a2hYDAJG2disOoNNWiRn5h7xGFddj/ybtvckLyVDgZNIGG4AHKN0d5HUV1zoLEhkRSkeJy/WIXE4
Pm8MQL2Z/CjNfn2tUGaNxQmiKlL9qE/J4142l0WB0IXgniA08u1G2dZ8RLrBXFihh0b2gAEkwl/2
t83HMw/4wqWSdmJfRoKC+kldZezlGCLZBHlCwKMkmvlOu1fWEcqu/WHDNUWdwPqaYQ8wDfid1wbm
eQ39aBVCNRUny1exZigJO5JpFuBKGLJTMXszFw9ZuJle+F5P+WoPqaZQpcqzfShUjsAzHBE8mSQO
FuZA8trEYNGd7ZR3kisB8TVudT4Qp1h3VmYw8vwKoYVETy9tDVw/52h7yvIfLSOtvwiIJrOXF2jU
o+Xh1hrb2XFmubRrN8lQOLptT0J7EmwUuWZYrHthY/XX8T/kqj3WbzqZ+PbhrQHa+44b20+lNxlF
+Ux6TRFG5JwpkVmpNPxjQhGrXYtAyL3ZtPCh9srx5oGYEBMKlmjQ11C4ahb9fKhfSlO6H2E71JTx
1v/deL3Odc1jPz8iluB04DuGnggtC7i1pDqJKiCUnzY0QK7Me+xatW1zWpx7mboB0uPKYAIJVX8H
2NJ0pKiM8gd+NckhvPDyMWxOYTXA5/JVh7lTYuMGv/nJnMKuoFeJOlLIKjobZULefjah+OLoyi+E
d/Y4WNBOz4oELDDq80SEN89pBgdlrQbOUkDs8uuy4AWFk3tAIzK7Pf1LaEx+Tw4oo0+ITur5YXEG
uMgwgNem6rQuJrLD5BXTyuxGsf2/uaebgHUiiZcpSDH0qjcc61ZYwuqaSOFKDxGFyJgF/OkFLIUw
ceSrddEV5k3uaCCAjwR17f/ZAQrK9+K8G8PPiIZl5v9H6N+4HNYG+tWTERLq5x1VPh6SRh2KnHH8
qwyYvTVIdPesjTQNf5vetRv8cNkoxStQAqNfk8gJXDk8eqI1c0pHD/wmLZkPC4L1FxJvO6WW2CvL
DtTffIgAnLbb++Ydwh1VUUhV44Wz8fTQ9AhTC6MZ/M+LHYbOYXk6srHb+MUs+539wqxT5Yi0sI5q
uDvZE/ChOu66ZAB1N9Oa+b1+RQrXxOMgkqh3j1Cgb20MMUijTgcz+rsVgOjbMBw+XH+C2jaT0AQV
yrkfT3pDIX4pZnrB5JEzjkqPmwXGt8fm1OL61w/LfIb4UyuBpKS5jQcgNbL8K15huIxFbdSel+rT
769JL0lFn4yGDFPOLNyk6GOOItiQxeZCv8VNMDVyMfO7cR57vpKSu/v3k8OZvg91ZCcjumkZVqsH
/kC+W1kOOxxPHC2IgRgZgKZbf3AnLDr5L/Eahc+YbbuRAKq74jSFzmsjsG9TVAIULE9mgv4ELeSB
41Go5E+gCgd9aLZXSqna3YScUaRXJGf/sEPkNBQYDdtceqXuJue0jBqI0B8hhSI9En/E5IbsRV/S
3oB2uZX0piFhiGNSel7bPVVG0s26LAv1v3mG66UlmYnVwe6usY5eK6HbKYTlKvRkPVttiUxFC/vP
8Qi4lNFtFYIXBRBGwu+fg9iSy1LgFbyDr5c+O6hBD7aRt+nQfBCwewA9a7HnAhGyUYW9gOm8Wtq+
G1h24EyDVTypGytD50NbfaoeYyRAH/hzECC1Pwv2eXiszG+Q9iiE8SUaXo4ByEO7MP2aBExuBh3G
iW+4WkIFVRe1pPbyP6clQUr0W3npEIzi+lKMSmi8+BWuAi71otCUADcJ8/1fBKJJXKAR6DayR/5t
ixmGAFIezTUBzYaXY/szLU5ZCWi5Zx8QvCtePnvPlXe9P8cm7lOxJFHW9ZmEik8Hca6wtknUSXKa
+jxtjZgB7ROAY54qIgVm66wOHR2jDgdxv7Ge7zD//02JgUtVqXrcXyARXHXxWr748WQ4qvxpl9r8
p0wyoA3D8o9RngDYJ/7ZEgXJC4dZHooifptKJDxfGRj2UeOy+n5t++A396MCtjGisen+7AklpyRh
AQl82W5LUvFFehuF7a+z9hHcWM0lvK6DwRLEle0hXUUn0xFNAYYyCxYH+mUM/Ytqp4YMlxViC0z1
3ST0Y5Y4LXrUWvOPbyYjXbyncgGfzT5bv1qKV/mz5Dy0HVE2HSeS7VVqQnLq0+AlJhg+aLAi4Mp8
uVs1hQNJDxFHNPcW3LpBZlH537FjlPo98JxppJICJZ3cU4rpKPud+AD+27GEUFsz6h+GOyUePE9H
K1f9ylVDnLJA8UUvb9bRvroDYzb9ICzbp0fTOWzN2kdlBCovOWZVS25mTpkM7z8uBMkz51J2JJk1
6poo8aa5tqTXCsUKM7tpbAFdLwm4nmiPlPwqqMBMs1dmuPYz0WDT8HjqF4Alye0cjokiVfn+gwgw
X5ygYImST+H5RFYXWc1GsUH64rNhtdpyIVe8z2kmo0avfjBIqZMllFCZ3ZxGqFmzwXHgJh9+wcEY
FB2PLeQW7AFRbPVx1CuQgmcVUOp6vhvaaXMzS5O9Q7pmvJjaZ1OqThfkY0VQSik6kgyoc+UZOJT/
6d8bhLjQw/C5nPiQ13sbUDtjW8Z0ZDU7DLoXBY6TIwV4Pom6mctYpcM1oA//tjntiwRQnSkyAVq4
IrAXVNsHh+2ple4ryP7GMyjHB/s+3OLLTmSx4nwWrAwaiCAfb/l9LEQCQJegDT7r2iIEjWjORdZR
C+3vFYx3ExpetQe8eW4wWAJKKywVbdP3PSX6JEVASmGuBVCeg7Qxnfw6i8oLkG6acXv6oACaBTNN
a2YcpvK4AtLAabyzERQDvLLfOTjPI07iqM1L/rePHzIXViY4mKNH5wGmvTWAQNKOvxoYO6FRZF73
MIFtPMTKRSQ0DM5L4S36cLIFlZopP5C6YQzzZt8wFzZM4rlLbA0DenCo+3TIs+/FyjXSQvkL2Bxc
daK3XUrHAnXQ2k5YNA4O3Qc+NKR0qnNVJ7O1WGuccSfuiURKQyCMUHCHP/6+gzHZ5wRmsMlQdvqL
eijfUGmZlCU/2zYdBbvh+o5YYUs9+cYjDu89sKeVHP/p0jaUQPHYKeWmg1HDGsFSSNne6vmEBC85
Almj4vX1loF+a52lzthnDWSnfTH9lzq+KlK9NI29yx0FXTeH03XKGm/umwb0jDZLg+hLWsdWMh0b
8/5sIA079lvrFwmqE92tTThhX0FKXdVNmpAJXRJQ29fRlOhOQAzjzrX9s+YJUKp4dLqXq0SkqUVf
Hta4mwQhB6Mte8v4a65DqgW/qddAUcPZiYFSRGAFtMKsoOKjtGYhUiLFj2tLoE40bmI5qBa26GNS
BbHSOyZuRaLIM0G7ZYR47xyKcxOOLxtqB2yMQc3D03pvc8KNS2VssYZGWwN+Q5NGX93HMMruNTT+
aI1zfhM+s37QCmt3m92n/FPTqD3or1/e4EQPU8F0HfEWoLPWkYBG/p5whNv7nV2XSYJAp0Uk2oZe
pudplHX0VejykyFgXmfJKM5baYebylcidH5JCu43e7TD27WSMOqiJyz/mjdwU3gwOUoojua0KH4T
Z+hoqZPKOfNNypZFzrAMCsPx52zzXLsrQqlGpXehaoERGHSOOiizkZXSDTtyjKf6OiJOhoM6vOxo
gwlWKNrpVpAK6877VFVvVkauj8IETxzNDvbN0FfrGxKKFHay4OtY3vZcdBlCdSa+fw6OLwBIvJyn
rSPhLV+irTgli5sZmcKE3JXBhGiyDWX5JjDm0pds2LnZYf71jRynAV6ZlEv3cg3T2kQGMQlMmROT
LvGOUIRkFk6bq9uOxWzAuUTOIsvWEtjxAHivUzK4ruGNo3cr6H5WjxRtf9aOemkr5IXOTBuRZXEY
NWoVbQt/xqaN+w51MAa2X3nbNwTPlK5D81Cks3bxQIYSV8hqAMjGDKXBih+DVJVz3HEX8g2kH3sy
m+7/kV9G/dqqDKT2lSqcj0kBFUJ2YhqJrFGTmuIWSC4Ueqg9K8dIuwNI8vvqGZvD2+YSZPcuiteU
iCctdodpGU2dLrwP2oUQSdA2bQsdLZWW6LEJlSDmaAF7BSwdDQJgaSoHKGTsUl2k5ghrJayx+aiu
q9vbYATmwWCH66kQoIEybRidXBaN6BowJZetb4sIQRWeA2wXuwqqX5z/6XxczOvCtjVjj8BuZWHO
7A/dkFFC+x7SmFghJVcTw99u6QffVwOzFEh9VjWHYULz/+vwnjFmbQyLJm+vuYFU2uyz4saNoaYA
tCw2ti18dzhjy87QU6EZPHE6f7fZu16iDcffSYh9wk308HZUDpNWPNJlJ0U/12X7BTG52FXMhXLC
rIvbMsIh0V2P5JST2SqgyK9lvGhzX4Q1gbXTGk1WK4vwn8vsfni8dH7hu9lTeP8ccA1LbBuW/Psc
Ib/VKhmAiqSQcMg8r24cdEDF5IIHeekohCOK5SQJD9LcQvyuEZzUc8ugzFDJtiElMqFon61OnDJL
MfzjuxoXAloTm2gjEHJmZY64tW6NTxyuudlUAzCY4xlg9NKYdIHog0IZeklb0CEGNG4pnBewHNBg
IreAfbZNyXtDehHjqb36BrGdNvge9huxO+vg+Es/vEPq5BWWT4mY98dIdfJs9P53Ag/Eybn+Obe6
Rbdr5oKRSlvTSVlbdBuVcRjLT7EUuIWVTB8B7Ec9oBcOE08emwcfNtpXlnhpiaQovPKY20HI+qmo
ukFWJrEByuqw372sXOIKIE7sswEH4h/vy52adUO4CIKvQcJLtNlL2EBcu8rN+zfHtRhy8+tP7gai
11MsRnJ9wttM4b0nIyrOS7b5fXi2+Wowz+nBiVA7T1MVlRVZ2cwVBbWP1+5JUXzww6LYyIuMzvcT
AGy91aorFvgBPRXxaWB1Ed1R31Ekt6f4Y2r0tNn4Gd/8B5g8JxpchnVjhmmK6mwEIBDiD0Vq9bPH
GQTjT3vev4MP0axMobNSo8fF598fxc98so98cMzFjiZv1VeKt0m8KYdM73187CqP+QFW1rQL1w4U
k0AVQofR1GBDtSFcCWQfEzRQUMmIPGeC5NmmDGjOsEojdATnNQ2MML2k//KQRbCOyQejhDvILXy9
OxU2OxBS/oNyqMM+61OO7mZLrLZYmKjSui5iu7k1hV8ym/59ZFGsjDA4XAHz3pXDvrOcZxYnmrZd
DJVHwsv3c25lL7Ah4/dd/3yhSWUkMfCEDCCKaH/iYvnhAVN3J4KqkBARDQWi95NOQ/EwpIgo0vyb
Jupqw8X6AXOyhpyIAlJiRUeKZ+6qWvPZ3klNgVJkwtWZQWP1y389mvxwqjbLtmoblcEMObnlaDOB
qG6ptq0PeIy8IOpXi/+X6fon407r7WVpd1REvqatuo3DY3Zd081qWQQgKVXyAbP1uO4CnMnKeNb6
CRWmo/mrYW0tHhDxbApJufs02/VGS4PNNR0qYlGd3xFFS9ddfFwpVRwBeXAk4xXFhvpQ3Xk5Z8sD
MoSBO2RRKN/321sk31gThbrAEskYPdSytJRzgEnia+yO/wOmGG4iFVkwovRXGiZQMPbFPUVSK2sv
gT4RGDQDMGxc+zU5z/LBrj1aDmeRPfN/2XM/HeltZXTNzQr5LCNYV/e3uR7stk0LxQE9kfVeqXD7
TYpKEIZRXckgiL/65i8HKt19gifQHMMFT018pk682hmMZ4bFgla+5rd/SmOy+8SvBegDTh6guiAP
cJOFf4ZIlJuPmNQCnUJ/90FC8R+Bki2BgNE4A94IuQ+4QXg2sRR+pjaez14K4BiyjtCE9MwjbPm5
uYVfoizlZXEzQe51Fk9ZWPYLbMxL9I2pWDewiSzN5C+hU14q0W1HJnkfw9fDKhH1ovHbUFGiGhZI
oGvMgSa8mRju6isWfyudHQR8ht8LyleBwdFMfvKF3YSZrmAAZ5xI/9mvG9ay7G7yG4a1H8j8Cm3e
p5Jmdt9d7KrMeZaj+OeIM3PBczbbHZZGwR9sv1oZep9L2In00XcrR3D7rh5lGd3RZU4lNM4XjqJU
hUSvHP6fISYrEGBCRh/hYGx2uCILaUomrbTeBDjP02jMZclQjphczIPsj9O7+DpufJ4eDFO1pRcj
dyaqGthpNN+6/KJMtb93Cg4DFJV3IhGYLKpKadUVePk0Hb0LyhwpsVD4f3e5ddJPYUE8DH05/7IL
aTXumVuExc7EZhL0eg38BvMNoVC1sSGDGvlhv22TsuubmrthIZVR1nO0ZglO/3LrSwAIjlRqQOCM
2nAh7rb6iTkBPLNcpS6BE3inVB67Q/adaDbzRxEhPZUOezADEvJ2auUJWBfb1e/FRlgZw854CZd3
VcZHL3ggU1hx4Zb6jCs1p5Et2bOXekrENsxMOeCINV7WPbcFrKoeDMXHgHoJqg+i1ZX/SBC5Vhov
bT7LOTLIGFkz+UUaNK67HOusx7o3y9TlNFqZNGHPCQvoK+GutNvEA6Km0PVlmbuBRakkUORaV5Jm
Dv7QMPjMeM8e54f4yPluid7mIK2Hxf8d40dbu3fZgWToReWtucj/859ynQ1EC8MnIFARNqaCVpRl
hA+bUMHAwVWVbiRBNlIO2VQhlzoDD/PN+ShJjX78Wljt/lTyXovXWdwyNRaYh21H9MlTU7QMgyiD
3B5GMQbJSYTZWleDrzwOZmQ9xqNayOcV9dW+ylGGW78OpDMjjjAK5C3oKB27EU05MtoaSLVcUwEY
QEqg4ry0C2opAlBeFsxo7n0MHYAfzqElSkZ+ZIZ3RoreOqf/vaQD6VIDaW++pcr5Yeb9Bae9IZae
uN/zBIMD4j+w9ikQneKPibZfz/n82crIDc18RXarv5FswB8zYATzN8JWbwMsBjwB8PPVLE5fyaR8
AvW1ACALWj5O7IIJkX4WgkB4N/CLcL6WD19052HAMfAXjKaBXAP6S51DEp0xbZHRPMd9WDAltDdA
ETJS1pKM2+aDf5A9EJC41QRdhrKkn0Q8mphKBosGl3N09FLkRpNRc0qreMfl0fDlIr0KU5i8LZ3D
VWH52x7agqEb9ViRhHpi1WkYyXlgpJlDOaU1rnp/JYurj4lTSrIY54ANT0qgqBRfNOHEtgGCeYKY
rzglWDMbMNSXtFmFuw9pRvJaSCm+Tfl850KqprleKMriqhpAHdFxbBiYm3XfiLksuCQ1SpLf7fRc
owy6iOjH5YY5JJz+nmUQN2xvyyQIC0ZRTER5QS0Er6oMg69GqWnmdM/t+d+vTgnP60Q/HKsVvUeC
tMbiJ0PS87dmtTQLFdFjhlWv+MHn3wfEs6LXmBXqhNvwyV5jHJk+gZfamzUsjRfhkqXCbVfHWvCr
Zb7s3sNJ6VUYa738n1hwsk0L2Rkcj7AHfU9ouERoHlp+luKcYyBA34mhgSpnxKghM5Uj2osch2eo
33i93Tyy5HYYaByPTlr6WqAOmNIpPhRCXL70YIapi5gfyrjtqGx+Yl6ph9XFeiZTWId02BB57Ps0
CulKTSjyX+gJniSwPqjLTuzMGKnPngVcAxytFAdJ8YILO17FAOu/NCP6nJiz7rcc7E9uTVmhoVDN
e/eECaXFzQNCNwlYsWNVtf3ccAS5BDNeo+ZJ7Jdi8/TwB/7zdRfzzLV6HBaqfDdgNOvjappLT8f5
ljNK+ONMNI6BixMcLIFfcqHcl+0X9oKjOOansdenQ9/NtBGHyCdeEZ6aN/k/aUnu9Y++YzpH4voY
j3Q/moTaQMzTAMn6m5htJO4M1exfTzLTwlyyKS6tQUiUdBq9Da9+a80YsCDLz5OAuvUpFwzEqwhR
fQnXPLk5+pTunkqq3zDOx+yld6LOGaouO4cwgo6/4LWd27y5kfRL7G+O0cwIrtJr2bPphL8ctTcr
magYaIcRaBw6R69CotNOdfh44xNA3B+Pm4YLQE13Ysu4dBTnfiI0qYk+PgiYG97V+6/EZro+PKS1
jErExPchCh3RAiqaVSNZuv72SrVkfB4BMIvI98kuNTGPVAVQqxx4TRMyrWyq1vNDagubrhoG8auc
a3n1dtvpKg3hX3OMz7KakIkLeDAdDSPrqEyl6HslGhyLNnMR3YnwaU57uLf5RzxwhCPwMd/4ng7s
9/8MxZI49GpVMkMsE44dvTsvI0ooxZNMNGl6Rh5F4sBHfCqRyrk7bGPCXhM30Edxa01JoRkiHupk
OdWIAtXwWzBmucm8JuKPpr+ce4pBHH8YWyV+dnMAub4d+D+6fBbtiPnyHgmXvt6CnSrfp8D9qSpP
NqocnIzTFI8zaiCYuil27BcdztfYsr2FLVdrpzD+1Zme0WGT0J/qcmSd1c1csKP9zC/nIvUfJ+6g
PPPY2/CUkPItYmRTII6+JBy8oEcMhTfI41kOTUbqU/jpdVypBovBrWOxTPPU6NUGckDqSrE55NxD
jgi1gGDq9fWUCOEUMAo/71pRDvGsHMMgoqFm9jH531dcm9Qf2KPDGybWqfyFFbFbMyjmLWQRnqxE
R+sMYQw5ZHGebkkKyt+uBV01O/LzqwhFRG8ax9aWTpAXFfPa/qMV7ifz46PR3fGfC9g3Y+jref9f
RVAwZ4G90rcNWfGoFKSGXt0+rctnxO51kJH6dBZSXqCBiYblb4Qa7h+i1tm7kHFczvIbK6M+IAZJ
sOEkIIT+bvuvKVPlrtSxO1ejHGQz/eTr3y78COzU7xcKUwTkxQKFiCEJ0DjiP6t+etJJiFkhR3sL
UNKVuTQudSBfO7C8eHaRFoQpvXnf78wkMKxuHJx20J6y0QuggKZLgCLDS9Klg+mscsNAYDYtyUSF
7gBYH/IJxlx8WMsckrexOEe2wAonSmJBAdtnxs+7fZQUMfjxAWSFkK25BbRin1obWANObQcxEbUu
QTkhqzwKpw3coKuKOwsrQ2qHmxDjFtg57Snt0hDp11FmNr1WIy580DUfouZ9u4r/p/KkUbEXVPEI
P5rKzpys2p3zbW/YRIVTYD8ZF8sdSasEDTPU0pl71v84t9wJRDmgEBq9e/hUAYnkD0v4d+BD6psK
WpsG3X1rhe5IhQjS8d4XCuNBDXdhziJCtmrPBzasP4yC0utZlJGGqfy6NNI/H2uGmgaVO+d1xgzo
NY1riZaovj/qAGILkTADWo3kywaUAzGhkPfKo6nbvrlQwX1putOyzksSGFUYMjwQnHBA0xMVB824
zFbJch3j6qFjLxs09NgUsLJIuf3c09ZAwXKfwhnVBzxzi7lctj6xraaNhCSQsp4CLu7BVDRSSQc9
3XviI474itl/2YcqoAcgon5UbP+FBDTsGuYKR5vpyC3gvfE3d1XmemfI2O9/8+eiq128XSMPDzpY
Aa/mnBLU5ghqCO9RCuJlID1etvs76glG9kHNeWGgme+i9cNNRDFS/5HLb9yjNBDvX68SjV+9yQrF
YJOTv+ISheN6xOgovMY6orwkBml3kwxgGTmKqzT6qt8D4nErhMrh+cpaykTC/aHXOQjUxdSYHNzB
efGsB+sFKY6IBF8bNMI7EbluXW0y0yLcPeb2LYPw4zDoz9ewLV0z0J632lAjdwz6VHQzAiPIQtPT
LkmV/mWwX39nmhJYD16wNYL/S4ewgc9h9GHSoJIaJjvZq9DrmsybU1gsDJUwltDf/Vbsbo5TElQo
Agzm0nX9ngvVrtnYcM4aMvF+J1Om0IPdxyO6ourVjs8D1GK+YEgMB1g7/8RhZpfYooKU0PFFZ8Zy
yaJ3BLZHzMB3NVZoeaFC3jYjo4ER9n1/WqgkwEQiTwVV9uD8tkjp++YQfrzaK7M2SouPaprXxKif
7Qx3ERT3ucRbXLlLt6GtK8yP/+s/bEn2sMWdThL9Okj7wH9BaE6OzKKm0uHlRlOfvwUmD2Iq50sc
L/4lRrsqD8FB7BiL6v4Bd59WmTPl4VS/Km6sKxwQBe76YbLn/fFaOGo7coVV/bCa4QWCUNdYtPZg
6EopGWl73H5yM2GiREoGzAO4u2xgbk8gufazKqEGARohLvetMwIm4/X0AfW5XWNtAYC+dbgJMaPS
MHKs+4Rb6BRP87yl4GKBoeWGzaHWTyS3PUVrsvo53L6PazLCDksNajFR5NtduHZhi16dZllhmvmt
Ra+gfJIq755L1nSIxOCxiDBbqhqJWCU0gQ5vCwW4Gc1Xo0aB5mtSALaAkrOch6OilRqO5T4/hpSF
NjyGAV4AbxNJN0dMp6mpcsFBi44uWnCjOUYFmZd/drTYG8hUxc2EynIaXFoT07ooazD0Z9HYrrYx
WRB4lFqzEBxiuf9QqeNFtk01ipOm8jNePcdychpwAA6tobsRiKkf/2XpX0F9QaHtjJuYHvidbzZM
57e/w8o8jwTlhvsr9vg6QWSZ8IR0X/2FYdRy8Q3eesHpFzS06r6FAIYvDi7XNnsJCcQmPEXomABG
6MhoPqMye4hXhOqUnrGmEZglUlyh09gy2ouWuT9SoS8mnjqZVR8uno0D8uL+SY51Kv+BqUNBAPcM
EhG5Z7UhwCeR1cWtn7IH65iLc1pzdv9kA4Eeb9nqjz5cUV0+OOfy+GP8Yu3IPjd7IQbODqNbN1Nu
tyjuCKTC9ZFBCmc5OGR60oTjwtGIzgc60MyaXK0JsTfr1eN7dNrUD6c0P5I/u6jqbhCozIt6Qmxe
e7qggwdkFGGqJuv0i1CfrNy4RiR00mDqPWCqpGFuiT5CIBI0v6mVe9saZf0GKlNPXf03FaDYdJWj
jJ/AfCJbHONR7hTYC7Vv/l3AgYp6JVZsaXqXMK7OSOXk5gJZtoMhV9S2JD6gouWy2CWBOGB3P60g
fmUzKsV7HAs0RfzlPeQ+J/zxpSEt1YCWc8vftsLpB4OQtKm/6i82578R6gWdbKWXspaZTcjnyvRd
7cXS2gdcaLaVEBEppZHwDLPIhR9IAM4/zHCpO0TQ1fbipGYPS9/1kDd8mXyEb69MbNNRdlseEO0h
SVoHP3iNyLsjshlNV9C7x0q0sNwc1yT+AtjG36Xp0XRZDuQEyVvCHVlTgI5HAjFvvp3wCq03MvF7
8wH93YQQv83s8Bj2sXwPvaF0aQu1iagWJYJClRob70P2lxb4jhB4/hEixsVFe6DSDw9kj9r/cjoI
kLEw+khHp5wZn6sUjTI+6EmXA9hHEHOs5vzJ7uTBOPzu0Zncb7MKb9EPYyuhkeBDvW8uZXsa7ewy
Zkus8t39c1H8RakjyrrWDx97LQs2XlxPL02c8bXPArIQnrKjbi5LO0078YVHdWmVsJoYOphApPje
RaldD6n8/G2LDWrOfn4sXLqoJ0KmPW9w3K8/XmUVkN5DngyrlSaFVx9+MOZBw+aq0vB83I2ZS26T
xqMOTvPs5CB1DnuYj7AynK7XVOA10mv2hqJ/KKL2oFOw1mHM9r8Bh1gTgUwE2ouHCCJGJbTxYN57
N3zWgyzoe+xo9FiremA/8lY8wCqLob4Ea/y79S0RKKwtUqsJWRcpT4qIGe3DZ/DB6z8ZRYvjT0xQ
7jvG+n3Xf4Gy9sqEv3VprLh7Il1FgVk4qQVGDZyySXhbGKlfv0MmtT0N9HWm0v3fffir6k26WJee
MJEFWPdxjLH8QLGG4NT12ZG962Nkc3MVGus1kNpS6w3FfSk6us+07QafDoc0lQjiE8iLyhG7USUW
6vI0vbUfKT/x4nzmxQ+cM36a1RRZxXOVfEB9kpw/+gqlSO5P1YhRh1yK+yr1bUagvw64CWD4IExp
yL/NZVzOVeMEWpI34Ktmvot1mYxzzZ2DFZPh2596PMupfVqCGL5MfiAR4hDn9WvomUnF3D7Xhtjj
pmA6du2Qdex5jIvkp7mXPOSX1KF8CaSThfNEVZnsHyI7QAQmjnkYaLT4AFSzhXPphdBPALn9/13E
Rcb2+RtDLvfywiwHOg8iyOZ+vc3i6aZQ7UH/Pf96k6Ryu8C0toEfehm+OoVSn1ReS9m6euQXUwel
pBFalGQFj6F/B/vSzENk8wXitsPH9T+5fn+1JHSfvepiM8UQjPeEjDlXbntbxim07polVVcROJcE
uobVGjHvAVZbvC9pYqms4RAImSXCR2uKqDWz3I5GePCciP5AefOslpuP6DZQ9b5owxeqhGJn8AfV
j6zL2wM1PSBKsPovwGFQnqKR3BMafHh6jNfPxH97hri3AI//h7Ht6a32SoRA23/+s684kFGo6sQt
Xlp7ypuLLO4owjsYQu+FS415LPAlqMPejczhJ23XH8mH3EX/1VuNnRvyGcxgAQYXA1AdZKGLEhtM
uBuZBO2djQ6f1o497qo6r8ZO64+VSF/1VJHWTZBXmxJTtsW5f9HqxwM//xk9xs5SAE7B1ncAPs6p
ZGWkaXi/46AwA5jOdAJRFquyAeGpaLnkMH/nxbRBi9ZRFpfD9tU3v4Q8VblK1X1ecp6m0Q3xx4PK
1wrQNccBmlKpdub8mFF5gXIjqEFCVtD2NOe80AWb7gtkuChLL08Wr4R8grkeEHhg8iXXlRiZxQqP
rkHpKYwCApD4372LaTYPDlmoYqeqWCqD1btcpswge/1ZQTbrTIo8dVfq1MidipoetYm2ZAnaA4fP
8+GkNds7xDuL1lHLhz+rj/tUDay6dA1bg3Uo7ntb8EAAEDQE1c6CruRiMAIcfcdPxBMgghfnU78h
93KQvX0YZGleLi+TL8bqk4E4km28IUbuoAtmRH5BV6w/9eXsupY08bI3IDGtOAMKAIlvy/gXqAif
qOZX4a85FcCBXl4CDpBFL78OKVQsELcP3AajD4NuSx5vUyR8wE0hk8W2mtzAyyL4zhEL8lhvnJA+
2W1ozEr8dqSzXWrMpffW6LFmiZ+EEXo3ub0bRatGd7PkVGsasrfUM6/ybE6UBu5U4AwfaUEa8am9
EKXBNhQTfg797uhCyLK5/de69HeKq+nH6pOGQNxUzFDn0lSXS6FeqzdeoqMdxgV7eNN4SRVD5N2n
aBVr+I9o/RcJPQys1w+I2JKgLMN/xSgW1a6bSlIQUJkCL3fGWoGAuE26MBJ9ugQ7j480GBCb/dmH
r+YtQhXeEivxuoBpF634KFGNwkUabzQhQQVps/U9Zk/dlKBRBtXkjgUlihK7C/VRnvTNAz0X9xse
2XDsSu78VFnomNhBieTqCZD8XrpWKzTqyMgJO80thc/ygcrlQDItWHKLh7YvHBdZB1HsuiELHe0o
92eKDcqHf642hig69B0iBM326uKecGz0kHI+cMelaPlKX1plud4AUl24PjTXWderiFsbjElHtK9X
zxt2oaa0o1F2v0MUI2yV58wvF/aKOVg6GVZBFA6WtqFlIAJoD7Q04vNpGIsQ2IYeRMVEnnxg8OSA
h/+DS6eCDWCIuk3v4g8OjuKHrjAVNE6wmIaPiGtCFtPYDigCSrAn+PiwiUHLEJT9aSLZPhB1mjC8
UEFAdA6KQiSzVbQOLYn93hT+oLoQCe7QPvlGVS2tmHSg62t4sAJa6HsXCN7wmS08Hi1VPOAtboRY
KuVUEN3b9wZJBzlLid+HXk9t9L2zZkIQxGUm2fG1+quHnbtNTobBY4NkUTMSoLEbB50Kpk2M4VzY
kfeNUFDNnpnuYBFud2oyCxQKPKSPm3PecyqaQBCub8kzJOVlRpas5M3wEPxrF8xt1mXJtTSd9lc+
2l5BxLVQ5RjN8yQtwLsZgMJ99hyRyMELt1pwNN/YvDlyxYDqIWK0aWNOoZMiEd0er+rxN4ChEO8e
cUQXVm4FB4xVif1hRqCXKgUaIQJWkm+5G4UTlu4tMs/1yGy4TEmvm/czy3pfZoCgNeQUHYHP+Ar6
2POJUDXdnnYSyi1oX1qO1HZ42s8CVn1iDQdkmn2sTY1evaP6lfWNG9Aoe8mXbm5ErX8HuZ9TGdKb
ZcYg0NGPc3SwMCqK/Br5EAZwCKF0uwQyFrARU2sOMUUOSe+VlQtB5BtWjv/nbs075plVPxXHROI7
bICuGbTSCYeM1Grod4jcUTxCodTHV2B6jP3ZLOMWwf/Nm+x9335qFpPyiKvgCnmSmpqkYzifH5+1
D9c9kVg2WhEo/pvvKjp0Z338t4uLJRwVuXM+7jBo2CQsNBlpnuyVRPS4xbMJPR3ISK0+eXKZIKd1
r/d1GQdfXp83QdNglqnAJbFcESEXsrLvinLI8JntCtUNORCYDPLGAs6tJNNY0GPlFndsBXANx2/t
T+BWUuI3Yf31kHp0J9E3pkjUHkNoW8IRgwTApffLh0tZhQfydGUUggHdOwFBCf5qEuCJCnQDkET6
SI9w+C6u/Y7aHzbNBoeb1J4a/+tMVV+twEr///9jdC86otB9qRkaiRyiRy3wHv9ux78AHLDpa+fl
Bq7CkXUBwj21aRzt/znPOu/bzqHf69LrY11aGVMcIs/QS3bovDrzFGH01B8YD+h1DUoH/Xavc5JN
er95RJO0yLFs8n2hqG6O7ZzLufZiOb2aZ9tEJw5NDID6dLMrves364s41d1DCugaCPqC4KwC9oob
Sq8v6drbTZ1uWnq88NpHlJZ0515scAafDSv/HnKS6OSwjW9Z0ux0mQuuhpPYRpQBHUE9oRkkWsv/
5LRYJDUHMAGdDCkUcvsKiW303Nb3ueKhvgl4saRWOZZoG8lVHpsAM2+0Styfl3Ok1Us2A3R18II8
Ky7p04vjug/UvMM0x2J1CbPNeUKXhaHEkf/3IQtSLEbc8dDu9CSMwODJ3S49S33AX5JaCNjM5mis
HKkx6zIMsWeCWIFmV6cXWAChWt2veT03QJnLeahJF9NFppvBrzDv0dmtNZ4TInd+S5uTk29Wzeia
iyRluQjHsP2ARbuvW5hAZv5B+arjlhvDoxZy3fqkbJ1VRfDfhY32It94lpZguZEio6WmCcC9F98M
eglg1eSJgXV2PGPhgMC0xoOeUcIpqkH1CwfqBva9yOy8QBHbsghm0J2rE8H0dTml0YcsTuXAcGl9
aejKvA46ERzeiL4rkTQXbm0U+RAJOmbAbeiWct1Or+wl3mFHA2Y2unnIhUqnxKB8xa/VXaAbIJtI
Q+6W3xpetVXGLFQfKsOzjkyDJT76weL7hJv765384MBFE+/VnqNoQub4d2E3J4g4LQFtwMTnFIUt
ZoyL2ijJgpZ2J/eQxWbKKrM7iTeIiGRCXB6yDKIs/elxENZbMj6WQQmcrg1awmUfodrkTP0eSLBg
9lMPC9P61CDwrGwZpNfkGbc0Gr8SN4sMgnQfvEipNWkiP25tV4ajZEtA43e6qm3w/EzC79Z7BnJw
RjPfzuS/qlmt/SPuI7M3nZ7YY5cnxJfnGFhK1khuR35uHlr1r1CQlrUdcFajk9xy8VbJUgwkN9tl
rdlvOC7nHZn4gGWIEAnbrRUHD2tUK4MhOWnmbXSk8A3kROwgC8qanxDoK3vr8RjUn7RppASFlplM
0y3BGMGlhKiOB8adX6AD/uGJsKMO9hh0brTwXpO5Nz0AjPSz3zdxpQWuvx9MC0t6CRksJofdyYnN
hreaqR9IP1uQbnHc701Mjj1X1mwhj86+UthoqhAq2TTsIF945ig55GK/y+F01KzFp0pw7Wv3Fhf3
hs9sY1JLXguCq3ej2J6p4PtusUbcu82lomh02/xWVVozb+l8KU02Y0GAmaNMTbrv+Vo62nDZx47l
wgdjgTt5yupZXs1TguSn7qGebZiY2gdXYc8ljRoiSCDV4ePRw3FltyDVwffB/E0Tgx6RUbdRrI9q
dk+KIDzGMW/VWBtI1yZHCGPOGLZD4g21YG1L66mUjRZDznXOdvvCVCwrh5nAndqzMpx3407PeX69
GVEP59kGE43RX2+bLdPu+89WakP/c4PF3vmtFnfxEvFFwLYJ9vW0XySYHPxmUIHuR9tHUjriREPp
/4Scf+OkOv2+5c+X6UsAHIi+uJyYRO8KYyaSeqT3A0kogxUEckGIvYzHFjDZ/kXajBq04f5o0VdX
sWz2FQTkeEBf84d1dYyOnkaAeEAqnQz6ZfCCxuJSajgjmIjcQxc8vRgnn1nSD/JraUITxn6IGCRG
y/P13croUpFyGmnimX0V3caSqVtt98HSxWfp8asChEZafCkeH9SOT9y1qbpQFOY4XQGeyhGQB90g
SyhFPk/BPU3HrsKaapDrhSlGEY5mXfQ6H1UBQvommtK3Hsx0aWiu40KiE+O8zmR0xLJvbQ15jD1s
bBAYljCzzJZRoGlKXTrlr+aORkF9FFQXth/iQibziSHT2MdMUW40VGCZskBsEi5G3Xh7WwCtOdqn
8rEDrwv6veLOEQIGbuinXDQjRArZSerZr8urPC6xpW9nm45ZN1+JFHHNUYAC1LGfkfPW3qDbp70w
Q0ahUPcYxgtedpjtgm9nlTU4/A00EqUswvhgEJyzpgrgVycWTObRjO1E7NOohFivWMlma1cN+seY
S03TkhlswCfZe5Cn0TX3u4OiiYm4SsH7AVh2j1yiN1mfoLmYzz2/6VjYY6pVoJT+BqAIltY0GjSN
sFcq2L0opw93hFnQFFUNGXW3nMdRfdli7qai9OvZgUY7O1xFYYHUKCbpfrzhVJsqLl92Y3huKJE0
2T7RsN9JnXCFcayY3lDTd9KIk+CQRiHCexWnjFUB7dMcB7U3N9kvfeaXyWqlqtj6OvHoP/qZBKRr
DMCsEC54SGC9Mkls6BKbadLh/R68N5uyBehk+/MLv+2pOllbptJP6KDOc3lq8an4jbqJ1VQf4aT/
oOXCqbaRdy+JndkTfuLm4Gk74XhbnuA+cbshUNednvFI/BxiAJPterQkoq63gMJ+KzYVcOgZ5NWf
ZPV+n1u1lByrz4feZyTkhhzWdlVyf0F1ke1zwojkIlYhm6hA6x4YIDuGPD4hkmLStlxXgnPULE9G
yYFuzPz4F3V/+97DVP73Y6PaIvzPS0TL1fFhotEczoFL5Q9un+iail2EDQqWqBMay2kIhzoqvBF5
F8p1uiOEYmYpPwRrQcLJLhVkieSCsPkK0fMQEstig7k81DKr2fv6V0XtA4FgohOQOy262xk5Q6Uq
w0AiMWEyjUQdAEDluJB4G5IBSs+aSf4DmFd5VCpymNlBW54T1yi70bVuxWpQpKbBGdepskY87CKe
8ZXh3fkfX3HvpZj6F4rfCVfbdFNNMPfQMs91YXhCg1c3JcVhi0twEhJA7n6R/pJ5N02xhU7QHRL3
tLxblv2t+yJI9ZXaKS649PpJqhOwxdHPRJHbU65k9/8Et6jva+QhGNniRdGIVJVsJdxs8r3G0rr+
nuRgvKq9SrbziFwNEqG9cZ2s+nBK2Fa/GSlp9RB42ovPwGrygLTnZ9a88FA0qfU5XeP2WO0HZkR+
l3sDteFz5h5oOfitPc64oHzj+xUwHn9Gx9y+qJzbX5u0VgpE+A8C6TCrJ6amEksxMTy4e0qQDaTQ
2unuCSM2vOrTNm7MqYdZKKZB5h0RW/czZ6eX4qURyUUQPsMpP8+skWfJ+V7GQpWchYpQLasASvoy
6epfJ9ejXOECea5SAMTpbV6bI/jv+cI5LEnoPLJ+hoHWMlKCzCvreT+seyq0kIehHt2TSPAveRRf
I/LnFkONohDRtTFA0wiyPBpvQEftKbtuIK3lUqocVcu5FnlUGne91hCzQnFX97lcDrJ4ivxRnWfC
vpovPCf/3QeOh64QLWTSVHx5VdUwoiwxbMqT+ixQsx9vuzvd4ub0LImC2hXE5dtrj2cFlPZeEA2u
jhe2+Ba/KVKlhMr8LSVwyrKWfvWytQFEwMtALkedDiPrugdHMlefoaYMzFHdJ/fRTuSmr0v+P9q0
mzmKkc+koOh7X7p24FwnvFkspjNsBGvfwZKKR+e5qBl2O3vT1a5b50fMyNOtraNwMabB03XK5LLo
+HRpMXdYZ9EvUt3yHLaBvOofiamNvjqPhroYF6n2wyUBsWGw2giRv+BIJINHjAEFh8p1NVAk+krc
0MaqJMVYxhBxg028xFX1k7yQvNVva7TKjOwg1neQ/X2nEqEmw61jo6D4frnh2mEm/7nCxPTCgMcu
mzOirgokh2bqeA30ZM8gq/pBVj+UPQcBdirzwYtvJv3uiCzFtw5N9NIwaelNTd+RGtWu76noBmDE
+WqCmrRDxVWr/vRz/HjdJm9yRXwuPrczhdoH73kR4+Mt0+/ZaMZPgIigK+75vFcuZeQlcbNcytJx
Q4FJuwlGqYHOP9jg0c+k/4gpk5wJlbKIr9zndcW8BbrMZZ378q4JzdrPqz9CukBYhx+DOl3AyHg8
aX8VoIlb9MEcEN+XcPTm1d9nVErCHd4gsK+stw7hiYTRTAcIm+PmrpjV2ng7Usl3FYP47AZcusuL
nHWFvd62D1boNiLq9Ogg2FpT0Dux2DvmO/JvaEcXHy/+iRntXfvttnlBxuFr1M0QKygngQjhUOzH
S/KvzLCCkkc24SOmFmfMlI4fFzAjDZ9m+1J3qBww64TF8zeqn3pQfCQ8k5lP4O0FoXfvq6fJQXk8
t+CIuVX1nmeZXg7PC56iU62Esr3LWLqI+WWNHWgXZi7/Sx61rT6UOo2vK4DwmVKlsOm/ZNAILo5r
Y5FCuWxcrCCyOE2tH9OviHZH44oBtdRijFrploECqYep0upqYjva5sGjhR86m0EUfz7YFICxDJI7
f1FOI/6qQApozQRWrL8U2Daomu06onIKpRXE+HKVm0JxlDUILIqLJ5DJ4S5M59dx4rly2KaZ0pfn
TIvWpMvnmUrGQk1mjFnr5obTyYsed+4MPGVsJ8MoM4YCRUy3Pn8xcJPiW00ub0u1jMVnHTmUyM0U
SEqKybquhG3z2GZJw/NvCl24Ih9qi8Moc/6lWJGjvPIzDhVHCpiYxjMpopAIbEPSGkk3bxDDRZg+
VZu3KjAUDHAJ0LJXd9yzLO7je1JnkKx9OyczlIqWzKICRkVHwuPT/1198pFwCQBPD2FgAZvnl0Q5
BJFDfEhIu25tPj6GZnoB9KssGGU4/wh1xEYotOYv9N+GR/8eAr9ZFBlRPIRbZDQ+gC8n2H1timna
JwjGYwtzCBI1f0B4IAjH8EtnFl8O77/PUBnx/u0k6N1FeBuJkNqs9I33TjpeOv0x7pklTgUmWVwN
F27IYsUzplR+zQoMyOvTlHdCQaZixODXUiquwYpbCccfAtJhif+GyW+wnxUjPG046ACFbubXqOFK
tkHMXqxSh2zawoNr+3u3OJ8e4EDrsOjRJilSAWLLUfpGhFvQkIQ2E3s0lv1BdyQFB+DKsnW6jeIO
tmSq7nGyGB0Ew6W/EKwNIG52Z6Y+DmTiLaLsyKbr2NbG7AmZuoGDid0TwkW/SfSNT546h3ZlqlN4
U5oyox3GZ6rggSiPEoC63I6c6AsieGwV3T1B7t9JeU6yAwvzP6ehNuOaWobQsPhVqr6jvD1NE1Zb
Vt3oMtjhQ3879mWCPnx3aDm40Lpr1jGjJZ+zdklhIfFjVs3GsPbfLfMF6yY19Fk54m+5/BlzHnrf
RkXXOs4gqDYu8pKOl9+FeoYZgji+yvwagJdp63xHKZs9zG1vRiL7CyMV2YdOWvTI/Y1zePtpiLOL
AnC5bvTQ+cT3kCBb6Nhr+pOMktOGwTCndpmuaEdXrScykyAq8EcaXPDkdBOmIo7eqno6W5UFZAQr
nuEKZsSTT6wkKVXxR3UD8bP4Whb71eYOUnRgH95QLMfmm5HHYo+AJJ4MglHG5kgSob3uITIEA8ZD
qAh7JZQCFVFXl4PuQnnNuNveKFy4X3WE7EwtO7l5RQrHZptu08NCh/tWSFP/pYAwpG8+4R2/qZRu
3KULxOswCH5VZCE5VA1Q7okkeNSPmkccESQ/D1h3cX8X5IWX8s5WuHeBOkFRzEAA2cQM0NKciA5G
s3eOmEwRO809t6N0aym2/xucsbepBLb1jarK26fGIUVWbkg1+/NJ0MLTDz7lhTX8pvvNU9KQnFIg
p0LRn/b/CASUnSwCDPE7EOsHpyE7vROgHJDlL/5fpvYM/AJJcUk8O7/WOVzs/dj90L8d4jR+MMev
oCD1S1iu5N9U319oUKm3/IyFBlfI/3PlSeyv2C2mB8gDUK374WurXVTuFL5XLVap1sm7ocyNjFmI
rTB4yZIasgQMNzJreta95qYp70B7nVD/EZrnm7vSdzxPslmCdy7pOMFz4iJWX0+YUYPlZqC5t66M
uTxyBErssjdFDDEmSNXqB3bZneVrWtB2nk4H0CTuxcMnxrtddr0BahZ1EBH1my36aAim45r4rPTh
jUy2NAjaWoxyUBW0H7vCiQwcPb67KLQ2pdwyDKPLOlcu2SYLCy6sy8zI+Ar9UbIpSGHki57PI73h
24SW5Dn+67HYFThmOAMARVIS0gaO2VBW9eeKrYJCdQd6KTRR+/VDHSx7wwoaCU6PlDVWO6udVIWB
+pnAhS2FeSv5+ECVGqgtJdLr1LqihAoeCzdH8SrHtkIwksjcbGEyKTUImKX6ij8Mrk6z+7LK4FNY
Cm/396NOUW7vnevtYwnmp9ER0vB69+CbCI41PnS22ZrZcF0Kuk34btaXaumly2YYgzYNKUdmZGx6
MaMi5N3WO1CirJfItERjv8ykbJ5jyWlBVY/ITE5ZzKzTYggQwDIeBtOVscMjznQoeUCooqEmlNmn
5yNMy6PUqGeOjQYO6iFL/DsThpWQ5j6GMfedpOyYtS95vtSTN/4OE4kZMApO8XEWKkMv597o0gUR
gyC3sSbtb9kNDiqySgoXPHjjEnRp+lcJaWsdw74Jc1Bcf+QzCmusvLKfXogK7rjA3cXzrDUy6S2K
+aH9gVB5/4oVV8tuS8ruP1vVAeGFdVzurGxsXNUlrxYHFwH77JPZonqq4J625LiYpfoLCOhlMOXS
fcDKSY8NcCb30SCgh6ekcurBNiSI4g+b4HcP+bbiMjSBZ2A3BppyDlS7jGG1WWQyFfIc3ZKT1jAV
03aEpMIxcTs4GLNYp4bI7U1rVei7eTlwXsUaHVkABcanAs4P1xP63Sk17CF1zzEBi2ZyXNXM4D04
M5nBJEnZLh0d5iranudVUzKB+5z0VVUj1a5JupS2ITrWWv2RGLqoS3nvJA38xdp3oS2DAFkyQybx
gCOGWGqcFJ1Q/DYhVc/A4HbfjZiGHJ2B9ynIOYHK5LRajxNkom3iaP8rXqpSlhGMdxf6bvnYt7Sv
pUHCfX2q1qOHm0GtgOSNp9Jt1FZi/LHX7FoqF4fy50vbLpvzKFXAvx97K2t46z28U0x6bLBDl5mZ
IKq2TGqKyDKf/x1+1iq5ISGtkWgdqEd5718Gi6TxqwG0J2lgI7MHm6SceyfQ/5mqBzZGOqxwo+8n
F9LNL87KSF0zNDEShQL8yLI2k8i19spPYGWw4nQx++YwZZhoOFMlOs30Hzb/hkGg9TRowFD+PzyS
JEMUEL9Hjy2pMd9KRRzwTs2+DwKbjvRRALSbHJvQDJqZf6TpDgSnJhZuGf98hTo5oimdABKjyUaf
hDvTUpFp13xKII/it3ywM72tI3cwJBCl4hkKmVOcJegPlfPNk1xYayCFM2HxzWiZdv5wQzNVh1/Z
C5M4PA56CsQ5wLYuiEanMb5b35zzHF+IlvuZAnP7CjNuapjc3aScFM5y8bSogGrRa5DpnbWLStKN
QzMnF8R9d3c9bA/Z0KjJhlIldxSOged4MSH1aFXEffKYpDcUKws5ck+BZziQZsCFRoakvWb1QMd4
QjGu42kN22CuJ0WKvSsv8yn+LFCfflGqrf2SsresFH33ZfWsWg7iIYBcMbmQULmVJKCqUtxPgc4h
JpGKhVrk2DcqWdnoF9Sk6Zy/n5xldyKwZBCsrUylOeHxvV6xHPdyJ6kSLANq3Q8j/5ulRSljAKrt
HBlK9vosz2ptcNtYO5XunsPVQCz7kdG6WWqdI7z3zqX1zDDctY/kToKGyTSO6kEjr+dV7jqp66UE
XDzDzi5RwaJnf2P9m3Y+5Ic/OHWmLNDpX45j9lr1NlApC4IudcLQRnO7Jausn2PrIgKKfu/vV52y
eJ4eSw+6fpXfddInRs/ZhM8xjaEFxUUbPI1zG2tlhiyhwlG1X1w3LROfIzJz/R5TPZAFHbRVE+m5
MuSdovr/I9KKbCoCnstkcJFNgjwF/VxCLN3TP/HzvrR64BKc94LrwLcHhKyNcIUR76yqUZltg3+e
f29XW69K8ANGwCJsm1dnECSOaGrbAocqRVRs+fn+1hzqYcwKg1/m7u4tEkj0xskllC/oIVznuX6m
2EM4s71bHZmYD1CClo0XD0cgVmPzUYJLaXLUxyWk5CPfHTAk/dUa+k8iviJWgdrPdGWJTpji0gP0
W9IAsYtQZQoAK8ZTGcR1gfJKrgKyzweWrWPmzTDH6OwL9U02Ua+8cULu3WPJ2qiCZQ/JZJJyQ7Xj
/sas5qEA1r7o8+3QHGbGXSmdhy9XfvxpDrmjSvzhr6pwQ7bAWp5f+Yp/x/5jVklJ6ss89AxHJQV0
mhf2+z5baHg8MZw4OB6wjr6fStXgvY3ZIFa9arTOAF38V33xT1T7QrWy54k10oNwcnp2wHg15I41
WRD8Y4nY06+AgYe7mwobaFA3klGpC291HcL2S8o/jhPt9QE9hJY5vOLz71zwfI84IgM2IsREQkE0
9eR8SONTSqOihBtj8RAQckgoapywLhIcqotC0UdRXL7ensvjBISMsCGhxUQ1m4W0XSHe5ggazVQ8
TS2AK//8HUcRIDHpzgki5dohu1AQGo/AmlxxWW+XjX3Pu/aStNs5dGifMRj5gfiw+ozHeGZ99fbU
eaGPFulCxvLBh7MRc8fyyX+y+q09yR/kAwuYYVb7dg/dhZe+0A/+b4uins0UH0/xGu9Gt6eNnh3G
eAXlMevpeC80YpLDLrU3e8KZMRMu7wmM9FrYSK8/rDVbHk4ftYmYV4GvP0erjB9ze+nwc7FhcCVk
voLdZdgt49UHdvDpRhaS4QuBec6QbJ/2i6hY2uCjV1XRu0vd1mGFUU1QaBRyHMy2GgSz5vWtoy2M
TGyhz01LvTLZK53HUdV8NkDxt1dkK/hglZqjnWlCKYB/yqPkBD/vBS3wEtLoeYqhOkUgIReRJXJv
Q0Ad4KLQNJNlBdxDZ+AEnZfpxgpw25pDXg6S0J6weogLKqVFp5Y6ZNCr+TVOnhH4xw8EvbNbCTgy
U3Q6+5+3uLRXav+otperHvhcVZxgJWVQQTsgE4Ih/loGiZoFKoOXFfvSRu66mfnUkHOix2q0u/ft
ueIfExMVRkX2wIn6Kj0Jvc3Mjd1x6yD4klBSnDQW9Nc0AO4BcE+dL1AYePXiM19Sp+2mENJx5T69
dpGEcWk+uoqFVCu2/8ZJx1JUzevi7yeIJySfqCR+jyrvGxOi/8S5zPzOYIhD8I8epjfuFt2+C69Q
atXzpKfCPAvgTGxjdAQvktPOaFGD5yk3tJDOOoMIKmNgL+qSMmJHIDAuBWXz51LbVzRT1e5OZ38c
2g+yGgTY42+LVk+Rno7rzepHltiMOo2NP5QazChlQCFy3QqlpXPrK6LaNJUYibVrKanTmWUKGnrl
L7J/i1UgJt9/wsvYNtkivD5bePvAjOKkW255iO6g1sbkMxRb++ddNaA0RSHJxtZk+OIF8L2/1A+p
rtXLu9d6aLiHys6yo0+QQfiNMlx7l1hcVXamTTM0vC1OJ0M0m7UcDL4xqmnACgwh67cCJiQpW6UD
/PxVne7JtJjwqDayhQIb36eTkhl4TiekpN94vml1pAorOgxafhIh1Mmrjyl9Og65j05hwIkibVlb
DtVjpnwFE9oS1tzUaf+sTtLI+p7PEPdiFcOqeDwgJScDMkJbtQD496dMGr/U5irIYG3YkGaKt4lp
13zMeUWBBHoLGnvqH/bMLqCEmreM0U64E3pKxClgXGlFVXnkZjTFBRKxClX018c3yURJ8fzn3Kgn
qaghaEt/llNm8G1k9vfiVULg3IxScRGU9VEr1NwT0h9HAktFYxCIxmSsdouioBTzM/QMsHQEzXAA
MSAUfzvF8YssPaFpa4U5jejNCP8p6iY2ebbKWYMjSwt4puE3NucUqWyKWp/+E10YTyWmwapihk6S
mH7U+zXZ01kF8hedpdKDxDacj5mdoN251BBwCS2XDy5M7iI4V5QG7AO55m569ItzfMJAY8ZXCJr8
oq4CsIFGu2PvRVIuzTa7QoBxHUfcvZVtHmVqfe4qrdUQiyYS/Xnb7bVRNSfr5h9Chrr2oLnk38HJ
viBNb4GQpvvY18UxQbCaH/XAj+v8hDTCCAj37mJ+Znk7OCT+6gpSGqv55510SclssMuRw+ZssF9w
k6U6xdfNODvrdWYDDrvZ7B1uDjeif9EFwWEABPh++HzEcKYTmLOiaZQmPN10GwCcDBohpyKnmH8T
QB8T5gbiz+cR3rFiZS44t6vmQ8QxXw96UuIT8HClWFy1cYu7rU3M4J7okns+4f4XzuN7NTnmMzVa
xksd+pdN2267f79/bGa818uXdjWqKmAJmZOLs9D8KJZfEMCvL4YdSzG87Tnr6xZR3ab3BpD9kmeY
kYlNg//waoTy7E6i9FbdOoLrgJWarAMnf4f2uxPwkORKOA5hJucyqJku8qfD2BCYhIpy3t+f+3V/
wMorT+JjhqO6rgqpNp56zlBLl73Tz4NJldJ4nE3yqi0UimrwhApfc04vpf5lKrF5vKOPQV8czla5
ZpqXWDTkUKp0NsGeTHZlNPwx2Sp7d1+ZXH7sLjuTh3vFpTCXs6GsTAAQfzJ92PvSCak2nXhP2OEZ
/OJ/AZZ78Lix45Or5awmWdgO0jyh2BJvOHk4E4FoQ+IiLsLIgDM+Pa68xNwk4IpWWwDVHs9nxnih
LYgEJ+pBwkNl6l+60Y9WM5lFLjkFu7zlRdxfUOZrwteyK20Q9fVi8DNC/3py+YTUs5VWpuR6HlSt
Rk4YQXCj1YJVKvwtJ7FljtVKcBfx6JMigFv3JjlQteDWQFmaNbD1RK2mfk78R00SerMag7DJpzDA
4DLrsz0+N9IlH2Wm2188nvV9wnWgAchTAK5JLTWJ/7GLqGGaglq4xhYi4DFN7TVWOZ+BHZ/DFy7n
z1BheLim5RVszkPVuxeqcOIut2wrfoa7+bfUzuaS+nEkqSv9bc+Y4Z26qG0kfnXpcHrC+trr8GLp
rYqzZbTn21radvEamg9G6XdGRP7GFFNOXddKtusT9xrlvv1Pbnuf5u8MYkdcBYlh5IOZ+BRw5mZN
9eb3Vtkdf00B7fAFeX0V2EcM/c00appUkBJLpzvwO/8be/XysyasYjHdu1NBVglJ0imNZZeY6juV
PbG9IX4Iy1lIhtuFsLC+g8bck5Efg3mzMiMclZrNAJ0d5Z0xgEaJlcPzUV9ppo+Y+ISPPSCTOn3L
hBUDDi3locvVkCOLMc0/fVxDjGd/DG0AmkicQT6uVoQnh0sZWY4zIlG89DzjW7WpMNkcbp6Ajd2L
Vm0zEtWPFMmsGiz8svS9BRmBSAI4x4j90KdOUTCNCmhJWDIIBBsPsEyl8eeKjzNrcZBQrwgLSgwm
TeJguS13f+ri0STko+iRarlXSXDSh2RGtKV/tvcqOOBkIgSnUmkaxduidXNA6KDIt6eIQlAuwZc9
aBNSoqDbTQY7urwPFlbrde3iRzw5v2YDdb4re8xA6JN5NnX8TTmGKNFEK3gCEp6JJYe/PXx804aU
KDuscsUC/82P5Qaf3m1KDhNPh7LBamodMZ6o6ONd1xWqAEyrVKNdW693d+5FJq7xl6gIeR8AHynY
TyOy0Z8p5JG1zBw35yw4Tk18BBEuiVqCxHWY4b8E6rQb2A22Als7q8J/chxSCEvaxtvD2Louamoi
eJlsl0aHRqdI7+LIU4NxEW1BsvyFjCGwk+Efq1Gk1fSIqnoSS5JKBx18401qCQdYM39O884uQ0jW
Mkwu5LtrD+sFE6deNMZS8ht6AkHcSfOxGu6iDGCyydDjN70Dn+IdVJn89/L1U7/zPEbPgG52xLIq
Ef3Mlegv8mzg/BiNShdAdu9j8fGwxKVNQtovpLhbIJxMdPAMvZDKgLsohCqvtfw5SMH9FQ4kR1Er
+yu4E2qI1Ft4F986FtCZirp3Bz4VuAIlcfWvBrBS9j2L3MBdJ6OCzVhSiOEuqk3nJ399aRfv+isR
1c13CSXqWzIT428Mj3tpj5tVtwnv3O3ax9YhHm80SUgtDl9CnAmk1FFPDjRZN6rkhDrNaI0LqdCp
Lv3Iv5FIelKEKLt2xxm5fZLmqAmrkKvIEBCeL6TpTcuysvJ483oT/VE34U5j7UUC/aK7/iA0MnPD
ZzbO1WykDeddTn7qiG0xDe7bu1mlxv6ZNVxp4Q7dLXyuXoHFTECHdrYozk/vWOXF381+G0VJqI8Y
PIGPzaNRaFvEv0TMZLIzSRnf8fiT3zLOj9GOjzUkomI552qSMD6BiMTnncfj9UOlJqljftSsrOGm
vi+P9qw/xI/DnqZ+QjZzQmDBw2Oqs4+ldjn+zTk2n6BXSj/Xg3YEQ9YnZRsJOWKi8uZ7nKQ+RkHj
npev/3zcCpjdXQfcmQLJkP0cZjGilxUjgg8ZeND6TmttVDawkkrdlolLIOc+NU3wDF1VWvWZANCu
BgsrWmbEaVGqi3MZWSOe9zwC7eGlt1Ybltyd1NmJ5ybiI30kfGRwYENuDHM5guerTOWg4//ornbS
MvLx8frjJjJPwJJxDDShlTSGJOtYI59GvrciuIE5KeDPpD+wLEgW9DlLs6qRIMMDxjgm6ugDf3p1
dVMJDINusUaSEl+aCDggZFIomt5RbYclPmhtxDBpcGPKAFID3l60/LDmzgemlWSqnUg6r2vtZxut
hq31EksgJTaoFfdBaH7htpOMCuEZyXyxT+ktvIVy9lYDoS5xxDbL2NIIvtVXneCS4bs3X3sCFcQM
pdnjm+Y7+gxkuT96uc9FeAmXpMGzPZuWAPfySDxSxaY967U/VFXEJNJwj0LwxWX7erjnE1VQsccC
rUC4nUZNZmYq5SlkQVMvROOJ7OPJL4HknNUdLs4KYUqsDShGu2IpyodpLMg7/7wRc1LyimSnxXoh
jo+36ASss93bhOj02UofTI/YjOg+nCpMfq/cZbQeuH/IISsPza94ys5Xue9NyxQgLD5fur9grbRw
sxQJhP8QPrSbkAx79HlHYX73cWdLxwqyN/GaJhWTIZxNl1Y/wqt8+GcNR4UEKBjst3CV1XSrOqTp
DF7yfiFs5GXjudosqFraARLbPPiEY9YdUpeEJ1FYByvR+PV8IxLEhS0J87FkgLp+4kv3B1P8DT9y
1m0IK0b6EVRGMpxZrKUd+5nwc5uT9vY6O6wFfK5Iz6jMkKn3FKpEcHZu7CWwTD99ejdy3fDNlz+u
w8PwgIzA7gfGiwgvqnXG1jrwNoW5F2/23B6CafkUsmOaWY5j2vY3XofJOXfYQ8tv5KFO4waSrKhD
10G7w2+Mwl6hqfz1+lOghfsQgYuWPXjcQysiPTT6XZa9OS609kDDy/M9F4FM3dgySkmceDUE9uTh
DJXZy32NVOLKbCBEo5pkC3qDY8n79jLmiNAjcl5OsLKlMQvnyVgiMHDUAwJmwwWl60ZqLPNYkyAN
NU7yLKGMkJP/RRvlJeoI8MqzhZR+7IZsZD8XfIu+zS5u5rcrOzUHR5zZduNHNpDHy3AWDJHWBR++
Pa2d4RzdT8LNannK8xYlMIKUYgItJ7slJEXpg+md3tzDaK0aRXu6fg2K8krwiwZfR7xr48t2dAnr
I4TFMvD4pWN5s73PIsOmNCei3Ve8WQDr9n1KdMsyMs8aezwcH09wh39RUw3ubX5krzDRiXtm7cRQ
cGuY6r9m4vKFj3xsX2OuMBjtJiFo4J4LxHq9zzziZ0THKBE99PXYPlb4O/hdznaUp0BF16/jG81Q
dO58uI6W/vkd3h4hIBd0fQXRT1KO+a6dRlwRMzAlAAhh9H06iXdGiRsrmAvs4yaphrD5lfzL6GZH
Usd5oSWiRd6xZABdc2YABnhd//Mv51AOYkkl83yt1ziDTmJtbOKtq5KKEoS248oNQx5RiglRzRFO
cJa8y0++m09axz2o038WVOKhRwRRtDoSe0nTSee2GbrjipVqIjL3T6EOHyx8l0xEnWwSd/9p/Y2b
GgeY3bfdo89uzzv39S5FDhffFAiN9NMjIkWXLXzyvB7kRu3vGRYNrnVjvVzVRGmXEec+b1zLOJ0F
5Ahxgc9z9TfqBgN/ZtHj1dPPwrjUFa7h0phgHnnJSFsDCc3MpqqKwD0Phw73lWUfPSECo2MTRRCb
reO+g1cboCigyMqAqHl73rOMfz2NakKMo7xXtCv0VmVYcG5r9ExPWb+5Iyt39QI0F87hPKi/esFR
37+NDXWpgM1/E2qFqhsk/PM1d7y5O9KvDrEgQjFq77oJf5BZYbJc2dFEDz/PEPweOebNRpG9ovii
tT+BbH5EIc098wWedpAt1Go5X/MdK8USXifZsIUMwOe+Oj5gpSF0BhKbeGgKl6ocml6P1oMv1bEa
5OCOQC17nZLPc0ruXSqOui5//WJxV8SqkLdUdD5hyRnuZpGk5Wp7eU+qV1UWQxRJznKICMFFiGiJ
5jSdQloMCsurbasaHHuRMH+kIAvFDNMoEMRI4XGd0zpaeOgQdBOBVY2Irw5aynJQHj8PzW+iO2T5
T6aY8DBN3lvpBmdGSNUsHv3ZPkbOXhq/myDfo7Zr2NmgZawYdYAPvUsNHRcvmpAw5J6mkzbpAthf
HLs14XVToKEpEixNQ5if+YxOzaTYkirf5mrnCeP9FUT9f6AKQjnAVrJnkSETX8gAvXU8PEp2lcaz
1/3CzRhKrEz9eYYgin0TaaFEPkoffYV4fK37WCXW+HyS+Sh2vAyjqq+IrOyUj4w9IeSyiECQwP2W
DC6U5Xl8VX+fIWoavSJ/ALb/SZe+JOPFUpk382ar0hzpDkF5dp62GKOnq29ZDUYvwacnMVgxEC+3
jRqcjrCwFn/4RdYGQhCSFRSoe6b6nAm29/VTo+aOTr9U/4m5pB87pEnCQAG24LE7uoLXlXeWorIz
h87DSgqK2/7pU42QG1gxpaE4u1NfvpGh66gAb1/pzYT/RTA2RkdwjopxovYvdipTXUQIH6dqt/90
ZCdLSfljXH8XvKPmpO/j/GYVm3+CMRAfYeTAlklyRpsfL1crYFA4p1eBM29e4pBBBIbdH28LQyxX
t0Qmc/FiPsMtpbORhC84KwRw9sE0gj/As/UGIuDCkhdWPbO5SVhsNwRq8cwAvtlKEPY9wecVf8O2
o2tgTNagkLMvTbZRF91uZ9XD//3CozlKpg9iKYdGxM8/3u+k9Hh91neWgzRHMkJ48QQF/aka+yd5
ULnpg6q0S7pS0zhphZEjeEozk4T9h9rVju5Z0YlkNFgLNznY0zkjGSxFumTSgsMmYxZ0IJ/t2GTC
0yX9cMb4whMADHHQou0Z8hLzA7XOX5Bok+/fdhqtcwU+HiAnWd0MuWZm4uI8Nj4SrHFpj7kCu7t0
1HAHmm0I5f7q9wSXyusg2jNEjPpDKWn5RVAtyBZHk+2i18QgoZGyVhBQ6EJoDdQaUmz86YaiqMQB
f6qTeVPrQghjsw9xMutMbW3qEeHph0wxJ+T30gNll4xislR7N2dVkzFMhQf3OShMnH7G6CzqSuVW
yNRLNkr+CUnTS4XbjGgMKvuCttmAj1PvumlaNmu/T4y1AgvkLw6bRQX8Iw8nSSIynAVRUi4vyDKr
Xo0hWsEWZuvOKQr5+jtidU9r+IbFgldvbsV37hGcVTVU9J9pcX8cp6l7XCuH6ik6f5/faq4mWAdF
T8563asgElFJ7agsY8XfyAe0Xe7X31MzWqGlo+PtfiYYvqRFkKJ9zO7KU+NKePH6Gk6fCyUtRJQs
JnEH0L4KSigNBgwTfvS2y8xMTyjABrhAewwaL/jbWUX5lB/K2YhYAE39chLUVrK2vJMhCpYVjdzR
k5F63HERfI/NnWxHtith0+IefIH2WBApjVVA8L3GUSxtsruoH17q4kEnMlm5E3161y/8qifKW77c
QZDHL4oeT7PXIVrotLwJj2PqHACQCORBpH51+OVc1fV0uo9MgE1SUzb/YtilJKQ7XUHyCuIdLTR2
sBB2n+X7+IAfO+3Fti7rs19KY3GIs3bpkBiipL1Oav7kHL6kDSpgWEVyUCZoFmtrKCTTi6q4uKKj
1dqQduoYsTJIOa2GCeBmUZYldANKwJdx4YNIwB8UnIqorK5H4MAs4hFraD4UIOIjOAepqkQNr3fs
nOQfkjUcRXmaMFQTSTGyKgq1PFY5MZUn1Wk79qbpZnZFaRDdp6zkAHchMh1pXFkmaHAKeg2YddNx
eMa/jpj+SNiPhPrO7vE3V98XT40wFhkTSt6SeitI5vDcjXYR7KwRpwnOxsRTLdoTiCSvAkEDVyRt
1K8lB3aeQmvi4C8DaqyWwNy+KysGW+esPe052qerq/ZN4TCEyPkhSclgvFSlLchLVBcocogodT7O
EO7dwdFnQv6vd6uN+E1gmXMy6y469osJ0slQKI3eSy6ff5y4oJ2sOvW+CVl9lE1nCukL01uMnmbY
glzGearHGOajoIJQ26hGcrQgjdk4Qij4uxmDaklb9ORiB/u6CzyVlUNHiJeu+TkBpj7431tcyS9Z
59XD6PX5uqGnIL+PZ07cv5iDT5Pe92KaqbpbxlYmBOsOjWGvStsInk7djvBROMvnz2G6zHoSuzlm
0sbKHjJIAF/ptJT4Egay4MRSa9jqhHGClYjk80+ITadnQzQWyYWcBfWAK3M5m2S1egsB3ekCCimg
U4eMYyhl2ji1g1OdOsqh3dtQNLgO2uhszJaMttnQrjqGAcs43TIZIFSo+OY7bKw4o3bpwn4favPP
RNies/4GHuAkU3jpR2h5BueHSYLZMta7zqa0MhBjd6NNDDn0WmiuVdZc363G881Hjrf3qwcLx4+r
ZixAlz3rL2Eilec8wRlKtSO4vMZ2/biPJEu8Fc/ePAjjHCzcdVDIyXLeuTfSJs4cR0yjqfI9juCV
P8vMA00oYOoCocwhqrBAdq/lVXr59fsus3oVkX4Ga97ilapdguXvzR7uhayHxBaaaht74NILRAbT
WQ2r6z/DH4cFkpbX8UU5TU/9sHfPprueZmr7K2vLu5TeSc9NcOqSEvh7SpfP6MEa6Yl/j/mnDYzT
kaEvzt+4ZhWrWRCMGqqd9cj/mgsXgPAZKPETk48lvf+Qkgm8v2nN1PLc3+WbeIhuzXOBHdeSydSd
YCLooWJGMRLZOpKgsKFlNOL/0p+cgFk5DmTp9v3ZcqfCHf5QunrVauh+E+SHDzhHtPSPya4Di1N/
pD62/e5JoFg3ugdzyxv13UcrahL1S5qP3zN+Oz+CPEMdj1+2G4Vibk+tegcPoM4BXPAyNPx6RVO0
hLdsqku4bNQbG1QiEqH2BuMnuHtm9IjsePZFX+njPgJupqN+mTQwLOP/cTzx+B/d3BxaWPEunrNr
QESwQ3n7nd8E/P2uGN0eONm832lAOwq162JUtkACngBfufn/irPaVZVg2Uu7Kt6PB4yutPLhXb2K
4jwX3sPmxMdRbzTctKz51M2+COw/FyyGQKbzKbpw+8oDSafImn8Oq2R0BHnXLziWQkjIvrOQS0H3
fJFbrTognX4c2+2B/yPXcTgcw9Nqty+jZApbJaG/Sf9DNTydqESizsehfSt5shoSB8gxWLQZYPOe
caLWIr9Blq1EMypokfgALk+6xeGlLhSbmFUVMC2oS3iRzvBR0BaFzPg0wL4y/srF6E4GvnzfF8tM
3w8A6Hcji06ufeF7duWek2NAhCcmI/LWzNnLUOd1b+pq/QoEwdViDa3Tq0wWQR59fyOUg0IZncFg
d0NuqXT02Ur0lGETR9o1B7jn6Nq+Hb+SeHePyykIOkRLUFIgsaVXVjmyDPgHcpoA3UCb0MV5rIuq
mFkqftirT9uhYRIGkpHG4htZW8t8LIbBlqHcLCc8NjpvO9WfzPxrw5I3ikkb5+w3EG9OwFyXAxq7
ddGDrUNTuPTSVdLoqivWqffu9Grs1sr9aJKHuvqcLkfUsO0meREBBxJCjivlXFFDtohpdVBpjuv6
vc8QiwrLYr8CGIxL4NnbnPWFfv6g6N0le0/qSu75fWyIVQcNKoh9RsAb0b8DqqGoVQaPxKCK7VKV
s/9PV6JMvX0YTKoif4oPidriqfPLGq0WInMYf6utOSI8SlCFUX1zuuK2LX6+bmzQFDbuuZWYlVeb
xgLx32dIRaxAGPn7Qa/PzrsNH8b50L8AUxt8tUW4g5OXw70TafYVVxCurq1AR2MmsnbrU/ItdEc/
wiEhffLQtWXqoYY0apU7qiMQvlKVr3gUNcoMNXH+ZIWZRpp/h6z+nTbrggj3R+qMk7nyO9a+UcB/
tm5PtK9GLXYE9sfG/98C8dmYucZKT50hf6o2Pp9IoflzSr/AhFLVD0KDronK3ZuW/ge75YP9xyFY
LUMkSLldFmsaJEkY/IRmB7fYLedJnWbZyZ39ZNmh4RCnDMuqMKTHYgjW3EYGC36iV+OGGFzh4QLJ
krKOjP8llOw5e8qM4+dILoVbCDG5yvENqomAS737JRZcE6AGvcsiydyDD+RHC30bx3XVSi1vBDGg
Eyw0xZ4sC08QGqM/zc0R7qwxAsbR/E2y8nSFftIyo1EW7ieBNivALcuBCzAjKXt2cUg6MT2Ny7/Z
D1Gl1iPBoV5Z7pwCKF6m9HgK7Z0VaDkvedlSqgswvBUDNpW4Gv00ivGNkp2pm80MYiwDtKpa5yma
7OKluiszd5msMS3iBIM4KARHKwBM6kumngWP1cCNCYNCtmiTWWFQDQyODuPu2ezmfXp8BPCIW9ZO
QEnZZzgNZwGs3A7JQSCRJr5gR2A9v+DS5fEDMhGSL0rMPbSbVu7rGs/Uo3o4SPTyWnxc2o0XWPgG
plaNccrWPr+OeCbv0tKW+Tn8ijRUAS7heTt644a9P4CtmuWZOflCPMKm/a5umwFoUXBtmuqkX5Z+
86Fk1UckOIw5gD4QqjBbvvMLYHkNaOGeJoj87QXVsJUvWJjKK26L4K8fu5tfoTs8/0NbMOl5u35v
UYS5D+UdhbS16x9SWeJhxWDT29nZAMBdemmcXslK5ZiqhHx5voICwZrG1cVpBx0fvqG6nLV/is4n
iyTbNUD4G2MvUW0xTij+Sz25smofsmLQBSpfqDFscCsd+vN34ZAZBmAOFXGORa0UQCAZXFVdfY+k
O/POOqYav+tWi0V7hlLETd59kBNW/N1XqYl7HxagX/zKbGaVmGaseNnj9AGlmN8dN9RHQAG3PB//
MRbW1w8VSlw6NhQmDiqLhbpeAcoS/hj6QK8uBe27U9Hmi20jNXpQ6348rWOOr4guMtKR8L4xhlIL
PvHWaC1uyKtEyE3v+AW7K6KIyb1Ljum9GP/OBbu4d8Za6zOFrKeJLG2Br/MubC/HZjyDWVuiPfnE
FTr7NvtCJRLlz+DqtyOpWzkeIhQq6jVwmxVkpQBS6+SBxm7qePB84uRpQX2UNpx4Bi/w+OYhZLGR
App7sx+KTzCEJ3wH4tScyNDwIjgYVFmXIaAUQf2itxS6rSj6K7SWnphoerdXjTns4oVYvXznuwQY
6CMlDR5JWZie2cgmEVWzhq3t/mEfjbw0PsFTv2uAd9ESujlmzBPVCPN2IqijfJKIJv/IjbXOWh4p
nSICS6uTMz1rLg9D6bnxkabQl4mBxRk5vUk6XFw66uToSZFIIki8nG/NnlRFG4NOyBm6f0l+6YNX
g9FdpddT6TqTxHICW+7GS71anW6rz2Oz3Iw3nI1oXHV5ZWXygPlIGRsY4IVEy4kvDdf3syimeaqr
80qPmgfoZIfQvBPcM+eQj6p8Rng4i076HmE84SpNkExYlTZAgGKO6MWigtfIjI9xR8S/un912b4D
iliVkfQSgT/lnLOzHMkOaOiKIIttj+BDD0eDf7hNJ+fpcT8VK2ucGafqTdv730kwIBqCJl3iGM2J
e7eBNvxNuvSiy92gPj4bm5xg7rOnzoYVILZqV3ksEtxTcfa8vpzCNXgCuTYU5mDTf5Iyooc4Q48d
aJ31aixzJZYGe4M764lGdat/xjIIZKhqkonqhCRIQo74hh0svBnVGhyeIlOKgE63WvWZUB52MzCT
n12kxzq65lCBdXiUM/RRoOUJpWmKu0DweXY0YuqmggFTMMtJf1vbBSgytSiWsh73r83BMh2EMQ04
uaIuxeVAsH0pPhFAWpyynoUeHUYAf6v6QV9jveoGuYaTk2N5TAxz52ymzWyna+eV83yXKf5Omt6Y
46gI5ImOYhfi+UIOlaEFYrYMrTCMv5a2YbMLk7Kt8Hg1FQXKUZr/8qAbj7RNznzcnTC+xttpJ83j
hyd6npYLBJrrTcjnmType7BOwVPQUI6+Y3lHOQ5hSX0w5atzImS3VOEQmNviLlfa9LZRCVuRiYXQ
Z7ZWbOXignlLo0JxZtqHtyMUGYdf9vXvKK7cbGPQzPMM2l8QLh7nwBPiGj/5lus6o2S1CDTZQq+r
hCXvOnAp/9y/uEMuNlVfdX3HhTjhFRvswx/KdFdjBCVvJ+PLaqkRzPTjKJzyJ++TPeimlCg3Yj9j
k5ayvSM4I1dxuw4FkwS5LFEEZQY5f6H14oxlEUPwJAQHNDSN1GQ32mabc4gl2R2+wU4WKwVDTs3m
zLM7NDCPa8ozDjmtRc2JO5MpZXZd3BZJXXyHkuOc8IRjwrVi/1aBs30WA8ePNOxw1obhXq9ZGRIu
4vNo4UzxhVKzOJwwj7UN4NLLBn+U4uPpS94KSV0S/HmzA+lpQwVRg546hKEwPSVtSCpNGrdqw2N+
ZgWL4LZCeLb1JJVyFu1BfRFPwyWdMtiLEr0zC8IPi2WYvNbw9+XRplEB610T4xycgOv9tsCqfUKb
0gZcounqL33aDez3JMDMajKud1TbO+XnIPePLxKOCueX2sX7qUIOnxdVq+0SrhCdYCXmgcEcAKBx
m+1vQIudqCXvLfHoLZsJoHsG1MOMgnbs2l6J9qQj9M/5wzjiXslnSxYKaCIDFRVmw65MjtfPs2tq
DQyZUR8oNh1xRhTEFf1oG/9PNNsR5JgMpIvVyx9VeVLcCWm7H2CTi2onoaGzQ40W4381d5FdvEnm
Y/PhlVaOj4uYyZt0AqIiUNC7NEL445Jh7sKLyWEWOmzT87Kke1kmG5aWsmNKq8pRocNVfnzfGJ1Q
VgPBlceWuL6Iili/MDWRcHrRXGRDiUURaMJjXhoR5/aUaYrkfUOQqHKqA5EjmqfGwpIICZS4Vhsj
5Oj2HvG5YPAR6Qgbrd+d9cMa5ml4jLgY1j1PCHPHT3VEzIH50Z1fHLmN0kFfdO+5HoZnaeXme1kM
EYPTI3WaViNsYur6Mjc6uOxLockOvicWsjORdv7h8t27AqUEETmkeZvOnmhxt+F4RkDkMI+XxuLX
sbCIqYGkhq2/OtQyhtpFygztdvzj6wcickO3wu5fuVNfzdKiM+XysEr9k2qT+zu8574Y1M4t6UvT
VzftBA3wxmbi92Opzw9BfhMiqsflr07jV5C0b/G4Y5a2Yza9M4O4OjXk3R6iAujvrQpoj/iwp3vS
hG9749NwEltGw8Hs2cZ72k6qB9sHJ8UQT4AKryeN3akv3yp+wf6vl1NlUUet6KnFXnW4c+mdVgH9
34fpdDCcITKvpgjOyhKCHZLkJWvQNNYuAKC1X57LK/SLezkzZGp3/iDi6IQw6Y4IDdKneiAleTCK
LMleK9eicbt41IgfnHlnDQTXomksKJrzubmYSiS4l5lGXvqP2aNn/hp+j7wa71z3XhoIgkHxn2Uq
G8Sw08p6wyM2RDn/sLOuz7D5uDkKtTrDeKBULFRHreuXztc8j4K/c/L22qmL5wXUfOO777XRZFBB
I95ZDmJy1ArmUqzx9vopmd496uhoIRTMgT9zIVC0R6zqry+2QPbxbikk5SvjYhuHLdslo06VxIcV
+sjj6m2SJkY5Y1pSgicaCHhEambTJ1Qbb3hqWWMN1amAx4mvKzjn7uR1wK/jXpmWITpMh+cxzPu7
DgQf4/XmfrlMTnmlguaqsW3GmLK47Lq9bectls8Vgkdzxf4CadpK1gm41aalxEa7+aSiAzJ5Lfpo
UvwwQGKt5n+GJvxlpmIVTsCIUWLNL44NEYF/iQElsGoTfHzcgTuVRyC14A1YZf8XJuTTMOY5oPz5
rNiMefv3evBw1I/QFZmLC9fJQDXRiOvHIFpjxoqWW1dSYx78ezwOy+P/97QA97YDLWh+Ia/fTsLv
/2UT9vF1YIvw9TJNKlyv736R5HnnYV4she+5AiURVpL1CAfoKGL+/XLPgooxLiWiSC16eVA1F8Vm
pywad4iwW0laPjVijBLWEplnPQspVGvl69Q7/7V/tld+94NYsNJseKrab9Uyw0IQf1Hpp7sPaWBJ
iHqW7c+2VU1P8l5M2XdmY7FC9+8iZxllY8TafXFY9Oq37haso9BSoPNl4jpJElZGNoUFzrJo7gR7
IDJXysrs45hVtiF8rw2yaE/0XMUaeQiwaIskrE7DqLQBjKz4p8cVm5D+dFbNvWbabEGqbtDFeVIV
HGhRTVcvLOcyXbzGVCZpFCf2bhDQjsDqI6XUOdIX4aSP1OXYCCOCX3CB3EiEjumYyb0lkeGd2F8f
kwAzbPp/NbFz+9YgfkgStdTaRPGS6vXxqWfiarQomg5W0lOLplXyVStAUCrnnn/1ogEyQHMFefRc
lizcZLSH18ZimUSO48d4kKaKlsU2RtRZGZc8/oeVzTNMeODCWIrLhlQSJ+m2zF4RyrbePX5R9FVN
I02XQ2v3lAuVuncE3BSF6eqAajkeqXiOVRcL8vBOjDSfS65hVuURSGhpL6etV9tjgQUnkqxxyYdW
CoCXSip8v/QwJiyKuGIdomAS4PDOY0Z9LSufwcUn4bicIcImH2Ai/lLHEgxZXZ/DxxbbepdfUVH7
s/wnlROgCD/6qyhMY3cqbOx35g++gNfQjdO8mzlYOjhjWgoiHuHTAuqbUYK/htruJ87zXAo1f9wF
mx7rIdje2vrDgcrSyAGwFm9dtJa+qXgEh19Y8d2KjI9DOasdrGWeExLupNL807UkDeTx57lhngiQ
h4q1zvlv/Kp1A6ivNiJI8OZq622sd9NP674IofcOZ0jpYJ3cnTQzESFEoOS7ODPI1MaNTRkqLJqA
4WUpBHyXpILjwbYchEY6zpxFyY5ms8OQ2OWtwabIZzpWCFViGDnfMLwQcegWYlZ2jz/z9hIddjnQ
b859QGdor5451GMhqNVDtvaJGRYOG30OQOGB/oLJtU3KNmk/fnK2ln+gUVAuXg8FPYNwFoYdW89y
2TzKfkBivtmdDL3gV6R+rxtjk2F27RPmSCQcU/QZnA9BV5kinIV8nnZNw038ZYmQa2yrahiifmpO
AeLqterowo/pT57rE0A6Ce4Glx58tiJEZIWZUmRXuyCM7qdjWsPdIn75KpmJjMZxKno1Mnf9sRpO
iZ2UszxcGRj1/QLjYfYUlRbIo5DWVtEiEWqZQyhrXTGNDmkR7lD4Q7qzWr274Rr4Uwj2oHDuwnHi
32K9Tw6JLBZ9jq28gLgAu/QbDpmwoUXm/hmlu/jCl+o7UP/KWM7r4bZ5Jhi3/h/Gow44Kn88w4qq
Zoc1rQyLIH/+FtZDLohyRH75Hnansnba+j3AtnQtYqOfQA5pKO7LrsAejxLFGU7DkibwUEvQqYVa
eM+2anBXZpotHCI+2Xyw4iRwRUuaRY+xCUHNEK/KapM7HfAjk7ftQZrKynj5mqgtJBsrTfkFP8Um
CWCAcuFMY6Ke5xkV5Re0Zp7MV2WO3vnn+AX+iOYeNXInP2HawWAo2AGKMMci+87BYFJ66rciWD5W
eizpXyw/eHVdOxj0bwHsWmMP28dx3eG4Qn+S/hgfufF2YF7bERg1G5cj37pr05SePvzAWw40Unu2
w+6NEOGJThVThiABF5I7f7NzFwNXo0VWK8vvRyOND4yxewuZ9RoO1mjCkeZrXjpA2EMc6fOfMSAK
mdf8bX/fITrcuDoAl1CzDw3sE46+Tc1I1hke/w6bc52DmfnQLwOuCQrG0+jWhqnX9b9T91s2EL0N
0r8pAVvWAHPaxdQIL8fTLoxdZA5cf12dvaUfLwf0DsNMczuCbSUjMA0PChzcxy/klLnZwRSaaPs/
FlvZMTh7Zc+TQs6Cj/HMh01xj5+D8zXZhhV3Ob/mSdl8I+5hfQznyN3MbmPGubVYP95YtAZe1TxD
I65q1ha1sw+igaTHvDX0pjV+lWmOsG70qYTMv2xyS/XILTG+JvktboBvz0LcfKpzfJICLnkDa9a1
1w+JLJq5sIH9VQGhREBNYGEXqumG5GvxhaFZSSD9xcD09t7r+8r3V6VeyCzEBVhKVmBW3uRmIlAT
cNXdcowMVV9aFh+8110XGjFlo42dKdairvmMy7lk2Pfc5YWEY2i276N7gc/emPwk6G7FJ7Kqbwk9
9LUouWZoCRx/KjfL6JHJYzC4y73pAkzWsL+Tur/iHozQt3QvnP50D4enhGOjVUkqbQr9UJ5vOSj/
UjPZhY3cTrv73/s16ACWULt0elQdSW3mUbeSO8VygE5vwN27l6rUw/8UZ9dpDLZVIi1uhC6dAt6k
uSzR4BJ5WTATax6gDpKJ8hKa/C/81WE/lqGwTvrdb2dmBoD2QHWZRefqMGktBpHi25xO6VU3UG2b
cfwLH5WdUH7yJ2BA8GASb6Vk7JM9m2C/cXZx540Rubv42XKwrBifP5Zw+D3dixxaenuWFycLKy22
hQx8Vtiho70Rx8c8ldEzvBd4vfVu51jIQcqfFdMvMv/bDUwRwaiHv7pmEWvqvbpCfV9p0ug6vd3d
KnG+qmA7CQWzcaq/1VufWPfaSwfBH542O9D6ZBI1h7FlJYgrQ683AR7J0Q/7KOlAgOy5C5USaJB7
V7TqvE0mYBMQ90pQ6dOOdzJ3rTXMRTYGbhxCNq4ZNU96oKsjHwtVNxp+9rRuSLHfNchQCO/BMaWF
6mb0bTzyf+kBPqC7gGkqeUegGzPiTVgsPBEE8FDly1nPwodVlFF7VwKbM9wXMQ9+l3Av2vBOrT1J
6KJEiw9Rl6g6NN1GYQr2/3/nLIsWJL39bpXNUeUAu18ieMAMePlHlNSk/ZhD/IeNF4v4N52v23on
pR5mYcnlT7F3T+Ib7MtvXyZqw7viofQbnP1a4IvSRwlardJ2R5tPzwzypd7+ATcYNxrv7tHdy2oW
TZzZvtQqGfJNCuzYi+jIp8Qenn6uV/JpEE/0OGz0ZBock/fl6BRIFKfhQmzFTo6+RdHJcfIf2HVA
2dYkAVdcBQngT/MbZmpXKWEx6pcVSXskh249Q8WIv07szDh5uciFD4zMgG9+DtBPczQcyV6gSvp/
1Okugu6LEQ0v1tgTSUQRFV4xs8nEa34jY5OECGtfieWV4WKabQ5gecQrh3Kl/k2O9VmLVCy4k/Nr
KMzHlg8JPE/QSNjgUl+IcYzzYSiuV3kV0CiTm+WdfMl7kpHyYX8t63kiU2p2Gici2FOZAZDmfnzr
3sUFma98lOca5vKVOKWHTlcoWMea4hfUlhjeP7cSFr6GJ/Ey3KRNv9PymqH10VhqxXFNTWKiRk4o
yRim7ujUxDn4w+luKz5fmWFKCHu5Z90INh5WpNGr+vDB2GpjT+8obbbQvwk4qFcXC32vwIwcTcYy
R/r/+/o/trK2y6v1ZXDHsa/PZFnnhM3c1bf+JwX/nWFJlbLx6+pri87ICuCPAFVj3piReO4h4mwp
qoNW7UkexyeCJXLSf+HH7LbJeG0gPX9rgsaqdG2qq0DRYnUfKC4ZU9BQjVsTr/dx2Z8Kv6b5ELTL
T+Ax7a7A63nSaB3JdEWot7SIdBSfN03Gxsy5A6V61RpPNtvEd/cyxLS3sV09gYDPv2MywvKySErU
8QMyN+9JcBWj4qM02xXehzf7jHOGoY9xrhhCWI3s42cq14D1ViRPKx3RTk7GfuTl9ZAlk9YgC119
5xRcV08E8zBOeJqcbj7bhq9hhoOPKi8LrGI77ONhdrHzTMRSuM7f3s4zhZMTW6U9QJU4qyYhsqxs
AZlvNn5BOAhdG39cYBkePp7uqqsw+ZCFy2/8IrkeXShPlvcsE5tHqMGQnaUGgvaPqpDIsIlqCrmQ
yg3N4BUGKECuluVPq+4C2INcRXp6kyYHwOYFx9oZjXkg+Z2UBMTVNyvEBIgNlDdDawXKYykMUxGh
KofXuOg1AEPowzsXVkv/DiMZaBQkRBGNq7r0pIShKd05k0AsE6uvLe3HPUtDFwQPMH92LnSdRvaT
N5bO0IG9FRLAPg6nOkh4Ux1RWUS+e/1DOTFlKgMxmKXrzGKsWQt0iaFx8t+gbbRF3wl7gI37aSI0
a6conuYbOP46zWiClp+0rgjsTuZNYvIRIX4naQa+EM8TdQIS+iqhDvbfeYVVt+DAvWvIQaF12YhE
bHPgKhaxhdQEPH9DwO4BBJzjYm0FyTMQ1zfYiqG9GK3Am/rpDXJOf7S0xLHmH8f8aom23bm6JRBD
pjeYnHNwLRRwGbqINhtlMD8GSODfmn/MwJgjmMsTtN2vNuLqvpzl1sT0VZDL6EP2x4x+yjIfSqb6
ESTWM6XHooyQGquXTuWQ60KljQqsPie6BhgjZlSEhNXZmkCudSrP/dbeM5+0gVNJ19B7aMPjTlWM
cuFU6meImhx/cdFVUTauBhvy6sF2x1d8Emwx2nVbOjqJ2oWeuc977Ef/LwKBKmCoJpxdGOe88crS
DnLwjCLCbi6S5v14QWjhQ6n2Vs835cDDpT2ehLnC7rQtDRyMOuEfZOyRZDu1ZHSAKrCc5y1rZd7B
Ey8dqAMdixvjlVbZKttVITGN3OB1stqdaMywUNZ82liy+lmiPnlm3QqmCUmHy6s1ouslLOpBDrHG
KIzdNfPBVVWT7C7laNQJPKwhIzBxMVSXPctFIClPSTS/8Dz5NAkTYFf9Eaux+GblvQhlOeC+WG/z
L4z0/GJ2GfRYTbUnDft4UdOm9K5KQEL7w8q4K0wVknUp+vepqtoTunIy/rWZBySQnvso4ymRPurL
jEO2lM5IcFA4hSvhW80cJKt/p6yiE2Fr8vGVxGvvjk3Hr4gOv92PFxHj17Jguvs1hcgdb9r09KCy
J2ZaAmhYBylUZxRb2otgEyEimXm4Gs4szZBICmgxKFdrKHTfOXOcKyq5fez7dlv5d95cpd6eIwk4
Ooxx2OqsdPcuNerZkV7qWJATq/TpIAfQEedCKNaNWJuNFzm8IgsI0H6Rah5bR9+VfDGPF8KtwFOU
/F0r5D5v7UuYrSP650hyT2P9vXSEygNxIr03mhKmgvpjIOKDxwgwcocvCh5AWUgiBxKS/qDFsJjH
xVvxFSdN3hppDO3mad9pAWMJaegCOL6fF7utVKTZZuExWC/SH+d7eaXdGAXxE2guNlC8oF3+M1gi
A9rQZHBz/WS03GfafDf0lFuOH3oylaoWbq9oNgJC7qzo5jXLD7Sx/g5G3FEwFIcJP725RfKlBiJZ
BO0Wu0WU9KNsZgIb2HayMer/I75fbpP927qRzbnEzsBMy4a0qqslGGteavWCZ60IjX16o5rXXQ+c
3PNz/WVPnYJD3Si2R02IWSj1bTKrQu0Y6s1DGrGjVEP737V3xPUzIEmakWXMziH/jTI1m3ZBPPmk
6J4P7ZNyefezYcV/hy+/D3BNONrkMgu2gC+UOvfLvsPnA5etfijDj3hQ6YzWYE4RzdCV4gXXkhyo
AOeYsstiJc6yfdGjSfxqEPkYrk1TgitvivQQ1Hot5ovK++h3bICIFaVV5QzHk7WrTenW1KAZeOF+
F1t6aY6I48o6psiDldfT97QZD2GvjpV8bFhXLjMOxQoTm04ZpClbPjTNKFuF/qsVb32lAQiQ5asO
4NyXHCYBXWZpoaNo8SiQ63QPNDvmv5xpnpm0ruHwuPEk1jA17cXP0tl7jD/iVSQslaQD1Ccgd3d/
9yTL2em5R5Tijd3Rhj1piQOLNRXS97xcFx7Da4vN8RwKJ7ujbsOW9LoeA18BRWxMqMewi5tlqXJx
qUAgMj6q5ERkStDpMblI4KMict8JIaXyUDF+zI2dhyrjOj1wS50hrHVZ3Ns3j08ClncK/xCFLfOe
faFlaSpg8XqaymQdonLVQmp/ucPg1BKbdU2ruN0uy2qyU2hHWl7B3IfPqTALwPDa4CK9BY4OEZOh
cEZD/ZVdCDGls0tmqYwg7RpmkA2PGLixABWZnjMZsGC5PH4UhLvkJR8FqU/8fSkl3ZFArJbN3mbU
jcAsjg4sbbkDBLJlRft0Wuj1fJSa8b/BQ+5xYiEsQHWZeZpLsgfQdwfHH7YUnFduRQAfqbPmiGBw
oUok2KtQRA1PlV+f3m4Pkizh5kXNW7rQGHjtal5gu3POzogG9eToi42w0oa4dOgqwQckPBO+dazS
x1HwrjZJsL0tHFfk5NRIcVFbhGDDbLoANa7RQgXK3cC6Kz0AwAAvLJvH0i5ln9P3WFuTemPKjUIi
Mk+0r+9ffDfA/M7MamdncYtNdNxjX2fgscrJkFwaBu4HqgR4zrjgrj27aONO/bDHkHrykonJQV1M
EqyQwvQf0wCliEryLie3O714DKkKYhXsVj0dmfxDDrQ2L200KXMW21/ccDsDUJntGQVGxS3dG05S
4x682lP5NpJdEr79sWRzmx3rpiSclmHS8/qO/IjEkBsN6P9B2fl8h/IWjaKhQ2zjSGVpFoJUceal
1QwT8uFxC4c7g2Ioe3d6273aQQi7Kphe9GThKC29cNtmdJnBXVPrse3eeFV06dO7yxNjcU0sdJ0F
Rh3KtXyJ+Iu3lHOEsQF7vyVnx4Pkg7PHA20taXcM3jEKnzANZK3Ujf0JhQzAFM4N9VHq0GqqCS/f
oI1AyxJjEqcd5jdBq2pjqx18S71/VOwQ1nHZ/xACqcPme+XoafgRGVqZkbeMmvJKs8HoDTf8vjiH
4XL/MZlvGyw4F30cv8VJDlpBaBCRcIqkrCmUSeyft5TiLMeZwkpeg9AvorYcmC3koXJCUf7W3kFB
8Hwak7ZDv71v3H+E0LeLedHH+9Shg3SpgPDyJA3HgxKMTUcZBe2gp/pO8pmQlvnBwsY4wi6RdfgZ
Y7x+9uykqxvKUrH1jQUIG5gl3C56VFKSgJKX/SxpmeAJZFSViMXWyS2f+1v+tqYypnmQDrs6K+KB
ky9Q+0Y3U+t3a91W1hjJZS5bd6FYG+CdS6m4JfmhyG5sVCMHV4tSM/CLUC8sHK9V69ImzqjBVd1c
Qlrob5leoPXYvS9WFHqNYYn51Ijy1J3H4xAJ1xAu3m3zi0h6ITnI8ZU1jMeqsDKaYTA0RzOe4S0q
aup8MfGlWMJCUnH0JBex0Xyqw1t3MMV9/Nm9Y5GGFNlE3yXDAA+6UvX4ujB+Oj1eD9A8aJ+tqYxi
+LYlLDLREJPGmaoCoYpUhEqPFgtjGsDoJ+U/7fxB5iIBvUlihnV2Kh0+YJ2zMmlS2tWMrKLh2A7Q
IUNMAZA0t1FzrV2RPFv1hpBLbFbJXd+Jus2rmwCBjGLmuTiRzzxlHxmoq9Y5UKZ8R61EBHmtg9hs
h+RaagjjNXaRzSi1vVu+nzlLmqfpWYhnJ61EzxVeg6JZYLC5WByHPK+2zUwRtMc8KLMml50u1kB+
k+fw2f4AzwHPSS9UhoW8+93PV6Zg0ayIGA1qCt+M4VJwhCtH7aLVRFm9K3/uHCOyFxHQeLzrSilP
r8/H8/7J1Iqu2cE0rfF8BtTGMoZLvhLf3ePrxanHjFWb3BXVkAGbymsuinODRC2xoyn/2ajSyVlR
tLkQxnlRl2Kwenwkh9+XPguRmj1P6u4kEKrSPTJSsN+Yqonfpi9/aulgJWasisZWwOPNZ3BfTEsI
gM5cyer/YiEzf88PSw2/5ZgIZQKJtOHuVTIPHMqhBGNAS9eTgvPf9O2rnH+Gypo7AMKb8sjUERON
Srs/44YAlix3ZdBh7cfSfVkxxM9uBL02lL9C5QI8OBBQ3ahcpUnZsKIx1nBp/wIkGVbPIpv61owG
bmePdvuwr+zMlDD6apxGdBvKNxe5xdt251UzRY2peu94OwfqZTFHdGzP4sJRiOsGaLPHkffa7cqH
zqnrd0mQ9O4PcmAmAdz+kGVz5X4tBOwOAZ8j/5wQS0f6NQsIk7sqC4d7fyJGxz9FEHmUFq9N9Nw6
9rgtZrDUS8nDludolyu61FicjtVdyW8ur/f8EXXcZK0Kh1JE9Uh/+NnsqLeaALgSIhaW8db3uMbt
QsFOwud/D7PFTiM+juA4y+2bpR+gsk5Am0dZ+zsayNeqBllHeNc0zyvQB49ig4djk5uiSdhKvwHH
K1+zVrIM3w4N/bYtvBLOmqi6vuvLaCT8yF3yeu5r4GrjhURxGGj7AkT7uXF1kL5QqUCTvWIP8Yz5
OYsJaU1NNuFU1gK8kaIlsrOmYJijWvcgCxinuxSwfg1Zw3U3VI5HzBCgEK+Iey1T58BrPvTs9lbj
hSVF9Ts5CYSTgpvT5M75OmKyrPTwFMZx15qevr60w5evWzYBCZCUfuxhf2lFkSowLvm2j20fcBYI
1mhgDEvXvwRryVca4LAVSlG2TblPbJ+Y9QxKpFMoUfRFW5Zz8sb8YkSWjNDaT9Bc300rQMPGOXMS
d4t2lklBXawwm2ryh0FlDJFU6WdgWLJTE57PwFHqgIK2EySUHLdFYkwPvf4VIa2KH0ODdVIb/geN
foQd7tVYqenyfpL8g13bGtN3J9d+4mffl6tMWzAWoIc6Z+w+wChGpzg9NYEAF+PVHuvoQ8RtH8le
meIVxTWs4jYl5A4ueiRe/oD3tu9BOLeRrFgfwUpcboIrFeMZvy1QSHruItHHfeJK2/0aWfpIzVrB
Q/dat0aaXYlW9RTE9nm23tPdYPzb4U3ji9B+6shzTcoXN7/RbSdFat27sqJyC1g++vNVBzd9acQx
nqeHMOPvSBNE7nLzDelSpvxXjArjBqGp3f9Q4OvlJ/s9kU/WnmpVT+Xjntmv/EYJo4AJcjhtQNmX
w0jj30ErTG15CYA96ZMP7zmowlOEFIvVQpu3OT60yShmqd9cTokNHVZ1vKDYhBLnBrKGgCd7H8RO
70UwoP8I/zcPRUWkBr2yCWyxtyFD68cT0rYe6Fxwkm67e/aAcN6IamtuYjq4DPORjiqfD1JPFGUP
EwccP0ruiwDSKEFaj/SlZtP0iV5dFPnk5ANT9U2EZ4raaIydK37ywFgr/X7n9juLaLixM27PFwNO
pEOsh3h0MmgFXW35hwaLv4gmB3pTxypnuxJT2xOU6mZBZ6ep6UebTCqZsl5IokNMCgQUnk1iXsLn
mhlzmOGycaOBhiGc7LzAXjfF1Nwlxrwy7hxzykKhzGaqgk3jGTWYW+bargcEKz9QUTI+W4mSKi2a
S0ymFEetlhe0cq4dpCON7bjGVFhgbpvxZw2J4Dx8u1OEd+7dp3BoYBJhrH5d480dHuotPP6sJ43p
ENZ8ilnw7HQnqbvFDe/EJe7gZ9NLyLSwmenvGCn3gZudokCApvB91Kqk+wXaRDzFCx2/z6Fae/Q/
AbUs4heic0rUpPOF4tlPZrWvN/tA4g3EntNUUDQqFLpUnw8nFhkH+0mSim1ZG+baPjqLXd/Rxn1B
hYc/bj2j77j31G9QDvPkyP90FPQ3iND92JIUJ1CA6Jou29Fxa+r0mO3fet1RE44e+yRZuA2cMtxT
i8IorWoa3e9/4KTxbcTazQWHsFwuUT3CHuEGEfKj6wRx34C5CzbeUUuIwGPNFQCpCriRmRSPp7Au
T0N/qVOJoC2dzqRrs1Y/mZsWjgQG2AI0AkZgj+OP2fpf3mvo+5TYs9toM/SXfwqql7JqxLVP4UF+
4IYap5a55qxNyHiR/VjnGDNEKfVWlddyKvu15lpJvtppKu6ZCzqIL8owyvjIVB0jdX2xP6bRl7Wl
gOSc7/9CxW/uDStvNn62AWWmU7qNqmCp3qvgCj27wDaFv+SXmNJKHT9xFBKau0F0m6jcCr0SK2np
TM/laMShTWzzT/Eca/xpjkCWHky6HYwGP/PYHGDX9MQ4r39bbM2f8y1NgkL3kPBAwavlBJ9xLLec
lEtmE2LXbR0qlXm4B2lh4rhSYk6EnVpBNLrgE0TsL0Awzlesm0X3Kahe0R3qvakMPCpwu0l+kuJ+
C0wciPvgVdTFvm7duLdcISObGHdybIP+uI0QEoBo374GF6ZRsdWgfRCq0CeW2NN1BGqzRdVOy+TB
8wn8egqc5JXInOAOsSXmp4wN7VZgcr+Q4cZId/XzE3pOqQqvYOWY/vUKBvcrvrdq9rTlGoYeHeAj
4wsDmUIpbHVIJ2lW3zbiUXnIqyM9O1MmFcTeRsPeRy4CSVOfamkj9mW1Tsz8IiA3tWQvlPcYCkvu
b5OD1HyQ/KesfVDnp9JIE2c4zbjbN8hISeZ4V5DSf0yPxPn/TWTgSVPPIumud2BMonrI82m7Sob4
IfnFjbsfb9UK0xrlPqpHTgKh/g5Zh5a32TAHc4QxxzwJBbXXI9GJ1StNVKauRlSIGHSqBlhmLax3
3hCQ6PyLagEnOXo//EXs8ULMDILtzxeCSUpP0WwxgnIhJrRISlEj7p2gRBR9jFX9VWXUrmmZbVPy
vedkUgcBEiUrA/Ulylik2ISUET5xZnjT2vflmoJBQHnfEUm/gEgJbt39AYnQXiykAxCvm2YVSdmg
b3KFaElA9O/pe1gL+lqoGVtbQ8uqWoYiFtRs2JJNHvjAId+/4JOlCjyQcYTHV+I95GuMvTSSrGEf
ygzNMU3SrLNIJruE83brmmXHMPRMmUVtqh8wUlSdJbjW29vyZTX6Ew7ZdYyRasLgn/55RMySu6eK
yRlrZzwV6LrL/sVCvfh0ARDtBK6y8+SsWUGPDB4Ko8cgwtH2Bt0AS//BqgaTVpAJn2xnsw2+UZbn
+bnW42cT5FsZ3ds5RdWrzhsakP7DIWB5fbYQRsd0Ze+xLA11zlOHrxd7phxDITquggqoSYQ9vpaz
7bTeAV6wfl+czDlFCJXShezCu6WTC0jcuLWkRL1cPb3Sb8N3cQ681SirW51ZsA/eYpeJQk0X7tuL
zDMROeT50a2lWhqSHKzGWHff0SSqCG5Hh20jGTuW0bNHgm6/IAUmtAhcsPkiEEP3mLuhSOFLUSDs
A+IZHeu/JY4KRn61I7dO2+Doj2m8GF0Pob9X4+3qsaWOJ3+ulQyI5j06/OOB7TObgbV6nMc5V7b7
r/GBce1snANZ9w1OsI62/LaaX+nhgA1/ADBF4kxIB2SV2MfLGF9F4UgrY7KAFZi9htNr/VlhIC5l
WTr72BQDeuEY3XEBCRdGlI+h1DgGkLhvwZVvKzeh9BYz81ySmIrz0PpOaj7i0ApXdo7Oa85B1LUE
gLPsNvGBnL96s89NlDand+KnNnE6EgpHQ5GZA4yNt+azBKkcinkbd3vAYAYANw5K528pG5/yijom
HkUynXHxl86mb9iLwjKmux3IKYmuigJ6hSq3lQJz8/a14DHxsREwe/bOt+DWmpXAnCTDY2f9IlCb
5zvsnIEamQPfZeA6z10fjx+hTtpuWeY8OsOpBjBj5SS7+KMY3Mp/NIZv/WzCP80h+lthnzzVzDkK
UdrHRQ994OpBgRLj35wTbbXrCOLkpP6DvYqdjd7m8WzdRX/OXHRA5mVVTKIlQ849eCihYYg+4VpM
2nIFN0qbjobkhFaS7bwaLXt3IqF08VC0TTSgBocbGVg8+Sef3Gy/9XSw6uWODHeNx0E/LW2Tx6B5
Tu9kEq7BRr+ACGNFbZsDIzCmAH6Oaou53k4Fqz5CoO0JfnxaXoE1BQXwnwwS135H6XgNA9bB9rCg
9fZFjoDtQr2fgk8T/x+RflnfqsaXgN40TZmFDqs3/3f0W2cqoHTy8WlXBA4o6U5k+1RkFrUGUev0
dc6dSmvL45Wx9tVVZYok/9QWCv+vpSOVSIDUlEaFwYVezax+andkVn9WqNM8nIbHfcYorMKQbVrd
O7RBkGNHdd6lFEzTw2KZuMoDQrvAWgLaXKzCUggo4SvX+0ZhyQYfk7P3khXFzSP0mUkPe1PLxlzJ
XRoueeOcIyNO+TYhXwbXDxB+/6x5qOBaMnS8cHb8Ik5iDHoP9LBRcDYMXv00o3wA27+Xm+iYMB0s
VHf0G9vcWjnvEB/lNwQhTluUJKFfK360hBHgPaV7/BsGQ2hOdRlJtNzES0B/V6JjlWVo/ojIyjMM
pcAuZqJasqZRAbyf5rDWY+JAPadpKbMaEQEF9ynFKXpKQkGo/N7UCfcYmLtl4LdMx+fRDVPL17RO
+lbmIFyA5hGAAHWj3sq8am+nGBFOanJsyJ8KUxxo2eNTY0C4RUpS4vNplOZs60MkYp9gyeyiIX7K
A/b/YiuQiLScZnVZ+IREj5KNNZanRW3ZbtNH0I3dFf9C1Bs6ZeQXhzc6aTV73YsEctj+FRc/VwOp
a5F0yyplNVwQr4URICJ4VXhiy9uaS8VY4xj3sgG9IjJUsFIkYB4cPKuX6yxto24TIvVIxPitB5oL
B3z3PJvcXal19QrR4tUPgMEW9b53L5LJoJVc+3YU3wSnmv/8sA7EUyW/AxOYXuY5O/dZbC12614N
UdbktQPW5plc9qtXjrWJqTl1HusbQowVOg+hEDMGECH7XlxB8ZZHkqe+CVIVo1Yqgwr6CQyPVogs
/+pWwTlglLnw0jCNoScraKSVIWt/KC5cXJbJs+9zxUrQ8qKnQqaQqjPJHE5H6nBIRjRzvSy3L9F4
T+bSk8M7CNPTlHW/ysI5euSQg6gtmjWHz9e6xfqIFtDmYVs2kytXAe7Loku6fKIrEYxeCSZYYR/N
sxyOeie7JCI0FaO4+ONuVQetNEHkZYIMtc8IFPj/tjyGaS99oTlY15BOhh578/a849NkMHnZ1Q5i
48Um4i6EoDm+EjwwzUGjLV7sIKnnGPjwRsSqo54u9voT2dGeb5+i1h4Ft8xwDma3XkFeBEpD4L5o
mYuI28R4KW0gltSyIvBBSOpaEnFyrHf0AqwkhIcjOQ2fwkOChFfNdyU5LL96D2jBgIwoaNwJjXCf
m7XCnSJNz2WxTdvaLUpTjvA8Q24WjBO6mVtjM3jCkIRPeMlrI/ey6mhG+irKTdfPROaXt+8zUEkQ
0SIZgWBU/nDh6zfKu7HaAhFu+ZAN2ssTiJpt3dWtFvkvauFhEEU74J36UvSIq+60ghOXBqqvjgze
gdari5bZYX+cHmMR5u9avgVCelpAWGbNvoXeDXXwgXzLXEZjxn2MH0t7ZOqz6iLahzRXihZRzXKs
2RmBLGZ5MhOZjqEeZ38EzpzBHrpWIZQzdQvbdnLpSybCi4V0c50ZA5U9cjK+QSf0DKSsEpwepg7g
ZbOzuVc1S7VqI1RonGhCzDO5od9BvV7XX03m5pOAR1ZbfVwinYJtLh+DxgXFl+1ep590zNdFdXFp
s3fd/M9kyBeuPOP1Xs3wU27LhS63n3pekl+YbsiIDwPwb5oEyJU6XCotNKpTUkC4y/W2CP4qF3S3
QFNhKyS7EyQVU2m79Y2FW8IioNH12b3LTVQrflO7f74VByn+HdyCES4/pIJEB8Kb26MKZ0qZ96dV
0rNOa1FeG2ov2FzdzSjJNpfD5tlbLzd1vX2SNcUcpnWYgmtAQdK/m/izhjb4lf6JCXD4a0kymVZF
Sn5xrYitLUSlR/9dLUpMq/ngHMMJMm1OYbHNoh9SwALMfir2wqrBpG9OwpOKCAIo+XSASayhMtRs
0MZMQTXVPEKWx3fYwpqAw3AeCGn1YZRuLzbcANwWymG4V5qThlEWg05iCW0aSawXiHbR+SGanIve
wfcEkrgqQCGFdM4C5JfqB3gtm7hR2K8gFqZNpBbA5ya/QfEZeAdZgwVEVcQ2UO3EbEXIThKljrb4
L82y1m3zs0o3o/rTDV4LZPaRUCz4RixJmq/uRj79MP6w0gWYd5IXQbSa1XYL4mOSa4gNsRwapa6X
BFNBCVbMAgPSdaprofbTh6U0kuXZ8yBod+4CRzNrRYbnPIqYH8I2+n5JHOaKhUq3t3CUjQ62TrkT
E5tBzYg7JK09wsihjicjQcrh13wBa+JcH6XPPUzb9nHJvOdGCe0BLPcZcXaeVMdHeXAyH2g8MUQC
NkKYEav1uckYOs3zAKiQxxGdFNFFX4DUR5xFLEFH6QoPosA9D8p68YWrn/rlDLQXzBu9zSIw4Z2C
sqIyJ+ayR6hOLQFZDBFmFxP5BGXQR1GkN2chOcpIVf4b2jXyzzuKFEITKiQAUvlA3IU+nkSblmIg
YhEcOv0RHBHl6is2paU9QkgYJABwbCzlMO8wilYMC7fLu4CwseJjcviRY/1IXi+6LodojFK4qU21
PpJzQPPukJye3KXyeHyhnENbtK7j0fdXSNdYJfB7ZWIfNhT3MpFvx6qa8d8sIPsO5QzjvGcsQyeF
iBw9iMOLC3gfhTyOk1g1cBile98AfU6PSRsnh9HPWBGEaSZ/ryaJOSB+ODUaE9jbJAcFHVMw8kXt
nQ6S6WcpNibk/UU9q7Colny3dOnqulKmwNcy2LND/flZAtZfx0FymBOw/gizdd9YgtnPYbjr3qRR
eU988TZbvsWtuto+0ERVrgBvGqVVTb3cnmYbXmfxhUQFAmR1ut5jv4HJlhbWeRl5R2yEzU1iktj6
ItBAWdG5JYRgsU7FJsh+L+hiAC31u13H+uAOunkAifyuhdYKQ/SZNJsCrpOCGJL3ikk+z6EriqGi
cRxUFIyZqmHtfzD63gQXuykGhYprHp4CM1MUQ0V+dAisFOnQcqFt0Ny7mmLfQYRsPX9f+bzfqfmx
jn6MBs/3RAHGiKEagIn2vF6/c2rzfny5pVVTdPYPL0Ybsjsfmdn/BuzT+//uz3cAICbJwf1aQddh
MRpVoS1eCGW83siMlqu7PmrSyyT68BeIPlHHl7NGPN8gAi2g0STiZ95IAVzkAsNQrGZy5VGDbyTs
wsunyNHqMacv1EDr+8+ioVs4yE+aMvJSmNc/VKY+GCr7O0VSAMblTUPycBWqodCagfb83GQ2P7yy
s4WXMtK6vf0v9NXv6yQHn8cWydAlCEzUAFVAZ8F2X+8N5vdw4AOHZ9NyvBbe6LZ+8wNnGifEDf5J
/Zrc7uH21Zd7tGHQhnWNaHl/wb7HVyZjrwadfZoP0PC2OL6E+5HQJXSm2R/4tErRUrjwsaMbdowq
R4StaV2e+yq7P2ZSb0BeFP8i0j0RmtGX33z1fIvMdXxeZ5zdQZ3CkIASj1n2kSh/FKaIwvXH7hU7
J/mQm2KJvVPV+sErhwNcBN6Np8X2prEZaPgKDFNr7EgppH6Q1h1fu8km0JIFJTnttZbjyTAIvYAw
mchBfCvGbuX3JixCu9IiSdvXew5EdpgshFoT1P+KWSDZo3Uqhw8Lv0D7CZyV0e5Gyc+QlT9lh+jL
4eA6dF/RTLuZJ5NuYH2c4h5UR4Y/s2poONJjmtQFcYcYAlC1t0p9LF4gvH0XwQpEvD6dIHHQkz8+
u2qw+TCNHObvGv+JN8mIItsjuExFCud2IgQVgT6Bi5OKUUhCg4UqYvMWj9Q+MFOa37wmAo6727hq
8OotC1s1f2yqbqi9hhWtPI1LXd/N/gag8fJb34GI7uziRo+KGz1iPnYRjW0nnuee1PL+LTWxwFP9
apja5rxyt7xmeDdUBMq8oT52uJyHntRbTQsD/JQiYiPu4rdfBjjDtFKFO0kv40ZUM0cJg83ckrqi
Aj9WeT6cNPPJbqA/+vVO+T0lg25mv6uXEHNWUtuE8/7H2Gb5ZxtnDwqgFeNvCCBPNXTJ3mo1zs4T
uubZaczv9Nn73MCrQeVl7klHvNGYYuIaQIks1m0na5pHw32/QEk12A/uaiggn2RVGZy4YvsvQ281
ZEL2zKHi557pgbcbv0Tehx9VOO/4B0l2VdVjzZbnAKNrupRBnm8OhBlor3wQhRA9wFBqZmRIHcxp
dIJ92wxHl4af63cqqYuGhNJ2Yj9dQg7yVZTh2e8fS1lyIzgAlPDk4Qxwq7h0RVjY/zLkVVHN0h/U
+x3qFX0c4c5GznHw1MRBUKzlLB9GZdXtrl+4p4E5zf1nWXafTNR5Em8nxzAPO7djCdHV1fgnqY+o
WuFDl2ZjOyJ80b+se0QJ01XmUGX29KRzs6vIROOhL0iXPNgB5Fpsv/LSTX36k+bq7rlK5JqVku1x
mpSb69YJKO1wZLA6KdIQ5G9VQkhHiAmJvOSJWyo7gTgtYYzNHF+6uRcO0uU6FL91Tr4dR+1kWcLY
+z45I4Faoj/2oxy42alCNeONHAdP4vkObqJbpZhQa320DYXq72IeKeqduutR2CkabciK4lgBzQay
SAJHL1aSDX3dIz6GD4DbGYiD3Sr03nfMeEtB1kU5ALHTvv52A0hJvcuXcPIhIMMrduzCwlEro1+L
5FeUpyUBt8l/jeSq60sWysXfdBQgtEixozC/RWWHM2eOu7C1DoXGwf1T8a1iDAXzhbMxvS3HJW2t
24CzyURMjNY8rt8bA0hT0uIP+Fz4bHlC3gBlQl+wKKWmXFfrR9dzS+uN6g92CQjI+0I1X4LH3KPO
wp11ERtIyby54U1lN9A/W3UkMIOMNfgRTosxQKfZy/jPDTDkl/gax2tcFh0TblgFej/yohgWwWGV
ZBBrbYJ9bd0PshLjV9qC1dIaGZDR5YbDr6IedgZVs5slIm5Q9ZnniMEo9sYRlcSC/V1LkoZw+38o
/zI/CReNrSr4iTjqI6mJehvArLxidjG7ypkaDVDU9WvyB9uFxYnmYcq8RtyHFBBJ/aI4AUrQFBmk
fkt+D2PUtPb/57w4pLTs108pJaPXR7t7v0jOiJB94A3T+e3IjPeOq9t3qdkBm4VkByXfkj1ieyy+
x1kZwO+KSAf4kzB4aX5z8wPl+I8EnJGzW+iLa3+J9cIMA9/NvVzsLSwZQ2DWC+6IuKRf2/RI3wzx
sZvSHucatflInVeUvh23z2cKc5jUn9tj3fdzmVxOPE8JkUi4dTPgA0o6njgrfDpcbG5FB3U3lgFI
YlsMCf4b/7uvwIw6fLqHpLhMR5i+8RUpA6cwXPifus3H5q8jLyjU8Ubq3jJQO/L0k32Rm8uMt9js
4dZTxGWk//0I4pSeArm9UxQzvW8KD6sWUmYAz6hJGCRsVyKdhJSTdw9doVI0sWYWtidyY+uvRt8N
LtXZ/Kof3LXpCK1o8kC6/F6TpW5xhNqX3kwGGddlY8ONQRfwv0XUF4qvB8chPc/spIqVAKLwqsU4
CqahAJyi1hUmyhk7tTH5jfvAd0h7l54HeR5OgdUtpwbXmHI5HfZKeDTK5xXCImjT59/4bp7sHZD3
ZdntyBit2a/oGQzvpvEgc6koNS/hzaVE7MFH3UabhU24WE1/FwyTYW4nSx5tPkS9nzhpmimfWBqe
MO/mF0/AkQq76oqsTX/zR9ibMvXKDc8Yy8OkMHhrWohQbYhmechkjpv5UZ2eJL0LAC6Y+rN94fpK
vhnCKvJb122Zs3euJ37nQwJNXrDPEOoHTn92xyc2p+L+v+hmCAwMePhIJgcUMxCpo10F54sKwQt5
10fqSOI8+xg/1a0QZ4rvF3HVpcGAspON8AabBfoQqAU3djmgdRT0ysxMW73q41ROilRgJSZpESxY
CIbBfEw1zS7fP+VbnnyUicEm6EeTqFBGQq0fnz8AtBf+XiDY70Tk+lSCb60zg3lF0L6GA61hn1AS
Mo9fE051rmfKPjOoakD8GgDQqLxGep0aovKLRabvd068HOgecYkRaZU17mKMRKLc1pJYciFeZ3zj
qH40gnUr6WKY3AX1Jn+Kh0QLHmV+A/ONh+yPBUbxgiUW720X/xwFpCkjaxJCbxidLeB97zpmiVeZ
GqFRzo3o8bdyU9pK+SOMVoKPJ9eVEjTiQ1Tmwlm1ryB0QdEX9RgmGwZMx1j+UC483l2F+fWosJkP
i9G5Aed1NMKLH2top/dMwOmsBBA0Lkz4NQ/dk4R6SCDpCNFYFQ3lNs4ahSJ1lx7QOyIzjacGgfHx
nkp9oq276R978GcHmNuXVzkSR7tJJbE/RdRhr+4V4ZEzAgNMorsLJfwMykFqlrfrlzLPlFRChR5i
wpK6tNFXrp/twR7/HYv2qmTNruFVXdGjB6qsoMe2naptmj2nyRTteMJMvI5lkNwLiZnSoFT515MN
sbYDFM2tf0RiQLyEW2XMrmEiVs8zrn7SZRTVuhxMnKD20X11o5c0/PSpzh2qLSoyUNmfzC5PZRPN
6aNzgLcIJwScO0nrv0OLjNxwV+wazZRsyxFISyRERg8bWAwWozQ0z1Pr3vvJStmt9SglzfTFvsIR
HQxDE9LX4NvIGeMrxxO8/3xKGXcBMhlXPyGJaihqdkNdjs6YJDWwXUUlSqgxtPAzqelyQOQkbN9a
/Uh2/PXERnp9EHqyVmwFpCse4zWH7PjJ0w8+915QAxxPSCh2hLmBWbP7D97fFpyRtl81oAWgnEfV
jjmvEARSuFn5Z/Y5340cdEejQqfsTrRk5StIJC8zFTbW9XnLZVbWzAItUS4ZfW5AN89pjQ5YhWVC
l4fJ33dajhalhTgtvYgOd5SngAg0OMw3RfhjvyjyEvPUWq8VJluWiQNWyqG0iNcqmDp8/4kH2QVc
n2EtYmAaiLwmCwHX4p2q7A+XowYkAUM2vEI2XKobNNSiWskg35C5aolSMyPKOe5oWtHJTYjjJGAf
q3UxN9Jxx+YkzvTlTgRDaJTkv1EXDxivpiDVjwCLc1bNoPv7nk3TCKCXDKWuv8uaFlqGUIzbrQVv
IOz7BWQs3zaIkICSYGHHBueyLXgNCt4zVtlVh/aaX3yQDrlL/91sPK/SdqEI96sbjTKy5Rys7x7M
opMAU4snpttVxoWSUraYzWTnx0y5AqykzUf+UrlCsM0vfPPUX75zH47hch97pTMdtHK7qq819/sO
slrlKp6NXZ6XTNanxqW7Qpn/OgL4q/lN8H/T3D2N4bUBLN2rN+wSj2k2DKTSK8MX0H7lcXJtlOQe
kMnZljYI74h4tcViAXRhDuDZHPtH/eE2PkjsvvOxgAyhc17SNX5aCnPCb60dqvxnSmySMkCE2hSz
y32BjvOTNumPcq1C/B/38BvlxMTWM41PeYiqjqEQKfL8LTlG8bo8ge/NXHK8Y3HJfbXhzOX3QPBh
2eMd5tWCHqg+vCC75TTmD8+k4mPaBYnqzD9loN20Pc7jmu4moFN0yJAU1FNoiiqAGRapwmjBnUwt
j/nM6xCw9/Vgj4d/jgIqn+VCkvgkGpFI0RAIOnL4/gDNTCNEMpazQ5pwAE73+Cn1n+6NYamVme7a
PXJrXS2Ls3a4gLHU4l1wp5ujR0aYNaKDMGcusBOOwjZGaKNK4HY39vEzwY/3HY2aUDG7qC0lR9T9
HYsohT2crgKtsFrDUxM1Mqaps1JX6Ac2uv/bb+LHn08xL6XmfdTL8NBZ6q+67A3nbb1yoAO385Oi
VKnEtlwQ8F8g5/YXCAS/+7uHFWA1EmYpl0R0xsykaHxOpVoPhoW0WIBlqGEHs4WFvOD5hxR0X8Zv
dQYXz/w0YFAjweo3vw4j94ZeUYrD1TVUxplm9Tvmy4YgL1Fhe5cB0RPF7SuxQnOisMgCZ1Iik4GM
TsI9zfO62JxBveYlNELXQm8xWbIoG2tTDij2M4ir7K4nKhr97ulD24zjVVaAzGHcPOn715kjCviq
q30Be8LTEzJaOiNq+xMU8F/SMylXX/sNJasKTwtutjZ8M1ggYCPA5q5AeNi8jOeG40D5/G9TFrfD
YIrldlQoeBpCu6gZUXWRAgRiqcp1K32fSmghfuJBOGXKSYSHh7iR+AHHgYjcBZtdi58TigijnYvR
l0R53qaw4FM1mdQMGdhMSA/tiMdq7FmtqgkGzA9VC5um44Ilv2hPTnxbXQHeMVb39QPdlvsSuc4U
NILY8Hh4v2WXMJQQKwXmSwIu7HmfHQ5LFVjCwu6UIW3+7wc1Pcd95h6fI9ARvP4JcHFXteY0nTVn
Utjw20wRFCX8+6l8PJ5ex63Z3aAIxlJzOEoUh4ygXaRVVLwTTGSJeWAcxGQdlahZNLapckHqRVY9
YYjoBcA3X1rogEBzT2rIO5QjO3PUZVInENfhClT3VyBVKmYrxOm+E2F9q++dZIoPgviX5Qaw7s+Z
S52gFq79wt9r7e+sZHtHMNXQnl3dE3h87DsptKGFaXCE2PqQM3Po3vnOZkujCSUxwP+EaQ4vAN2g
p7uY7Ear4E0pm3TZaeBhDxwBlVsN5wkE1EXcBjnKUQ4HsVUI+kZ1uIQYIm0OC7eHKStMUeSw8LPn
5NDTxi//BJ/tCR8SowrLkqsapdR1eaEMG82Uw9QskBm5msNbEnoqd8iPiaDpcuFz1lHNLiFFcyK3
JnbUyq5oNwr1He0EV0rO/hyXFb4u4cU6EWXGHtx1FQpaSbkaiEbqJPiMZlTGv/8Y1/eBOJnqM6jI
vGkoQkN9vqTlGB3WXUy6VcN42S0TnpDXJxRpf55ZZ0ow4OQbwOp4vgctHV22s78qzGwAqnYJvkSa
xsP68ScHwyENOApWb7R5DPbeTt4JY0cFm3Z8RJ2uywfqMOH++8FGO5G21Rq+tFA9pYgICQJDUhN1
cFIrgV4c6CKHXQrTbsCyLhNhVlSPdffgHuqD1q6hxnPO4g9spiWxYz9qQajKLoeCGy2Gr4VQfnfE
twuL4QdtPIHYuSlp8Fo+E2UFkKlsOttLntN4UTzfv9zlojnpDBwUKUIM3phFd23dxKrQzbP4rLeg
6m/Kpt0eJSKN0XTi5Nk7LofJf6+poxUrY0zlIB2NT/bkWap9R87ki26OqQPvo469/ElzkBIwFJZC
/7dir871ei5YHGPKeyxmEWUg2p9FaqqzQO61pOmPGQWMf4gLv4ridkAXgJeEfzUxVrnqUClGw+Fo
1dGUOajTq3S/hQ3J9eFIlwqGBKM8PjjQuVy80CV1YEq8sEaIRAR9XXhWIFj2MXvaxnAh8u8Rdk0n
7i7/Br5X7k17tgRdjKuPYAs+tquesH8QmYaAkvAHYvYNKomDDpmm08FGW6CcOacxssvtXUm6bBoi
ABo8wvE815yz0KqBRsZm42AJWadX04n9ubKyuC0EKMueclwMe/le7VzjejmG5/YukFQ9rfQeocNK
KfePSU1xBM9UxbO3LsqRUfID6q6UWbv+oghZr3lndusX2njpFe3zRJgdwCvj/0bkBJvyXUinEiJ0
4amCfSxjTkd6qC6nKHOcpYphe8z//76AbGsMP24e0y03Y97UKbr9avNw1GP2N2zXSVdrD2RKL+i+
WU+skBC8dTo8eGi/mmMQBldPDmcXONtYSOAATzf9OMvvADwnJrR8ufDm6xm3VcXWdv7Tuggkn2cb
ys9DFanSLInJIzoL1zPnk7SwSoz49tdVW5DkaJF7WpTVE2+4XY/LryBzOThVnVPelnzeTCxlbQb8
JkMvSqpKseHvp2VBVTf7K+EM3qMM33HnvHvgDz7wemJSrcUX5CMHmi7+bcW8yk3Uj7uoU+VU582K
f5GxRlMNlBEX3hcGjU0S9XoISu1VyUXuqp+2XK4W81TEC6Kv3GtIuSb/KewdBHq2scofsYlGA/sc
yfdw4hzQeFJ90pOV1/BeOAaoCNGO1r2o8QINqlioOBoNB16BVxO8iY0gLYWL85kHkU4AgInlPD+S
JNz/5ER7vyqPRuUNFQKjXh69xg8R9kI7Mcx8fCtKlcfSXrucgn+EF52C6Q1+MMnvjQxp1dUb4Uoz
yHTdHsfs+QdptDpLrMtdrRhZerLjJ74pGv8Zc3OoXMhb7h6Exm6haUK4XaTl4inagE/6EqJ9W69p
37NVB9JnRYWmbnXBX3Qp8sQBcV1CafsLys1XPnUz3y9EutAC0Un9m2w34pRb/N9QBa7Qv7dJOTjE
yne44yOe+mmW/vPWV0ECR6oyHFl9sn23NrBpSYse2S9mTX2Z+9avB988Ar2Lr5HMRC/23K97RGyZ
NsVAG3lTE5gq4HHPB4c5iveHjcjux5CcXk5WeXC7FyLhaJHDtm93119MRyjIyDcsYTRohP4+fz07
03RCEmzfmsrTEFbJ2e4yqt96f8cK8cuDQbRa2gHXCJS9vHzSVDb0eRokvzoZJpFA48snjY11O3Oe
lFF0jRXW96nkvLzsXIwX3ITYyLOzJjGqQJVrZvY9vBZrykeGpGZJ10d+cH68wkLIdeM0XQ6XjEmz
ODmUe9gjtq1SHdPNAongtmDWYwrnM2APiGji9mikhYWuJIhJmGaUwmUq7dmuqjD0gPegVw59ehQq
/AXZS130idMX/zqsCT5w4ZNvPogyAkeaBcsNVzq1ae8w95gy3Yragi6rWjbsv1cubAXcSPELjMAA
eCyXE/FxOxS+WSL968AtEAecmG4STgqvpWGmgJJtgY63JELg/DvvCZeTKegOfs7Bl67L/zi2a8z+
r47tHIaylKXK7E4RjhMRJxFc8meWJzGdD+Luahonu6HaNaxiHeQT0V5Qlq3Tv4AM2TioV/+eQ6WF
DbQTDGLAKsZJjeTnbxn2JDJfU1pgJ56WD8qsUILM2WHjgjGwwUfohVYpMZVNTP+eiTqtaaybI9AG
PA/5nct3kkk5uzot/34IelUjL/3qKf1H4iNnKYu5uWsxjI3A8ZwMuw9Z3vwk0H2ZMP6DIITDQvIq
HR3LGEGubbsZTF3bZf4UPxnUy6JqrujrJVooAmEALtPnq0SsZE2YzTI97JH7NCfkqZFerZhBizEZ
W+F09eBCwa3wsekyy0wMqVZFrRrvKDghopmj/TYEZ/t3qHbho6VIt0aAyOd5QxgGTPmzhHcDKBQh
2TUc10iwJwMRNcHibWvidHbNOUogOHNquvCtItH8rN4/QfOb6hHbJtXeqVEbM9564jS1i9k5j+CE
wLh85WUN9IhT6vj+eqKedPFl6TDmTx2OfM9VXBzrQhWOG2twC7LPG8mRFIT/8SoRTG2vG4XDvVm3
0ypHei+XUWNbwLfEqIpvJfMLWpyVEqixopD7W1v4Lg8zXRwDPqFZME2JjvnzQkZc01iLkEK6R8TT
kRWXlNjOjAujWLvHmu5RTdrrCsyseP/XOAAVJAXQA+9vWxWQjGU1aCAMdAflhF0FK6JCAtB66As8
jcYGz9qKbYTGqmr8h/CPWkmTgfG83+Mb0jsB/Srs5PT0SUc1VW8vTYBw7JbUNaNOnRo5IYDqADCg
ddnG8s4QDaWXvc6Ch+Pt1TUwC2ahQ2JXYqxD6X55F0i2Qz3L9yXFLXSgrCI/XDqsRRt2TahrEAHU
rQJV7fs9gzV5r6V/szaC6K5RVqnzVFGVqXySYdge62oYzJBjrn6hEilx6SnyMwqiZNQX3BO/iGkj
XY91+b6Xoy3nAbjAh6WKOKEjzfp8ORBA2NmV/rCX34EXtKTSzHR81eptM9u9afqK7foBSLXutZQK
QyNbxIqlqSP3wEFCwrZmqB84dGGLzcoAWNAbTg253jA2KNQ+9AkE8ZnGHlWa6uOFeP7xyx5b9TbF
tt+SnnihjvG9CbFhzKzuq8NEjsdaVvlub6YZGBf0W77X8vo43tF5eXhZxHgDGsTgO5LyNMQuyBSZ
RnJ3cOGO+LiLBZ5iJHshQZApFNJzU3Wp/16OG1Xpkga9ZKgsW5qFT8U8pxPuovQaOFZulJce0+UU
LBcinBsAP5hBCy5EQz85HFI0V1kRiXPTYBsGAT/Kg/dGBC/Z8U0+D25DvzCO5Zz5KVevc/VQ8wX3
VkpEyPcRaZ8FCxTL4yUrEifLOP1fSt6N0fZq7nVA6eXfAErs5qS9cj+09IsZZV4Rkp2M9Gw/l55f
L0X2ZGcBoJYC9LPLNWnVgcFJIRquxuDWnXvMzGcXJpeeOO2qTl8K3LmpJE2xgUQgEgiLA1Kdj5LJ
WKgUXr8qAGcZzpmnyYxzjL5/GtEC4R1UZWwpxJtfbuYpqkvESBgGpo2v0nihp41LPBF4ESSi5sYz
FIr/jXWSk7MzEalNNxe/qTTovM3o6DFpIgY/SaBAmaaZMLLfA5WlR057gDAeWf2qnp9uu+Y4LO12
yRPDya3ujnkRzRBLYe7IwA5f1ALR9bg0JngPqjQ37X2QSQTf/k11O7Ph/RncbgIvVsJXQjMJCq/u
jKsnwK7dVSSbByIYUV1Mg+IqBL2asOyvKf+IaXf0NxPrfdCcgw7uuMnyocvs1v20HMUM+f6OWsd0
o3F02JqRclQeGmwGCP7gFXwaGcH0MNCCGF0biGbooVH+WGlsQLJ7o3NFFBVeZNluCfOqCbv9vEzZ
PutUDtfrgOEqo/qYdNroJd848mLDRPN9FkYg8DVRi+j64DlSJZB/6MCg64yuKAO6GDLfaqUSBvmc
/9C1vMf4tbUdr1R9j/p9JqzQCNEYT1xEmR6ipQfuXZ0dy4paIk4OUvX2ikOljwrI5HpvunAGyryS
CP/3xcxJUEsooCHhcwOCD80U57T/u4dgrl/NTq3P//hP/GdPKkTjK2Ue7K68HMzMSORnjgG2zLFV
QsX13vqMm+VSr0xadnN8UkWSxfpH9apq9Kc72z7x5eNrPWZFygAWNGmP/0DbPikdfczPofzU0Vif
SaEH6VEgKBKuAcsfKwWLVWlZXM4d75OjRvGbu9aJ6WnJMa/O3xVZEYW+Ms91n67QBuIXgmZGE36r
aKvpeJEuGq4DXw+Z2fexLNiKLbeEy2nbR8O7OWFBvkhrzb850dYEBgC8RaqtsiddC4h6/8fP1I2K
Vwp8GXbTEA8JzdOVtFn3TP4SC0H424V0qmaHl5eR1M8GZeteALYrS1VtV9h0M+1KKAW4sB4Y68ZK
1gfqKN4ifx3K/C6AoOP/nMkb8PKO13HTDtoF9U131MrzgH+brUgk3UR8vP3IQmJ9gTIbeR+B3Dlu
4dVMXtWBi9gv1+p9bcF568YQRGpIaezXoTn/oNHc+lrLczMQHOp1OINPUGyP93qVLwh4PHtIcAKG
5gwRnL6+/sPjjXevf2p9RPdEmX0mESx6N2Bn98tVo0QromMwRLhz8KlK968cGLfDNBdG4cdLbPWK
s+/Dug/yVwAf1Ofueh5rS6/5NxpATiMwMZrKiJF/O01EyD45bKuqByrWjLwrXiL6qjnf5E9gJLje
sLSuz5JhcpaawmqJDzFqymB/LVrD2yCUsRNMnOYTlkaTcwYes2iLuxsalQvXbpgVTyQ0OOE5eeWD
Syq2cMuWwx8XPfUmxf45JSbFs+Nqefh37g6T7qOC91KOekCEP+9p3ONNpm50XgL6eNy27h4cm64y
CwKux9mD6o9LM/OYdioQgJU4Q9SvciwssJKzSMCvlmrzMmnH4Zpa5gz+IT7LAV2Rgfvw8t7Qos2i
P0NF0HGYsbGKycaG4E0NR2VlcRcar4ZAxpRdXehlu3tjnMpRgj8rjy/xBBCSq0Ms/WOH7mcxHiNu
JStt1hvQzXzat2E/mMTaYi/MJ37lacasMNptrKm+GUM+KJhBJFzt0GW6iJhrPpMwMNvbfgX7ZnQo
ojAb6JeoPmfKQfAzARO/YWxNt6b1V8eGwFx5cHe9Hv++9EzupmrI7bQtXIQf2JmZ9OqQS78/ro94
o/NKzCJjkJyzt6ILm0ChlXoLpP2VYGWNdkPuXhiRUa5cNqbc/3BzCCSvCvfqY2qSbWbqC+qSmT9l
DNm0My03l5D4HPjOu6+fLPpCWhWpk2W+zFTV2sjwc/dNpxr134e/Ycub5DI4pAJzZ3rQ/mN6bseA
D5z8js3ElBeOur0/nHg4T6YQAf7NgYUMJCsEiMZjOC1z7odQP6vUKEEvYyQ+hVuqpFCq2jJT4igg
W6fvNeZXWjUyLqUDgd4oHWbofrmyRpwtlqi7T3Y2q4up3tgKjhPA+tkri3IppM/pY/Fuv9CpK9cX
vCmPW17pNmkgNR52acYkLMSd2g8oOQdJfh2YYS/5gKpCyYqe1oVwgDejuyxNlqcNFhX23Lad32EE
hLgMDB3+OuYyYkp0UvT06nao123fTaAByQgqweU69QDXxpliOT0vqUVyZZziSJct66/jVZOYucbp
EMt3P5gGv2HoO/yTcoEfz6D5kkR+qseki0cxsnRAnf2OdcfrLtqGIsOX3jy/cwv2dyLDcT2dECtl
Ztn183awWJUyhOz7P89MqzLKpQI4Ucb9XPfTOWDg1AydlUXcXDVmHm0Uvn0Y03d42AAmBJsQvw3p
Zt28PgJlo3LmDIsm/Pe+nCfhBt6tSNOBlC5xZi4PbpmF6cVVnDm+7oZ3yj/3qNCXQg5iFxe8j1T8
Ep7jRBqMQHwfuxCIJbdEZ3FI3sDU/3JXAe/g7i0DgIhrL+8utbH5rDINgRPWUySI5Xl5hzwwsjNY
PA9jz32dMQ/k434KSuTz5PylWz80r7v3Oacwsnt2DeD5ossrJF+WarDiB+mtPZUL7K9NUuoZ8Kzp
98BgxtXu6bYvlDcvqgUcuUH/RW7qwwaxWYFH7VdZB0TkJ9eyXK7lBDFa/O2duU6CkIcNUeO7MTDm
S3yNvys2QmVMVbInEB9HdYxzJzsn/YbkkXbB4W/IoSO6U2iHpzjA8wkbllwNPCu5Gmq87D+jTb2P
e9zasY1dYEWPFnFweCS5lnGBZqSOXmIgmY2UC36CI8tjM+fM1NENXxbqy0qbhQtMewPUmcbIDZ10
kS8ws+/Wnsd7CDdjcyDhmZ9GiPTLwXE3Pp37F2x4fU+5yQNsyEQ3/aQgg3CBXOwHcpe5cR+LaPnx
obujmIFYEHykBcFAeBU40AKWUlXHFpiEk3eBrwi0cTKYK15U8kkCbdrNklW0nvvmlHHCFTeqbF6J
EoQxlTbu2b4PUuDWsBqouHEfIOOR8g+rmxoRmWcuvZ10r5OI2WVmFHLbbYFbfux0xTn9koFA1Fnl
mqUuL9xHR3nF27MGRJ/ucBr/lxsaVtcS+uPbDYk+bgzbDIU8eqUsNE1RwMBbyf5+5My3Gp4S0Fpz
KC2CEwp3dhRvCQNBMx8LPqmOTB03Oq+vMx0EnbZAM2nfh9jBFkz9PIQYuR0yS7OZtiBN/2VMsbgq
AEOUtM5kvBPqK0I3evMjJdy93lXtkqpbo2RUXL+Km+fATXA/F7ekQuzjyNiybb7EhnhvyxxrazJw
kRA8z4fFeEfpgwgCeEzEr8TQkkjxK7X58ia5lMcqw5CGDhW9f57v7uMiQ9YHXbyulHnwJ9NAbFPC
0eWMh/VmY1Q69ru7EGWAmwYMEvy7mJEUkRhw32aC9m1MyShOJX44k6kR1bEQZkkAFVxvPPzRQznU
RRepBK3yShVM4Sntw4DoEHuesZHxUcnEjC1O7VVRdpQza24RN9WatGLPq7u5QDnHA0BCKe595NDS
ARRKsa0UBUPwsjzNuq4OPWQANG5ZfqPPaouOK4Zh/nJbo8qxGQ8nPNTR2E7D8nTcZlcp1aVOnDDG
6QP39u0IbC1Vi6qT7zwZRcfssUJjBa4D0WdzhfXIxi8RVNwjYWZvDRXbER6KnAmkRqOZboLRawTU
Se3g29M76YDxFucGrElHD4v7At1znamGvC+QWPfGkQjF2od1yh07ZZrrR9Kghdp9MtMW2c6CiKSj
18eLQgvhO2MaUhMCkeQjDR5xJA/h5FAyGSHqfOeuZcFXG9p2jFvKcotSy63Qv244AKfHzrdA1hLy
TeQTjQc9vHGpYKEIvlXaB5CcQXsZXO5vN0Snv5KUpOr3KGsivpp4nraGnXEuXT87QnGE3x5tLB13
cVG77ssCVshMY/zznCU6kXX1YQOxJfk9xGJLSviXEZ36xOD6wCMp6uO7TFxjOJm4iDOlmEWUxeNE
d9UpuSiO7lnOGLYoM+RioZfYsIzwHnA8IppHOmGlqDKE1XU6Xvvk2HPLuWqNl3tCXTTJuSb4xNW3
rYVL0K4vWmQA0nyoDfVQsI3ryhbh9IkdxnyxEj4GCndVgaZAklhavCmGtJ7czeV1agIZGnJccDpa
EYNsO04QPg4BFXcelfXk0MGxoiyrx76Qv5daYQ3PtQqi9l7jKGNGfi09wpQ4vXb8iDek6yf6AT9v
HXvO2sJVna4USdD1BCpn3QMpxonr/SV1bfvdLF1MRoExa9EcwptAFsK0ThJcCiTQKVSVCR+Ff/+j
tXwaqCH9dH49XdPt2S84l+DAcfINspHuUxyugYHV2elK6XjvVUmOOl8upP31xQQV4n3cs8utiOBv
zaPzOhHPCm6zlGPeNXhUmKfc7N/7HAljl7ViWcwB/jJAKBYOgtwlugen0vPg7fpnznqNVSIiXYVR
0CguHj5i2Bp0lm9oOzldO+WXwxoNExkWga0lXOwbHmSRE+rFX5BtN7+CnanNNu7ThpTaLZ22OnP7
iacgKgZsU3SV9s4EwwHtflems7hgaO932jp2RsVRkAo5W5HF3fmraicED6X0T/cjEAXoHibbB+2e
P2J2SUw7hXbZydLL9X133E6PfE3AJs1kRAgd83+LkrsKwwM4Qgn2GnqANsGd8kh1LgK+4qZEDbTD
y6TCGhQKwM/6bqtF7HM40i567L7kKsJ94TySiY2zjBEAe/ODm9H4U3TIyxyGZA8YpLElrc4UmGcY
0gAye8nD3XxwxcAWNNvRSpEk4+6fODW7PBQhqClVeJrS47hBq8cMPMlAaRk9PH+gMqe7kj+OMkUM
Lo6zKbqqr40GOtExXxuDBrYoB/gs3DqI0eKX9uUS6Yfb1dgFCThIgChgBr3NCloY15NfiMX7woTb
vSLF78KiXrUQ52lSW/p122jIYHYOK2XtQC0O/qx+vQIxvqwITSpLVX7t37O9GhIKG2syL/B8jOUW
sHDdLJCxlK5JjLnPREFawEgNEkhE+NVjBCZ0VtdJLTJQaCrPLy0CsbnevAZ7xciWuMzYBITpT93o
o2WMK9EkFNc2u3JEKKk9TI9zocOn0G24VFD+NiEQly34AYdZnGsVMW/9ngBZJpnekyX/EUNSS2+e
PfxM48odL9Rq3KZ5NJBsiJN0axDvXOqOZTw4kPDjdHSvhNSHc7kaVh2zCytbCanrBnCCiD5E1bHZ
EUbjFVFqxSvd1ZSIRGIYMlnodZBWVgymU8aP0dR0cn/WAzyIOp4/pcSF+qbqebsXrn+LSvzTR210
3MjVKNiiUOgL8GEYVwq/9hNcex6MIjXaqol6XuDq10ym1Ly4zsJBpdnrthXR4fBPqnGFklMJWSt5
9sq7AyfT3OqbIsoO9AfTVlgiZdtcu667mB37fPFRNVlvS6ayfvts89YMAfIvoRyYektbM0jqv3Gc
CUlEwLW9rSaseEXq8kEnf9c+EXXMQ0cDC/zaSK9jWdETLjJLsdhaRpdF+9WeV3Th3mpY6IGzhcOb
7GbzgQNh5GYuKX+K1xS3HHksnFa2oKVEIgsOutW3AiEAhzS1+XPFD/6aS8t6ZLXc7/evVqtONPoj
6aeD91dH8chxbDu6UOMFYSCKfY2mDQEeH76jReTfuSGEXxqOzl+uprxflOUSpEV/nPF/HMvp/d9z
jeF/ytnR0jJ/Zw9C1xQ1KG4MYp+0Tn8EihK5JLXh4kQTItNafyY/zUlirrroEYVvZAt17jfx2h/0
xrHVkIEAF91SmunIorwDySD//4STBsMtc86J7Xxbrb6zHUAtbqnJdDDBZ0WAQZzMoHkUHg/lod2y
rSCV8CVMbDTY5vUO2Kd3rW8ZR3eH7i+Qjnu/e+H+Biio4ET+tFzU09eFnNPi+HmiJ9J9319bkc8S
8uO/VWQeb0sQm5wDZ1RgxIejLedYeTej7UMsiXmr7/YQac1Y7U458dXPfXwD1f22doj0ly0aAHlX
WpGyVxQIyjHMOQs6gnxy5hc9es2ODtI4erOULoRpN9ID/IbQR1XoYJ25eCZ0BPwt7CDpTgsI3/Xu
5StdI6iBqa/UvZXGUH5SwscNV7rGE4v1TX8watxrNBYpPblF/JpQ9maGQLSHUO6H1tgyD0KCOPxQ
/qmHBqdnAwwrm6z4OHfHvG3zsgrnhul7ivvFmNSQ7we9X1kw0ZYmMJAZzGP9KFXj/T1SoEv3e5Ei
wrw8bRPGbWEz8uSeswvPsKD9UmhV023VGkPI2m+mrdWC3s69z7l7rpebwlb/VFt3pu9R6/62y7tl
wrkud1H8gMvxkBO99LS1mYzLUjYbIqU14E548jaoka8W88eT0QamDnaDqF5lVdUmhs7C9VREgYzI
F2DITqoG+CU9e1hDvRMU1srxUvaoFioYzr9ymuxyGlKr1pR85gI+MhTYTcm8nqAQr7H61QZ7ZsC/
WgU79E0SD27TdGerRoSPCfgwuE9NFqCUaBsRv4WXAeQymtaAkd8j2qYIepzGSw38aFTfnEouy472
R6iH17/0oaUvfv3X3dvIfxuVAs+kC5eSL5TQPNI9LHi2oXOw9BJ6tj2Tu9bHr8Hv+iNKUEH0f3+v
tK8vS7W0ttqe1545HLt81o5WDzATA6zxSnvW2gGqCOAVQ3wh3qKptGTOfZOY3VTsoYGDO1cESCYS
5LOR5SaXS21i1GMp08+EcDs7GL9cTWb57v0QowQBnZHha8isOUqCLPDcpl/5mvL5MbV+MeopDkQA
lXJQVY+NQQpdT4PKWrpmW8KrxaaYtbH92IiUFWUMwcxXAhKQKfIfum9gyGLp4bR9JDxY8Fi5gbos
liTt3cQWjgwAV5jFKxe8ZnDnOIMnBjc63Z/H9jXcZh+9v/OGc1pQMIV3pmbKRY4s1NBWKsxaYq3W
0eC8m85g/3Ay1c895mI9tzoJvucYJq3/F33BtCgrSRUxFAAA/6Z6SSsQDNcJN9eO8KaEEc1OMdd8
1EPs6biRvAgaQnhkeGwYMNvu6K1qLq2I1pPmUNHiTI9hhiSsd/luDyrcb15GMR5bSlRxWTkoqvig
N3L/erSzybGI8eE8m7B1s4Y3E1TO9qd04lST2DpFXWWbIlpGSrgGyjipR28SfHFOfDjgu2giYJWz
iKIaiMhClPfwShxh/2tFfKwQcEpsTW+o3jGXHbxEkBFbejYTalibGPNOIvf1l8eRPI7Nrl0NqD90
R555XjSjmtlu7cd9PY0uEctkZj83XGcsWbLQ7mg7eOKmxo9VHX/glt2Zag4A7HLEyRkEYcCge8V6
MJMDIpuYod/6alN9AyzFg4SO6+FAGjwZGEnErr9FFmNvuSmRMYocD119N3EkXqXbD5TeGim7iKnl
VSiTHB/6B1KwLLeDrx++F/MHXylE6recKrg0IlDV9T20EvlzNr6ilhGwMEfQIJMrJIz2Q6ir5xuR
J6GfNbnBQaRX8sgJbaiZcAh375Ifun3sBoFAHs5tM5d3IFKq2SSDLrljSGkQrSJd+uM8JIZaR2F8
T54/Y3SCLdbsmVnkKeybL9rfzh2tOwjRZslKtRWDM2WvLVfXVoOxhs0lJjTpg8qZY9/RPAesyfOx
13DIzJ0nnLcskX3OoUnnWGZ4vbp/t+nrl6WNYEqn1leC+iL4X1bP5qQePyEkE9r8f2ntetuCE3NO
doWY25vFKqpmeHHkJUFYR9dQjiYzjt7EapaZ30Ae+6pMAi0gSdP0m7ZXOJpN939P+hq5OFetJxpy
TvMteHrJyjVyhFJW79i3mkB+hwn+bpZiNsi6E6TcvNnVz7xI2S57xGllglHgFuJAjZA98nJ8hp72
HK3GbG6RMcoXXWBqPKJhJMlk6p3X3/i8QvH33cvxJI25tu8XTOikV0urijjXSD9CMM4+hL2xzF+0
+wGmuLqdGVtpIPJRT4D1s98nbgUYdc2ZkvrNJ21JXK+it9IP4SdHxgA3yC/mKXWLKwZTt3vsHUeE
BcFpn88KV8OTTMR6O4rKFEny3OFp3Mv8qC7xE05bRV1Wb57O3URcDB+tzvwQGJ2sC0sq1da+9beU
F97egAwaD0ymEc3ohvAFjF/WkeGr2xiVU9IhPctZCLFwtpkW5Bn7xXrXbjwsTxLNjBSoxLqHGtaM
tfmG9bz4mCxY3mfJ7DuXk29HiD1DFohVYinj1lpxSXo0KL/A3vqf9m3q/VKyxG9QpOGqhJTkSIER
NqFOgeY3RuWhxBUce3bh/4F8Td+3Wf6rgPGjTdAorW66zKNEQdSckgPCeLvjeF2tJHwWAeczIcUS
CWlxXevEP1TdsFrWmw6mc1Pii5hKtDHrkZKaRw0N/+yi/o4if3vxP422b4kuQAilbcVDKZfuYRO+
uaEAU+z4HMGqONwMjqQM31whVG4XYPz56KeoId5URs2oTNu3OpXqxUh/kxQj4lPZX7P0FgrIuEmW
FTBx5a0aspR8StOskW3kN7AI8+fd3BeXEJN0femHr65YdFayF8AnbHcEr1Bt5YeKmXJxyDtptfkx
P/yUduO9lzQlf4WSRyIxdrzp+uGBywx2SwUzlj9jHMZXBQvDXCKT5J8R6jOXIr43P+CZsgjuNeco
HV3ieaz/6M02ImPU7hsh05fOOF2m9t67PpF8jdzxbmaTxKxP6UGwCXZB65fcerJtpi7JhP0o4oCD
Nph3vXWtNniurCKfXMrAvM5i12b3ZL9xy5LbhhiAziJecD36Uk53/Krpin+yJ9oLidDteNk8BTrw
6nJbQyMP5kVUtX/gulGIAw40pLk64GX9KaNm3fiu2X2F3ZnKa2NUIBu6xpBwSY3u1oQ7bCjgzw9K
1SprKJm6ooA/PyYlkSX8jIeISZe1LITquja5/GJSoLREXi+g+fu8pUkIwATtOWRQPVxVAB5JNPiU
X09+qOaQNvuBpHZuFFW7jBK/j5jQ2CVQZ621oqJTh8TM/5VhTJfZ1hAEXIPvkX+kerv+WjZbgLj2
PqcnWIlso4bySORaeHoxMI53E1hoiSa9Q0LtlAOcUI9JTklgBu/dXVc+XdbHGc52MuZtYw4z3eqE
5018f7bMN2b/abGT5vDfs2lNx15Ja+WSY7D0Fk4X2FVI6Zh5IjW+f5u5XUCWNmpkiNGlGEMRlXZw
bXyS0QqX1B2OiwcZkp+YstJZJ9ifzLrc6RTL5mO0NP4VaqX0jJWVNi8RozIY72+gmG4vnQ/EB9q5
IR4ygyfJiMhmVpzJ/y7/PbCKDeVG3NvM5P9xcVy82WDj8FrdTgqT0wUG2Cv+llk9nzB7Xwa6yoTa
wVFL8BLP1KzVNXuvgsmDdvwuzZVRK2xBxMJGemiQcuLWfRp8npbe5pYvOoY6C4DtYQ3FKrjFDlfr
1gCtie1JYIL6KLhA1Z9uya0rc5/O0BKqgfx5hmKvBbZLNYGWWE7YmTpfuARRz67NNedbCQBHdzHT
y80I2D1K7UC5/hy8DiryUk0zHC2nvTPVx2nHwa5W3L8QFBe6M2ti/QC771PcqAiHrWaTgjp2vIJ3
Fj0Rf0/3CmfhQhPl/JD16YjAML7dbebxjeT25KE/5kwfLVsU5DEMNtECLp0GTJ+F+tz9vT0Mel1f
mV7WKZALi4Dj7B5rmcf2onHGmAOz2dlq39VjOGFJckzuJg9GG19rbdyktp1fYlfwleRj5ZoeoJNq
rBBxSCzAUkWrDKJmClxXe5QQRVDVIJUdkZTfyQnzSX0ai2drscaYHyzvYLj2rISslKiChkt9gHxj
NlvFV6lhmZYLSCvasxQCTHXSFVSaJPvykRUyiq9Tvp7TNtAHO8JN+fxywbqxj7aA245i1Wb6gC9z
jWCx3s1af0IWNRtLDducfMIjyZygjYDLMU/lGz78QBM6Qyji75SfkaNdZ5IBSEhBo1EMqZIM5Kh8
fyS1XtYPnFSMYs8tNGOoeN5uJQGsR8meSf5GlYdjZArvbgOa+G+gfHu9NQ40nfCq+AOMOjyFzIOq
Ip7Fk4Yw24zz/65wSrfNSqw0TGliSiGBuvejapxse0WAx+pck+HqlD+dxAdd1xkl108gmBOmGFct
vwIQNqTWho2sYRKZg8OIUvc5jqaR8Uh0nXGn+WaQwNwPmpMQTlUtEy4j/cXqMWKzk1Vfl7xXQt1U
FhxGFqrxPc1tB27viTSIJCkgZVrlCXUrBaBD1h37l6v0NroiqvJErk1glzJ77V256y7E+QO7A03L
rmmxSWulwZ+1QVg9pOSao6gZTvJkG+k24Mqt3Ce0fsxG+U7QblLuOZgEoyvu/kah//cxJSvHFGXn
AL9RS7e2r4f1l9GDWzsry6hmBKbzZkByMaI7iHMsKDRnNe5bMrStWJXW2yWfFgyi67gbfLwYHyTS
cbZZJJRJIr5Yt8bKuIEjRA1pULMrkBpNJl/Dy1pLcnbvwmfjdcM46nuQwJQuV5sKp2YnuuYq8tve
HaUJcnQKuhRnMZYJ4uRvSHnVINfxhjoFxydooG5yhhT/usw/u3r+CGkmb8d3IcBj79xPbXdWXpbV
xGDinZxL6FDd/vmRfScXrdASkLc6eXbX8pm6uNg5Yxgwx4ocmgKoeQuTLFZ4ahSY1/D3Jp4BegGc
kTAoleccNwxtpmmDplhYdRj1zem3WynI4AecB43NsKt1+oy7aBdmHk7Zbw1yuYzX4zkx4CWmjH3l
W5wwhvPPhoic0GnoSFhik768ngXguj4DshptpJN7hPXDgeI7LcUAnIBnMlYIbbaPlX41CwO2PrTO
7q2oSqCipH3Rehugk0Tb2ccL6+2N/iv8D8CAwWVjSRIdmLMb3iy8IWr4PtvgqztsSfl29tnGziQp
SCP4jCJ19V7j0uGn7dm+MBvWsXoYoDQMhl3Y3IuWg4uE0H2HNxVC8mcKgLg0IXavJlrS8aafDFbY
Zo9WQvJD+AVeBHI62ogpB+98TuGfFH0vO9gnZtiQYTJlAaD1aSg9p1MVruvbmDAnoHOfxEIoJmRT
gPIa41kzHbGMx4Sacnk6BVrt4HxRBga5oy8JOrhrhNQvUp3/pYSb4pD+CgzqED+roPSIqQHLxIW+
b4D7FhNZxYxoG6NFl0t63U/0u5G+TYv+6bJJ3SSI5RyAJ/FQh5wFQufFjSfos3QXur6ia/fEJxtS
xXfeqcCzZUziQPk6LDH2yxJKnG9AAqPnEHn2UPhoXCYUGprCBirEga06VvpXREYcvM1xt65r07Em
iBPzZaa39AcugHB6FMG2DS904mYj9IFRJOFtSyp4b77UwVs7x+VwOa5SiyqOvLz9aZ8mCOT1knw6
MmCyE3rk7A2ORaQQX9gXkwC8EFVlLeUZ440perEArIFiS5V2KrNDXDBAFgt1vpgsPQCbuqY7vukN
WyeRX+Vh8bbnEH6+cFaLL+gQ6TIFaZqojLX0FbiIaPHBT1z54mhSbQc2w2tez4s+eeNOJiow84i3
sUgtyBPYwJ74gsB9TNBRQVtrqgUN0GAqR/4pk2Zy1IPqjnQQAzgHIZwxnqjOI0ABuxvlVbAgZc9u
efnVQxaFsKQpBUbY10shmUrIKgKmG42y5YpxVo/O4b8aRHOhiR/sMot84QgOpnPuBuiTx81ptJ3H
w3hUHYyPvMDkkvkG8Lc11qDZRvo3UU68TZJ3ImcTZUF5RARSJuXTn2pQl5qtw0wobhLTzxf8UfRt
WivX1+u2mKQ9zoAmsH/hb8Lp4C9oQlH/XpJiLEufcoE3sS3uuCQPkWwBFxLT0C32VcFCLRAmPyu9
vzD4lCVZRXJ2lNsigPh0cegM/GqA1wjjtYd+PIjmHrhs/ehTz0Z5d6HeM4qWfOo0QQBwaL3hh5+f
r8dyFnyIxMBnVjI61/3T6c+hn+gCBpvrbArF8dKlZXvHJEvL1pmDvF3DRN/nF6xD/Uf5/2WumZSh
LsjslTllXZWxbzqUWQUYpve+xFD8a+SSueoYtszaaeMGdoSZpMwqmy1r3AqjtdYa5Kk2kIl9+IsH
PdZzYqKV5IbjoqH/GLd85T6P1kuNWtrUfVU/WHaEPM7o6XmEyPfUWH/KyGE171lRGHPavUPNMSvg
CF2DIwi1IFfWCWtJW9wYUrcQms3NA/7OlrZ6/Jk61H4zxAMhP3uXBU4cWAy7XdDeKmvkmyQ0VhKq
sDNwnlPw2Tw1fWxu5b0GL0xlW6t5JoUDTWXWWHzLVWHhppgFKbDVizihFs5k3thGukvo/nGsIpss
nSTaFfe7SPYiqUBacEwUou+tcYZCVFK0VUSvPk3+Hw+Ep95eMi0aTt9XAT8ER4xxDOIOdbytse8j
/rVsUpyFlGCrtFV9gJyrgGgvfQCEwnMSgIhAtGzMi5rtUmrtVAGT3TxRLOvuwu0HS9x61GtsBHPK
AhY+9wk/zJMSsCNKidfWVNbNwKwVgHmGPXm2lJtSicb9GWfW1TIK6qxtcGUQOLuNVKf8MyeO3iTx
7o7ojGb216TRqebMVDm+uGcEUgpBmZFarYr/Wlp7Obe3Jhad4higcH8xAq62xU8PjZQBHSVpmHKJ
fBwjWdyMfe6s2Yjol50gu5U7j+evt4g+6pjqC7OU/pdMK1HV8jxbdAv6sRHnV7zyqlVs4LGVbYK8
wDKSDi3VksrjY8F8lFJWZlJ1hDsrCT1rVsgkUL8UY/OhWHBo/2WyAz2BrswJNDMfYSQ98aLunnxo
7kOaX3hmyxoTNmnLS1VZ4SpLYrfYMLyEcHYw2bQQn8igo05vowKmDOjjlNCIcekHcgvSaaCgGW5k
b6c2nudo6GN7nyXlV95SbxliLARo97gzlvjLf7rwUAj/Ph8yd2GuJk6Nxe+qpS1TO3sWzrwrKTtS
O+1A/M9pMJoAbiNGesS071uNTM3sjzHGPPm40/7iTjt1AUO3WD5SKkPPVQZRtossMRCNJIoRlQeR
UJU/n1+BS5nykM+t3V3O69bhx8WOnaK7fm4PExUGU2+EbEFUjgxInOpMx5owdtjFFS4KJZSqQVgn
ABQII/DC98r6b/Y+N9+ONZi68AHt9VTTASp5y69H8k3AoyMBchd0hzVCtzud1khe5UUQYQIbyzhQ
pzLi40gqywZ9qtJajQOPVie2r6VBclYpUZV/Wt+JK6ZcBlpk4syI9z3YMWsfiZSGlwJ3/Y2JBvLo
liya8jdees4FdQP7MFACCO/DBh1jD9cdFhg8/RXKVmoJWJRQcOn2SVrjSbQJBn2gEiMjrrl3PAA+
owfsQAT3RlC5Bu09VmIQ1bQlaEh7lvfp2hPC7cPzCmPovNLSts5kJjHhAJsotaRWBxTWGHeoQS9H
dgVhwqYLcKw8FK3gdA2RRk+FqjmOuXxFEPk5GoQXPTLSS5PGGAFrflv8mTm06/tridCiZ3PguOSE
3fPaPCiIXoM0OLJKZ1RTzScRv3Ws0dJbcdniDavJa0JunBytOLoALsrtOCeslkcmU6x5ArzOLRTj
0RB8aSVQhY2pHFBKuBxZTwG/XVL7L8c56i/EwejIL8h7ElDHYUL3MeDr9y35uQmXiE25dBqYYlmt
NtIh94D3ejo76bWvTMs7nP6+78KEKJ7FHAfJKmc7nGXVk9rjr9Vp41k2npgAJWkDpnAtHy/ZPB0l
IrRBd+thduUjVyvm55dL9TNFSc6ErPtyYQTIsD7c8NeNxc834B2BCjg+WNqcwlOXOTBwhyg5wmXM
1vcw4L6x/6N9xtraJeaH/0uMjV3AvDdB6/X+slPb+9UiCaChfoU6Y+5I23wy9YQVIFRJoDwh/Jmg
00wERVrz7WQffkihdNbQBHGKIEYxeLf8RRfU2ynbAGh4zlEkCvN0rPs36yBDnGEwDvnirXoycGJ1
gUvO4xr2tt8uoQcpB7USmnUaEwgI9bR/ph0uOvw7EtkMrx7t44DG5cCFEFmWy5OGG7trFPsW6SeY
Ag2C2eNAkDX3qYrWPQPy8CfjQZM6gyyPJfnWBuiKvd0Coe9rTltEcniu1pH8zNwq3PBdaW4YDRAg
kV8Kd7XQp3NQ2f7Q14/Ud3GNk2WtazjsPOLIb15G2L3D8bvNCOvEOZnQGRQFVn3vMzmmQSMvQmZk
vGJ6PJzH7kw5FmNsJcreIpEM5H6HKQpjhy6PdCAUNzL9NBmgL8NMQIzy/BeIrmyMbMrvpWBh0CFj
3yh3yKUXvdr0DIduDeaQ88V4Ep0HmCivjWPxAENQtxHVSKWFdN/qEDlQgWykHuMhrpIufbnoY5i5
KRbDmYXqkTJmIlkarCfgSVnRffq5iucD9jC2Ph6bp1COKctZX1YiabAjt0NaoDVOCuOioWqgagJi
q0nSxtCMykrLyhgkZy/QnaJB6FRXnoXGy5Uxu/Bvu6Xp1pJaZNm22dnyFfdDbeBu6f+SbImW1Gbb
/0iGo5vakwzd7GsCt+p3Pv+kfybG27Jhee4jzCw9PJMouSrnW3uJMQ4WZ7SM0EBu7APX8it2PLVh
hxtCZniIw6PRny6DV/ppfV1flirUn31gMT/Q6prZIxRszBnMWZP+/f2ORFZT+4zx4Bk/D81baIp9
IzFpEnEDlElpLytLcy5f1wEKZwiHxv4k47flf+BM2tli72HcZvQOSZAPz1TCzjoXVgfKIq6JVK9b
KbTsdffCFmHwW7kyH2qtLXHUn3LLNVU/BpdJLy4+SNOBxzZcZYkk68bfhGX6ButsnzoQj+5IAO2G
yvE2ql8bZT0s3Vi6t6/PJa24HYf/4M/AaiHQY0XK9maDmEVR4544NZwxMVKFwQqWQ17QtloyWZ5z
2F2XQTvFhQ/6VmXjhLyMmh7SjFprE6hwcMCKgmeYYST9YA0AHntXg8RUIdFUBlbWfHOCu+X3ogIp
92dd+d7aA5mecAXR1p3AltdR2JQ1NGzIncbTWBMjQ1dhfMiZTVkznMWlfZ4EcLvlAJJPfD7S6vLM
g9ek6tDWe+KQ9SQdfcf1mC5FsbEDF8a5S5ZYf0DjNt7TGKjueYYsQE3xEYE9/zhlTtK0w1ZCWBLW
1+sFwe0Q2rdez0ZLfGRvmDDBqOqB+S4oALxaQf/a++NQYOGYIxF0hVYiXwSOO11yEflZCszZc1Gk
BdhFngFYWokFPEHgvPFja+kANPwqm2edImwJbNzg4FQRfnRtjYIi9oxFvIC4mfeKYqjStSBuWAHY
6HqYRtA9GB+BEI+MeYrjfh3GFv+m60WFoCwX+mymq8Dj47Z+nX8dB0z3+rPIDCfDYOmKr81desTk
aRN51p+OHC8T7B+AXKDv+tgeUZvPKAlV0v8qOEzHUGaadW6tMwTfQ+KeL7Z7IF4g6BusOqUMnvMF
tRWQHFhrIyiozOenE1wBGW13xf2tFRM2LyTiE3xczhKOuBFGw7Mx8/tZ2gYdp/4V9o99TSEHAJVV
FB0uGOKDI16yCHbSSInWiutDeIFXSQtFcoE2j+AK/dD/G0dndfXMaGREq6ZXGVyzsUWqjnv/BM4G
KslPjKAYR60j1wvSI40ClVb3GpeOnKQ2Vtq6srdAfuG7eCrVLhb47hbPiv1cgwSrduRFCrgMR/Aq
EitBkB3hmBMun4QTOZe+ObUKFwqJHC+uvYSKS3EHNzXLLe94NvHG5XJEEke/bPIpmNADJQtE/Z//
g9s3rgNw+9Im2dRz+v/6AZu+xlCWEaI+VytbuLEb4i/ZnlHVhnETmJZjIIkraV67Rff7nKpOI3xv
a6xL8fWdTMzxxK8eO3IM3BdHfD3lmjy3sJGYgYudsi+DT5tIlcUw2siWNKWtUl4do9QEEYjyiPVm
WauMRdZRXJvSYQZBXPeF/xM1Fkrw/E/svQ+fmRyh5TmW/56yHyNo5W+03hHNizSWtXnKRoqlJWQu
E1yXQmDGcQhGc5lj5+OkJNUqsaMaI/RkkE0mQYETea10GeX/Yt9yI+05oy6VcaSnzTNR+juMlWbe
z4RaKJhrkDbGmpgFobwwgC5JLa8lNb12OVJApvr6WrCEiGwXfqmX5BPFKA1A36ObvKFbKiDlqTQv
sETCDXF6dohNHCGh+zYIr/0pObu5g9v3Viub/G3Q8ARM4I62gF4PM0ccTH+t0RuTDhZPkxmMaxcJ
UJ5yjnOCKkNOEW50McX5zQsESiLDs6Mp3HJ8tzzw6EN68yi0A3cxl2bSNJkDRMc9tsptES8f7gND
AUOaJSqsP94tfoJ8cbwAHIx3UsMH5L7NkUKU8sY9X+KtuYUIwEtevOeFdAoMQb9+ui110/let5Zt
mTq36oDMvlu0VwEWgmuxw1nmzV7Z4btjFjprbyPgxm7eXnH+wwSaHX+mBcytOm/rukyv3zXqbwYb
pPhij/EqBt8KVdY9z2T9gj0eDVa4W71pM+y5hgjmbwED1p4g1+uN4S95OgDKckaZ3DkjyUoQqkBS
/UPirH0K2YurhzGde/YfIhUkCr59HEcXA2JkRZTmGSWwDURlosBe0lMPY3RG2dBoRhBvzXmHWCOi
fdSFGxH/f+flV9BtSGVvK5hyCxhU+of42s+LKDGScLvX9zfxt44nFSNhcBFiTwvFhVLoUhhDGB/B
puTGO88i52CPk50SyAInWaHy0sQaGN3qMhb1doKBRD1lH1EOUotrmzr7C+qyfpKsvxb7GWHW+QmD
wLN9kEf3LPUs+CLEZdbgGSUYab83FU66VrxgrOVVWvQeAAlLXmh+AjxGsO/uNnk4MysqI7zO2H+i
ghgSzN4KlqzNYhEVF8fef+dfVz6CE2f6m4Q4MoHuSH662hzelvSgWaJqyAFr0H8nO9JN1WuqamRc
C1jZq8JocPzFzYJJj3dXkBo82eq+1YY1cRWIdhkUSQZFp/hik2eti8RRNQuRWSB9drH2tlVSUs4u
7coAJTrAgc8nI9wLWXFyNrtUcXSQyTLuzB5CWWWPvkhyTdhJ1cL6w63WxZVciqNWMxqKp+fiUiOk
TBOlnOrOj+OKC1WfQcdojUbF9sLirejohiEnrBxc5XcQWomqnBQwR89FfDfXf6UZGUr8Kg6RHMaE
zRzUCYjjkzWRKbKzzG82iObC/9YJ0F34Esk4yzFiFWcqIja/OmIvMN+tbxifjm/Ao53xLAgQSQDg
Y9R8uEZqr+lnS1G9ACBH0zFEBlEl1DxAVDkmYlvMccVjnTXQNlO76OOpkrDeBXAQKoIL/cPumEBq
x7ZxaB+J4rI2mxNa2CDaVEmHBFWlzMZIdPzGHLi3LCCjiJ9JMr4eq7qfjdUSLiEr2g1+geihlDwI
LdD+wXwoXLrvNp0NdDeUKBFMLuIYwMmuAb6bg/mtTyFcWJPZCA7q+UKWMND1REhlsgLMAiKSflbF
ctrVrhMdRQvOoVRjPuVPtEIvyxjOl4u5rJ9rpjd9dvWVclHJGRz44Ke6iKqMAcJi4a73fmYNcj+F
LZpvzNoI7wwKErA+dANadp17SY6RegNmu1/5l0CNVHLJl0gMjgFXk3hZmYl95xj2Dg4kdji0V6F8
Vbq+a0R2DLsS4KLtI6b0szbSLpuX0FsjTZWUFLWoAtYXahTt7anQ0/hD9qk8o47ih8Ka8SDlPCGX
dvHWU7QSUpH+MXmS0CJIigwnSqB9hgya3KQNA0SS8+7fTPZoI5h3D8xZSsVZJ251TmDC0ubO2t7w
P5guGQQ0I94jQFbVIV6E+cWnvRZcTNH6zjh6J6iaS9CS0ks9TSzDDNHKq6yC11/ho/5G6XCFBkfH
QUDMFDCzqqE/GeCz/RggJIYPb8exjrXgRcuZJmoI60RHKkv9PhxOGS4UN2C2dOmG7BWuGQ/2j4kI
M0TV8+oFr0Ym3nIUG/s0/3vNcTMpcgsBcgVk8/6vjlbmr7Ucnd1mCUE3xiOVWCMvrUzeVpo6PUpD
bn3igo6sKZPBQ4a1eJFeEtuWpm3qBYvBIrCU5eqJteQSPTEdCLXPpE6tl34fihJiwHyTGk6LteZ6
gsp8PgR/fBTqeEkGgmkevZ1pzyFIj5z9OdtuT5FWbTYQA5Bn91SF9IwKgh6cEhFLPfkVVw7iq5x0
M1U9nvWKlr/xXlkl89oIp+gOkYptqiMm/D9dL+Tt/QYIcaDgNaCSjiYWwWOLQiGeQn9WHPbnbgk6
tyrq114j6OWBSKKMXLiCVOymwFnxBul4RGrJqqIUPiG7Mlzyjgi8FpgoVKMFKt1ufhjxs/3RRCIq
59EQLWZEVr1bzyEBq62V47d1IoRNo11NjZZZqrLQjmEsH8Li0fnF3MwjYQ7oP+uSGq+0jYI3eseD
cr4OBxSzGPOfkVHOXnPcHpHX8ncoM9Zq3nlq+chJ3Y9fiw+6OW7oRugb9RhCMj6r097P3YUAh64v
bZ74DaRJ4TWuZ/eoRueV+Ge/UIk676yCKBJN0f/Wpl/WlRMgv7orPL413dbkqG/FKflm3oOFKuo6
lEgc/ZWDn1ELSrQgSAID7Sa8nIg7bhNqffFa615/+o3uG4RYgH6NEkY/yUHJROL8qwVyxfLZVSK3
VZWWNmhGjfhApuRCMxt/jHWQqI+EC+IhiVBYUlxQwZ7HnLeFwm3ZROj2R12bsjvlc/XYVFwKspkR
dZwS6wFPdywAUQqOidLhcxHsj60FUF8BEV8ZqAOy6/T2sY4zXamAleaNWBQQugeKxQVdeABcq5P1
fD7Ae1h25Ha/DzOyIGTAyuboU6/I1psWvGiKTyJYEpsaH0r3I7vP1uLY/4q3X+L5QOEJIKwGGt1B
MdVBUOQew1AmwP0wIFvM+/O6zNGqLNpiPEz6jemOwfFHJ7pSacYduCmjqJrcXFZVntDaEbBZVC9p
Z1fOxj+Wyk6wFdzS8tyD3lyz5s3rd/ohM8S/P7TPYieb5yQTYwMcOsRudCbi97+T5OhsIU6IEHH+
3r3EOdkRNnGlhEacmAYU31Juzd6b5AxIbxuvJlZMNYd1Lw5rTLoU29ZAaKztv9ZqJsOjP+OSnULP
VwcORiGBIyJt0tlxAg3Ty1tAK1rf3BM0uYjcDrBcdaQW0wlC9ZbQJYXs6rj4MEDciIcOzqC7Kv4n
ZSlMObDloj7g5xI+ucZZkguQu2heU5Bk1EsO6iqFfMHVyLnRYHJPxd1p+wDZrhKxVfoppN66ib4Y
cmJn4gyms+EJh7aRJv3VTmrfK+QpejCL0/TJAdgUw587zzDD1T1Zd7xV0Ozklxhe/RwtFjPaZAfV
crUmSzVfBKcQSKs6FUDZ0V0wLt10qeCcwsC7i9mPaGC056RTQyVlLtTCUlsAttH+tEhZA68ZLaCS
lVhedxv+N1ywxyg2zE9BFMRT92/8fW3XlLVtCERK59LPTuKH7bn8P0t/uVPMOWX0fqZqpduKE5Db
bWURRejIu+xAjPiiuHW+wj84IfL6yPCC0E7CblB+EprpVIj49ZlCdsOxVXOGhcahV0gH8qyGab1j
g+fqEnXTheeBPY+Z71qPqCedX/IC42GgNnojM8oO9gtDU7rhRbMjffU5LHjrMF3JvSz+Hqop/xcz
he7obVjv6h7cazi4HbXOxEswZVzv/b5lolRGCcWs2cZSeOJNVVq92DKT5OcdIwydC/9K9Zg6z4Ty
T38GjJbbwE2OZkOB/5Vr1AvIkMtjavJEGSUtiQ3kKCdYFv4pePJtQdand2A6aOEJ4//bMwN4AoXH
f50jAFsvTBw3ZN4ikJyYnCGDTJ9Sca/iq9aXutPLTzeuUQN897b6rSVlf43PydlsSVs6pVq6Lwds
hSRAABERPH71cBfFvfW+Qffs7J+J4ATZ6XIBTeu65jRx2GP1sThPAMQLiGk4K65p68Bj1YvdCzsG
hXHNF3+RS3IeT/juQHPCo2Oxe7MDDAmGT5yC9/AnKmm/SynMEexXDWtiwN77lKu8Fp7w5/fuQfFC
Un/YbCNCAphOthF4xYWZNua2jFZxJgtcg1YbLTOObi+R7Jtu9CJQLD23i7wYsS2gqq2SeVa8EZdA
EGYAOChK3zEtUtfKlBa9ud87Py4tJrsGxKLGriD2IwWxcJjwgnNU8wRScK1xqZ6fY8pkILopx50/
F8E2SmwZ03EAv1UIZXchfaWzMIgMg2pguf7Wll/TCCtpbG6VDkxHpWfxIupXTsHL378jHiSCE6e1
ldvTF0t1gcOnb3ixuYn0RWLbNwWfvl/Lz86K062Dzusqzf/aDEEZ/rjzSlxp78bEppVj/2FO9z5M
XSxmI2phdqsye/KEcNK2cbC5g1sZKnGyZDUBdJdEPhvWiSc5RrhIIBZCkNwReGwHwKgEBQqfI8+e
bfnlhAEFzDwDU4WH2HA9JSjoPJu3VOh01zPAXl7vwTkpTyBzfwjRq8QhiXNMXzxLtK/JFf1jFkCe
KJtf3dJUQ5fWEHXCaF1WVtpDaOXcbf/PA0nr4YErg2r98zC3aJEzZ2MJk4Wg4iPy1/Zd+48seDba
dRpWv3QcKh5slisEgvDArY98VQ1C7+h5F/5cVeFxe5OfR1RVJkUNrL6py1V7gypHXaPMOHiv24kh
6/FyJOs+ftX0RBYaVarlxPZVR45C1YJSGDJOi13cxrCb775G1Hs5DRRixH+MDDnXzt0af7bNBChc
sgCcdgnbsIqbuWS+uqEc7rdfBoqX6furnjpny7h5o4VwK0myrH8Eg8Xew4DVJLObKtUmUv73RTWk
O/WJ5ndK9yGSnoDezf1LN50knP6mtja33grQKVCUxFHWWQNjDwZ3zosNj0+5A/V8aYFSjKbvc1Cq
4XfroMGBYWosZBr+yGMz6TfZLQNlQlo5scLB1uQ9uuuVuNuug3dN1NcfIV5fIeEwFOS5SWK+Zsp/
Xg7X0NM/Cc2tCzLWCgFRL1DfzB8UqevAcB0mM2DhZL8tbWex8WM6XuosRvbvSVYKYRlHRMgsrCq5
GlS+K2yDa51Uzn3sqFepaj4Ks+lTXE71YRq8nXVXC6cjhMOnPsa/ZqSEG9rwnNtbyxFhCN2ILcQe
KqQKWwTeNRipFL75wPcwKnpKWujRycBx1MtRg9fuGfnO5ks8BLizSQYsuzK1PFLpfRZBwuzampDm
jcY3/46cc+gl4fe5FLHmxDw0Wkpo8tF/B4z5l1cyKf1pa5f0rQ46M6AVgYD6uoMlWWISL67aG/t5
0bfPlQpraXe9V/4751lu7s0kg6663r+n2BvE52jFupcTiOF6N8xxhGB+5EeahGfGenot/FvEtZxc
wrYkkRD858vIPQoNDSXEziH41uJVkB3f22JBeNPdIe/PK90Pnxe5dRCeklcW6EAr9r3jC/LFVSHS
qauqmwTXn5rCg3/kZ/Ocf31/xSqwhZ05SFdOP3oKCclr1SxT8hXd80fb/LYYPJZnfFSmkUZqG1DJ
3NPpUBkxnAib2Eqw9XizG04gTNqqdAZ/30oyXlolIwgjf+fiU+KrdDaxWuyekpByOPwDV38oIarf
BIgh8SGdV7/NA4PTF8qNWdcEaKiM7YjOifpZ/coVp7+OHZo2Hgrz84Tetoo+6PjLP+/0pgHI3Niz
aYeD9uMolJBnmXFc7yqqCaiJ2zxGRxZ1KQHb+sbPfjMidlL2zbg3cr2i8BvzfUhU57qppv0FPjrM
E9O9p4XE+rneH5Hd2UPJQeQsbRXT9b5kEoP7K6pRv6h8cwkPpN4rKSyqU0b5QRb9rQ7QjBGaCCZE
ZdkLDKb8ekprkMcDQejdinwF3kxP20G3FYjUxx0zXE1/WARvE8ARlmtzBvvuFsTFpVEA+EA7NRmr
fCVSZTHXerwwctqomeTb2JS47G7vxmY/xxb8ckm+KkTXYTZ8UJ1W1OTiDyrzbHfhpWts9v5KFe7k
97uYpGBsC2kPljiUpC2xBm5NqWTUkDdHWgwsS04de0NnqijMJ9p9G3HdoXnSdghLG7jiQiVQrU9T
Zdw5+Mz5NfFA+5tDRsCGWrJ0+PSA3JDoNkFBVxcJlbzDTcOAWtRhi8huhaaNp7waHeVjPEdE9b1Y
lNtQ6XVVAUq7N1JiCrEraJQ3nymN+93YXSGvRO7LYtiU91gsAacoVv4bJQ5dcFELvx1zMozckGvd
jM0qR8n3GE2foT8n0o5jUCAs+wWCo89k+H5ENvvVX1WCSezClHZ+7tJsiYEqedbBLBTNrdAeqFb/
jW6dYzf5Sr1BKBJimyqWqmO61FPHPabCWR+iDvSwFrJXz98JDfWeBYxmCT1hqpssli71uBy+y3qh
BqQwW7WPKOCWijOtGhS3bBq+xxuk3i0j2PfszwzVx4WGVJZJ4S2Luo9Ml4AF1bgNpjP2hcH3dH0s
VXtEykovyIhhMqSVjV3dclD+oNQvowg307mCxciECr4xRzku/TYgTDhhQovXkjP5VzyaYSfyWjXz
hGSxx/CDHfQnQKARMCCEYou1PuY/xdqrTCT15zO9d4DvmqCXgTQUKnmdMtYFmMEEYJG4s8mxCl+R
h2RxPB0t1gmK3l0XfMAPs6eRoI8tIerHwm4mWxqP2kZwkkyuXT/ruiSwgxnt4ulc1fEYCdGWBpDP
OFINiQseFeiV4hVLlb+iLPNlS5VurfK06vGVZfjTu7LDPA0gPtO2V+M6q8AlGTLjqm/9WqUhLCaa
cpajYREUapg3oMph3+L7CtrYWWy36eabsbWcuq1JQNlHWovA7BbvvjZ0CwHg393LZdRnb/Pr/vcA
Xs0qy5mcSmQgm6sQQuYlnFjxK5Y6ykAYCz6Y5c4TF4oKwC4bCOpOkWJlH1LnzQ6FNsf/3BBFkNOl
EBadKN5tdprYFEAWl83zOViZr1c+RYv9nWYyQ9zninyCfkcRZM7OaVB+mvFMZ78z13OPA+nhntfU
4t2sPUpsQ4ODaQQ99SDdYO1xYfwsCYLAxaT6PPEc37by3M26EI2B/sYRV9USaU+Ipjwyu5/Ht1l6
/crh95WUSHNew+5plvWKuwEmH/x6ZSOj5vbVqZ3fouQYgbgy2eSgDCUb6jG0ljaave9ia30BhEb6
8UDUrDJq2mQ8xMBRuWWwfZSII+3RGdaDtFPZYSZwmGT9acUQmqLmnW5F6aO3pwG8mCvzWcvCxFbq
jHuFGWkQSVLm9NGSZhRi1qPZrBAX2rGt8SdlGw/1oQU6Xbtqw7MIUwDUcnrrW2QLF6JBRSJOFt99
2DgxdM6Y7BM35EWfRGfDM75tiE4X0jNGGOvVmrPfunp7jylCCFIPs5KXEchTKhoLJz3VY/C0Zdy5
7zkdjtmaFBqlUAq7NWwxWdYCIuFRurFa/upw7Ju4+PUPR0FLRvpMmsznnjCUzNNPGSZLGjwya8QO
mIoBfsV46Eez4xfrP6ox9eBDNNq/5eEZC/LVfv2K3ILQt0XXMDN1VmlVNv3dtQYbf43zxJgSqYXE
UtSi7a3I5eOGgaAhF3GzxrQbU9xb11hC3VZjXeJvYZxI+CVIJOfId796f4mF05tzGQ1dx6nZCDUk
eKflUUkmEWr3lCnCl/H0M0rVi2cS94B7ObU3iOVPvegCZDLjAHe+vTxRRumgOtx2IXyrDAu6SDGK
W1TY7ivcU/iAOtfhcXzuaxCT7sfaw+rfScNmLTr6foxR6gmr2USJApAXAh/xCw3YLm4Ig7mehWhZ
O5OF2CARmvT31ALbVkacP9zQ62/0FTHO/cWnTHw9CrQABzRMb6l7csOwFkR9Z49djZvzRRhqvqL9
1jU6uwf2/LIU18+O7j7KkYwoFQRkmRrKcBlGHkuI7s6f1qWlgC5PQXyjXhU43uecj1PLG9n1PrJz
chg7K0D3GHeGFKx/FhlHqcZL0zzBsYVVuyk0JU/JQv/ffpUQtVbRteHNXjXEqdIIwanFTcMZSN0f
fF1LXJRzJSkCAHekuMt3FXU8r5pqPBM33z8SoPMIKrjHEhfzLxBxKVvh7uuc5pVZLrpL+7SOACSL
hkly1NXdFU1qaRbzdtKXuQqA49oGkR2i6yyChySWWHF1t+Mwf/dQr8Ei+R1xFm56klhckYMAhdY9
I4KTTNZNenxbhSUWyvuUrgGsGAYGLvbmQZjuDXRUVy1K6RnCrUVGawpooTnb3rBphp1Yo/aLIuCQ
0VqnlN1aHjLMiXOJHN26ZFMwSELm+Eb7hktX6bsobgIHLZ8fiUhEj2zz3eXVQs5CquNYbn0zD7n/
lI0I7u8+iVBWEH6O8Ef4DdEsXFoRjGscb7GvuzaA2ZyLPw0ndCvfGO9s7UN1Ue1ZBQWWa5BYzeGz
CBPTyuA7tzmyYDhehJtp1/HyAIOJ5Yd3DJ/dtU22GIz1uPkPANIYGNiVjOWlxOQAQ1pzXjsscl9U
x4O36XTvEU7IqLwwWrXuoLpYEOrEb2HMjaNbnWin0jxnm2Z14Ah+jJ4O0RSjUQm2F0FA+YHvBr/R
Rza+9ZXa8x0J/O2+upwLQc3g9s9cZ2oIg/EwTxnwvBdEpw18mNXmTqbzZ6ZQ0/jnm2HqQmml0vgT
nVlZaB0co70pIkTlWIb5LWZI0RtjqSsxnoOv68kCp3KgcWMrZkczONmvypVogFcOVsCl/R7bSMhL
b5TpiMurQXUGQIql6d1kf931plvhJ8vSB1b+oFPgG9tcj4aMdrN/HbvN9Sa/Nu9RcOr/pVb9PHwG
D0xNHu93AT8/dadlzGJk241xwqbysxYMaJKwEh8r2+7j9svv0c7bcziibp21irfjXKRE4n3QNuSp
prP/YPUJ8CpEGYmK2XmCu1wd8H+stbg2gG8xiaso9F4l2jNtetGJsMtWECv9MaiVZbawbsL1lnQH
RTn5ym0bBjtbp4D5iQmgHX+foznFyNm6/6p62BbUe0yaTP0W3GSoAm1ZB3/Pyb9j+zLduKk8Efbv
uA/FVuqYO/a7QO1vWu91z8QnLb5vb5HlXnqLF3UG3G4wsmOnL22NrqIgauevIf2UF/jKEmEHqtQO
cfIOq7pV1/SFf3W8gA/ii0azq8jNUyOeFpo+fPOHPj9Kq+vQ3Vtecp/7bcf0pRwuFOdbtlapFwi/
hsQ3zyWkgaEhUq8KLF6ugsKNYs7FNtcpZCNcJj+D9voG5/wOgBxc+cWROTndyyY3+Lm3RwQRh2hk
ci8qvhEYwKr6fyfHh175McYh4Xy3vXwivnpKPo56/sYTVvY1oi3ZC8Oupd9Uwh7u2IaJspLvxXDA
nTsSSi4OJtGpP96XmayQIMFa33RJEjSWnX14vn3NXHZcOMUXSIyj/kUF1n/ByyADCUT5NjlFeDIb
m7AhISgpXQXKH89MHZD7FrgPDfRZuQ4a1A+l9ImRu6wOyUnAVnK+VpqfZAQTvoQw3ZgQ50iyvNFa
vjQYvvohuaMuwoTXuye1N+pfALSKRSFFF5dabvNFq4ZvGw6WlGgJZG4jCSBhRMsViyn5eYHn0yQX
PEfw8hEcCOLSTYqH7+nJcRNY9DirLKIV240PaUi1RWXWSz1FCQ4roYoTv3mRd4eIcmshZ+l/U6ad
rB4Ln5Gl2Gc0homto2OGtKVVrvjofMZuqQLs4hccYQghE+TXTsUgs7bJnokRTWTJU7bjqbVRWimI
i4ZXoEbuuNCpv+Dqum9Qq5gIGUk+OZ2qLtSaTJ3npcLvnzZBZL1yEPgODWMqpRu5Xiuaxh80O4ah
RrKraZlTii80BZvkNOw77wLUuaUq3GhhsitnrTN0lpOeTEIWlAtkz1ARSflRjjhjfVu+4qfCX78a
bi8iAxp7u0NcacXx66Bmer3CC+slVoi8nCayE603tpebfSVMNGLTwtMGmUMHX6g4om8iObx07T56
Nx+HZnOm3JU0Hx/sUGEQymv6wh/PYJRDwbMxRpeDIojDpaZs74J4Io4PA5MBxfYVtioqSMGZZR8j
VUhTUw3CWlz/CRJmxnPHhVFvqe+YcCWdR+tF4/ayqtFwmhzV7BGXft0DfkL9IkkEKOpccLIXSzsM
tFAISxCvPgg6+7E3LVJmQ2w4FlG52y68Mz2mH+YPu4jrOuy2WaLYw19CcTcDvIdPUGMGB3SaOqT9
nyz0PlgwGTKiZtWQxNFqN43c06FMTETSKynSDuTGQDQZo2YyqoQo/Fvn8UEqupwnqA16zFu1hFmX
8mXKbJINquy2o2OTI+kPfbdFlw0O9hZ4rpQ6uB7kFyvL+JUN42Cmo8uwiFdvw/RJUV2ES4nH3/rE
uMBT+c8XzWqWEi64/603FQwirrm44sKitNwnEvpx1mnng2xZDkimdOdbsS2NVBw7ZEgfy/Sq8uw7
4WBPcmWswHGbkN4txVYuRXTXaOq5i9aO5PKLunfYGBXMB01ZSjZ/5Q6EHFmKNEGk6N8nwMTLLkKq
YYxuuYfxOP+PHhF2DQWD5JyzENqmSE//6jRSWl16E4GFsSK0gDcH8DSETCKo+OAv9usaNRZXNGNg
lswGzOWSBqwNzxvUjck5swc4lnFd42dWjiYKDhReDcDnKht6mvkWITDLRQrsCoPgH9bhGQ3eQCj6
EifRmsyFL86opOgx2kfRqPW6Ge/3EGR7pNK6xtoHAgmC2Pv6Me4i/pGvUGI1J2kiZZ+4ePaUsped
NcQTgha0nERH+trPTHJDhWUhqmmhSHMg5eV9/zbrJlRWFy8Gb3enBe8VQv2VN5SCI46nZLRgdVQb
QqaaovFUtu8A6zZEOUjRtIb+EYYHccr+d42D+QcokiZzqLbY8q6hp5CzWR4F1jOROeINFbQtf2sz
CxmC4QMXGnHclzZ6SWZxre0t/3YlgIAseaApDIqDECEEcpPGeuKgklHiWACFcrnTVAL9MuFkx9Fy
x3Tu/ym3EUubWiGgMKyLAdHL+2X+bu9/aTN6afAdKDOZFUEI0QRVwbKy925Ym1EkrAl18Bg939Xm
3aKmk/nvpJLD1+frwKkrN4J9/PGHxKCEA1IQpuWTpyNN+iXQiWNJRNGZ6hc7VoCzL3+CkxkOALSL
EboIL+YO9iVJ2e8S7KVkZgvVnJelcS/TYbypJR8lADmNK1VnIL0yOZ+/4dtWtcf3Iyrb6C7FPD09
z2eCO5ffRkVLzgAf7D1ym0Y5w1i9wrF2g4PabxB6X6buc1/x9WLvl+9ynnjujOgyr9aoA2oxn9VY
mGpZf7bhH/zSuY27AjDGPi9GATVQ4wJRz9BqpltLBshmNr2Fj+rBphhFgf1OuTw6x7F87hfv3H/m
9cZjQ2+LcXnesoSchEKdDG+zaImtvuRfs2f5oXvIy4CZCB0lODIiL7k66YzlPUCOXgAKvQzo2X/0
Jz4xCg1wj08hUlccNvh5aEFaHPdyHcxih42PGjFZaCWfAOVo7ykPFUZMJcCPaLQXbh53Wi9kSdMC
Tyi459YOvlwOHOP+Xe/OnABi94/Ky5YCmzFrBwwr2LIjWL5e63UiW9EtMx0Yqvm5TWYE3PgbZ2Xv
OPEnsE7BjggndLCQKGhn8IX/qA7QNKwFm6nBDYTYVnBlPceZa6KEMRa/FQjYmetGY5w2ZDhTAd1G
kVWLwgPWbFxsPBx+RlmWCzEdK4urEMxAa9jMWqhYlqvFqTayUviFVrIg7dLdSQBHVzmirxaxiCcu
CIMJxYrHgRiZDym5Kw+qLITi0HzKfbJfauAX6yyvdn+3JNzspzhqY4dq4zV1skxljYhFoMWeB/5p
i7h6HFoP2Dok0/ce9xasT80M4hMYr+7ajIiMXUdJ3pg14rm+ScdpIVlATZ/bVDYOu0uwLEKBxkAS
eez/6zvnw/S+yMC/btpDWT53HflFt1iWTcwko3r0qRS4Yl53OdlH0z59aIDn/QWt2rs1KMbq6rqJ
FfoUpSzekclpTnOLCwKTBOAtQGKEZdhLDe6umb3ImGHNCBt3yZP3htTZLsx/6Q8znKgtqw0jSWGD
bCcvQNt7CW3C9ZZhOTFKWAE7TlXChfCAckjrfTE4ouON44RVkF5ErrBxB/tNGteMFFx9VyufcRcb
TA2/AB2zdwe0owxr1IUBX38VdfV9U6SkjN1siwKsDkGmZia8CyI/HTKL3jTjJl1psn92bxFohs0e
32VEsDhu4dcrne2eUd6J8xqd1D7VuI4f4MklcXqtsiX1fukRGCFXmoWYWsFcPgB9CGJ7VKpxh/83
OvPnmYMWqYW6sR3z7fxsJPkXMfJws3KnwwodeiDHVoplUZOwaKelpd9Ty7VhphzfiHyRH/K+JH/g
/gcpv6ZnyrwP+GSgPIaLTe1TptrUh14BcDBxtuZmvVUfW3cZnfrWC7I6pGjsdfQS/i8wUqEqp8dc
arwGhvGREtxHx4E+d5dL2ZbzJDFUhyZW+5KtTx9hqnNChzNed0VOBP44xbrMt8RhPg+wJtm0EzJR
t0tTAQle9SjMU+hN/qhLC0VjF5JyYQosf/+wujsQt6gGqJDezK9B4ac8vXKW9lp6lU3whLI4vcgZ
9E2n2sslAd2BglVM95Z5aij4k7H+XuPH1LWHXrAl6RjTp9cKhOH+GDoIlszjEStAuH3DrPVhXqHk
He1jJL9wabrXoJgiYGnNpqmknexl9ByRQlXXvQ4d4K0nyMQ55VcHMQWg6vSojxwpoI5rssgDsoq5
eV/Xj0lR4W7h6FRk8zIwVSn3gUg0lN8W7ZZvGj/269DDDZh/QLXJUwhK+HNWd1kxyV7XAqM7eUNu
ORIxPh9gpBQFfoiOp8JvrWRtsGZvU/lBaWgN7HdxJCd7OLXuuOwPT23FCgyTEEtHv2sUMQ8+AofE
54Go4mncJ+FTMN7RBwvWPhztOwDRA77TSfUhydLUQuRMBG8lKtiTT5Pk90F/2iOdxuyTUQkylSH+
6sRAhn1WSrAIiJVXuMxgJtGLlqT85CYsWKONIx34pRSMOo/RtoJNA0MlVl0V42hGVeJJSmxW15LT
PRYPGO3nzaxAHJ1PqHB0anvm4vUcV3WX42q5ec2kWPDRvwiPCGmD1Yap656QVLoh1ilZVha1lA/g
1jnqWuloB2fbZQmFWitlmYpXyWt9jRdyoJ/a4otd4+keDog8gVn63guV/GPXj4BxnhUY7sqt5QvK
ADV8SrBuIPOrL1jrAIg3qXNppcEU6rIe1KPi4Wc9Dm9CJ/6gUmPIVDo5TayWQRtMMCL838zFH1Xi
wi/jLGA+6ag4wi+aN65ZQ+h3LH4x4t3Vy/82IXOldASq0XpE3y7I/MXajwkBpD1os+1zooryZg86
9zq/aveLXP1VIqRON20agsM3j010fZki9zJH883CYSc91LYxGl9hspIBvm6u0WpCiNn25DA8hNZI
1ZRXQnkdbpnLH4c6Vaj1c68alG3Y8rqcknK3BjNHm8DK5/dS9eHco8qr4YnAk/mhnaOXedhu4zgA
7g2qStHNhwhvP4uqsnsxzBJXhqkv8TdtLSQVJ5ac8p7CX81SgV383nlLpCyglRTK3YZC0ux6Xjeu
US8JpcMAjJa+JPe8eSZL8+6vgy92kWCRRCjZtL5iY1HTXmB9KwaWKbDY68HbAs+6pYjs7ry8InBS
nFQk8oLiFEPxIz4jqgRqlBMr48aNttcTo0MbJpJMt4zzD+qHygcHrU9aRJDrrYo9moapDsiF98zu
oUSfdlDNrsKfex6WjAJdIk1Kvggj0ARRMZo5zBDKImoz7AxHHAu3ku1ggAfYaSI8u3QtvkwNj44A
Wt2eN0OzYYx5833tqy0Z24ynuojgSE1OGf3CkxXZWOoamIyY9Uft7iJw92yWwq140Lhrzy4jYTLC
EfDypYJSDDqBuRR1SC8leNZiI2l0Lgf0NcU6A96W63pq2Gq++hgUUaMoyvucuf3Ccd7ItOzL+VMN
ecNf7ZphAby9aW0gsV73xZ1FGWZG4VyVDM2K2W+Vpv+BlcJIyDM9L0P6Hv6Wkxjqse/nTcBtLN54
aAXXKmvcPUV73jQ0ZrlZb/CNJMvMONl6CuM86a2Lhi7vbNrJ+DKEvgNAtvL5YJtIdU0z5aEayy6F
a/4yHnnb4zWVh68M75FU3Ve9cyFssYZYOT2wpePafA6tzrXAgL4Ic2fhMgPxhzMnDH3LkeEdjPAK
ozdcc3Ou0jNUE5mZJWJ63YVxd1Sfo0FyrqN2ejjfi1E+UBjnWf5Qu+CsW6dsXbFpFdjBqLPD3yfw
3P2WoYjJLD3KgrcLqG8DFor2SnfF5EM+J1sGPJXHt3VGPcweCnWjZuhEMOtFD+po8dFBZ4qBHkDq
uczyB3rV0n/Dkc2CqRGieGknJEukkDe4X4fak+cfOaJMtdeTf8/5OadAC48O0jbeaHeYEidgOnEu
KlZDvAPQm0gh3Zt7rGMraXk3wfoaG/zhfvUWiJSJPjo/SaedNCGUN8Nz/tjeKWLpvChRctv6TgO9
fj9bGhhq36mYZD0CWBCOSJoMXqXuzChQ1cnf+lXJD9MudiyUn2DYDXNj4a3GQ6s3wKABdb/9th1M
Sx3yLImAvqZWiYWXn7FfiqnxWUEcxKfZEQ5Xzs6H4f+GI/W9r98i2BLe7oDzEXpW5kL16b8az9Mn
0vTUnl7cLFWWI+tzMOY6N2XDpQ4aOoGhNnS2fcmIVxAB4kNl7pzsvkkq/EMDY00Ilr4HDeMWoh2b
MF6ZpVgIDzADQVK0Y1cZPVtNpXZ7OlD6xwPiWtaACPS6Mj2mgBo1tEPyyK8rxMNjDwKSR5xAgJXh
+P0KEIkwFPxL/IA5VyAMc92KW33eWTwSk6/o69R7hTpfRxiYY32bEQx4mG/jMmnnsH+HGFFE4qBX
3t1fRGS7xUhxYBu9REE7lCnJE0YJgGsRARvTIzit9TCqz5XLBS3QIcX7he/swfwuFX6gkBRf4W3i
YpXooFPqSi6nQ1zl+0uhGgVDwKn1+cXCV8vA3dTaPT9VpgrgO17ZdLMCZ9c5XGdaZvK7gUXBCbIN
tU5EkheE4hHvvtYdxXMN/8E9jY+ovaxfQVA/HQyKFoZzIn6XGp3/B1s0NiVN8mMGrQ+NUA9YrhEC
ZyNJ2obizLoqzSpPL7Xonm2PzQW/ECzTEn+ZxXcqs2ZzXwhDD2d8IT9r/Ng6FI6p49cVphkifogC
+ZdDaeNEGsHGeH8tRmVgV2AOWxKsoxAJfjT9K0y3tpKS8K+WCHdDrYeJnFyVBf5GoYvyvl+TGaZi
xA8tg/83yPkq4DFe6RA6HrBYDjCJAfHqGysMOET8bPeNYV4NxkfQxMG0vaqWeJP9Bahh0ZdxOJfz
VOo7EW07vGIqOdz15HhKdH1AGe81Wi4ZXk+oSHM5+px84spX4TpZteDqCrhMuOTM1pK3cIr6t0hF
rwuhCoWnXX0DVtLedzJdWutDKZ6CuyEJ7R+Opk1RjT7Q+19xOu7TZUsVR59scGqhxIQGvcz5eH/4
9OUrOc/ljrk6K/Taghb6dlFGA0On44Tuxey3buRSeShsP6/M3qGe6C+4len1FnKbedHh35aaruOc
GI7IrK5Gr0sk3QBt8j3IWke7cw7SsyVdBVOCEU04nZnE7YFfflcqYqmMDW4fUr6AaiyX0rbBle5x
ieMt/5r1NzHPrW8T7HR/FemBPjddHHOu8PYn88yCicFCY54NEgc6zQd++TmQ5utm2iNdB13+IxE9
BQwXspj4/kkcHIFanFX7VVmmTqMzjQNWYfvipyIlc+N+FGY7iDZD+IP8FNS+ytuc3wWOSbkziT0X
iWzkAyrPnf0WY5Eqx/vqCtRcobwqnrfrhlQe1hWh/TLCdt6/q5gfYl2OP553kXVFjGu9gVuVyGEa
My1c7LEz31Df708jmMwNX3ePcB3Dbdhd+f+DARkhjGSkGOSFmBQSV2V3LpzAkprb7dwoekmoQGgG
H1eJeqEUP2vLnM4ZinMetLn5pZ742tHO/S+zsnbDktlwhlza/eBljvFfk2NtMNrariQ1Zs7hb858
i45uo1QeCMX5sAbmNU86cdY5o4vgQaoEEtWSSFS+kWcoOSGBuF1FXopyrA5lLcVLZ7sIoA5bx+gg
QKzsbO3+yLIGwLTdDrNJr+ymhH9mOXQ0dkTJNBt+jqtdQOyqJInU49o27f54fi1kFgi16WhPAMka
gcu6o8/rajuV8VmYvEUHfC6CHN4FBhgr6dmGdwZBTpiJCGfj29v6sSl6+BzREnpMnRurvTTcFG/c
BEKUBuiyYOl8sGtbI1mzp8hMVXvRrotLForjV95GgXszOPjkVVygObrDQ2hGXj799XwErcusODio
SvaUYvP0XJgsf3Hx/osZP91IAbuyCCbVbOHe9GXrn8dL8NWxk/qtlm6hPRs3PaJoP0J1BrZy6hMy
tOl2i+zl4ZtQQ56GgRMTLquKp+oc5QUKrUVb468JTBmyFdOCfEJ7FDAj97VvyD+nYUipEHfrJCiI
axgagVeyVdcM80gdNNV5KODMVlgLTwNm+WAKn7ndxqmD1vrKIFx6FbrUvR8+iVxYjg0MhDY4BTua
+k/JCm0MW+m7WAErMtAb+Sn3af461LdILLTfnVH6n1NjakcbQj6aNncF7LknUR6PvscGPHEuFsth
ckJTOQn06OXAjHiFxVO59fQDFAQzKsGmH/7J2dt/bfUwVPJg9HZoOlULMs1VqnWzT0cQBUc90mLk
s0KPV+5Z/giw/0pWMjxkht9X4o1Yz2qOjAABqcOGEuqgB+haCLfP9QHWnqZvgNVjbfjGIE2pk7by
Nr7kIs2USylQWn5erUuIA1jcMVAhqopS7e2Anm1RmPwZQCxNKr/GTD08JEO7dsNoKbW2WsYk3d/n
f9tZcv+3UvSQdUv7d120Nl0iaFHrtx7bsUYJasLPr0Lwh5yt1grSh0yGM7WmPyi+3O70EPNx72wA
/wJE9Qd08ITZAI8F5cR4FyHVDXNMLpIc1b6rJURFZLZD5ITsNf4pkiPCbhHxYJaJ1wzYAgV5ybb6
wgNY6DoT2El2+AUHAJf85ftdY5+7983qOnKHKy++4r1f/H2/DpXoJwy6GfSJY0tJns5K9yq+Bec8
/eZNAsvpiY/tFFrepLCoAU06GcZE07lTAnO0leAblpkIUOr4Wp2g1FvewHFhDQboHAQLs1mAfH3z
mjqfpyuE2MDAW2DG5wnpfv87toF3SlvwA34hy4mIAei/uJJLbQIsPBHEe5HmKtVwG7xKpdWlTqoN
fxixFib6YrQm1RucDzUxzdO271uxNBDdobD7aG7sUGg/mGcdXdsPL5W5iAgqoAvX7MdOLCQu3qVq
BKfI2WQTAOXajzvOfjKxm/1Z4Wxzv0P1Lpr2cF6XEeaUPp1e/xQQ7fjLX2Bl9/+Udp7yuNtKVjNN
iWQNgMgG79R4OgfFQbQgMArbXFYBV5sb/UE5kxGhuFiy79FudO6gGhAGHBiFrpvv/qPGLy8YnVUa
1GVVm9Wlv5u8IayumGndKX4P99adPdHuZtLtZBunrmezq/zzca4/uB8azO5tJL0hrYaUzW015D9S
YRPBMMHULJMcbKc21xRskeZ8uRzw1guBnt2956vDJJMrmHcC1KgJ6Zcckzfsn338PdO5IQabFoaU
uAlHx0u4O2Sp5coff1FM7hm2L1sG/T5ctTLy5lvFA6oa/8UmRobjTDP0ikJX4yCjJYa3rnYZOPbV
HoM7iuRjyZSa/v7yOdvokE/LPLryKG0x0UtjnnGCmf5vOjPMgoKEEOkNLTjO5kzBQmvtPdqy+0B+
wh1H3bCp2F906Yf3XxlRj4JbNl77mrCY3apwmRF+7Brz0XArQU6Eu7kC96QBqDAUQb+rltYiVx9n
nEICz5gfwOKfxei+pkYLWsDM8LxPr7q4xXhCAPeDYdw15WQqC0Ogrey6dZLBNwdxgi7vNjmzUPLh
xT+rEAmF6k606kJQKHRFu/TzHBdC38NwfTyDaccq5U1UzRxXwYn+AtGaDR/NG8mcXOiWPOlA1ggj
286tiv+vbGCvHjFWqrzRc7aApViM8dhTW43YhBMwYhse1ku3odECc3o9jIkhznkuNNdExIYFDP/R
4PlfQXPHwcowz5SwILiIQe0EBXesHUujWa+OMPAnL3RJ9xt7/CbG65W5vNVF6yPOBQsbUxHbh0da
HjjBEvfs+acgJIFREkSy7OU68gIjKIsDhjU0wAeV89uC50gaBI7NK/Y2JBSJ5HY5a01a0V5F5uuc
mtnOjoQPWMQPkYnonO08VTmIgmExRV0TSF9Uk75QUfW4OIahrh/1+fHULGRZJM4KuxL3/jRcfVlb
eTv8AmN9Jb1j1DWkSrOQ5yQLZ2cSsIlNBT2IQiSzjXXFa/VodW8ubBIhe84NnhuUxKipSyl2v5EL
3MO/E/iINyGEi9xayOuHEqrtUIUnu/QK4TMkxcFEP9mehZvx2LuMnpcTcxmo9R6GHk38BmHgv15w
yfWdQXCdKkmWs+Q0L5AsK4SwG3CGCneDupD/2aJjXuWZthr3LxYL5SB9UoX2H1w5IN5nKlXToNPF
Zvl5JyLAQU2IusUVAGcPIaUCZYk4GXRv7Cugd785ykBAhijDwmE0+pHOZ9DtfTQ220Fq/ioXf7Gt
mNbRmkuJPI1WLvU/gHINYOJV7sD9aS6wnWneNM/pzQ1YkgDunsWnrIKeVoouzhvYbk0jirEISjX2
44SlIGPauN/nqr523TBN0drJq+clRsZ3t5Ej7OsfsoAwKX3akaNXu07PqiSNG8UtV60mn0ASI66S
/HyWngiksXqUpKE0uK3g9yx55xgTES2EX2eWW5OmWJDPWh4GR42sjRw1IqxT3+wQLyLLT4ep1Uz7
NvO8Ix9DDnYjV9bQak8DpU+STIyGqE+jt3PZ9uWzFUZuMxgy98gnU0Sv38iRg5Ahb6RAOg8Z81eC
eyu2w4qn+dNQBXjPZ+uAAAFFSYF4KQBtl2L6PJO/j4KCdT3e9Fc5++Y6a0Wwxz4CkaqgmKAwtV11
ksL6NmiSOrSwab5A5lPoCkEAoh1yb9kxmI5olanKPx0aVp4yQ3QYa1qlLZ44y6x1FLnQc1D9Jykb
N3vg9AV6JMyCQJd/01nw8mtx55XmHFUjQUXGaPtNKyR3eOrqxuhZBgprYoKqcf8Ft9y28KTIo9KN
4vY8GIklFtnn3bOCcHaPUnnwH7EsTftOa1dHTy6x54FxWSOhBHzqe2RkMw6VKFcuqJIT8RQ+1PCd
6fBkQd8f5i+m2icsQf4nV4EEWr4yCrujL3U4aKmRyPnJp3zdwKJbR9rcwPP4kTSOnL5PZyywBoAV
fYNMEyLrjwtVPwbXJ4czG5DiLwiKw02hSwUa7o73CO9hMJw4RLyoi8AOTqVEcLgpEU1cHfcgpvzl
ObJyQI8f5IAI6BZX4DKXLfkvRDi0DTOCBOXKd0csPzhS1zaJLnUymhi936KKygWVT+Ox6mXJjVNZ
wqiB2CtOXEW7qKm0JGhNtM+ThpGp0ilPkieZqmgs5m1JMlqozntL0c16lCVyyHLvKC28rZxrCn00
u8NysJkYClBqvjk3l2NEgYM5AclwGho0ZM9121jIVYNUeD9RHlmlXIWlsA4cqvLff+egTqKmFui2
qfZc75k1pcECp1HAlUUNhIOOE0GGSKaFgtObPjx8jquRdNrRuSFK7lefxm5MwpzwLXsT7zuqoZzQ
J3Kl5JdLpOcg7VpVyPjKWmGw3BPvnbMOUVOfzTPE9kjhZhgrIzFQMcdZDGaIQUXSyYKpvWtqcZPB
ypF05voY+oUEfdw5sttNLk5maxvWTDAweFt+AfIcZ4Dje16M7DMfJKHWAmGK+md0Kg1Z4jk/A+ZG
7wu91zVAP8ZJj52XwdY7R5wza517KmvCvfUCbkMqMp8WoKkauw4KztvRvlcN4xhGcY0qyzDQM3lm
teBYBkVfE78sXB2g38kmgdyEQFxP//CmmHpmGNHOpu+qfuFqoj3T1Gw/SGg8PJ+bjAYHS8Wa8ilC
M3bSbWjdVx61jeNShfYWpkQ8x0JPJ1hLwue6kwpjC0Gv37K17HN3o604TNhJo8xEPi27m1ugfO4J
PSJXlvB8xN1a0UPBFTmbc5+3VJ8FhjjsUR93cY2fdIzSmO+oJTENIodzg1OCjAsM8OlqbN+90iD3
ippzyNG3cAnxEWu7rNyRbzeaeWwQA7jWIWL6BQqP2eq9dHDqO9tpGWHfhAWwXvddZZrIBdgh5mtO
/lNAdZWrC69H/SYgWtwn/D8fap3V7PFqdj/TdOgK5vE8xYM8VpPa0EmuZNcDDMoeG1xMc/8Q0Oq2
/Ql7+BxTBxyG02qhO07DkQAow5VGrd6vf7GWbOBAQHYckN31lBhb8CpHqBuhGi5y3A/YayrvUZ7m
MYwxhN4iw31IXAkzDZArrsoy/+fnEQXGoul55hYPQvHQfSC3x6hwrJ6I2GGIQGq35d+NLjzO34U6
d1hBNUM/HGlMapEbmKTsKptRHYYlkyoO5Bef6aWmzTKfHZJfcFlzC6W8xAZh4HqusmqWX2k69vG7
EuH3gbyTs8VOGjutskaRTuUNWTE0NkfIxLJWD2303T+hNqk1l/w6rdM8KlJA8x7uVMFxSCQhgGAE
qatPpuz9GsYlxeijqgP1RqJl2Q4MU3sg5UG7W6Pb57BJlTObruFShE8RYL0MdCuEN6sKKwAx8lUq
Emjn2CvZB5nckclBh4nazyFYhNkiVGJKjRNWtHsRhsWE4X5Y1b2kAO8ezatoBLXMit+8akp/9b9p
ZOpx6pdm1Q1snRaCwBYtPlKGZFk7f3ZhHlP7dOGk2sFqTpGccGzPQIKQtHSxlZaBA5iYG5yYI0Qt
T3Gc6PoNXg5NebzLzEkADOizQQi+W35SkQSmNbfMAE5jKmF5/3hDDNaCZTuzb4uZ1uu7prxptdht
UczsA4zD9RSWQpvBq8mK19RcENYZKLv0+oHEHimsvJGQ1IIjC+BV9PIrdn72I0kS2UJpPjI6yhXo
5fCkI+kS9pRyGFWPUuWjr098xxW1wMPug5JUrFjf0hDhrlrjcMnAeVy8wtdKgBlGme6aQiG2psmN
ARuhaibakRqWBfQRBNvNR+tz5gHPk63C5D3sXFecUrsngGs3G2byF1tRdAnhFjbxDN7f6ebZ5Cfd
WoneW28WPQVXdqndyGC/HzppwexPnHzIij89Zku/4e9q8SFZuajKaA0tOwkE7+Z5uz1EIzW6o9Ou
4teGM1sEgPNKDJ8cRcWXBgyH6Et+duYXpZcq1y1oakkWEX3bFrxosE/UxihAUKKV+ZeYORrf4c1d
brhQxouA8fqMwGEqzdJHMNLUcFxorj1C8NqqHTzHkufrMdKpt6YhepXnEIPGFZ/bPQhKgUXW0iiv
p6cx6Dag81VuVAm0pOskW6Vzbiyxkij7d1GPO7vZw1rUkoSsFXNnTxsY3IMVpvepyv9cDClww4C+
WT42oDC+U3vsGCZlB+jOe+nho1cEZDkhYidOIGiaEWQK1e6ofOTT8ntNBi2egnVSL0nr29QdkDKv
4IHVR6u/ALKqdNzEHjB6p/X5XZbNn8E9siQdBkJXNApVQPvNLRIL29his7OH5XuaGHHE9fLG8mBX
w9pMHZq2E3n6m+Ha6yDWf0W+i0sURmSOaszANfVj8nuoSBirYCp+cIuzNL0gkDYfVjdJMTpdm15V
6EfeRYGE9XGT8eZ7lHHqun5hM/jsmA+eQGpP5FOGU9LModsm28rfs979HDw5zN6oahd3kr8lAjnE
J0Mu9pZ2Z2mlj9xZE4ixg5a772Wi60mX8IGjdwUDJIPPNZPbLpsSVKWPH0m3Qo9ybTvSWaZwha+g
cB30HVTpIgzJAQkjQZJUYWZuIg16PebU3dl6IzXgqM+cv1k7WXD673ELOi0bdRAcgtHO8nbZnvVv
CgW25VorhmeTZO1C9vdXxdQTZ4gzrpSDoWf224XK/2ITCzWpZQmPIhXutNni6rvcuHuYfttBOTfz
wVniSEw8HEhxjuP8OYqxt+UeTwIkB9nB6Vzcp68v4a4NDLBDct9bsFSqh8a2aNWcsVWVmeBfYAwD
8ivqfaTz6S9fI2lcPuDS1ito2xh0EGKvvOCcOlrn/uK4Pvfg17wO1BX3e8TQjg90U6KLpSM526GV
+GWUcV4rA40t5P7XvHPOF606V76etbvrUa4mBOMGFMgo/cQKoKulhQbweFPmfSuulghR5DxHZey7
QUSBFrg5dm01eBRz07+qhyDbWqnG4PbWTUxE/LHWJzZFwGtuIETcup/5WqnN+22qiqU4clbAsscp
5UAQOBJ9ConvTh1lUYLMPwDWey1lYSrWL7faoHDl1VKr/63woNnBkL7lhdPTZ8l48NMWCpc3QuZ5
eD1S9pluO+aAQCdpdinDYiYLa3mm96dXo5qWotKPsqQ9k3bu7Kciw/UTGQ8DuyafdrRdYD9oCR2Y
4OO3G9fA4j40V2u6mxYpLD9yewTvL7GzqohPaGIzpioXwrUuryNKxd5AXUvcLIV2Kr9CewWORdTI
53Lz0EnUfXQzMV6QarexTiQ/GRIHuAyNy5LzOkMrBnWnPeXtEZ1/qiu1z+QHulwDjrUFggbWwt9T
ynhXcwsJnT6FamRtgFXTAeP9lv3Rhz+DMmj+HWYmAgcKLrUZ8zO96nX32GKEpb6OziC2vm2TCGXt
j0yiNl8PsMk193pQfoj5wAbeI8fAV9PIPOQudbymu1N54Urz94+ZS62HaOYbVpuNwR72D7XPMza+
PGnB/yZIciwmeKe1Hcjk7CB2a1d3SygGQSmuPveZKo+6SfukhMQDZ5VBpv9XwR8kdWjgrrK/VMN7
voNTM6PpqQddj31RCXJzVLeSYMqfzNZKML1/Is+eii3IrnWTLJeXrhtXV/tO4BjUvY8aDKfMsTD3
uKYfOX/66ptErwRP+IUIo9hi3WEXY2sPA9fZ+dvoPjanF1kXVA6Dx1eaYqFsXB7RoqjIptEaL+5e
4547wZXr/TrIPhu2xBw0aiUyYlugoiP4yqu4HpuYmvre82HcVm0076iqJXWp5bNOCR3HhmjAsmWd
MNNYIqhX3/3l4plCl2OWKcN+VgNRD3O25HLO87GXGpSh3bw6rdpSmA8X4IsAyE7vjvV+cmv4IYFM
997s9uT0rnjtjT5DkiM+RbXKQVJz8w4yY44L37dR9sLP1yp+c62HoGAp1XvQywgrUS1d2Y/2y4Nn
y8VYDjFZwQqcV6v+iOzmoKNBnx1yxnUVkrMgsGLjky/iGtkAoV73kWx6IaJWyxkK1Ud4U8+D6Wle
JGjtMQP3ME3qMK+xnPqnPbYETcnu7xSBQkobeEg5G3pcguNgh8GqQN/o4+u3bFdo3ywO2fJRw2r0
wKnhjwQQSpJbjJnglz14D3iEmLs6pTQNCXBPZFbiuqkzpdRFBzK3yIrlXe2Y0sUb4ckFmLcYj8xK
KurD53NZA+oaoISKrRYGt8NSJoZw9WPkx4T6JFVX5Y2ekTExzg4oxWL1FhiG7U4gmvdviiisQsjj
U/igSBSgtGIcZzRSw8C39FMZJXj/YKrIIKJDvD8JyugJHexCZc0+sVCWQuN3vHmWl8qewQ3w0EuW
HJCgjCc07OE+yNXf6ZgsZENvYxFuhto35w1cFg0/RGNF8dP+DQCeWqcKb2WjnjmqK/XchOpUp350
WhqXMJS6PK872ehLLmoJvDQYRoLHqrm5kKAx8NR2InxiOn8q57lXLHt5r60qys9rMNwI7y9uJU7u
TtQDSqHTTYe4m1JeEUbpKBw2xraB/r5zZ2XbVMTxLfPt+tHyGiq9JwOf/5j3uHDZJYYtmc2xnV3Y
o9/eUvG18neDou41FAAeu5VIRBWQqvs7KGXnW5viJl6h16AJT0iKf+cfXULy9W/YYqFPZLEn1z7y
G/BStt89NjizegfagW6pRRdb1rAC5EtPfT7+W9XYtk/muS65fCW+IT4yXkS2Q1olGISsJ+Zf+s2Y
64bWqB9NOQZKbYooImwVOt6/K6iaa/aPS4dWi3rSkybff+bFKUHay6PJfM52/JDJlCdnjekszQUM
zKiiaSGBgJeMt2ZkmUsS5JNU8O0cPOxA+QUGrQJxLffsAmsRv9Kmdzcqr3+gKpsgxRCnUsaCcBXd
mDwKAVGBeUcv7ol60T6ye1z+5oGNB6ZfVanJgPTJ27mkkH3osowHjg0q0Y7z3TwOM6QExsGB/y9O
Pi0R8+Fx9ZQfDLKzAdMasTK/UUp1Lrx/fJ3dMdhdK1Cq+H70s6PgiEyrMCmGVYFy82sgPCp88eR2
sPdcb+n/O4FFQlPAzwA77dwv6xvq0UR32CQ3sABM8CZEzSPqXJaHbW69C7dZGhXQRbucXhqSYCB1
OZ3u2d6TVHNvmRKeDYS3YlWApG1Ji/O5D1fv3GvnUUzi5f7gtNMcD+sUQXPM6ThxUt+ahViudTcE
n9Fv0paUG9I1uPstcNv16muV+24LVUS9WwW3be6kCXL2nQnLIVk3lFmdbIWy8DpxDZkB9DwKqPCm
KMwxayFVPAl5MQ5S35sVcuXDOCL1W3lU1vz+hMVNSbWXD+ZfTIMP7S7h5Rv9yAIzzeorX95QbzR3
iJzRqibLqKsGOtL1zZWS0oS1Lls+k3agCOQyVa9bwuMhPy5yW5oZP82WXapCdJtoxMdFjVDdU/tS
cuvYUlYl6Xziub+B23NyyRkLWw+cPfPErHDeVXFCzrg1EwpX0oeTbX6ec1xJdVCXEi0KJJGcjBQD
2shVbuMBwlzxk13CY3c8/1k5XN6z2nq3SHOrVMDIHzAvyFUrawXep7/JOWgLqgUkV8wmZF0oi+YM
XaNjFez5QvkQWqm0Lf7J0Fc0bmDk3mjn4qNka9eLtjZjn721IRkR5cdHsqCwBt2psYbq0Shm2vWw
QGWBxHWPzOZ6KLNmLHXseGstqtDIqiPfaPtDTzGHyqb7HgWPQ95Z/L8WJAemhxQiBc0r0NUNtvmU
OdQKHmUHc3PGwyhFkBpc5wN0sb5MVy9y20e7w/3qwQGHAbfbzLi9jY6Z7uLuI7ph/6Gp7iBSQdtd
fDRzFEqL4zN4xcoY79SW9IxfAKh3d07ovLAEZeaLmjfZZbBd6xGQheiRTcp6sbpaZhbbxfjdZPPv
Jy/VeljmP9UdYsLFvm+33OlIT+3jEdoCiKsAzUM/8kF+ywTfFiKvUWmtPcTzz1XdpSmLp3ChCZOR
aaXsM1AUyl9nOdnWklW9IoXjS8lccQBaqOhiC/VJlJrOJJauI+wyJFwkLB1xxYZlREq/sIdnRKIA
yYSoCd36uxkG1R+P70vzC5tUmV0RbJqVI3OyVuOoP/1qjwBhnyhIpfuq/OvNQbTwkk2iZ2nQEzf5
IbXoaLj1ZsUYCRMtazu+8NUumSaVwdDU8AFBi1uuMDUF1Wa0oUXqQYOoZneRpfDtjISgB/i/GK4L
MtVzZO+5IMVe3DV+PbOg+n2djfa9muTB9Q0wkOxhv0WP9MCcv2ZQtJ17vBGbuBh6GfdBGuIfL5RO
WnTSHLSMsbLT2ERYeRnycdKxM6LLdtHq/FPzZSK3C8SEjBAMFJmeQoFGSlu6fAaMJ5O2OtNOFx1g
RFu2ZGTYE2MjbowLM5Y66KWd8FowIGyqrcTP2dNt2MRezZRBibRREBQIWRsDDbgGGJBFI//YnIfG
X/oJjmTbKIL0XRsH43uvWGQFFM9yBZtLnw1satApSBzRSTWVEdAkBlAXAp/E2ls8oI8xpkhA1Jty
xsuNVpFxDHzOQdhwYv+amoGqRS5fW6ORJuWQYdl78VLrqcusnYSEY7d6pImexRWjiOj3Q4mlsDGW
T9RbAbARqVawzYtb6wfbO0r6Z3kaif6NR/2B9GAvoYh8nu/YCsnlgPJh462bUlJFnkrUwWxMKv4I
yhmx8mYAeCZwqzs1CV3xx+k7/Vq/a45OuaJECgmD8hwAXKfytsBFK9xgsQO9wkp9qh9Jbs54zQZX
xwpxKJfQ9TyXn8tfdd+AWS3mfv89HOZFA+BL2JTNd/eWld3yzWvQqSB0beAX5VMKZe+37P/24zZh
UjxXOD7LNS3lmNRIGA0hgEzHOnI8em37LuNTweOMot8fx839ANnpVPZfcaPICDyvjP0kClFD4pny
6pKLrnBr7vvzZ5bLrvA9i3vML3aEQdgHtskGwShgsEfolMWfG465rulJAoCYtet+Slk1ffZ2GVwj
gFfWBDeJ5htX3DpRZrU7D2PGHXE+BjboObwuSxNj56TbcxwvBZ/lLpXfTQgAZr7p4k9DXRnnYmTr
p3glEPsjRzJBSJ1KulmMjldbzVeHv22cC5zQJHg9ip3u31Usp/tW64Mz6IfhpYvo3Bm0L33m5uBy
ub0BN1jrDneVqsel4mfX7TLQXZXCxlddH8c091xizdnIsqkfFLGcA1lH63OtMg5WAQddWG3Vlmc+
fKh2DruCDc+1KGC7R2xXrY466O0EQQ65M1Nr2B+mXe23fd3edomPDMimiv0MAxdeRPVwSu/Z0dKD
BTuGmQvoDVt+iZttUVQG6YtMjgjyjxEyiIyrcra/qQZ9+4GgP6CQ//fmdmeaQdcDRdTl1idzRKpU
DXMOqe7xxzCV1uRs8GKx+bsBLMi4oMrOsjHfUHvI8h467/IkNF3ntci9opV2rRkWG8F8cm6nAD4C
UvYLo6awJHZixK9N5P22OUiX/lp6KNC1+Y3ylWuPsPKh01cSLymie02fxL+rumEEcuZbYA5OSuL3
Na0XbIdk1rEb2YRZQaxWWoC2HJOwyjFmL6qAL+3okQL+LOob047nTy+xyfMsZgyAB8IfBYEWwB2n
VtgqMPUA+1B/GXUvSEKdiWwLHzFFV5EPtNVeA/hslDQ8pRuc2XnSqTxy/EgRWzn9k/4/GO4/O7BP
DidLeuEQt+nUFLOhlB+JiFGu7w37VUlWEeCAZOUo5gO2uhB3upSvDd8/lVBAvNpZIayFyMPAUbMj
Gv64O9dIwX6mZLgmWFroewAPSk7emw8PcxlcQAZbfn7xR395NxbbNJUvxGYKeLhvKfc5X8IS0PLU
04Y87HPmigIJstHEcNxy9Sud41gA+mo+LUw/+bwu1Y55cRAHN/SJxdtd/Z1uY208cy9UaXvZWiuV
p+TdFW7fKaojiATDdk1xJFRLE1OCwgONa9zqsJaDeZVCl1+WZb6nYaWu1+/2fsrXtvDTnpahm4d+
4hcOc7zxzPJusti8uux8ApUO37O501z+VYNH+fKNKJPOduBuBKWF5Y7HHpxhkC7JkFecOItzGBEe
Ay1rPDYqiYnPI6kH0VlD3cv1nUhXoXLCywG1P/61l1TP8eWmldRfJkOfwRGcHR1+k3TtO/O6s9JB
pM1kjCinLqJ2Uquv0FlDgglQVPNxxfNrNOalCVvnpiXi6Xolau7PCiSXXNqcACfmHgFhbGg12u2o
Wf/ofCDdZCoXycd9rt7L4N7QqStBj/mixhSysmuiapjsYPTRvNjBHHDoSXuszAVE4PBbfsZLCK1e
U/BfFHw6gktCBHsazhY+K+4v+4r9Gpga2PNCWjq6rK6DH/OpgbtUssYazybOyG195amtBfFC6zDJ
8IhL7EniaXU+4c1W1AW9zWotZK5CuhJuP6hWNw5EJC0TFMOkSsb/Hxcvwlu58/7gDovyUCv4zDvS
syc7dKoHh3SsgzNI3EZg7JIzd0E4trLlO4Ucxho/6w/lY9bIwzH7jMm/EKOszwUpfOgTxWH9mT5c
tvGywMWmhY6j+Yl9UZYIPqmycv6nBPpCNEJbDmVaf7WZpoQqdr6COYUa/DO6W4cJC4WcIuuo6NJW
lQ3MjYd2tnVFhKc9v+9fwJqMSdLk3uTtVhF2+W/aUC9tiXth/MwSR5fF4zvZ5wIoDm5sck05E0YD
SaA508Mt/awxbmUOEfu8XOyFB4ZUR8thJZcXwsXeb6i5xkRYufTNK8qgZnsLEOekzED59TzvANhd
qAfd9xYq64DwZS1FVWAYvXHST+rmfgo2judeYWiKb3YEKi6vvv6URc2IxZjj3uyZHCgxZ3E8BzrL
wnrDN2rDsG7I9xSNy2VYCXI7AyLsGHiBI5DsotM5Fs92E2mDtiypJThiRyVRwStyziv6mcqC/UKc
FeH6XyFwMMfSLwmagCsj7aTUtjljuloJkjWa/4NC1elnmIlNpfb9xWUVWckTZpQQwrzjkPdUtMrx
b3mNQHrKWWG+sUwsg8r3sCdDxAUkoIzxUL0jqwSEuAa4FNZwzx1p2p4VPZUGGTQY9Bo2UasSONCT
8CSEdTQwFETGKppJoGz+a/KqzTgNm6T7Sp3oEWuo6pLQJoRAE7qlMvd28SpplCYoafBza8s22zFA
w50HXiGCFqI4GJve2axa2PzenLmC3ZqZiHeHEMIcXmued93jeuJQVOOArde/2ugfxP1mbDadoT36
Q+uAw6RSJyYYsLnoqaw6D3RDOcpIOj/XXj7Wl7RlUjYN/nHXuG7vQUnBjX3TFQcWUN1PVImbTPeB
/neyo/4N1hpLmBVsGjTpFKcWhQjrN0PqevxuJSvk0kdo/3oCKAwJBHScKBXX8qjQjji7+Zo4p3Yf
5OM7ni3ego2H4XLCJuP7Lp1kxNJLb2gi9e6w8naKFs0m4b0KNBExxl+3A144Q68t4ZlTvmWpGXVR
+vEgEcqBnV+c8M42MIvoGuRKMj+oUst2yIbr2ijVbaB7siMYQi/1BfmCXOgKK+8lORXeUplTeacc
MG8lsGV7wyT/gyqEEB1v73ywGgrgZ6RKiCTNT4QEdPsgDYvs/pooun7axF8/hfq0CtEz0A8EiE+5
wigRT1P7v47+NaZDf2rKQMNrPMbg+B3DP5Z5oLg8Ym66ybLVkhcEFYDK4iepNTm8ojyrb35CMa/E
AWo1PVxp347fnifjIBnEzE5O6kLqr1RGZkLaKUYrP6g55pFudV7RlJx6nwqdp8M/ruq7o45/0Lhv
0hZghwEVSUcD3T2z3JMk3AidWyMrEV0YuVsObNs+wR4uoyxEQBSHXc5jNCyfFfDSCfpWdgcd9C3v
bBewxgtpj3MFxn1g8KafmNUD83FP5LVH087KEn2gJ6cE1vObHcwu0isZtCOGunPE2w1cruGFEPks
Ed1hf9Sv5+87+alZ4MdiFJXeoqeNFm3hZMDtP3I74ADMNKHExtPf3O7sh1V9WCpTry38RdOPZW7C
Es1isjD7q8HoeJ0aJhBP3nIq0eBF74Sb9CKMGSt8N6x+cvRAtc0yFDmFvSe3p1kPw4mwDuUoDCDC
y1AfkssJeq6z+pqCyoUALtETANdtmBBEhAw6qZKDEr0v21kL02nU7x2gyFjlE3rz8WVB/7E1NBVX
2x4aBP/T4dXSi2sgilsr04PmD1PCuYvtIm7G+sZJ7MPf1zpoRYwuv6zToBJaYqrjmMRhbQAGCht+
UFNzwCQeMEqwbo9OlD/gSzs/lVCfYYwYdgRZ17b+xB7HPFhdVKoUA64CJbzON0wpWyHjA73jmu7C
Px/ATMiWdPufBIewjtp5oPd30YIg7v4xymr7C2IEjDqXqCOPOr3tiB8PB8orYqA57fx/8Y6OBJI3
JaxHevzkzQnhaE/fBQsmteXv4BoJPu+/OJGshK04nqHP88zMWvzSLDxPIla6REOxtwsn0H8ErIRt
WfXiWpTm5GwVvZ9SoL6mouL1fafqDnqW5m4eN3GbVxD4yauu3GTTCb8LtnO5qSXW5TiQ5jhq1+la
JbLj7xQ5eClp204uFapqN6VLVgkk8dU2Beo8ZNjTsfqXaQActGhXIzg1wST3ubkW9OcsbzI7WJ0c
CdCmPkIzGtegx+5ITLPsKUOxBPWkGrECKslswfYix4e77Qttk10CrLpKipeth1ahxPcHKJzl4HbA
yfR+2pij4pFmirxCjcD9Z472WZ5pz5Z3MUyXKsLZvl8miGVN7DBJeejd+9tgL1Dxd+KDcm91XoMC
xzii6OLy+rdRTmOw0bRevz6RW5v/m2mgEh7Xxm/+8gRfRNgpHsHIaKu5mB+2NEMTVes4FezI0fjm
4NnjFXU6uEVE07tIGc7XFxKTRWdKcIj79cic55pw4tO0lKQDkP7A9+OUCRuCzw4IYwcZkDon98n9
XvW3ik+C+Tri9WtBlboANPPJ+1NVV5H8xdQeDnx9oh8cwQXHIvXy1bBFLYbAII5BmZZSj/pxX2Kg
2JcJy8csiffpAbUziRcJrnp730YGMFBVr5rNoMoixnNBWrr5Ucp80N35BKT3oP3DpeNe9O7r5AKy
Gb0vxrWNl/N6p0dzzoyQfNIwSf5alKF8h/ypT+d/V+puls6H8Nubd6miohTPwDGVhTgEx/2JU0a6
gQwM8OoGFEU/YvNUimuIVJ8OOBnvED/2PuPnByRPTpSqUV8EODOAJKWVKYbtDWsJef7PbHhSS8yF
KsXoSkCuxDf0hy9JwBDo3k5flhx9nKqE+TJCnKa/3TgBzsLqeCJ2NiudC5kksEz1gKrViUOUMsg6
9BRqjz2gSQZ8MEo59R1+MJYROs9zqEyxZocsNsmArByDLh5qTafvcJOfxnhaxsPlq4UiuetcMBd2
YnytAuWo1Uf/eNOIB29FxNkem7HIigthP3orVAtM6chTf42UpLRxTcwyO4ORMJKZ2dJSP4xct9GL
HiOSmyy3Wt+K0PWGUBoYQ/A7LJheI49jUtFjMpApGsMAPEFhbFXCcNsaWWBGAlNh6PjfsmUlx2Nd
OmSxDHKZweZxo/KWFG6Hxl8bGmWM5xtkrn+S3VmRIiP+nD6AtN4DuiFT8VPjIy7meCo5pO8a6tty
cbjvi2l7Ke9tYYPOSKzmxeq+Pz85k7/eKmAUsYx6zEdhTk6vMJBjEnsD2OlTGXdVXbDcLTpiPqoU
v5FLnF1NH43NCKCh63jlxxRv5D4TUHiFEKWSn6iFUnFt7VaUZOlPcgSA/mOrsxHj6tUImmYpRPZF
R+tfKfLyN2GFav1vgITkj4im8HGXCSbRb77zs1SKMjzrR3naloXUDJTYKRQj3ut85ivh53b5Fbwy
PgIssiDS4xg1O7TgGdoAjCon969aArrVrQP33ntvEGKi5ZbzBi4s+YWtHut2+RLlOFS8PzK+LA8z
QYWT8xYHoTUR+c5hZ/rwg9wLeWfN7XDeoFbVkRiaDKf+Ktl6pTVOMH8ha0nDlqWRm/8TEyFJKrOW
bMMCnR3ngZUJ0a7nLMLQg9m4IOZgyB7Jl7iuF2VNwrO9AU1fHiXVCbEJrNDgBgUb/GjzDIxMbetK
RWoExjh/UTlZd6jtEOH1dA8JhxQ/uwoGEhcqZVsElEibRCNdFdJ/88wUKbuDdEy3awo61No3Y+G8
Wtpb12KHpZv+TUFQTy63YFPYLrUPSbM+DIvP+jhoSIS96/fHpO4yuerCPN6dozvlXuMFa4QlIWS2
uXvaWCU3kgzR9pt28F6gFUs7/XA35vZ1JBOCXT5KllC0DeiReuKyi0XFOGbdKxEgUK0FLG8NYVbd
4IgmKUYN1VsyRguOBU1WBWN6Velon1ms1AEnHn8EtFcdGs+/Z59mM/2cSDO96WQKbB2LN0XM+Egb
/voMopDMRgqPtJzWeqIUDIwv8vmzUC233ZJLq5FdQ8kzHKtL1CpwaYE43nc9A9Y0gU0Bti/Hhhj0
Wy3o74JiXxZdE9HbQZJ8DefvfLVn2wxv9d01JwzNLlJ9NNOgJOx0PNThm4fVJUJ/1JsEU1BwKSYT
dPPUAUpvA78avZl9h713NlAuo+3aj1hfomu5S8ZoprRs1aaxteCHXlCeDb03T0C7mU7vOiVyOLeB
QxX//g0V9mkcfQTzFEgU1iG0Xn3Wyv2UwWroBX1po22ihBDDG4d+S7ylHPPnpbFMEpTDMo5IgIjZ
KLlX01qIV9K839qX5LQkUirH3dYx4M1Qe5Gd0d9s9vS9XvaK9Aumlsy8Ow0rsKgxV9S+ZhJxwenc
kDIb3+Q+0nUDRzCMCvsI5tUmhY/VY3LJpZ1RTsifOPUsK0lbPY72W73YGP2yl1sMwW7zwZ/t8YJz
nVrc7EMtwT0ukvYct+oK9WJ3lIffJwOd4e35PIViVk72JsdqAxx97Ow9e6XrETKhh+mYNB2u5sKV
Bgfj4Ojr0r8z4xVyOLLMi2TV+3CC5cHQmlQfleCEXMHSMiPap4/IS0Z0MWKa0K6lvyJbE2DzS2Mm
YM1u8xRx8yFSuNms79CARqyqFGw7dXAQiRASy57OlsTAKyv2PsJrH2CsqpSgl8PSIzCgK/wqRcL3
CZUfN4Z1CO8ZKmjCegWhG192+dtelZbMzP+MwehOwhmkQviltbm2jMaInI1u9zcHgDtENS1r9K/5
xR0itt5YjMRFrKib1PYxUajO4CSoTzBBZQ8CjuNKmmeiyBlROkreP4RBmhFim7qI/k9NMfBiS+4m
WPD0tBjpzFs38FXHy4ibvYgBwTIvOs9Xe10MxWNYmTJJwAg+dhD7ZI0G3pjYMWPy7U4JVXlR7xHk
cGMlHkMive5hxGDKblsAm7+I+wdtllHx/LEALc+gnLyfhvK0yQlQyN2Ut2JWNYOWmI7bnboMp+dS
0EngbSi8yfiVVSzt7krCTyL6VInJcCV2RS2T5dI4BgiHLAlxvPEvX5oPmWE72QrzgVTUfmiiyrFr
1DgvhMMSzC+R7J6LRj/G2qVWieCvqxB+6S4MNloCtIMN5OCUy743U0LT/0YB4Zjqsi2lpvgeIolg
zroDLqP1U3gtiA8GRB4eZNk12cFOLW9CT4be19GbTFjKrpMw5qb0DYbGl/0y1g9dbonAfDg8bbz2
bEqz8sBbKdKuVJ8XJZpFJ/Ix29UIJh8QhBWi0EQJVWJRYXj6v1Z6UWUafYlL9C/e6Ox3zWxzSNVy
V/4SWBHg+KE51EcJ1rmXWlJslGIu8UetN5+6E+uoqVfi74m8hQU9RX4Dw2vHYIr9hu0aJ1I6x/5C
nlfLiJ5mcsiHMOiVn2SPSVe3XWwgk8VCGuzBiSHl0Cku6+PcrEluBlT7aunjC/M7VjMmZlhVH/NC
Ios5Pfc3N274f5nRhjJHJYAuzAPn/1SEzl0a4n8dmSJrRYJZaGeGxX/lfQHUgTxfbJINfHWbpWRT
jO4IpP1rsqKXN7s/Z2IfL+zbCZlN2Pc4B4k6eRfOdqNmAJJF4UXMIaazRHz6XxATQaDMwAxtvlvP
Mj6tot5O0FNnQ5GDtYANqGIVUq+cY9iB4TIYl6hTWiJZ3iy47Oa4HqnZY+5zVeOoJwTZJe+/ZYzI
Wr4n/5ZoE3KyI9tR9tGmZi9ujeaMTv8++h3JhfBLgeFJqP6UkPdPLUnKw+R3gTxMoaXB43EMJIVN
XvL5bzbS+k5x/JqgoViBtZEBbuJ/sI5/wJeRj6k2D+IFjhx9e1MXG8MZYw7NVljXfSL/AxJz3hlU
hW8N33hmlnQsSr5uDTuqgZCvn2vJ4K8MPj0CJn3yBi0/mypZVxImjaD+NrS83LMsZEonxaAZk2ep
EQkTEGLMlGv5KBoIkm9Ko3rNDF3SAdLgpgjJmMU/55IRVg4kMAk2AB66h15c12v57Ztq91E9GEBO
8/enqrxPKoRSS8RKLWnutiUazzDqA8t2BGOnUyNMhIR9SSOb4+vySQCFsiO3y5iTSb6cjysSqx6X
7Ig0U9CdLyphRsl6/2xNziHp7On61QCTSPv3/cK/+3X2XR4QEkEp9WyQXzoJj8Sxs+vm+JIbdwZ/
6jfUqmou2pul2h1MDxdGgwmRuZsfv4yioDCWNgwMFlwO88bVJIuM83o1/5StCkBin/u0xlRV3vBA
rlS2eog4fWQHr3YbTiZ6RYjHaoFtjL2JEMcbk/0VGv4yTAlwhwPUCc96jMJz/l9yroCjnWfmfscn
zVj9chT9zeeglClnB3SL3RdhxEJKj/HFhEnizuRwV11XlGX6XGXH6ejpKw0h/vy3Ni9NJqziRIka
O+u+5FO0iaFRLm/g7yyBJH73LrUUIt/xKkM7v4hPbXCbusPMgmtQo0Vaboe/THXmMeMllTuU6blX
mHQjV8iyiQjZbtHBqQMCakRrBcmSuLBPpepaIrKDtV1WHj/I7WfSxKU4U8EqprkHf5171rSsajj4
ZbsOjUSbekVpCgBrCZoUcT/Xf9DvQcDc4amiVFDedOuUnloORnxIili+nguxC+t9op6iz2tQZO9Y
LrmXUEKvgBoNJP8fcK2+NeHbuQEW8FBUJXZMIJqlFg4vxhiurtlLDhwoagy+G1TAgr5Nm4002n6z
jOvIcL8V1ZGINeDhFtGj+qi8y7L39o6i9kl6A/Qx8AkhU7ftvoXyAxsbs33yV3DsTzEuu24/mpXV
lo50NTXWTLGswflNtZXuXsJMgR/A41r8j6ilCclWLmxTWWeHvqbyGzMd7H1V8XKZxOzMnnI5XKVj
Vfna5FrJsaiEDaqi9Ej9a8nM8LoX20D4vfyLX8A5m/KbRhj9SMXnPoE1+VzGihSK2E4YLrw7Nv36
ox5DZ/kgFdJ7jgFuAcXHxYT21NW3BVTlJkLw8ONLb1MM6hYCO2Lz/mjHecnlcZPe6cSG+nFyu7kh
Emecn4TjGuGONL+HumXAQREoiCXn7k1N4j918y14ZrQiM7XIgrHCwPvZJLUknbB19CfatKzd/Km4
JQ5GpyGnFbfNSR155lg/rRFA1JMF/J1hZZkORSfhnCPwCGzYP7iYRWv+j4TYsyofa1Jl5lfQEeWn
wnqjmhNC7ZLdCcuaaHeEBu3BSkzkuxEoDG6amJOdkjlyU0IQ/NI6az2xqBVEp9jRz3bksvu4EtW1
VLyZsd6MBAUj46VayyBa3MpoeTwYXuP78X4Z+/2bw1kUmKWn9bXKz0IhcFG3wg6ndeX676A/5UkZ
G6rs8tZOdiGjzyE2bJTEnlykpUUvP+HUz6x+Jcom5P4o0gtjjKaWoBWjAqx2jO3HhrptFDt4GXcZ
cIw8e0uH1LswQaAfFgRRYtEn50gJANF1MvGTZolDEQqNFYjmKVw9YfcgsMzqMCCtCsIywHK4Hfh0
XhMMVlTEg+eKz6yw0Ce5NDRYhjEAjazj4F48TIc+gOX7RhXySDSPpe+1K+dWU5C7HFSHvhcBoOMw
Z9bM+QrX9z6YVtH3MIqGA3AVVfXftXaKojBr1oInV1wTWHL+Xz8xXokGNc7MtcBFrUi6vcmDtPM0
8Q6FL28lr0XWud5hIPYHBFTBNCA9zbLqDjXjRAKLk2nQrV6IAxcF4CC7Xj7NbwXuRqHMNUGcl3+V
08reDcRgHAFKuv+OdIoesbhmLaHefgsTy1fjRFXXCTCy6uh7+EW3Ypf1JxOPZ37NJR4veRxqLEg9
YnpEdWhhuADB79O/5HxSp9fRF0X7SsvfYv/jDxjQypOaFkr9yibmWrgsaW8nczpYuyYrClQdl+4P
1oDPEyS2N8kcW99YWo/Z34OZrQ/f6PT6M5OrOVmobo8RixgxZ/Ebw3Uo15DPi+dfc+2TcGk6CPgD
iihvYHr4AhDYTtvLE/BDt9EzBATt5nWxXH7ArM4DA3GekDHIN4zFItAk6dI7x/mKq0xZvYjwO4fV
H3yzcu7n7GOaI8o2JG709345woOpXqut6VWoETkU+yGvZlLaM/JyBiy+dykOyLHw1fRq+WFDt3Rs
BclVcZA051/wUXx7JpMbrovDQiT79ZSsRiNk86UBuuwo9iRUrP4xq60X6fMPAsqTv1Qeq/l84XRH
SnE5dk7PqfAB/icVIMwSnqpWkpGy4bOcPVjo8J0txu3XsfcXwDu9U4XKxmn70NyQftw1Jd1CZeQV
ISV/vqYMlqKCL7jnIXfJD6ezEW6MNN4zZTMRkb0BoAmOqvL1uQupsb3s+hlhrLQQodRctuTkWRiW
RkY4fE+qCKH1ZOuJCObpXZdjL6pHMLmajSzcxTK/Pz0TEn9qlJLOPqYgTb8j3xmjLknW9C0TpGyj
8QiszMpWit2grKlKAPOEbjaGQOsn/A7YovhchxQxJhe1+maeI9M8ZnP8k026D5tw5j3gy5AT41aC
XLgIiPjBzKERihlGwqUW0OXcmaxIVXL9Bha/0PBEZHoewQcSIiCquepM/lwb0avy5cboyiv14pT5
xsQ96m+o7/G2ib5U1r2OZFd4+c/8IFJmyknJi7HHtGyRniwVtaREse84LNLqjVpIFaMv+pbcDGLy
X+3wwDaA4ViCkuMOTyNqjKzfdsEtjdHiaKYEfRKFbs8oMVkWp2dBB9DV+KQLhLse2pwf9xMWQAom
LYTqkrAgHp/EcszDjyI166srp9TXY7gKOe6YJI62kdD70Rn2ZOFu8w/n+D6VbeiGqoVUDzQB4xgM
Iyrnzx3FOJsAyPoZPDkc+siAOhrZIPEfNnhVWNTYWpVFgMaLU42YCzmEhJJKERJnGh2LB0OQcFaM
T5Kjvl+EfjmZ2aj2PzlycKcJCg81Ib+ax3ugE+TyY7qUh+dH2sOi3J2kRg100PtU+YmaQvkz3VcT
1aytk4ibL1k15DUomh8rSHw5IxH35W1MExHrfkzP1FkNgMpe1X/OTs4BQM76okb2Z3Ul2KKN+DFv
InVopRP5+0Iqc+kZ0Bp9Jk+XwyOyuEpw1vGwcK4uawdL5eLd+dQszmfJBsypAz32XZxaAZxqlnID
sHWkclEwx6IbOruJt90BwLaI7sfClWwQnKbOCjSh0Wde6nCmRFY7COuCYpKhAm3UCdJ6UdhAnyxS
PYmfl+4b95WxxJpFa9N53IX+WBUXCkqGyW/NmoGK/mymiAEVawzRp7URD7ozeCem59/nFtTlifrD
PoHjJFy9fdABsdf/IkReJvjTIH6tcSRE7PXZ6qayEq4iJjQGzAl0/UEBmOlxv1QGjhJWekHI1+VV
9tPryz+A1+2NRjWVkaI6kbajbkUtPzU32fGl9FRiSHlfuDIdlKJ6srxqAgOLXc508ZAT2pdMn34D
DVfyRsPTg+RXXxe1uuCB7q9V3wdMbLKmaKvq77kjyLpw1uSkSrAjLEcVDFsOyw/LtsUTCHp6zhQD
vBz3+X7xEBetp834/JUKo9pWfdExjp+kCSMw2sztyVV8duh5MQqDPE0iurcw9pWPrFJV/l8KyEgS
OUBXv8HhquAmvWZ/jd3Q8/moH4S6XSbDKAiyXKNsFPLq8EeM7zD8n3hWUJnL6kTtc03Vug7UF0hr
8grMDrTgBCH8jX/F3ihpWIObNm9DTPjIqIV0YrUvWQH7yV4r01hjBMpR+EiqS5MN67TyKJB42JV+
54F6FbIwCFsz4792BDV1Tz5WFMMuSIvV5Z66ZICyyqRYKJ+6dL18ussagH3NxfGJBhQhq2p2ZK75
pbzgwJQK0itaZRw6XvlZNPH4psII1LMLXtMDXQWpJIavJgW/6vzVGUrtNJIefysm4UK5p6THFhH8
c+rkPHueMv+68gs/l9vy+4Hn4n5LHPehVcQsbvgSK0yYaCwHaZY0mmwXr2LdelrTfBtZXiIFZGUM
vGygPkp0uPFjwM/iHSUymONtuHqRLaNMJ+8rGDYTfaL5pBqnONDBvNqxayeXRbIAyBkHyIuxaW2X
o1JzVh/SFBBwFdPnE3vOO1bpFsmGDpM6OspcvXoXjTizmGVrSOYOE7z/70JK9uteX7vc30UMRIzd
uVwGi5KoaV+k2Hn1U8N71TT3O++Sxjm7EriQr9NyKfPa1e/y1Nv7bwy5LWQtD9wZ5ZqQuTVPWGx5
d7alpmQLulKECVe7yjB7LkypCCEu8n5UisX1sgigk4z+Dl9mAH2TpY4SFhDdrLLaT1Cvbnh5ljCM
PQDgmBnk/j7HuvP4U9UVnDhUwAr/hpfzAGGcmsPAhgnC9UAuN8An0gmzoj3VoSpPwc4gzjARhdPc
WZBuyMOnxw7VX9GQu293hGbt8TCJaPTOKVpEBz+06Wy/UfCDrpOZgrvcddzinQTtQgl5yMJRPtvF
VfqECqtsEcDUIOFDroOD28csqcjPf236M178doyBeVJ2Y/ccRYvcZhGT1nTrtEyjP1chKhD4c4gp
zHD59N7LbVy8sPqfUzd4C1WSL44Uhm4deEUe6BYESlS6iOyiS3eDFLn+azOiL/x3GeIJWgiwT3fF
ylKQmusoI2wSysIlQoutmU8jLgWbvkFAvSlBc8ef/7R2J20ED8y1kmwRKDyufwchLYZZH4yexHpp
He3/G8JuQx4atz1dPab9tuh/cQVHHwrr6kxHnLNgVZPPrcUOnm0klH3TLUgi0FTEF+g5XbA9jH2K
zZlfDvUUhE9Tvrm5zNs5kIIfrqBpRURmmrGx2jUwTQlccEWloDIJwH7bnVVS6pBz4lhWuY79sXKx
V4T8zjUBmv53T5DNkLJqSMFxRROV4dY9xxMc29xgydnym9yQOJyt64xS/o4xTMOid50YRyTLG0hI
QwY6kITat4soN/VEekhcqzXFBy8ELnaMbO0JONl3BEiLaeGx1mXx0WEGdKMcUcIz3w1Eff6hFTde
fcgol9gEb/dvtd9HpaC1H+rneP/+CFCPwXeLxvb14x5uRzLQwMee9oF/vnroUVl8dtRHw2QwQeWU
Bp/wydAUy6B+qGT8oVO1c5M7w2yuYP54izsUE6RrDL4jAjHWyon/YSNHoaTEZf7RLYHvCI8E1SNX
yZF7noL+8RZMjceLOk+Gh06fHXlN9ztDhavUyy03lLQkJK7QXKfeKBYBu0Nv6gbjg6MiQtjOeinN
GCVpWSyR68DRuGzfwQeXZeg8p30f3yOYoRcV4ol+N90WCmXWRuchtaWhwbB5gEyT4yPRIJGwivM8
dQ/UiOrwuwca0wsuWtvkrWulEQeAMwdr9L/N66OIoeoQ6k6TYgDsbJsa2BKL5ikc+JUdmFuGk0Sj
zOFS0V7gdsdD1JFQJqT+gkdEDz1b7l1OUu0u6ppQWIYbS+PrWRW0JRxj9qRbB4SMp76oU357GRSB
if2moOGuXan9Ij9H9NGjrrCr3ul+jAdnMPQ+N59GZ2VQbH9+MFxZZCuq/BcLqvlzmQT8FexO64YL
EimlOqy57G5lYoKtZnAfN5t2uiMuiIfD3wBQ3FMMwZDrBrLITuaty6GVeGvY4JigUtZ9um3fdOWQ
k0xMhlGGzCbjRfzXsQyux2au4tGesqnT77mqBcJAA4aTjGR7maNmlmYeGQOCsoipF2QI/vmIEjQZ
KLn3uGiedj7mVTRADY1zFQ5ruipyu+4LH0be1SO4593vI68oCFLnKKWQ9+JHPowuzGoHJUjGI6dY
JhOxpiUrHQBIeYhzsakMq+pSYZ/AgfUW7EYTWBBZbeo9eE3W7vik0lHDhJ8Oo/ZbcQmWJ248V7oz
ROfnvFa9OPOVd0YC+w8Dxt3YFgzxXaIrZGXk7W8CbGRaFWNYgFwR2ylOjMDmGdjbamnso0Vb8h+U
8UbSCqovZ+yFXKJQMnf/6Cm/v/Cwv4bW7DiUfE50prBtdmIIzf/vSev/6cW7qSAuIm2gl+zcjCn/
oUFWIyqjWyKUfOrB1lOYVn1zYVCzDknXU5S1CKXpcMhjPorKfsX/e+cYDlhVN65/wx6peYN4/HYJ
kbEbLmY8PaOYQr67sPqWB53hWokQ8kKqB3N7Qr/B7Zd592ZvIh62Bc78un8jL+EbPfp/+7t7MzCl
tgNIDQFMc57dfFsSlt9cpZYoeoeGJ7iprEYwCfeaQ64JMATR1YZPg7cGTp6sIGVypSgKV0NZTjrM
r3/cyBfoXt9mpNuziTH5U/Dx5o6Ay/0Otc50Kc5TR4BEN7vhPYTaG8hmAllHzvnOsRPnz9h+TDNz
hlhmvhKtkNk3cgvJc0dQ8KGJe9qlatkQQaWyNLdbVjV3O7+jFIiJOLDjkEgK7eGnHYEhSuGxrRfC
yw5zEVhPfq4tFGBqa1ZYTxM0cUoFsxA1Ck/+duDKLD4HAcYJZ0vD3wIQsSRk+I7LvPDJ5Rr4pKnK
Ud0zHk+Vkv/5XYPwrKes63C4OIyRPPqc/GyoomFxtk2d6X1SJ6rlGWWqVlqHaY89WsQzR1HfFqev
VMDKRYBSrnM0nWywt05goVjK0OTflSnxzmWkLhj9wQCQVNyTBL0AMHXd+yQBWl+dhGYT2JEcGnxY
LeB/rpuGK4LEjhy4aPvzWPx0Mj0RNJ33CPV+YgALiQcT87Qgspl2s0GFWB+F6OwErGu3SAbv94s1
nOgWAgxwizKBQhL2gynuxTaRA1CwTYZBvejWSymxkO95Rhco/Afm9RPF7FEMNJ83LdiKC6eOwcdD
n5Q+TIjYPCBkYw0EenWjQbhlXfwybZo/GHfjTgyqd6wRlGRv0iDtffqTQyJZYDy6YrFjOrI8jwzT
N2QNQxNn17uIKNlmEboYQkWu6xQulp0d9SydE1nTW8dkBFM4zZZNHPaKaV04OHHhdV8lN32idKoD
M/VzE84c5PZsrUrD31F72Mn9lJ3Uq4OCC33e61b0IITLcVzJZ/onc//nggyxpbYxfmax50rsNCj7
4vKhh2BgfAJ5yW9dpOl8WbogLlDeT2Rwq4xMtR8bI9gyUt74nnrXuO9nISI0lgKbM9H/0z5D+Y4M
WoeQGvTnCL8mCj5OYYVoIHQtzNA5C+a6Q7x9RrLIFtLcjW+gh3jtY1yVZ1SzZhlbEjhAzGg3A5IS
3JetrCjPoSFTR4apKMqh79dsaB1ME2POt7FQeX1Wun00gHN9yh25WwGGaYRYVnJDxqly62TLEnod
x+hkkI1V1utYDOlOBM/gbLjzCF411RIGwZJPApxTKheSnl3SApuzWgAytpSE2Lrm3F6u7ZgPvX4R
T7U+riabgbv64FxDBzHVNybKvV+B5+WA46ZGxM8xk1mvYRYaGMHIEjTN2hYC8YdMwZkPlQRJtvBj
vIiynm6LEFbE7GKN3cH1m2S9q1u0zNWDIKIal+NupG3bdvVjUsPEZPTrN1/jX90NGTdrvfIOm7BG
MG1uh46YPr+VFCc4WOW7AR6Wi7bL4vTeNnLr+Vt4n1wEiMk1d58Tg0KvUt0xNEIWFM3C7Ldh5wfK
YUGlefk0rVcJClcbBw79qrlI4GkASd/OpKj5xp3x/fNlbBDFO5VzUVlGQuuHTT/IM3bT1H4cdbjP
REljmEnludPGJIm8ThzS9OpknWJOy8Ul5SELhieCkRh8rNkPb8NSYwR1FaPSQ2rjclRw6MvG/Nao
E319tFsckPiytKTg/bqTGLWNF9ahOv/dZ30i1OlqDljLwYT64PazKFpjrf4KFswRuofeeENEaQpZ
EUMEnZyMjSmTmmmchAZify5CymE4pg/5on8jvFcjqOjgB2EmT5jenaO6ueXIX/LiJgLB41cPbLFf
c/sD0muH1t7+IsT36jdQkwLGqtudGB8pvnYKo96hgr4HYZYUfYOAxSVD6gSBYOwrfoQKKw9vdahn
raC8pc2MMyAVDwy/T26C/H3hOXw5GCcgszTz7L1JnWhdp773S6aKBe3tVqF2Aw+RCVXILW5Fil83
YwbDpXCOJ2x18kfyQHJqYTZLw6ECYzTA6haqIh6GHLLScEXP/AqU5Tbg80GlpGGwkU+937sSqs48
kuJw7/iyFkIiT8jXbgqyVV/E7qDGg71+GwiA20TFZ1fdk1jmyd0g/9Pk/WuZpIUG3gK7c91yIfWQ
MP/6iCo9JYVHfY0GnDj+ArzGARvvttYVpJ4rDZPthjB1R+wuIly+Dhd3RGZMzbhnsqFu62IoG3gj
/l9aC433p3mdT65SESj4PnbnFKnKMR1PVgoQyI+YoUxvR6XAY6XiWeJ4X3rS+A06JGPkSIGnviNX
+rkac4iP7LDJWBBEwSEqsc2zoiHJjwp2h4B25mDD2geawhAWwLqVZztKYnD1sVTFMfgNBkN9UoqL
NtXw4hdHB5mxrkBSQp43gxYiZqWTHH9Rbyd0OAVygunjwbt+wOKLAI7ydR3HSujiisiYBfgiwgGW
pb16GxJtf+4syb6A8HRT6M3W1re4mvuKVmiFFcpX6KAzZcAnK1bHN6vrc/uqmhMPASRYd70S4OqX
SmbqB3BwRQCd8rPhIkcc3bDpCSjWq0BYqIp3fwmDZVqPCoDr0m/Zxox6LIaqF1Y6NPc9CpzX+9Ya
7GgNrria7IkqTJy0xrRHjIx+GgZ3w5Bu07Yiuowm0dC1B5BdhsoSVxtFhfN/DQeCaqAcpw+JE/GA
yUwhAxplXgboz9+ksUntdnUW1bUT45Aiwn5n5GwxlLMPxg9t06/75l84Fhb2Iv0JVyPTyGHCok+b
wUek0kckHKZ8IyMckY8zxfXPOnQZMOCmT6X6BKEaOBcUEscqmKOIFSglkG1sDi3XwwP7rES1sCkr
lkL5AcvP19M2RbW2Axk5tTObE2cIvz+rdN6YDiKBZc29FTm+PpOHBRW5fVQRI/Ydko4LUCqki4x8
iVFFxCtnRaJyokrOEABe8Av2LyduWQFU3fIPCww6nR5TTL1iWh3Byp/CKXDGcX7RUPecmo7u0x4G
JwVdKG6dIYZyOuNwVlB/8FI9uj40J/MWO1GVTQUUGZlFQABFhOxOdOmuKSP5uMoDKTLZfQGNDkyG
kcUyKGd+B4ujLHJWEBfoHg6P2Rx6jKVq4yCHd3mku+P1fVGdzXV2t2Gpp7+BESVuScHLqFSaBygD
SvRIo/wIBVYLYn8RidZMDvKmfzMAe95m82HlUMzBJKR+/fEzyg9Tws+nyy4do0cv4RZyUUxjuofZ
kBn8+axZ2bH+kBVILpnpZu1Ix1imYnmObvROgAVb3dNRIQqsjvFGsdGMaHFW8oJIeGeng+iKLhL2
eM1XYXE/vVYRWokWx5OOh5snF3qpgXUXNfy3k5feXDOnHBt7hxqN0spJRPew+Cc43ThGuSmq6BAR
FRtNIEkFejPW8T6+GIEsttWjrzrAPkze67Oa2Sra/h+ltOBUGjjv527Bd2pWZIPbhnysEs0DqKfd
ybI0yvrSopgH5fMnXDfrqOVrk6lr9gJKMLFdZC7MeM2V7AGCzd/U6nXDWX+I0i1xag4+hSnw+0Og
LAswPBzpGQdFn0bLsCucxvF10EvwqoeVLBn1q4w1KcQwIC7WArkmGYBpwS8ONF0ieGyjzc+CMrUX
LU/NCqjNFkSvjnOt2pSGnRJg0Q7x6ItUn5RwanDUa9Wrbnyn74U1Q3pZ/2sxQe/VrCkgxcbDv5Hl
8M0j8QtteAUnn2uJyRv49kfkS/jEoUB1AoA/yzELXaV3Ewp698wkGM0cIWll2ihRkmY674UMqBn2
xC/L0WpdS2bw221z+P056WZfSnVV/6b6tTXViRErxHN+RGFNG5RxChVL1MP5NtfMiRtbCWHp6B7n
ueP7G32gUaP1WtqoGAwr7F/zZl1x/DH4SeeItYfYH2Pu5kFsYJ/FfOFvWAqxT0iqp4cTnYe69+AF
JUs7VdBTAZiEKvgWqDPj2W5Vy7fayHA9plNja3rg5XlZn59O8+ymQYnPzszIlz8zPx2tpnEZSOyy
hEhSc2RANTwc+r5d2r9LCSaHEJ1HSe6V2jpH3qIF/BhvPceZd2mgpOlmT4vh1AIxnMtzKOVFhjyJ
0L1wFsK/Vya5DUH1UPyKjNvi2QZ7VZea8EssZvZ8Fy9kl5FMjCCTvR9jfcMQdrDww/sNmvUnbErK
CfmpeuXCGDtdU/wSrvUkYGY8XcesqNgdnhOCQjLTDguQ/wC+V4uNpNd6bYoItL4+u4wzU8gdoIyF
x6v476UMqHeAogKLoTimcnVxMlb/dUSZxWP4gJIweL/sEBfLOb/+EwwxYMvXpDV1tbf/SeFLX2T8
jiEHTvJ+NMG7e7ScdYBHhQHz9bRrEMunttzofewe1idpNOVj7GbYsj06aZGiCQQtB6bDH4Eh7rC6
4n6dGuuNSqnPlJV+lqtzL5kibbpgiRsEhKiLThRNMbFWm3IBM4XNv0+tqLvUohMxDzwEMsEJBRBz
hGZazvB4dOpEXlfF3vaURutLatdY+A5nIa0ud7gG/l5Ohn/tz5oCmCMC7u+P+0wHBbS5j6RiaIcs
hvnD7iTJ+hPHLUR+isZJV8iplI6H838reKLS64fm3me7sIH8/GFLpy1HbaIyGtdGEG5uNTZcni3/
ae3iC5rv/X3J4qtlYMe3wPUb1Ruzqp4saoif8GPy+/v4/NPKUbleHfZdoO0omFBZJPjJglutjcUN
dbnoqgY3sjS/K79OMzFQQ3mV61fxe7nDKsmjx4SS2zEsd7jfEIFV7zGsd3dPOGYX+TpmkP0G+N87
XKwhJfDCTbXg9Oz+doxAV+24uh0N/EQX59e5vsExY3Vv7jVtDaZi31vHj08oVq5Ja2MQ0LvlipIp
OwmeT6vJAP6aV+mas3V7GRnmKpTKS9wjrfGTmQuU8Onle2a4f2y8WCtEVlAHKCo9EQt0yF5UaVFQ
rVpB039X6cVN8c/crmAEs5R1ERjIpLVk3AuQNKHZdZ4/vwdxU3onub4E87R/ZC+aWjtq8U8wSp5X
CJBWX2u85ZurAVd04K58YT8V8iCyLhKs8FaeR1JeFp8ZTqzoQUSwvJvrsWqxkNbNv98TZGjy7B8T
HDshJh2NsTyzRwYcxq4tv7Oysll4ciE0CEYCvOC2TIHzobQsGhd5I8WL9z+HxQb8KscfqkTvnf+g
7AA1KnG3FTqiOXtgJSjFTqvrfuKmimhDCR56sbgqTgi6XGE8r3xdMapAC3aOAxHrR4dkcMFNFy5p
EvibjjgdEf+SyT9zCxBhzUsYsiIIOqmNIVmIONGgElWbB4a60D1HkAYXHZtIYNDa0Pnp4NQbQoHk
KM6+Way5JSAXucCNZBzc+UJqzlyiiC6W3uexGyh0C5+UGFfRGXbaBa5vZwBMOsEg6pjosiKgeBMw
FMHcPIBjnf3x5IcN+ZYqICFM1PveElq09Vr+Q45WK7IvHfnqdvXA6dt6cl33p2Hx4z4na6YKdZs4
JzqKZFmp6eZgAobW4MlRNlIPNwk0WsmGExJRqqE6BlUVT/qTDoDm1mWQj82fSHI+r1ugaHUSuo95
f2kybtsRYL4ZaqMdHAwndblIEhAX7qXxmKDFcW7/lz5HuIKC5p56luCQwPfsbWX6XqbpM9RktZ4+
hzVt7/iyJC8Nn1Q7fQiII9AyAy0nOBWsVgL6MdrIkLXnonoqTh14NmShfxiQ+mSPOPu2bx18kGov
V9kH9IIb+yyESFP3ODloHlJTto/YM9RCOdlRM3y9gxMom6vM+Rnt/SvvaKG6IijZ/1kmd1it5eQZ
pzObwV1u9WhgEZEjlYDO/no6o1fN0Ot9v9QjOrSaqY9uxtEgYDqgApFLOR42VWjSVDQ/ulH2p5Ze
WCuZlmDMmiZmk/tCirrIzm1IxuQ2/oV+KlVIva2JkWfFywIHYHd1FiVcZQbhl27s8LytQrgWKiHS
CxoIcfaeOvq+++GGgqHA3t99g/EHsLRcMRZ64VD9rxa5ARQG7Gx/6aqj4grGZU6Yxszht0aNVXfB
5ul8Pkr0GRaXyC4GhTnvxwibhtISboLVky01wiMZAN7UYqbirpXlDMiM83QZWI9HeFMUV9DnaJ/S
7y5m4h05Y4/yTefGWw62aF5dWEwd+WUr2HfT/g0aurj8RRM53qG5il2uKUmtDx9L9utULsTkucKU
cuFqpb04fB1UKcX0CBZFdaYA46qRczb6Jh4Lsl5qlcipNpgIdflE2HvI7Wmmj88UvamENWs89Jga
LOUsbXpuUyurbDHuz9qmhXraUl6OZOWUTBL8D2909640po7AAIxLWI00F7P/0rbmfipl0phwrE0o
o9x60qqj1oAakI0jDlPSPPkPMMpqVYjoohvQli9Fl6+5Vc8GB/940IKU5Gs8NzLcaiTo6CZ5/d3e
r1S4k5KQriAJWGKsAcGGIntHpC56RwnsmjIKgs1YNImqOZyYFkDvRhw1mpxjLlKIk6O/3syI2cOX
M6nNJod3IxslZ55oPybLnR6tgIDlWHF0diLJWA7H6XU5qpT4nTWrghiXCKXjwvc+Mljadq6DYIl7
FLzffBDeKnc/ZjWdEcSX18lbbL1ii2R6r5wCFL43ZaBheCx4QBgLzwqYfj+vdsUGoeFnv3OHUJne
UioM3e9zNbp/A7oEdpq38ZdCuaWEyb4SZrTbBX/vn14MnW8ln43Mn9+AF8b+o0/3Yuon1xpkNA4N
8m/c5Y6bzRIxM0xUVhET6A0Y18OxhZblCxPXHqoGp2bjCOOgaYOYbGF/mBmCDmxNKy1KTauCF++0
uxs3zNBHqHxXk+Von8zK1cNQDBny1WD9Sb0A0rA1quoVQAo06GXOmseqUQE51oJ6XI/QjgN7fY0h
wkObfmREmiWr3LIlP+5x5YHojyZcGruhzCZPcuMhsr4RETjUcxPBPbbQEiyQYZfKc64GXQJg3hXc
+xFj7u/JOb/ReQZZMzO1HvS+sERkCPKUQ3bR0J/0pi9jC0UPexbXjLaPvrmbf0T37k0lFPqnTnC/
PMVAGiYwXTiU4A5a2z/2QUXOt+JulfR0OFCmVkU1oQIaKr7mvp3Nz1ivk0YLzw9iKp1qNRYHrypg
nh8eXXqoBTFdqtfspX2244Gtyl/2RG8vdhlRM+foUtMl/clo0S9swA5Ou4jR5xeInUldW9stsSpJ
kc+6IvMQ/ggk4vibTmx2TjeYaW/mNJS03pHqxA8lE5owPLuhBD/uIE+O24RBfi4QFWMKzymoeg8U
seCJRiqbkJ/wVxOEUguJOCIYII56GabX4tARv0FOef90Y1rJTW7l1O8lzVT8woEvApg94W0eHRsS
atdtheFwt+m7Bqqia5cr4A3Zy3JOJwyRzx/Tjd2pWe1pDiblZstu6QajlK7z+p9m5oBz2EXHtCJk
sTZTKNuzv8Dz8i3uEBeDd0EaXOb4tdqt5DMumB9sFXRiXbImq78NkfSb4fRzfNDg9m0+KOm8slI1
AGPJrQ7TETesxk5yR/w04CHGf6PIe9a1P8C6umIK0ZgNrmpE8Q1apxLrQBzP2K4xfkFwKxw/HLQQ
Xe84LduoD3efCRRrhJdTb2uQDg3S+HbdxINeKNHmAp80m7rQ87feqhzDRj5xYGfpuvDwMYiR6acS
QGCxbWDX6Rem/RafSSE5jFjrK1DBOzD1EtEGov9cNUFl3qyOuUnJ7QC0HOzBzj5ugNrmWePsQgxs
Whf13gUotkrlYXTZx3oUdP1ACa0odnQW8Ta3Oh2RmArGand9EiR03dgW4B7Eg0IWq+MNMYcBMRfS
/i/rYOZUoyMg6pP/pZG95NTbMwS3HGf6J+7sun8BKhSiLpoCK0E5Q8H7XAG7FMOKQwZsmEhv6ORs
8M1wlCHDWdFLDb1BeLhHXEukYJJPofzaY2Cpy7q+sim5s+Xs1OC1AHk42aU1IURh7YLUdjtzY8el
qq6Nyuv3BD1UfAuo7sGMmT/YggyZXFhRNXD3L/A4ysSRjIzBt6kd0NZugTwv8OX2DiuKaixWCoiQ
1EfcEG8FC1YIx8P1tBBGx8ld3LW7ad14w46N4bhXV8f04lbSLJ3OGZp47KhweXg81oyFIzL72GlX
jCPlG1HYdlN4AchEBg8JKNjcw31w3xRHAklrewsvKrBXvjov5SAFxcaR1KvAxAVLNm9/7HOoroff
HzvwqdDCz1Flg+PSWX4u8Y8g6l0XCP+Ph5zseNZuEyKQ2mK3UM6AHEHdpo4jy7pPxN+js5+0oh2b
1xPzh+V/DHg9AjfFV0Ig0Ew2/6aYREHJpqaG1+QxWM4z+1sS+kSdXVzxdDzSWp91+QuY1O5eoEl9
vrL5a+7NvUox/kNl1X1PJZz78/SUuKhZiSigui+HULpJMJ2FQ6+HHv7J4LXmjUd0HxnSC7hu+Kmh
oIfVW/Ill01T0Lol54lFSzlZ0Kulpywpg7CbHv60dXst7XD1CYrtoTMc9Ho9G1ABAMcV3zzbMvkG
/uXXZcTGfGeiS5+yVLbwJr/yFdM2wfQVaFNuZZHv1vTeFIDTe0CaqC01QjKrhKBE6Kg135d8tPsA
TZq13brrGZlS1Cx75xW5hzCfKJojz0q7Lv6ExEDEKMc6lfUWbJ6goNK9hJRR3G0kVY6l5p5e6Utj
oXctAHmcPabHNTBkwwLOjol0lmx9kpr6IgiejYh3DQZqrvy8v3hu7H5I4yO/xxQGQWuM6DZODNGO
6u+qBoVeVpjLL7lS7bjf83pKD8djGFjEXeD1L6+6LpRWESvtZmGdpJKTFweLvKfMp6Z2vNNpGh7g
6Lv1SQLzPYwE4fa7sMPMymZQXKlvQGlL6YVcnX80S+BuGiIq4E75qkW0w0PTqgCRv3BSceBOSowJ
OmJ6/DZBrcmhwil2thIV+Ep9RcC0ilWYr5p1E64DRZcPsbtZIxSWz0fJHdmcp6p338MdJlGtwI9/
ZTYdfzfmivWsQ/rbPegzM92kBk8PeYTWKMM8fyYONIQYLTVeAwt7lPFX5CgzfR9luiQYAYFw0MNo
zbXqnsS5Syb9xhv1RxE1X8F/3gsmBZPaKTzn1P7jTJgfe5OCj3KAFwAuCc14iS/tBbZJTI45ls4v
cVEnmCdM+gXodGgIqb3lwiT5T5YAbDd+pgOXHl4trTZvkJbPdmMW7/MZPJ4jEQ4ARdBpA+mEQnTg
RzbQW1PN1IgBYFqKS+G78fbd8KUNJpv+uuchrguCnHLUFQ2MGDfGUe4yJzXFwFabDoHnEKXKrdPd
JfyKcXqN/3QUQa8Ma/Ie4FmUfocQxURN81A+HxAhZ7f1wD+grLPhb+g4Vro/JUOLRwyj+uUFaJDz
xzzZ/oOpSZgppnMA9/cZ0AhYIalE3QaJDwEO7DCKCInrvdKuwmO49CsRgkFkBX8Gwwahm26mxlJK
7CBha91K/WXphxXP6BHLVxSZi6EfjTNRPKpfbvYWiQKYmMOFG2kHihNVsmk6DWJEFHsDw+f5r1aA
XbSvXvBbULFk6pvl1Vm7S5EnV78t+0u08ilCLooOKJ3agKvF+jQmkMIODQG2DRrD0u3fXD7LNeOm
DbH0qEaQiPgZ/PPVOkXqs/Yq27om32mE7grftC5l2knZJuku0ZF65BCVEZq8geOzpR9CCVdOq3Tr
BxXV3RBmdAqO7c/ifhFrcxs7Gqp+p1Lvj7mhCGLuftyMmEe2wzw36ZEqrUu7CBhE3LAZzuLUF/1+
QS3qlTSFbko4AJOvzwtoi6oB/TrI7xzNsbkMZvMMkxAuBBabbr3ug3lMaxyNuWyi/92/vesoEmZH
bHjCqqysExRpe5NCHWrSMst6VHmh3ZMXm2FsFrx+H3fFJ31rhvKyyeaGSv0HPZmhIMAXL3tTs8o1
fT8zsiQP9iKtIbUSvvosomnOqW+XOzDhThSrU/VN47Ku/0uxenpPFOuPi4yB8jpQ1AdMT30WE4hZ
IoLMtV9IxO9gotjp4MUfLbvuXej7XclW6ys9M7wmI18+ZXo4ofHeebCf4ZgAd6SB7zeKOrD3A9Ty
g+vqN5p3yAJ/HUZEHgippE69stzf5H0QdCNRPl2iyTklrtXVBbIXlQ/PDh+mSq06py5VIRtUeKKG
OgULZOHfO4FFxROng2S1l8vAiqPLUtZtN5dVl/B3iMFbSrbwJ2WJaF/1/58GXJc3j7Uk7a4mZtna
qDXyexASSJce3u7b/v7SaZhJtDsJkQ/C/VdqARNgFX1CC1ov10/vmedfSMTeAOSqD+XOBVlcjwMA
GT5FpHXOzNRZQFbpHCJTCYDRoKGstdriGHqV1QJ9gLA2XkD83lcoaVk6a1hMk1t1Sd6svL6IN/M4
gsdVRUI52+WOk4j+6twTIPgHe75c3jfnT/ZOxr+R9xuRumJgN+/9d5B4dwaCpoCXU8XsR0hJc5Hh
dfR/OpOyR7von2qfqf5bKeQyGcThIOowLtC1lW4mnpQC8XvFrpHHr0sKs2wuX+5Z/XD656gsfofW
GUNJREaJMgdbUZ9RntrinfCWy28DRuesPadQhwXyUxyyPe2gjaODaTufUjATUKcmGRqyhfULP4vp
p8DLABzRcwO6QKI0FgfdqMaeMh2g1VrH9dm/LmlovwVva87kqp85rhRbR23+kgqmYGnjcfXACaRi
0L71E8h7qb/ckUHP0jVomARsl1Py80mQlfleakbqWy7fC1xZasLyGwoStbEAMOs1Y8kcA2AlMLXK
1BckuLVedxiIMnfBWsNu4KlxV5ZCEu2GNhtLXuemv6P/82ks85PKnPOIZPzKKEic++gkPEGhC6lA
W/gFpS4zM1ItKibuWnJCcJ6IXTjJXP0tEtiMEFw1D/2k1AAq47Jr5IgDTBTNUXTnl1N1j7KEy0SO
W5+PXny/RzlFJOzg9nnCF98dX5v+ueuQyT6B6GIOaLljBpxO9+JiLmMO2k2y5bIYU03NBqYNqh5X
gSjPUVOEKVPEvUu/WJVevS8YcjKs/1QdIqkDLthb1ugoUI+fi54fbmmBkCd3vyGitEdn+n5BF1q2
WJ/I/Cbl9id/YlsA/LqmwzVQfWDwRbEPL8kYqdeh6/5Fc0YGfBkCpXIM2w/iIgcj1aljIEn2ni6x
tfJ/fElRXq7+t0Oux4CzwMMn3zbbCQM0VQkGr5HTIxYNFZJhdoF7jiab64UvdXm14Fg4/tLqEcrn
B4OC1vMLfMB72PnB1UmcZ1rGgPiqsmozOUuJYdHLbjPu8Xhk7xxnNi8142cwlRbypeEurYloI/6H
gPMXTTRWRkURkp/8QRzwFHLMBQ8zoJQFVI59s/AEBz1kuvL68XZd9ClUw0NHqlzJp5itf0baxVI/
dBAekyCqpbVeR66iz+DBbLeIKMaJjDcUDxc0mURLtnUgvh/iWSJERp0eaiRETbrzH0gq/SBp7lOJ
3m7b9wJtAI4LcjOdmwponi86J/to95CjftO05bPPeSIYdPjdVy/55FfupjREEsulTsCcWr1b3P5G
ZnkDH1UU9HDWWmClIyNxT7ttD9JYFflfHPPDxpUCzYfnijrskLMeprp847OoBOuz3ugfZxfGYkDG
tF/TZwqKrIvuGT43kdghgK1905W5lJqYVHaBkn/FIvXjTIiuBSQ9n0EH3bKR9kpJT9d90c3hJ+SY
M88yvkFYPUr5BJWDIARZFXp4fVkryVaNMd9t41kEqV1C3cB/od45za/vJllpSMf6ktkKIfUjcl7r
ACLwdSZw1A2tyk7lguLOmvfeglvx6W9PP27skl6iG8vAto2VTF+7A+kjUyPnHvhM2JBp0HhYg3p6
j0QIVofozKs8plAjGyUeRor41UzhO017+iYbN2OdyO2OQ3C6a4L3kIWZ7NR0FwE2fMmreKj9vv/W
Uhs4q9buTNvUzNY+QxMm/zo3f7ksJbN0VckFbsliy1RvSbh3aT2ZAtMDYbXgf4Wpf+FCWXIuRtvX
JlrR9y5HBFA3Uqm/3RuQuMAP7Wzv5lXeXH+XwIkeqbzrtLgWuhrK1IRf+tjEXp/PL6Eu7nw92Uiz
sgZiDNaRVVAc62FdH0HcbRzTgJYZ5uowl1ZvIGprWFPE0VYhSfow/nRWHK51odg2MvS+1yCnousP
Fw5hmimeA+RzDACokQj3aZy1iIajl9RqC/2TvBmKG/G4Bp3n+D0eBhwGfCpx8e6J95ApVm3cz3KX
woomLApgfj6KFvztv1HOoRl2jVuO0x0iGvytdzzMYIpoGvmSMKIf/iwSTdkQ3PmF09krT7CJyL8i
cpn4r7sFCXCKegu7fZ6Z+frY+kGdxTCAQqwydZ/IPOr33+sBC7Ym1c+2pC4rU+U969yoG1yEmHF8
E3qZfhPtkXn4KIw7GfxDJA4uQHcOE5b53ITZUnF1y8QStCRMxNKgztc+E9DVahQFKheY2T8rgzxC
mr/RN8Rv4Csi9VpTcrEyEyTkn49DcW4MlEUc8R0D5nnx30P5s7zgWvck3GFvkbaR8aAbSYDSGU8M
XOli3Ik69dclrcoob6jaMYWy7hZgqhMUkn1pE8xv74FZIF1l07mU8zZbQu9xYRhKiPAmfeAazpyu
41Rk5gQPEpIpZKNNN2FYHbkrTsrTPtIQIqKw70yT4xUDiOX4S8Y503GOfp8DYDxuokww/Q8C3i1o
hLBrlmCkngs+HWebLofkWKZZANDYJBFDiZV/pZnvCW/9o0DBz38WXygtmISw7loeDUSC0TjROnlf
PdqdqYDJj3HCzAGJfUEbJowizl/EwF6eyKJVDrhnii7oG1ohtR4GSlmDPj3/7LPmvbhkWClZRmDc
KuWxyaGskvRL/dXwhXwx2chU1arudTieV2//KIaJtaVHFgj/S/DEn/UCGbr04Vrg2pQ7jrT/x2I2
dmxR8TLPIRcGMXAP3MZJ30RK8PQV5QMrNljuPdqj0ewPj+q+sYQjr3Vzy8fWDtSdbRtjjmse0Ix9
TRafyCbY2sFdnk/NXHEcYxrpIh5ajrt2v1PAr6DUtTHmx+mbVU+vW4uIyO1LH/SQ2OjQBEeWeCi+
zC7LBJ4Dm/oNrek0Cta+r1Xa1uECrIlPa4KlM1x9mqOsJWjU000YT6qf6Q8kJMA+Pb/SYpNQHvJV
VSv7yMhEACH125TQ1sQ1lEOe+lfPDuPMDnnoOOMdAgV36B+lDD+SZmR0n1VqQSj0Z7vYybNvPqYb
Lenm13mX4IOVNgB/P2QzEgHgWSY5kqzHjJy6AGusXo/prvkWg5GNbtj+g4TyJ2V1aYcSBfdB49uZ
nBQLsqxzaIM7fwytN6agp4LbyCOUjI6XJhcXhR7NU1hj2Xed5oTdI2nVu4SD+BgFUZmZ4w8rIsgp
0EbdEExB/gl1IdK72gl+vLfCAobw8zVX4Rup84qPjqnhlhEGCorEUmFEuwFjhRFHZZ4DzqF6bcX5
RPQY/fewR/Z4Y6ho+M2ZrNcdjVCnAkjcn5ygMuU1UaseOt0YF5BMtPgx+f5ospVYm+IQMoayRvL4
KArbhOejqdU/o6gaRBBVxhCBYrOsPPpn10tDJJmffp3Gm4KYO6XQ4VyEOzxl54pVRfA3vpiyskL8
iBmYQnC10hM83SXeP8e/wGzy/rny8/G6bErma6DZ22YJ3OINpvBha6Vqul0JP7hlFQH9OK4/CQvo
50q0vCW3upDHnVd29vTHlrdLfewjNWyyh0wSLIa2Q252sQ6WqSiZeuykzlXHbAUjCCWcIiZnRFQS
RSODWAKPs6TGbBr0sNRDQsw/ce/6jkDUJsfOxYwNgWPrK9xV4/WZ/rU54WWo9+4vCJ2D5vnuCUD2
0O0sTq19YJAnOsMKW0+pV1otlPaVm2vLeqtYEKD9i1FMEDrphoQSv8hZODNKaiJiIvz+gf3Ycv2p
ddCbKSxhQsjalN84SbGoBT8jdVMeuIHkVxZBlRIlelfkjLTY04wCIJkWGQs3EfG9jIzbXmvzKMSd
/9P6S7aWi1hiY+igcNY9LwqG3ynN0xghotI1ubgSmC3ckoqcFifAqaTXoX7K+i0YhzGGL9baZR1x
/fY5ONCisvM4CpeOa5QI81uPpa4AdVzKVL6wC/mcRkPpgvCkWj/11zQNfceAezXMKvi3T83eNmQL
s/iqoL+zaYZTdopnYTb1ysFQXXb5ZDpACmHdA85l8UrYBWXZVyNXGcx4rQW8G3gif2RIB7fLqs7l
x7/K1WGbLHVLIoA7ABlIzpWBv7jQHB3e1NTxKYd+cSpr1kJrv6Aj8QzdjLUI/IT6fHzx/4eWtNdI
hOhJoYMwpUkFKpYPtgXy+5xBoBDgCeHW5s2kEFZIJWNW+VrkaL30H2aYRiMX1peULR2XbxCg/t88
OFtPd5NPcDjBsVW5QQjhHGOzNjw7dDRv0iorJGIc3w5Breb+zWOGnyfAdroapypdQRBI6ZQDzIZj
ge6c9C8klBo4md6wiI0pUufb8QSjoMgg/OmsyD8dW1jptLs0FO3zkZapuplSokszgJVPwIwHGUWH
Nh69p0r5iBmh8NG3AV+CsTXF3HkypFav4/9Mth6SrEoPFMS2hM2Klp/m3IP6dovfjLVzNx/uRZrL
9ZTADpRzKXuQnGhWiktkSH1vKW+oHuL5968O3KUO0fedqsjMKkChrfcTywSBPBKEmxQiphYd9joT
kxz7YgUmfo9BKKnPcLG0/X2oYhH55i8jj9EmayaAVtblu9YNYYgQ7Ovpnvjn4wVy8Tr+p34ph4SY
3MzuNVoNEIN0ll49E1UQp982YxqJ/AtPI3cn5sLEpEo0X0k75XwCgeWN4/ONctyIGY+dbhkVoz3+
cywNA8en8oIb25FvMCUyGlDl/5/X8CyRYYYytbu/W1eNuDUfzTAxjE509+xZWMM2Vm0x8nxyyziy
20SA7MA8caUHTuB/Ny55dqdGokU7pDkFFBjepud3gyyw3Q4jjpVhtDRYLhKXgfcdvZ8UgbK1/y4h
HC5daq2KXaDdsFuiJQlVzDEOLpws5Q6zwWkFDaPh02ENTTP0HpS84L1QSTTqpc5XRn9pyeGy/c17
arMUbXNPUK9M4T3ou+GwdT/0iqUGvR2FnMJxyM/lxMrgo2n9dmiIaZWA5KdEZ3K7InFsCBMtJ7mU
r15pJSh926eI7g/AVVPJwS99G1sNkd8FlOej9N1wBS0I4hxLQ9r+ozPTn4SiNkmpCNCXpSoeyvUs
pGb9DEw9WKdNGX5f4oDARjdL/c6dFm2bAGkwgJqAzicCirVw6uSpZ7kevx2gaNREXI0AhVFvqiLj
qZFglM7mhEaUFGX2L2x2MNJBFoqMqhB0Yxk010Al6OfRFtDIuIGP3/NKDl2Xcq1vJ2UGTzTYb5Sz
+aIlqtxKRHcUIwCjmP7aNgH0iTy7THTPxC2CGT4AW5NQ7kB0813QjLZm503UWg5KmV2fGBjeameO
aW7TaO9QVowKs2XEoLxUYYZ5EMFZzqJJpoAWgfDh3c6KIz/XcENVTdKJBsBNalTXlqeFdcoq+iO9
yIc5AJptw2acx61R3fdEcgFumXSU4ujUA5ck9dNnnpqg/wwpCTI8K/HV8Kw86qfUcCZ2RMtb9sla
YeiCqo5KXlUA29Jk4L8kbSsOI24Wc9Ap9ifK+NdOebZxFtoUkUCtzXSvyI66/rHE3HJxMhkrihE7
zARrhO0Z11oaRO2sx8KzrRq9AwozhNcEPoNI7hnoBxFZAZDzFMuB3o0hGX9M8DGHd6n8jCyV2E5k
hL+vdK2ZYNWHjWW0wWLUToO1iVmbFMTHshmqKWiKo/QJH13MSGddoKwVgJuuISDDgNaxBjE74cYe
PzZaExxPvdPRHim0X/hFCXKTdVewRFehV+4z0yNttmAkrelNhGQMyCbm2iakEo857fnKyzeReI/2
jC4Fz5ISvX8qOAZKASfFO2V3RteKbJn1l8Xy3O7O/pFKllycXCCrdrfYDgFG9V4+DLVNtFQvGfhk
iEVGXZHv4nHifl4rsm1S9tc7kthWqCBQBYVsOlRjeCXrGVWmSUx1Afv2F06V6MzOvyWtSjbgCUs6
m5HtBgqxr9HbueDwho5bT0jQC0OUj/wzaxvxJkMOLlxx4JqnRHs6EgesM+V/CGMJ8LVufivQg7Bx
ycCmM6jO9YoT8kAiVcyICTBHj3qzUdPqStORwfacru3iego/I8yRyh8gp1LJJiAqmTtVQfAePylI
slWw8HCKz4Ropf2tcT8x9tIWikVsBSJmhqIl/CNO5dc68Q3BD2eBuI6JMgTiX18trlCEVPWcTuDt
OtvFxnQoPzz2njMzJ6ZBLdxhb4i7aL7bnXdPF3XvJJz0FWHyyNsbPLawMiXdI7tu5Zxsetl928Us
vh9z0pc/1RQASuQWcWiFlTC7nJIfiyCMVPZ8XV8MrHQbho7LtbL9MGdWoXO2LbNw3r3xmNc75PHj
2z05TvgDU9LFTCNfyFfufrRZaTFiURPi6Um29F+E3RXPWzMGa5TUqIDIDSfN8Deij2n3orI6+n7x
2jOgwPVlS/CT9TaOGASq5zNlOaAn/8zM3i8jKRCv7Og/MziVPlbnuwoZvnCOutXDCGpsug1/Jla5
VgafyYW75plQdFyhTlGL0Ot1Qxt4MucA0X0Kva/JksKOuNx97bnbU94VjWAhqg54f/gTllVhuGHp
SsdBoveosrq+NIGGGJSXK2wYUXv/SdeuSZNRprMQZsYWksg8Iz+bpgVABELXDvTNuZCVJp0h1g3A
2afY9z6hknwDPkwqgyLRUO9Spbz4+HMmonicsGM7coDZxOcl5TV0CNYAFC1uAI3gOS0WNzcVSnLp
wlgCSX1J+CUDiM92drgXfiNjjpMShoaj51U074taeHRywCLX75n+CBexoXoP2rSxXQ3USLUIhMAE
NYBTH43kmq7VlN1gfMdZRinrEs+wCQ040POFgk4Ql7ZySGZ14iG1tc5Yln4eAZj9n0YbHrG3zfFI
JYm6EqobDptRWq+DThsMWT5K+CB8uVn+HtJR8oMDP+t0uNwT+3QvWKr8yVkgPQ4dfMzSEV9kUfAK
cAs2Xl/zrAKwEdmBYzImHGjvXUhaYPuaT3b8M0C4R2uuYKkHEcMR+qUeqEx7SD50SBtUQQa38yJs
Rmd625m2ZoWi+LJkt80XI4oAX7K7KJAwEjiNo0+zTWYEWt9ZrICV7EN1ja20d10YECUA6CLTGYP3
94M1Xx2RjqPKQpQlvT0fg/b3Br/Ckh2c4lLpmQG93kdzGbuSOpEeHMVSQ9XlvKkCb2/7s0X1VpsK
pIbKoVmq5GwwadzlQ5t5L8M7WktvP4OCHdK1zxPDqK7I304QxIFWuyPD9rgx0WFX0tUT6J4gmzDq
ftdti8/jwIIdQJa5wZ0J1ecgIWHXSZnqRLawXcyilpn0ueCjCUDu81XYqqkG9NxRedj6lN2tgRxm
Cfh3DSlaqCDC16FAFyQN+e372HwYbR+koVGkC4qrhsa+AumJUOX39LzZBMkUR9AhAvvrF2IEzw9y
WD7twK/HMF7CM7iQRB56iOYAq4hBGQs+zJZgh5azhqodP7lXwvOgijRDJ+2brXOes6ZFYTTqSsa6
/BIVYe9FAsdxha+M6Wwfo1CLpqatzbIF1pr8lgxJKpsWIR5oiPzuF5G6gcr9YiIMQXKNWyY2eXxa
jIYdhUIRsoGSo5rIcLIWmI2dZBzNZDtgsuZBqf1Eqs9tXRAhJnJFcj9rCpq25RmNjUvbQYrO1Coc
WqPN1ehUJLyT90vp9IKHDVPvJwlM5H6uWB1fQySOcy0dqE0/grYMlmM8h/BVexLPOzwhlZVqcBfr
QUVDE1RGe+aSbeLyhAOem9Rfq3RvUHAzxIxayNqvXa9tvlpYajyUXbaWbxsGaoXxIjIyfw4oWqWn
eJDOYI1otyBfmrOHOluRX+vRkXkgXgflU8Pvg7JwfdHTa66gyE3MMdHNv+eu+idcOnN4De6Vfzfh
mzI5NYvpOo+YinMhl+OMw/04pZoPF6g0ku2QPTtW+nADJIaRVCBZhegvKDLUcoWLjc5rR2vvsyna
zG2/tJBQ7xkewVRUICPwBU6AI1v05lnzyaRyQ3g9ChlcTxZpGWRwzzwSMtv2LFTY4wPKbWfX8/Ir
Er/lsNxxqaeRGqgYT3+MiKK860/Q6PMVXAjWAXJZ46rSLM/Szlna6PBSLG9yLVsGamMtyz87kgnb
aplg3VKAk8obVCP8kHSBa1hb3FIcPpit1Jik8iSQ1Sn+s/o6CRQriQwnCwi0+kOgDzfaxP5Zs1br
4CHbRMXnnPk0s6YNTVhnzwEJEURsw2gkfhqui575vGnVk9yKtOPSTQMIV+OH2lniVGT6E5s9UWe3
ZXAFcnZlcwQJjdlsu1VSwADFtoz8JQ5iGLUZdJjwXIcqYXoB564FsWo1oN9DH2cAd7i7K9u2Ewbz
cpo6UAf50Ekk0ZePSE76RT7nyff7vE2FXoMxZPvVub+l2Z5xzmbNdtwy5uLUQIkhZ15/iUU3Ixr9
bnHxLkJnJUvZNbuvN2Qp7iPlPe3zuj6lGsTPsOICmk8pYLj0P9glrF7HmMjfp6EcHlrH2zOEXXFQ
VqLW9G33lqrYCjIXPH3620ZR+cl025QD1okzZsBzlyv0z5hzvO9kpMBHfbcV8u0ytXb2LLDDVla2
2NSEQRWkcPFU9TIcjKNymGxIXRault9S4Gh2uACE0BIoX+ukQZrutiy3MRMhgHm/XDEu47u8J7gj
MuBFmVj1p7eeDjWyiCFFnVfaqbQAhAaPHJCV8EZKRh5F3kRnIRdVZvsYPp/kMDxx81Nb0KhyfuQQ
pHOVYV/Zx64Z8zEJEVxwqGjQC8ihys8jb23wUzkOBii7c6KyJlaxSQ3mNbRHc0k6x2Dj1w/Xm5Jf
3crnNLLA0GEG2q1CKiWiVRcJl9+zAsOpM3KVyTaB35pVz4GR0FA5dy2LS/4QEKMXWsAXZlVfI7aX
BL+J3fJr3fBS5xGWpuRwGJq+jfA28wz14Cmhyzvju4PUDG4KRBpBGq4/nIj+C+waqmop0LVm32M2
zVfrYindnagSfp9vM6OwSnxhepsbaorKX+Ys2w8vT1SYINjkpxb6xBDlHKs5qCaP1NMUB0BinYzd
QVEIG2Io74CQxbRZC8ZjHBuSRBy0lS9od9W5U6SIsHJJfM+lRNKkt34mCDV8Yi/4yZCd/ujtWQWy
v+OPDIcbifj8AZUjZbr1oQcz6810i5zfoZ2IHZGPIVHPu2hFhNXvD+lKiw+a7VRCYUOVnpaDdkij
c0EfoeSzHmfFvWobXhzQkINfX3jheIIxUyxiaodhBdJE7JLRBKj1kt0aZKf8GYZfgvz+gdwpvEHZ
D5rTmPS0chrhOd0fXfM/JNhCsPcSA8Eimp5aLoJKXDDHZIedLGgv5goWAZ3zhfoEVkNgL63t8B/L
U6PEI2NEQTw9Ig1E0La/CtmnaOLx45rMtrzdUmM3A97cP+UZWLUnwcSwABt3RadP6vOy3+aYDEyv
+TYFS+ZTt2WVn4s3TAE0lMWhlPR21b/nn2KXTF1WM7BCRMDqAmt0zfroU1tgp1QSPIqm2kfdHJOQ
AjKjnv2eqXKlVh9ZZz7mLCTojpEIFiye3M+UJalADdT3zlTV4ZUrogCVI2Eu09RGxd5F+IqBXYFg
GmQ5zEsqUnx/OjsvhFlPy0uQkT+WuKyF0lxOIJ5Qws2vnm4bIJQv1hShyI2XNfMpLrE2HdxluzjO
OaV4lpd4VdQXrwghpjTrImdj/BUGYnL7Gon26Ulv83HsZQRZadSrOuLrNAt/ezKsfF/m95RN1WNa
jEw9HhBcGcscH1f5+2zC6COVumuSeL3udUaEyqd27zUWhHb1u2fcXcv+RSDTFZA7RLpUOUV4EV9v
9VWqw1K1IGsNndZExATbQg0HS7IVuFJOYzUkN7ux8sjnIEgCf7cvB2QW350x3Ywuiw1acI4KUJmG
b480i2kptmbFzSDRG34vxxQR9sl4isUyToCeuO5EH2XYxesRg+7YL2NCUR5M2e4PnZ1tdNslExR4
6VaaSsDXNJ6IV1vnRdwrx1OrWoiKjACetD363PobJ2ErPp9wDdzA8jPCS9utzr4Vcq8BUsS3/0LL
DsXsRSnOPI0NDtl4opcknMTUDYp2bP8nYDSHUE8V8THG1z6gOvN9Qqt8CpWYqEVMX6ASrCPUb70m
XH3pHg9mEtAJRVUfm3Ud1ZyNnSZTDd0HTz/tT3EzV9TYO46ea4ZJLwwQdvoMaLwSdrBD0U0kziXU
JDSE7gZ9X5d/XWd+4wNBnW/ou6UfIdps4m+SYjNmXmhlXxovcFu6cxuiMeWOh7Vncq2jLQOGGjvL
1bPR44oiWVBxUqPmN5dUwBsvSDgOA+mk/AcrbZaEdQ9hVMUUViwaA7v6MYeb5otyABSMWNEErvzo
xOOUPHT4tM2+81Jzsf4Zl7eFEIAE007MFmZ8l10GBOgi3ahyZzCySISe95FARCiSG56/OmJBgwyg
A1YC6i8yNDyzLIff7LNh8ItCS0nqq6xvDBr9+Sp0PWpIo2U14+fWesb/2Lo67TixwtI/4L4QOIT2
Y5/DiO7KxjHPK6lF/H3h1rja+H8/AoPVqgQ+95RDtNNr1l1ZAhyI4s5pzlgkRT5LR+Eph5tYfIcI
0NwC+Iz9gRsZ8INRiImR/lfwvUJuPJAQl8XGB8wyu0tptcGqF40Y88U0JZKKv6hnUeX74ZuX5IGd
qLEACoRWlRVEz9Ic6g7F9KNtO1FDHEWwj5Xt1BLDvbvKaLA/Q7Tp0Vs/4sY0CPm0P8ho++qM7ljg
0A+RS+tCckUs59mlXAWmZpm1ZS2X0gTWyCOQ2cz/u895eBWxWOfbihc8B84LbmLoKN00mwsFzTIa
UJEsyV4AW0l1Wm1UAb447rHBdxAY1p6lpj/kUoMi3rGpasZQuM6wAYuFuSqg27yJ/WxAUhY8dJYs
BmV8KPa4aAIr415F1IsU/MCCbPPuQ278/Pv4NXzN2mCwyIrlOQGhkIUEjyLyKrlVaJyP5fQtssLX
JKs3cewR1ey0hMJ/UCG3iQ9h68y+P0emgq6qdML0VuaFoUIWIzun7Wt+X3KaIYfWM89q2K5iaYWJ
/PqPX5hZVrHunb6gqSoLcY0niG8RWO+xZbImsMUqePc1tvjsYNoOwRmEBaTHmTn71NLH/rH2h+pz
1/1EGAFG2bWymuLErNgsE29qDgQmV6hf/px/SugI0v1Hov7Ly+wUA7X+zu7zPwlQN/yPSQhctN0A
vaRLOckdrUX6ZgfQ1MDTyYa9jwkNLuceIWXw1yOAqqjw8Ivf+qq8QKGo1NNvyggQ1bMBuC6rSRLr
T+LuuQ0cBifBN6ea4cza0iP/nixiujUulNChM0q+0waLVEQpt1wK3wGEiXCms6GBzyojh2XWkDzK
xz4XwR3kw7aCR0Ui/haX4hv78DMf8syRPGTPgX2w/DFXLEp27O8cxLa/kYxiW2zubH1+bgZtVG7c
irg65wtvmDlN54Vxfe6mbUjwOsOW1eHasgkf0mXDgJNRYixjQ5/74dTlWx9F+ILiI7Xe4DBRIgWg
MAF7Wn8QUZnZScWCGoJos+sQiePLwG9vQi5x1EmXO1IIh5JsdseubjSgMCryCTBUta8CeNXZ3g9D
y83mpH6gwamE2NLGzwEDRnqf+O9ZdhGa5j1IY/W15KaqWAOYWWsdSAtaoZvlq8wSn/pXIpAjwJJT
gG4UHzikjVXiZ8vdQNfLmp7MJiB2ceFUQP0D2BHZUM2LSBS1emjet19hjZjiMkgnq5Elvcuoy0Xs
YQaTNE1mxVylJeAd98IcImeMTFC5FkrqebWAhusiO8GG0ZnZpCHAUvMBdd8ZcgqhsPsG+HsNZZa4
ReA7RS3YC1LA0GYPDXZ/TpVFkQA6SYGZXo+RS9X300LVqIGWJK7nj28y3s669vO2KnjTskGK4y/V
mAy58Ma3QnfyJ5SOU7LX6v+GdoUTV2FYbp25FNmZtNSww3MG2PmVbkrCvsGdmaxJNKjF8Euw2Wbv
mL1zqbShJ1aKOh55KfFafqiLRkQOpeXFmzu6Wtq+OS/ZqSeniLhMvVQCYQwcGkeayvpKYZ0NqQ3u
fOBpoVf/kq0Z8PRe2F7A8Af8grKm+mmExluufbejBAAWWr16sGlWjKhkTjb1AdpL3hvkEhzuo4iq
jjGRrffsHTtOMtHvksNUquea0UOIcz6Z6OsdAMIq2IW7Oiu2T/42+VIvQ2kCCJKTq48GzKqPpofr
A4jR+FQ4BzJD2qHkej6fV2VgT3KMTKyqj+lCgHiG7AnfS72lmXxwfsoszPAfnk6SHpkMyxty8PxA
FtVouwdBoxnJD6lzPn92nE3NPbceQLV+8lC5yYNNRCDCVZYy6fgk3gMdNRdU0vhR9FcZV1lyOh+J
/6xQtxh0U+uLmgECvOHc7OMQyHG4T+Mc5oLLo+xpkpzO27Jd4EDuWRbXipDkB74K/xj0DbE67hJT
UC8Nbj6/BDGfMmB4cfEmYYUMf9k7/o6hfIXyWbF/gR2lUzNVpEGImsZBu1QGZjrKNo/ycaPGYGd5
KklQM3/RO6K5qXTTaInDcSasNQEDpVMg9FBDetOPixV2u+7p88ETZhX2MinUlb7vZwaUpR5ZtQa8
rg+Z7meth9eZCI8tUgyHxKJqSF9xUTQdrrp2vj8kcWoYse0wwc9mfEH7CsqMwMP3jn9HHPK02vCr
TtSoEEyoP0pbrdc+wuCe51ily6Fsy4KEsvUCfA9RQlefSIjHVMiOHGugyP55I6pkEYEpY2fCmIiY
nPkfSaQqPQTgdU9SqHpyoXfNfaw87TPMQcgf0tLXiSxfyGyW2kNJfkj9LCxTj7wGnHu6bTRZ3wlV
vOgVAq09xBzlpxP9mXRHBAh5udljGpVelBpmA8AdRTe07ygT2bs6oll5lyhxmz88pOCpbvb1IEqQ
5VkI1dCko5qOH91R7YZ4ZN/hCalO4E5HJ+yhSOUmyYP6zOxlrdNHoQh4caVEWlO13o1EdVNQTqd7
+vFIWGklLVzYMfk8O0fG1923OZHHzbuh/bfOvrKeKqOv/s+6GxdonPf+RPJn6LDXZWo8IPxmGZky
ku1Ly85DVAbhC5HDt0XYai+V5STL+3Q/mj7i0kky9ls7smwuu2vaxef3LO1+OXXZj6OEawyMed8i
Aboyx4DaR8Qlcolrfvwh8sG8JC96wtXYKO0KUvVHnldnGdTS8+epd05nRwhWrCIq4ZoC7HTup3Fc
uD1ty1vHzyJaCf7RMJp/zOtHrnV9fZ6mDr1N2ihKxRUQmMiKzkYGmxPq9wRYLHeODfaMDLYX1Ig9
becxn3NiH3fIp1m8rtbsgjex7Jb3uM6dQufmPk7gQ1ejqqoWWVz9he24f+SstDCQHTKlUGDZb5JD
FBDtDFHIod6817BRnMqTrtZq0qxp4njFzi5iCiVkdBMSlwx0AWeeYnJ25AyebIQlNvzo1HGuBeRl
CSffuIUD3zXex4JrqWRA9aLeftNwYqB5FApPpmIQetNe8XubM2pGZHcc/FAyoSVPf60atl2+vwm3
6YwHys6VjfcmcWr16OvJAlIbDi3Gzbje0xhzJKkUCHRnla/r/vXCI+xVi4w9GspD6ZN4hiii12Ei
gJSsMxMWgUcW28GvoT8jRC8GbN3LQ9gVkOYyfpaEYkHt3TAn6I+qtF8cTqHd4iOA/kEGNtw9yGxY
UJUYgl/sBqwdOZ43h8961Eo1g3NF5/IF/Ca6HdLklisNvYRoCM8zOzDyGGoqONm/CpWOBBjExi+x
DeOLpc6cIawsNPzMUaGVGEnaX7ovaCTaTuU6HZRu5sAJPgE/iPwm7ZKSXXufdaPpWgdbl/ume7j+
HFnWjrW6AsAnydfXixxLDK8u94nVbxWFY6E+825sQdhsYtFZG+bhUxZbnewXziPfPDwbc+Zrwxlm
yM8MPiWWjEQQw/1tdmG1VGy7rlzDE0uQV19W6Ue7WN1bYCbnSUFASpop8qBWs5qI0t3VDgjYj1e/
txs4rpNDEL5hKNpfbLy+gWtcpJ/qT0h9XIzNrIp+Vabgh7AeZtJA75iBpT+xnXhElZRbT8D6EyTj
1Re3IOFdGM6lNZjARGFyZ9y8mT7bMrAXzh01sOjp/uBvu/8nJY8gK/mMDi5bNGA/lzc1WiqnQpw7
duZ+wAo3quur4P7smYnWr9NbIyYAdtUt/4ao9vIt7EioYk+CQrYe9ea/jFaZ5fz3+S95Z6WXvZ5N
dfWK+347rkBo7eBGRbxA8D0Z4S8ezzEbYf8IvTLujo0R8rlWqPtxFxt7om1Ah+r5xUKwf/LEs4fX
IEXvUVa3zd3oq9rCP3E/OTTjPZ60I0vwIFOfs4nu9BbeXfmzmlG7LpOT62p9qXqR4pnMnfN8x7ln
BQBAWaydbK2hd6nWfyGZVOUp4pQ70Ec0ohlPL7d7Oh3BPXKRYm8T6Z0KdbZhyrSGHsIxkxXjembg
bLstQaju8avtPFwQnpA5kRShei5PAiKRTAysrQ7fcdzTZZOp/f4vUkDvRnPBV39qvmn20z51IxQh
zk0jqgGlhUKZoLXhUnuLZl+VJOw9tOGrCCC57q3gWUph6r2vzL/poUdN3ncPug8D5OgNy7CqswY3
XjbB/j6+YDTp2v9u/tk/7JfbF8C+x7R6w52EbEJZ9ty2Zkpm9iZo4/V0lSfV4SJMjk7wQb9Y/wy7
jP2Gr/bsbAuKvGn/qG7qehCdwHTZeFO/d7LIIGuMn/3gytlHzf2tpxp4HmonM2/oL7Igiu6YoiH2
tdarlsgF2BSqLYGRDvIiIJWOSVG49S/46vlRRySrqpbrOD7Z3YZDBIsVMeBVzv+VQZfaNCNvb8lO
E/5gud//9KoYq2vaXCaBKEjzwhzhj4fqnDvim64rPwATYi8jU4oibv2oUIcUSKS3tfszXnzRl1z/
sQO7/PfnYgmTQ9zAWVw2+X3bgK1aD621O4J7N+hfH8BX50h9yW6LTj1TANjudpuAtut8pM/dx7Mz
cYIJa2tRDSPY9uM5UUeg1g+wSaJoNeJVQGndQwTf0MGNl/Y9JgPPNdQtSzYK0XMXrhO4jBQCrRIF
3KxGCX7gdwHiA2JWCHeh3qgpMsF9ozsI836TU45Ap9Z0aeFSN7Tgm3IhdtaBECJAcFlMT63ACHFV
fiUTLz5AnxPGXQA/c43FAPEGYOkkEL//RDsGpOtLG78oL6gMFcXhiCjiuWYhb7yEah1u8L+dvneJ
i4y/wBWoyF/tFantIjEK5owybo20/x9paXyv4804BSB1DwVGTiD2bbmQAFCX+Q/zPppeocFdWAN7
QAcEk3uDibfHRNDjv6nT9ZjVSjtJy96vStp9monejoQVT5t4ltejwlnQQr7HNzk39gvctSseKphB
TlRsSrKJsp+XyDcsYlxn5IQO+SLv+1n7YVUv6cejqWkf+MLxFhvJ8JdDdOLrG3xu6KKVXeWvylUP
tRK/FF6SmjeOLqPl01ITU2mdbORi7HrdIU6hxcko6pmVFxELwkDTAMiNXhHdPRdMFIVCR8ZTEK6E
7RAX+R2OEWaJ6fGr4aDG9KcZiGsKLtrA4rc5Dz0UiICzxcEK2sznDAU066jDhaXWQwx+HpejQp71
Ln125jtZRI5B2SissQwgO/Cyady2QJKyPM24rtcc1kDl1U1KS1JtSdzlzCrirWu64g5gIZHdo+MM
vs6L20YYSVyQizHri/Vo0IKPtuPqzgItUjkbGEpXfYdVPS3qSIAdpK2V+dlnsP/BAaJf+fajvoOc
2VquaNoPOKf7OKmei0HwKc9d0yUfv45fUzOaNcD+hL/gfAmMfiRCxniO6jQXI4flVf2ZHQo3F7y+
D7dHEiIrBcg3x9jICDCnPjhXeFtfMLLqzvjKkuI0mc50BQI/Yt2GOy4t9YBE3cYJDh2m5R+JVt5e
4I71LPHWW6+I0xSndlyc+0aXxc+jOOJHNYfj/KEVSHig9z8OjtLneBfy+PUV2iR61QGE/mVNW6xI
AtdSEfYqfbavQsBK1aBipTUf32B5eRJEG456QArc5VAN89M0iCKmmacXY1oymYfxmdLuslnva5dG
3X6YKwcqEjzyahdWPQLyWLCXbD3dja/20B2NM7vcBymrl6Y+5eB3Pocz+EfkJ/WQNEOPMOBb2e6p
NUUfYsMWXWqQVGE/20T6gqHZZFTiR1jgyQBV1DoOCw1RvMmMHlp448J3Zdbg5p1Aa0aIfWtksHiP
E636Zy/IJBo5VHeBEHQHoCQYZ3CU/pdtZvTY5An2836bxSfGeBMlpSWkTXpW48TO1hVxUPquYYGE
JAUVOpVlL/mUWSfTerkPWcrTlOIBroI9BWyr5RrexgSS1cHf6/mdJi6DLwuajVd7Qnma1vyxlZMI
zw/wA+cyHDeak87P0LVyhSceWSgx2YxHujUeuicKM0bno18RimlyuLWgLc/Wi2h3Q5nldlAQQnya
IE+nXzDmvSNuMmmhlsbiS+zreLCufu9sA6wcfSYWwdKICHf7pk4Yh7OytietwTz52nfKX3h1x5I3
o7oQLOD7vccXpg1EXmsYYc67YyxJbT8U4rwxAGrv2t3qanINT7WKJEUP+Z9VXnZzqxtk10bkIgqA
LsUV02OEKeaWNVtO4lc/WjjHVMtBsa6Fe9WZn0yCHwehl+76mnQ0Arrdx0kw39SOhrkIpRXZYTQq
R7NO4BKanDrQqc9r6thyegCXKojDdhOv//FsLv85Bt6hD+ucgxM0QCHBdOAfDKZBgXoFTbmzQZ79
lDx8OdL4mN1rAYCuEzDS0YX0r3fGTFEKRB/4Svw4qQHtL5MQirLAuAOm3qG8n5mVaAaOlrmQ3dRI
ZPrag5577syMyW0djwW0q0NEK3snFeYLT/cCv12vXTrW4c6ZW2MD79oDn1XL2KFQbGLkLg4CkIXN
yR0aBJSBL44eNznbcCSnZ/SnFqnzfiH1rS1F/vu6oKXF5TjEYrhnXXI+TCybOrzMB2F/7eeiLndL
nezkVoegDTJVUHyoxzMLBpTRtO678LIeSLC3fmtrhMH8uWM0dvoThzRFqqNKdwmT03zjXEhGfww/
Ax03cD/tTqX6VcSLJf3mLn40/2leOIBdq8aDJX2E8Dj2RxVnR9w//A4LM83OiBwoB+R7gGCPfGEB
OEdY0csWXn2W5YPML/rX7VOSJN04m2Luf/ZpZR9OZLC+MPi2WTwd8i0vMZV8mqzyCNmS/7INwdHO
NEXB/D96aGJIrTlrW/6IQxKxGygsQDW+Ak4/YY2i/MhV6+vVyxdfrx04hor59zHOFl1j6mgoycIY
YkKVJ09h+gV9yupoek+SOTAwgGrTd5rBM2H4n02BIn9SP419qa7cXOQBc8R85VY2M4yTTL6haWNW
LQNBywOAb963IZ/EPY6lnN0UOABIqtp57MSkTZNr8hnNJSodipo5Di+W+2mh6B3BJVdpMOnVrC39
fRxMxu8XEnPkLGqADb8aRahRnY9NUQvbxlBOvRcyGFB06wNRW0XZXx/0ILWT1pjuiiuc9QkqDbDs
tkjA5k2A/Q4EigWzJNftXN9vQ/eQCTLQ6BGWmc2wMFk9EqEU5xwyRxivJW1uWoyGpum6ZFWMQCOf
fYKd8zraDF06h1JJWJ2enQh1JyOm+M/+6p1u4H9XKzuakIAMFeh6MFhWCXCkX1HY6a5PKTKbXt2o
Wc7QddDzRS16JKK+Pwy+gZuF0PIX78Me62Heof0CmrL66eb/2i9PWABiU0qOcqN8PmPBNKvGAP0S
zyIdtuvBGPDHn+Iw4sJbXpeR7FtQ00k3z2SPNvvhP+FxhXCbGWWa9d4OTLShLeIqmmlV4TmwsLSt
yxwUKmICP/fq4Ob1KqThpQ3CeDsQrjmBB4bnkiDQU+FhVhp9/EvP3RFAGu0PxCnE4Xz/0wQBv8b9
VsENAgDqzClOF4cO/qLc+TMGlL+UQkIuPi15T0exFXb/RQEvcWFJwutqJ45ZQwUva58i0fkSbUZq
8R+aQpwfSbfkS+eZtwTh5PNngGC8amyWsYZPbIDetZyoaxjgE34UlRE02RqLJqLRkCZUMGKUO2CO
PDJ5QOUab9PogYdhYC+NEn2DHGor/bHKnQ5m1P4+0cHRcf4TEQefLkT8AEUcgZRLQTuHgaloljA4
2DymPasRsQDE/t+r5IVG1b9cqG3zROuSrok1VdrSJf5Gox9AcQh7iTSeBQIWrbACCgyPz3sniELg
xwTcV2mPoGyUwTNQ8CivnJJpgjf2dg6Rs3zEJhKkkqae4ZWOFCt9lfSK+5+k1gYpWa12usvnvZRV
M09hv+gf/Y/KBxdCAv3UVQSpwOGjhho4CnvC6dXPr9Q81y74zZiqXGzhHRiV5N0+u8OIhPTc5SWb
mM4/lFGSGLO2SgBquTk5QFIc1YmYCKc+MgLAXgW7Nofymeq/5F9O7LrSU1xzVutOzOIqP9dVqX6p
XNrvyeHscIfnqg9AiRiIlRcqpMXDCPJFxJiWWfW/1XPkA9UeThGwWCdp8i/w5Y649OmSo8w6u1hX
Yu3qldIeNhQfSxYh1IyZIOGgwGd1RIx0UL7YtrbJ0KddrZM5VMbrPMv96/NU4Adkmixxp5d8d1y0
Hy6/Bz06qspDZR0SJvqZ61VrYqKpSlRIYLD1kHzKayPGXms0Ge1+r9ipD2cL+bCwr5PAeIFGDx3U
9WLHKnCDzT9vljTnT6JXGMpx7dLZzsp/DAE9EhYqFMO3hDZ5LjQ0PZM0bzssQmR5riDUPNu9VnsF
Uu/zBamKtehztk1Sp8FO058Wmj8zCKn/yFNIKxU0pUnXB9KZDP3z9zHk04yyzYUWntCQytm0feIT
EM3cIV3saaUYys2MFbXobuRpPlZSCnX3ldbAvWSwNksMlPpGTsnHQZebJvbLPLiwcDhPe9jxtYZ1
wy+BgbALpyKNeUvPRmQaUk1OY9Rl2FNx/8CENGV7Ytc34kDg9C/FCaC82Ytw72c3o55OxgIputby
0pMf7FDXSjurI8PELuvCvdOHtMKz8EOdiWk5G9w+1aByu96QfFqcBEfpLjX1G/o9AYNP3V9oA2vl
7GHCETORp4FisRn4USsftifva5kqE6a7h/66Jqll+yBQG4Qb5eYKhb4E2dBPrXOfQ4YmkHrtlYb8
e10zYPIOcRSeZLnRlA0xG4v7L+bF73e0ujEqQtCrMVmMOIqKsAb6n/dPpBr++3vqJ4vxaP6LxS++
b/6I8llNgX2Uzrt7CWmtsstGt8prvmlMYnTUEfkIt7qE5V4pO17DC6Cyje1DFhOdNvZ44RGiL1HM
Vj4fEjsf+GDlSjf9kCnxc4tVKUp4mPd0cKcE8cd3hEoebgdEckTK/sPA0IavrKOXsnP2Pzqv4R8h
m/LbEIH0r5jySxBsZpH4e7jPOfSxVdxkM/kZqJ8OGmIAjE87kFrM5cV6Oo85x77R7iXa+knvuZ7A
v+/cYMSOCnSdA4OPqYgStk1+pjkXztgLG+9Q4UhU/kSRbU3KgZbm6eFlVex0hU6O5QmMvZwGDFTC
junCdKPlvkVQZYo2k3DVcf5zOX7pQ2LBsdJuCRj/qOd0HWeZ5Qn2eBCPtBIxNqxhUynZmET+wPc+
I40p8bvV4q65MLouF2x/eulA7C21QR50zaMdgsWq/qSNehQsiMWHoisQqq9i196IaxuI3t4XR7vt
xcfibBwCCS7H/FhRcdCLHo1cj7DNZt24iZqKtxK6V/YYLpjojwGnT8zc6/pdyrUaQI6zo6da+Swj
t105ih/ZtN6J4+P2iT2aZzn05GjPLQeCDmWkgV6+4xknt4zBH3VTt2ChXJ1GXMnINsbe0eVsaiJ+
9heD8L7zXsMzvD69tCOh0qOcHFVyJP2OUJRWtWUskiCt7kNX6jCPD/YknKtaEDyAb+DOEHZx9SSO
X8fou8wKJ3HXy6+wlpcCIdq+OGoAqxYJ3Gx02fy3CqO0WoaRwahnA3HIniqURq5DpNZriXw0unFD
tXJl8Xqq+0UriWO6vWd5ZdVnDfRdjL2+A4qdaKSg6D+X+2o8UMyBdMSc01v1ypRhpAkFASgthZnc
vaaJsYa9B4OHk+cjww1UX80zQFrC9qNaymEtJHgURgzsUUBz54dTjlrUcJlfJpq4flJf0yx2/d3O
eq4cB0RNx1p6PO1hZ+EQXqfXXmSGyvH8bm9hYXxHGLCN6J65nNTrgELXFsuKqnpXFLiFcZM9Lu8f
tN+kdozrjF7DEtg7MhqbILZ9UL/yferxHlI4mRrkXLhK5RwyDgh1JhIPqoS2EgK/iF7q+CO+uwyd
1NEAlHMhQelD4+SDp73cxgQ0fp86KrTknZYRNWg/BFcErztm6nxW8awFUirlUAh+8Cm0f5NTQvOF
2/SOCJNbpu0vbXQsWWVF6GtfilOQH2RTSaixWY0KYGGgSLISEvCyD9zsSEIl6yaXB98Xo78DTOvm
asFOrrVqR15yuwDw9agV7HpL+TP9nrmpdlwFRq0eXNhYz+A7CyBzhdKCKrz+3vQfBBa7uGGzSrgB
uo16PPLdHg1ZAoucsoIrSAZoP+o943HU9BG5CIJ1/0A4H5h4BmiFH6aYjHUdjIsxbY/ttFnUDj7i
0GumnGwEmP+GP+Nuk2m9+ZG1rYoOdXU9T+uN6ydUF7PocgY/kjO3KpC0u7vdKEyw710lIprRNmBL
27rFkTm8eHgODvXektfbpu2xe8nCIys7mLhGBxJonKnimNDUzSiAPnnTasqoYFZ82E8/av4hToU8
XhfwWLcxXqnt3K6DRr1tSJiyfLgxyYKHNvvMYNNK2REDvKLUNtSEUs39TvJf4b9arFkJhnItdjWS
5Q8itwBdZxLxLmsh2ovC693aDDvQdS1bJAgS32A6MBstj39eEpet1BVYAnPpu0Rbj5Ik2lZJhGE0
KCosHk8JUqS8bKr5ULTFyXogoQnxKdmQZbcBaaBts8qnaZAmjiYKgsAZkT/w2Wli7AImiPuj4/4R
jZNOPcSw4wq4N62wTcoU1K9YA4oBFl80YtwLT4sLUvIDXt1/gpg+zNSCfvBCbfOhYBWrGE9zc26d
nG/JqVxtxFhfa3jOAEMydkrNSm1XMji4VO/uceHJzWdGtWA8I8oE9McaqxPpTVrMjytYxHfH60Qt
kuMTgklOMMw7wVJpvGp2TfBiidoZxRuyjB4TyJkQcw6iHNt2x/JOJyEMrakrigwdIENc0YV/8jkW
O6tFsZYXgIa3Hj6S1eQSzzkgegZKUfV0lPhuFXsyAaPzv1lDAwWw4aj4+fAKdbo8SuZTtvB7kgr5
JRV+CQLf5p2fh7DzB2LFiW5nAeMgOidAr9FS/hbrkKRT/JAJiJX4EtNfqcBb3vPyedbY783Z1a0h
OotFY8u2FyXlrW9U7lvb1T+ye1NOe+YivAqkY6DfOM3PGNOgIMxGxVuMzHPmzt9NojEuqwdI6OIA
RHbkPGsCGnvgTo/OTj3O3sUZUFGUcqqn6SZj7XzWY1CDdUIYICy9aTOMTJnRjuNZT7o03e77MY6r
/ZXSLlJkAs+hs4SEAeH9yBDwVVWBNxxtDkZaWlAMwmvVHi/WTLsdqGZHM2NGlByoDTbln5L3kNG6
Q3+A8479R+7ypVkPrl2VaQJ6d1K0Vjl+j++8b++Mmet7iYxotKzWXQruBLtprM4VjoeCsRDGDl4c
s9eeT+4yJAaETtJxlhHKKxgmj1C5EvHDrAmNku3z4hQNFWS1xsdMDamzzPvktqdOpQ6FRolIGMJO
DyUOrdyVYVKUEhUXaIpDo1k9vZWoQsi4vWGkHiZNq22O0qdC4xsv4l0Wzr969+OkzTMocACAIaKg
WRh9l+w7WYrGl6iRLqq0ZsB7deDOpLl4oNo86ExmxUlZlojAETdr+S2Ry2HThB7l9zHRajTLUP1E
zLDUPvYLBAabEBT+XCzw7mGJ9i7hn6hiHerOyttTEQpsMFSMUhiW4wRRiRctax3IajaNlv5yq9nJ
9nOGjrhzP+7WnSFAVk0GfWDMmAlK8jDLYqAMvFQHzdJSygJaLqvIv1a5MaNoUgFPVkvQhTu2jby8
qKtGXsd0Pa6kXEq5gBXr0a2cRszc2ptk1A6CF4Uh/jbwob3PokiZghtpaZwOqH+GQpW772RDy5Nt
mOerSez1lRFYnOA+sUUswgnydy49jimyCN3Uq9FfovqCfq5bWKapuFaQz4/d7VibDuE+zgqoLFZO
uZz6QuyieQONgh8Kr+Q7BVjOvmdHWyi+fGdb7BCKQ4rQ2smaKf+vPN+3AG/BVV14rSAatRmnr2nI
o+rD0dZl1MeQnmMnIRv6ul/UtpYgD2xGzqOdfGlWx1e22me5LNZ/gU9dk0iaSxHG7MWphgmH7WGl
zuBNxY5AyoAN0Ppx03jpAwdVFoWffaUZ7sBMRICfTqh6WcYPfln510Bhfda2OMziK714A50iRmX1
pyBW0jUICyy6uSNXvWJxMrR0pV1bGLD1slTguyz68o9ob3ObKnWeMDoMV/YCPr3071gYGpvrzHcw
JA4BntFhc9roIB1pVpPF5+rz5RtDLZNpohk2ZEbd3yWqzZQOnnHofxDpWkP+9nWUbZPCZGwQ+7dh
1SL3iVYLgUivZL4IQMOHQEDTskR973YYldrfq6CMNfIGvd1xolwgko+WhvtEYZVRyRmOmov6qzAG
CSAN+GJPEEVtiYJ7d8NDmy8fpEzePqpqGpa0i0hbGxYwxuzklBZ1yTFxt7Ml69AwGbOOMSElXDjv
2RdJBcK0XfoJHV6GrlU7Q+rG6e6000DyHtKJP40KwlZhwnY/xLb/HD4s8aFYEZJ0F+gjAKy9wcSa
VhoHvboLnWa/t/JufLbhPMwslMNFClIKEy0K7LJwaDAzb7Ty4ISGMAbCF9tybI+433dC4N04Ylbr
xSCF7g39IijW0lWn35N6uRm/bEw6DPc0LOOpILL6JeICtzDN7AOncgbbSEXjjnW5b3ubYgu27Q7x
t01ZJBl3QbjAQRHGTvGanU3DzvtF+5WB0pmEYSTzuTjghSm3hHfm4touH0dU+lgCITzDdtUAqLAk
PaKdQ85HbmHZYQ9CiC1OaOEgMrookRvr/vVwiBRL2vRI7EDU3z1eJCqIwuu5GUtz6N9aR6+qT5ny
8TFBcGhO/xr0kJJr7e3Teh2Ahd6dOgdZZFvunDuLyNQ7d069492U+4lgCRAEsTZ8YTXJCqoPR66O
nSdXcYLMCJ4jWUNoFQKLCq+1mrn46kXs8KS6bm4RvADMesXSFqifQ/uyob4kTgqbvGPuopD/Hpk4
e8LO/+NB4p9a8f3/miN/GRd7FL11j8jo2RmSJOC/D325ApBbUPDulVpoM+NtUzEthBljh6/A9XjS
SiTWAZdVjffj+rVnPmTZ5JUGDuuDHz0lBaNLJi2jcCH5wNvvT4Reo7/07jKzzhL0fsuAxpF++WE3
fDI5R204iBqZZOcaUpf5IJlGTB2i/6oVmQ2uSI9ENXuZ2LNwVHFQ2kkQ0q+vhMUgjWcmxYu8/jOJ
ds/dgPLtfVquzZSohJoHgSjiGvRSQLz9Nyfaj0uj3jlPoG6N+KsRUmuYuUrM9SCQ1kjR0INHn4hE
iRTFWRuf9aKzbskMIh6WepCVK9bwSDyiAeXGRmVT2BwG0Lp5GwOfOOpjIn5RfPXGcmnEJCGhzO6X
mmrMnAtTX5WldizqC9Y7NE8BbfmIBHGIKklv6Ax3uoEeDJ4ofYlCJa5TjGvFDR1fXnLP/0OAYEw2
pDUJ2UwGY+nWdQW5lZyV4tfmYugUR/VeNaKv3waFoN5s6qwyoorSBkKTHh2P5/npFYEN83XcT+tE
/j6ot6RBn1Vgtwceraxi5Rff+ueVlwFU+04K2FZa7QuaufE9qyeF70F2+MVD5tEsYrRh240GGBPf
y4py5vc6xiqE/6N7osYPv7MhS/FADAboFHpPv0u5BuFCeGESG8A32PfoJ8JTUQCELWew3fUN7xWi
7R+axAjzE3Z6BlO3scbB1zZdV6jSp8KPYsKvNXjQMbYR3C8dj5GTryO1FItpOFf1id+CarKtoTq6
S5eFG9qBxtA2FKaeXfVszIDFPkqgwCRZxc8W5exUy1opLq+SeQyTTaSgFo+e0HHFEDcvFLXhBinm
Oa81I4NSL3eB+JJQ6KOfA9bx/jeYEZZ7C8Jg9zDJngmxpz7gJzul0P2JBv/xn7SVuCQLTO1mXlAj
UqtgZxgXKzslYCPpj0SUlYZYiXA7a7UqDxckw5vGYGOCUQeyzNAfOObZcjgY+qQVtCyO3kwm9nLb
EwxIQx8bq6oO2HlFBnUr0pbY7uGG0VSntnLB4FMEsCtzlaF0NkqZk+rZ99s9Ezm844HhwQ/aC84e
T5WhHJpmcXPDQiGJHJWuUspQRVu9FcCJfvUgLmnZJIz89/rESHd0lEomgwAKFtcEtMNaPckiXjwI
NFOxHGdBr5DlqPOhjK1KRbQJh8ObzqYsSMPdTZm16ulm8cYe+HF/8XorpnlPwsaWcoHVRycWR1Rf
24zEnbAOXTzlA6og8/kAYPp3Yyny3D98/Bhwhm3hM3LAKsIEcLiK5zlmAF503ouH1BlgrCVrHCMS
ZW95Uu1t2CtcHGMVDvOvEWQS84SnVjzlaq9UyNgbe0RvzqU1CHWn4m2zX0qIkRuNIMf3zL9eM2Ze
zXCWMguI+7+6oU/aYNZmRX5ojuhDCUKrNz4FmdqSw9THaa3KBN7duiljnrSQbzHQEulcScQU69wQ
RWZC7jhNNwmzhJOaJSi1nUm4cT3/MRMAaGLDG6aGD419cu+7gm+OXhdxzDH7SaN+qrBd2HVdRHyr
tOFEUTXxCADQG+joVR7Xl+jHoaoNQMX/i0joF86KBKRmNVqQUSNnDKX9govYdQcIXE0eQLJI+CMs
Ms9qK2Qn17n2Ray53n1IsCGvPX9ZqL87TYxqSQrIVljUfhRQ0z7qeEJbcx1aaXqUL/TFKHBr8i7b
q4BID05LQUNjrIpcUkN5G/66nNb+EDOwZuyY+VJ1+xr3od9xcjR+y3A627AgPZBjAOWT6GVCyqpX
nbGYOyFcAfiNJu6NuH3fRMbnkvWguzIvWsgJ8bFdDiZ+toLvSRuFhvQuO95P7NDBVffXK6gIQCIV
3aOGRjxJiWEeAzrey4Ktojp/cGqG7JR8UyXxYEFHoMa3ANb4KjTUAoJW+IPydvds2E1pxaAft2kg
5ypuLJMqLD/8OvSgdL3EM4Tu7xtQBY/oFYSmUCbFQ7E5PX2DHQtDIKPMVH2shMT7pR4j/jgMsuoO
WydB+9REle45FpHzSiNApaPoE08rsUulNI3toJRVnoxkM/Cqwc1Pp9k0W58pRWdu1feuZNS+LsYf
0Z2ZWbEzDEQ6A3VE88JzQyffkE56zUeHL83q/9YTJZcqdSHxxUUGU6i9E0w7fYM+yREGYsW73G3O
Y8KooLQspTpYnk7vqXjuzGxKCSvY+uSuGKS+BhnDGqvNP/vaeJMsLX6Vn39aVv4+T4JV7CMiLCre
To77QFuJGbxx+d2yExnkk1vk12qsMiMrGX/BpYlRvWMvtRUdKuN8R/C/Ze+z7qDt7bovJlAsMXLw
AG3D5wZYD1dSfVKV3CjOIGIa3e3rY1TXGBJ/GkugJCtjStTE+UKYUAa8qeK8o/AAYakQpSycaRbK
6unTacDhihgF1ixwqvHl+XtxwGfaJPcz+5b/z0w4HDl/gUe3JlidQaSwRC2EGaBCtnMfeEHleRfz
ImGBBYqgsTkyqckexh7vYsvqcgP2s+pM1ZybEDc9X/iOGIcyi1RG/QrXFcrmQsmwQqFK5eCO+OjB
h9y9Ys6+1aC+6y8wjpN2tpbAkAhHIWKlthYGPaDY8mfjNhwvJMQFxAn7VRZi3BHzHpm4XITmTtXv
JQCamEYxN31vZSjd318PQyt6BVc1HvMEiWLwZ/s0gb7fycE/aHyu1GYKJAKVbpQMk8210t2oZHuy
8BWBJSpCar+adxskUOoPi5RbpPhsppPU/eo++ffKpF4r1M5bPOy29KEysnSGU6Q6V0jQg85rtyU0
ZypYRF4T+ZLdgPDLcLvOPlCiTnLZKX9m7IPAE7eHolOng+RMD/JtnmA5T9GHikG4mRzte/Hi4nWR
TS1Ctyr+6ASY2BELJSmfy2SynBuKB8Ig6EGO1g/dklam9HJu8XfEHOtWZQDvoQ2JVAQZUhCesf1A
u/CDJ4wTZLKr7Wqxw/7ANBXuG9LplBu2GrVpC/7AfsW8clTtlGUEAEX0ECri8Yc01FxfUPbi5HJu
UHz1no8E0+TNsyVZjKU95tAYOVowDbMnVlebirl+/wX4hfOivOGFtSOIBxrcQJd+9UTZm1hkwyA3
iRxvW3WAAQmgcOjcVGBHDyBLP3kN2v1v/ZxYYQ9jjwbVNolyHqbOVrlprB/CfOipZIVY2bW9UYqX
mOt07MwlFbDwZZtQOmnX8f0KyBvkAjmuBorkGQ/5jC7Sxw8MosO//pS/2Fz9BG/gbanY9nKeNRDJ
vBb6Au5IkXtX4Qc1J2hrMXO3HfaNYyXEZqRc5nKFpG+QhuTUgHWJkfnowDcR9m62R9qGy+yp4+o3
hJsK7p5S3AySq2/UIrrQTR7sqdYEpTXwE/zqJzKsRAOIHS/Btbgzc5+3+HRZ0Jb5TzWYIHsQj4N2
fS7rPsx4QpuE4UBV25gsaUovhYZVb4L4Pnypt7IV0hfTJAXD5Q0/sr6QFV9BGXxvS32X3LRKukHS
oIxPqlATQI7PRIhD51n80BnpsD2avj/id7F4J0Uw8NYMlg5Lz5jFZOIHrQD+W7t9yBHR4MgD+3AX
geXOxQz1BPRfxy2pKPlk4yIsWTZxzuD7PdEh3soY8B3wi6r2xuq95zn3konGuwZrUSMO+T3WGPx/
/Sgak2DcKfks26/YXVjlTJdiL3rF1xuZZ4zsr9ajzsztKPdy9UlZe2CcacsUtUTpujaDQIBNlcVP
oQxS5yFx7FymdL7VBgICyRNZkMIGC/V+RRndT+GMgWHYaLGdbTmeJV4/xL76H1j63ISQhff3JS3/
vQe7EPud/58cQoWxkD1jck5NqCBU0+svQXsUqE6+pX42T6Frw/bBBuaLRScgI5XM3oZG1vPSPjhr
9uIPjMxkq6NIYJBKJnKshyjDaB6qzlSc7AerL+zAh0iDPKHUd/LOg4kBZeX6pV4t6emCy66NXT0W
Ci0NK7nXqnOp8dlkVf/pKoDA90ANOZzD4s2OHiCFzj9u5DTJT/u+UrvHDkz6bN9t/UAeZXfa/MSf
F9rUK8dcQqnS+oF7ZL8IesDWVDK5loW7JZM+VFAQkUmdg5h0nRuPR+My067dAd+/M/9pPfzrPI1z
3hcPM5PewLZvbFh3J6Dt3Sc9FtwVlz0aIhIKcQIeqGHRyd29UYcE7trw0duUBpyoBMeHG2MEbrEI
DUIiuaXXjlHr5507R4EU0nz5OSYbVRQ8cqt9yWNLYI6BbYT1cXUGII32yfghmVbLL1fP1BlyD48k
/tRlANJArQk9Qbv6ZS1P15AYvtelxrYCbqh6K0YwsxINOEtZarfP0kvuHP5bljrv+YOrEq3TI1SW
cBjldudCOzc8KReA9TwxT/2bNpu6mqKxThBdzOvqI72DntYB8ixXTv49AKLV6c6sPLE0bu9BipAE
7pwWkzprwI3sNNTYr+7FxhNyN3vX6NbQT0P5TdERacFYPHzphjs77fdT4s3wTg4UwsaZk3+L5hmP
al9jzimNv4IThUuW40xLKI2B2/lHa9Z3BfQ4v3dEDhlS+L7Z6xPquIPjXJOE2YpmAuC+56l9GRYc
/w7Z+gVPAPB8C5poeGoN8JwSv0buMpoeNjepJb3OmxRPgys7LNII3WthN66A21vp4eVAoUVCv1jI
JwoTu5Y5dNxHLjf+iCQa3F+du2l/kwVgAsV6bmvtuJKiyAjVSJhH2e3CDk81VOm57TIpYsYqSZhz
BCmnqpcKEfrz7YXUSjYRSUGnSY1MUK6eR2t3PJll2vS60CbeELBkInh+iKSttkIbJEVi2sYOqkTZ
/PsbbgCvJ/z9B2o/bCOV3p/ifK5nS2/gdO6mSEkj+gsqBVUlneNWhlZyeSpxvWOh2ov2IlHCDljh
77UXGinHa7RdP81HhqevXKojE3kZOIcOfa9Fe6zSkAXJ4/uF8WN+dIvgUxumdQWGOmbDa0vi/oFh
kNOFa57Qz8qzglxVoE1gJftS/z1hvI5dnVqPKKAcZrNjSIoVeDWKNab9hxBFfr+slKjO9L9qHRM6
I8WYpPEQYJAOkEucMZ3zqZb4UeFFkzRFowb3bb5toIVPOA5x4sonBLGCyFqKTbOOwB2F75j6pRy+
UJm2K8nzQJ6GWSbskkkAoUGN3ZC4jNveogX88fmGFGpk9yneghG4Kvmjp5kjtQymS/GqpQ8XIDI8
FTuG5HViT1S1b+EQKP3ubFb2yhSFUHN3Lzw2Rzj69IbfMMjk4GLdztqq7LaDJpO9HPDgnVmXJWwi
MvTi4RHIS+KiuLmQZedF48rNnZ3mk8MhZ/QFZzDQGMUjXxlg4TO00nh/j25TnZER3aW5zYTN25D+
MFlF+PR8880M7MHkRq5HAhNxQl51SgTVypSDg2b5YwRfc6JPC2WajtmstVv+21SC7EL2Ysd8jnWt
H9T3jg09Oh9XW9ajr31DGhdiOh/dHgi1i/1mrI4yTJPBYvwvPH7iWKAzYbhihCLDBkutltRTrZfl
esEbn01ZcbdKfwwDiW7mnfqa1gr2+HVmQMR7TSfTM/iUh+jc8Pp6e+nN+tcCwBbVc8EfQOwMIAKx
iE+czsFBAYTjjG2gbB+nwxXm+HxuONbsZfNvgxsvtBLAX3Y9LASqZmHCYidg/nezQmjC0V+B3DSD
GRF0D5h3BtqgCuDdlW+nuopjcE2hHpYV+j7+k9KPPE8UbpXfUQ8UFKqpCPOXLEUXJgYY6es8L6+k
2VkW6+qwkGMeO0uelcHZHw7phIzJvoWCWY8x1A6c+lV3DUH0sDdpfq6oPIkD5QPLymRbnrj7awg3
8KAffJyvdXuQ5AoqYP2fvei5sJbPwM4MM9pa5VQDANl0WpN4N+neOJSS+jg5W0eet1FEO49Ho3vz
7+agb91oz8T+i9ODeEjgJKNxIsE5jggNHbQB95d3rujhCKA65/pUX8VlhnDSHb67BbfGwHnw7pvH
6vlhEJvL6vSv5yrTGDNO8EjxcRwkKX8Q+D9sUEMUGqSzpkU8hLkTyEGJvTKnPFUDNQxIdzcxet+F
Hc5TpDvPQOyJ9Wmilf8AmiA8UctGDVFFWQoLFylRv5roJnAWk6gLzJE6ONWB4LHrj00p3i4xnDD8
HpP/RI95iO34D5KXnlrzSKMD8WBRhS13jAUHeXkqlGOj2Cvy3Vjx+YdUS8t6gOG78DX88oQUNoGi
3yfEoApQk/Qtpuy8xvxdWzkZCqYDLxtv4khlWvg086xM2ihGfGgerX2kQuGcuyEg4LEBocBdRv2m
cqLPRaGpYIZlQVUnRS/M0K+zSMRTaN/Qz8tcsYB8OFAa7ezYCBabMGrHgWT07ng7/UBhH1jYkA6n
U8j7oO8CYv9kzcT3xM5zET4wG/35nSSneZjKcG8mAMRT0Dz6ryXkJSL3BaMARVl9bstPRlFCfIgK
ddOA2HBBe24ioM31b+RYRfCDWosfYpVxxqFQ59w4Bq+Ecg1l44B0JXMU3GZDaUhJ1skIl89l1JZe
SlwExO1hmOJ3u2wos5LbwavRGCBPEeWe5Aaw2de9ZOW7UKRB0ig5/bZWErrRmHK8uBJi+jH1YJ6j
vRqtMIH/9KfHlzSOJJfH3na/G15HwZTFjpA+5AkQKLJPbtjB+EG3fwEu2oZLROobpZg95+NjA5uX
2WV1QgofOU0Zq9/RcPgtEavKUbS2dQLYwFEXEUtfMckHp1zv7utrVtsuTNF4x+Whs+jLDpKBGTV0
sIkmtt+KSBw3/Gg40Ie+8ifWmnKmg9Atfz4fEYGbIaOZerKYen71G7kIg1277SLMacW0zXUtXCe+
o5SZvwLiKkKxwBpAQ+bPlp9+IRNwH9rHmYkAIdT3PTV0PVldwe8/WPN2ZMD+rt5L1PEVXOLPTRLN
WfG1PJN9is78aFZFBikGKvBEiSz5j8fpDEO0t3xRb4IiweTWpZFACYNh8CLw/lo8nbFmpNad3B/C
swZcLBx7nu20qm1K84uoOAUaEV+JClBd2R4fcI5iITpycFg5BKK3jbS27bOf5vfMgA4fsMwyGJnG
5ttyxf6L5ficVzJfIx3mEtXgDCRUl96MRgDAsMXrGpI8zbCEcc5twldjshd2hImS2Ch4uivh9iYO
ejXW7SDfVQTSuJzqECHLYZaMgOUV5B2uaHptP4yPo1i4+vaWrgakJqS1F9VxJTW91Okd8yXt3RP3
E3jirqbz5/yF8DvZV/b2+x9iPDGeTDS7pOSsHM7txrY2ftiD9kxU0Dkg/k4r2lw8uzqjiZWy1bDM
cxmOzqHXXVBDmJK+kgz7KeHRWi/RW4lcSRol20mPkDLSKL9SAuyocdzDGWbxfCtiPq4K50efAu6x
2cWAwhFtnDF3xpzZ8PECc3OfvY8qdeDcspxAqhrHeQUxDJ+n0rQ0cS6gc9pDwhUWau2Rh682WYQs
3UAJIbW0ilV17FVs3ssuWaZP9way2qpdwofaM/f/e+HkdJytFANT1Q9i3Z8vTxcWksMccFzwpufl
N1zJSCfa4Sx46syiFY8xeI3Wqr2i59VEMk9NjbOQQooqHO9aONBsczf+/bFmtFHslDMj2Tugfy8I
OenqHMgLatuNImIZPUV57x3kiNXa2E7B7OQRQ5861QEg/YjdNArZJYKBTpO44lMMyeUbA4J4+DiE
2n1pgHLJNJt1v81hKAmHOJUe6slKx3fDoSMnAIjsyBemMjuTDmjPVSNNzKH7uQr29Wm/CKxjOb11
TtTZ9YyhXlv3hmyKjw+/lFi3iQKE9BD0mdAxWZVxDpwjuKuA2VGQncl7eBrlgXmmt6FM0k3rRysA
jUx0fNz5/Gwz9tGg99E5mxuztm7xg6ZxXbjHPAiEwOVF0PX0uTqYTs7TiKUkj5832Necnt7fAkWq
yb9jNACEAXZVHkgYhSYqxLGaFPSseL/SxKtHW+Ov6wKFbDSKs/RzqHXwIie+HmKwIRkzR99V9G1M
nvXRQ2VrfSQCatUhu2tROvDWBPqV2pISzkEcD5KiSPUpVjSzW2RKx+Z5snN9iPF4a/z6SQBHUBHX
VHo5mZs5+6+z38M8xxDwQY6zaIhMNlwahGte3mvzRhzx6XvkoirZb/o16ck8IM9wMLFg7WC2zqHN
dmB0UgY3arRyavUt+aflb/aCzUpz/mOzXCbq9eacur8MZl12ZABEb9tGUQqJlVctMXEw3JkN3Op1
3Rinfh164UYaR9zFCBU9SL7wa6JCR58Exc26mP7X3m/yoNa3nJLkAcoDwFK1TBJvA1pc37hG+pVB
7g1nj60aTfxX2Ghe8sQn11NP1FHFGKoC/lUDKnRGKm3xPcHz1MXqtJNT+cHc+19AoPTtf3SKoidx
6ojkpn4FlSo1rsh6RAAfPYqukNp8tuk2Taf09FiG9Nqjhxlt1S+0qgFy9rPYV3FwmesP4/vqrHLZ
6UJg6r4MWtVvQ7pJI4x5OjeZ0ccDLJPg470V1yTM7Xw1KHqWjN5xwCnapY8COk4ibweLo5Wgy+O1
SBG30ufiSC7gnxCkXx9mKt7CT3Mvr1NdLhqGKoRFx7R8LE+nBGtX6Z+0gSDxLH7IKfclZMAox9Ux
CYVM03z/4rREFnSupl8h3lSW6rambjjayjIExvgGz44dX512/hVHlw6pWkArSWj1pNmMqj9fwtaM
xM0569G+JK+/W6qEiLKyvJKcNKPfpgu1wqTLGtFZp5aVTJziZEEOVg7okrgP+FlSuByVooBRkB9m
ISHW6KylTsiUh4S8d9jbxXMybNeCsBsXiMsybi/lGHHfGpCPh5CoQfD1bcrrdBppK+bwKGqNrEPr
Fj9t82yA+fOA4Ens4U8e33gG/oo76ljHxZC+E55Jpr/036CuRAuLK5j5A5wkBKHTW9qExvoLxKVp
7420I05zDMK4d4SfEhovBRM1A+3p5iDQDQ1+0j9rvuaNwISQ6ohuwyOczyKXB+0bQqhMnZEWz2RP
/TUbaAmMy3LUSeEpSWQKTpCtaJ/eCgl81gDGX0mgxVNxWpG9AQfVkY+S0ZUtVeB+6yw+KSZXuY7n
Epy9ZkIHitb5STeCfoyWfipQR8pPsr+3SYXjQ7mZJ2tLI5iz71XlI5ZP3rKCz3fQlmBGzJ+nlIxm
RBMjZKVMCU7oeIIKS6pOgxMHeHZ+fh2tgM0PlTNI6uH/ds1BGLRghcFMH9NslT/2DSBZ9SPfsIgt
KBoNqWj2BBqs5HzbHaU7svS8lXlhkfofNFScS8beVfw9X5brNkwbUkMY+LddQSEmwGeAK6P4bTGd
I3dwphX02E/MXbSMl69QPsSb0L0y/URlc9f68GYogTjm+f2SDZj25seyIkTvdxuRufoweWBR0e26
MZYi7nLGQlH8gZHhzf6/dOqhrD+KYuAcDIRlYmlEX44dWrVKYj2xAWYPIo8FFVDW+/QvXxoRMNvE
f2gv/uQ84ljtYreG571wfiwQZGswgC41Qx88YK9iErbOXFU2tJu5g5cKR/TI+Vkod4g8ES6RqAcY
XTirmTYMsMszIQPXRJlJ6eb6FbYZO3IkCgLZVx0X0eELBPwcpLlZRfEx3BGQGgx2V9SMfH5FrPlF
Jqh+c8fTFXa9VSug7L/VUGavgMIJSFGozCZWdlgci5/npkVh/oFebQfAGHapROq5XEVYyT4u/tyN
9LE8dNCxLnYblLDke/Ox2OyiLWq90fJ7AeqLto//6B36YMuRV0Sz8TAil+3fzzcFxBnbJ6a1zKHz
tMIQRNW+vHEsnsSdGwk9/g5MRDEvN4VBuw+Uevg5vUzFj8q4X+APg5i39JnOfFRvKnID5/ikRvh3
83/KgaoIL0AA4ICVgH3lJqXnZAMsnsVIOpVbY10XagfiPEme59J4xszA/DZi/VAubmm2R2xLaDQK
P2RDHSTY7JNxB7IktUFHD0AqxbTkgRIh07iyvzxMnvsr6w17nAg2Qd6NwAudpPLj1nSIVSWAiDZ1
eO2TUbZBjBiA1eR9GXC0Dp27rTI7bgM5puSdfKyTRrNnYgX3/B6o0ere1svHLbAEDqCvppw0GQdr
ibHOHMrYQJl1tbu1dGLAldDnF2iOmVRRr4A4fTxaoLTQaVXM61nWURDYPWansEwY8/xnFu1Q2Jfz
SoWfe5Rd9WIPPgNbikV1MfkDP5nRcufpndPGohpjbc2PF0ZlIWxQmiJt7PoIr9vee+0l1/fEDIiW
coZfGhWsVFt61VHmzR5DkSHh6BcYqFrAWcMae5plGhrokxYLqfsdslt4WBBjbKZmp5iIeq5oTkcj
UqSQ/1qWSigsl+zBsMV440dximXZ/eRZzjflrr416dvTPHE06bwh6xM162CNkn7oRrcAjcMEKbti
JcA6+hizPEgeRYuVZ6k5jB9IayZkUT4bpUTYi76kC0cCk/az2ExiE5P4BybugrLtz3ub1Kr405WD
mTXfkkcZ4dmS4GRv2I9M0j9A+eCnwEBNrY270I492axEtw6UfGbqStEDL/OcSZvwtZocYjXTUaKT
bYjP2MbCr/RX4j9GteKMQS8oZFOWOZsKVMiHxtYZwVtLxDSEpRD84bveAAyevErS1ZeLtLKPYO1H
jz53nIS0RMg5hQln7ZUqEQwPvNbMBuFWvoae2dL0BiMuATjjpAeKDXB5ibonPIWK3+9zrJLCmlew
qGbYcZeRqIGkzdpL7dZfmF5nG1R9FI6chn9bTJNuhQpQ/fr+Zv29WWiF6LxaMv0Xjncj0SWqUju/
YKjVIVHzVJFqZmEUtn4YfVskqFn/S02vodM/JoF8Wsp/xdHIHBBujgJCskLEPmR70Ht22IsDigjY
HgISIMYs+eaJE9c5UXuquxtVvV3DaP5w78qg8A4/hS4tbcEoHZeYxBvxCSLtPSpFBYJ5jieuvG1Z
XrZ8nGanwdiOJuU6doLuipEcbg+5hM2O23di3zeC4ce9DBboMQhiOmfWStAD9lWLQY8C1oGVA8Eg
IAvldYTpAYp36LSkSZBirlYbkD2MlKeqmeWghR2gw54eR/OSGTOv/iHCbe9DGxVXkw7KCZ4QPoPM
S/Jo54sz8gdZ9bPEkI2uZrI66fIPrhwDvioiJWT6GjiZVFWsK/O1uYdpErChZ/0Eisadu8GNArmN
QBOTfcUrBkVneY+51HX0N2tvBYIM83/rtv1Vlu0BwjQZ8MoyoN3jabyDg0MEA3JNXekXYnJ/WkFb
wuGUXvIEY9Pbt0Z7pHi9juqkSc7wzPcPgTzKmMaWoOkA4YIgtzXPvKKk96Q8cezYMXjR2x6Rweqo
i0kY+EwNOFMtChTIBs2codVTFS6YGslbjyfxjYyAOoX8cxWaVY7iUxe1ThQ2FcLK733okM5vk4IC
pq1JuAXXlZh4AP/MSV4nnWIUoqsy1BAi7KRg6sgKMqSdk/YOSUJzqqufmFLs1JU2KjF00Le1AHKB
k7CqkTwYXIfzjz/oD2ICedB7bRkpbnibv48Tb3SbTw7ViyFdlgTVifhU+kyo5kL5/P0YkukEcaEp
EKoiVx5Gnf6rBNJZZkhJvcrVK7fZaGTNy5GCzVuj9rWMaTpQjle97ivOm09JYleUvGfa5+MH4Y/z
wcUy6RVR7jGppGFJwPZSoJoY40VLuwhCxDzLAM36KHjo1374ZaifCj3oUxdBV8duD0oewRc3ve2k
+au0A+07ADK6OL63XgoXD+2UZq6Zx6OQWPJhINw/IJIw0akuGgHnmDUoCsYdAoGvW8NvXzEovQ2I
c+Lb7oaCgY9UnUnQYiZpVHh0qMGdYxd1UbmFCQUYSU65w9EGu+1/iCCK+8jGZPOS1F8paTcm2BDM
AVOgrciGyA7EuIi0qh/WA5jyQelBEgVKL8bifkD3kt4Cf9fgWfnG4VzAn+qBC5H1KqSAbRf5qYFW
wSOq+Or4OE0q+j0l/4bXxoRCX0AGOnBicqLWEBbUtPNFMZ84XZvqY+LChYDge9K+q11nEyiohi/L
QxFOG5hHJivLJOHxY1XDakoVVG3O9R7rSy1Fjxw3V1AvCANmsn+7stSxQOW3Riu2Hn9E0m2f4XkB
IklZLtxyJHn7b3EQOU2H4//Vu+r40VdGhuLyY4hTESquvR4sX5W3/UYcvStw1qxXkl3L7s+aINuM
rSpWRRbcGuyBSBWbIf4kAtklE4e+GfhtZSFFsfQGPSFZT/oOW2zLQH46vGwGMmcm96Bn5euxw/OP
9cC4d/mPU6rO49o9L44RZGbZQfDU9tZRHEY50R15uAh71upKT3l/biBgWcrxXiOfPxMQ1jVoSitb
3eHK0+XBhns7zBkH8VieAJ/pXr4PMn0Bkjrr8namPaHdHjowqALkNJTxUTdDJHOrZTjeeCh8n+5P
LyWJAQ1M9AQo+1whKJYZxSM5a2v7eHQKtRcji7ylzMxucu+l0DcyZPYHRYAD6Y4MNOuqRs6ThIlO
d7oOyNr7pk6c282sU5ZqEXZa8bjPGmfCySqbPUs0PHgipX+b7Q+XCPtzFDgP9zC6MkUS8+F6VOK5
bcCymaN3mQ1+GN1FCV/Vh7vZgb/OAfnAB29Zci6pF+HtdamCzwJUjz6HtARjrNjb22UcrdLWn3Bi
BdswLLWBCYwXAUWOXB8B8Y93lHuNOlEtU/wjpEKw/B5Qy12Jn/WkEe4R4xWvBvWwO1XzG5jmeRb2
KlsxbOGPg6mygnxGDv347kDbJxMlhmCsJRfsafxHGe8yARiLAQJ/od7XGIhC5AJFFrRJb1LbgJ14
+0Fyp/D5Jkag6xv68c1j4KLm5Rx8Vto5NK9bJR4J3WQR2+Z7E4fR/Su3jYawbPYj8xmgphefD0e1
ZNTXE6xAlhOaCGDmYoUc7bfnCeIGg2rybyvgihroks79+rg6+uCGU/sqORKxmK3FHPkx9Pvmv2ft
OAGChnHozQ1VDtjP3fpw1lY1r+7pM3bQZs33/xc3+dEFtZXizE5wbKvGxpdLvdu1nyDi4Wv1VdFb
X1vOVRVtoJr+HMriABTCtJqPYLCoox8lT5mqwC7nvyRPlI+9HKpi7JGc3teBQh17DmpASGt//FR+
KxPovYUd62cRH2Pt4Qvm7TxNLPB9L9ARotFnC9MLxxnjHisx8lTLWyxDMjpU3OEpMNXsmEvfBE2l
5vbE8ndgnA7iqk0CjGYcdKGppLma4fS1UODv7ew6RzuQAR2V9J10uEIFpiGFWHK3zyL8+Mi49q3d
+5qiva8mJtcOvcZnSc1NJHpOT+RfOJWQdqDA5t4JKUwaVKVKpHtDYeLYCL8fPplmqwTM/zVmD4iX
+FXEsVFC7j+5Qng3GVWe7LLpx1pZ9uhyfnf3SvtbTj7L/Vp7L2j+aHGT/cwzdEmT3uhL03CtaN+s
H+0TQ8EgxeAW+wciKmUrqoH0Ee5gntsrNF9bUVRp6aZ3kpGoEk4SqYHaY9/0Iy47X0GIQ0ol/faZ
JN5A8NS/SY62ExlDzYtqv+TXoYFxZvjBIL+wQnM+VzVPZXDHsFZ9+FsQnKwGg0mtx/oFIfryVDly
FTUZbBhrIhJswZLj67kx8A09IC6/lvyHLwjMPpDSZHn9ap81yw2YnFHKMIaEvN2sGMm+VYycyBcV
uGGsznuSjH0GGdvz/+y3Fu0DSya4eXItlWYoiMBJq8wNzQGlDVjWwmsbekRlZFYNtB0G4qyjT1Wo
QBMCYV8ua/HkHFsk9E7huolJPF6wy7D5ciaw9XnNDdTF9IMOvkd+OPAztvHlHfhITPSg6c9zcRwT
qWzKF5sj7f21gLRJlpCXpK1TbtHgI3jE93OXChatbSHZRslkRaxWD7h39qMdEfHhKIF33jPH6G+7
WSDTfP+xwdmf9x/VqiZe6gaiZHOknf3TQjb9BatgGxCWOO/UsTDAz3VvCduCbPsR+9p+US8Kigd7
uetpwFxTSkfLoV3DKtShjpsMJyOJkgNs8pkgZvif6vgw4vnvH7BlL9kWnszfnnRjPGosz81WWdjV
UR3v4efr6PC79UjS+ek1ZgEvn6lBHz+vmDQTZueWJXHF70Wul1MZu54cXB4dPzp7srncN44u23g9
KXd/lfNfD3lzvpCKWFL+P6Pe+hwPrXwbMP2hgnntyFHBJLkWwAidT9rikyivdt9Xsq/u2kRM4Qtp
aUxmvmxInnVbI/AkVSKEYD9xhYzxFge8Wn06+YWtQhstVFkUVdHgSYhtIIxnVeky4oA7V6BnK6dn
trf0Uon6F/xHPVDnluDIJQgsWOKoDx+59wgFBOzz6cjjZiSj4Jr/+L1A/aEloD3ezhtGwtnoMu5n
kx/Bnsgv+Glc71EHie3dqMzh+HLdf+yis6RONHJR0TR373g8jC4VVLbFbpS7ArZ/3xnta4E8gr70
ZxlcNWYK4aKR+hFYE+wpgUvjpJPx82X+mH2hBfPHTJ8BYihoIjq2L9g2dwAfzd0Ajc7rfFK3E/LS
nIUaCnUGX3rO4neDEiwBP2BKeL/GFiLd4aOtvXtsnBGvjpxXg5Riul6hFTXy7HnNeKYguSwGcAzr
wn/1CWYrR7fzkxPwDHGRsfHOHK0FcjE7v+us4K28nzfkKvXjiCHeVuJrtUc8YAJQoUR8jyC6zDa8
e0E8eL8c+dgRalAZNq6BajE4gsLp5sBVGVzMfin9uhksNKVEIpUHObkJoukObjByf0dTlpo80utE
54PSrCv0pJhMls9YLblQVvVEe1igQojH1CE1C7m2CP2JlG+r51PfWiU2xsQhYMFKs4ezSmwvqOjG
kKtPxQfBhxxShVdxDBOzOAowljfj//23iN3yue4WTcQYts1gZvc805j2nn3wGBzv6+OOP1vr3GdZ
IvYB/Z/s3J0/BlDaMK0EA66Kf04cytHH6gHlw5uaqkx8Fo+yh/czrv12x1I3MAPmMgnbx91oUTIm
+VJiNUji0xhUw7CLs4f48rfr/rPaB7rvA3vzkhVKLU4PYYvyAUkANuW8PZAJb6oKtOxamOfFCqJV
nDbAXmncxsoIIDd/ORV2TvglcHW1MHGDYhqpQXHzP9zAR5YxlYY+HjyxJmrD3mb8ph5/bKAA5RhX
wKTeZexDK2aXFOw/JH59G7RroVcOPgEPgwvv/7wZOnRo9Cthv2cQERA2o9rDs8nCRElOq8ZThX6A
ly3vwQtGMkduYNbgcec5mjQfS77TJrUVAZjUFPQmhjRfmlQy/cbMUzwkp9g60fDdrecHPkZkTXFd
J5KGnVJENL5MPHX9YFV97vP3yl8Z25WFoWVOgXoFmE10a+ImQWINIBwpdt+z44Owu6Ivkub5hxr/
rFqqQ+o+LS2H0fvsLgBRwz2S4/N+ma+9MMvs3oNLYxxAtJUG2k6iw53HsUUFp3sTSCF71hOrkTfN
xLdOR7/uXxp2i+S6yfdHFokNk30jy4dDwJywHbigokk4WbpTeKoiGHv/PvEruX79tSAzk33HwrAU
gl0UvnFAcVQOxdGJmqaTDeiuau+PEbSjtLUoWcwm0/YVBUABJEjBPN3cW1JuPd0nh/iCU9ynySBq
JAc1OlFxgMUKc4PKDpM5qY7NyjJg7bubhHt6r4spmsp4i0ZR/zKgT641o1uzeoIbnTS7D1u7WYAU
qMPQFZEGh35qts+wxAiOfaBNPJz65rApl3TFdmsWX0GnXnZSSWY0JCCcOQ9pQuT1JfdENukTG2s9
S4NG3r14ZQJlLtbpf9PrhyIXboKWwqeYCCmJfC+/CcfIhBvq+xUQsSysL2OIVPkRQkFBDQ+1XFs5
OmvaUmcYsC9GrBoIAnS5eeZcYPx4RDM6o2uESRtaRdxbvP4J9hNLXe/yxpoLjOfSHmj+JbbJ3w7K
DPXgXpKEoYFxWGqw5y7KBBliFF6t6C6Cs6xICrixvjyE/SiehHpZSkl+EmUIwSD9D1ezkwPJQjzb
CCot/01jCPKQJkNHfq29pwdBgsnLsk9J2+LyozbP08pjN2ILCIHOKcddJYJEBwUqw/HzTIA8n1eZ
eH1NzlkYrtA++KZG+d+k1k69HMmVvALT4hDtlVmcXfBbbXRj5NngSCH9/37DQjecNFYD4IhM5B7c
QCfyoC3y7PN5n/Mef7BY+9et//5V/F8cJ/liYAszYniFewwb9guDuoWNJFpiVBArAADUo4f/NIA1
1xPJMT1b/LHzfFSiT40lQykNM3yJX0GaLzM+PRk0fNarxpgE2hTkhLvHsJK1kvByG0knsu1XNkzi
0D6JLySWv2WREdHZ+epWNrBjyP28z8cIT7ZRgac1Kyj9PpOiU9h6uaFt8liKjRGPFnHzwnR9vGc9
Skpk7NE+zOq4RNRTtlGRj47Ahd55Gclf7sMdSMD3/IEbLS+N4xiJn5nJTnNFSEO7hkzJAVxr3oah
8uSnmawlYKnyiBOlducP9A95bJmOmJ5Dz93HX9DT8sTOVndzs5lZ6yxvnvzKDypy7FyQm0GhD1/0
zGI8+nJPOMZlmesfXkkTlfvIJfRzC7ZLcjyboHpeq1sIqCtAe4yLawL+2hkJSHYeaGOF0YHZyHRR
TO+vFUmgkM8WxD+wvmq/FvqIuR+TKiQlyt//583JsF1IdiiEcwC7p9rp+D6/HFQHN6VtVDedIKcG
kws1kpkmMuBDxjaZ+Yp6zbmTRfDkgnnLiNa9u2T9/dokevp36rmQU0NSCHaM1Zr2L7lOe7eF6sLA
ui66S4l0kXMC+dk4ycUsIkcMjWcTZ2DPw0gt7pwCOmrI/XR8XCKUE+sKW4GCMei9Qsa3IBwHOJzQ
jgJ2EzvVzrKOy2oo/FA5D/SEHGLT+Kjwot40ORncaMhCoY4Clmj2CXjOi8DRsBacW3MKKupJJH5u
vCvE74WsebOc302iANxZBAGHCp6JobPfH1h5GLIGNTElQsyPgkcv8i4n5bLnWh4p+nKiNWH8jOy4
2KgssCtkCGF6iq7UsOFcr4OZwe/i/A16IUl3EUthFulNVr/94co9AVde1JCAdLoaJqJaHA74Gy7/
1B8+UpFx+QzXZrS6E15UeyKKblznSnhSfNWJvBrcACdiqvOjuqAxFt+puDBaXeWheALTBn4reRHe
ElmtXj/SbvC4gtekXsIsLgfWhhPgHfQk8ET+ovjSUQcOszt692fKqe5fsTphOXwfF9o+cyj48BFB
bQs4/hFP34aNtodVPvBkb6eCdf8zLndnWOKbYjoNzpC8Ladn9DToufBrkIF/iO/8PNuv9OwKhLPm
kdtfkqJuyEfw1kSNDKlLyInTNLW2ePY0gMUjmLbJ4PPrg4X/Oayr51qvmIR9OSh15lnrfs2MoS5J
UbAl2gKPxeUQn5sPZhaYF9FJ9OfaBu7tvNI3AoDlY2YIR2RwjV/PEP6zpEEP72OP7PMQPBHR2CL/
7tura21xc41DVx1kahbztrDduUeIId336X16Dt4c7PTVXfm45PhzHMn49Qv0F8q8sFi/jo9A0rOS
YJOdUB0Is/rpFuXVhqfnzIaJMON4OB4No+94jLMzygsJBJXEZ97DVVnEhDQdzmIivMyfyd+TywKu
EWOhZYjbD8NQgcBEw6Y/iAyba+DPfjjxIVfArFeCeW9czumcM4VIVuAHNH8aY46Guq5ybuaP4Y2L
Fts/toXFIDfgQ3JyjiXKuiXgQG3T1JXx9Dm32q4kj2b67Tuzx8xUocm3EaAI8UK88QEZN/qez6Ed
3nuy5WMm7JcOzFudt6Dfa7qHi1X4dZUFePQIuquLpGsinyLxitz4hIkduBWjh7RRqJ2K+6XDv6LX
GP55uh2Qz/RZYdxdlXfCnX4uIytpRtunhfr1b1vnB4VMqxo/J8NWUBOjRHr52eE4LmAybuzB3NLe
3Ec3j+6dT92ar3AxgpnFf/XAH736L3y1hf5YM2jPMuI3wVKpMRMeJpliFfNEFH/e5d6y8mF9kNRC
BXhpStYzOe/QG4QDJIzCd+x/cbVSoj0YItH1dIHbq1Vz76t5peSQzyw2C6FxD8QvMeMtMsgpX5BY
/Ah75Ch+Mb1kz7gGxd9fPc063qgs6329fD2roo4KfOLduJLB58MOCdOoWHQYkHUm3fFDc+CsZDmy
a3Rhana9RgpUQ0ZKNzvggSHIddw4uHScfYW7GOUa6eT6HRpce1a+4nBJQMUfz4FtmdnFqBjpSjRp
wHYbuahXA3xL6dEoUTqOT8nOpqWB2vM/77gEp58MoHAolf2Sfj70ct6zKClxVITpgefYIE5wS11X
viULTAqC+qkAAxBWAMvx7ESJ06TPkK0yOFKdqhLhC3/A/Qm3vU61ZwfFvnVog4g3/Oz2XsmTmLvC
1WewYLWlO7YNg+r7WOjcTLK4Gh+bcg+y7vAr3YatXfh4zbTYrGs9opnDQtR3xJYgq5iUdbi+ApTy
90MH8NZuh34chWjs4nHtpcbrACR+xJjBf8G2wdxwlhTwJ/5RoRcZc8pVsw1PQEyPZ4des9BeLSKp
dVuyyc5Vh3XLxbE6xldEYlvMHgvyFOSb5W0fxPJbs+ZaDg7oSmJk2NGPIv3KbQfDs6Cej119dLPN
OynQdxJbHnMMuZQOAKJ9wtJb9IG3hPPfMRscQ/mF3rGq0Q5ZXL+gRQEg+WVrCNE+UsSGDcbWqlD1
FxzIZn6VfrjDuFsX/Oy6ux3oV0NKp16C7Kee7pztE2/5hWxStriiG3xXpqtUy8k4L0NJubM/fIre
LdKnJKT8cSAI//XBSYxhFjFcmkfmxWfFTX4z7Ii/AMuOqTpaYBOkDfha2e+Jpuca1rKeb0LvlbAZ
fncyyAV27iHbAtF2xH1E7vDjhDLVxTVgRQ1gzMUnpOECoQ7/vIqRyQEuauLMu7J6gHg6uHFQkVkw
zbCoJZfvGW0ydrAYvPIqrhpcwGA39b/d/lgtzb5LWnDDLdjvOyczuRxFmpUjAskE98RxLX+qdceI
ntD8U8joPX+hdoo4OzFHR5RDvwIsxn7GxkNS2gzO1GW4PvkNvju7wn6otWXAcCzINriVB1LqT5CZ
3jo6nHpv+3TgXjSGinEOyQXujGhlhcFpVVqfRbuO9EKGcCtST3ZwOWUyAOPkVcREjSBSDPqMDPui
QkLnwRRhsgyjTwGnWOIrrEBc2fgQ4BBnhyfNat7V/XL0nXPnwyLE56C/QwQCMMp6AuPqkOw4Ur2P
erpGCJS29alCAcMr46auqioaSocgRWKBZYeKCik3PYl6Qnz9slcKMnrrjQV2Zg7P3tyYs7kEJ2Xq
TbRcHam3FzbRs11AAsY/PP3O0GxPtvT7Wv2wrFZsPZ4syLZudRXezTrNuMgKfvc4OmZYQ1/WGdFx
62pEElt9Gp1mnAeoOfcC3r++D1VffICB1hNads3oQgU8IjIquA1k5qsBZMtQapCBcDOw0Tg4T/fQ
vmjfhqA+JTt6Nh/8MlPsZMO6bAlquaFCkSljMgM4FW1n9Pz97SmYc4SZYQPdGMvHmW9SEFNl4RnN
StZR/WaF2KqNqq57H/cLz+KQEc2vFjrEzj0BRbQvH8IeOIihInIhFRVEc0bDjv4mlA9B8aigqpVw
VeK2UHO6+8OfIPpQRozHpK+PfA/IFjOV5n3BKcvaAz6gRw2jtUaAmNWankNYonaPu7gBoorgKQFs
xCfbvBGoC12wN0waXiFT1LOxudnSJCAp9wO9fSs6ZrKHlAo/iQwpaQ54rqsY8TpU5qQGeUXwxKgS
i8cTvWyD47XAFG9EvHGjuUqQu2a+40HiSUm+C5r1QfiarUDJlMdRw1jIDun5tfdePMZvzVBU2zD+
IyIAcn96N8EQhmL8FIKHbyZ9hMPAi+QfNTTgXnWr6yCU2WxDKKk2h29O97ez1bZvJ4AjGFh09lke
EkJ4si69oAAx3xTr/oQcBUDR8puefN3bvBapCIAo97mQ7eS8pVYCVy9brB24lAb/Jux2SKk1FkJl
LroMEKFOBfBc50ZkViesGcSb6KiOJH4RFtQbqOAOkctdiidzb9XCBeSpIcQdguTcMgsm6X66PJcJ
9dDjHEbf41IL6GM5wDvdIZ6GGH+iDOESFJ247Di4lA2FQOUl/3VuT6E6K2dJ5BjxOiE/oY/qPcDv
ZiqdLnqnfHy4EJHtKWFmxROqBc4RQW8jzJMLftdcuMPvnF9hKSgY/z5TVLNPrGFXOhF8dR/UV52T
TYvHEQLH0mZwvNFFDi9QHUovYDK09THErXqjLDNpEbW7AKEdS4W3E4hIWlZtdgH3K8LmIGfoAADQ
IZtSL3J3mVIYYWDBk+7nzJD5m7vTOukHo6fMfadN9y0AqIj+MG5DrBCxiqLgiEo1fx9FLHzw6Jvz
WhH4vzdLlZfxX0vDCD5mf5SY2/xXAfoRInrK41lXsRGRlZM1+qAu2SESGNT61YzotJCguZ26rvTP
Ex/k26BUCtkK5s+E0ufc77/TovQxXWGdjUWvkVuA2ETARg9XnVjHdgc9jATT50MfegZuvOrTZxcJ
nV1HSLGokMCEAEQaMiDjeIApWcq5vec/wwyodB1zl4EzhXIuf5Xn7MhOjyJJqXDjLJAeGQ7ZWD6W
kYp+GIZAf/vYHXVof1jrxqK+pBrVITD82ead3r7SX1DPSJVQhZ3tHAxaYnipCa+w2JFbkN2Fm225
hacgTNqDCMbw1r1UGwWjHW1OGEb0rt2oMxcPQ9hyYMN8kIMsSsdDbQsMxW5BlRJiu6Lj4EtMhFcK
CKHHHMS1PFXxzwQKqlsAR9KyvFnyJGGZztwHgqDznXXEOlsLICy9XVhhiXVoBNRwrCFSQXkLpTlE
/51AzqdhKVIE6cz+DI/fzn2h/phA0se5TCg02XGTUEZXFbhi2Y6qNTYwX3Hq8CS7Dp6krGFAH9+R
9Sg11HNlxW78yKTZS46B7MhhyVRoDe9zIy9jnKsaCe/SMvFLtR+qDnRneaWCsLcPmC/qWbIRYiP7
5lpuAKe0uk4RFL1ytCwAGyQRNpIOtLqL8sfMtfU+9tjDmt2FDYDT8e8hke249Lz4Sq+I2W6I8+fo
KdxNlOsUoA8pq+Na1p8G/dVzKabG96xvLyZA+qJCsT13C7fyke8Xh8miUlbk5H7HhGwq/iTgBOlx
dSr04tOJYk1DVgj2A/9Ca/6WZ9WDF9nhSmIXaIgovef2neakL/0ZnurshDOcmhG97JlF+MtbvLTT
2QcLqOOHNtXihBonqcj5QTc/hCjsSXqZtD1jY5dq++Omb25N+b4pTXo6/Rqa05uHiJvaq5T4kv/0
rA24nbdftKDoUHK3YtviH1EdwLqMRiauBwqku2dwMi/OBNhdHprrtBiwsMiDNtHBbFfR6A5ebZca
81YFSR4vr3VUHzU3VtLjQhKMcRvU43w4yKRjB/pR5vDiLkHFAnaXcCiCg4aEtAuI0LUopXQWbXC8
//xcEORsPWqJKDuEuN0TAn72JtncUZa05nzQdQ4vm0kGN3YVjRn3e7iVdEHQ3f4jf+sL3W3unScL
CcFUgcLso1uLJ6kglJt4F/k1f2KzZvHziJ7gFw0qo0EzD5th5guvMf/RfCZ4Yhfbe0MFoMkEwpKU
Ohm2dFYnsvDbHYcwykTlPMDTRr4JBSsGPXoLVMyUXbLoreBcZmALoS/PY0S0VCjuM9vyo4kqEIxM
Gl779sUO6LokXbjZZskIqMUgn35fOOxneX7CGfMrKG9MuQI0LE1+a3AeN8tmZBKKezPb/eOLaPoC
LDwqJDjRHydCBOyMT3STAcht7QeOIbC2wKr4qkXoSL+z/wUVfcHW9iCax2wVPZxgTyVI8QIX9YPr
FMy6rt3yN1ChTVv7q0lNRVMoLY/25OqximDJKlWKX7s1P4FtPhrR8KX+SaGY+D8yEuFJ5SYWae8D
fqi6SY3IwUoGNzkshamhK1qNeG5viq7+JkJWuxi2K0mAIRk7Vo6qwuzZQMrSmBceOcuUKqMDnptl
n9kRfEbICmbMc9JBxVm73E2yiOzy3STejYst877I5AxmToCBrDzYArl1X1jmY5k44BDNKkq3F8x0
AtGweQAn9MbiWZbQDZ1EwCX4cKr/rqL6Jy8SGIvMUgIgO7YAG569sJmO9M8SbSm3B99zWM7agRxb
Z/YUixqswV/N0vyJfNVAbpmi7A0wD/4PQCm0VcpYlGHDGlxfXi/TXzBgHuAvFx3GZZ1oR8u+PiqY
PoBKELGMWqMuQ2/+Ta0ukAUOpOiXrZ4w1RFxytqQfS8Dwu3ZnIBmrSZbwbMjZ4irEFsVCnJ4jsou
AuyTJVNurqLCj1h9pz0MHVADxqqXB4724VAc4jutoUuehN/kww3W9h4G31O93BNef9FwpeRC3zGc
qRVJv/ps0PveFoJuAdqJVLjRSTIAUSOv09TNeFaLlE9uQh5HBDjsouKNYk1p0s7ZQKPHjmntYRR7
1RDIgo5kqZ116vMZruiLc/h81Lf8AdZoanRc2EVrQkS+QFSo2nnaXsTs3BfAK4zRtNOu3EuQbj2M
i+cjW9rdlZamzA9Rn4Z+wj4SbGydlRgQBPLR+YvCxEaov7SjHsG+w30TBgwpvIC9a2ZkublKe781
GtOMMmk+5NLjeMK66fZGyjqw9R/4L5PlzSydujCfjBnQB/n5WHEsY2Y/9KPyUbgqlt6a18yIfSZw
7HSW3bLYJpZ3uOhUGLlF1NQX0eIvHyoI/Wxf2fRxOzA/PsvX2uFe/zQjPH4KYZaYDRLnP7zgMGmm
5jFDcMwjDCipTTYdMO1wix7mVTeonbF0ZLYnCc21begWazhU+aQyu//cipL3RlWz3L1Pmo8H9E3+
ckqWdjUhMUmRrdcW+9/pa9f9uRq+CNcoq0iXU6RkzcebJVeqj1n6IqZt9CMpRA4XT+6CF7Z7ENT2
F7cumzO6m17RZIAfqsuBfj22bYsR5si4jfxYSONje0MUCnzwMpgBOjnsaDeeHUzZMKX7kdVdJzor
UbcVprSHYkkEiP+ZF445sKoGt3W91ipfdoXIhKEHkrIeyhNWHuKhnCpZ2qXmEnNwhFDd9LzIVPCy
oagn6JR9avvNjkO6E5rQ3H+Bd+c9gzug53OK2MiNMhnjXa5GMAPQsvPu3eTN23DxXaDUco0K9mAq
OlwMYxr6TRzv4c29IasGFjFb1SjiR1A/HmjQBCWjdC5cxjaCUeW4+AO51fU32iYw4+fs56UStadG
OTTg60ZAZQFNNrGJBLhQ3zHOwNAWRiIAeeTxyvPZ9dyZZYoq64TV2r5mwfhExJzIqi1L+Fp0LFx+
mFYxx6rfx1M75QFNnkC5xCA/oAGQFisyv4pbh/Fm5ci5vsz1AFGsK7TCzZ0CpuAAiIxHAgyFhLqa
JnoZtZWEwWZdVaH1fK2o83x3TZ9qRJOIRplaSg6nsK8rOxAIyhbWOxnCPmJf9N9EuefR+c9ZJ7HY
5v/GL13HKPbq3hIvMFYd5DfnmLsYKBCBEMYsEKTtLXRHlGIvOlcm4hmTyzPWFwoDkQhw/p9BdS4u
J3CKvc/dtIbeniojo/0jgoxfa/YJcQARXMpEgnJDitrUoCfUUN9rW/tzc5i0z597UNiYqnSQo6M+
VkS4OP3w12V85YvOncEZL4yl33YRdVMYDLiQFG1xsPCJIIa7Qpi2/UbRpp41K0aqLIPlGDkWpwn6
4rM+qKm/g+3PEf6pt1fIf3KKcZHdt811FDQNPccdI+rRtaJLYUiMrK8NUL1KClKYOZo7Utmnq+9N
rF5pfgq2nelvmd6+KATc+iJw/ICT2TMD0ZrbthlqvTW0PxzuhglLO2Uc6bgwPmu5kashkmuMZvGh
mO9eRuE4o0gFZznqn0uGmo3RkXdINjNZXz4KFPf6r0OXNs+iB9w0xJq2cUDUZfhBQmOVfDKwrKBl
Zy3wNak8RSTMKzc1v0+9g6nfa1M7NZZ7f7DSx5DkJUWPwu2B/6ho/Cd9by3S3owAYQCKXD8isCMu
OtJZxoWktD3qJOtX16/sIt1WhcCF+V6fWQeOjKHtC9v2VpH831at58bWWD7CtZp67IaWz5f1ys0g
sw2JZ7ZzRXu8tyKww44KHG3+ZpzOwnNJfE+buwJnfHplCEgHQF6iE+s6kgcJFfv5Bugbg+vHU7OG
bvtiVEUI2wBg0tCYVwTL39eEP7f4Jh+eSMsNTuVqASwAh+3oE8ENo4NoOUYauRqNydu/J7YqUkVg
i/r48twYkXpJlzH7kZXq9L0J/0V4TFuYPwTUC2qL3ZQxvJDHZ2eW9DOVE71lzkxy02ryDwsZ3u61
0K2gP/OE6zBVPStp9RRx2vHZLFL9drIqXGmfWIKUldi7v38SU0a4BoMauGdUB8x0NoxuaX371tTb
r7fysAFHstkJoBQREHxvPvcM6arr89ym4emLvlBlFunh43YmeSlMvZO+iVZ1r1XBZ8bJkDC/hqgx
69xe64kH0b+Fk5Um2/EyFBL3LtFuApg79PAKy5NxV6EdBzuule2E23m12h8BQKscgjQtdmdlxBDg
fQn/WvL8pI8PFCs1YPzd6lOKkDfqhZ8PFWGAwpgybFYvs2poXjIfWZMqe3BnZ6u/OE8vU63Nhd5B
drVJJIYHxciSLIXbEWXhquUbKKcE2iDlSjkaOLienf1xOPwAPuhVNykI1f+GPkZ73OBuI6Xd2J8Q
kp98BX2XjJG6nXBkR+qynCqNJsqui01tbqaGinhJgFCj6QTwF7/myOVinz5jOFkt72BLGMRN9w/N
gDyen/K5Hx8F418rv5AH6xGYruWjQSH1031Lh4g2k5moomSUvnaE+B9Ll4ARGU/oWm2VnSCYzPda
cC0qZONQB9fiELEYr80Bn+lM0Nk5xrPKb847tACDWa7QTrxZvwG3tjNqRWsJsXE4CX84NsyFMtwK
8m8i9b226dmFogdYB85oz6lDwAPd55MWsPAS/JmLwLm7O0a0eOzY7qwwU3s3P3Gb0LtXuvjt6Cku
EbT/0HIzfMeucINg9m2BOBGc33tT+t/aVtqJA2nOl8oNzTGjOfoVaqxzOufLaIY2aha3qMjjlsep
z9ZdygtF5JHZGM9T8bXpEDc9OljphqcPcXZUc1Af6K0REDbin6IqitTviOE9T6sbl18ZSyGnRjeQ
DGzYC5X52w8VG0VUN51ZsqWSP0v9wKNtRnI/CJepVw8ILE4DsF6BLYpaB29XzwxGTZzka35nJqyd
+K/sAfMgOUVEwvXqjIyChgVLYo4qsMo21BSXVPOj8GztzdshtVyIjNLNYLQHVcbDw+H2KLat0lKL
gjZJiAbFW6+IeDYmK+/u4fSOGLbvV1r6GVpd5yOXo3cMI8tbl9AFaLtYBzIRKhApTtvC77/ED7na
J66/56XZQhqLHIefD1wDCswkcvUWUYsvgY1juCEtMFdN5lyZ0qMgo6Peaj8xGxFRZC9hEaXjBjUD
EXkXsGvooZkS16fCuwGlKYLjd28+ByadyBf2BUKqB5N69X3UjNsDOlJFqb8gdnOdFrWVS2fIZk87
7vDb96P8HKEf/jqBwe/UeAL+7ID11wwxpdvF3pwj5oBHUuQdQxziHV7lr/7DmSVwI2QCZ+n1c0Qm
M/vgzOcFxtKirET+YRfLgE7338jP7Z/3f5KC8i7KoxbwtRxV8Q/djeuWZKY49fnqSTvkmPOJ6H2+
0irWdqRU7s1w1IlEPcW3HOiRpy4gTgixAk0xvnrHh2z++WvSzMHp6gFdJJIfONavrHUx3VifLkQl
GYwp8icRgFZoIdF3vroRzZug7p7hqpYiLKHnAD2ukQltNj1sZc2r5OwQ/QXxibFsFuZXcIBew+4J
pMQu2IZ4T0eT1iCUucUtMezskHlVpR/Xj8HA2qyzU7oiyxNjVd6ETT8HvAbNZJOsq91xPM/OzLRg
HrzoRSowixE++fQo2bjulVJOGJqRf/5k9xayygKjLlZVQIUung9+tzprk2ewgLWUwCxmhVBjuEm0
PuaDOpt9/CQQvqCtqy3tt/Km4zg7fYg0k/t+1mSSCjNYHXHhbLpH7w+ijvu1sMtsJ+an77At4Ys5
QEj/0EXoilHu/mkRavOqP8ZXJyKCmEN03izP0WEC/NEXCsAcP55601wB2vkIAYnYvhZ6ytbPvQmj
b7wIRiw535iX8mCo5Zw5TSs2XAFq6PecOImzBdJKv4Ti5T2ssQNfaelMFFk8vT84HxagkE4ZOh/V
0sxKSai4AwlamRPEkAH2JKDkkhFgOqfTsrvqY/mdeyTjWBA1Zulz5Ktq9uSdLbu25ZnKkBFgDWyX
rfxXAgECuJ4L1k2M85hTOYHDffvJXaD2xNF4iEaKYFMNteX6uqCNHejdLf4pHuzB7FcorCrL17TK
PlC4IX/TAd/spRfXPC/tz29oLeY91o9jm9NJ2S44GsRgS5ktNXoDZ6S2Bp4MW93UR8iAdia0E43/
wtDqrhZGM03ows1DzX2DuJjdPwvgzmF+fmSO3KO8YXaT1zbGG/94wuEYY2BH8KVtkcaczXxIpKur
tNU3znhSaacNA6Kky6r7u79VJdCFPyW9RMaRl7DaSsXbqPnUJiP1MCfNWHHQy0CcofWYIp7r6k1V
UTVjwnS9E7/zHfGRNGj7mJPH8Wky/gw/zjeUOVwmT2W7B3GlqKe1Is6gmxJ1Cw1PintJoOXs6/Mo
2SJ5HtV1g8QAFy4ErNKmBRepVQmUPRONl3aKnz+jHWrFktjziEFP9nsUaqaknGhxR5/H9rA8hzS7
8fRDkMLVqOl9xvJ4Hhw7UThF610VpERi3mptwrUnAcIFMVTXvMMRe9wuS/XHhyMOs/Z7fpfxEcfa
5Cu/Iit9JNTZKhFl5LCiUttdrGFSpUGzVXqCU7yn5Xw2wOwemV8vXbu14bB4T2Ekj5L1rmj3lxpF
jqrCni2BuKuz2MYCnUlz17/eLZlYadVs9KG3g/Uz48fcx2batRz7dSZV6QKh6ix3eFtjld8I1WqA
a7FNp0bfA0Yz50EM74RXePJiAtuyhag0A55yxaCYJR/JSoGjGfD3f5csFcOePwUyYpTQVFVxCI8x
gAIV0jf+PX6lR4iSAAh/7EDH5f+mbeHmE3E0zndSEb00Fd+0UzD48VW5eKk1dJ2VEtpIT1bjWbEW
esxTldkdwgwLBJi5RWqpzA3w6FhTdoSHXmM6t5ov3hvX5F+T59kt653dDIEOJ9ix4BXRIlOlF39R
UgTpVsYNlsz1rDAI4UauTewSw3/HyBtu+ov0DOrLFf7LYuZ+mmBHfLvv4eoVH4XT+zncA4vFprhI
TnD5CnVg3+yeJzVSHoHnyuD8GwVKdheyXPv6hVcSmC4L3DAesgDsRmwMCdvMfwwtPO48h5v1qL7s
6tKlYwNmU2xQndywW83EPDrpPjTXmGX5WXPSVq8UHRwGk1rLR8fRenBZ8Ai4tkQmgE7lNZDJB09c
bq6Hw/WFsIQ7E3Uw/oRJmOCTL3VhdeVc6oCjlSp0jQIFCfYYR8G89ZkwafCD4Kb2W2DDPegvDMCj
88ZL3HlA5ac+B5q7PrsadljFWyPDqQZtVw3A9gKVvaAVDvR6khcgj9sRV8IEd+Wi4R8+dGniOTSX
w25oWAd9GdfcG4+eprAFJ2e3/SvGRZM5EQlRNZXNzNotgOLoFKAsSNg7HqGJRwABzIsIggGOrjaU
mVfZ3auSSw2WAwmqoUV9+kLAEP3fHOHqGeJc3aOAINdsOU0jbE+b3P1f4aEVGDeJGllQ3ePmzXLd
FDLqVMe4yvW6DjUYCAxEgxuVI8yQiJS4Y42a9I63QYbYuV6M5uNaC48+GS50hFbmsOk2UXCLl2iF
fbIjSSffq+DhsdnfcWMRb0oV5Zmx9M/ViW+vwgRKbHIkGKjjoIoH0YCh2qosPD3S+ncNb0PpcNWA
O4GCDxPD0CJNaI/eLLrsoHxXX3IjZ1FghwxStDvalxrXU13JoOqWo4SHjRC/3U8FlzltYsXIjB5U
D8GTK8+XTtmBcx8kT3nRANzQ6aY+bLK4IPTgVOQf+SC4jUWbyRFTFi0ic88aec2cExPv7FCdKmp/
6shx5MLnUKe28zgLuA6BT3OrUOt7DP5WrEWtJflzg7rI+TXuzk8uVCu/acNvBhCsK/pWHH1tWkxp
QAyGL1glS8OOPakFk4yTwK50tgrMzIcnkOoFJoeCS7JjX83lQF1FeVZo2V4HdPzNgUDwn++nOuhv
ASjPmskCy8P/msFxttp2QreUs19THlnP4FVl6KwlRkl8GgMOnSWb7POHutOuYtMqSY6IIevjFpke
7cjz3GkhDJVRt+OfyGb/Vuklc1HKmMTWDVVVcZzm1PAxzUHrucl4RJoZaxq0F0xSUTJ9c4P2DpCI
jDvlnfBngodba2L6Z36CfiHG774aKaL0BVi001kmLfWjNcVKREQBPNH8OXawmWhIjEht4Bowbp//
lCkomco2Qx4G3Z7gOAuo7BRZnlLKoSfEJLii3C+/s93FOr5xqaYqX/0EEPyCdDodvVY1QKU1f3qy
qbeimfNhMvC7AO5KxFTjpOohSJKAjn0JzW/xkhma4dKtB4/bP22GX7GAifags/c/5FAIipV0SIrS
+0J5it2hOTvvyxKb3SAJtlCe7kdL1eMOAIpxiRXu0zxtp48DiAS46DJwAGqUOCc7D6MjU75C9Exm
+jfSRbVA3u7LHl2CUIlsbJA0Gn3JaFs3e8HNyBfFbkB4iy7rh/GoiMoTve6IZ2U8Gkabe/qblYGP
t+6DCD7Jz+6Nrv7HTnefRyZZwj3Ts8lzV2g5LvuM6UGTwOUEH0S/CAKzqFXomLax8hPssGCHYPBF
GMhi1wxMBsLd/rESbH2wB7uIqjVOEauaLP0zP1n8r9A//7pxYHFkgkO99PzG6OloQLjd2PWpCYbz
qfCNMeRgMoi0+7rYc6ZtMEK0vdpOhCCifWKCwSMvoHM2lFexeS3gD/+4MSodq5jkM9QkCyfiglwL
JB2A8J14jq+IQAXtPeGBYTv//COvUcuwm+OprTh5qpW6PXWBRIGDSnlNUe6U0hR5nbybQT/Hs+sZ
QnEIbWKdSVsGBUf0d5GgPzKclCACOxENpPetuNEGKp+uoEHqtB809bNuUkQyryDcNFeX/Rz1HJbP
XcJRVtm/zmlIUZ37OsH3d0NBfbPvCyshIDHsl+1FOGDIiTueVEJlh+jQ534Ub+XiRWKFX6RebA0a
Zy8+U4pJEub3XJovSPA9mKz9ChBAZG9VCA6U5dWwN/QKxBcG3krfD42s9vkPrJaEv3CjVTqNdwIw
FEnkUaJt5um9trudpK66R50rEgKFgAumbj9E2ox+QHqw9rqsTtWDEGGnvSKcgeQ2/aoDQCR5GlVo
Yq/TJBTCN9w/F2s0foKQPw/L5mQYRUNGzBZVrpakOWlubkmgNoGup4mpwXf+ixhmARjK7sNY0MO0
gwOsTOBsyCA/4R35U+kjuQMwOljWTVZJyBlHWyWVWLv6noELtr1UY63hhD6j6fAo6lNQXR6DVr81
VKc8e5ZASgdAAb6YtZwsFruIV1Si9BWZgRJlkyy6JzoriGC/EQC6RJ2f9o/BjsMK3CS1+/svsADM
ilcwngraVZ6nsOK6nxcB9Ongasbdh5hzC3JBVW2F4W+SmZm4mVMcsl6y0k3ngSBrpyn1+YoY/8vC
PFawfp/NE9qp6era8CnFNTIiE2HOzcuo+aNlIHPTrA02J7AHqCuPs47K27WTnG2up/ZdCIX/Sc62
vIMwJ5gVQJO+VOE7NJeFOSngDv2IFSZhxXCW5s+eTOV9tgcLYYHNUOFKLjSDTLRuOWl9NbcXeHKm
MvUlMXeFJZd+a0zCZgRYAawU2UbWj0tGVm/dt1C6zbB3QfFLUyAzpVRmzV3o9voA7Yzx1bMIBymy
J1dP3Nh1yV2FeD+33OpPR2pm4cLG16RN+m/mzPICry5I7sEvDNcsMNjzeQ6IvkX/UJuQTSIFMfNt
weKRvSAYmOhnWQMQ8iM43B//JzF3No9a0zXMkx3NBLXB/0mBM9Y+udeTwrTlW7tOhVS/N/6FLiXe
ivRxAMmkjOuZwO6bKdgw0oopI2/CSzXXVt4rOFctHvHgCAgCe+f/nvO9jrirSzLQI6pbqtOS/SlW
NbRmbxGmIrdhgsBIsTopL1aFLzLPiUxINPLEZQd/Q14sbnkFbywfC+Kcw+tbLNQCrLYrZUKERXQX
/gF9ySCsiNN9Bw/dKod5NIYPGwNveomZJuyCIHg9uKwW+zrZ2SSQ6jhtyBE2paqLRazwwQtG5Opx
2v82i9ln0jgeskYZJHIkvcCkR/rqNUZ1guv4DGO9eEpm0JsZ+yTPXHbEzgTGPnDZnmFLdCxoWTEA
+4x8rd7rAiwJ0AbTbUxZmoezV1qhmhXzuaZfe1KYPDQUxGS8tbCH8jvjVxP3GLF0ZYdcJpIm9R7H
NU3AqeUNIpBAGM6Xgy/nogfKs4S3f05hea9xA2QhBvxjDvMKDXQ8V5T75DTfZNpetJrzXIWr735c
4y8v+e4rZU6z3K/ks9V9kikyZzThktSEKrqfSEAShK8njRvFLOv9G9MCPCT9atr88AZ23uQti/+O
OgNaEVpWMdgzzjxM5m/wB53j/rH5Q8fG5AmMYn3LMraAOa/kwNx4f2a70wH3hJPqkecKT5i3vPNW
B8JmV4UZ/k7daskK/mBPPoY0GRYht6FWREurfSY5abRh0L1dKYVOGdm6OU963dJK+t+ZWiK9nmMw
05YaS7rrkUbbnqLnAt0SltJmQe6HjBDT/H/bkm/y8ea7Ba9/lX8NS5R8U16sD3g02UHCkdjXf018
guxHLzQ2l0e69AHkisJyiTL5OlzKth1G+gzdtuYKY+fFPXeoLd8DGEYXPK5x9904C0NA0O5jUT+z
4V7/w4moMhfBC7omLZzkOIw0IqFHqumVkUK7zlgIhaLtYkxsKyKdsWBiOKomMACZrWFE5xjLDSuH
uXIqi69Zo+NQ3cYINRDYBDWOjeQbVZ29y9w6GnZTdsXjXKOwbx0uEywG5gqZvBlPqAc3oqkFbfvW
J7hKrJbeePIuUKGhTHHVb7nO9FhMCGh/DzwTbG/9gMn33/hItQaFQB7aqi576QbHto/wHGEP3HVV
MlLXrxi2gITPKXf9M6L9HYHzJvpKJR4KAO+G3Eu+F3lq52ArHO2qYZNSbh6FKckPA0JgUKxWeZbo
Q/3j+B83m2tyDGj10EIM51IfFjRV7ovhNwkJ/DgG7sO3DLB62y3NC9ZFsz7KcO9ZfNNiiJ8zqWTE
zxx3vP6fcuUQt/dVdlr+kS69qdTtNhObgYTvCPj1Nlt9LcE7QcrwFrUIv2cmUCxaZLRy9uYBzFxG
mCZqFIAtvxtauAkOBL5KzoxXO8fiv9UcZbxuDZ4E/nrKh9fdt+J3Xag/DAC0GJRiQRAZU0TcJDvL
DveriN1/E9Ta7GArIYyeIurY7AmyQ6GyY4gEXWcOr0+EKhFtSYQTF6KczGDDZrB2VAVisIMnj+N4
zs7YMQglFcEErZJLngkjksspsRSxBSKgu9UJ8zBu0kvUE6zSG1t6OtdA9MKsRxWxyG8g+uMAcP0r
DYLUNpt864p95mGJL9agkD5YBMaP9uPVavqQzbXm+UROI9VQTNk+KOve/VN9WXCw5bEKLLnZzN+O
hj5AF/TI4sgT1EHhefQaN4rL8f7NZieuC9Nh+U/NSL+f5kwRPXI2+TdPWcMDyyH3+xvIdhAyV1lD
LEsjF6fsTQ4qAdleweF9vxuOHb2NcAQqXhTYm5YZ2V+d3Zp1RLLdKV4yxPMBkRhx6mTufLnWE9H2
VMdjL3ELC4wD8ZVvOY8n0dULQvLToIF7cUOy/EqyIrlYUMAl8BLIOjS1Trfamrx4oALQVOFIpXA4
/BqDZISfuYuZMlBUkFjIs8lGzTS2AVX77oIJ4+SVoyURRCzuZco06GKAjeo2Jk/UtAQmYqLtmMuB
n+cIcVXfiKxYkC/726cGUJ91hdP/rC5MwGALDdnnFq0bK+lMEZ2q/SVCO6h/z1Q1i1h97QKet3KV
Zq7uKprpB+lxlYhN0JhkrQCP9qBsEaVYeSylaXzYQZ3aMtt9Ci3RAy3NxxIR0gLANM+cU/pgHFp/
UQa93H6ik+hTRO6AtBIk90kjTyjC/v+x03t49BtQrga4mMPCbpSunyIpqYtGchQ1Kd9XHNeOrJMe
lLm4Y8IfIZXhpzLceWm6AGkpxrnILPJcdDfLqqr/nn65MJ8QUdKqO54qgNU7sEiQV0NKDSVj6/gc
8vZG/uD79bJYP0mE6S83Fy8HO09gquO2evXZ8d5NZd84kP/GM4JnV2Ua1+95GZ0IIitWUbI4TwOZ
b/7HqdcMMZo2X854RM8MlX7cQ8Hyowcvqq6YhNUwvpDdTUYi2/rOQqnWaHdqNZ3WN8691DjY+IeW
qrDfnY1SPjLnvvbseTQnb+38r+Zg2rFB7QbfS0B1/Nf5YHcvty5tATlDHFcX9aFjeJHSa3g9ABMN
wzzYF4p9EabsDlR5I+HJ7UK6ItIrzNu3q0hEPKmWeo6G4KHmHmx+uRqV+siVJnXXL1uzP18qMOKc
lXRczQklXcuUxpr5nYv1f73MFPZe8gW1/eJfO3BDZN33C0CeQSteDxUHXUJCozo0DZCtbEfAPR55
icfMA2mEMAw2mdtbXy6Qss7rm2xF1DKffUvtbkiChoLneJ0jxEt40GIl3MPTiHvhbjBwIoWkBwWN
tV7g6wYDUzpqmig3jORbEKwqMbFX0A21yqoXzhdOQQiP08COwbRg3eLaaBgqEFVnaaT5DbM3Ybkg
08NWBHqnLZUTQEXG5V5/yNq3XwRGsi+oATL8Sr8skc7sz95NSJ5hp06ZiEfhPAE8rdsrzUCYJZUn
UZmoK2/uQhkHrqI6M0dJnZzC4eYKePJNoMWbcuIMmGSJqVB9W18DM5aoYohsUWM4rq8sSUHu8scJ
8ENNYsIBPGVWyk/KsCnttcq68Pn29lx3S6U7m6ZjYij09Qzr2jakKDfk8E4nghbhLD8ibiNa2hUe
yNacndOVGV4/EkZUXieuCr7afiNHg/5KqJAuySzCRsOTFHS4b7w/h6YxowYOxZE+mCzEHUIJVE64
yb7eF79UV6W5Be9UlrCZnO8FbmAJFy6XcOkJuyY6rX8ujUOzN8kLYte8gahjnqVoEQE5yqX7Rhex
cXMYBMveXjRqprFoiovszIEM8YYITW68KDyzJ72A0gZuAaIi5dKBaOh+H7H/3Q8PAWzJCc1zrYh3
WeyYVOUSIKkrGVWHe4CknsyZDuX5oWXON8YxPpu4dxf3DOu9//kCUISYpw6RdCgG8AjRdOtpbIuA
OaszBMUV51zF3COQYGMYVO89q28icNv9DdTjG9FZROyIhXcjn9qG5Y13TxPDGKCcPGwtKv4gGiLJ
bz5GahU8D/tHAx+/JAtkUYeg9Z5tf7j1YSFZiXKF/0ziAafAIxv+kX8r+5VPok3tGnDO8OO+gjVp
kaMuEtB+TP5B1t8NyIlUXrE9NDvmvajFQMQpbvrtZqCQZ9MxsT8/EyDmniekDmWLk02diSzX09/s
MQFCA9MxD8wEIj8hF8qVpDXTGAwIrk2sDC1WdrjiMYgtPkikzY0pROwM2RcNbHwslac6rDMgYp+y
kZr37hPLFFMwcPC2IJ04ne5x0WhNXIGl6i14pZiRUAVYiMcAP0UKVZzBmw7LKpNuRWI2rNDNT3dd
1XuiOOqXRJVb0k0R6LzgUhIFPEkEo+XoBAUZDLRxmx0d/eFhxsbVMjpNrmh4Ge3Mx+ZhnB1zpVA8
BqJwsfT/byda83uhQF7PQArSmHe/CGfi5EAcYss2T7Ka0o3308Z0TfmiTSOJIsuK1cvfr0u1N0yE
RszSX3s+5FQlKWYN4N5Fl+zWwi1ZFyeQdLabH7aH8NtJ+Rf2OKAM0ABC8jWJXqREHEVWo1Rrcap8
FzNciqX/T9q0QA3xKQh8u3sjha5QdTcMDXx1aXpEDfQEiqxFT4tzzB1utVnQxZa5pHv9a3nQEl95
1+wZ9u5j3Kz/Wq//Ej6KUkZ3pV+LptFTR13smkd6xvIsNaF2dNgNfZ+s39iKmScnl1d+8gbH+QDl
8xhz+HcfcjwfmDgEjGvl/GJ1TSEejy5qT+7NuRBTxZvQfy+M4hLkWhrinzh1FoTJIG1uRZlqGa5X
cN7ncx0zt5a7jLR4F2bjb7MKyJE889mcoSIC+aHiAlEpjLjrUgQkA6zYQ5UMuWiL6A70PPhIu0Iq
72fVwNsHiRETncqDS85AYSjQ9WKOUp01qTxQaQyil+z7VRtGxDZW6Tp4AzjUYL4wGC5DPbcWdtwD
cIEFPKJ6XDkDutqC4TOQnC6nJal8w0Dh8413Hy1szOggpbaU68J/ts26J3dGfTH7YGsRnWy598yV
E5KJOklbXbVn2waqxZHq3FIJcF2RRbDvzLyunqVfGVI48eIg2SjBTzV8lBuFCv7pViB63itAWCs2
VP/KrQc6V11rDrhLJ2nJGUGYzVBnh60iJq3uMNMhsSZKB6oDLjyXtPRVY9kiS/KTou9QMMUlw3Tk
VXZdp2QT/ocJizbDRE7KqbJtIXsbYx9kHb+ONkvlmohdcgl5tgjPU0qDAa0eZejFfe4yBDTGGj/a
DZdMzl4Avm/ARNYi1skTMDMJzjgR20Vtio+Z/foweCcqMVfy2QZoYP2/kSGFtmDQel6iCexD1y7p
xNAS9bejeiVKTFMAlEYPkL0uF4KOdh1i5IxImVuBTz5fHSfieWXglgeys+VK6tb1YV/MnZd8Nrs/
Rs47ZUfQ6Q/tFhsc5ZRsbJKUOX9p/0HxW6ZJY8VKZscjPANpxChP30b4u891AEuCDCu4vjNu8swu
q9COe8iAdEzl3zngFFHOpDRvFBd1/QeBjU3FdA6YZStWQWN7GwwtshIo2Qs1NZU/VK6e5JLBFpY4
KbGSqD0DKvwoDq1/c4Bozn49/+U5eljMeBvF8+UsYrn6pboTwcvvDJTCCO11iSlWDuudzYPUuGFp
MYyRm283uRG97QizmZcEiLXGyqObcJfceE1YfpWkCZZkoZGjwvhFXRBd0RBbjFiQzHm9L9AIG4rm
ko/lzg8BRWnt9wf+c0ltU7/SyMCxpUhiTBymwNndSCfQ4eJr07OrL+Ay8Q+7UaCx+2EnXXGk7Ls2
xrPV+b0x5woI5m2/9QVEQB1QShUwVarCDIqXS4gBhR6X8SeiHRLKnx253swtYKypIFMCWyfMFBb0
RvBkGLZKXGYhukIrEe7bd6l+VIUBRPpNx0oGl+EPz8D4VmjXIzbO0vrVnHAztKm5SvkiAxa1aFDv
9bCX/6Gxq9Ln8JI9G8DHnJFKtWmW2521GI7vW3lB92OGIXpyr+Os4u7j8WZcPPHS12FrTGAZmZAY
+wFgScCXBSakKTKFWD7SHqdt7yE2cIqBoUEnyzWeECw7ozipD8HHXHWo5soN+KcgoGoSxQajFGu1
Fzat5qiMyZe05FmosyATHhUsKJztVtcx5YnnTknSr9fnfLHBJLM5RCMjng62Gh+p+b2IEAI3CJ0Q
uNQNgIkuJ0Hu2ICa5KJH4IJ09GRp6kMe361gDtw88PzR6ukZDqmZSsuJG1FNClt+EIX8/QbtigbQ
mrwFEu5Rzz0nLx9kC/ufaaTPQ8/RSJsaX3bFj0OhFzIVxIWBtQYSPuM/ty/DFele8fX7ajeww3NZ
3fGeFFSBegTfHWGHD+z9DI3UWPcCB3WYrBWC5T13dkxY2UoYSPzF8S9Rs7Yfrwsl/52f4MA44RO7
Tuw7uD+kh8Z6cr+SZfdPGSIJ9zZch9uUp6fpJ3oU9s2tTUzGKQz0rrjSUHfeQjyemNmbnSBnPvI9
MaLlbffnlDk5heJYLMAbfLiZZR7vtdFgdAaFMtw//NKFdZVQrl9glbTwvsZ6li4Z5xromkYetNyx
1tkyuJNvQTaSqyfLbC9940mVAqkKdx3AlnG2yQm/DdWQBTChK4fB4zotJRoyfqCcWskVTE1lbHrg
HXNdYVChxjzgiOXhWQ0/PtMBRHPvMvNWz7FobFGu+9BfbVqqg/5ORKr5IcNbhzztA99sVxXzDziV
VSH4pI3Kg3zODZCMaWDY1cfqVpVSuf9kKnuFnLsWOaZn4Ludd662D8nL+rqZDRuoRWw4n3qwOfMK
2S4jTdlhuMmZPajp8KYhT+QiyQ+7Ha//r4jUZ3h9bfSLhVVshW4yKzLLLhp3DBuGiEYwaOXrrZVK
Sd72H7oGV3DUSh1WNkll+Tz7FEBcoPNE38zXO3emZgKLOUA0cpi6O9HPbNChiAmnTQ36kLVW1+zy
titWkSLjpLxuOCunxCiLBgGiXCdHuCPkB4DfT/T0IXLwdFMrn9nWK8aZDQ910Gmrh7kUnw5Sr0jk
Cn41R5M8olLSUDmkbXVXSVpOMQn3XW/Fu/HKU0oFNIs1lCccibKMVt7IVD+tUrggRm8CGBew3lgV
NQqM5FlUlx2VBkpaBNZyxWmb/Qshf+5Szh/0wdYzsbLK0LXm3LH/WaJOp9RndpGjkLpIK3WC8LPt
jc7U3G12CMvdZ0Yp6yF1X2nMO4O5ISVBRLNEbwfY4tatsFO4V/IOWbwmUj1EceJdaodrV3586+ee
tOwfqdX42y/amULMdNFTb6uHqSAAGpplg6K5UHfeNYvdRpUHwyhz3Unrfb0lV5KqRMf6zvDfGbQl
q3aPkFNG0t9yiEwJBk2mn3nQrghnlcPM2hcfc5rB85B8/hleMZW6tZFJ+FOMLuJbhz6MXzUvv9rc
YbGUkn2KPKW5AOGk7m8Lp6FqNrfQ4yqexq+ywkqqBFKLnJM3V4dvn58GKK1PjF6fePS0sYt+gQgh
f8MEbIQnS18TjqF5CFXCm6a2lGvGTL1nrrM8Un2XJeMq6AiV42N8ozHT7uBFd9OpE7+/dVg4NgpE
eliLOKOelE87uYPqLAjdch4p2d3koV+fnBwJ8jVY7tihBHTOoGUDE1jk5Lz2kXTrLz1h7hcXzDk0
2ZA+Tjxqfmt2Z8effoIJ3nzIxhtCiWnyACgX710AcZP7DTAvsMmgLah+Ac2yeaolQVvhRrkhLLZL
jHfGhPQYIK6c7sFwoYXVVLUBq1xUitg9objkeWVynGNZmyMh50z2T4MeapIS8jcMFdOxxXylgHob
01AiBWzh99DcMaZpo3sMmQZ0oZ1xnJ0HhtDlc8Q5yIXfmKUtrl74szX2wAC6fcu6MVdgkrm76ZI0
S50UKgJ84grGYpJc/abAWt25o8uZtWdWW0DZj3rcpc/rouPWGHMC9+mPqAUu219GjptpypwMtKlF
K8U92G0usl7dgIs+NfJjh1kEqF2/0/VZVTkJh5bnXqfylqwqgJ90dGXopQxJmu7GBrNgRAX5bVCF
ST9zHiwvf7fhIuTVtuzxNSo0wAy1Ybfn2KrXt8wQ6EbhD2YccnoO20X62xi7cr8LQvk7bO8hwPrk
u9M7xlGoEs8mBmCdV3EI9CMENl2hNuUxp24mp4mtPcMCnV546O1FZQ46OuocNzQ8klBqS+OVOvo7
QkTzIhN+0hz20HjsPFaHVtKYitOjKbMoar/oqE0pHXPzp552kV+PrxN4cmoj5CtMYssa8OuFyEVd
GtMbnZfktvNDzvYknTjsAy0Cu+HFa/sGhQTQmTEboAdrTbmdaWQJUkUbEi5ZVuev+Jvp2WfJCBV7
JBrpH3/OLWocUqdQR9DmmCHL5cV3bsxSu0wJgm079NOPmOWF7brmtTwvYnZlVrvxKeI9WK2yXqcn
CVjdyo+esmuYqybFkdgPkAcvsaBQN+j3o7q2nTERBmVGSA1V8Gpqqgf4Yfp8vD/VmXZR4B3hts7z
OfDMOhp79hTGe+5y0elExY8iPy7l0UXGx9elkW72JQVVIp9Dcitu1HtT3tP+9RuEgwhbDQeW5GwJ
hK0/e97vndrJOXfn9o8nW+0aUSTRE/5/m41SMX/t0RWJL3qXWni2Cc6D1aRcNlFlhk1Hw1Tj+nub
adRY3MdgPn6BeiTKddBK3he1NuKuZkByxDIezT4RmIxGPRPQWrLAhzgFpWpv2VV0iLOtsYEHQilT
2wuBqLwn2lurNO8hrJTWJ9pB+2/K1yQouDE0h4Ik8nCM7eHHLORL73mpxqmSsYH/hdkQW6Nvs2io
R9oFC978BQZ9kgQZfhsdBsQ5tyfNbnx0lHHILgEOXa/EbBWPJ36c3gCCAXbYezrruImx9gmN6gm6
u+diSIYoRQ5HeqkMX/MUAMTUvRc+lcWVqGdbM+t/eZRvw9ro7e2AdMF4PHFzMCOCFVsEAemadVk1
4Sl8u+bKoXcGrIqkzp7iXftI0hNmz9fshmTZeSeZxy7AxYcR2zS0ltnLn5MM40g5bzextI7szYQx
bsCLE22WBQA7DQ6kkeGs+pP5RxI+/1WbGh/UmmnPxmirU2CMnbUtfsHViVr9VHrLAyPg/tsZDAxt
blgv9YGPb+8mW6B9azOZoQ5+2zNFwlqjwiPpWW3EzPqrUVHXIf41iRRy+xGTvUogaYYaQxFknjGs
i8S2cL3RBXbqa+Wv6ucrj/EoV6FlcgpWonwUnLYKnBy0jqP5xFb6B9eHXvCe8YY7y/728Q/8amTc
7D+b62wmCCB7jXAiIbmtWnWPZzs0c+XjYsyCZ4VsxGZyDHO3E7nLvx8KEyOQx9LerrTukwfrkG/f
cWOpKv6KxYUyMoH1vecl/DfxQNvxU+4MQxXsAoYQMW1DR00gFXhhkiaDgPocLY9ipdGS+MrX2cCk
FrM5Jo9hmExQGmLNBDa5FMW+rKVfiUMoYcKZ3hOciCyXlOxW89gmif0oFB0DVrAoPGlmBDSHoaXb
xDUG4ysvYot4nv6nE4bEaFEMsrtMgKEp/T6FLgN4mVOpnkAcHy5EIj8/42DIIIGhk/8vo/I2vN42
+268U3hHMW8qyIQCvcTHAHnSLZxbRGuiUtJ+UEx3AJhU+ifejohcoc0w+Ul/bxEUbzww7JUSlFZH
h4yYYfWWLgrKS91EdscTJREjpx0BxvbZExMufTyD8Sc/8qDA6pUiC3ydX6PW+MdwpXzOmq1SxbK2
VooD50foh96PwVRN1V9Bu6x9aLqI+f4Dn+ylvAc9+uPYR7dPlN9z/nhu36YQeg+L6hMk9H7dXMZ+
kyVf9JzRLBmm6rHZwFOkGmQQ6hF8G+b1M4ChWzHSwYc89CttiFOjo+lzqu/NLqSadA+xhh9+zj9q
vv1LCCon5QORzJ6+EIc3TMeXvCwEvjsjjetp8E/CLaKIF37j/rxs9639Rf7eW8W8cwYeWQ8Ohy8z
BtT2UMRKz0YxVArQ78QExhmNc8WdHmXmM0JNWezGS/sob7xU3PMZ6WlfJKLg7VGC41o07eHQ9bwN
3xEqwB16AG2AWMISinfUSgp4HJjsgs+3UHFefzUSsbp1sczqYEeW1NQ9fZCviE85z2Ejr+DBqabU
G5Nv6zFhBM1sJlX57pVyJsUQv4mOpQpP1CaDlD9KN78/qp0iUDsbo5ItKtf1BbJzzN1gYXKLXCUs
6SNX0Y3PO2jIj+B6SaVVyn4wIwWU26m+yLebAl5O1sakWe0khxT7/S+HrIUPfgFxUatS6/Wo59bq
zWrrB9DSZsjLc/iS2n7UARcKDkS+aisQ7yRe4q7JBBQaZ/9iPYh9uw+F4r6QMJD/bjnbcZ6V3rFA
btejv+dVp/5HwliZAu2b6gG7FF/5/RkezfUiQFBNZKu45ytLnavj4GvMnLfspmYhJxle/4ycOQXs
y1DaWJlRAYV2zPdvX/asqexIjz/t/bHyjl6BX7nIhxWq4roGNyRqMj6yxFwo7RPhBm50caKB2i/s
DwNCI2R6cIzdO/+/qrx+GLux1QxQgKDj9713aLS3v7XAFklZ+zk3JBy2D3dICUmDLb+4ZqcBxTFL
UHZB+OJBPCRBbz0rvkNejEL7ldJCcxuxQv7EoKyo9811bNIRUVV6nbqgYEAcPs5q/4xAZ3haXgI9
FqtNVleCnQmjDH2OV+CPcL5Mgaj4JqugH2H+UvsubXYf1MOvhKmeecZ/s3YyjQQtN939xx3Qlhhm
LIDSfGNAAtqkCmkjA9HvRJH8xiHtgnakCQPX1FDCdtI8wO4DX3ppcffsQg4XCJqNh4EJZ34AlWPb
VhhTZgaL0KV5eqcm9Y4kY8uwbfqzPyq/2N+QrXUpCjeve8a83hQgQRzMRhelNO3mrLr/zUE/NqVE
PlOA85jyrwOphGLxIic3iVl9QqJH910xyev7RBfxsUtYITH2z/fUP6ZrhWU7Qsno2Cu6oDj1bSdE
ZsUsPFT6+/YxqbeZ0gSyyK9x8wsRKGPXxGZvKyqf8IVMJL2JExB9n2x6I6ALV3Wc4mUBTfmbSrN7
TzLfzmZOBtTPlZ/t57v6VTuU4JkkNUMgORCcsup0EOVbUk+h8Mhobp5+KYBiQ9lsdGCIA9oxT9eF
r3k3a2Bb2/2NgV5xM2Kxh7l0YY75xRgLM+Uc9KHWI5ECdGyOmKKpqWkgc0wLiP3Pg0Kb+w9z28ro
drRfk+VaSlQ5jc2Pd6cpu5qlSfB/XVHt9LsOyGYLHKdB9jnrjLnRU9975RdfPTMjC05KNXG7p29A
NsDFy5nmNj9KtuLLcvPa80XSjigcigW7iMFgQ86/psIaqfK4vk+SolBZCXcXgUdS7pnacsbYA9EX
IdUOI+uXhIL4pK0mxLPzl1DAw7D5Gfr14Ryo0s27VevsKcSgAcbayCba/0KIPRX2wQ3T5mfla39a
XhCLw1rOHtRCr+y/Ei8tBEzNTC3az4whDu1myjYoHZ9UG2MCL8y2FTlZ+5iYfuYjcRPMzXBeBkoR
vOXypozvkUGN28aa+0fr9d4P6LPj2UY8cF0A4L9hjrN68C8WNWX6Ju8MJPthpBsgJrZiOnZyDxDE
gc8QOLRc33DfJIcOkvcNwV2TxtEtyyC5fPVpmHfs595pgtKKR8GZawEPVi4sBJ3yzTYsXYJqIyal
9AZBYXSY1YvADQLPiukthc5haQcyzvpfzXnq1baPvm6Zx7X2JAZovA/UCrafqxYg5csAcnoknWQL
cYMbMxRPYDBiW+oUyrdnmHDF3XFFIjZKZnFaRaJlHhyBMeZqmXxnnazk3HO7XUY8ABbtOUTcTYMU
pcpJ2Qh/C1dPHysKh2lVfzoQnSCm3iQXk03VU9uLqeiFayqGJa2uH/BwFEkJLgl/h23HFA1959CH
JH8/YRgJ7alcgjKaPVIpo+kipdVijP4QbUs70iOYv4SXdBjP8uZFVJM47HghWurqmHbRlF+h2id5
7bGcZUxt5sLXDSkD8iZgu52//waWE1H2SdjTjPviqFaCt5SPoKftiTlJSw4gH/rr2hVaWLtH53DE
kFjWv1HdlmbMdW7Jn8BqNkE9TboIqjcx4nxcweeRo3+Op6rCvXn/Twruv4fCtqJEolvwuE305jEn
2C8EdwYzKxtvr5ccev3QedKxbniPkhnZELBu4Sc8KXwU/Xq2dJG10OgSRgJI3gFg0ZZBF2DKaSFx
yaEG6zZ/PZJzfWAibUXhGP2oh9ORAn2s7pRxHKBECEVFCOtnrNPbLpY7iMubIoj0yJMQifGVOiou
fZT7SxOFwJpp6Ewoh5Wf/s8jcYHOwTbjBMLeH87XCGuUNefWDAVA7AYjtZpbdy6rj5O0abt6CN1b
bfADpTSqeLdZhbAyLUACUXBBzn7SB1JHOHi5bxQc1ySDl3irkwbJ0A1XXw+X4Xr7tLXt3LCJA33q
6ig+mTBsQrqnhmJuzFLuRuPG+hChjMH8ZLwlIicEdhuNANHn41azjQFWC/BtY7yAZOvIW3H+sIJ3
k0gM21fp/1nF8bPYwAB18DuJ68On8Nw3aIOkMfR+ofsAs2xWjfrR1pB+YJ3KTq6SmWayuDUb8irG
qpb3NXNpD+jKzlW6TiJwwt249+2fjqUoVH36UfhjZRFOdxIzZlgxRwiF9YUux623K1m/ShR26SKl
UA8ly8ckpoBG4JwBrkCD9dQmY8bBy57FvXTfB/mA/jh1HK8xFFhWlnsEOTYxkefrbbAflUUaGXUd
TOLxgO94d/AbD7sgudxBSfwduhbkKPqJVWtdzT3z0OEjmao4fHjZIwrizQidxlbWpV8uODEidLrV
i3JkGi8s44/7glNMUtXatEn5VkNlRWI5ZC/PbIi1j4AEwkCnfE0YBGp5DpKT3kneAS78I03wzWgo
TWp4X/IQzfVdzLBYZo7yi0T3Z0UsCEz+rfpVQvzJs01QzwjDTHN1Yp0Ow6fmiWimzXGdDLW8H0Uz
ehbTTur9xfnBEto/ewwqax5v0ZPEtOTZ1oLbpmXmYqMx+r8Tw3F90W3RIlkIPs/a8wrRcfPkrGrA
5+ml2NLY7LukN6NTf/HzJtC8nUF3UzhMprj+BvMvQ+Sr7oTxx3J/y+nNRy90aUwcvp8IIJYNxJqK
tGnMAJglTVv2sRubLZ3iFaCB4Qmd+bZq2WQpkEN6bwdN+KVxwQdCaIyQVjXXcIGBR/2Mu3Z8eHSc
Al0KaDj3WTmC5ViVNVKk5XgS7MTR8nwk96ielFHf14IetqYVMw8UmEqQ9fj5KI3nCtZn5VWiuHCy
U86fh3ywspQ5lvyUcy6HcuWiR0by9NB8hpZDbDN55cQPeb2W+LD+AgKOKePrXf6RmhulAyNakUDc
jqSWaeSH0o2JqZLU06ox3WQD8dolPiynN67AuHTwUaSV+w46oo5vb/BeWiSWwzVxk2UPg0qvH7zg
miI5j3xcU5t4PT9nz5upF8KDUccOsdJyN6HHsFNODms6WdRANIx9EMlVGBFGqXsZXJ09w78xtQ7O
akHgHjuPH9FIS28V/as+Pt7r+nYVz8+uU5aDjDJ3fpRlLb3yhAZOH6o4r1zwGP5QlasbvshSH/ja
hq9xGmsiZy1ris26txAB5FKQvZvA/iV11FfudDmM9G2z6NKEVxypZ4HbZg58LLu9VU6N/+sEeCO3
WqtdtWVaLDtrVH1q4gdLN+waZla3MlquqF7lNvgS2eJ5PrbyYCLtXPfVNpo2h/R0zAu6G9r8/Has
7pgxiu8dvlI7kbXIwqsS/n01XGyEfoTv6CRhtGwoL35lH59n9J5G4FTa0HM1hreywA1SCJwAdfi6
9ZvZpxOKD8Bc/U2432RSRdvJ1GStlzqRyiSzYJ6wXcNitxCs5jJYzoTjElOuTY9Sm6mYmepnI3O0
9lM+ZSvqh0EkjRAW6gf8M80VHa8xvlGA0DfH7NC3FmAlV/iRUGSR0PMJ84IF04aTihM7fT9tCVtW
LUn+niQqzda8RMIwcuWrwW8uzuzBZnPDjgVjyQhCotMFQLNIEC8lsJzmAbAYpI2cezDRhZPJByN5
xFbms4jDmdXVo7QEztiinVJrVgJaYunLAmTKP1t4C2L5yzzmdQ7dphBlCUdtKf0tlK+uQgKfOgYA
HCX+U71INrTZXoBCvGOT3bQL2lgDjH5xXPcn4bKRVA2z4/SKp6ZCXgDcvZQB+FiRZHIFLzmgi12G
qCGXoYcsK4/NWVrvOWGuLwIXpwkjiLj17BE/SZXK6YO9P1CKBYN8u/Bnb3+1FNoyiLDKK/CKQl/8
wlr8jUIcH9YoIO79CSREkhqZvVmVk3QvGdkA27ox1Nq+U3A0i1u/FJuJlyhaiPLeHWZSEquTs/rI
bMdoLaJ2hpIyMPEi/cuYKmYgVNwR7miS0J7TPqlhZnK0j017ZeWJ2z8FSq9zPPW2VjT9Lq8xMW2M
as4mPgf0aI+d1Hc5/8l2hjMNNIN89uTCuzFyOFKpfUrMIBDT+Hwzs30ooJ7+/ypQwVgzlNMFJSoK
gSXpBqagRhaQxpPU71zLMAu12zBNEfa9hZSyeNBk2TJsI+iU8fD1CKVU1+4j1l4YXiKyGXikRTqd
URqZUYuDMakUnb5w+4QnKyX5TP+GX1bLedFamvwAcICWw3OASwq7rxXBD0a77RSmV64zRK/Fqc44
0C+Tpu1ouvC0Abag7ijMxtmUUQYbjJkmw1gg75445yVgDLn1mOY8AocKYXGP6yQQF5K+V6aHYoy3
kcfCDHoM3rhHZUs6nUSzx6Ijr/1yBydcXqu2N5o7k7llEO6e1AZ6V0hMnYMGRV4OuCP89ZxH7Fob
9WQu+rPTDhs9Zu67PCOI6FpTh1WIqc9n0xIheHsSIj2qjDS16WEDObDgrPIfjqrkIgiFIg8ds1X9
fcth2ElvjslZBQNn16Sjr2yVR8M0nq2uaDigjDflJXYUXpsE2jiEJemHPb21fj8P5CfImlRJjroy
3OYY75VzsxeJ8dStRgqZdXNflaY9UAGk2OAK9OpmXhfajPfwkShBKBT2naFaBobooVVH9Nafk9RW
g3ouT8VCNMxcHcSfwXNz20IMz5vXZ+sDVN/fwZreKnm45PG5P8+azLJNJIjhFnAqTHIRgE5p4ZsJ
Sno65Eb1jOrqdLj6VGwM4/hOc7XhwG7XGBdOx0WKIcgpGbiRBfdZMaVN+fl6KN3PusX1mcC/RR8i
B5KQUHaDwQ5gPdY2e0uyLoU2w5CyLjvks2LpH2vdGGuhk5XgR3WRyaSefLSa++ljxWxuxCz1yceG
aKqGlh4/bB8Suwk+n97Z2TP/Rp/I3DcxYdkv89DUeE+69Gwl1AxbAZDHWkS41hJw6fhBXoj2KMor
pEdvZy4ixZYSld63pTqmmuKIv7sLzod6uleirBPuX/xF4nEpRrV6Q3fYdTDWnBeJszj97HafbGXs
xl9gRvTtjJt09H73eBqeQD5UoCg2bEYaGcAXfGM0y3PwugubmwXMxFUKPkfU35axdR+Li+UQCa70
E8N2AFrDDV92tRFO5Y6ere8wgc0bEEY2VQ1xnzWomQ03wZ+0VG8DQIh3TawKLFfD+41j5MXiIj5z
GKY9O23uCKu7k6G4fZiabvG3GcSRFJSu9sdFSKZ27cVr/fj/YrYcJhhKkA2iX5cLaQCDkcDxjxpH
iwkwkGLX+d9Cqx77ATPkidDSSXxkbZmJgd27Yz8/oIHhrVOooMiDcxvTzUpbIM9fRcws4NUreYP+
WihPb70ukL0eN9GrYUvvKi51iju/4zqKkgvMoIAWLhzwbhdNQlea/O+M/aRgvW7kkJpRSi3z+lNa
mCq62ftVZPwh3CD0xMelwmplOmc6TlrbR6QlQQcMr2K8usaoRlvOG7/SsQGlR1WeA0FpXMuw4Qmw
dazvThv0n9JOQaJ71G5FknZ21ix+YRtjujhPZejmF40QBuA+uGLS/2TFXVgTXEtQ1cWUCqfI2xWr
caXnY8VncgmbM/loZhB1EbZwAajGuVLW1zXvCb6T2fcA0vXhZl/YnfMDRMpYxBlj/s+fXb3IWAQg
3So8TNdYWK95r9BNuuG2DNji/ZGPK2mCgFIh/hPcfHJOIuyCnXjEDI/ym7Y+7YJ2dK50IwUvS9m7
lOcLwRP8dMQN4XLldPWTCA4gkR0ZtRBEj30YozKFJuvJ9pNQcGYex8b+rTcNP8Mu/XxYPRIwKJo2
WXDHiX5pFgqjmdtwg9xblQu8HuOC/1ooVqles0c15uAuNd0V0XcoRg7Mz1SNZ6YB1QjE01tyyiQn
ka9GRzs5EwopVgRBSTYlU5G8HpkmatuETCTAUPhhOlEPlCavisDQkDu9j3oIvYuvKwax8e0ThIrk
N1z8WkkI5CM3r6hDux6wPpH5A23ONP8RXMiQT4NG3l1yOLsCCHC6oi9NZNjUvv3LHuLBoLPlMbBD
k3b58WXzFhIiDtbMIdyTdGG9rmCAOWNpVV/hkraEngtZeGjHKV7uXJyih9B8GOrKFobu65sqd9dc
5upqNDxxJRXxynTG4xQjBzL9OGemhnj8VufEn5hoSvBGMBOw5GHQCFGb2xww2JnmRV+2Jz6u0Din
mpMxLRznzrVzvKvAlUPXrthikrf6g8/yHGiXVllDynZ7udjSU1/gdD6wklzfY6Pi+c3HCXjnWbbh
eraupDwrFT9syWGiEGrDz5PHpR4WiebJhYS76v9omIuNOe3Z7ukC3csun++ERx7MaVq4we3ayGLg
GsVSUzMU/uajDCkR013SNuy71nLtqxz1vkUriu4u5G5VgxcSZJ5v9ps9leGQtXql1vETcyCyXYyQ
Pan4g3zNC2CrxizzgxgY31JLf6Y2VNV7QxUDK3+m/DbiXJBy2haaIzxOn4DtezaKBfTyiZ8uCR4d
BvTIPY2hJJqCMWur/t4gIy3pd24hIKpTrccU8zauCe3nCafIbbCUJpI97Qwhl4NvQaEIqgzZ12aI
nY3yYHWzoKG6ueT9ck9EdblnAupaEbxw8a/19IaX7W7aSbiNvRT0SIjeiaFvWafTxuP8L5bSnI3V
6IavolfbKWZS6/8G57PYhilKxYK/3kWG+e3eFn10F163ZgUsDSHHxkrY4vNin+5ChCy+aW1+EkP6
krDQhqwXjzzDdO19oVpaO7HSOa3EPm2OSaZcjGG0txVM6KZ3uGxSWBSHcByPgBKIM8CpXhJwQle2
Qaxuavpv4QqOKXjGlux3moiIA/1T9rFt98nvfd2oiHAh2ASczDs6+CztO5L6McSwG6/6fOpIIRO/
JeRS1bpLSdYb8+XjR6uXpmfrkPNzdTuNxMbR26Wu0K63Tvrnl1s1oHRSq6DLRAuIlAyc6Sv2f/Nu
8DG+00CruHUiZjKGtukxEFnCsB4qZUy4NhpuEFqFczRRmwn21Ci4q9X66SkC7bWds6h6XFDk13tf
eObuqMNeDitxUw9EsG7Fw33pzW0xLcp8q7t4ppDtTm+jxRirAc2VTfZA3d999zICHp12Bwdw9XtD
8G30mavXGsUu+nSbJ27WU4HxFUGBf3MLLkFRM0v8rnq/OnNOPkweaRVeNgSluDqLhvtyBoeg24H4
V9rClDVG1saBBB27xvRJAUJ2E+z/n8hwRXylVOMp76D6JAQkaPd1x5jFyv486MF4iZlZxkTpvsXe
+3LoA4t/5VRpRC3+6dUmEk7Esg9W76PzWUcn7QG68FBU5uZB7P92Zux4Zo0BMtDH21yjUnd80fSg
oxsY7CE8na2Ww7AIuGoatW6//i7fm+yNjcH06dWhjACWk95/8++gQNyRp88k+lhb6hvFYOUF+Cp/
sdJN9JRVZfgVsqvAQzjUN1+QJUb0f1E5LGGVl2sbVnGd1zEhR1Oo16LCdGu3dcP8rJvmeOP0F0Lk
K9a0vY+FKsTqTTtJSoTq0AjP6D/iBtV2xM9+s28foi47CBxT+AwMGMZ3TjRZ+ThZbJsZ9OHtYEr+
8M4Ku5OQCTSPCTV3tLtvqjRawvBI2mvYkmt9Q04KlO22DDw/QCvGcxatpdyNE9r/Yi1AptW8HyFn
u50Pvinl+SycFudBqhgxro3BsNCRO63hEUgCr0ApGc7yUIVqI4zUj+55plNM5x6buvI/2T7GsAC8
wA0UFExX9bWLPEikRZnrYcj/kZqWHfWwWHBerVedQlR1NXPIlCQecEmVkDNDX90O6+dVN5G1hVC1
7Nr1YewnQlhjbec5xq9gQIbKaRjWFWUJBqmlL3vikPzV2U+e7vZ3ThnhZKrutiT/yRbe425Dkn7Z
n34RFdafqXyzO/apn5khI8vIsK6V7Ri5u9daK2pntJ+FVhL0yGwFPeLfKqloXaolIzXe4sUlNaoT
Qe3Kwyht4/TY+bnjXl//ldWYsIid6rLY0CNJK7Sq8PKJy93qlNGaSy/Weqdgx5eAopT/xrAKCw1j
i5otD7ZkBPvubQOt+l+DO2HJQDY0nHYiC48+Iy7pNW+gyAiKQI2QlCzXrFzYAJLsnm9KuojzSWBw
uAZ3qUC+fmSn2ryUATl+D9t88g0tV2aPBzURwX0gY1qZh2geybjEwvgCU9HwQrSUaGPFfvw8mTNP
hEvJshYpf9+KETruMee9+Q+2JyQ4Fogc+xr0S3J7korF5jN0BSAnVO3svrYcAI04yS4rC0jGflf5
ab1nYmVLtPSlNEq6TKALLLI1NxcTxObKjTma2Ob6IB+9Z5mTFmWmCnb3V2fcq+4YNlzXVYzGmI+Y
L9iGirPMym4eVzvlNRfCl7fuvxJqrWG/wk75oPc6ldNNCI49spxw6bkqdm4aLB/ophd5bkrX3ykY
YISl/LEtstwI9dFrCM3+Q6JQSfb8ynCS5C+0e//9KM7KgC7h6EOffVRfh0tFvgmZyimT+VH13FWk
nQ8abs5owXyHASPfsG63WVHvMlfpy6YBRTXiwLpqJLg3tFv1QLnA4t1uxs3cS18NdhwTYnjlD0Mv
YjLpOGDI9EevBkGkwHjt8s/xg/0LpvNN0CHExp6WpACEn+TYbyKluEVk3QrQ/WnyZkAM8VswErGG
JXiGU0bDgmSUgH2zZHTBHO/54L4AIKAuq5IklKDLmQqwGF0X2cUr9AORcGTw1nKhIi/c6lYUXPiD
TxC2Mxk/NWoXIsiaFYBhIjiclaozsNWPtG1F6FQMTO1UwUBb+JjbS5KGkvHoxpq7jAT3ZlpMwR6Y
U7Uho17pmdC6WQzToWAhB3qTo039quJ11rsQjPf3VFY0VGYXZ/fRul/Do7t/9yf/ssBL8kYhh76N
DXtI6+ECnFeIJ92Aj3Me7Gw6dFNfpXFmU9LmnRHdTpqA80hsRaUQzhPMfGzRbtQ3JOKzrcjPKBNC
0mklAHIPOzNOBevVTKWTvty8o4OG5P1KmZqGIe9C3IpseHnFNR+l6X2GPOoGiFxJOF0tXCX5kRiO
Hq2rjyoQs+ywK5CefSbsIV5bzP+/PnshIKbKk3+dUa1xOgEO9++BJTSuWvA4qvZSN4IaQaCrlvrK
HJU13VYW8Exj7IrlTNHYeNcZvDkBY+uER/EQjT0aq010RjqyjDmc7eHFJ6addJjl1SMXmKpZBIuP
wrL1LlWJmB+A+qJ/qDK0Jx9uQ2uUAxrvkNRJ27rLm0U9eWN+u+kSCqbh+I8xrlmB+cZ4y2SWf07I
W8MbbTWC+3QxAeHYCb8Hd3fwPdB+4NJ/0sitAPVjbdWjOp7nzcAfYdGeEJ+5T51cYVVDewX+mHHM
VvaVO/cE8+Kr1kZuLJmwsRKpThGfrrrFCwK4CuPh80T23wBWXxR256VA4MDpiNRMKSkVOAyQMCu7
8lFxKi7/PnZH0OQ0XxM6tlao58fgx8BB1l5gfYkZQuS08OhZWYnWYOY/t6HQXmZkeJbf8XioszIT
f+6FFfLIJryoxiBM5EJIm90cXZDIuBQUISfopW0ea4gfjXzEIP9NNZFRAWAGX8HFzj5LhC1g9RRs
Epp3fTVFYBcIGmbVuksUsqiHOkfRjA/ov7B8ntUCtpGtxjc3upLsedcQHeKBn7+9a5ZRU8LEB5yZ
MrCOLExP4r2qar+N9UFcfnBKkn1fnlE2xYUUlSxi2Kg31Ar4M8WRdokAYtoqos1tjemXa3ZXJ+Zy
DZIvQ75uXOyYEnb2HSIcb7ihwFG/K6fVG9em4igjk46ugbduuhRidirEBHDNxYvT3mcEH/Vr+JDu
w00i3Z9iYO7LFXZ7Qtl+Mgu2LzPWf6I+wn1jFIBvA5eJn9TV8n9feHoZXpKe0ZcGXAxaOAUKvmsO
BwQsiQ9lLA0lCA+FuOXi1JLCFkPUZyWwwdaSI7smmbGoQwxX/YdFfMOZFwM6FvXeHpq0Jb7NanBN
346Uly4p7w9HLYaj4iQZf+WysPcBU1o+dkUTZsXsqFknMwdY+oO8VlPBnB/8v1Qrs8buPmaGSCT1
kyBwewVXa9bOz5lmOsAiC209vsnlXwF0zu2nLA07KbBdoUfpMLZ/iJ+30ZPjbUVSTdoS6wCQaY4l
cowBgfkOWWh0HOtjDHLsZSSXrrJsMtfJWXzHDxBIuM6NLUqM9JuLfkeLKySx4FuXwF7TcmF3NGCM
fnp2liXU/OKCoz9NfHAy+tXIR79l32peCa/7PJWui6T2ZMlsinC8UwXxzv8q2rCMOJl98tjywRKE
95o2Ibb9eSKULJ3kz0Q6DJIl6vrDjK9LtwGNj/aQD4wCAl2oAYjIM1uR5PT9vm2hcvwGiXT1Wr/T
+8N1E5Ufz1NZt0/k8alBRYx+7XW4OrNG4ro9+W2gHAAs/iKf9a3GKl7NcNCYTQgM5UIU0SoBt2E2
Taz19rCdYrjpAYSccW/rSHMPwA02fUd4Oewn4LnJYQ4+sZj7VSmvSQIVF5FA5TxDStxMbQ7D0Npw
NNCZ6H56QFLm8KeGeeMSAurKozrTfgljMdUP+3Ci7FNzzSI7fVjKwVKugQnBPTwiHWf77OXlBgFF
8mv6k7iFcIG4yUBvlcVC29258HR8NcAEmVUaYkQYBhck/yiwGWhcZaDdw71v7vTTBE4ekhkE5wnq
YcmkBkwpHTpp/HOgQGQm8oFqq3w7qf5mIXoRK/OAFycApFwtx9pZqWtbDX2CR6LHvhLWE1TJfqqB
x6x6yWIahzN5hp48rhds1iHZ+n7+SrK/Gf1TbiWxjJqZ7yvuzzZdn/Dsrih2NMa+yV5tLJGY2xOn
/Po/GdFHFfaClAIWXpOwNHo3ManCZl+EYJHoe0hYXMB8GoPQ7NmSAr4iZl17YoDyaWkLxPp1m0WE
YMQoqvh37ljWrUrMposavEkJtIe5K/1Ql+F+DlhFnnWLCDToVlWzB1IuDE0pKJkd9wAYo2FSlTvo
UeEG82GKz2OM/iy+p8PmXlw9uvab3x+ArdOJue+O1dtSvZDYpOsCw9vYyZJ9FwMn85Yx9gSOOHzX
unEOxhpKW7UAWGvPTyaJl9M5FjRNcHBkI4Azw2CIuEC0lRtUf2o2yD0fsScHKzW4Rx4g5PAKX6Gp
EhJegB+b3GfxcSVsZtm+GO3H4iioeik/Edr1W+cYNuXtLHL32T6wY55kdb0y5qYnA6Slvy5XMZJ/
g7bWcV9oWCj3VumKOcfNrWvWg3CPHjeA4SwuRnhJH+dhQg5Xq894+2Abu+0nGWTKf3pO+UR5TFET
t+WTvXF/qBAAA9pRkPbRzSaXjS+xnIkuwH/EqsWDtkr/jrlxHdFZvSPMGskRANEPOawb1bqsj6d4
8IaU7zvqv2POLjzrWDFN0GSOAK2NurYVClK7IXBjftsDilsaeodlqnCLsgKEUu6P6QZMURvjbvda
YXNSanC48/eAP96zYDwhWehY5p+m0utBVarQ9ME1S+W0mDxgvckVBNg5MZCz2fPdZiEjk3bNTIKI
OYt8nJpTIDwGje7rwyQF3gkGSK8guPJzzl7LsJns8/yM5RqQa8rVYyQ9SBgUEQfzujNm0i53EaNU
WWCoKc/WgcfxVD4eU6hO8l6S0oTh7r6YZNObykboZwYOaxJPVKIb0g6uQCHx3e3TWmwIBMFb1qNE
BZKo9U9AhECz2C1qx2ZG1QniSRn2+uvY1KLToilmI5EuMYhEPWNgYSSqlfwbBNxBMki9RnWkLVCC
nqMitTa1rhWvqkmN1vQuYavwF9hFoGrdEqyYZgoqgnye4tSbO2+CrieONVD+ePXkTUhue6DBAR07
Vd87iX9+iRkeje7nKQm68ekp5jpoiw2tHxZ1tWPCKTfOHRYO3Bd1LQsj4UJWKljK/L0Bhnd3YQnH
PUOUKT8Kg1p+orIuGtycm8nv3GWeFqh+OmSmLdN+/+QyrLKG055B8UdNHVS4acaBq644mSe0Nxe+
ekfPzyglWlS3RQk5O1P8KjaSrIpGKzobuLzxc88tz82n9CAXQB0Hw478nwD5UXOl/ZsTSnL7Grah
xPncsfPGyXiqIQ4ifFUVfEaoGTxWOeJcK0TbkTDMNHZqNfku6DfDMjsyb29Oy/+IxU7fBq7GMG7z
/eOmLaY9axKZ/BXhZMRUydsw+prdRaxQ9SHVpgIoBuEhzX64A+oDlFoZs/at4x/2eOMA0Q3RmxIc
B0GKDCe5G37ZvaNdopK2nFg11LonKB8n0CogP3a6ElW+AclW3c+3emw/NSs4KZj+Rq8QRY/fOc1t
FDcLVMteL9mc9J9l3So/swCYvnIeTWcbLh9IBBq7X1YrhmHiu0dSjqaVTnrrPdodcBgbDUmjWQVe
MYbko2c9d66YvHdp5nzQK6COPa996DZbc94x3gaWuzx8MTAewpj67adUzNyKEJeTFbNSK+uGveuH
WUASPDJdC1EqRNL9hJpgvCBiKxHIulOiGSIg3QAL3yug/c8noRkudsqRPDtGLAIqE4Ga3/ylyXb6
qel68+GaQHn1Qqy7VzVNAOapRQ7SnuYGPwYdp/Ns2vhnd1MPgJJgZCtrppRWn1qCIQo5rG3Pazoe
FinhQHMxaUUwdIHM3FPyHDudOALhLYm3QuvZRS5y/EGr1GdYVAy1GsBJ2+RtISPD3YBQPXbHSjNp
uD5OSmbjdBM3gLI4FQaTIPKza++1dxH/e5qTeieibqMPsT+0DRwHcv7sURIZ22BHLfoc0D5+e9VF
MedI4aEURX/7OhENXi/hGlWfsqEYgt4CiYsJtSuZKLuL60vyeC4SVovPGLyIJKpb6UJGFdV9Tk2J
gdGFUnvamd3+daQe13Po/dZFjAEVEDeJJeErgcjpbqXExbY9DmODkmLh4Ct4BfmRpwEINvMGUo/m
cCxrNbyZso1P2ODn1VS6+sCC9DCybjcZcdELQCVFp2sAaJAAugMObuqeP9IGqMKHYNopH8QPULQJ
v/b0EDAjYDG/9z/Tg4pQqyeLAKcI55Gdm3H73f+/ke1pjd7BQnynAhx+2+igMw37CTkcxhTSCkDD
Gm2l/9SdwDgRHzuMEQ57PgpHLEYaGHBnrKdeKrNhp4UPvyLyRbkRHHWiV0A5RJj2bbXxwT1vTgyY
T9+bzmGIL7wsXbK3fNStoL/EgrlKUqXii+BSmRm/pcvjQS68s+/vR10e9ujs2pZEBAUcdgFp1Np6
3jqF9TfD/xyuG3W7pHcvVE7mVmmqBw+aJvFTHwzM3BchWTfiyyHLKWF0quMXVo0AHG5IZr8sIEYY
Uch++YW7b/NXnGBYt6+f8ckA1cLdC9McqffjRQeIapEgZpbUsqYB6QBhubWqD+hB7dtFHdo+1HFu
O3LXa2AtHuExIsAAVV6wckl2bfvm6wrNgFiTF4tgWgAbnVqYOiGgGUNp23wuouYO4hvsC6ip7/9a
7lRzrKHuqgSDhibzyWD57fsQnFZwb43XFcdTY0NDF3PaBAEsrHvOkIIlqVUwz5tThIc4AeW0BNmZ
UsijESxfis8PPC/onpIbUVTy/knA03HC8At0RgMSEdVWVSPbLxyLH7xndmiaMb6Pr09xSaLctHeU
oqbZB6kmiUV2Mo4E5ILz836Y4PoePhUI54qg4m8M2YO96Q9up/M9zRnFY8BwA0yRiW5i+xRejUOF
xKq+tHaM5jum8kWfbQqOCKPBRT9rZZx6f7lHAmMWKg2yplxLqnreNh8OSqBWoEjTSGXIiU1XiyAT
y394MLg9J+WtAH9ibJJYyzdmcwtfu10VhIULrjM1ZrwMpn729+nDloDry7TxWQolzrpTmyKkjU6q
TGfClA+I6Q2c1780ZMgXIvsS/bFIqesZcmNho9DQb7T3n/+048xN8LSVhpndfEf6Ie8YMx0doXyi
EPvo6am19Xk3HBIPZSQUpLJhJRkA2sStsvEbB2LARxjTvCQ+EcWBDX2AhugwQUtV9CGPNHO1EoCu
YL1IeJt3YScy22chVgYI/lotOeObandYg8GLmdsmLJ/fLkC7rQ4/dsGKUSLIiJeAEicIwWuiEbuV
zy6IvPiSAftZAIoUmDQZ1UWpRvIiACw9XqV0sCZF2pNr1usOAfavwy9YxnNQEAMGxQQoRsz4F4fY
+MyFLO9ty+kcUGZFVKbNnh9RUrPzv5hl4haq3byq6xaIShf8sHFL3YLXRIO/X4lQF2CCLpBQ7PkX
u3kSUNOG6OKFKsSkvtm9hHBfRUX37WxHpip7x1nhc8JzT3f4+6w8NL/osW9wjC7yGbULucbfqvIH
O/z6f1t9vQsRf/77WVCe9qIhwWgkr5vIHToxG64aQAm3uFsKewMrPDKYe7oHHzLAtf9vHXZkTkuW
hu5th4aDZXxWh/98qkwHjnWoyqJpffX8xqE9aW3Qq3VR9KjGtUdCe/kkQ2q2XQu1133Hwhboqx+q
8pEJ0++CwKrgcBP+lG4QfstSJ11GvAvItccXpf1X212TBa309vRmX2hWbxEk8MvSCr4UeeJL3DPQ
iGZg+HZ91TdqcBu6526ik+piEZHS71WHHU04LSeA37YWm3ZlrKnZHvphCrYwpIw9MAdm+JyhuqNr
yJDjaGEpPTVZJrqL+OulodH9lvMSpV/H0duwCykBRvZtO0g7w9Km6PrEBrY/K27NuzCe7mXnB1kn
1OfIUj/vKMERiK4S7eyjHfdVOPLEQsNL6lzYQYK++NZF53TbsKNe5RYZKTbyh24xlvgjyWdXtMP4
3c0/Yljx+qNRzHgI4BZ/vYfe2OISV+Q6e3rFOOyGolGTOeKBIudfSPqbM/z1nTyosnR7cHbmliYv
pcGXNaiau2VPKz6/K5AeWHu358OZ6hDiFY7LCiHn+HU31axIB+LGESuBwz14oTPAkr5w8ZR4KjFi
Gi+AzpdZrx79+Si1jVANgaRG+nmXXTw/e0nU7dO3uOULwLFcjJX/jZs9APXpl7M6qIqADdfX8owX
+1hNdlT01rEGE317iLwBbSvy63n8biyJiDwnnR4ykjGIIrZmW+8ouG2GV+7kHRc+0PFrfoW59QO2
xmtSyEuBKw+fTIXP4SNLTmtwMf+rOoVa4N/vPCBQPjRGk3F3CyAO6FDS2ThrSYE/+8h0JzIZANyz
VEGTT9sy9QJOPclF3djR0obm+urZXYpMeoq1XMQaWAJnj5L771OgJWjNVv8nQJGfZywUgViUlASs
+wnUWJ4KHbBE0XvWQ9gei6UwG/OCdwVJSpfjuVUEF5SeIfFVHxwu/LgyjprpJ9X3W25Ykp+v5YNZ
SvESRDK1X7Ji4j/XdRqG8jZYNQxFc4roN4j2vbbH3mjIpko3MfPpfeamiEBatN0+VPNbDkPcwhKV
SXqd+izcXA05bZd4rj8iYSIqGXZtMQf12QN7k9hAYiWexIzTPEqTICs/4XJZTIm76hlbYEZ3JjO4
0i3Iotk+S169hqwvRkaVgwyBpH2xDw5PW85M6f5stdrQXK7ROhGtucel1eGLy8aL0Y1iLeKpF8C4
kL9pnDpI4dnRccKOSjBxr4MkMdqRwzHBvLo59zLr5F3ggRLYWbbdfUnP4J2/qSw1WXp9YHdVPI/I
hWuL/bFAdjhVpM0b8LrpCyXozk+mgE3w6dgZWBI5KZJOGjFx7ZpSTuxs6/l0i2j7Gz4V6gFD/DOZ
NBdWk20juaUA+RHzLVpJk/F0akCKnBSAnC0KXUq47EbnUKpbtB60CBY8ja51poLbVUnPkqoF8tk/
VCjv2zm3P8/MThuaoky7wko9/ESteXmk34Mh0cfiStefZ25S9CLnh520rGsM8YBwGOjByLYMTH+C
MbsUWOD2XLLuqJNzu5TWSScUqUg/PYkHXCYFJllSf2v7vC41WPcw+1jre1okP4wwMeILzCJ4UCsz
RxRftplJVlzqk4sUnttjaWvK8VuFu7/QwAeFPM6H26ky87FMnSF39Kvwy2ZS7RVDuiU1/RR2IKCl
c3ld2RmbKl40aZLz/EREXYfD7xrJChAMAHDDa8uL5ujIkOwBkn4Ijg6loWfwFYtqHgNyslkLlo1N
TOEDlXrOXxGZzoGfZ2hd8t2znmX1QXWu1VEkNTwXq2ow69LfjTTnai0a7ddjG1+oOacjO1Mgji1F
DHTP1iMnYsdrvzKguww25R+YcX27/gK+ejmZon3lfD22UCsNfAfnRtIWeFfQds/AFFFUGuBTGQyu
zgKgjFuFXcbSbe/bg/fLeZGvc3IHP2vk05SQLBc4UI7M8sSU+nMm8mFQPJHQdlE/YTKr5CZJ/jFg
OQ/TXhNNkbJ4oT3sPXwXoFndVKLnI8WCP/y9DPR82JUgXna6PjUO7H9SZoKKpSUFoY/hTilOKNei
apQitBuYrkoXw4kjsZcKseZUG3m0SZK7wo97ExLe1a+INyoZiDyVGK6Oz5BGNyqoi4CIHAViYUoF
4SztQi3/P9jO5NwNXaiKjVyL9y+OdFitTF5H8qwkdWpUNN2CvelgIDbDx/sUOCfFnGfk/N4lbnJB
s7eSpkS/kdMOANWzqcyRPgfQUiIhO0AOprHQLnMcZNN8fvmPEKQQNifEp304r+BXtXGjfF6aqwWR
j31imJds1Z0ZZtoXlQZSC7D7Clukr8Ps0beXpru5LcNyM21y61aEKcSOcoYl+OcPEnDatuFxJmXy
ztwkI0XiSB2b1qqijAhbwz0Tx076cI2NU/2sJESToAEAI7TkPgokJtzHSyNo53pqSjuROFaL0eYL
Pqxb2OOPdMfcif8cFC1y2xI2WYklLdbeNlI9F+yoNXHM32TgRgtHp8I0tMvX86tTzA05Zo+i9UzA
kHH5ScG1yUK+gseoudZScVDGi6pD3YyC9WWvpcOl5bwJebosLbXna0C201ROUUxQcnyvWgXpyV6Q
2MFge0R67zWAAfCQ+p621K/idRa4LCc+hhpUGxSri75pYxccJtshdl17ThgvIQxbsdfj8imSb0U5
Iq3qTs5GnPAqEClYsEh4eicVQoXTliEOFIRSJKShHGMYcbeNe5Fvv9RwA+anUWChCKWmFZSjcpsR
2OofhkYmIcLFCc5r/2hh88RbhNrxP6uz4j7yaTIGSGQGu6huf4TDOipZPs8PvEKLiyetkOw3vsPD
6FuC6MoWzFnn4hhWa/Rg8+hLLfv14QQyptO2mU6YAQSh4nDIwcvUQg/CL3vU0AVlc+fxDHWtwXaA
0R1g0MFA64DdOdCcvgbiRZjJgkS92nrdAURf8HwRr1gbyXhVYWlGaattodL1deVn2onC71dVIirn
W6I/Uyy+t2Ui3dF80nB4+UVrKOjcW4KShQtqmCZow1tJxJaCS0EmbCeiXv5mQ5yaAP0CxrauKmDs
z5Sf3yZo9y6JTt6JXTvcEl0UD69cosagUJxza64jvho8M/Jm3/5vdDaNFIy82IiEqMTfjbKLUCBC
BB906ikydCU9NQVGc98Vr1nYsalBKCqQdZi//Fpgy66uAeYqINSGVMPhfCN/cDBUd0x+VzZmwXqa
l6cYe/Bc+jjxmF9kvnEfOdqQw/GFAgjUkK6azYe2UWsM2pjSpVYuf2w1g1vjh+OhjcvCDsnNnXpe
UGg/n406vSimZ5pOQ8UcfYiJUe5MQSTFVmMuaCS3CShYNZWWHyeIqew0J64brwwlRVAx8yk0L4Ni
ZH2DX7x+2gTx2R8VidO3zD12On1lhGoVAznIiuJmFjXAYLNPw/cRRrSJl+Z/09ZbDsumd684Ujs+
mxEI1DMEFLpRbCAGP17JMD9h0ZP47UceugDxnmS7gjcZizDWobEKam6Xb2wFq2yp9pca9ofVKbe/
dldRu7DnbGlCQPIK4LlXHIQg9t2WJ7NgUadqn4Q+Ud+FZGlYE2bAbvxGDYYDv1De9gLlOnYrYk8U
Q2r7dlFeIDr7ZWys8YaxZqQ/PNg4SNn8Fl5GwY+k9gqi+yKwGo8xdvKL8VpBbCTGAcKHYO2ci85J
UAB99sxeKMpLla5labUsDrhXJe6BW8Ute21MZBZHzDyPlEtg9PDyCHyIDnR+wsEHHd0j3e+NvvTK
XN2F2YdsusKSSDHxVYIppGpYl1FkrjT10oju0SPR7Am+le2zUxvtVeHK3ChgcP+r6K6pRiuyhTWK
uk3kUlDjfE+xP5Ns3PMZtKL5gj3N0z+0O3aZtX+fzkSPLU/3jHcv53CQJCMSiFNGSFmr/slHG6Tm
cfJVyJ16ttDO+xnMxmaaJP14aJNoVZUUwjyOYYnP9IQg47xsM0ThH8Bf5MvQbif6xlrjbnCGm0Da
4MPy71XLoDha2hC9s7tU5Otv+7mDv6aS1FDQp8y6IU9prJoUZ5G3PpzBfNytPWPdI3Ix7Zp/uChu
B5TTF6DTmMD4qY3hd0B5RLA0s1JZuDLpjEtoqeYt+D+/r2Q4y45R1IHmHhuvNHNJMB8vmIJgB9GG
54ml387tof6vqtvm3U/L04qpz7GyBCdncibySpPSRc0SU0dlMYLKg7v1mEYg2CHWX6Ap3Hc4HjCH
Tigb2rafp/g6ChkRuujOGcXtD4hOdsiDZ9IOivF7KLrXL1PAyRAicfBAw49wVWRlfcBFsLrGxS+s
7Xubld1dp8EFn7YIzQ6uPIvkVZu3L/oPetxi22v2NJ3giED0uv/M/AOT+8lTDw+2KAcUnVUTaq/7
GER4qLSulG2oQzpvLrRfBoqE+CDELEl2W2TxOOm8Y81Fy0faFOMMFSoQ8qBYDBkKSnuEKWkqoNm7
ALKwCXKjJfWN8EBmlVsVC0DUPNsRdtMeUCWfvXU0hsVZ70FoKkgItp2vCeJnE3JZEkWG8iFUynrg
Q8upmsGoVn8XewvPA6ndsGeLYExZjtAeGmKbQFiCq8dbBis3KzynUHIAL6Rd6jT05QSe1MdBzkel
GXDgKPbserfaxmhBWONPdfbHQ7csmKBW7Qz2Yg2pM9Cc+IX/t9DdYlAeNbkzmPt5HvO+w2vyoyuU
L/jK1nkpqhWCbNmd4pYlPW4k5gVYdZvfMce5e/U8Jf/bPevsWEnis519xSIN302NgC/H5CLGx4uy
9skYC2U+DjctCYLcv3Vyfcnh2vyKK5QMlyHhLss3fYa/pflADGd2zjFkS/N8Cd1V+6biwndOGdH+
BHapnz8K+XJdCp7Tqv8e/2DVWLfG6dv4RoWyVOxEkrim004rTc06q6R6/Rg2qxAiAO52+FGUfGm7
fJ/YV1zfimULjTp8Iy7JGbrwvOqDzoqSWksvkPKVA1Mgpp5s2zOsFLyrRdaeadkNyRlen64xbLo1
yYoOWXRusjviifOshUWLKdon93kwc7UxY6BL/yS0/Pm2yUCJsb4C+KT8e3sN01ocUVNJ/7GxW1NI
Z9AC+Pn590lOCxqNxGXBvDNSnVPnybf92oRVasP0L8C+bmZ7X9MdUk+tHRu5W4ZgNxu4LoIq70tn
eH4dzk01996LNYd8eZCg0MIf4zK+BHmsTl0KJHCwnPGImd1WNlyZueba505RI+BM0tPhhlASppKF
gJvnYUBwXpX1mEb2wTTizU+KlA2bvVkSNDlS+/UqqVLiV+I9gAD+eLMuj8yiAhCNLi7Pqp0VXJG5
p9ZvI16TsQTXQHMJzqwlxVNNfXwFo7Gum1bs+8lo1px3eSIq6NIxGzOiMXuAQDv8nBNxRFnY8bCA
QY4ZJ5hp+GI8ibgZsSgOk/h9sprlhHG1JvlXzkVqVCklkOfCvOV1OXbwytvLH71m3qKe2dyD884A
GBMXX7sFK4DIB18jBG0rq+uJI6L8gsqB5xT+Jh06Og2x9bk6LR3TaUhZYVTZPElTysqtO3DBpHXX
2RRB0aqhVvp5p/Ap07PAZQO50D3L1zxQB/TJCYBbRX6pal9qXJL9aNxnY0Qq+JL5EDJ9sJT5CU1x
cAJFDsL6edmGybQnb8YoRRQyjFVe6ZdUxdThCkDuf6LG9KAWVaXgTnyq9tMH5zj2HnybxXvUV+rC
C3HR88Dyz7ZRQAh5XNbvfxxkzGJPnipxY/EkSLWM5mTagt0QYqOZn2yeTNOPe0B/Fqd4/Mp0OWde
c2FkrLPIGKsYHPgv5tClW+qr/Ta2xLemSq/v+5TardPqaGD+l/o4rNXPxnC+d/oawvTfazDbD0lQ
pz2fVYF6YgpseZbfrawabN31NIBr5GvOpGbzzF+4wJMbkOad56onJuEh/h4lKZBE8dMwuLXEUOnc
JB18SOfZWF9hMpIH1885+GO2Q5PRg9ShxaD2hSF2Q3TCpQosUKrK7C0rgvHHR4+jDpKJPLTMnY11
tkH7ODXoExhn5d9V+chTuUlBf8rYMTJuxr39Akh3Lrv14wlL5UIaOG4I/ePD0cI3jO1fSsx7bVEx
DRfmodIl37FWXK+x1RUp3do0XsfHHPzY4fKVI3F4SII3f6HC6MwWl2n0R3l0uL0s490a3rO/WjmN
Du1zHbgEly6QvSMKVJPefPi3KszUV6OiCvyslfYHQIGP8815VXBfun6kGvBsZ9JCxavzSiKQU1MY
xHwNOh/HC5kYsU5Z4BqCEUc1ylGmtAvNzZF5ZvsgTMMUOfXnSDo3bzJ/yq00Fnnzg6Ff48WG2zVz
PT3lmkc059KvlQjpZbmrwe/a1KlYDhypySQBL7uYE6oD6RpdET7D7KQvlgdG5FgOFJUDHG1s24w/
UD6X+4XqZoVID9c0YVJJnPOalVXC2H7pvQM91jBgXG8l67Xx3Eqf3xv2tT+8E8ITm1Pyd7OksRjR
ugUBGltGTXVpSfryVgU9WYKdojg1xhAIpIkmXy3gwackwIuK/oT8BdcgHGjxLIIwVTAKkesdRuTO
JCyvg/5P4q+iDBBQ+BM2nUAZpuECPaLx2Z8d/66uXCSfwtp/W3igBfBWCiPoLToteLdzEbiMg9KC
l3CLqo4JfTSDPv+/9yAaBlOERs4UST9lU707wW8e2+SsBLOOLVRmByAr+IkirxBFXXy6Le9JvTMT
Qz9ek5SOmg3J/ixZGqD2feNfVvxuQfcn5DrISx1bk3hJL+pYxXUlRteggmvaR4dY/I2PMdd75maG
VkZFMFGUvAY/fGYcCmEPbW8I/hlUCceyKtxAZdj91tvCP8ED2yTmdlwCAXDu9y2aofVn/O6gON2K
883bZBg9ZHOxPXHILkg48fQp9NSCjxNJCc7+r8Ho1BlM5KLDohm6RIbNDdgr34s4aJryOFuwF/IU
xaeJ6iPzsiVZlWp7ps9RPJOL1P5T2fXE3il4cfp0vzzYUKhR3NLUWMaRzuw49ulSIprnY2YtzrJA
lFJVCQjDPTqjmtZdD+INdX4btU+zs3V1tIvND64G/HXwPkoOYjX6dTUuJOdFqR1iNHaGXIwIyjtJ
8L/2wxya8NH2J+awJY8MiprLSnJMXos0KQElultVRP7pJAkp1iGIIYsw4wo6/pC1z9bdaZfS1yCt
JlVsMT8cbM8JX2PNHvY0w1RNJkzT01Z2n+rxxAKMWvSbWf6uT5W0AKmDNem26SGsjToGDj/8mza6
U3fCNlQspGMDFBJFF4SOFuaSexb0uy/Gf9BwXOdOCCE1w2b+0oFQPfqxJ+7MrtLlY6w4gDQJllA7
VAGBPpjN/33rVfmRkfB8Nzza+vbCEC/llabc1b0H/eudjtPTBD8rz1iQ4UAtyE3SZEH5zJVF31J2
zIsTcwbtWSRFQK9znC93M4CZNaYGLz3VzP1faen4jqfm35nwRsPl5bO7hrv8mBLeTNBwiVco+8DG
w9a2oS6RpVOF+7I4WO1vUYJHenaVqH1sPfPa6yJq6VyvOMDsHUFzBBy+tj237thOUfSxKSnNA/tt
0Q1t5UWvb+fz/UzuvGoeFDCz7Q9xTsNWlpK+IduuIMrVQmZptH5AvscswuQLtH5qyJMMXko32UsA
HKshdzTeZHpBkXkHkppiiromqpH0UZKUK79yHrX+AQXIdNpwZKs+q80iV+eg9isQUEUDUa6f5kXO
PkdrT7fef7mBVy1IPZhdQ5zS+AbZ3s8g8nmlou5YrQF7xU7LJs1eqCd2jmoAeUTYUWDKP+696SOX
CqK6ZeLQC4nWRM3QZiQBVnzooZsPD4H+KUHaICyYqHfw6bP89SgKEak9sFeNNJQNoyjRcLKwOgaK
iZZY9nedGenAxUmHffUIlqF+l7naSO8mlHQ4ik8QaeSHhoJlThR0oky2R4BwS5SW0ECjBVKJMBAC
aljivXLanvwQQ/ySIs6JvnHAge/Y4qvRcylcG+cb+QnNJRXZXFvUMZCni76dH5uKfVMciJApwxBw
Pee2ObEhVpK8c4L7S0W79Uf4GbrqzxeomBbbyYAKVg10j/Q81rNHtA0f23rPZ8/5C57dLHM1+7i7
BcMkirvtI5DxRt08KJ8/o6vaIb8UIghDq8fgFHgRCH3fGKLEIIhdpt1hDTU97VOAvA21frDT3xec
kMxId+mNy5WiDm9lpXncEyBhvg0G6ZVhe35t82ImsnHwkV+ZYHWZjd0YWLCwcmxoGJloVDd76m3X
2nHcH+uAT8SMeeTVhbzrP5FWpMbBOq0sR3kr5twtkyz/JKIxw0FaGwA3bFHTWQy7iwcyckXi/c1u
Vw+KXpozjYvJI+17BZav5IZ0GmxCSdyoD2LvssEN0ioFUJfWmesFhLiJ1/yoPB8UfFp5Mbbux2JM
xzs96Ywi/EzwvSqQ2nRtCSd3J3KxYufHA09ddK/gETw958kGWOe6xylk2nkJ34o4CT1HEGyVCzm3
BT/VJ41CDl9Mf8LShQu9lY7gIT9DIbv3504IOmZQbtu6nkg0sEw62c4RS36BtjW0LaOKqfXLC2NB
AK+iBZUk5vW7QmEbahYU2NvXiywsGdPqyhpT0Ukg11oTxKDDfU2NvFLHrocImpuOOhoOfGIBz8rE
gwUVM7sX1BkZH/rj+1GCrqxHvS04NirZ4swhqvM3oByBI68SsF0TypiNQ+kx5E7+3nvRfIJ3ler1
1gBaRHWWWS3E8fYdhUEl/DHlXRj4g3CqG1zQvOpHPgD5GcoftpPHSxYS+nt2z2fCRYGhbZuXZREH
HjT58RsJR0xZa8/Az2I4L2SmNroENxmCLenAS5n5tkxT41zoouqNNzmk1NMxF/2bDmjrWMBXebMk
u5wzPcRB1FUiIWd4k6gwDBZfQd9GrXaPCkBccnJPJFpxSMyc/YO1J/GfYwi1dsxQtutQMcbg5Ffw
oN6A0PfGXtzAeNo2MDGr4xKQPm09OqLWnGY3AJ79IU9WvkCn9hSKaEk9sAZoBTeSHJzj7s1BWl9B
q08d7FvSLlGQ/l+yPKL2VoXvq6lx6rZfw7kBTQAlESAsCtHF/srnD/hF+4szfh15UIltsBI8t9+i
tA7ha5z81wi+LocvHEECczMwbaUMnYQ6Y4DpMdB9QL8sft1MLXYVdElSL+EWV5zXwbAw04Cw200v
J3216wmO46Z/RNzxMwxRwnvMUcOWAIlDKDnSjMaJOOPPxirDKeoKoWX8rMD8N26QFqJnjMRwku5D
HfoYE7HQ4nryO6+HMKafdBHY3R2PZV0lh5UpFkwUu2JRyve7KRCyiJj1EWmSPKkc6llogG0Q0JFh
cpsFAZ/Xieha1+dodInYmgjM8/aRV/J/0Avj/ZpzY3MIg/79kSugyA77sxbjugMW8VI6GzDHIL4B
YhyMeWnIE9OLB8O0h90Auq1YE1kLJ5ZgF15hn1HdKMTxKaFd0r99qYx7rOq70h+HRHXPW/SBQ7/k
196cnV5lAzbw49V3sna1T0RbRh/yD9UWtgAmc7X/9Yd8TGHCzZ1N81q4/eFcSN8KsTVLNtuEsdj4
ejBJdYvFTsMtmh5T5do6rPi1mjk0K22t2gHA+ZXwEq/pTjC6POVyPpXyWqlWJQl6otD6KLq7eari
7n31C7es6rMrBrqL8xLknK50lH+3iJeSFUm84MWJsGeX29lah+wGK/dgCiQILQTOZf/QwFeLF60s
7ytMWnqOgQr9xSMewfpzGqK3Nvk8qo+QdOLIGtpf1usxvnbDMdj7ETjYIPPVdmR56h3Bd9HBqZO2
+F6XSN3VicEbQ059l/SvbbVRgafRrG05D3PI5XpX4tTNs7Ga2GEErCXhQauwO0u6caZk7r06mu2L
IH4Qf912qXUQtyKi3G0NYPtiEAuKR2Leex8EyVmz4pDNa49oJ90NmfGgdB/TTgCUgau9vebRt5G8
S8EIFDolHc70hCNM0bCI0MMHdnyPbLJcpw7aEajxcqi6I0LZT/ldmwgtkbJGmJQY00B9duApM22a
fXR/KuUKORKXEdYwlPN3lOw1rkPckiwZBg4VBZzVR6P0JAfMvCvcbpAFSBMZmLsA4Xo2mIHFeDZc
N01J6tnsc58FqbH53Ly9VB669Atmj+LSO6W2uVWSioaC9+fIsiVfFWPK2xOvLdBJzCxE4KBEcnlI
cCImzfol9tajjWjDnBXiZIdWA2xLl/mytjFTdnU4lQ2uUzrk5jRjYYW6fZT1Q19BSrOHDHaf47wd
T+UpWSCwUFUZGXr+ZjWC0TLam6UK9iB0JNbpRdgbB7k9GEF6fyRa7VBggEzAh/V7OwONSg1ZbIdx
LCEStD7lZbPAYPVio4wfnSZph2C0G+/Hgcc0hauRAirZoLWJ8+4o/txvKxSJ7c0HFtcC+iDezbIE
wg3uP1Fy1GtscQmqr0TR/W05U23g5jJAdUqtLslUNopN+dkATn0WML+M1g3fgXyAgUMB/OQGsLGf
R7h+JZWNrWlqBJnqevcyqGyIh+8aOEXdVbEgKRrv62p+mjUGRfxXp/HVP6/T3hqDrhRmhx4jXAll
U+elovJfeADzUT3C1Ve53L6caPcIHtPemtv46iCNzKmV0i/AnwS797tlsUEyUt6TJSnJ1FklYXPW
X8ULxQKlozZfPriWZmfNy/kIH18QDSw3yRiil/+vIhkwAeCzFgUSMnwdDBNA8uWVaNsGHsC9DC/i
kzZodzbv3oJcwKN9BUbPDjEXcZzB5JEsMBQqHeXrsmBsuryBfVcXTXVu5UTXleC1mTWDX5wZ7BGX
807puPYqCs+XK9OGpC+vAa85/EFV4+/NnqcTO6iEl0M/jTyv8UlRMfAGYgCp/tiU3q0JN8QIv/YQ
DvXroRD78IGTuyiZsvUgR7IkVCRC1Uvyfqu5ZHw4iRJaYGPEjBAKnmou6xyunxRe1ysklMk7xsZU
3AtGgv/99Yb4/yk/gQBcchjbXDyDXgyQ7zCMHBbeCj6ZhFQUUsrsY4HgJEOHerIANl523mezHX91
DiI25BZjJfLsiEldOmMrIxGOCRQBNzKKnoL537fO2QSxBz6WVZ1lN3tdeUzFkembrODYuyVkoc+o
0qME5o67GOFOPSxkVdtfV4NdLU2QtH5DLWPdxlKIQhMNGoCWy5bbqyr6/RzV/qAGLfK9xVtS4wKL
ng5lqs1mcrtghVTnE8Am7qF8XLMkaqSBNleSEVPStOF4zlW1UDHHE7FZiWMHB4acLHsi8cVRaPkM
EZM31Q89ii1bqRUNZdh8gcun2vyiLUHIucwnkYXu+l8DTJnQjEz2CK/pV6kwWF/ZzFU2/4ebKsq/
rNcKpHL/HZmCtFlPTO46ppVK0uOuzmg/GrW8O558+ShVNq8IbLFpK6/kM5blQbo/Balv+Jb+I3nv
GBm7FxZoP31thbojXQWH2ICP+WU9XD60gEjrqFCaNPemXYJUtHayUtAcDPdITulxMG+1l+lMVDgb
OSCcHSlIhlY752SU/W6D7AR6oE9a1yl69uaXwOX9Z+C90YeGpEOd1owsHLMpkr0Pik8QPVC2w4Jf
1iajLdN2uo2Hc1UIAfT900PePGpjtlKCqB6vAqkNCN8komBwQ3eaio8cd9jdhUmf+Ah/8nvy1T/g
Y7qfv5vyZ73JT9R0+n5iNDedmYEupAyKOTMe4WNRzoI+HtVDOVVI9P5ZkIx/HNdXH9V2yvd6mov7
s4dNS12vIgv8yEyaiJf4h3Xu5yePWXacO3sOz1oAfd94rRxQpzefbhEdOHgzeBxA7273MSboGuib
RqdmTr6MMEoVWxC4mG+BwuD2OuN7so+DOyJnOC6QBLKyHA5jqMgZYhhYk6DMi0VwV2OqDBE0hNme
9dCduQ1tFjboriSxI1qmQ88dy7rTq/uwvwZHotOKsyYZcnzkNCDm4xDSiHzic6q8UTKEfWeRTRcp
YM0s/xRZXNvXXGG7ebrIbsPSD0KusQlNFPRXoPL23tGViytXCu/oGI6QT5/rcp2jZRZTk5uHsWMw
HwbEhOAervFvmJLnU1dkpx5uJO5kIFppg/8FmNGawdKH3/M1MllPiSjRWXk5HK7Rcwn2uaXNwWx9
EeRw/55Zb9BBhCUeF+bA98kN6f75yN7On1hD6bSLwZ1sIlMeqFsDqb/B5dkRojmKrN6KFPQHq8Za
vD6BhTmKWaJvb19JRQAaNPVh0PkvzwVwfPYOdaEGGukpnuU9OgRT2jwLCN4zb6prqDYP7Y0axhj6
2P91W6pnfAetHsI2LTaDNW/xDEce9CKGOuXfpnOnbuaGrgic5tUuANNq5YzoAWmggyBL6OXhWow0
WQhOaKH2asr4ytQXqvje0emxlVwRSyT92HuhRuVa7OFd7p1/EY0kV0zQENDSpQ4SUcS5rP/Olzc4
ioFY0Sawz74GlJ/Gfaj2D9B6t9NgwVYvHLxiSrsDeZv0gOGCAprSTPD9k2NE7dkd/eX5rIO0gWAJ
sOdORGuv/9NP2l1PelwMtasW+6WbtCswOOZPXig+8pxV48EjmGMlYt9VkGDycv9+ryzLrhMo/MUv
tHorAKL+pbVey/kFGhgcOFZz3gVsabVVaE+HPOgDlfSk83h/7lpZgfSdgY9Ge0uV+FhFtfLP6Y68
kFDZ2D1RGJ5C4mWig0ksrAz0v2zTY92o61L9zj7XfwkPbviLkuFmJ0Lbq7nvRCyQqDSUpXQCzFgf
h4hTk7eFpT/DaSL9C7RA0IZMdGEMD3mlxiiDRRrKdy+UZbIXLhOqItur42iRzWA6RSrAj9uMPTpN
qkQ/APd8JeBRFJCc6ruFGdhkUZ4LnJmvdytqWVwsMhlsVom6noNUB9Rh3HsFyTAWlPDl1PRusHSs
16YREABHEfEsZLiHixEaMdYUa6bAi0zd1TVIFV1a2/EFPUat4ou5ZEppEHZm2m/rvFD+NFdi79Zb
hpxY1MIjh1p55D80lPPGDPvs5a9icv/XllI9UhAwyA3SLriz6+RkjFaFOSU12QWNHnfbwkbrsj75
wFOoYWFiYu/Krn55QX9maNMZRXM5Mys7X22BfmAAg9mNEQlbECmjVEQjGIPR3gaaHT8ZontKws7H
p3eXI3pJB/xWYPIgxoUnQFP1Mb9oGIIU2nWCpKBgEiceymR5NKFNh+dEFdXsX8rYLDM4t/4qXFzd
7foECoCk3lqbOp9XSDen19uJiDX0u0P0FhMkisQWHLZmtbjuWxeFyaWhJISpsxNGCJaSoo2yyd/8
pa5cBUnnCZa3uoVQY1QTzLedOQMeAwfNFeYg18cqzxO1GbhMM1O0xBxksK4lKL8xMcUCssanhHfD
jxQHSoKdxnARdUNBaa4dYMTw3feaF94UuyChuSv2lWyD61gpz100efrbjVyseSHaCZfGRZvJRfnU
uKX+UDtfpWjsTvqKIb27VRzeo75FUTesw0DmMk3ZWIPNW0sk0EmVdvchy7LDaDmoCMBfha6VhvD+
VGbVBGGUw2oIK7m3uYq8OYSYhqhT+RRYSRwq7uPb/9AcAeifH4q+FD/wzVRDVsdSLU87BFtKN+AJ
X6pHdx4aONIkHXdYmx4cP2+Bzm8XUDgEc5mjlGzvzZle88LpwX5NDtjzTF7jgHiQwFVm9xDoaIy5
h14BsfCHYNm/tdpVfNjMZfGIfhrjpY6zkpX7n8TzqBDWc6lf22Nrk/AMTJ10RFZbYJ92FoSdkGxW
r9yM0MG4VYduLnPIPm8Om2IAnHmpqG043DLAnAuXzowvPqcNqt2R/jq6hWPqh+VsZTfEAdc+aGYm
WeOsrglQLouJNRlXKz37pG2MKn5JBDWVh63ALrNPmten9/kx9x22O/TAdbZCZVzC94a+A9Kf5DgN
0ql0dPVXHRkNyKu/X7xuQN6xsA01rqz+pr1IIXuawg/JyZhsbn1LFWPxu9mSL7pBWMJBwKorooAy
MIglzsUd1qGhZt43b+xgrAcLGSMED1WG1vGTdwN5mXE1gcInAaGK0GvhNzRRcfkQJMcCm9RopVOF
VihLFeHBBl9c06SueKKJMcxtruMi5T2yJazLY8X7mjVd4rVmr+5T1Pe3FSkxFM5f0Ch6iAniO4Wd
hnkyyy0Pt++4LWFrn+8FaGkQu3EHFdqRFKHwbo3W6UcxBUFsn7JAsRi9FYIYKR6knhKd8TmA/ISW
raUlXmRcXjMkfFf6z+UyaVN+5XbLqfPiimlUe2m1msuCDoE+IPtNvxm6okpYYOqzXLpxMDPnyCZB
WlIh3chyIWuupQ5zhptymsmqb5pZyVicKtC376wcaJRrJXtwNvCbTVpVGZne29E0mEsGHaKtIxjV
9dsMXc/NVbzmy9dTidgsFRL/wObGCGH6/cEjBEwAlwZXeMQcGXMYLVI1y5bhiEbix6BFnYoIw4xf
v5CRCb3E+CTTF3r2K3v6/CwAUkXhZ+dPds6lz+ZFby5PSqsr5YzOB3GcoFXJcWlMt3dgBCKeZ0rf
I2ShJ3xvXGyTB0++GLeKMXhBEXthFNP/VQXZb9uT/HKFozHZSl8jPApjFjNXlVkacGoh+yteGg04
bTzGd67FgSIaST7DqmrB0jYPWXswChw+mS87lRxH6e+CF4dHiwA1zZot1XVRKy/MO0PhBZ/j4+k8
NHcVrWzAgO4YNLCW15/Bh8sI/oV+8NxaPTt0Sri78MuVxYQCxC0dMr6atzs6jLe7BUZDhWyouDdc
3fKcFe83P8R0LOFJGOB7fnZUr/tpW+3Q+Ezcb9CHjVdqsUdjEt8inXeBGC8NQ0Y7Y2tuMxZ1CZRv
cv3/yZV6i4/S1YpTAkPmohjbVoSft7dkA88soA68Lv/RMD7ktqsyyAAxgLaHJWskglMCGoiQK8D0
4Sd9/qEHclbOaABbz1eb6crPOs5zUkoVTONjuffJuGGmQ2esxAgKgWjBWUWU4+zEe6/U61tzzuqv
+s9PZDgFvxSKPEUSaCJeHRweEA9m6cvgzAPZy8Hvl+9fLcn6emrnM0xdC4QIvO0Y+ULermlsyWRr
FXFpUvsmaRCYVXgs1khniY8Knl3F3l5dtuW3d+ZHzyEGMQ9Z7GovEijlnWNfuM9Nk2k6u1Mp/qFg
qhHtBw6YTDFied1Uz2tffvVPX8Pv0rHx2DtHwFjhOTfM4V1WLwK8LLnniA6Xg75m1kRdhT9lM+Oh
HO8BLQeNcJ+TbnhSrhoIbAC8A9UEFUd+AB3j3bPXlMtYJGPg8bh1DsBHaK+jHvnV2eO9ke/Hg7F0
XWp7TafXZy0i2gYphkYL7ffpOQf3xhJrQOQebWLyFrQ3jzarW9wZDYnPhP1YLE1+7b3jC9JyCPft
YCO+R+QM5ClXYYIVJkcZfv+hbod8j+sl13aMNRNtac56kzkVMaE1Q6ImOLrn8wKbUHQvk9fHYvSF
W5mAA79FVwOzjeewTUYkNLy4Tsqw60B79ZXwZIgsDSfFj+MeE/bUhDHdYJljGzV0XgA1ncgNzAAL
DulNEtQuQPxx+8A2qR8dj0FkKl0fL0Lm3VqqYlyIVasj9JRyvVRxumsthsQecfd71VtlLHDIHUBE
I8IsMpff+jUAVxPfLkxP9sE+j6ptce6aOVKa/z7AcCtG/13yD7kIEHWRFg57VtLL3jya5hj8dfbW
nU0LY97V3o/XXmtdseD51svYDNaNRQGK6Ruuls/F7OJdhYrYDxYvAz21bupOQQ0YsbdTLhNLwVnZ
5fn3mh+Pefh2SzZvo+ZkALGqCnamOLXlVFNGBC9leSRfqZoc1rRU4T5nsvVacM8Hsu3QvHpqnaIO
Wfhns3cIzRP8eKG6wpqvNNs6FvPE/FXWwZrBsrv3CbGtYjcg7+pNc0BJIfF8P8O445GpU7WbuG/A
PoSlAFQnx5l/kWd+6jsrp2eP1FaDM/9QcHx0FlsN4CsxdJ8yHkrP855/i2FmchyUZ4VKZv0Ylmmw
uV6THH9Rs6TN59QP5H1FQpA9S3486/SCoyq+csKIVSqAWbRvNggMDzr+a4QNs4UvTLFouoZNaOar
Bk6cW4u1mSGQ55f3WeA6Pb7Sy88eh0FAmCdfovVUTHimHQl9IshBZhTgiPFdyvM+sKL/dK/w/RK3
WkH1yfQJ6lLNlIwstbVjCfn5415/mP1okp+5wrjCGfLceXBUajPq3AMRjCgWKPusBkmS3t2fCAk3
LKXTAKk3XVVitXev+aKv7s7iuoe4Y9jPbPXSZC2BmSDwc/VwmsDS4DBkxXlekHQF35PmlFxa8Jfy
3GXz+D7yaekl+uzYkWlWd17q9ebEbDOimCT0YejXLcG+oHyD7O08XcbBd/VFaSeXJOrd8PWpDYpQ
37hyTfUio4DXQLuN1oB1DtqJ2h3yOpqHNQJaC761flXrmU/dVORcQ4xz9qXununyuIqHiTFtfFg8
7pD2s/mupKwnX4jVvOGoZZJ0eNLCgWtjP4oBW1Gt8E+oSFPK2nBuChb7R6ibuLnGUZy68lotx9vB
mgY+w4UwF1AlNTdu7GFe+hQtZSWaQpMlBSrojPbvZWU1ZxjntpdtnVYRomQwpyn6fnaJgIxT3Q3e
egP/xcoSOlcZ+6WHSgdPHv1T3D1DNCvzU4EOvGGII8kwl+vJcMKo4ltOsefW5AqBCwnNGZDl3zev
2G9ITPJ9R4O3EvLa+ntbpLrYQjPZTwV8g0AyraVaj43TZQgn4LxH36yS4JcGLkzi0yA3Czr2bbMJ
0DcexXJVw6L8DrimctPcuwmnN+JkaBx5WRYIXsj20YXfqkL5BjS9wQ+tdHsDrCneJvYL8gmXJPwU
VlN6hsg5ip7jxtO2kaac4dx25BjrowWcltQFbarni6sZ5Xrc16LUgNnnqRTVxAd31CWj2YFxYWmN
6baI9vOv1K3qBErHKSqngZgH55DxWUOSjzLHqwkCCYezBqm2S/Zjo/2no4qU1xd6nvY3o1lH38z4
+AUvqKAeKX3RAzxtjJT9IuzcioM70p9oGk3eSH9zE2MK6eFrs5yJ1ixfHV50Xbgmbqe9ghpyqLDf
PIFn9m96tL3bRH4/oH9Hao7oE95gwh1laQcXr5vJ616ZQAuO6sGH95gL8xDqByWdbJjFHnjSVfiQ
dV6dBg1CddQ8VhEgChPI4WwnkU082C2RscrvcmdHV9v+CXMLCsp8JAnGiy1mbmcu0sgBUF6sZ2nW
1kuaIlzkV5xE+EpwWIyGAbAXCR6lJAKapsV3ejJbyNfZvhiFUn1E9eoOSk35iuhSxighkY2yY7IF
p+FQKYNctYc+qKOjVHhEBSnSUyCTBKMk2GF0YsDEXjaU2B9zMrZVNnp8/jEtX9W5rhaPVumC4zLX
7rX7PnuIgKsXjL1E1QT9OclLqOacAqUPYWujBnSGwRXhlm6b7qX77jh5TwG4e/aDOgEjSe96EOmJ
QE3sIDYKoENcAo78VGnNzlb7Gd0nOi/eIK7MSn4peRIinpRB2qug5KPXd9dePTFz3cHEeAAVMF3A
Yl+/6Yi6ji2MBG3QRYtAYXCsOxTuOtNQu3yHJpC2gS3N0qk+wcsd+hWs5jDYIWu2oYT7Zr6J47bc
ROnOt6Kg5XVeu26s1S9KKDZR2KNUMyvhWwaiWumLaq+6B12Xg0Y7PQIfAELwOp9d3lU246PO8bcc
iyot1llWAOPHTs54RmtGjgK6J44Gs5ExvfQ4gWVMjwwKp+SmeCtRkIe8eVZTGmFCgzeutCnU/ZG3
aH30xMSRELl8owu2YWAVAhIB1jF0VgR7AcakErq9ICVFeIcbPtcYEeAdAZ0vt+kvw9s2V/HGtJ6v
D5t/dsHAzbUy98I7UEHlUFqUVWTmJMc1zG00dmf6i3a8aNo+4yi864gewvwVd4MV6aAsbjANxwqV
V6Jc+Rll5v90BwefZWRtodUWL31wc0pFWjAzmhrQcxylt8SaETVyvhFsq7+5WUzZuoThEezAT6EA
tWtdLIguPpJzbX0/2HTBCZqrnQY8MVz1U5+qHRvcMMTKJXu6pkC2AaKieyxRJdmH9mTbewj7LMQc
9PErS7YhT2GprzP0CF39imS+RKa+GaCyjacVxBGzM9XGVN1YsCtwoY/Np1AIrrSHu5oY1K2cPZ4r
/8l5C3Tqpgam/bu9/Eru4L0UxAJlNG9nXuaIvTG01fcc4mqcgDJpphXI+l0pPYn70WJyTFemG7Gm
kjx559jIc72fj5J5FMNQ1sZIjl1urmVhG+W7E7odTQPZWZXi0b6nL1IUPsYo5p3nFADGkl/oudER
wH6opGFjKhoIcvw1Vk+7rzmeXlRugym8G1OaWiY1v/QfArWjixS64IDIrtr8M0SP1b63VlsrNoGl
Tx1lODXaSB8TsqE2onip0crslvUKsfxiIGXhD4KviXhpe+AZ4ZDymEmP2d2yUvIpP2DSIMWaRabs
6L4L4ODUz+RZOUEJqgfofd+ILovzTxRozC+sLEkV9nMFMPsX7g6GzFPR1nNZwv3M8f3FMw3DQ6tv
WBue2Xz/WYzG7X9rEUrcu52FxpffwlPuKLqOHQPScVqv+wRdKmGB5vGDojcDf4myxAyHZNh070A4
PaTYG+oZC/4cLAYqqnRwSHlaKPsuFYwr50u+tKP1BuME6Z0PdbCBTU2mmU4v46TjW21Y6/w60wq5
h9QQTbYpsrbGnb6XO9POezS1qKk7EoUj77qqmmLtzsxGLpOD9BKvh8lWwUir2LtijxlgQMDuLwYB
S5Fsz0/vrUg4i4sVEkfgDmjxIlHYk3wC20FGVBlBiseVZ/b3/byaNNcPTOMAl5EJvFUgf8gsD2Kw
ty1Uc1F6SGw9KWZXwAnN6TXmvBftLrHB98Fk/khHGVn9GxY6Z1mKpyWBgAuARpDRLQLMsKg28y4s
Hzb6Yqh+ZGxEvlI7BT4FiA0a6lQWNSshMFG7yb6bhrI/w6jXsx9G0gEvjBRExQUuIXIn2fiQ6e0W
e0XbBkHqRMCTjXKC5lC5wccxuR98CGdb3puZ33FygkDdI6By7Xew8Z8zfjMM0aAZdXtASNz0eC5h
v5J2T1RqfrQU9It+Yoq3qUIgqk7u1dywqtfRxJjuQme1NHqLosDaLLWHZBJXMkNUrCWLhoOw5twj
BYVC5K7JECROjx/WBMjl9giCuEuycJwIKx/CsXu0lXCt2BB50qNwmo/1HQwwB4dizjJPyxmVmUbF
wS97VApM5g2EZ8u6zh2BrYvKPBN5m/KaPexN8903k2NQm2WRLcLQq2hthP7xTDjtCPYrYFsj/Nvw
5eGUgJLQE09MGNm7X/VV7TcIFmN/KbdsKAyl5EikYe4fMSWGZ/DBJ2E3gFfSD8DuBUDhnrdGCt05
w3B04H+OUg/cvvY2zk1Rpvf0buN2YwYbTfCSk+mV/D4gWcVgyJ7ZWbAUSBZdcXrkQuuiwgNmbcMw
flPngn/A1DlAOd5DCftJfNduk8R2EezaOBBHFR+j4BgDYuSQvLxjAB7iAJu77DfY/3y49dr03PxA
St7lRaFwx8l3qY/SN4Be3VEZIUtUXjUGTgc2xRQvV7/lGid8j0oI9e/8pNHtMHIsBLRe3AdT9U47
ZvUA7ACguxzqoz6LGt5p/Sek4UVrYJP7d5IRVe7Q29L5/6t324WWciEB7Ww47KQb4s6y73F1o5lH
cj+FYOXxVfPvqPDugMiBLWbbtQEvuo3Q9S8nZg7VwTi7eDGLvFLps5O75ImyCPvj363+oahVnQOX
YKoxPmyefoIZW6jRN//SSIzYHra75F8cKik+aHIRAhCu2EsIANr45uG2DFeTy/L0Vxa2V2VewCix
fS6uDKjyoV0yMExRYfBUpSKLjv7y2YPqkckt6427Ffb/aVjjsSqjTA89gLn55NjJoK9JfdtpAu0f
O61gT4PTIT43QYT8/4Nzx3ezmuOmXBx+ouT4eeXJLSQ1jxScyzzuNvb6wIEpz/igtArdqps0GSV9
34waOMmwzTJmC7u7pYxaRB/F9AKTlkuJl4+k+K0nVMkdpZx/18TEsqcE36CreTNGfn+RmGMufvcv
+VQi4WOLBbfMn/dFotgJTja8qGPXY8v0i8wgto2Lh9Z2qv1ugSxosT2FQSezF9f21EYZ6IEE5aJZ
9koXaO1WiMF8kQkoXLQBJ8F03gvsfA2GYoRx7T4sfKIzICDRD8cUeCpSAZwkBak4yqXDyUn3JEnA
xO4KmTpaWpxabMLnyCeSRD0hg26qntC0qsvjKoQfcehkd+8wdf1nieVilTcvHTWx9giG1h4GSFMu
ONx4Eb3epaISgHtxlXQOvgPSnLrGhfwiIWYuIwWYAwWVxSCgPpjcB0xF8l3wZGGnQ9nVWcaQLpfp
7tD8VStcYohAqG4J7jGohvv/Vbday9201L2mV7ss6ExhfTorlKcPhRiVvOo9wk9s5CxGID7aBIcf
s1wvKWmzRpnhk5/8iurMdSwOvqotQHXCTxH/zPi9z87W3fI/xswVKOXUSNvaXMn+eUJtITuNNpOj
+zIt3yNwmcDqgzW7U5/rqu/phiZ6bVLVmCd6bEPym/4HMzJNK7XLVBrnP1i3wQbE/Qk4wt128bX2
8fvFBKX8OEyvUdl6oB7KL21B4EnJ+MygZa1BzwjQW6so3xB7nGBABMwJya+frhkzq8jbKxHKbehY
BH4e8LOTk92Qr9hNnfg8r9WdGMYlofKIPyOIbR4wPrvLxI0/F+6v64L5HbcqHj+HcTdUCbxpzm8E
XKAIk2KEzTIAwGYFzVJ/FQ5sHOcfc6WENHRd5xG8C0FgLXzbWg9QVJ1zgPwpx3Nd+pTGHoqbcUdI
DfB0ZH1YYbNE9WmvHRPpQfk/tPK65AsekGa5YaGat6T+IQ2GO4ZWSVUXbHJZ3njcked8PEnY3Ru2
OuL0jeYovN2Cg+/TwixGEV7Yy+p8RE8hua7rD4QtUiMMrBYw7GBQVWOpml1w1bPm+GLc0IMpLUs4
0XCue3QJIxcTc3gfNfq/YwB/avrb31mRPzZR2w4eXGXzdOanok7uuXePa0CF1tryo8cvBCePudEZ
01mHBRH18c3kkl+69vl3rQldiyJJos9YLHcu6h8ElDl+/4tIOrKAsD+rIye3NvzlVV7Ze9TJhX8e
9H9HXu64uzClhHVa/8bKlBx052XPgesINJPs6Te8sFJaa9hpTpUmm4oc0ECh665uk6V8UGYWS1W9
SKSGqhN392ygTXYJHRwQZlPaE8ljS2dzY/qSuPKJyteWDdepTu4CI7srMuXGOZdpRB8ENpk3KP04
mMa0rPvYVzkQYynPNAlhEBHGZrKQ19naOaRpC/nMEUZQ8hglpj7i1r95dXvajYjGztlGX37zJnCO
Qk9rgqK/CKDQNngjB0V4RVWnQ8k2JXau4utIzwd2UPQNlWsDh7D2ItFMVxdPwYfnxBuho8sLZlDK
VENd13mdb+7mpH+bstyz+g0Fj5CsQ/5V6vXp9CZDY71QcceHtD6MUNThDQZ+JSVtBGhdBCtX4HTM
HTDNCiF4wI91NUtCZb7ewVzLCIiqUf2ukUSt61K4AKu7n39hugupIqQhCY5UG2QkYe2XTCRaroFv
yZ5vG8PAJ7yX/s4hpIOHaV4NAlk74MEs81dxrgBKlhA8gnYIOrRtqUjFVnHqjO8WXUq2CgwiUlVK
WFFnyLZlg0KHh5ckggKHjVIpmdqNyeJOPyf31iQh4miRQ67Ynhca0wzZ/b1ILoU1TNI9S8pAHus8
SPXe00QpHu+t+42BGjSNB3qheSbzJNtoV3WcLvxLw0hu7GUtnvBdEXv/7mFWKWdCMhBT1MgUV2OM
tVp8R993UM10iNdPJHHdONXkh8JGmcOZjx800CtAnW1Ya7Ut4WaLskwf2QLFKPS2NLpoBh6L7F45
bE5beublFGtUse/YlWur5WsUBqJ/FQ7Nd/UcSd+IrJGUgFogE/RFGdiGipnGjl72KBm6WfW5xvLO
+9QQ6T1HNJljwwVo4miVhNmmAC/Hm/ASiI3ZQ+SKjHUk/uBRjIRNo+1DL8HWGj1Zryk03KZoJLU+
x8mT5Iq9nKGK/yda/e2TolgFPiBS0NgdvtYroFEm7YM94HFNhN/W19pqT1Fu2ieJH5lH7m/+/4MT
GSHkeMR5uyopLmCSKcif6AEHjD2Zi6p4xAm9cRhoElKtJ2Ug4MYvR39IVW4FD0kyBYj999peKmK9
1jAX75F+SgwGRArxmuiT4Jsq49qhcD6bP5mFvOS3Ues/GH0lKwUVKy3D0L1xdyvs6BXaDJrNVkyd
lf3QXgSCwOBJ2SmS5ZXY7APoUpB9xNqwKAiJwt97iFV4UkSK+8pNFu6uGI+3vHiEYDSLhmXIfvgK
ofyuD8glylTS8Moe1ygvhrSJNA1Mqam23AHRxSCG1zlYV0XYQe/3GtShGybctTKy0Jz5CZ80QhYi
eHBGXnf6bE55v+vs+8mEO7R5jLV194XhalplK/Jtg1/ohaZ+URsinP1mHCHwos+ZfCz0CGw6VV6D
s3fUv3IT4rAq9q+8QfcoHDShXv4WgEJwLYm62SCzkcbjYhPAP/fbl9nfgvoz4qUTzRkbifRnOAw8
FPES8re2FPdvzlqtR1QcnV6GhkiSirH4dizf34PHjGFPtB4wyhrs97nZvfmLqbwg3DVKIPZkoZhx
4VqjqOTGbp3N21l7rTQUeWaycO3TvE6jh4HTUV1U41vLEPz9ebJ/UTA6ml51NhB1190XjaqKdRnm
8G2k97e3a6V2GDmK+d/mZrTtwQKzOMFy9gp42Y0z/Q38pnQHVKDOny2TR3YxhbjKLEv3bxFG+gyC
rcOmr3fSkpyyVm9sGnYrePaBFVndB/6EaVR9NU6jBd1nsnWJVCOoVRCnRFH8Ww+b4FLV//BH1cE5
dHndss4xYRyuXc+IvlDBEOZGTEJqgGYxH8eGTfY2Js54uoEOrhE+NNULsYbp3eUJb9mdB1VNtQt3
5YxTL0yE59xfXTVS84XFo5WTHCSYtd76ylwmNtPLhSuyslqXGt1VyOvnOZi9MfwA0i795v5rCWfp
Jt/Sf3vUKx5c5T469E7tmGt7hvORNbc2fntDdISSR7vYJG7xN6ATSukOoVAQfSk61VaNii2etdTF
CgI59tBs5f323ilqHxqYVOdiqRx4tVbuWbFkwfHJw+wmJ20N007Own/5ptPyt0NJ1/QJg6/WR1ft
WF4u2WJ1z7S5pqPCkRnw0ikh3opTMHdmT9EaqFjwnc3MDt2j5pK74+H5dr6F/YBdjatjSEJUcgIr
PVIwLbZn5teqoLI60b2tWmdvwKBmW+Q2URUXHzdXnoVQJP8SFS2+/n9TJJJBaW7o6uD4wVDk7IuX
/S7tCFI+qvfOvgAvKbxthVCtzaD+3G9h1UaTJKlCbLUfqYqPnujsnqaK2wBFJxcO74fv+RtxiauN
2t1529XCIDBKn8ghsFeejUiNFtsYTG87xEwavkKAervYqBGnPGweZoSZqITLzv3YJO+MY/UK58/N
mllnYwM0xd9jyyttKSfuOTgcEd7DBPIC7iVfVisuQqfBU8Xt3KWPe8u1yIwbdPo/068SXbfuPv31
N8wzRF//EUpP8n7HMooSNvVWJr61gS6JUW7mEOwzoajr7VNMRKcwRHVijSxEk9ItDksyuWc7iOs4
dOfbF1FOoWtY17zHFFbrocVLkSp+XrAZO1++QN+03Kqi8ZBgCSvio/BQpMLCCgD+tJMKdcBM7YMi
fe8WXm8lxP6AAXPll/RY9JGDJCn2XN51UmX1mF+F0mfBJHo2kzw2GS230emW8l31dOa1zN8qvO3S
Tb+lCJTCnpg3fenjkRPdZ4tGGEuCnfxMLWVUu4Zph3N+Kl0GEkKR72kH40XL7Ix7+u1QILU8mAYG
WGma6/Wd6x8mQYqY9vz46n1KjCit+3DRmtHFd1HByX9DoBOVp4i9DvdFvaOHXZa8MhA6YBCfH1Z+
YiQN/0xl7HqW502WIuy0AnDLNvKgEaypHSkcZQBCk1J57JgCdlqajtLsEGa9Nqzj/IDtTDu4N3pb
bXi+/j6TOCaGJy6wZ43uZnD/x5dorDr59t7s88dXrX3jUp2Pn3mLphQVCII7BL7fUFILBS7fB6/g
uVBZ3sj08rSqzeL4/ncdxsBqyN/v2ztyRkQO10BFywr6vLWI3M4Q5OF3qhyQlipSkwvIcQ7Y7bH0
U0SD0ACcsBzq5kVXjPUZ3pKlSaTNupYTCKzvP1n6bl0v1DORFhjqCEIk2LcOOfs0iQy7aUC7Hb4F
73XhD85QmdvqYzPV4AudpbidYfzddDkJmTP7qJAwk+G2Q4KfaeWZXFL3TxMQxL2dcy+a0yiF/QvU
k+Nv03aLztAxVokiFDoJAWnIEpnAFdoJ56BKKcX9XbB+60CdgF8qOpHoNsWlaciWTXpVej+iZssH
D/tWLPpaT9ex/npnXCrYQzTxbXeoUbV8dX0/qpIS0DV8R/fHUAkgCk+MqYFL0aXg3Ty1NlMZ5Urp
4PWNNEJMTWvzgUdWtixjmSvl+vtXhrtL0iKA8oQvKOEBljp0wnirqvxzPQ0a26f4UrYvN15PRBNC
xq4bmj40LVq8ozGfAg7IeB4k2VxqXDLB02ss4wGWJd3Pj5K8GSQ+z6rOuXS5ce6QaWxv039JqEf1
T+I/DHyXKetdMvzP6qFV0iI9qB8X2S92jrtHERWHqHsG0OVxsdq+AjOgMAXDpX7fPLmW3eG7XAIG
NHUIimQLiowE+Ne40uc55JjS3A0lhLxtp76KHfJfAtlB+dMrBHX12s4QiYkC4gXyJZmgR2xlovFm
+J0l5MGxiFcZMxbyjQX3KSPiTZxpid0ABzJ9byb2S43Qias6UmZLX48UvHGkP/rXNt3KQUYmdwKd
t5LkJYeWiBnv1CW0qPU84WAxjuDkoGgTAQX8/ULp6toudrcdnGiAyteVFvB0mcGKjQtJsadbbqGl
RU8CE4IevWi1Ji/j2nebBZxu2q6FZoSQ6frV8Y+dq3skfFYcyvKtN9WS7bWRJ1uUp9bgF5ZZs1ux
wFFvTvknghgLD+Dtgl0KkvaNbUY3bZ9q0mBddJSSIMiJWFoyQQwPB74b6GUFzyi8+LTzETLWRjeF
VeBxo+nXJUNpaUGKYviIt3MvIlhrfzml8J8DySmWMLj2fEhofodAazGN/QkSZkh56v1VvN3km01v
N51VtTZkVUWBe8CKC8qCumDiNAowbRwlnx5TOuBSDcSL6F8H9FOLnfPNv4x3mhnitH6gmlfgWMYC
FO23enMJ9otn1sd2Nebw//mB0riPoexjOXVLFm+cJWuSDD70hyBOLGc21cNRh1wPtbv8FKUeW9LO
+bPqL3CEBqBPgXGNM79asfG+sV8HzVgofz5foeDVvW2hzb0viDfwIiPoPXBjgDSl8J343iOF5CWr
EnwShqWAWp6h6WGbzp0TFqyQNgTKjcbh4HI0B3Wk5XxlHd8Vik+MFGKRqXCTgrwlK0CIBge0prWk
k/qarMQXRUiX520nazHJW+y559U8xwa4qog8eN4Tg3XyycXb3XaTz4YohWbxfr410gVNOw1VMy5j
//KN8lFKDSKLJs0mUol1DAjlv8BIcyZIdNWM4qnXxMBxmGPVoeD7J3iYV1arQ2Tc9ydZpFD6Yo5i
ZQpOtFX9jLE0FRxiSAn7h+/1mhIN+O6pPqzaMBKnr/huBTZUcBLaZ28Kfa1/nAz0Dr8MrmINWKpG
ely5a46QqTVtAwYY2eB7T0yE8y4Ojye/rTeVlFyV6dcm1P4YlPCpASQGtrGfIitigYDZDRsNx8Wg
6eUce3hRuoAZczgyowysdxLJEvi+u/GMjyMDfvDh+8MwvbRKQKVepAvRQW4FBg4aSGLkHYw6bGCR
ihQZWNy6Vrsj5/zpP82dEnGUTrdpL9beZj0Dyx3CZPGM7Hf+oEkMBsAbaNJ3JFupTm2Doal447cZ
XJt3iWq4HpcBVdSRicxcl5VYtkNs1rCX7uKhuqof6EEF+62EPzpYj5JidL6wcDrMmQ5cfuQ84+pC
t+i85gBE3s+JqzJK7+SfhnPL5aw/W/qWgSLpzojEfAxsTvzVJWadPzoitE+IMh3a4M6nFy0ZNGg3
E9vQoN5dzZv9HzHe4evSkDFqucl1YhZUYzUSrAxEvJtYpQvH+wl1jP/xdpF2irc+n9tOxhjtBTi1
VkNnfe37KOBQwGnHgPcBxYfmhJViYaQcCetRMSrKrpB87L9UkapiMNVYUZ9y3aP0cd/I0JtcQkW9
UVB77FvuBT41qlelazfBX3CBDeiFP/aLfyukgSmZ6CBFzfK6LPmRDp0lWtyAEKEtlh9FplS66dYB
yjYv+BWfI3NB+aIeJFYmtqNJ2ZVjPbfsLtM81qplQZHLd9nnLyPkMbrPp9yOVXR9IiICCuqIT9rb
ImrSRtO4l7V+CF1MIhmH9VG4FNBH/FK98NiWh7RUQxLlnohMelt3s8jSq3HNeawRXCyW5LTVhrVe
vUxLerKTDUwAcEVe+YgTINKmSiU31fvh1MZKI/4bdOdcs2wpEIR7V/I37cowhmAQOicqt7Iv4PbF
Aq2+1YRxNcS4mK45fDCg0jfrNyObdI8xUh36kbMehQ14jZ8W8vXOTJLTyCNt3NeGO8q1WSXUQRvZ
5kw6n0OoTkZICDDn8xYc6OS8YNvTN15jV7E5Ngcpb+grAAqk87mUH1Lplpt7jxz8sjnvQQuiqQD/
aHlV2V0LnefjFpLgdp8Z5KBgG/U6cHhFj2S9zmoPLfk+6aga0aKzjz+JNcqABtDi44KT0vRJ122e
ZgJT1pC7oBCUtic/WwCnHf1CqzwIbBt6bZjjzPDK2q7Ed5lcaj3yvA2KGCXnR+abxGFT7PmgNH+F
U6DJ3S6ySajaRwMxG+l4WpHj3V2LKgTMN47NFk+6fcUz+6uQT36YQVjTFyDCX0kDmT5J74yTIF5i
MnXoUgYw86YfgNSMzLPo6Foru0d5ZOtUKdhZyxpWfxmG47eWbhjXrLchRXEf3x2bIDOeurgENL5U
33qWE0VGYxoQAWkQhDncqt3ZLrwuPHPNhOpZS6huzTtJIr8GwhMCULofLo+RmebdgNRPTQXMLSU9
GEELihMAwrXX1ptUGB/63oJHhDQ6Qa6RtJFrFEftTFqxGSCuXI36ff/7rKaY7lBC++6Vw8GhT447
+IKu6QG8cSsDNlXT0/dyFHIncBXlByLfl0Cn+MGwDNRORpaU+Imi5TYq7Kas+gzJPx96siMX7nP5
yiaaCGJMP9Z0GJhrVrMxwrKTn7ghYL/5mYjZK498brKina6kCjVdk4zCeb9g46DT25JBfh7fMKcx
RpNkgnb0nA1IHxIqXLwxmlrb1zhoWG/CR2/liwNSbbOF28KT5qSRSHi+pHr/ND6J7PpphEf1JVxF
qVTbIzLCQC+E5Im4nMF2+eGTwATa/hIuOEU0pcHOadxb0CH4N6ltI/Xz3NdnK+vVGP3TYb6WrTSy
+w6V5FSRlEvWddLM7UpSZyhGkfv3dMjWto2+Gtf3YF5ylHyyblqLyNab12pFqtiOEnThM1NP3dGo
+FkRWgQTfrXzOA9FtlUby4BCnPfsSQZ54KvkGa8rt3LGdVUxjCM+l0R+767VmKc1MW8Te0e8jJ9A
pLfP14XqdfcgBIGoGfQEYBqzbYW5cAyp/PHjqnyfjYwCx0YIwKGra33M8X/7++mAD2YhYPQO3RIt
JNXZvZgit1k7VRfkLC8nXkal3IDe55EXf6rz8tNeR9xOK/scKlZ2usFC38C66hcuS8spSasAt2Fz
WWytPr3DGRYjOr5rACTM/FXyGs2S/zlMN/O74GrhQ0kIp6CI3RjWQu0kVeotvezdmzNZPy2jHe5/
QMQDjN5y/cVZYrdkKtQhceZoC3j89D1NEpx9M/POAkk8dLBLlxxtbeTDyLM2Ol7X4KUIOB6tNX4w
kZ2WjOiv9IkwDqliAWgXY4GE/zihvu6rRTHnPoVmrsKriWASzZ7S5k7KWaA9nQj5wtgZ6RFQGLPH
21BI70R9IvxkC+ArDaABvH1H7mcXc66xDMkhcLWw5nzuImZ75fElRR4vknU68rbjpC7hF+xrZIZP
khp3SVxAvYZLcXXtS81nq5jTG/O3xeDLMOgusNCdtpR4v/6MP0Kc5WyrDTvG/6ijEeTuIliZVWZM
+kggSewWIvNK7f0C4Zjl/A2pIQSu8IVvfP2pgQp4zRY6Xd8Xj1dtR82226aMWZIIGPfs3hCPrOnd
sw5GhK25AJqkS/ussmDAoBV0/TSgFVL83/xXYdi0yn9GnFCB2uc9prVO9yFFtfbjl8InNRRXba7O
OqawImSdL6gcApzs/XAVrEy7wdO1nT0d0fqTgYOrNOuxaj228HFg5jlCN2SG3O2hxXr5TRDRGinO
kn9H+5anoTzDT+mB48ZWXnt5Mu+3/19QqeIL2uF45KwB42r7xMLVlAxIwPPJGMi69tdrscPk3GEj
PjOjhcvGgvMO/Z5AnVjKpfJAN3S4456WdZJECfFSZopagMxDtTJwwjsNCprhm9IDfY+HJyOU9S8v
9H3ymZ5h0u5VuIuyUxpfeah27mFsZWgES2i4976axvQTDyD4a+QUgVkEK1CN9XkAWWDsyIFv7LEQ
pWKS1HzYlWiyajFv6ZjiPLPPDhGtWS/24NHOAdmJVbiqWw1fr3/f2iBziIU9+U0xq06j/UIHg4ut
KkPjrdhrMS/cDkO2zCtxAEkV/LfXGeQJC6sDevEYYZJ+mzTmqn88xPfBgoTOp+2+lIzEvIGWG7YO
YPNzOxWZt8NuPp/J9AHY7h//VVXxFjl09VaOTXj2NP1qX8Fpews/jzufAvVczJiYSts18M3ZdkBS
lFXss51t7wtCbjNDA8ckHErfspZX0nR1Unea4z4GNhl28ULIQETLjP+VTr2bF7w98pIu5t2ScOt0
g4Kfxq9crJWUUZHIxUP4iqUOgsh5ycK8w67+uuumsjPqtqKvI2W6z+vkW3Dqsy/cMUUygUTWfHmq
YJJ9fPwtMte0tZKPdIQvOryNPSD8xDBPkD33c8+M8J+QMGXEbM1oTTu8U+coEyEPf/7/vPX1tPfa
iTpJjbppD9OBCFBz7wOa5n100BQxqVU8LGjXslKqzGp37VZ8C3FYBDM+E0IpBjHVUs+bSIdYhu93
+VnfaiknFNJizimymtjrOjePDbxusRDMds5zW4TmIcr0cwd8B/5iLhfP5MgCnhZWSV37U7rqLuqC
dS9PAm2fUO8FTXNdDtmgHm7kCeAjh7qpPSnydbXEXJUWcHBS5SpV//5Zu0THJmhvCL0yD8AAbDFd
rwMgMbtznerxfrmcmyb3Bj2VnLRd3ztMNMkSaoGtEAK1KxGicwr5VhayXwyipg+pCZ2J1Kp6eFVI
NJeV+5Gw2piV8FSAjY719QdVLTymZyd/0TvoOMRo9BQq4aSUd/61pFGQb20EOhBtz9GfXWbG7uf2
GZjJLRbJ+85IouxRX2ZllR/QL3R8FXQJdAR95llOYnRusJF72EDM88bZ9Tthd5K0o1JZlDOwsIG1
YaRA6AsSX4ZmuyieE4mxN7AmuJ5J1vMpwY+FgN315upXWql7zO3wNlVtpzPO0ExGZ5MhLVSVfZZX
iCCn4ChiCmCJzwWw7YagJiJXk/ekzbKtU3p8N6lqOYdrwdGhBRTZonJMquzXGPIyfpqsIpm5DWDy
QzhVFuKt1WgpfK05ZjwVell2+hTLr4P0KC+im1zpKi5G3d4IfptMUPf0PQHjE00C2HFLsjaJdBp7
IYdKx68QOGbu9gL4T79163U7LCAmNPXzdMguNfk4hLf6c2BnASjDu1Coj4OXaPUXvzkgdw3kHvxZ
EYz0YtctNNMCO13a46z13Nf3qFhhpEuJnxigKPW389bFHU0QE/J6Aze9jf1MFsNBh2K7uhc5WnO/
FjvEsKxzEM+qfSk76gmzBl2WQiHgIsJMGWs3a1mg8nWbjs15oH+U/pPH+zr65s+QFeB3cCHPRcpL
g/GjfLpf3Gbq0lDaGbb/PWz6HK3RTU9GGBc2pEO6QWFazAIDwS0JLbY7f7Ye6fM8fZ5WkPW+7V7k
+/1j++ZVHMtySoGkQjJVggnAEx/Ndmhu1UDLswOOKLegrUJLHki1I84dZAS02izX29xQUGWyhVQH
tS8iE8XotjJnkLencnFCQnutoeCvrBbkPUjniEbniNRHXYPmM3XHoatNKWTHMWCNBQkw3gAVHndf
EaimueDwTOLtCqwLvvaH6EIkKn+1c4cQO5yH2WJ4BQITzysy1Cv5JjYq/eNWgN2gb96fviSOBnAY
7jok70CH0n3hTRrpsnTqC7UpTFXcfDdWE1Wr9Q7/AWGic4t1FgWHKbbNR1pdVxjuLDdadDtW9VRp
MhJox/m224DxoJdtW9V/xXNajC3ZQAu3MP8pzAtos62t/ybjg08XfQBt6i2Jx1WGamMh3rJw73P9
wNOD56WGDxYh2kmlNNtusE1OpBdvUJkWKLCHN/ksg3ynpbULpwJPCv+SdN9s9lO0wljKHZzUAY3L
BDOu1rjM0kci6os4ImS9m3ALuj5AS3q/IAIYoaPsUd2/jawxolIRfJvtdvuLFrabwpBhUlSjcrt+
YqKPA9jHOhX2vGME6e6+rzmqK+MU+X663XwFPnwIPr7hKNbuYEEtfe8UOeduNIUEcHSUI2iUeikG
MMKEVYE9mBDzHSiPcq9fCx6ECYed2+7Y7cymOgYYb3LeaFXfFM+n0SumiYpkukopxbB/gSGr16L9
K+6FRvqsnujr2SnaPKs1Qohd8kS+MWKMrrGHEW/Bn0xhS8GWgf43NhoxicEI+fnyQvYMO0oUiaI9
cXX+oal06gsAzlEmq4/uMB0s96wDNrntopJe/Fi3R4BU9155sED4Jq8Cey3g3sNdHTawU4D+D/GU
VSoaZLrs3hBylNWmzvcCvCP8yvn3PVWz6goeS8+ciPqEYZEJfJ8ldbijwun/HTBjvW0Fg5t204SS
9OWlmUk+mvIDzRp1c3ZFYuM33DMxQZmzj4dO4I6cZIub+gb4jj0L7hANPJsqKJ8Q7I5Elhm7jJR5
W6Xm4CHomIlmqjAkPmdV99Mdefm9NKOugMfOVzUwZkARGohUyD2b3dpMajzgtd5dkRGg3YbxdjjR
nu/Uj9jSPtqf5MXBVCGqOX2sf5PLBNE5leKyu3opcVaMPIFqUh9MaYVxFNSVXUv6/tdWbV2P5Q0S
Cw31PL+Dz3hxIQEwLw5w36HFLTmDEjrrvBUPdiyttoHRvO2GLu5mCS1bpjdGOedhvKoG5wwpIlLe
s/u9dIiVp3yEJhkWr9Sy/+kDZkKFYo9xdvOlKojgHIO5ebDd5K4Xjm0+xbrdU74dPDXIm8993BVV
2XISPLCZMf/uu9Ei5EnMrrN9+UuTgbChKcahyulgz4XZxgD2+7MGOakLGI2ZPP7JCoy07Mmbf89m
v2qBF0nQ3j32VrzqUo3lsfDBDwKQnCzYkhmyc5RWZ0aVCbkMj5XmzzXDl23GuMOXFYVIUXk+qPje
4gSoqt08f1rLeNgaouEukCYYJEJwb5zzAPDszMxiIuyZrsvyzz355+D1x4Qk8VJfyETU1faH3HpN
Zo+369y+lvwbC60/97N0QcwsO1IW76oFPIY1eBQZ+nFsZTe1RfHxBqiKj9ZhPyLFkfKWhhVTYM/5
od1tNEkX39HyRfqImvgrK27jHBseVFKPCiNHFpySRyySgnu8VRIX8KRlauCgEtLT86RYUgAUZl5Z
EH6ZXSLUGVXmoPyc5ANSVl3L16T/LABHMpx5R8kExwQQ8zCW5Oxu310VhNR9yejGOF+EDeQz4Irv
d4wGXZ+LsjDk/EIRTPjNx7V7yS4TT+AMAuHlTvziu31Qs10ybBM+GgUxZw6/aY8oHB/MJqPAA6oV
ZE5SdApzIS2aBsTBjT2qtZZuiCUmSatacAWS9Fb5OGf1cLu/a7WtsGKhA9FcWxQT1PkfAlX8kR1M
SMqpk0EEzVg7EHpZoIGjbM3fCXebSI8ReltZgn9akHRd0TgPiKitO6YVR0aFuh/HyAN+d7+2OrZq
M4qq3XoCWAifAnF7nc4oaxhpVx+05EnXQD23BoyiYTEe7bpMowdXzthERxSyJ2T6+HeaWnFh3ScJ
cSJNfzdVMtpn1m9gnr+HoBXA4G/dywPSYW7K374nvXX8rdlP+LqEGt/HA2jiTIoMRA9QeAjsM9r5
ZnnU3xlPyy7zutzTV/w0pBOPWAoqdZdkDFx+6iDDWFWBrkawGWGo8M9shUoObPMbrfQFHxZ/jTHm
n8M9y5VnkcBc9sLcotmAMJDfP3hyOFPyeQLBXAdp8w0xhU57trXxpOqdiOI3vXMe3yorO7EG1sTA
zxnobr2T1PZnyJstTA1ZItLd5lMDRKKRuVpZQILAIkNAop8DBTWNCTtxTbamOQCh42hesMxUaYXL
hAFlznYkPxzmAJPKM3m7TkfAE5hb20FPqzuiPiGtHMxQZaQIxvb7T/Mo8ClZ+H+gxO80XP17YNJc
P8HZ09m8uMwYi+OiUvYOKPXXR2HRo0PlgCMNE21vwbIgrHcjH9ZNFsnFXLVEuqL5eY6W0Rk5+Zyf
4FEGB4agl/yeSGT7l86ctLcQo7fywDeTxluD3fCvTWWbAooAVa+xOYWqL1rCU6hDHaNG967RDJSb
j+Eyg9vqbEo9ObViANJS8GibkCRG8MlfT4faVh9VjpQE4uKMYOzEJBwsNk2wkvGV6riyRcgqTy2A
IZAMLQsBmqtBpd9VBHn5y8VAul4deFHjjqebFcujX5bGOQsViLDPPYrhB/ceB2zlM9akj3IVhfHB
N6BYDCTaMZNz7j6/BptPJZArhHk5OltqakFOiM+ohiparXvBCrlIEvr91wTPOXFeOxxgvEpJ1rJD
FH008LMd7X3+GvJpNN9D2qaoco98NSsijJxWwhAheF0NiWTPGWwCwHNQdJRVU44X35JpgFSn8f6Q
Sn8WM9lr+YZh2p/dLV3QvGJfTr3Wg21rb/1OI5iOJgP8Ys1iTRg1x7/zbXOY9w/wSL66itzEGCkt
w/Swvzxm9WdjDZrjC/QSJU5AyW/PWbJ6mSCE2bMEgV7Zs5buAtMDS4U1Bfe3cgfxdS/a3G260YBS
mm8G17gaBNz40pzOAt1TWneSTiLUeqB3P4Kpy9q3hwprPjChOw7Nj6YcAIV91pZ2m0xTToMHrW7Y
jFHh2uKX5/V08LsyHRJiaU/m342tAgKw1mELJNvxZvUBYylh1jg28GSP5KpF29otrkkntMnU9w8F
Ibjl15QZ9Yg083IWphj1Ib9SMU5Hutgok5yWSUMphtFX1/Dl1Vg/CZcwZrXl5tKFK9JFQqn3cXh4
0kqI4ls8I6ibV5C0m4QkeCZmlTifw2+lbeCZPi4Y4ZEL4SursqqdUaF7aDBDc5nIdl3z4xXuI13X
qRq4u25mW+zFRIDeaEsr7pwsCZyP7oKzjSmsMh9nZw3iri2np6X+LKX9MXx81+8QIWvqC3PV97un
UlxJFrOhIIff+JsDakOVQmAVQBlQ0HKlY1Ye/DPAW7pWU5KkzU91zOMzyXXJxDvNmrPTWMSk0wrj
rjENxGCPYtIalZZdXjgmn/iSKzJtts4tVYLZ1QUS2OzI0VtpBsgBzGqPQiHKipyBzMoksQ+Wuxjx
aQMXZMM3bRqgCm80gc81kMnszlMgTJJ17cgJu7krVKJdP7nviN971iIY48ugaIuwdgc4uczohs0m
N2cuzTrgaHE9nGg5ZtczAAX6x9xJeqwnkBAR1x+J7kyWIqWWlQiez5YY5M1NwpfkY/7YsUBCM4L+
6+FhRNrtdxW8j6fkpopUhO53Jxvlaf07aYQnJjRzZADaqYmyQMN2xxSV3GSl168Z8ZkmlUY7PvWZ
Ysy3JMf2r7v99DICWMdMqqLcyYhTOIGlBknGrmQU3hRADK8q8gxhdz+q3BS7rx+vspc8R/EaQnUc
yzGW8oUauWjdqAYn3cY6R1oMHIEbQS9ZNNnh/02KCvo4UWXHJ54NUKt5AxnHJ7Tj8mUZkAYWHkGk
P9elurTzb3+4nHrCAwtpzsCIH4nZbiMqpKrxfQraw2rbo5qiqRvJ4pLNLz3zyVSJJsLInQY1z1o4
c3b+uTTlmEfDOJvCqamEuQ746TagRv50/SHsmG0vgvf5Fu6cDabs/rSSf89oJnYkp8PtjZpm6qk3
mnUZONtq0dC9n5e/4qxs1oyLWyY0VDiq9G6LQJwhWnbwwSN2jEgdm3utuEyO0zacCoeG9OFtVR77
qxIhzmimUcYv8AZg02fM/yFMZSNOY6bUTvjq6/B8QZ+Dkk6ppX0PGqes94KRvFs+tlJZ+W3+SFVD
25U1H4WxdNb+RWUTwAJjISP1Cjnxh+rCGUMSTyN3gNp/cmBf8g0RWyVi0y1soBd87FF/NmNInarK
4G7vbGMkeA9kXan/PHChabkj8Wr6FtOyFld2W7ollVExlm1Z9OowGxCC7/uA5422ah3sHFrc0Whi
WdFNquTw+VlVPl8Bh60Tqx/Nuxyoa4Zz+rZt3CKe94R7bTGycPDSS2DgyTbbEqmm9lKAK3oIwpr8
Aj4buEiP2C0VTKEM/7lrUBEZdi3EdNA/wFwl4r/q0ucpD/P2OaFZ5Sf6gtTMJB8j/tNtlnfUevU+
8DM8AX+ACwU54g7Zs8M1/DiE0qbgosOHlj8m2nPUTKl+m3Oxlg6pDbJAYNrCTkgeMp4HXsm3ezNE
lwV+unXgHHkntHzgBPSXkSot6yGw8+JAU1hrnnqSUDtJGFYzeYgI52BvLVAwcmq5F9uJ6OmpQHYQ
2oHi23W7aTNmXIRaSj8FQ3mqsegsXCNH5cSriVOx7x1+EskrfIDRwBtWD2h6w4R5kMdTfraLj8cZ
PrEmT/Z6mh9T0e6VSFzSHxe6ugmN3qSfykAIdupmlweAv9ucqwb24sdZuW+sZz6iBye9anCAUVq5
/hpewY8iy4BfzhNhPL5vNLhalIvvlvwnqLVKnpbcMXtrV3Q7cz0heUlwsBzhF8dUd475tboiusvp
t9dZ9dSo7RK+fCp/ZFrcjxa2T/e4k12JfUO6k297vlBjibbRN/l0X4JSuqjNO8hgI97LZwVLlfmm
SZ0AWEAwqhVsb+qL470RqfBstZwmoRkrY1LGTh85WFdTxt9wKiunG9CuIfF/I2cgAwsU9NnTXryu
ZjE7gxl1QmCG1ov9SqxeQNh/DpUwSd9eUoNu0pz9UL5Ubd3Zo3G2SVrIw2a/KSLYUyQynNRRuugK
19wFDm5XNz33NKueYlJe17j8vu8/iJ2eKU3QDNV0cn90a0gQ+eKVf3/IPDehlxUe5jgojdgqNC/2
mjRj+MEq6k+Ypfv+065jHwfRNFOdULGeDCQWxgiCdgHDMDMkf2p8wzDtt6D3zPAhALXtsC/BqRx1
kqak8oPd1I476cOkYpYUyLxupcx7gWpujBqhsoFoLNdXC9i4D4oSAD5ErMb/JfTLWxpUcIuo9eaw
IpnHDI2wMlXGoautKT6UPFpQW3CZFjTiOAnVsXHmQITd+HRQ77MTkIxx+m69oVo/P60g7FgHjb7b
twqgU6IX7hrd/eBPQoyOn23SMQ8Jai/T4pzMe853rXGrcSgC69z9bA4yj1QsQfPDBvlHdlcBZpCC
q/Xi2EezpQabdKyarZMidLa6SmKbZXlOYauvjyMkJSd4eUrcqS7rQe7H8Qgy150ogf4kqk1CLqBB
iib09PuY9G7u+sxCJ1UVlji2DnIceBtEIByEBystd6xUEbUYXuzVAM0axz9Ra9usOVVgiXhznD/T
+rc6E11z/Li6ciUbcqvQVAYFMKQ7gvSrAQ81rYRiHyqxhrzBaMmRgUmM38TSs/emIa3Edg+HEKSD
r2aCNylgbRynxHclRNiEXxU/3z16tWcukYcJScoz7SuffTdQZnwEw3MHOZfz2+1D4Rt1cszvgYW2
jDt9iaPBniA7y0h9v1+AjQC8mT4aPxI4XMmHsOQeM8ky2WBwzBUgTonTslnBDlkJ0+9lJRfFsRKu
j7A/o2HlgNCvBZ9KiFIS6eTIJopeXmKqS8VBN0k/U4XgAVCXhVdsVpaMEd/xYGoBuW/6VWzq6TMO
qoxDtrNqUmUv2fubvJ4HOnYtq2hLPIzAeenil7VGi8umSPvvkytUOeGCtr+SL9/GATN5SDJQaTV3
7wSCZki68UAjwQsIrmivmMXvH1X5X/MgVWs2Owec/L+56gEcCyKC8up8PbZAs2UOX10IlaV6rDoa
YXGhbRkM08Rp7m9Eb0uHXlVa6A1efAvudMzv1NM9NOwvtKxjHqcmu+YylbiY68XXLc8T1VeCmslv
mTsve6eVlC29kNK63eBMNderRSxkTHO22OFG540zfiRCNMPBpU52IhraQolU8/NlgOb0ZGorvu7B
YeYbwR7/yE0z1JzjNbut5z3QCh/VU6pxJT4+H9a7VVqz5QqzrAOMj1advUCtxKLg8XDKTL4bgr96
rSKgufaxVrUa96ND9gLagI3YelkiklAU2C751cM1s3Q6sthKmsoaPtv+oiUrJFOGBKO9iAWoP2/+
ibuP7nkw0VsRaKLEv5RVRS/1p1wKSHeZ/5ZLlNvwKVkre8gKv5zlCxGBOcyAIw7SJfeyuuSxSIo7
OTI0PJwLuZkU0mZWIOxHulZ459HtVB39TUOGbpPhToFqgqGthTxBq6yn0KcVdJyk5fX3pSE84AAL
UYCVl0QsGyH2W/1ooG4KuEak3BYJ/KPVqzwakiI7TSNDeE+nyQy+35zFbvRgyroKsKRuh0ulTaL6
XHyPZ7nE51JldNqquD1M4BWsbWHqWAdFqvq4z3NoPrZBpXbcbjLPCPkPu1HsSSsDuLs/tDWS0sg6
Ltv75GqaGl5HyPQ8SzV+HQv4IwjO28j5xRImzjkGi8tkptuGvVbWWp479smcKMtjADh9B/85xxwy
bHozt5anK3euICWP76fVnUV06f02HF1ILTQSgnjOfsyfrpc+zlMGl+M2cZecsuPeGQVttMIomYhW
z2SljhBuJXOGGVfFu0qlx2zscdlFxLoGRHc0GRR6jh02C2VJR4rz8vFC570pN5O23D/UcMAu0V1Z
rXghg3vFF6JlA7YWHaofb8vRH70yuztDTya1Y2tIAkshaVZxgzXnqdsZ5YH+2DJ+XDVD+0xQ4UA9
ysOSAjfUhxk4Edy+DRO9rCQaCqGebJKiz16i2cwSvkqflKB1Ke2QVlBDOFUldXY49LPN+nz+wB5l
A4XQCF8P81NANakg3Obuk1+XlHBNEpqPLfJZaFy0qYv0N2NQ75hiPvzxPCLN+doAFwp4qSDaKBQs
VHZvFzYDg1QCymZZdR/2Xcf+Fi5tbc4/XdC9qVmYDoIypTPSlFCFOQrlW/v6m98/Yz6NUDRtkZrP
ry/+qT9mg6KxIRB/oGvFQzmUe6SqOrSVV4l2jO8fz4ohS1AdssW2q/EM2e5fO7/yK8sr23CNoELb
N/sqcfl+hKbmpS1DLC1u/u54aY/8zn5y0a1Y0tIyfpXKWGgHBL/6cvXwbI3chq2IFYm5aYz17FDj
QjP9uA7aGxU6cQlqEEZjcsctbBzP8Nhpcqe6yHHo6E3eZES3M24feHNM9QMDVDNHpCBar3ZUFJjL
Hfszj6Bc1GbIwA6o6HZh5V3egiK3690Vfml6SaySkj9ZXZ+9Ja028ToCO5nWiPds7u+nb7fDrQXD
WMHPMVCm1LKm8t/GE4hgO+/vJ3Ox152WdmLa02Cwu6Nh5Y8C6feTHbKCf+TO/Thu8FTP7CANHjJX
r+tyI4xxX0l6kuhBrCDCDwyHg1/asJEOGgczEuAxMtL59oejQPnRQMOKAIYcgiDG6FPEdunxTUMO
LIquQCmZC5WsrnprUarjqIVI9neyCydB4cKXFiYd5JBh5cONPCBwZoUrzWEq/qGahCoBuRmRekhh
g/sDt3b88VA+rup3Lzya8QGkupfXSo8tChmSPOT+dSqbtAJxiqhbf53ZlyZXPXlWWKdHVriDIe1w
BHIVuuOksMPCaSGozLx2I/VhxDUFvtIe2PJd22gN+GVHGmSHuwOX82KrPy7gyirqRO1fzhvdGk10
aJJCFUDLm377+0BjhIDR8CO52tWZdbLPDrLWL+tW9FN0MTG1gcx2rxjy4hIe83s4CqIgjpsehUeC
LkAqdHKU+BtqLE4nW1a3MhSi/0bpzIHm28l4KBONpZOHZ+K2Rl17mebY9XL7KecixyzO3nETY2Ae
d6YxjzlzqZ28zVebO7X+Usr5rbL8NC1eEwuaUMTAgivnnPNW/TaGOxsRBos5bDijZKXZK1nFlOTH
J3EuDdzo0KOPsQrJ/kS1rUOoq5/frehhdU4pwHIlS7QBDtV7NEOH+6smv41c4avLbMiolt4XJq5Q
Ues2S/VvNudftfVTId+sWcpHuUm71fD6QMavPKfPK7MqxA8H/oZzjmmeu/cJbUGDT9VEsguuIsya
DMSqIxGm/nRqcITkyoZvyeF9x6QFEnKnYq8L9yWv6RlizLWGUOmZyWwK2++3crNAsBW1l1Ar++MH
NbhG3OtipOCymON4Yx673hNzbTieV5WwSPyJU7WF/KR9fe/axkjwMjKapPbS76N9qQFYdKfs3yAd
oYOdHwQSQWlIvTrAAAQaeQyELn+Me3/q62b/z1CuvQhGs6ws43RFGvTWhDzuED0AAqIwW4LtNOQh
laGuR0wpv+xNNxfCWbD6HZw1/I4poNPzEFkOd1jOixuxfNIx8CET4MeQvYVTA24Do3v7oZ+VDnXM
9SPPJg/9mqbT1D8LfwjxJXNo62Z+ctdVwfRLlwKVZIMkYHJplR6Z0MzvlneAN3XrhhFNsaXmX91E
y6Ja4CdVKWGUWgXCB+Gd3tPnJD4BZSheZJ4wEVMPay+JDk7K1e3Wng4C0WCFe2wTKESSEb/rQr06
dnXohx+vEAnFcNGi1YDESVtmCLvMMk2Epl7nQ0j4px+QTknDnudeZAjFuNrVm5YRC5tWYhUBKSCW
c+enbcaizCRP4X/LuBtAemTku6ZX9iFYUpZK5e5ClkfSxs/7ATNb0pJqc/qPTzK6znAgzxqSO58b
YvSNJPwlWZ+upCkWyxZimwV6EhUcqiBpNEG01QtDUdM0UbP4YWVgmftf7g/1ClyKmvA7dWsckyQF
LCr+4kfPhJFOWGzNxyFD5AuHk/5z3RZM0fnPPk8uunLCorfZcJZ5AEKxXqlwBnIipIJBrxxLpIp1
ULQS1MIeawVictUewgtd4nEHIAhi1IErjZ1/adC2Xavxe3qNe7YIFOfHjdUWdX2bMZ+PTGjBuf4B
ARWN6pZU/UA3hN99U+Rv3UmF/bDLFz+5OVtAo39qfOwemS5HtykMlXt/YAQbrfIFoDhaDLegFHfQ
nVQGbwMOA01XN5Dy3tLDwXZA3088+/2z/GHdj0SikZCISyq+cbIbiPNS4ZE1nt3QkZIL8eHpkGWJ
I4Jzh642X6weVvO6ijcTXAkzqY9il4hT/Hfj47ZBNmlBhXKfeurGdD/DzxZCME+fAABAuFYgSS0i
hkGWy+sWZ8DBtS9imr1TBG5xxz9QVLIMh/QTmKAmDrmW/hqV30dBufwNWr6YHLr9XrmFkCGtCs+R
5PYXU5LZewDv84/BAL3yAaXtA19Lx9y8BVZ2r4+uuV6J2niIYaPZ8nj46/He3WPyayu2VCrVIg5m
GGw3E0DSqAOWDFg5tf/VYdRpVpQcrIq6winRKdZi7RKY3YFbXhK6JYsr2uURZimRTel79y0OhCRC
KUjQYxdy9hAaHX08pMUqMoTYaaHVuQNpou1jQsp+q7hKwxSWncfePTDqcoAEk5h7qinAgJqnkl60
djc4v0mAgf0hhxDtokeySbBORtdl8CSLd7CRA6hp83KmSIgyvCvPDeA1Y4+PLthIoev+fT9p7MC7
pud6c//qk6kYQPTKdxiozbxy9QyrohXGTar5gjp7Ao1Qf6IbLEwPUA+pCwKy1i4F3vaCAXjzFLFb
gGEUCIP5mK2HWOygQhHm/AJa6zDigUgvpK+1CiSjZoqnKGIqawCthuVLqf6i64f5SQ0LUoV3HIp0
fwvwWoBHXSsgz4Xg7xXV6XU/7usuQwqPgb2U5ca4thM5wgOHmxbT9AySXFTccZyEzquUgmpVOqIZ
zkrtgKaR8+fstM+jAEi3Q3yd3JBhrWS13U62GT7CRmsTQVCgmqd6IkzW1XycCNbwM650Q28TGcH/
jjj/n9aC5OVnLtWuz35UWdKiDN/MECQmxcZ+CrYsU6uHk1wqindf4swYOMBLrbmM/ctgWFC1TORn
OGgkiEvXRXV1KMVF4rjijh2x0+BvaRsI5Lwad92BVP8Id9M/pkNX7csvSDx8OSA03kaPIw1/hjrV
3De/5busR1mCoyBGIVCnMR9owlxeAoMoLtjTBdeW29Sbf65UmmNaCFTFkQyCcOHG4Sp7zvRJeZQw
rAsWX6at/gfR+ZJFAGptdthCJPLiE6ojxuPtuVnoRcB5Ptd5Mlncbei6osOOhY8cDsGRa1jnH1tM
+FlkTPfwBJQ8x9Cr5iIrMlX6qLfbDHSfyCd+OcNUnNMAXry97uAAIrYiYqJJXylhh062d2qeLvkL
/5YsVDWozDi0WA4d7ORqBan2cItFzlYrTUVDYlZGOKuZ66lbrwbSdCntArjeO70YLaSs6JbOPazv
9bf+GQwjz+V3cGe9NO/Lzk/250np8F1knV3TMjfuqSamdC/8A3dAV6x7wx63+udbRdidl/GI4XQg
+VADVKXf6XcWQRO/zebKizh1XJMEBD/rzdXMj0LPDI+oZHZz4ucY+QATdjYfr3c35qX6OktJ2Y5H
lZ7RUzCgo2AQFtPhXGFpIuJm+p7bmMvA+aJufYmBoYjhC3onUn7jlmxuzlzzEaoODjVl6X2QvykM
c6D2qk/9DKKXuyMQ+XMVx/OTlzZqZqAmMHHohQldgqV1EFKvlATx07oJjqDt/x/phBxVEe/ZH1DY
bhEwQxZgOlfljfPXtAFxfeXqdyy1Ksm/afz69nnBuictB2JJQBm+m42bdHs/DcixvIGeuPFKhEwn
mRwJitcuOXjbpM6AVqXPKPuY5ZTGHC6cpgDe0v4LosFLbXwQIGhCLZth4JIkkPw9Dnm9R9INFQeX
E6ZwORG90l3lGX/+LZuI2BISGdny2Xaq3RbttWHxA7lxDrRrjQILYWgLCI6tuNo4XDnx5R47nB0C
y2bta+ct7whiZ41q0jji4qWa7BmcFeq5ekfA7pEy+KtZ6OI3clemb1qTg2QDY+5gQxJVPPwNXk2Z
0twz9ZQZusHC/wJeJCnAVGt9oMyM8oGKehizYJcGcKQF6pX9vg7ovhpzpnNd6TD5HgZyKHyGwj6T
4/NVIPd1zkFgioxdVr0NLLQOJRVIwP3r4hCwu8Bk6TINcVE+sVSqafJ7cvegHemd8HxmBi24jC22
fwEMbixMaM+2J3B3qkwWnGxfJIL8KsSiUNQkj9OjHyoOq49wnsSJ6+d+7KPNRmkIfZAB0KQW7lBb
5IwO80azsnv4tIp41dK07p3ZEaRRy4eiGNjrqa6jL20JqfyFLkI8jsdl+e39nRK/hpIVmUUPNfRZ
fTSTKjajJ5++avcnwd0empo7b92KJIToKrgU5wEtkfEzLwRuXMm2ce3Of8fbYmJh/AW3JuxUhlzn
e2wcVX3UpSA2Nq8VNZq6UGo2YkpznVq7wpKC05AQdjLyfimj4cCAdx+rfjn8j5ECNMmEvIXhBB03
v5F7nKeRvfx0vcwivWcP0XzFlTEeMdKCPs+dP35SOx0Zs2Hz8gay7KhcFHVkHNJUblzDGb1tzqPS
TQ+1T/HwRRNnW6Ja2s+Ztj/+7m8xCoyjQB3WsXowwT228CAz8ksOU54Zev7gB+yOIq63XteInEVH
JJ6wow7MOj4OpesNkCmc0rqfzvQHPL3Jc+EpmOab/3EcoKdlErKoDEXPqzpUD1kg0u8/pqkRgBFz
NUuK9WPAvaSQxVXG8RcZGBxS3N3BYELs0Q17aoQpbxt1WcpYuq4LIcTImJcrcVDhoCjbvUEQLCDh
kISkXg+jxqq9VB0RRAkaYVKjj3YiZqfYV07SBIy24SaZg64TsI08Zd9AA7ebpRXENiOnSFdyf/6Y
oSMffsoPRDe5K0XBepBm+n2xtLq3QKqHkcgepZkkw2WpR4iBv6g+TE6CQxQOEZw4sDx5YS+epFJr
BMr9D5ODXEQYwWgvrx8Kye0ViWTmk8F5udMonuLxIwaxatqIzzDnSQAIKD503LnbeOdsxPTbJHbM
QDdH+i1k5X1/C8kZvu1kQeASi7HcN65pcaqXSM2aiOZ4AJAVJyZclz4OKbZ93WkHyjvur+pkg4Ie
ae9fMqGSmavO6pllwwO1Dl1hG5bYn1pJfpUq2Xm2q9enV/+KPgqiKwFS3AcYHpFiF1o2bAIsFuRn
XDjm2q4Y/G/jZdX7XjrBDW0dWMi/2i+aMwHRLRKG4+fskruakTOIxmRCFnz59F/Fa4kZGnvqToGY
2NSz3bxq1dhyTNr9trV95FnhKiMrfUJt9ow3RE8RupDWMGn0aUqZ4gKMmnFPmIJ3/25s5XQL3iFJ
bBc/GXACu2cLpt84FC3TKbXLr1M5nFu2RiBFKVW1YAZY70WF7ulqhHizCrP3MBmy4ItABaT+DOcn
WjEQNQC1cPvs2TzoGR4eHrT+RioBBJS1soRuOkkV7P6f0MLNAdXJuikPvCWfB8PprZ9iUoi7rLbN
Z++DNDz5k7eM+Wn8UcPnwozREGAZmjg7gATBoX5XBM50BZJ+VC+NqL0wEtdLMOFgUpwOpAX3UL8C
fYokjKKE1mmlNDw+v4QyZ+cjMDB0alcEPkFVvCzRiRXxvzrhAlPec/N3+6n+Ep4yYZoIlLB9dAMh
qO6VXk6hgt8y6QtzB+86Oqo/y7zW152wj8vcU309MHuYpZE774aeTycoIfkOF48Ir6zDEly6tOJ5
zq+OWlMdrp18QW5L4TgzmhyDRlrra8snAKQtYQhbTJOz+9d9EkxxVVOc0ogBK0Ou8c/pWT64SNNq
36Z1aBIZgRqxxTss+P0/dG5BqE/DfTdlh0HRkNX87BfYEKdSu4T4v2FxSnM/qA42ExCtM+QVRFuO
8l4OclxNZUz0g+HZguW9TvXqn/EVVp3X0JVbRWgQeJVmbaFeCKocnBjNtEWnDW2E/gnMsZogkDD3
Va4tEw6voFyY+07MbEqNAyx3WkSfBfU8u0XTQJOb2qZPYGjYZzEqFHPeOZ1TvtlqxWWTK2SIZ3fb
vUbc2jGZkHuLOVBSUKtO/bnb+v4l9dESYFh5TC1vgwRE2zITafyJHr9njUsMeEMpuB9RJusjAEGM
HYDRjpIO/SgIFZZiRf6QDQeQBmanY333by5MT3G7AlgcB4w/P6gW3YMQgZTtfnaZIEsZPTh7aqql
jPrl5b1o4KiO5+UgqMeYPm7/Xf4OtMPhgh1uFtHQrEHZ23jBqETsgoFrTZWS7XT7CpsmAGIMkjS8
13WeDJGgLskkLPQr45OY+1+q1r6MsZ0x7ReZz7+FKQkQ/atbLnefJWS5az/bYYBrDhU3ya+D8Z9Y
aploJskPlN5EREMoOoRu8YHHOfZUgzar712XexzDI/hmYB04BnUyohaPamqnsFYk0mVKQFi5IWpm
9G9kdcWoLxrFdzfF/utKJ3oKdSGbfYJjFOUh9oRvPFrqO2sv46p7Knq7qxx7caSm9kkpblmzCau8
1osGrRy3zBhwsZqvfTZcmMmOa33+RBYyZKDmblqdsyy0GY1HNcCicI/nTMQiHsVh4LOSRGIvkivi
/WSzAppiQr+WAqts1xVLpGlF2yLMMGAt2Ap3ICfSM11wOEeAvEHvGVD9mRKRDH52QNNm178XMFMp
o2oqsoi7iNOVaoVimuEI/mP/7LkCsGrgEfWOjvsZjLLrk48RR81CjFousPIPa7i8YC4jlms/6i2l
UjukhvqdwK7XjBvShi3JEMu8kORRaO/7NxmrH/GRFxYGPliuDyBLN24/EDTU4VbJjyGIk3gcVawN
w28kkLxyprv8Ee+yZ4iCVdvjH2SxpZZdEg8v7XrNrrYiyjWppwJwQT5Z0+DIQNRg6ufYLqceHMG3
8FtIKJSmrqQpICEYTpotfpv1D3xD21K9pVZe2WG8gEHenLGtyaASJXP4ay4AfuKpK92JaYA2ht7n
oWuViA0SrDpbA7fFzqoE/DLLvS5X9T0VnFP3Tz+UksfdwJimdU7hQpPagSMxuWsyK4ulA+3z8ldg
ouTfQvRrrkuDnnDuK1vv6qnzlvMqjWd0F028XWUO/cLxNtbrsFjcriaifxmVWNob6K6ckvOGujr9
wK5F1M5syvw1mVtOrqKoAFfnd2kGAgynj81pdG3Cu5/dDe8HneetZOoS+NV7lJiJNryA468kWM4S
0pdhyM2qt26k8FlIWS97hqlqtiaWcmJASo7ZO1eIK57kE4oCyoPiBxfVxURVOYY+dACjM5Yg5j1K
YlqFAq6FnbfWrk3qLyqE+wmlj9GUXeO3YKohHYu5CO0qvMGT4cnaezYp+6pCYFEnLPFIinc/qwvm
Sdeo7Im1PMobk5IAjvodTKVdr+34VBCCg8yna5Uo7ddPCS9pKV3smsW1fTYPH3ihiUqjN4iclKRt
B0Em1Lh6R0j6MWogjxMI6gC5LzchRrA38qpp3xw+t6YD7lZ7gqf971snC3e7VOHMQkP+8vqeKQ5+
oTi2ScU6CGqy4ciFQou3547jj6E7343GXYeN6XmAnRC0paA+BDoz+yqe1uTjuwxTrZ2NxCkaox0X
B86S7Ob4CvzIUKOGJru+CgZXBs7E3p4dCQycgbqdvaKalS36hPti+ZIzpf6L3GkVqHhHcQpHlNL2
0sfl3WgK0xfCdcYMLNpNAa677uTs3ygctJmk0OD17nhcD9AXp13XKlkB6DNARi/kOaZTM8q5i6s7
6L/ByiHIzNa6YUBMkw2pNrm+LNRkuOasU65Jny2UErtvXDQVdN5feJA1UvOSJC9aW69w3FSpCzJ+
R+01lJGBEvfF2gRAlSWrb4oODaijxqK3K5Ryd0q5wkkHsr7YOAz2ERlUtZrd5/RvzmGKKLPpSNhN
13GPq9khsXpbBIdi288oaLHMYtTRPD4Ah5C19syINngoDFeiWURfmFRgPL0CVD1S7DWlwtNxxEFw
MnawqdJnWWNOlfRdQaQ/ZSYohjeW6uNZ4ZsSnCTrlTNfAUEfuQpy3d00seOXygleTM5SjYH0g/Bm
qJ7JQhdtOhz5K2ElPDybzEbTWWsPtP0kQ/e6gGKTSQuC54o7frMKRhtYgE1e17DR9VODBRsJ/4em
RKdNkANyS/HIqp/h5hVDhaq48J5tIgNnBFVLd7hrnV/+xwOlCs7/uaMkWHMs9jthtGQKaMBCfsG1
nayzdhRjjz7oDe4wJcioKdqu7/2SmhXn3HkCd0qyFOQlGsMxRy1RYCzbT5tK1JTMhim+RGJimO7i
ib/Ibwkq40O4q+hr6/poCoIXIlnEFBQKsKvkrjFmDlMAc9408L08fPWImcZpqe61j8v4HOiCzQ8j
ZmB+upT2XBVeY9YDxGGlEfLD3hHaU4UT+McOZZ5+u34/8JwafhLJmZtsxEwpRsI0lsKg4cUCv/NN
4QOyJc9bBEDJLvlnJwEupHsKCl1F2KYD63qnlhcVJwjV7jTzB1XGB+9jLyfFJ/hhp508Jha09+0j
3ZDyYC55P+p4bldNdpbVbrFbtsBSjgmHlWXFDyX2Jw/922iHGrz21i1BwLCE1ig9Heg6f8sVvovA
t/aeznEys/NLAGQQj2KCBHYx+96b6i62SahZ3o7QrHtz/a+H80sFDtu8sc9h6LVQdKn7NGrPjPsG
19D7NfgfubucaSa1jyELUFtDdSD7NruQuMwGtfzlQlQ0n3I7QRlzsGfzA3fyZ2tvMVctzSrA9nBh
WfK8Xvb0eUoUyE0Ij5i55ZVTcMNnN/eonADpxaEy6Pj1E1hgGW9R5j+qWyTVJcfxB4x4G6SLaD6K
BE4hhpnsgpY7Jl2dZ6L4TR9bkwzaUR1Eii687HitZU08AseerQOb8JYwsCSpveKgiZwJkW7pn8/C
1/cSwo4tpzYPT8UG8cc/8YiZWApbu+O9aHJ/bXQq1lJ/aptytpZndov4jay1i/aCaIXZAeozpV8T
BLA4VD7hFBZmuVMHxsLl14bklMltJ/RuUQ6kKcXOV/EE+MCLW3Ol6TVo5C+TDZ/dYslD32y4Lm4Y
YwaPlzWltMyJXOfSrFJmwc5PYR7th/RypTmZbw8G6twUYQ5QiioDxAh6El/mhGiOWafyy5WSZ3f9
H6FwClGnOdPrgi1O+CMYxBLm4muTNHqGsifUT83KjX6aS5p3PcHIzFSULKgNMXxJrvlUnbOde5BF
qqYeQWh4CzCwkEqqqeb+VZdCvZj1NiPfkmhUuF690rpeuRauSL71yzU37csaN6SJwZYzLdFKrpkS
e0J40M9ruCdqmW8OMQ0TpArM3avGOTI3lkpAX+wvLyDbF4NIsUS1isN8lG0ennDuDHgTTb6dayZi
2/GSK1PhI+l7Rbd97niY+tUNhTZf3rg0J9TZeRWehxqaOFmYkKq8X0D9jhR6aOy13uYy3OWeQtN9
dde+H+C8MNVlKwVUQFqUOFb1X1nWJmjmGX7+flHYGzoGCQLQTAxkdMTeFwdSsjq0IBs7sj5h/G41
U0Zl1tv9qU4Ht+57OJCXI0i/e5xocTfPc9VRaXzyz7jo8mfyjCjTv96cnK+1gzeS7/kCQ9L/Mwin
i+j5c2ku4esyjCfCbSkv1c+jm+ajeOdDdn44Uery3K4aIjQEIaG1bER7/alsw6z9kMcMeAB1oofo
eBApVO1E6g9AuhCHOPlHwEG9IfZDAACUJVpU6k8Ti401l8+6qpHSGMmsF4uyVKhFLpIXOXYgl/B4
lIL5Wd+7EjEtAAkESzmM0y6lofAKxalSGsu0mIpcLeDvc3h1LPoMfi1/2pqF0SPtQkbeNyY/z/0I
wopbCC68YQVq7IoEk6zbPM7f8psQ85JqfcZY/VspYJ3U9/SYROA4nQ1wd/agb1O+MkCr0Z1buE6i
kS48oap5GesIRUJPjJmY+KhZ5hLnlPhp8BlsfowzSn0firdt82ug8z5INPqq6OyLGGYHYnN0H5sD
bkHmCpzm7nPUd/TP0mqd4d5jBA2kMiwtMh7/qh0KqKDa7w2WGpX+MayDMXuHFQB2HlPpG2Q6c1/G
MxDdSb2NmK3hlPZO5xBvpSA7Ueyycogh4Rgp5lG5tRLnrCMMqoVYSGZOqyaJKvJsgTKD7RME0/hJ
KrqAZWhTH1E3cP/1phfQykINMHUUME61K4TNexv9A0IzqBQuKNRXRG05oLr4zyCYbYR7YQUAjaUj
2RK3ybNz4YvJ2viImn1tpDOrf4YnVIBRa2oxp7QHtpt0cljxYTopYcxckDgeOwUi6OyNvzRFivIL
M3xZqeeM9EywSrKX244+quHJ7s7SwDJzmNzLFVOZp8JGPJls6vJ32aiwZensuwo/QwLFJp9F8TtU
QOq9Ww2HCnmFVoXASgkWIT2S5YGRV7z63YjcrjRQYks3ZrL1ldFo0PEieM6CzJxivDH/s4qL2vaL
e4oqNP3X8cQrnLVEyx3dmiiDD0Z9UT2dSDF9GjFgEMHccIL9bSEQluPzi1j44KswrtwOBsRoumdg
4TLv2Hd3JdWwJSUpuvA82zBTuhkXfazJ+7BWhvQTVnFFD/gpNPtLlj8pH+rOS6DRQOYbnSb9axyz
RQdFe65q8YKGzVmHnXEa84fHWr9rBnSzjgMI06zRLe+74zebO06bYaXm10NGT3J6phBRNGftrwoR
suOitsaboS34OaWX3I1uzdpejjufA7O9djOoQ1nYzHssHUECOQs2YB4KK2NrGW8Oh0Vsm9DaNSw+
BgqaDERRuXt2GUiSaR6m0dVaEeZb/hIAHIlHINDrl2L3A1/kXhctPurbvounwp5bzT1VUOcBWqiD
EyYFYs8N6pzxVHVsOf2110pdG818rlQPAKjVfz/ZiVGhfPdbEGRplYqqsL8jms7h9rVwxGAMKysa
z3gNqgzJ38dfQyBKAoML0PcdbJ7HyZd56H5uhQi5dncA9LFntWe0KiQis7RNBAgsyR4bC+Xspoay
796V15lJCa/XkiYXjgG/nO7nTL/26srVdwc4xJPb8+NDCSY/xcand0cP6EYsbbsh+i6hkSvOaQa0
E5yn8xV+Liseszwogcg9iNnkvdlCKn58rPR2ZXP0QMpUeMjmOi0FK6IzN0WxFMRMmo3USvxhWVEZ
7Xx55d+AQDYY3M53lXCjoDvlgBhEY+E+fcF4Muo4FeffAGybUlMNYkLFb66OxiQvjLn4zB6DUn0R
wmhrSb2bFvfzHZo6w4E3UQEOGAC0AOd6P3ZdOK5U16y231PDiMuFX8Evd14LlT0mCGticJCA/VZE
ntUidPKGh8rmx3RSO2L34rCL1cy9W5INHkB26G9X5h9BlOw7dHB4IaqjcXeF2HX41fCgR/kG7Jk8
KA4T4T2q2hRdu4pl8j5H5KD3hJs2UNbH0/EdYyYKtbatWnWD1Sj3r2Uwd2J4RaBxZOAsxs9enfLc
C3KtScPwLjnN1B1neM8xwjR50YXbG/ZDx1AnZ3x6k+YN71jV4xFCIYd3NOo1EMELasKqZ0hZJp7O
la3f04MdiGrba6vEtzhx2XEMZS5xOZDesw9EEwaz6X84mwD+PiGd/BSryG0M+BO+hmPAoKDVec5K
TejYy/LdeFFVbNCMzQitNOY+LHROPwDRASRpIEVekpsNxQY6ZStJYgwkUpdmZYkWAg4dbQM1xIkZ
3sJmtrAl/oHqxIi1KBw175YCLWkpWW9JRl3QPL/p15+4N64APJurI/nsV3Z6qY5kI9djqOe45i/I
NICcLs5FlkPkyTJRJs0SOyOGJCeX7XPCu2lMmn2cd0fGCENKlN5UkyC0TBUV5OftxDPjDfmdNEUn
wAfcvbEcxkfKd2XbhRhpsX0AcZnUAozgrdU2RaGECnQ2RK4IIUdc+S+h9tajminkjaEmy4nL2Fhs
4XJ07G1bemqQ/pzmU3bcqGXaioIaOR+Wnu2LZLzxGKtkMtjIVzZMAjV4q+hWVVe8PllWR1cSIZSP
H/UYrfH9k2ceHDMJYQmSE0rpw7R2zxJ9yJh1gNfim0sKQ4HLTZSe51UUW7MHMCafW3mqPDSNSD2c
REjLvvVAFQzknUsBm5ayE20fu++87mUc54b55IMcxpusnTveixOyc2LHnnb+zjQX7Z+ekbpzElR9
8zgtQVbuz8pTNotNAbrkO6am+x9IvvJMwPr7UuhGgs3F/VJIinkH1XdwTX8eBDTA2nMYxtJ8u/Y6
yKBIACVBEb8BzAcdj9ZB59S7IrKl3vjZbR2VP7nkDLQP/0/pT+3Uui964vjQP5RXlpqlSkBXCGpw
6eptzSfPdhBJdLnBoq3Gd1nwop6Ab5wHRSH8Gx6d82qRHycHGB5nQYczmSVlK5LX5f6lFhSCXGqn
oUpussndX+dHParjjQAY4/eLHzVEqkWfB+2m/eKK6qNsRfl1/85S/y9aBvBiA5Lhw5WHYiRuo0pv
8ES5G4cJiuMDeRzAbo5sJR+j0GioK4WqYB7KpMWJ3kfCjanB1pBDztV+HhjCe99ovjl7ZlL0yeWz
98+h4MthHcCCpUWnhqiVVAL0SmxXmkaYYeFuH5CcjgjiLDmrPJvzZKVsHLzDnxJ0YgxKsTChnQEu
q9q4u/Kc71DyHE1aUo/W8zKlunDYqTQQ2EDunHI+cV9i3re2/6mIcojY5TrMLZkWQRTC05yV07o8
fcuokF50j8q4Uur62MgVBn9D1XbL4fb7UM4gp2an+ttk19H9Alie1TT9uJnmfpOECNv+pGX9DZed
qBwY7tcyZG79uY2ehIGa8MSdRzDdIlUKcd5+GyquoiO8z1N+P81IQ+wM+0Avxtz72GDFgBAsnnff
RRgr3t8ffUBybvlWBgr+s99jHpuL4rRmffPeQmp17UX0u8fQNtJbVImRFjB4mUf7CxPofLZ1cfr7
5fdqw0nMGRMQd23w1YLPO7pixlAztQdN5pKvXJa6OZ8b+MsBS5wNG6UQsiaoHkh4p57BnRJE3JMp
guTijzcsvRH/uGzLscS1GRVx36cuBxIpZgwgwKOKtYX04Ql+cEwdCuilwC3Y4gpGkc63wXRF1oAd
Y/GFh1hypG27uP8/24Bo4sm3u41yL681tcyBkEmb0ptwr9DGgWx1wdkjeIzO6phO+WL3eXDs37cP
br92ocIgV9voaZuV2tV8630WqRPwuGPXg5kNdFvqFnxz3ai052YRTjz1awCgokntddJI0KSXvV0w
Ow+UdetNjM4XqrR3jyQ2HikQ/UpdTm+zBF/P895vMJd6iqkk1716AuuMu+kgxSEGsIr/4p/dd339
3uQZ++c2jHtp5qwFYA/uCrl5W8nd8Fv7B8444JZvyEVULsPFZ3PjkJXN0Q/1VhwdEwLjuGJoyqzy
udjHZhqihVjc7hSfmy1Q0r8KzXR3kHTg7ku5vMa53NENNRccTcWtMVf11O2+N0ZKDYo9g2jVz/DB
CGXlysAZP33V+0o7KD53mW/QIqkfPiZCCPmdtdxgwoMQzerD8wp5TZtgUJ7LJKEVWM5tWVFsO7Jx
q7bXMR3ckHg9A4I9qlD/kWUIkLoetbSQfooEx20XcYtIo6jGOv+QGsAPxnW7bT0xd2u1d/ubbSIk
eWVA/HAA7RxG/7pu485DQD/CUI6sMlR4Nd1nqxo7FRhV518fs8FWQapzslpjCrrrGnyYlfbaFC31
EDu+N9VnlNzeZ//Zf4di1Jo5bdu/P4XHMK4KzQZxFI8g6Dk1fSqznpJHJMnhzS9hVdyWqIg2H0hW
yDbd8lw8SckLl1RjcX9mqdcqz7O3dK5Tttk3hHN46haLAokhsEOzINpEhZ2s18OpqgJ3XvVYpmpt
RnQtyhsFYuaRX73fc5RcSD+twFqlrB42yG6gabpre2/WfYOgUzMDkX7UlE+LnqCqMIark+1+pXmM
ohcLvw7WaAWVLBiRAx6fD7FOzwRlwUgnHcF7jQz4thtF38vZgcXzOwy9wcrqMC3/5AUUjVvQpfQ5
aRCjDPrx8XBbWXjHEgl79x4Vmp/FT19SYXRewflU3+dnNgJcFIIEmyyNmiWA31OeXTJH6mfpoceY
gUgS8YCj0XqeWg2p1R9n/XVTaDg4QlOfVAAX3XkfM1MZyDC0U6/bZ0lewJmle1Ktoqfn3dc3d97X
jnDny/Ad2skAK+9NQrWzVj0Z/HEyIkMbcpRpwgptZp1IQGDmU6/lYuG1PZwXZ28OlTIF5pbKq+IQ
2XQgc7uloiGtL4LpgPrWf3AoXe2f9nBhQS+hQNb3ANvW8fcob8MasQ1KnPEaKDbIGT8RfeCUHF/p
L4KHuJlJegddIOMViWNVMbTVuVSFDPCAAtejmM8Ei1PAftna8Og0UYFB4oQby5rF/oYKFna9sTbU
jmgpQ0O7Xok9MqHvTVjLGJyfThtmk0q9MWv44QeJ4h8AK1R9k9BRtJ6BnxYI3LRxau0sRQwaFdRW
7DpeA48hskI/n9vUwWxOi7clqkmosJykghmfpxyYsc/qQRjJY4xOgn4e75dTyr5A8j6jJeizbhoY
gw096J2czo4xdKydeqpF1B0Df2xfV12pRNvYvwAKor07pMjo5tSEDgWBogpVNFloy1mle7deJpkT
ZDYSPYX6WiZBIkYDuCmljBZ7HDWPp8IIJFjY67idQfFLjhUyVZenYv9hypEj/pogW1qOpk7eu4A7
thpE1SC9uB8S7hzgqvrCIeq2bzAxId1Y5TwDQoPXd/n3CLWEte5ZyR5pK1LCmGm01RowmupZXyDf
BTxR/is2zRLE/GPWOk1ycbk5uohYi2rUfJkmpdQEdw8wRr+rnOdAGXx5ZHtENcZbZkS3HWsbQSP1
9Pcox7zgekYy674AyySj1aFxmE0/HgleyWQlH5MeCCm7E0FL1Dc1IzmuOU0G4UW3daBoa1Fab8R+
E3oPJ7Xc2AQ1O469FHeoLqBuAwUDMojmUASWZNm0yQDsa/F+YwvyHfHQztqxTPwxUujYakdwYQJd
n1zMXCxV1ywUwMyG0Xhjc91LybtYa8Oulj2Wul39EAdK0sPPTAHRQvkFHlUHDhWzLiWKcVH99U/J
Mtvw3LquqvNkuQa46f8RjUneTvtHmwADC41Mz7bgbI12yFdfF4OyTMfJoYmuHMnKMyozsmDoy6V8
JjCDy5XcE/3Uw6yhobC74s3bYVORh/72sSfthfCsZOHh+dNRUi6HqhJcQPtULPXOD0QyWmuZr8F8
FTY5/hWlZE0WMTyZ/ig+jZjmZ/KeTXVdGdNkWflEyndz0aF8FwpqyTM1pfipC4Uhvs4fMpb5vZjm
g+9M0zQb8pik6mYbOEtcwrSEk9ZWQFGj0hB5cGzZILGGNGS4zADfAd3cC9piL/DmSUmB9lP59oW6
MRcHaYwo6VzXJbh0vCq199KVCEqrLHXHutjhWza23soRs2MraIKuSiziChQePG1476ZUx3oygCjI
S7vFPO58N84e3BraFN6s8jF31u/vGzdnZiydtBZrO2jKtdr3bj3KdCdu4uWo3rQFx2e6nxeU9jmS
qT3MhUPsh70Yc3KXyWr9eWYMg/Iqh3UEhjoSJWkkNHLuHKvd8ktlXTj6/BzH4v4Ucd4nU41heWn6
XnHUYjpsWx9cKhZMPgN2cVBn7Z6xfBvCZy3aOptf2mUGHbmPJEHaSmJ1AHEEiQhmBi4ahIErJDWd
AJYSguxxWHtkWXo8AjISljIfB55EuwycLdZO1tbJlmPVttVQGFE/q3TZp1tRbuu5ctwDoTDTi69c
KkE4uxTXFnEfXnsyVVwxPdXqmbTi3GrqVBitAqXIyWsxe2yjf8XpyGLnaNM/UhxpkRmMzmS9DoOw
a6Z79oVhNaHogBvZdVGE4iQ1EKIrSyAgtUtm++rks23NFvBpbpkLI6ZPCEzU6lswVp+7bSotxXG4
uuz3G+PwlfXCCPHuYfatQtMRGLoIRj1dXGZ91o8sj6psqaMRgZPkOrX+pwbCxLQyV7lkUhG1wZvz
AkcN1VwUwNArIHsSP/VZbHVQU5fgm0PbcUZrfOdJa32cn08HTRscU2i/IUC4ddYZwlLb/jpI6cjU
tGKCFBO3j876881FUgwekrM4cFQIqo84VprlHT+NKqsP1FTl+zC+bmdtqccwF+uZpdVnA+lHpUBm
Mo9xGTBHFcCKthW3ArLB1JihUIy1ZXLGF63kETzOssXbqde/JchwF1Y/V9R0TdHAzuezSrQ5qCj0
KprDFdQ1hQryUB+hyf7bTFpd324ED0Olgd6Lkw/D2jdNG1AAVR92GSnqg/gbAGQ2v2af/r6OOsit
poYyyvkuCP9PM03t1UuAdp4Z6BoHSpKI4lqDj1EF2D40GSIKP1Q0nFMKa/mWhxxlBSjXbYgcvP4U
JENkAp95C3bGQj8trIK77MKFsq2uQcb1SoNVN9jgNfyIP8kc9tafaRumZ14npbAxCeCLkMvlkLON
Lll2+2t7Nae8Ds1yPXc9trzWEwgdetobLYyNl980huoH26EORs4wk2lT/l2MXaxmY3rwdL3JLBq5
dTDDKVq/XANnBx9+BQiuuF0iBeebXCOYE9b5EtW061GERR0aNZfdVvQGh9ZKxrTkdBjszee0dkUc
XPSdUplCppgCsQFCX1oDgiQ7HUZ6oE0W6C95/W7Pu5N8kLr4KwvWUNffVQNmY3ShF9cSBBGfszXZ
Gluzj6MeSOTctRndVnC54El2kLLHYWl00Hq4Lely/q+jIbsJGAAbWFTlmO7js3nOFK98TiLJgpBg
ZQ3FuvkGI+y8t6SF2YWzMWSZImlRkb0Luz6rccQO9lAsJaernFf/tciHE85bAu+S9BTWgXPJCBvc
04ZaSk6r5XZaAi3nCQRTBEbEquBVOUK794Ar0CaaD076PfeDD1oCCvwapt0NMeJ+zVAAP+ZP0iQ6
9J/0zkKVzAxg3MlywgW0lVDYwsDb1C6F9zgdeRtZ+DAo12x4JMxWc1v2aQg2VQA8P5gUiIMPMepw
EIiVX4suDcl4nfIUZ3STtPdzypxg+5WcSg6/J3rpPgcuhKqqjd7+q7Hac9ZOp+rkPhy5BDnYPVHd
3BqVMccib/kO3EPMdEWq5SxErzYP4hY28fQdFYmfV0Sq7F5IgtcPnsd7qTamL7JwL12sl9XVsCHY
o9p1QYotHB75OjZzhcFBzS1xo4s6iwmwBwUjK25A77w8kRnN4P1dcaTk9hlQ3oamV/x+TzmDM+S8
0R27nbdywnwddJSPhJApZ82tkJ2zXhO87L5icEND179oGZ7hEJha+Ty1uOLOBx+USEzPL7767J4O
B9j7V2ot5iCT2z6/qYL04e+UcfFZTIdTRrdbWwF7CnwFg7IfN0X4dv5woY0gNWSw0Nmkm+KrJIF9
Idf4wlWDU2hDfO78CItpJ5LhX0TSYWriixtr5IZR+oFH9lm+6178xNeSa3hlp050r5u84mMH8HNn
qvECTJD72rYR/wLS2DN7cvNS3eFjMcibGNDrxeqy/dfKRAarMsPexcCFW2IHiQiHbcEezpGQ86FB
DQ8H2E8bJ8pRPXi4PBZY4xwDtiwxbv/j62p8TEzjtFFb9/qAAegY7ETVRfpibcw0LLPM9NETG+r1
dPOwwVo7aqiUMNK4rHI3ijxFAQaEDi30FBg2y5/iEXz+wxuPZKhhwbnG1ibOf5AtkvMs1LUQYxD2
gA4omUGmwLTIpsK9HXJlHYwTy8ruuJUBVbEZP+XxK9o59pcFAC49uK0kSTO4e03IP/Sb6Y3qLdoV
zANyzQWquEXWk3/wVFM/mhdmrdqhc+RBI7xA+44GVPLHrDyjW1y6uU9k2bp+dI4yRJqfo5j2lZG8
gMNkbv7BIIYdhF+YVFhpaA3Zyxw6s5kkc6ZpTLN4wZV0fGjI/wY73fw4tV7F+Dk6uwXAOfmZkiw9
gD0rCw6X6hAJ8Lei4fHdRrXuT+cKw5Jy4pApXilIKtpr7vkwKWyQREehb3J2D0iovjBc1bN+fU2A
tuO6KJ8HX/0xYDAzYAB5vVS40SuQ+aIOOO5KDMttpO4LjoHysJ4ibXLFIUPJPIfPTL53la1Dzxoi
KNDuHOttx3Nm0MUL6HwZ1D/SEg+jRaUc3CvIFkrh+b/KDlTkZNMHFOViIMGl0tZ6zgiokY029Urp
6C+seeAaBmLwZAL+pmR88NRkkwqDqy1hOy1t666A8VugpoUkRc/DT8BEvFr+wax/KLJPZ8Uczo1j
Q+EQ9dbXFfSV3+h11k6fCryweLyZnqRYafMKVX9yrJvdA+IFQG9CZVWT43ceKPZ2lEBuj34pU6l+
ZKkrCwIuwtbrdf8jLER3uYesXpFh5Awglk+AMA0trY2CVyK50MLio99jsQrzRj+S3Hy4x+I4YFtj
YrXToOvKF1vRVr06pzp+J4f2UXzLmteVELGXjOF7kmLD/aK9vWSNHgOL1iysfq7t3RtnGmtliaYu
DAZXL5fCLbdyuUv96OivEMrAOCmSTRCIs15zpNs6QVLgfJGlqSyyuOpkbC/wyM5FeGrZFGMRnnhF
3oDYsJRMiLQlXenGoC3dsXoeAkjAgbNpH+q1xnkuh7NgVe0UxFlqh6ZofjxfrMei1l0JDve6HLKF
3J/a2CZ6zCH8vG+DbnCLcHapwkAH6fHxt7MfMOe0jFsEhfz8ZXyF6ceiyVpd4nQEiVwJaM9107g6
02iqh/zqV3a9KmYW7L1L8P/yarCByuyj0VKt3DuhYdWfykcfLGwuB804SgGq6gJPgpUm4XsrgLQK
BmT18ks3BksQYZFn3+aImz+UYmg6KOp4wJ/CMW7lE+iCynqhH+LlMYF2j2IGsabH7b8ioLJN/97Q
lPZTLvNFnMO3tZSsTZV9WB59N7K9rgjLrkB3nnpNAZojRiyEI9dr5jjLO6jJNEAiGp4Vg7C9BuX5
tv/6p2m7PGnim772LBdzRgm73cxXA+8MqKr3goOOu0xCyI1D9TB0pVzVBEXOfL37WDjYjB8/y/6J
X9UeM33aJrsXikDHw80HGDpGFlJoLFJEp3FFRR/Efn5lZxxrpR/J9blp+UvDgNpjWerpsljilHV9
xhPu9HDZq9kwESpgt9be6qhuQ8q7JCHMb9CkByTUAPBtC9HmtmJ4rtS+EZlGVaUzhWChCR9OSjYP
k7oZpy8uqcpdIftmfwBZ43d2VoaLhftiinnxciyGYOEzZhiD2Uvos0JyOyDcVQlCG8VCyO/InZYE
DqzycTwg/BqZCoi0AP7H7Xitva3RtCbe88XvRb56p0g9ZP54ketqYpThqHBxxY4mlVAJR0K8dYZs
ikgK2tW27panqTYh8ix+d9lvFzhfYanuL4fnCdraj/9cKFETxYWtEwlV6EoNf26rq9XdS1ByXBEe
JTH778WWxuzSBUeWocBZOtm9iR7VGXKoLrHAPLt9WK9G/h0I6osuNXR1/ctuXf5V1CSsK+EjTwcQ
fN17YTuLNeI1JYL0CuZ932YrWqmKgAPUN0FK8mZRepVncM3kHKTPnKsvf0qOIt7VeZV2pWNzDYba
pyOBePefDEcI0sXY2j+C+8mjb7UN4hQcZTktMhzodR+zCQXBzSSrvqRCz2haSi5Y2QiE5PnGgzf0
Au28H7A0wLh0OXQk1heS36bwuTAxe1NqFEKk0afBmZE1j1i1Ojg/nhBPOCf8xMzlvT8gtWvty5xH
y0jxHoVjAeHIVW6+4OS8AWGlyeGxYgWsQeFti2ZGJz8gMTqN0QOsk2R2AZiXF420lOjqblHQcTHL
kESAYfA4zsWlGC/6s5RB8LCDywSgIfsfI5yW+RDFX6UAsMWZL+A0wOh+5kVGQ9D/LlzFNf9dS2fC
M4NjWl4uYzobWLCWO4qmew+7h4owrKzKClRT6/8kP1TPlXt/oA8S+4WMby5vR/qrW5Dg+ustIyzb
INRUq6bo51u2qjSBvHfYKvg+dOfimhBppQ1EvTjvTISZ2C6ZJ+a44ff1VcQo/Jf8+/yOqy9B4nOC
UCwEDx3Ym3Ct4OuWBqvQzldTsKjgs+tmwrM3IYXSWTVPLCVrjyB1r9iqvZCvu/0UeAWKNJEKFMJr
KNZCzEyre60SnfC6fIXZGtZNVFkRjuCSJvL4qHop1xjYniHcxPBz5dPWkDNAa/6L7XDhikVnXLb7
heET+E5HYgTNsn2Mz9qnXu25oM+UFbz4hKDRy6MqRz5L4NLOCLllFNsmlzlmTLruhoADovSKbrCm
+2LIyRCMT+fT0Jj+2e+3cqnEEjZ4zbW4UL3BuKep0KwsIW7i9XmmPgYJpSWs5GI2G4LfRKJ2UY0S
B5uR2Y4Kye9YM0xOyTIVrwR+a7Qg11x63tdiuiK3llZbCmTIyatY6Lz1HM8W1N9nbklavetl7iH/
vduRtZ4bkCQ6jywZRhyEJBUFOpb1SCUCK0gDcnVvPUL0cAwrEpD7ZTXHI6Yix6kXg5yd+ztplVaq
28nqrc5uGJpZzccvrBYc8qOZ54bKb4wtpFXCocO4k7FFShIJs7AfSEVC7vq8koAN21ol5d52uxa8
Jh1ixW7m8GKun+cS8NL9090dRn9FIslH9gvXJ74m0tQTVC4xB8+HyyI2rOXU2nGl1FjuuLivhZk1
H50JOAxwYk0LFJEkxz5rBMSWSMBAacOGWt50cXVSf8iLf+XFXoafuJgJLYO6mixpa2fFtrbEBl/R
F3uUqfsgjWP/O5tRtvSAIgpXQY99ga1SbbtfOPl+0/17GVknJW3TjstvMiLdsaUQAgqAPlMG5JMc
qBv+/kdm2AoNrnqZVZX2upxEspFMBItEFkZEiC4pfXAMHQZJRYKpV/Ez3SORTzWW/QqziMBtf5kN
gvFrN53jUnvXs2R3Mq15xWi3rlNmEpRSbbLYQDZRwceKZSi/LwPVl6mkup9O2P7DePHaVxi+lSlO
enXdjuftsGEwCCcgS0Y/tYAphto6hq6YlZBiZ7iMOUD7OWe/9hkmqqo9nc6tV+lByDWyuxkMi8as
L1S2cRVnStV7LAhl0B283y3t3Rluz5mFALtJJ0rsnmC4aCDdCiHr9fLrm8+WvoJXv6ULNlVHtszD
1VX8+w2hzwoMQJsJK3ZGJnL30A2o+DXGDt0pOqXA7akPGMgKna5JMEMkXtoE8/jPwHYxH187sRo5
5P5eKUMlR3JK23dDDR7AydQSRqmf05QezFKPgnLsx0oICvLwrheubA9GtyMvyvYO2EEupEDdtLIB
RdHrT2i377Fz3mcJBgODMzX9HKHDYsYXdKTuVZM7B4EnP7CIutfIeD6zjRfY8Hm04kuWcmxA4MHV
nDAYwiEWgwQdk8LyQjBxmrCUp5xvBvrFxhqjpEKMQg4LjlaQUzPn5v/Bst0AOVlRf51k/xisnHxM
Oya0NDkgoLcPlkJ7MRnwcpTA2730qXvgdxXQHLgxc0DYSPFx8oIuGLwc2Q08746hYRl0S9YInFX4
FXz7SmdE06bFPuQ7bhYoDi4I0eU4SrRFcb7wu9pHqON8OC8myYPLJ2qou+76O5ExQet9Cp7p65y+
X40x5lGUDwla1J/aFivLSYabXVHBPs39CLiuPuQo84WWItK0GVwBz+KJy6OTSxEsanm96v9YwqY4
3JucfTZI28buGyHyPh6JA/PCHDZ8Kxfnof89WGmqE2kTRkixvjb9CUL6GeD5f4MCvXWjbZuzYJeM
hBtlVkPH+cRDYpmGY5quj9OSAjdH3JDepxxRAWIClNXnCEWCJzCCTFa3+TEmK6gq6LyfMLCx875m
akkXNyO4NQzMAy4UEme4+JyDvo9Y0Rce3AaAvp5KkE7Y/GAOWChH8O6gCef4U0pjx75c9CHwFfQp
q0pUiIK1Cth+WcQWP/4mU1cZa0WzkD8NZ+hI/j5k7OBqr2G6yc7vjs3LzR7XUdIt0E6H5KDOiwTG
pVMu9goT+uldtXf2VGIjeziGZpDi7VT2k/JG0cWRlRpoPntjOVSYUmKGfE2wN/Ceg3pxSiqvs/hy
Zhdw510WyTQ6WcpDTzxTE17GfjpOFCtobIZ1NTh9XbbTiBuw3WBEHhj0AifHXumRPvGux4Lm/zj3
0WJqNj2fUDac0wCr+h2ar23Htz5SpJjEUYgRVaOIWY9Bf7/kROuBdn0QF8qvijPjinS0Vn4eTkOn
AOhGTvesEtyYBy3K4FJL+YpjcqIhWTd6Ogo/uK0HA0daPw3x1Znp3JJM5tzazNrvVABKEkvCIebf
2VGeDV0gv7mI/rhTQLPCbfgxg/2F+Ch1Zw5H24SDAlTR0S99hVIsl19eMoop6Y/4CsIl/Km+MVPe
hLbsGtQ+V5OUqUGmFFTJxMR6jeVkUIkM+/PSC2TkeUDQXZfnm6W9jCrNHHR2/gbVW3POMrbezyps
QFa44NdKWaEjSKWrhgHcGATfJaQNBHtn591T8f5Ivju6RlK+K/3gyVJ3YLRFQXc73BLWWc5vXo2Z
jktsRQSBRR6WgDvsXl617WhCL3nfyPQwY/+Lz8LD5UR7Ap/dclGT4zdDYIsdPnmiX5kxfO0eFAd0
ssP8w1t/ef0bqiUNqb1tavEzO10pogIbfdIaTiszorre/cBLTSWtVmWdPhGy4GX253rYPKnVTvNu
IOnDMMEUZV78GexlYQ9U5jK5do3eTARnRM3l2vPL4o4NO5oiond6E5iTNkV+jdsXM2Nry1z6Hb/X
9CtpP8LMwc8Y0a/3HGDE7P8lOVqZRdKOvvLyRCshh5E2VVDUxmpUU6vBtAilKvq6Mwj0ZTv73mga
4lJZKZfHcWmWIgKqDzF/dJfziof3mYViNVVsKLy7frbCOvhol6qtllVPM4gMQMOsatcbbL1xD+4f
WOzW9V3sMeLnio8fKk980CDTIAP/ETsWZh845cHTKUDBIEBxmQ7ECrloqQ/29JLNDOiuhdAADQro
CyVJcAT7BF9hscPTr7QF5xBQxkp7cDAwaWVDuWyTohqnjFr6tc0u+qYcDOdw8Ixx9m81Qc/7m/4x
iYR75iFcLZzjQYtMZr0r3JXgyQJ+aFfV6Ul5JxsD0Auf/feJR6vg5BgiyfhTTSEA+qN7ggwUNJ2J
bxEDVkPSmYCziEogjRedAaIngj7W4lvKTFpC5FyAdYNe3NfeHY+zkeKxxcjWO2wtya0WgtkshSVb
UCjf3/VJfahNsqR6dbepgHSVvAei5F02otS/LtyU9ZAIe3VJpjpvlQQxo9sMFybe9ZgsjT4nb3DQ
tY+a3oo8WXvisAz5ENbqkOxfvrL45G0eW1wn62Wqs/FiIyetROzu6SMPIyGyG0iCPfLqxOvDJuRB
vpX4yMdaqO/qgfERD3PlflLPg3mO3XTgtg3DEHXSjT9ErY5GFrwyju/2d8s0gC7zjqPYRMXX0i5O
TiIRd6pQSP+T9JOapYl+mC0KnxZs4V4Ow/0/bcHhWoza8aKZguCuippIcOT2gBLucPQaomSvc/Tf
fcA6fOlEmCKyl1AQwwdqMKm+vSGfhILISmxx1fZwMOg5xj0MQ9y0FfiKzQHeBwRvRbSogUXD4td0
ck+1Eg1g6Y5pnjMG+ICL480eDk6vwygEqXSEmwKiju4BhN5DnjWwy70l9QotyQk4GDYJ2LZ0iX4M
JE9QhW3Uv+iN0hocc74dTNOhY8E8GRLlsb+GcvqoSx6qdaKZ9tsiVwppZabYXW5gpDHJieQyA3tM
Zxd8Cc0Zl/0t6mvjT4h9aQe0xmR7DWpGCd7OkYZIheVbZ/gfzDLalDvPsjCV+E2r3T//tm0rMGDB
PHZ/11Bq5zG4sZ2SejaB7zgbUWcoottPRJyLlvhNLtGYfwxmVJRnUr7Y8kVZ/KqK1nCHxD1h6Qx6
s+3XeOzUVdRmycBn2LMV+kYS48SLgbRny/npteNqcCMBolwTw6MSaXXvT4BKUZm9jHmTC5MApBT/
U6QSfjhzKxC1eSqCC9LT9puJHz8xnO6YT5r+uxXarJmr1I/el6TVkhp62rspw5UQ7KKVBiSt56zg
DmR5NFqASy1+ZSrVp0MIGqfjG0CC6GMw38/cByXCzdbCo2353JJhIyn9SLt1vEeQwJ7g2t6KsMeb
fEkbvcdFy6vemX50FC31bBGnoVUzflXuorftADin5BEGARMz4h72IDP7D157141vTTyrGsC7zNFQ
LYA2roQA3WjiLOHPsEmoWuor9RoNmNi2xsRI85ugHQCApth6c4s+AWMeG8A1Jm0kdgzgZEop1Yqx
TBgE+Pi5W0msUp1OV8ZAKpddG2O7H01D82ft0ag3/IfYMQuWCk0PYPa85X0MhKc+xewshsTRrjV/
1wyXGgklB+gotVqmV8CZlrGFx/RzGOQMGJ9wQIKE6gcBFSA5DovYeBMrkkGDtSiGdFGTtYZg4RYo
1197AbB0QWWvbY24YigCfqjK7Fy4FjnghNINI6aP9BQtpFBYhEwycCCZqMWbesuFmAV/tTSB322T
2A3t6zsvU0mOBtkvIfXLOgoz1ltbl03lggAGqGuZiQjdmEzIkivZvwQvzVYY7QjSehuFrC11cJoj
9rjzXHLbDI2LBOd67+FlWaxyornIFH4V3Ef3AOvY8p0QOi3L/c1U8jhbpmmPJzfqlkWJoX62NVzP
tS5Ic8tVS+dfok5cLHUHrlS2+5/hEKtbt9MKp2fvfH4YCIOaEgiG8ktHFxJkDuyybFCz1Dgr3fXR
NEtIxvgsvlF1uH9LIXxPulMlJ6/N/fUqfcM5tkU4J3tWkNKjhoo+UdZO1H8quLNkSzTZWaduJq68
FAa3sidg6+KauGOS79KVRzdiwexsvDFDtotR3bne1uYQNJu22I0N3WmFy53X4f50y4RTCxb/f5Ky
xiP6NApHu0FCKgi1rpJqLH4iTsfQwSao8bUUclfVb8HLJ5ZD5Uh/lEnRdcKfSZTe8ERikqE5lbPf
tsNV750Lmxpd2GyNzKXaKh96aWld/qA1pnrExWxqrs6lSn7R7izBMZkFPiEAMc80yC+XicPsxVLb
HMeDpVJt7d26/qmCCy5A8WfkvCyR1a/WkXxW/1f2/JEJQteKmiOZnfZ4GTKb0CjwiP1Iucnas3zI
8gvQj5oEiexnkUtfKntmIYdHrcbyZjxox+Ee3GslX7Zgd5h8/QYxoh2NAP0h8xooKPzlBwN1JdSl
N0bZ30rSRwW/TblVPtdYdKDnlDTurbL97Qpx72H3cuiKBNr+4JmsvcO3VVEewEOLHp72vPEpAuYu
QiKjBqvgFFSk8jONr1E1wQ4i0uRWHGluwtx0jW4Ha/EPjDOFv2VGdS559TTeLvM2/Kbu/VbWbYYJ
CO6pExCPfQ61Qwj8DhNy+x+iXaQLxt4aORR7cGhh9ovZ+zwpL/QtRpy13tl7OWgHogtf0wg0nG1K
e/ii98tbyzSlAwqyIg1rQJB+mxnNGTOIZh7U0fnw57PMYK6H+LWR9mpcOnnia4oHkM8UTdpHGyDP
1TQKVGaPPx8z1kp/7mneFdQemb2n7Z7j8NqNBWwEwwCcIFLnOJ34e5keCblxhe5AV9eZwhVaYDil
+d7Vf/CLlBJmJ/vlXp9WpGwg1TSuBxz6hECKIhy3oePnme1s132c/gZqtLuw29fePR1JNVbHNzd+
G1gqockttXVZ14nNh1M8R9W/E/T4sWGtnuhCsLrQWI0JiCMJBW7piQ+zLKigOHvE8jVr9Ad1l5aj
05H/+MaVMoIw3eQUr7N3ee9E8kblBonwDKfzNrSH2S21MZTZci70ie+aSngVZ04tXgqt51YIB/Lt
8w0gQvIBXqRC+1xZjqtqYsxx6jMEZOQMsKNIoyM4RCJOWA6E+a/Ms4O4AWV7LnZKyji4fnOmlMc1
Edb3tEJffY89VeCw697+MW0szyjP0DBXVLB7Mxqc6ll8V2EFFfpsgxeScDTKEsbmtOr3ul+jdsi3
krLrY0XZ19u3dQ2/8UUOs4FhszBTH2Zk5ALAQHjfPR7U6D3+w7YtOLG3PcxE5nnKK/tr+uLpZgjt
7Yctm1gS2/oLTP81gRloUM5vC17iDu7lhJsiTlgTc6VxISxHnBAWcVJsw4RFtaN3kpRrXowLRXms
Y98+dp/1cqo21qlQOTkwSlyv0dQPxCh5nHSU0bUGYcXTk/YrR6vg1/HN60Vhdk89SpN5UvJzm87H
5MtHnO1rJV2ZYOigWHAShpQwik4BYQNe7LN+8zD9U7xzXyPmshkcLYu3uyqLQx/+Qc3jms8wjUag
AddU1Bwtc3gGPzPqVUA6J14eT06jvHpP/DHIR+o62CRiJZQoJFWp7CrYT3wniPBTn2JxwSOiVcjH
2beCZAx4aMAgcb9BEyze4YNrY580G24pUmXBWgd2lTqURyWAdsJMEThQetLXrhfC4Is9UIWRdFF1
rnhW9YlGurwGXGd5VyrOrXDbhRxQHlSXk4hpusaCKkLs4KZik9TcXNh8/456xlpdxGEHtxBrw7e9
lQggOMFbhHtA91+20szmeDz28SGnTzRdurKc9jgWbPCGoUQMFVs2o7wRTRUMfStrOQ9o0k/ACQ5Z
gIUVLaJP0+cMFDODwUll77Ze9wwijqSEsOQzBDOx16kh1w0Km/2CVC+r0tNqKZk1o/1MTseXj7a6
oahXO3tKTPcgoa8kpdwLec9pyUUx6TBDyAjTcSUgLqGXcddFqkAL+d6SHs0ZCbb54eqU0liQCU/9
cDu9gPuX+ia32zOjW4C0xCkJaQi//qsV5H3gzpeNrdfUOliu0eguoFRrIdpbrj/GGqkl3myvwIyQ
OyTB1BXcV3M1tVqiaERFshY0jXDIyn5HNg8GEmMmg4yLfJ/Us0/Z8h/jb3hcyhUt9lotVhN8LQst
T2+P4EnNPRgfUWIAhqm0kCGm3t9FxffS3GFZo83/uMuQimBAQPjRrHyVUlne60xHNekAPf9Jnboo
b59aGHMfleT23APqUDdrKvQkFqdVelahczekgBnxz6c6XchMyfDSpJLCVkzvwc25CV2Uqh0DJCy7
PKSqdW5+rMmu/mW9IP+kbraBOKkVmo7M1u9ln8gQCw7MJbECnEbYXcMdXUbIkDKqxAC2MZC9NapU
byKfeeJ72Gh/bwL2HLrgIQqaNPOCUqRSh8c2BGqB/Yyn/DJz4gsYvi/2Rmm9m4ODcaYNRmtYq/IS
IcNHCxAfcscZDqcnr3ZSO7+AI71bX2fWIHkjnn8bYA63dWKlyDk3/euRv9//IP5atn15qSNy7zOw
6rlEbCKdnSHC3HgNGVRFzMceLc5VbR9c0PPnk5c+7/cTLTHrwzA9YjKfO+03iCUy2aaejUNtjFz2
k6cCNrKKBPkyCPsTWUY4HCdZMMVrCrdRl1ziiYE4mmuIkmPYCHagNX8UV48RSbHiRXl+Hr2BFAiQ
LEOtLN19bZVejpJYrtVMlSkvRrj0f0Ay8sUt5VyN5lhxlP6xkTTfDbMhcrg6gF86aDzpiuRcCTNt
723azBsYt6tCS9sbydwpvMi1aW7z+VYAZ3suMoP13DzNg2GNHpDxlK/qqU9+ucTltH29EONXA/tN
a46YhN4pg6+RN00aGPdnDmoF05zwAKP97Gf+2laJeutd3aZcS4/mrED+iZztriDqbG+f/azpVmoX
wvGnVoi0g/+d2ZzzY2utxlx7cAgGwn292X6VIZPxQeRvkidIRzzm1QPuP1Eb09UA2t2/0Mh2nLDl
ps5dA4x7W2xpBI8kXguiIk5FMQPC5fhO79sl4F4+wPxG9BeLBMHHWy+2cP5cPlkAwRRLdxNLLfTh
gaKDD51u2E7GACbjceT/A7d0GOc9sSCu4feuJHH7DRTmE4n4o8IOZqJlJ6Zln5JmRDcn+6FmPEWX
ikNTkpYC6FqDbOJVqNikPQqn8IR1gTDmdSbyM9JWL2CKdIMFmOuY2Ai0uM3KFd2UlK0ZRiRqCv/R
2n7HXNbdFXYfzE+eGQfPARv9woAkf7PgoXwjcFzDiaI5qYJoRWmr3WW2oTk+fylhShSwP49xuXDD
bQZ9DoHzxDwNYtfNvd/jtCGvAdZV+rkIbImBvJAKRED6Huqs8dgOTs5mMCS7cWphKSoj1qEd3yYJ
HknruBLMRvugeOlTHuNM/z2BIB+cb3rQTppU+f8zgf3j6qLlu1XNvIcLvF/b19Bymy4N4rh1y6mO
LFoYqHNhKlroO+Cq/xPyKTRopBnUlm+32EN1EbeFjTDiSz6wQ8FV1S/xRphjpBfzhnFqEYw1GOpU
FWMO4nnBotSgHInwI+UPA213Bf7y/WgbpnCcVQBrpqDJuv9Ph2tpEsjfiNI3cLQJof1TW5HQPjtm
p8Z5S16ea9hd4c966Obr54kn9Nu55Gi9jFDgRFv8VeGWCPF8Jkz0A6/aMu1cTZmdOYqMfqtmSFUN
yw3SHUCHwJGQaFts5AA9hpOzSJumQoSwoQZ0rmDrn+6mj0Lqd8KLf5KdOuZhGfDpNahrHmZaO5uu
E6ZM2ubtEgMjc143FIghXlIQ8e7TDQXGq+354PEReJB4/f/3U4BXyRatggVLu42Q7/4jc/MUufYE
gNM0pGjqviUuZNJwha7zJT4OscFqOmA2420uVyyiJxLEd0ZNoZz2vtYZw6o196Yy3JHgrhFi+saq
mMFPb8QN9BdaTRYxuG+1o5yzASuzZpsucRI6E5na7YgcYihPfjVTvz+8CDVXweTnMbOTh0DYfn93
cmECnd4Wd6BgVzUIhH1EedNbVua5qlLPvnayH8G9uHhjMEhhZ6VPcQEIzAjOUPdlM5EfSFd61Ezs
J+38Cy5bblA6oL3pHybD4gLive5a7voZorPNc9Fi217BmkAXEy39hL8hTiV73jS57QAuoC+hALsu
5hemWjFpJQKGmwlSVnA5IduU51GIFmdf1VYuFuLWBJsp2WkX4Iw+vAP3L2MPPFbm4qibn6kWfAHn
Y9JxG6r16vmzCtIpuD7+RiHm2t6Y7fp/sjEYezCEIy+QzmGCpBxy3LUe8evVYM+kgDDhonTTNDtQ
oIRYjbCf6Jep65QC9SjOk4YSB+1B17ua3Wyen/SWk4dFLdveVQ2Vte6CenGE+fsnzUzAaySCCdLI
JmGmCFF0C9uCXTMwkvjGIKxbQhNygRBdTZhUqXAYAdH+/t8qWG/CQkvV5MPNGSjwGCnZT2nHlbNq
yLUcfu4EsqjaPY3S1JqQKHtzao2st66a9zJM28arm+/s5IGO37rXVOR0+jt8eQx+qobm/HGjYstv
xcKFcH41b+JiPLNTakhabv1QtfBUHpa9nhv0dO6Qn4mPZLz7M9nfQ6oLVi7dtmfvcaCRgrC9rPAm
37RnmOne6en+sNElJnOahWUHxzxqGkLUIfOW9f/PkK0r9IKeSVQ6moMtoSAU7tHZKNqLXSU/rtoI
nkLWhQXdlGjrQX0qIyNltlq2ksdehFHZVc6uABam5ggl1z7HZRysSrLen1IEM6T3uUJZebFN9foU
hppWx8Ti7YOgj1eQm102D+F6F9AQyHwKq/8F4PXJVuPVT8WjHkgYDQqNTfqQiWz5mv9COcHxrcZb
7s1RiGoBI6bLTuyHZCUcDi9NEDOrun6kNhFMhO/GRKp2vI/2wtX4g7lDMgJmbeZ7ahn6e6vmToWr
Lug8Z5R16Azv92XBfsSGGtuRMmncSmOWnAw8ioe7NsrrMQcA5zljVVkVD6b4nrsG/KpFa5qsMy1P
DvCB25kgzVcZ/eHNEZ2LTDvaWbosN8mDZ/sFcSLrMHdiZ5U5jj9byKdskBkYUNc/CdPSWXvHzK1C
vJZ4Jz0MTo2M5wDx3bxDotbpmrst4rOd6D1qOZtz+UNF97eSJBhKxDwu6p62Qqj1NV2/bAUrFajQ
+42buVtPOySemfPI4bB/BuYWuu6BrW5cxCYOim75SUlmi3vYtnwYN1+ZVV4AolSIbfi3QlzfJph3
8btNrkVTrSuEX0ugSyF/ZV0INhp8KBwZgMbWuvkQlAYaDNBpD47k5t6hkEmYGDGbgic0GH9fzxu5
SzgHMXpPReGgiU0KRkU4KUeH4eu9hEF5JrXepjNQhkdNofMRvC/wp0Vo1HbhZIDNRhszpIn2VRtT
HOOOaBIO1DgDsObcekUfTUoqCjjtDgSdZTLYGtgN9eABRXuwktgPnRtd+rNU4IwDihCpPErx6LwM
ZTtePOhSt/Sk+aL6x9GvV8G4IgDgjEsvCuGyIfrKhHUMXpcmFuz0HsPxxUXQzWG/4FzwvtI9/d7y
ZFKsSdLabHMoN4Q7LeMeXig+N7Q7iD+cJVEvXpn1Y2pK0x24NQ8uCzabBhiPywoYtX44WcJ3EvjC
8aZ/P4J+JOtPd4hpPUBO2dGscE8OqQktFmu8QVwXM8KZr8Duy4htkOkpjUACamtnUg8wphN1sHpe
uqWF4aeQ15T0CFfVtSO+enrN4Xt9gePdDMjzAFTJoX2cgQryWD5J6XcLbzOPzpVosnHooYj/PAok
PYvq4p3dDcWwFlAMOKO+H8bgVV0jkQNzBP1sVBi+JqAT586tZPNoc4czoFjKKkGnz0jIY5OQ0k0Y
m9QMefKIkdg0GGmXzjnXyhKkSf+30nqkoWAjA/wqtT0ctFkZQdvrpeSVM2vOqPSue57WX3UizmEj
s+f0hSFnZp59DjFCjxs34t1qQuz5dkPjD8lv3gCi+sywBDWGFeiZX+kCoBi/oDUwASQrVrXR3snO
KH0kRyKmUXQPn98qPw4U/aakLwkP0NS5jnfOl8dTvnhh0EszlHyEOV1fRVPPXtiGlX91GNw1L1AU
Ex7PnpBRClTsKml1lZ34zvJHnE6DYafp6/s9uejymexkGch1kiGiRvn6d2rKEJRoD2ABWWkgWUsl
2enWNjG4FwvGcc1Ss3qXqD+VlRrBnLG+1hjLxecCFm/xUFFIbQmmQ5X5hZvA3/IBrUdaJen6fXxV
BpEobVYHCQHe7qCbUPir9zrwHyr9NPv9BrRBUYbUuowBoB4T2cp6j2o+WKex0dZzNrh86a+GUvdn
MbUUVzgq/oQTmRdF4on2AEJBhNIM0Y554IMFP1Z4eHR3Rs0xUj9Xr6kRNV2jmlPtN/6WXFbw2YHk
SjrfcR9JUAOCX7/UhMASFXg82USCCS8kAIu9cUNAwNzdTfx6XdjuYh7AglI2Ye81ayhoz5b87sNK
Ju5rbcvHRHxRBecoUf0rbukldaRIMw0O21j5OYg6fyUHEzltD9Am8XNPeQe/sqy06VdiRHC1DAC6
YzYYknVky6c8WzwsmzVPCqJDbQqq0p5mh16umGH+4vsjc4fzSpakyO3ZyIWDWT6ELJYEPH1Jweo4
lOOOJ/6liZnAgLUM4Auv5Kg0xhTSFNESFPZ8HFGMNb7+xjT2mX7yKdOspyhJO40OjiyAQuRgm9ND
T6idki/cRSiw5iV8G4SbC0UwQosu6wcnPDQlS1L5DeqX+eVnFTAaIhJGMQh3t2BGPKbMdAnWJ57l
5D99MWpluvUDrGT4y7MlHu5B3GbEnwP2X663/5sDlyZsFHOJLOj7l1mSg3aRsiIcUlUP19H4QTW1
02gbVfV2Xvv32G8HJEoYTEaCgOfwBQVZqRdMnaDMNAjYELmOtZyIilLG1HqnpSNaWarcqI5J6ryp
sBdjetgvw+kj/7LX0zw0z1T8MJUeiaiXOWNyg09FzMtz1pynRvBZIDTcSNbINwB91/dsBvMGiqSA
8mk5Lgz6/TlwJ2//ELw7FgQHH8vL/M3w8HqP2mNBPYm66edNeGijimZsD+V8kUkz5OfxFrr+1i10
DzSrEPvFoiLfNPQGkkcUAU7Y4L42HqSyKrxNVGfte4yekvieWdWG/hWuudJRbj6Q/SEZVBKs4htu
LnNiKPo9SolN7XYdmOj5eiCBn7rK8EGZMsvzy6ESm6rO75r2o6/e3cFTFgJXzg1QMAuLm/xst+s6
HZBQwDR+6vF5zhoXy8qcsSuBEDdh1dpzyIfTV29/FuCGokXxiC5PMZMO0upOyTfT747jT2zPu0ME
YJMXQlx2Bw8n2rxGgREx+uw+jxZkuG0ehXzUggX8RSmYksX1xYShpHxdGB91VRC2zf03fXfArHb1
R4TLOQQnrJ+wEHan9+vKrIs40FN+TFAODnPuwBSeBHctW7JJ2JAz56oyvRGQmVYp9o7stzgh7FCs
LvR+tiIeFkqkgnkRIIP2un9figmrwVWlLgxuoSdm3DKIYf830lN0lm/lE2m1umahHa/GnxVBPsBp
Qo9K6Ff7yMeOovjJekOXNKEEV/T2gQMwqlDBVl5umUx5mp4rN367/A5hbkFXqCokQUawkp5HFD/t
gViwGFEUZ0pYUL3NiepJuyY77ds2wT3QYqC+2iQtYuNbDbvJsHQ58gp1UDa7z09q+aYux/dm5ajf
fnaoWHoa7IiOKHj8tzFfRjSl8CBWomY2RjMkjY8k2jCXNV79RW+yrlBf5zwGE36giUophbilUH9J
WPW3XXO1/f45sIE3rF1Nm+HHweaqqng+CLPUEp55vfr3/OZ0tv3NLHZ5TtLIEZQAXmglliyqskBN
7Ibzwn9sPPeaHtr4KkDRV5FCKenx6RJasNjE1ODg/dFbHzqABhyQxEnA9H953Cfn4RYskLnP+Cs8
+V73f3TbgjB2732+TW0epRbVdVsWk+Py8tU5QK2kMcCQDfiGnjbDjRrcwNIZnL3O1uu+quZ12ntd
sFk3cNHrRWmGJ8UZEFE+c0NemvuNiK/bTcrrpV9xgFqRtirVJopBM3pWONkpEY+uUp3dadPK3PLH
eYMwC5eDpGLGJTB+YdNMuuHoQ5oHcvrNPFk9LhvSCHjD8YojbFzpuwxKXku27YwWnKu+rEsT8EBP
6F1nTm5cz8rsMnbzO3faqbQbD/DBq1Chj/8/ABwlsUc9MNrsmSDzdoyvrK5DxJhNyhfkigcrUb/n
oJb0YCt0pY3wonl60+cg0G45NHc3G2GbkdZUQsJvnOeSesOHNhx7UzQNrBruF0gcs26FcG+VFYl+
x08eQ4yjwGJZr6jIR12V2y4F0w47/rr7Dt5DvIzrDX/6AqSVnorh1S84VxSwGmEWo9BB7GkMLIba
UrOtK3cvKDq2SSKQKliNtSlkE1n+0e9vxYUo15NCYmG9/q9Nk62xB6vz68HhSWB6KjHoKrDDoI/p
BTzbBC/ZB4Pbh321/uYcqiIJCzp5DAx8iSaMAEWXUeBLjvxVNSTHkya7Gt9/P5L2GXLNwcn2cqVS
dk/SK0SRtuSdy3Gd5UVqn0ANdv/w3PGZKu8EbuiZCcw3XnM0/BjEMRyA70lj4HqPYL8S+FjFzn9t
0fPEQnyzi3tr2qOOrX7H2owWA0dtoe+p/yPY+wahQ9vX+CRRNq+oAAfJjag0o2OajG2ZnWuFxLiL
anGQ7MQ28PHll+mjlJKURMeuRNfhhEtdaiiAikJR7sg7dkG+Bpx7U8XL5gAWmQQFLq1PMqCttqyd
MAQdHq9NJkrUJvLAmfDAxij9ZfVtM0GIqG2+v0wtd1W8ny6V8HDsNH7albPkue45ZqlrVr93US26
1ike6ItXCmbm62NRKougqkdLcuHTgbGm7gZUh0+W3FEeKfU1JB8tb9RXtihaKb+dkxF79YzGwicc
vOUF+BDoFFr+428xgpg0lmiOrYe5V1iBMqEdMS9c3hQCFmGCYxuplKTHSTqfrjwJu4+FDrrncCk1
N0pnErcS9MDMrqLaesDEcIxNeVDUl6FGllpcG8+LlQjnVTuzAqx4XyfoY6+PugkAwuNtQ3pkP73l
UnqnjHm+M2Jwda3luamW7iXLOGXMmdCUC8Dw6eWS9pCpkgc2lmI+2LrSfAw8Lz21z5T5pt2BYc7i
ZQbGK7Tw+QeNNBJv8SwveOll1taJzx0WptykXLeOluLbHk1zq+t7lACaeW4vwsIPoRUbbHBqdDeZ
/72bwwl8YzS3w5Eg+ftxGO3Tq4XM+ZyRAzQP5MfKh3gQvv9211eh8gED/HIfjSGn0Cfxx0sbLudd
CWhxZIjqm4W2QLT4svR6ZvBSz+3NKSD01Ki9bzv6t33Abu+wu6YZr/A/Hx1kT9H/YeSksUWrCa4G
MJ3LFa2qgwwe9+azKuRgNivYY0wK9s61NAoLDUzKlND9v+UkqZVroYEtk29rn0nK6Bz1hnDRn1nW
0ht0wvNimmCadG/JtsMBpsSJHtjHADBWccixPr9lrD6+RQ24lsY3XubqzNEgR6q1ivfDb9wuiUNo
mEBsTCHVXXviOkYGzxMWeFwC+M3XpN8EHmHR8x5wdJ/bQyCIpslB/2Dt1tZQqgHTUNCsJHKrlHmj
p1NSw7uMD/TOVKxmfY0CwRb4rdQe5ITDHowzovfXJTvcydMhV4ss0Q+jkAmsQJ5LGxdwVqljPgqt
FwjGyXN15NNgf9utiGW9CvCvxggGSV1Tby2wF7y9wWhY64B1u7UcQTn1dvSfw2TQ7Sr6xt6oVmGJ
fN3+dQPBjY5FwFeY/PTl4z/IYLqFCljZ0hvkMTm2wx1NuEnO8N50v96Hb3G3ucBYK247s3/QJwj4
GeM4GPW+7amf0Wqxv4FDGuxue61ka4xGqPSfV+4iBQPzKO97DJe52qkZgvf+TjebizKznGV8XSCh
85WAM672FgPJAS6VISpj51albNramKmaT6NmG1bR6AnpuUSRiUbb8zie0Vzg608vRVA58mHpGqH5
uqOkWg0DIqZBfMp6d3SBr7G6IUFOrLspcBMroFxyDYgaEla5wcYZ2pqFMQvJ/s0inVtzE6i+qHko
xErrJY0UHyVBeMLtrP4KUHDwZFXq8prNHEaANVMwN8hb9Z9A1R7kSyokpmRoUMOkAGCh3KXzpZhw
+AUDagGhsITj97pyP1ouBGlFkAPPBOWeMSAlJ8lZlDgeva06H7yWs0Idx/dvYHvzE4Aes6f3cC8V
q+/Y3Lj8To0apuuH78eF/XXJhmiY7sgDxfziNKn5Rqx2uq+a4G58O9H5Jb83hB4BPEf1EojeoH+k
gCA+TikTMz0T3GyaCgxibk9iqHt+uWaasr8WY+Psw9+M0yx/uW8YMXJcuBhMDyjuTgn2zBs6ES4I
BWsD94NI40YmkBsqhZPQgEH4MntfwKEpgKW7hmkvuvbBK1/R4/Q7nIasLHyxzKqC0srIr/Oxv5SE
yNRNLr168qDqwvaBkTi9udraVY8yhVvNjI3EgSbLCWn0oD/RG0z3Lm0XmADqwoC4Eon3cfuAwFd0
5cfQiiVvctWo/jv43IxG+fuY+sPo+OEmm/mDH20AicV/RqQpGSEhuy91+C3+A1Kqg4EWNiR9cspj
db17ck2TydAjGc/cGp0O1UM6pgpit+Q7QnkeEyGduXX4DLXQjhEBBr8ndHWWdsS5MsDlPvcNwaYK
LJbD7ew5g25arzEoESoeUsHddwVXp70wdtqPfS9u2Ur+6kIf1kzw6GyB3DvZSX4awY5gOiYy2gYA
hEcpuVn3wfbR7BOYPv8KfyCx1h4+DXbEV9AbBzs+AP6N0kiT8g5E8ZOLJktJrTXt+hKfY81T8zGB
Hido+eLEpk3TDMbs3da+HtfK/uKSmX8PRnWeDob/0YOirpGTuXOG9wW/HVF9nTjGF99Ck721Kif9
VHdX1+BguNBM+DDWmcLXIElZ5ZzfXqrPSbI1C/j6vED3j9/E9NpJ3KDjHr+w5J5nPqemXMl09278
FnQrEe+9SVGt96xTZajS4xP7yc0uY0O423YARUkpGe+1TQIJgncEZ4k7a6x3arjmnsVSV57nv0Qb
3TlCGR8ewkdULZDE96FpZRxcJrW9XpEGH9+HFtWhU+3yvB9vPG43gqc/0quymIFHETQ7dF7o7Fn4
yn3AZBK+pi5Oc/G873HfpNQRuRHPR7GSz2L/aprLQyz2lfyQJPUsMJHGINzrxajurAtv3bL11JVR
FzVotHau47e50bWtoCx4ewKT4TpxEOT7B2Qk6/C+XyUIM1xl+hAEMs9oMsnhNJ+TKeaVZLg7MRwM
RrYcmw8JnE/giqCCJga2WGou891DH1i6csAZGHIo2ityHFK4RgoVsnvo65LjQZIvJDYu/msbAbTN
V8gd9bgLxeLocDke619EKaSdv9xiCrhX1SDbJ2sRGnjnOLyiTHAvGA60aPxkK9w2eSSvS0oS9+B5
Loeoui6be8FbYdiJtqVq6r6S8qntDK0vFuGTUFc0ovPXMrc0VD/bY295tudfylTkSV97CVjemndi
tBmZxwqbMgsSYjn8uYJOLEnaViy/GM1IaAC+E7XvENBUe5mq8NpejkjVV6SKlM//rI8RXm7ltcYA
LhRhJpB/XDv83zOcpzFPGm7KSKJR6uyKvrWrc2W4FyRs6y8725FGp5kKFQdTjmtuoFiXo9QhtBYc
pT6cH1eOiGyETCiSN+GyRE6VsDzIPJdPZv8SfTB3eVLZLtcyYBG4pIR52Z0oJbA3KDj+cHlHMnF3
iVGDqxkmihXE3zawMSx/EwtsUPnyrSU920Zp/h1GfwXzzzaW03KRX0cIRE4hW8DW1FamKDNfW89c
cQ/eRiuWqiXYlaSIJ3lvIdLup0pVza8CkMLc3uQvUdo0S01ikqkKUvPaidwPIyHsvZkcM1l1v2j5
CwHzSj6DB1WK2oTakQKxksbSHwKIZS5ee1AxPweH2uMEHGK0J+8s8p46AxqAGsokEI73evKuHj3l
3iTcz7INulxLfJ2VDWV0mbkoIfou5Db+xq22L4iwkjBqP265q/VxaHSCRvIC5Bk9HkQ4+mT9Saha
qfzSBy8Whm9SqZ/fwim1+k4YUt/YoCBi3bGdgC1BpZPRRUHNfsxQbTki8woUvNfSUOXHtcQFefw3
w6NO6s6dEurCqhMnED3kAVICXlYlPqehTayGgbxbj21QVjJATqi+OyTQCApX7aS4m9ZdWnhowENg
WtftWeBqvj8zLsNcLUeFiqlFJolpekrK25ZYZvuABYAiXjAXhlc/aVJV2G2+s18aTDoYHZLM4Nny
o228dHcN2/4cWoscd523vvNpq2/bGr+2Abao9Lh46s2fxiSX+/Rex2hublvUx1pPI4b3kYyc3R+G
PgRWLh/NiauWGt8+FSGoBWRs4sPkLcygRPv0JDIBHYO0NbvHCvRlWrnrApjnjHUiOc+aDADcuYpf
ijBD5h5Gig0VU7qLeOn9YSPk+RTBw0mDmGWwmX8/l3uhMnAScn0oWcCSOT6BQVhQRL6IQEuuRVR2
HOG3rKckD6DgqX9yO6bIzeMeib/LS9yIDh/LJm1E30CZsxIQ3EKF5hMQ/+zvltd9VnCY5gRSKskl
sCa8CdKe6dqpIFWIIXfzN5merCduEEXYSZIS01H22kCoXeoqNo+8cTkH8aJk8vAHVE5+jjDm3mEc
GsQ5nW2ZYnDuREhsHcz3sfbL7GdSJh7/zfv1lI8spXpdebDCHx4VuHm2OK41DV2bv3ovry96M2ZS
XBHuKwTFwhUQ0ZJBB8/NgC8Y/PjA/yRhgUpBDeiUc+cMUT0FJF8d6dpeTLd3+vhLw/3Cb3+r0sxU
sNKBF3+hRI//D6ueIHGqfftwEBNWzm5dreraygpVBvJZzzvqvfCRJBmA3e643RslrVLX1+3R4DsF
59QhUezMc8a1N9iic6lIkQ8U27vmU0rEdftb0urdWkKdPv8xJ5xWyLBcEA3PTRFu9lM9u0I4ZIBC
re0fvHR1rye8UOl5RU5VmZ91vYEs5GgnlMoUJP2OG3IE+h6y71CO5CGxGjAO6Rtk/EqW55oCIzos
dac2CgfiU/E7LrYBWn2lwqE9UYhaquncE+rYwNLJoF1r1IVhlU2nvJAC/uv72NQHhxgUUPkShUVT
SBz3kte0lJ2wJKgdHqaf9KiuUUl91uH1HCjVbFrQwB1P7NmiDtQU3a3Umws20Wv09csyrLh0cvwa
e0eMOICpJugHdBirkos0x8xghHV7xouVBQDB4islChQGY6ee1yhM9ccDaspPUTQuLRcDGGFKgmo4
zIRhvFngFdorlYWL/TzOGTam3X1YczU5hkq4SpFQEKmCmJ+2DnvggZd12/NQDZQuSVl8QExtIPvw
ettfUzIHkv6x2YaQrWuz0au7pGrM5RdMqacqDnlPbYTAeP9zELuMyte52TISgO8NdnXYUk3LlFB+
RqHsRT8nbYRRmGTttRdFylL+p7U4IFV/5uT7QfjJpzvJVqJ0tHKytvnb90/HyN7LX0w2/sy9gE93
A0z6hoBSAYDafYH001/bNnSSTuAUK2DZO1iHY8gL1GJGCUF3yRoCkwicp0+R6VAKhNEb2UdVyB4r
RWndUYJnFVnoCdWdTO05W1/mN1KheyBtw3wh8mfnaser8Bv+Xsn3gGVHbRTWxLZhS7+ZRb2sqS2H
CCSwY+xZVY/CChWOwWN9eMOKdqAjC/UKM4dO4uZBlwnRjjoMDaa6Ie2eTFS2C3mTWigFAg4V8PYH
8c2WwKp26XHA3S7mxNgzZKXpCb0yndinTiXE83o3QyA3ZPVXS6EnVKuN+ZskAlS7OfEwWqpylaef
lfAYOLJJn0Vb/qOsuqmHI1MLI1x8LIYlAY3EFaQJImY4MpbdZFibkFugr87wgJEMyz5cvK9btSpI
RSQCp1uD7LNMK27nrnbfeZ8T7pO7D+HY2ttR6iT+5HXL2VEEqyrB6nUFtxk3nq5cC+Aumst3e6J7
mW/GDEYoj6g3CrW2h2ahe4bjVTzzkqwHUh6kwI7xmOoiOW9WXHJbBDWriaH5+1AMYRQPjT3ad0kH
n99HkztvGdSR9cI5imYYYuZoBmN1F8xz4N4Xz9O7oEQ+p371Y9QYr43e5UF1DOCgigLg90RnIWPC
62tFMaOJlts0XujTXRMPD51KshfDbO7MFK1L0Gd7zQYYas8I2rorKn3SbEyV4Qg5Xzk962XhEGSw
W+MDCVwknUSY3D74VwcNaUpzVU3RsYbuJ+iXOGR2n2wcomlretsG1wyMU9K4pIRBLerfJ5PyTfHI
PW4G6popMGx6skXC5pug+5llVUI7q/ywCFHvss3csuEiRZeQw5eERkZHru1BP3qBFZ3jEWnxcLVp
erize7IgXYlygIZFjtm0T7HsUeasqrTxPfNE2BHgn+t2t7OVKbSFmAgrYldMWKgx1nOSoicL8gIS
5SmUPmJ9LzSg43u7C4pRPgt1H/jgYNrza/Irv6acVG/Mn8WJIo3Fimg0/QDFOtZqnrsq0lobHYHn
7+9ET0jw1J2TE5DJhthBcw1+3hu6wHwsWoeGL7uLbHai9pm8b86em6UXgPheCXUPNoUcyll9pu3P
ewShgrBy7BAo4bCrkQqVt+j8ukUwqsFUu5vjX9xhSa8KNzIhsiz7BFs/v2WknFloVxFX7FFMeXZm
C6bOy7i0KVt6BmIY00QYQ5tnW72fkGXWBDWq14YDRjrgL9EJVrefCCEqSHRbycm1eD0qAOQrGIQq
1l7PdiTj4tCuftTLF47fpX4SKg3u72/7iDHA6nVQKQzMgwBqieVeBbMFwC+oErh/lbqniJ4FbmH0
BEiylqd6VhmB+9KR72V420eyaRR4MkxpbjPhkKmOyczgTOWBvbXX4MMNNrYz96IwkachccgQZD2q
hbcseiSK4ARlzg7cwiqjPrk7jz85WA3dDqd4gb9jhJxDAVc2IlETCbuxFtLRSSxOK9HCh2EXJOoy
nzyNJBY8PkImT65XaRSNqtDk/p5aDjkw8s6Upbz7BVWf/l5mzQdRegB4aLMY8un+7+REkJuAxNG4
GXAEpvFJhVA0Hr2C8b4f3kFWeCuQ7La08PBSbcAaiHVBYWOF5P/rOfXPEgHQ82DNifRBL5vFk3IN
pzPm2lMXylzS3su1sV3YsPkVBB70MQXOskw7pNTsQKKBlkECZZ6cbJaEX7YbLUiufiTydxVQ14Dt
Bqy7OQzSLyVxHeGFU4bMeW+DhdYm2sfJeKxWBYHu+fE0SJ8JwDH77oir/8KJ2sIzeCoMoIbFp6Iz
zBGAGBL2IUfwsXT9cgUzSvuUQLhouvRW8SEOqTyTV8+0GDQkI7mHaDgdE67N62H5nhET8FO4gLWH
+vhm0cXitJn9HfzVrsD22+rlZYN/cu7yPumSxeVB3ucr/cpW25JHgQDD7PD1iLppHJT9ph8YtUT1
sCVq+NbZ8ceN1fRo3nwvO3kJoCuNpzO4iqoW3605kUVYkRRPp589g6hgTGN/rbPjm5HV/m0LrMss
vOsGmPMCc7ug0WW8kifJOsn/svr6NkYu1exDXcOWQfZkhgtFPiEqUjz2KwhWe6bZZvWUYSHQwZzl
+Xt6f0yM8keKVLX2t1f9P02rL0CIgLJtzkdnskJ6Yk6wQccRX3gLSweYw77R0+nmu42y92YQ4/y/
CHC74ceOQL8Jy65hX5vuGbVDrNZnIWUHQylDlX55XPU41+5iaysrgbsMld2CZFch3/JgXwzNvhTk
XPlwdFd8suNDciaM2IOpmMYeLsUb2NjPkFRj3fhqxehVIok2T3zMntwGDHrSzMkW/zY/ybgbgdrr
ZNkqsoYpifAZqdv0a27busO2Epo94LOitULjY8HIsu+tc/dj6anaOI43GdISr5i2JK98+z0eLbad
IaucpldJ1QXWPiuwl3hIGKd5+oy1xTgpOinqbYqZ34YUirTKLY1mwveX8EQnW/ZfUGSRWW376Tjf
Y97WpI60t8rlXE0ckwtktzP8RE9MWnrPf4Ixz5Ov8xlMEL9LUoDU5n/MoiQuRYJHLzn972s/S3fu
1dHeb8Q3dLxn5yWovnx4psE2l5vxqWeAByMDKJiBF+2IDCkarkajfR4ioukPM5zPEj71bzkn6Sg1
WIMSHhCnZSV3fCFY73rz1PBpVIFhWqOAc/ht9GWYNtP0PyY98+ScEke2XWkCt9GcCyXUaltLaac7
1jrLPmVl6s5ydOY1XF99+T4Kyh7+GvZdn3el3ARflKNzX/YWxFedSuQeh4zZQd5JDeJOe70OgnJW
vZ0b2nBZT4PTE02ppTiYerq8f2+CmnCB5lcjj/WSALJDjLzblVGPtGSfZaX4LDi19GS7A6g+R3M/
ly6vfjGeXFINUPRcZe0XdGRuOiG+4cpWGdDS8YgtM/Xsik/61Cp8H76qhToIJ8pXVFrgoGyEloU3
N9E0Q9ZQex3hwxA7T2SLPFJNugPij6YynKsqGZJp/mD6SbXH8/UTr7DlWYmxVejd1fcgvH3un2Er
Ytsq6sHzDE6watRSITFwgzeNKrjH0qgHZxpXXWNvdrpxlCr1BTL/voNebZiYxOPb8Esd0xYI2cJo
BkzxVVnO1A1p8zBna1+ZFEqJMCqQgngWPtMNpw2/4/hZiTtUos6Ogmk1IS3wtI6eswLN5TOh4rHn
W0Afcljg/SCzqPaCVae4GPTsQ73r+AcrSUSexZq3Y1RRHaKVBU35mH/2JA/lHEyKND23LVYoBCU1
A+Mwq/KTH0ZUuzaahHH5FuqwkNhNpEoGk3o5K8k+IDpWitR8NeSi13zmK4lzTLT2GayURDv6xBnf
2g/bOVo+GvhauwpxpU1gEd+TssNBDEqrxS+jNNFUCX6q4uD87k9xb5Ct8UMo3jVZFgII0Pu8jBkg
ZKzW8CMfVU1C5F7EzUzDh6FkCMUkPeMAGEz/o69FHuNahoGhL0AUF/xOF9z9iPu3UNOQ0qK8qE+u
8haJgu0knb6oBsz0OMVDtxgTYbyZ2LhAkSgLWtQvY8lSeUjqmz4IDtbx37bn8Oc9ZdImoNphBOmm
VvUm/1b6Fg9YyuyWYzwUIY0yMzXsYBKysi5GDOLjKRIQrpRa/bmiANQQ8g37e6INyARa6qCBowdq
vTgzT1TeKV7AXx49SGvQv83PXqP3a1GXG7lVLASqtwWVeTB9AdG2SUp1SbY0C4WonhX+WttWhl6g
Ok1rdP7cI5aAX8SX/Af5kXDIT2jWWWO8cId29zYsva8oLbnnG0ftjujMDLxsW+1fHZTeWNsPFITR
1hfrTeHpqFMQzcQ3cJ3MhtMN4dx/k9MAT1jM4Wp/RBbrrq1OiCBo4HWrNpJ8uuu1tT++tvdQuinS
UVnNNokm+fIeE1D9QDgJO86oYBjlbSbxyejpaKN2wd6NImAW2rhS+pb8ikH9iB356RBCGtJU1cFk
ojzzxwPatrdB+QR97zVLVCgLKYavcQOJqmm2cIpAVbM9EYxe6t3hUZfNZLDZD05T+pEBwZ5wTew8
HpCDYO7SNUuiIwQddjxMzzhGPk4P8NHIiEbshTkUriilN/EyEhskOW24yYOPeY/o6gn0ijnjYJI4
CrGJIS76MiBfp7W+M431ZJIKYK5b0HpGj4MrJF25UFuAuc65vxv804Kxv0aRaQFsM/g3P4DXnpxd
WcckqxIeAVu/foOQYbgXf8j24eBpvLGsso0elgLAhS56ccHKkKbDlPnGS6qA3R9B9WIqkxtghKU5
Z44K5jA7DjZLENF/qdc4jmzBqHZbUvc12VWqFusU0Z/3WWQxjmEaYcC0sjvWlrsPGErMSRFFTujr
cf1iV0hAM3rkVlnobC4bU3Iw+tcu7MN2H6mmO27rFItkDYiYIr3bIsBTEmc2CS3Qgvsj8TtUgS4l
aVhkWwCL4Cq+z11oQY0y1hIIKqXDmuz5BtGEqXHCb/Q2b7tQr7PNBkVxQDFaYRw0ngOlmXHdVzCu
r7bBOo0O0p9PkOIhpBeCCrtLPqJctgYe3S4D8WNxPs+/aPrAPSMYhnwD/KB4lH4rd3biER31emm9
kxQtSQ/LhxDvR3Ba/CCZKyLcA1baTowRAXsMqt0WmegZoeRKFeSTyuk5VUwvYhhVzEEGdAzzDMqr
Ifag03Amfx92jJ1SqV4FCKz6KijKu38y5yMcxs6/ULSHpUxs6pYRXBDNrKDofpVqduzGBxt7RFsM
Tw7FT3MjZPlpCDntm+x4HyJB9LR2ToFJbbMHnclWpG8dFG5rfR3WuDYGaRb7yMCQejHDjaZeWu9J
seeM8mw+stFVbUl0C1SCXPZnuJLh7TFUkWdEQpyuj6GCLL/xcSUfEXatdQ6/4Xj/Twbts0lMKeXK
dvZO9e5oKDhrhkw3Oqas4tOyS9VrVK0/qSH2wpTPAcdGtzLPLiR68Rvvn1F2T7BnKS7gHYWN5BtG
py9PJcm9K04z0kkovS5kbrBb1o6CaeEhzrKQA9HB9TCNlJnhj2vjQ3pRy05KHFumSu2UiPq63iIZ
wChGO3eGnPUnnT6Cm8w+IFSJIjKABVXFxlHocHYcT76dNOHGVbknrV+bn/uM6opERVnFzfio5776
gk6RDl5F9YCzb3L5db2y7x+6jHiKK+YxTRLBm/RKjz9RYDhq1R6VONwkhUxZAnCkFTIMppXkoAnI
TUxiqBRYz//MDQQbbE/j2rzlYUPNG/y9nFDM4Pkk3qVtpk160522jvgOrDk79IOS1LXCBg1bZtn3
Dvos1JmDYSFhve0qz3WTec2uSkItSY3nnhEHfpOrzqKtZhfNw2nGKrUSHsWEEGYl9LygIi4ZA+fz
8fgs17oJBrS1cN6MGucbOI0APDPiDTWjY6eGbj44jWWbpF8EJWv2A50XkyN3hBMX2egCn+ZC2mfc
hem2Lx/+pEi6eMZJx4fuSLa8mmTrqhkGBlWq4WGbco7thLSBeLLf9VV5/lk5P/Uc29y1FnIViQyE
64YXQVOaHpFBkYou5UNrPXtAfRgRfXm4JLcNzYonvFD1XNVtKvjpI7MQecimhw7A6wER33IFR3i1
wf5J3S5IHLN2TvTwKh2TUEghSobZLYlzquQNWah+dPFXSdY5t/8KubqvpWEStAbP1bh6E9JDIm3e
QzNkZtfnzYFcJK5GXceYQwVOmKkvxglM54wNEp/xBow28dxCnRD357OS15NMw4snutREC/OkvX4D
7R8COIKPKXc7JU47GrlE3Ex48UwJ+fS0QafX/kueaTeqrGN3YeIkvcgi/w8JIadUwaZCy4X76a5u
Fej3SYnXSVjbjqsZIr2ZREZzLR8wT+ETEo6qc55luqjQM/HO/X7bbEBLNmb0iUX+hodcNuvdjgfw
qMiX5/XSQKtZNOnNpSztPQz/3gprqfLQN6NVIP9cIgzAbpitjyi2WRVLr+VJobG0SBQTLpBlvZS/
CJ+lJbRDHakKxP39VdSNwvh1YtkEvyBPNsWJtP1RQmy23CLX01WFc5znuXDvJbCwWwiwUJANk90c
E4DeiDz8hECTdXeoypQ4+mH2f+FVnFYwHR2O9QFj4Kr4TnbTCregQSUsq1lG7oRLrRfd5iz8RLjD
Syai+n0ePzHEwwMXRz1yFNuq+kgdhov5Ty0r9WsQarX7KtriVFRngLunuAv1e1RAcWSlMXoJj8Dw
RTJ/LVCZ8kqoYdwI6XljMpSA9c9GOqtI37t0i4D9pt9DSzibz6IYdC3mQTDpPCS1NiQO7bYz8gTl
HU4e1IODZn2DswTmifBrqO395fKqstjzjjw/1GUqQDc2Vr6WRUkbmU1bXXXxI8CoLpfbTYVzQGy7
nAN8IlC16sTapIPE8f7dZXxZnpDgR0Ef871pyffFiyVIEi9EnmBWCH5/oEC5YHL/hViebwhJVqJG
l1RyAqjAOlz0zGv5ww7rO2ar6VCnKETYHpVBgF2w/doOgBPZhZZah41CNbyDsguwgs/JIEplF0Re
Ciy9zU8q7kxULbHYT1+VykKR+H9UoP5Yw3wmFtGifOk3uyXtAq0flT/cKEJ6oSVq8kWaspbxX2RF
imaXp3kJJcOrWQ9b/RX/zMq6eN+QwJluTTqQP2Eu61/o+8lyc3AxAHwSwW8YYDrP4jakiUWpzeQ4
EbK/Vz1iaOp0t9p8tlN4dd5+bhhCLGrmhcl9vQbx+oRUlm9FCZIAPCRtYObC5Gj8E5tLGC+zuoWa
W9jNdYiTDVv6pRdcmijx1yD8fuxHGBsoDguIQ5SVR3OLaqOg3YI6vPpJ6zXNjEpN+NRMWOe2zKZd
M7rwd9mC2mOUUkEoOlw3y8VUUhYhHkHwa9uCx7b0MWzVE7/9sdJlKDvWr9/Xlso93P3RKuUfZG+0
tnsLifdmjgpZlz2RQO4x2aeX8+oac947hAYaFFBFWhGT4qGkr/wy+ixtc9SQAT3Gl30lonbXA7yW
k87gXdNAx2NTYou2NR87MFzPWVpFVdG5OuwsSHOievVj7l3fcIpHkvbcmv9dup3bdHch4nbuvohE
xQi7/b/NkKIUuFw4iS/boVmvykr2lSZSw3ODowB5IDkHoed/AhdDb2PnXhn+NzuiciNTmc9cj5FK
XU4t7c0DD6pNZTP57n+q2LnTOuemWdJg6tJy0OPxAsXaFd29mkkaTzrlNBkNhKPW1UTLt/J14uzF
peRmdQFPB9UETEuDAhQDFuJ48VzEcoLMmCx5VlYxLivrkENu9Usa1gfx3WYHDA67H2DkRos84mGt
xsoqk21xm8WvfEkjgvJ0fLT80QXSFa/zJMDv3h7lbMlZIXb+oEAc5cAE63wCBRDTDMyA0WbcFz64
QTQ61THD1Cg3SMVNc+PgQzslcumo46oMHvhH+mtU8eOEimtRHZa6K8fAOmpU+jV1m2SAqnLpKx8F
aKK3iPeQ2FHSYiodubinij7qtqPsMsg+r3IiDSgwL2kdewi5EfMSzviVl9tZGGwjVEIhLVJaaTFT
jzfUkbjxKzpicra/i6jlo1sfSEnDnWVh0H9Ny/rgZlZtK1vXfXzLTQNSpH1FWIYyzDHbAlbGSMLh
qmJG/cPoEIHHRTw0IBH0PyjCmXTjxSemQBO9q9h/o2iqqEeBu9a7vDBj+RzbaZ74VHqpW1jDKOlt
JpWSGu6hkbGuL2J2C03F8d8GJi4sLQjIInWfjxmlIxxDm8O0VeWIVhW0v6xmOBjw+Pr9uIDiCWR/
1IWMWJdbu9mtssvON0nD50KLj/anXaWAENpM+k6YVJXOCW5tm1tSDs5GCVH2czRV7dW33HhVaMVh
LCSi3/BalKvlmQe+HyV1qsX4U1KnOoe6FAW/WhS3XT421yiGXJwUaI5uNYH8fSrw+1Nb+vYm5Dtd
BhopprGibLTqmyThR67DOpUhG/za54bFMvL2rtHrv8MmiEx0LwDcKDzgV1rWwMtOtbJUWZLIP1N+
fkFLVBBbBawLc6NzELYVbwvD454REUTfacld0tY/BgeWUlzN3AV9r5KbbmPzE4SvgFUhz20rwIwr
YqQ1FFKOhq46gdZFRl9qt4C/vhLvlL95bwfyday9FnPqSH7EDFdEPE24TiIxr3U/jPlF1JVR4s5c
DszAiW9nrqIpEvZQ3dFCIL6QKoDhi2tP7Bzls9p1jgNw/LoLifV2+/cFmOeOJzjoHNsLHuXpG/uR
Zke88IRzpoYHb/KwcUvUXd2XhMoBlsbbjWvdFeW9TzdZy4e6VitUGoylV2w0BCjxbHSH/6lqZcp7
dvXhegS2ILEYj885cWrD22b6XYowLRNIFxJantCzR3IXB1M5QgmNAnVkLqKiRI2m6TfO+4NNBN7y
n8B3FemSrK4E8rm8cLDVJagwBLJRgBwZ9RcKZ8NCooIrmm+rJ0RX+54pFQJwKrr4aRQ4ej8hYE8o
oOYZB36tQfunIsAS4vFeq8TzCu8AEG8VyvVxuzSOft+CVST6j9suulo1bPqkU4WH4NKyt34L/4up
m46LRI9ICjff2HaiAirDJB4EPd0MygR3tdF/p81LFaaHKclPLwqF2B1JGEchnBDDf0sGFYMJ2ap+
h82trZne+XPWrV9JW7yT0JH0ueGlIys18jyVrQUbKfB9pENKmFD3t0OJshATBoBnDUNgpaXSrSWK
g9zImmPnPZpfCJWGbatwQLbA0Yxm1yJGyq2LVfjU5HDY1uM5wdU9pglUc6x/mo/T+ZuIDMkc4YtK
9NYyo6R9CI3/CZoHLpOjNUloWe20Z9IT2z8zJZBc0aJxhX+SIjt+6X8Jjr7XxAiqXLD2e6GBazjR
/0ffFLeLEpR8ghnrdhMWpI16dmcCaKkDKNCohWFbfMIoj9FGPbdJmD4z2GEUnWRw2kne+9fHWha3
H6+JmuAZ98nt7eTGcUvYg0V3ErEK4cpe95AcEfi4Ps+vnEYq4yWN0mFzC4d4wbnYORDSaeA5t7ud
UNBjn+60SP0XQIllRhI2j1ELvXv/ILVYUb+EAOrZH3eTBqAr8IxUtBrc+IITVFzrFaV/0DG9yN4K
ioMXt93r7WuSLAM2ckCaVX5JXgfhgSpL7Um9T1TyGRAMk8CouB8QuLbGjRTTE6okWVtVTKwN7sZV
tJA+RoosjeRZ7ci1U9dMk+2CDx3YPY19Itqk1hrjGLqoxjmt3yMm6S0r5bGkQax7jGYFksustKtn
nRV8xMk2wjXNhvntw3jR2sO33KJ92mBFQT6I+hG2SqxaecpK1xdH6LjDeBZoniJJR+E8Pf24OjWa
moDLFQBeMC2efbC3ANuWmuakGE/G/mWibRV9WgN/OoO2n5xHMkBuxLpaRhJaNvmFZGdSrGLXwkin
TgUBQJZ4p33zGqfHmhnE6cwyTynR4PtmOATPg76YjQ9du7jwyp3APGUVh770akXKFpobhA6uPWHl
7nRyKIm96aX70nER+CZHVRpR3MK+rM+IczK63nGhURJJqT5WI9whaSER7GywtesUV/uzyWZo9LLe
Hc3nFIrZBBJQG4rtqy1IZeL5AX45HaFOmZkThOuBf8XD0m+7xFDU/djYv0jtGWA4LsgpP/R/23Ko
FB0ZY+LberVBLcmBf7kf3vc81UCV1K1kKo1U1faSYP6CIzsHjzT0Dh1vUE+EXZsxyZqYMXMpCq+2
oE2vNT6bj6ZpZuznqc5v+d8UDKtalSSVIRIV0SNKxeLLH0x8uT+4CRQEmanA6/U8vmjce5957htv
CAYgT1AS7KwPtY1epAIfK8+s7lM9EmPB7zBuD44MsRfc44p3kA1U6Pt2N6VlQKQnghjHiYA3LqRZ
x8zTlEOENqhlJRPgu7sRavLBdGZJYheHcyOFsl0rEaeffJzj5KU+Ekpjqglq/WG8Sp9TcOicywWb
K+tEpE4c4zTt+50fqM9N+m4e0kkmuPMxdOYkXc/A8WRCw2dd8qGC9GIVDkO/32HnRb0LplQyeIaI
BQEpbZ+fpAS8o3s1nmL2yyvj1wncHxbVWBCo873p06XvDbk9vD9C36sHM+MpPPoC1FayyvUEP1So
2GQS14wLOHv9vAE2KtBjKm3qP7vPR31zZJT6ubXKtr0XmMEH4hkISghApiCvLWv5HED10VqXjbYP
J58D3peSr2iU6uDlyz0MQu20pDXL01zoXsl+pxR+D6ly49FIpT1NRlxeF+YUptL2nWFObE26fwz6
wbmm8crRV6ZD96gvGJfUMqXr3tAwkYqlfUEwZBwyPP6sL7ewxE3a5DLelUhMeRYnJ/uEQ5hgPs8I
JSt2dyDaXBWkEVdXj276FyOQCOw/MmexXwBgxdQ64YPzH+5OP8GOJeE+lFvZ+MDJywtXmVSR089A
hJ6nvxGHZn0sFd4eTq+RCOaBA/B/xUKuCESGUv02CHT3G8FzB4jZctFWNVGOHLlRhIQo3k7uwLoN
404yedjMC0F3lZeLH7Tf0DiL/bjoHZNJjP5r3UyhQQdSbv4j23GKEyrHKpSM3ILuv824YTsMIhAE
2OndMpEDFVnyAaTTdUYcmRNhEDREcR/qij6mztxKfhQjai0u7eHQppfEv7t1IAvqSKYPc2cK0Efb
ctuGQDIIEmh7zfHCyBDgceHyc3UI8nB1EhL75xcZy2ot1E4HfM/+RO+hJj8qnue7gB6UjhR7c6Ps
w/2EFPZH8L8QAx/CevSv7hAI3Kv2r/av46OkcWELz7oz65ie6I3NSOCrQUoTiPSuWgOwLcJ5VsuR
iwGT1S/4CN9LeJrTF4YjM42g190Dk6fElShM2tU5tLns52Eqes+7grn3M6WtlSotBfZuNyFfsnaM
GFY/+1dfiL8bxpaBTkZa8zKVTGB770Of2HR5q9S9VR7n4ZDoBsFomew4qW+CnNYyC1Ka/sG+sLPj
/cGL869uNcJc7QjV5pJYkwwU2ParVVDeWRAwYxlUYY0Ax3bKl+7I6DAPSzM2ZPmSz74JIQ2enw70
gv9uavYcB1tc6sWd0WKegWTfTZ5GmZXlR2Td9FVdyMhYwn7qg6CpztOkjyoJUcGxaYXvB7CoNqMC
rylsHgGMTlgb/oAPpr30B/FJJS7eNX3M3hrrQfPxjw+DSP/MzpVc035TBXNY66/B+MlrRDUaBb0C
0D9Ar8ZqpmHtFx2mRNQusdyyGKPyMFUgbArikhB8cTZ1hVACJEzRC1xI1rldtgz4VK8HqZ5AdW51
VS9QIJ2HTRby7QZ5eCf4SBRqjGteC5XXRS9vioLKAbmqZyMifstB3GIxjJ+ILYDaKipSR9AtpHnV
7rWHqUkDw6DTCJnOWktespy2ZiAA8xzh53V1W3H6X4NQtMKtoJzaylI2kn0TWriO4RtdIs2W5qEd
xVXL5mo3yd+n5a1cqwsNZumkOYjyIBG6qbuYRzu61KwHwWd78F1eBMr1Z15wJUiY1dhx0HgvH1x8
kOyIQeNUkFBmzsST/+Vu9+cMGigtaoshPUP5xXgr57naAONWN0EfQ3yjjJCoc81YGL/f7VL+cZ3W
Cr3S9lcx7k1KYI+XfDSmYiepm5L8JjnOu08/3VjiktkLA9l47NREg48BksyXBRb/ZxkoQ27QYkc+
jlBq4dNW+oqdHgWyPnw9aFI+gU39Fxlbr83wmtaLWgnquYtALIYwAxoX9jf1Yz0hrbXB9alJNhfs
drdQjlN8ombMJBeOLuc6bO03yVOAuoIcee1YwjPr8IvwIrhkohOJ74MzT2eStbAI/PRRcY5mTLxI
P1Coc709SsfFkninwaM+Xl98UbOWT41bZ2/v8dG540fVj8Zy4uKeY2b0Qx9xMo+Yea0iK0vye2Iw
7bjfIICJh16Vt+vBbmaGdusjoIx9y4VUxaAP79yRR4b2brfximPFL6LrNF8Rwqs6IthAIL2uVS0Z
+sI+pZi/Y4ifsgdVj4RNZPkauqE8jrLJokND/cei7sf4gMD504uDqVu21oat4xGSatZMjECdUCxE
9brRCfJMrvfYIuGEuTuu0Wlk1W6dYo9p4aa94nXCthcxr5GJp2F8taMSc+mCELPoIKy2GdA91oxl
z7rVGVmlSSbFqX9PMAMNmmuQALAIJrnLHpPYVbVpZiuht0ZZcExevj/gC/v0TOrS56lfIgggzfBt
WCUiwxedmmhdKS5Ct3jwNWDCZxaWv6Zs4LI7ewod/PMLy/F/mVIWw/YZoVANilghrGXbh7gfcBF8
B7C1Xq6pDevv8zSzQytiGubBxelcghqINFMZXDvn9Lx9Hmk3AL5aP1PKxAVeVUX/aQxulgJvTLih
b4G2x29NxGXAonwdCDp4g/3gxUwDJmWGct35oveW27Q6wECxuIGAKK61iJoU9m4uZXUnUlcANi7y
wU/wbaJd12Mmi2l5tZ1inuJAiecxNgYG34CNd37D4cCddMWE8c+JzsOYmWDFqJXI4q1zZKhD0bVP
VgHlUeHq/k2WCK4CjkdxEq+S90YENJhGRXHOFP5V7FyNaovyrb4iuWO8XXq1zsi8gIt/T7VyY4VE
OBCuwWpLY8k5WuNB7xVFwdvhQqFVNjHaF2nLYy72Txjo7gx1WGMeqmDJHQ5VJZqhgB7fEt/bn8dp
zYSH+iOIdujO4kgMqy5uI6vmbT6Et4CM59HvQK2J6J0QZQ8yoN+7U9wvAF37fh3BrRh81wq74jc5
SrHUt3tG2HTT8ieVqxbPCXB5alwuJYvyA09kZ40G06Thcylc0clyPN9Yte0I5TQQC0xwPQqV0PxS
ZYnO81UMPY7VgCdPKoQ7rcZDbGuBTgB7l24BlpX/6nGfVlSibS5Z4hK0ca/t7Dp0XXMttN8zp+hl
i6mbdrKJgcNDy0923GvkRxV6wzTenHhTuNfrHqFqqZS3JHEA35+zruI2t9CQj2Fk1z8Yl3l6rnXB
U+Y42fm7Wxq9ZMaaCeMADUyiUFfJ/D5UY6aDtcwVJmpnP5ppS9VLv0drg9I/hP09aeWuIcRN9wdI
imIqghiOPzm3mvJDMA5uJIivlrv/6ACh7lzr13K1NQeo6+9Hf4DDb/5xQ0LsxQuc95iFriHEVPDc
cFuOEhiOQ9EXQsTM09CwhidXdyluTwfP1AXuRTVk/d+OEdmz6O7Vfw7cxDs3iz86nQe3xIFf7fkl
4MqKU74S2asjvTDPnyMbMC9sL42pf7myY1LlWPNHWQvBKwlOiuRPuI0UUQy0pnwHotopHlB6VJk1
DnahF1Wt9jZ8T8Rh/uq4kvC61DSxolJdLnFbBywtslxok5Dp49xeOfoj32X1sL6na7gzv9HWgtkn
oHwPti/pe3q3UPTNryKLO1v9b3alALpub+pi2iqOywhrOk51tYqSyLjEj72jyhaocx5rIrkGIbmU
GtsGPpY/Jmjs9AdYt81JOtPQNTEJYs1UcinXWHg7tersZnJGFpqT13J1tyb8MU2XRQ8TIdxtrvG9
Zd71zjkZOfnfWwUfwb41elUvymTcn9+S67eGRjHhE4jTtQzqbeZB0bRMhb3WwCzkAsqihBRktMxv
ruCxIQE0EpMm9R2nKeV/xLAS1hdrwWAEuB3vzGy4stNhhezZWa+C5y1CaCTk0aP2F3xBtV/O/nA/
0FznVuGI/3GT4pkPVhMtothIDbCIEmZTpJoyK5huK6YuZ1X9/kVQm6KuVFk1kErwiU7sIkH0JJW7
37AgDhKEGhyc1e7gtB7mErOEBnQh9k/16o/Q6N5ZQdJY7h6KOzA8HvfWrMyY/+Txd1w7To1cqEfU
yZ+uHNsaTOiBFQpwaZQwtLBf5dyYXZT5LqMaYos0pO6xvAtVk2UM5ROouzOwnK4yr2izKN8L8jUi
ID3F3IUCwpR+tjxmAAkeL8OEQDKQj2XFFw38ehSqGWNhOMEYNsNtsUAiAhEBQ79NKie1qERYqXQu
1bbxFk/zAUoU7qsSNDvhKK0mWlqPi2I4EF+bbwQXlFYy9zi8b6OOC2K6zmv2N4Vxt2p21RjGPEGi
3eUiR788krYCqrAIjWhtTbKVXmeYmI58UaAVwoIzHXpXHkPpxNw41IJ+0Tz2W33YUBH8BlGrhM/M
JWysJwoDpS2cO3cImg65eWfHo6z7Ew+hy+ZJKAc15eA8ijICEEqOeTc8nodxNZH1yxqazXs7Fpg4
HTAowTwsZBJ8Q52QYqzL9WL/89d9idgNFxVF7tfKSgdh74oZpP412CsHrKrbteNnIxSi1+PxHADs
jqesUU4Qz7SlLvAuw+xyev5/m2Tnpod8fEOw24MwkHrQHYd8Xy1YIP77QVfLlB2q7ypMeEhR2jc7
CuD1Gq6656/WYVVXv6vl9maoJFhw4EkHlZhxzCJwIreZBwJ1YEnFORhXkP8n9x73aOCNVDEuaNf7
Rg8mXJM99ZUAyCSDe1Yf3OWAQzDxe+6npUfo/+4Tl5NVJCXLJH6XeqfOuGuCtUuwwXk4CtZp6fv9
lRgZhXuQkD52k9ulVOIm5dhVLIYXigycyu28fVgaY9hHav4TaWG5MxNLKE4McPIGk7L8L771HedA
ZObLGBKXl4jSZz4QgdVp2kgqhuCUvJziU3HS5/QPIynvMVGcGDEPumOyjuUzXZt50gbpIqjX+Gr2
zXrigF9xRsLZT1hEmz2ITTRoJwl5tkqFMxJZyWbfaOFUS6XkRNtOYiKrwp+NZi8Te0nbEuqvJ7Te
IYVcxPF+6SbBZaH9u6TWG8+9W29T3JBrLKD6umqaIvZH+CYZIHt5rR5BDh8G38IR/2pC0S1HUrrx
3NOyEhAL/cZWHqYoCgk9oTAf8XAczr7hXRWDrrQ0wGBh8cJQCitzoxzeihIWSLkliMqnK6j/nQdM
d9aM1Tc5kc51JW7zRZ1ETGrc9jMCcSWPgFxo1e86ZVPfLU6c88dJecefHsERi2RWWnTIJbQLVEtF
L1kwWxn2RqeTvDnm4XXDDP9rf3xfJVqvVuUFbCFufGWFJ3pycryGDQ0WoUfxSk7jakuhirS77Awg
/ka140K2ZNFVTnMHhNheEpojJ0lMWJg2TJwpeiqmKhjXaX4YzqV1P1ax0uG6O1HDPA3tntpVqT1H
qpz5y+yIAfnuxgVt1hoBw5KmHBR3K1lzsAQY/K1quCt5SAbe8CHU6DQCMncL8vhnTMWA+koHIPMn
Kkbx0Yj9pQVo4Sjc+e0/Kn82KGUrw+A8NLAMjakGYIKguZdG7nLAxTt6HgO+YyKu8lo0tTB8qGqz
jPHFZpn+6ma/+97VkjWd+QgwnEZuDXl7ercXXufMsnQkuwtU/mniZRYPVpuN6qenUCg5069lPqJI
xc++D987JrLr1JezRMWH5kTsG2wU0heDM//EF/9z8f0mrHMRGyMa9tXci6g4xP5mHsjLKonEG74A
FKdGgP/SwShlmxixLC4yrSkMK+zw2zWWn+wu9mS1vVv9JOq0KGH/c8dqjfr6++VHxwz9CXoYxXmE
oUYBPmlBsc6FBLIW9byuDo/hQm6+Iywa47WrNH+SkXHRuEPBNKVtsGB4VH+PhFYsitl2UfwtBp95
3v383d4xg1bXW1p8X67cVCHzFYwSZH9+4rRBsaXPoLXGKJFyn5cxv1PqBtZ1pCuU5sleWCrg4F4G
w7Im0RV7C0Py8MFpTC/y8U20zCDGf3jl3rIF+EOFetxI5EUMpdyyUaK9vq6ylzs5FvN1d618EDjA
jve9ZNGna2WYR6T3A99zMZFqZUDX9fIMY9aS81k63q2PLT5mvpwpSFNNDFLMBxeYqTQhtesHmNfv
0sNkdftk4XG9qcWSTFUzcQWUvcz55GijLS7yyqTfda27vlk6O62+DLMFWs2kSyqiWeealLwY18Ts
98gvEzSv842EZGZuT1bjQVQ0TJgcC44jsEQLtWDR/XMkYu5ZyZuTc0pCxm7t32irAXIJFuXtofWV
Ver0qGBWIDj+WdZRZQLeBMYYfAMIHrTnCPZ5EqvvcdC8pBJUFCtcU4T5LhQh/cSLTjmvMcsI1zXR
PGFSH1OG00gr3aiLwzVKSj518vw8xiFEntfTsr6SwZvZZXkWE3phAwbxCw3mqVsdR5iEPRYbua3e
eZ8BESFb/p+KEFBRqiAaivBnv7Op8a1R09AWakJLGC9XqARsIJ71ZNbaa+tqSYCx24Ok1mytYaQg
gdL6rwGRmImFQQ9QiEzQ5RlEoM/ogBQtlYIPjdPiy5+J3c19V0Ny+iAZnuVEzWXrj4Cb8t6xoFma
3cZ9GWiOKw1TyDuSHWojeIGvhH8AJVwWKfyt7hmNy2waVFYJ62ENMsqwce7apSuUCmZVsr7PZu/9
4Vcl+AawI/cXOL9q9l8WAeD9SXhw6Reqsvd44+wtF366ZgIXPO1kaOgzQEK9sePfEY9nVtHTdzmo
asbbaVgVCI5aXjUbeP2y6Y5KEaXcKkcZFk4V2m1HA+6bw098Rs1uNkqen4G7uzb6GwrGIgA6jZp+
GUzvG29Gp+gbIs5UGlx9CKjH1Q79VX0qaSS1aRIbgyiAR8vK7B2uFihzfh3HpRp4FadmwqIfxzpE
wnRC3ycOb5yZgw47YfeZtydUMVzkGwtcLBmn8n09AlfTmeTGyYa5WltYfV34RlC8tBucN4Vfe1P0
zmcf87g4oEqvVnOdRCJubJOoEBwa/KAmy6nZLwuFfKfOM0OVlsrfGU2llP8ORn2mcjLt2vDUJlio
MN7zB2ApXIohfsJHjvOkeOqyAp+dBg0+jy8EaMdF89EIylBw2YYk1g1b0ZgsKOTJ0YssbbBCgQq8
gxhewPk/eo9ReibUKfjed2GlItZTxCRLBEA+ghjSU8lUh4IZJLK+NYAVWgiUjbbi533poBL6rpws
PBeMFfdXJndSiKLvndUZJZInTbos/xBB1KGBXRs3xCpuUyFgsRg0GBvfBf3dMWOUyqXwnrIhSlJY
WMWaS3+QUvngZ/vuk4xHPWJD7rVWmF/S34+r8bzhfbDJmfbUQFDgMSZRn9f58mxbZwEndUhslOTl
G2CqxSTGmLMaPTeQg/V0m2FTbosyP+vVtdVw0iAL44y+D8bv9AwSzlUu2V7PBu9Dh7Gw3a45ZZ24
tjmY3k2oV+ZxSkYJvu/BVFQNuX5MrkVCWo7GHx7go/8Ff2scA8qHzLugPruh0oVBGTzJNl6bQbgf
mvmPQ40jUPsdW3tqPPeQjzQNrs6bHF+s2zy5vpCTg8GhJansJZQqs7nz+AdRQHrqmHoNydw9iWhs
Q+c61DuDFUG/VAgOaOq1qbd6Pwj7TgSD9ymeKOZgtDJU+5eJ7EBhYDF/7IVuldFxcLLbjktXorcg
iWtgqcvhoG6kc2dByGLJDT/9yzFYwy2ItocksLno+52Zjyd2aK295Csf034FFVVPhsVsk/5Tkn9I
WafPKJE9+Ebj96tV4hF16QQsWkMKlJA0XiCsDt0EXY1jwWk4FQXFBJuvbis3jy7eYIyrtsv9eq0L
7fIAlOfPhTrjuJqr1zTM9TluKXBYctoseSbJva7tSHWPtFOYZXZbwyv7PGuJdQ/hr2rmbQNqjTRp
C54C+eC6ccavmj56KhxKXDXacE/Ky/w/f62sFgTPQg6xNMzgzTEXVVMK+4EaEV1yqVSBIUxFt5F1
8E36pPGX5Rmy5yGpswjiVpDkZ/iyuM1Mmp9912wrBe1hKTIsOQDnbiKEGsUMCUhhUzT5fOJmou4u
HkqvyhTYH3Gdo0H+jYh6w5qKjgj+ZPUCRpcUsk/6Jas64KWLHjh78H9iS434FF0dNRK2V6G2JCy6
qY9eNu03zbul3fo4Zmy9xNm/9rlaNKgQyiT+wuwz7L/CHgWJNY6rwyr+SkeQodFlSSeC++4qrNDx
Luk8tNXHbKT0RtPocpRHF+7iRQWZc07NvP4lJRsuO5d8zwxV5biUoBrJ5Cb41eqBZ3XH5hlkIHv/
kp1GAjQt2CC7CdMTjYF5NWYFSwH6M9q8cnfDOFFOlAFUz2ndn7i2DmKrSwrZtRl8UL39iHbYBiZW
RNYUt75qRdhv1DKqRs0/5+MFL6XFa/eRWZA6u3Ec/emlJ2RTC1AQZksrC8VcHsLs1tdZbNqo/dTr
r14En5qMmMgJovGgzK3PWRmP7HGxoMddSHbuxzODH1IaAsjEKIW6nCaPpethmrfGNNF15eJVINpF
dw+BiD/GYyxkMznk+OHnCgp+9LBueT4jQuEbluTvXIO7k234KMXJot3Oaoe38b6Ne4wQEA/elE8f
kFZnlafZQXMbml7svZCi2JcAchertri9FkxPxChz9n50fO0rDZZy8rPw7ci0UubQxwr6hyiC18se
TqaZ2CiCXE4oVhHS5S537xHqMPFQGpterKM8/bmOZ/vFXVvV9gyncIsdSxm5jrchH0DtzQMy8wOH
Ttq6K72ZbnOGbXJd2O7Iq/axihNTa2t9R4QYMA0ouwMjjq9W0Ds0qoKlFng1VSX5n3sdJrLJRNe7
H75piPkgg4NxtsOa+/aACST/LOeqffPD10H3u66U/h7mvbcrOwNWReR1eKWQ6XjS2JO98p5zaab9
ZlQYNXS6iS85LGAOFqvnUpO2JUuGDWeoEiR0HIf+ufeoN4Hmd5uTreatdU/wQ44mj1eYmyBI96U/
rA0UyzRTjBeZ+v8I2Nnf+9xNeM4itoeEYijligrp+mnyYPG9jjf/dKzTJxDi4CJ0SmYTNS3Cl6jc
Sr4gPPjG8mFgRiWrO8eN8ZJAaRYKVrp2W8DGppx3/jTVHN/rhmzKHvBnwoevSlNozvg77YjgIxdr
GxBKQg7kCvxBOj8ha1HpcEYjc6hUr/ROn69vTR9eB2eeLon/A7iZMlQiB3myG1K0Dtx+RG1iWA0Q
hHh+djHcVhLRaCtw9tMx1jaMc9j5uadCw6V8KiDAliF0NXj9dpfTMI6kujZEtfSkcki870zNyQGS
ej//W+UCmxzjL3BySRkRgqvGihZGI+J3bfBeRZJEt3zKW5t+WFDTN9RaYlUjc7QjkMtszxQySaWj
BBCFnqVeOtC5oRMM8HWhoRqgytBx141xiktVvQ9H8ToTVQvgXgF+1MI2fggwZpY3rsoQlwZz8R6z
thF0PAjZ0t0pCse0eN40LVN8Sjd7HjiPFRiAKwqqTUSX+nKuy1YHhHwotRJz9pc9loofeQESF0M2
0XTHqDIl3Sbz8zEhNLpZiM5T8ig1T1LCycMnQOjOFaTipCq6z5UoRjSBmAql/loJUCokS6YrqTUO
8kVOerEcfuScVe72ZrnJTpLCWamDif18vCRqkPqSvua1IjgYg+fDGPH0TJMaHro6zA6KjQWXBlKm
iHg7mRB4KTG9gBWaqx2JhTTZY0r/XYqfa7bYcYCE1KFWJEJ7TaGNmXOrwql7habCyJ2Gugln0F0d
iiXeSDZcLJu2L1hZaZWU+rOIvgs/7gSM5blzqGo2RHs6r2pgN3InRDBsGIyFGuwoihkz8Cztq3n3
d/UDs/mMsnzhdtVj5C8dWYPsXnspScwD9RecNn25RUbXuv6KyIi0/Ayp3uYv8m/B5ssvDKd1y4js
iSpdLlhFo6D8xGLPc4qA6DVTgGa0x3ig9eXvHAFXpgRmHOMLCCrGE5520NS4Nk+taKkD8Lq54FIl
oRoIhb8aLqKFzWu3DXqZ5rBsDX+UWovxZRxZmesPtHcg8O2obQMNuIc8H01yDAYdLPzAK1olfnv0
MbzTG94c1ZVLio+tQTikheX6kFacb7ZTf6BzHWrx8oFp/fR7AGK4vpc4+AfGQFnZfC88W+1QmS0F
wzGhZOlQ+shiyVfqrq0RY/4XWuJ0B8ySep1zwlM94WcOjFQWadGUWpkSOwQojjnrj/NWOlZ/v2cj
Q+zvV2PC/OjB6UfkE5yolre6aVinbYD6K4slTYsdt/ZSLhZaJ5R/tmNFNMfRa7A2AgxRH8fqNLAu
9guqczG3n13FQCI8KTDQHwDdBkE5cjQf54ilmipOMA+3SPioBToKObWjAXFpQl92tXVpfTtT0v1l
dYZmG6+QVNIqdcnw28XKYlGB5OTqV0TO63MCcj/xrA+gLzlDJOemnIQeT0MhN8aoqSRfb4ZWB+T6
ekyQoOLJ8OaDkP+qpnYcvrkHB+APZnOstTh2IkQULAF9iCFMoTqvLGjO+R1iUyHpakSBXsLzGtiR
rytQJkNr54o0mBEA6PIW5TjLWw/t2iFavJFnEQwjMcMNg+oxHOVLx4bquPa55Q2qkVri29m+eNWo
0QgM0EeHB1URQlycQrdzoJRmObD6SOgHM598gtwGYTRrcoQPeeaOKeDChhk4w36N5RyePiLb/2sq
ji4MQpbm709WH6K9cf4TEcvyTQwFDZKYWYvgmDXieZVR9MN7X8qq5rzaulmMY+R0GMdHEG0WOAKu
b8yohzdA7XjExGqxAjsTqs+x19QQjkxZQsdK60MfS5kkF9ulL0zrJIr2oLuP/rjUvjVqr5OThHUa
VH667EieI4G9oazd8odCeLgI6cPSApwzj/4/HNgb5KHHFIixKktjN2X7edjM+0HyEahJFAvxGEZA
PlmbVt77RbqF9uqkrZrMeeko/LM5MlG0jvxdG8ukVghDk1UoEPsaNPSp7l52+TA7XLWy0JPWkB8k
q3T2cuWde0qH1GX3NjAiT4gYHI0SgVH2p4yZmfYb+Xutalr/PXm/stA9x3z/ZfDbGcFhKU5COCu6
CwtSArnILRUvqq0VY47v1+WZWZPOnGn5hlowh8g99L1+tskq+v8r+RVs02an9nQNd3Cn1k0o0JM8
r1VTJ8idQEjE2FxBjNuT12YezS2oza/3ZhTTep3KBrrPI5WXfBmMjMRMP40o57mGph1hzhb7sorS
7VW9lGHElw/tAMp6iJ5ZCgMnXhSW37NjvmvqJVoWuQ/S764NIi7XP3jCnItNbylI9Uw2JPJ5GbQT
e0ZLlM+yc8HcNtA25oeZpu6ASh0aVGr1TYRJf1raQsmqRSpc1lecTvRFf/gBxkX3sxlSFDg+09NH
CwN9VSHnORCR1S2NCesi221lMS+znOJB03jYe5KH05Up9Ezs7Th3J/z5jTs7WIDNnfnugfOa5a8U
vGllf8AfUAsdjz5A2h7bewVjPva2jjPy8bvvTLbSzF+oiEDMBLP2eeAmt4TrfAXfuc6Veu/9PhLE
3KR+mR632DKQO9atqNAsiZUHXDY1aJyNdep7ooQQUpWWmKg/f3oGmJLYGucNC1R71H5cRn91ItyP
P8O1gKjja6vYaNx6KH6WFN2gCgvIHi0tVsL5UR4ua4utbIk3BpIzrNKQBsEInoF67ncHYCLVhH7L
2ohfKJ45jo329Lew3u/mKCMfIeIjSeXBddZ9P1yjR1j0DN4YJ1Q+OXoMj9aWISRst0dl990csdEm
TCJrLeIaW098JUZctgueo+bhYbHLPk4/WXZ34tb5zKaAkNM37+uZVrJCpVpqmG0A6HGlQxzyNi7J
CUUbl7BH1N/rer7e1zt3CaXzDV4VltPs4jhMx+cwL8duh6lPafqzzfgc+zGBSiiEZOdoOunkm6Pb
YNPMG/VdkvyKKm5x8e6EDmKPLUGmMou+pPmT7yoFR+Swmt394ZswjnWTfSF+EcRkBIFJ1Io4G6vI
wGlLyLLqYZiz/cUa0fiqkE38B4J3rMFhBm4AIyU7ee1WyPvNzJ72CTP9lc7NAWoHKnaMgNMcya6N
jVU82U0H+2CktSstRh/41hpJUaYS4YalnOovMY6gy9VgsTsCRAIX/34LmbMxgfAMq2qSdXx7USnV
zRHlcbmPH/1/31J6j/O3fvt0t8IA7wqd3OACi+HHGAnvdpRc8HNDx9sBc/AIgepZzX0BD5i2OTN+
tXfr47yrXvNPqjYeg/3JUZOrLV8lbFUpVbvQSLk2mUOJOKSFGHwSoIDbkv5ue8a5rrVOeLQqlp/1
+flM4515MctQ19OYdtNWtBa4pW0mGtF9R2pqyGHVss5Crcl+KF46tK9SAkvKX/o0QyXJ62spbuQS
p3HJgHUEyVX+g6upVq6SAD+Nqw2o6kMvjHZjdz6OiaBPM76T/PqVFdsySthBhzYGaLRqEig1asAz
M4C/dVLW7ko5E091x6Rt/5dtX1hgUp+c6Kzi7y1Dvtk9e2+tC11Acr+OSNR0omdcFF5h7nzwC9qp
t8Tnxzxy9tuX/JJJBn1HOpN+ASJOOxltdwYBHIEbJQ5MARqbT2nctEHurnOVGI8shVw8e8RkLn0M
vacAq2LCWADnmZY4cz2+HPmvc6mkkOpkyyKDdcwpdDkCzdfk2InD8no+1VgFZZlZjPZm+D39paIj
jhKn8dIEQblhaIsUdJFmpAWRNzL6T/NHU5X5t7VHRo0Xy0Z9/582Z0jKOAgBr0WxirW3YUmJbPy6
nLWocPn6ZC+6qmGbJ1FKX2h3xvjS6wPmr997Q17RTHdktbsV/r9vb8LzWqS2oqaF1Y+dfvCnbStt
eUbypFotq32vqRbEiXYorgSDT1gT2L3HgUyJc3xEek+O/SVyY+VJK1BcxNbGhMHuWIq411kQV0UA
DpA4vSpNFO8DbDvhkjMbgX/tuZnwVOd5I5a5+kjnygkA/pwBCnKzOu2/+wsWw0iF3yMHZ3yVy+XC
5IyvmVk6ff68eIFEEvf7M5UC4WQbXDFq7ME/MGUSmPoDCkdsYmjFGo0nldDfob61dMXHgm922y6R
SWuxvRImz2N0ahEtwWtqqBqYI7C4SBejHRUC7HkIiJHyOtfr/noi9aV0yu/Z8zc9/zTk9MpYAfQv
7gvqGPbmrV0VEegLQvrhagppvWEO3qeL6jUIeFRKW26TEpI5Xp9irg++NxMxuVzOK9i+J2ZuhRK+
XvQftURbjU4ZrIdcHJ7/TDU7uj6xqjbSCV6Ysn1a9fRfn7y517hwP6ocryOXdP+o8OtJWvgZLmrs
b0Cv+qwWVqPIN3+IAGvxpZ1VlbiP4uwUVOXOv9pt/kJr5DURkssimLeu1aHzWTRsTZzCVj6M9c+y
5ktTKj9XB8z5fEeK2b9Yv2K/91MGAG39ymTpOIA836gbh0rNdcYanIYnf7E+Hy7sbRvsD6lZMtaF
vzT2GTBvM+anqloXRABak6M/xwiS6B/Oq5R161J2EtBBWGOsufaULhoyyNWIZTQbg2LXv1r/hGTL
u5c8A41LO/WTsXuEdCOxrKgvmdHo8yl4JhkjTkUgRfdaA0VGfwvP3uuKGPW2zePCivWOBbrCuXhb
hPolh/IHpU9j/65YoVLZLfQ2raIFAdxeYuI/iCOhOxhpgsGEvP8xdPOtlQykgiNqhWbMcETQ8TCQ
SnJOhlGJ+OVhjJdKjKg2E1TJtOMbRKWfUcse7x/tXdsfkw30nTZPGeH2lVflc87DX+xMqKH8RXVF
rMn8IH3ZiIII6Sq6SnRIH8nUebuKqW4BOsIuY9ZZTF1zLQowIqAHGa/AELlZVjQfsQOSG5ZDOOZs
n2+mVwtQ0UAFsKks0xivbIpTMDTdIVXCl55cAjYVVYwx3MKm5ozOqxKkD/X+mvqwMyJ8inQiQFww
BdUBqY1/ooMiTB3uT1l3cVKfybxR3fVoHKbmsNDU8WlPrW/T2lqLro9C8szg44mV1E202rhIYLLA
kJ6Y22qM64aoLj1ICmlq4KiDZYSaACC3s/iABt4Rz7+J0wfL0J3riBuE86zJXJ8xl9jRcKEJljF4
9Bxt90Jk6yNCFV1C6zPDHr6ADt2YpQBh/pGmtr04/tzXjr+IPrt8HnpE7I+xaya4PPZBt4MQ3NBt
aHDt40Og07Z2NObKvVrZ7R3J0sbssA6SSB3PgSluKf673tX2gs5IDfkqF9NHU0p/TO0Ydaeo2eEA
iJbt1oLYU/PyMMouomhSerjrPoHZP2TU5bsET9s31ZN2Uq38SlERy7woREpI9K5BDZC0iKpaOXXV
K/Tyx50mblyWt+aqM0CJGs+Z7e1l2Vkay03OaoguYQ4Nv9amkgu7cNro5mFGY0z9Na8fMwZoWclZ
R6bIeo9umB6v9ddMQ6G0Sk5W2CKcbzw07YPCQdkN26I0hbwGdtbrjuZi5cCrvsXQ+Qv9ljfmDxsz
NEIdeRa4FGH2bsEYTl/HclQhZxi2dzVB8omxAv6CTBSor3gc7WotVgCP7lz7I/YSWCCEPn3/p6tR
5bwA3WZDG5AEvDw/0FF3zEax2EzNLUCSqTkp5BIH4Jd9CM7dVUEpD7F5Hdxev/+k3dHvCK67ZUJx
8ukaN2QPxY/P7s7JSqNV4xa195+4ELYhMcDvyqgHp4H6A+MpP3YRQ8N8/NhJh2JdPnLE8Oh9rv9b
/ghCDOstM0wvMTXUCpaMj6LcWz3g2DFA+bFs/WHnjGtkte3+4qWwzOc473B2oo8gj9j2DiiVB3RL
UTrM/kBGYW3SVGaVn4CfBkHDiTj9vTMDrh1Muu3UZ5XXFt5oL7++a+9bVrqk6lkItvvBr7vHbhDk
AADayid9EvUM7/DeXQ4jPD6O+CwNuMkJYs95Jg1VU4JrR3ej857g8jCTo+CeWWaNLI/2YfRvQycz
9ZjZO1AnPoU/TlTnlrz3UdK6Z+UOotPe8zaA1WZYT1OW4WjcbmaWXudI5ADbZqNCQLgdbvYNWHsY
xPeTdOi116KvUvPIYPqhtn9X74SwbjlKJyAbooy6hikYiEcj6Mizt2vClkJBcI6WKPQ9UVyCUdCf
eRCT1YVLq6ziWqxlSoWSzaWTLY7ZWbGSf9Sl1ms1BpG6XXnySQBtcFvfbynsCS0nZOsnNqsknd1a
twaGLbIevQDwQ+6idKNW16FbQ/XOX4NIFusMBUN3HdE5GrCQJIYqE7F9dAwfITo8fKCIfOIE76YC
IVbCrutjEGeERxbPJdgQrs5yKWKyOKs7mOPwatAT9LuvKe0qag9oMlhzZe3gp/RsddSq2zBJwwOk
/iGCRe0yC7IG7ZWLt1/7MsfCL5TWzaLZdwRyw6jpMIZ/5zhSfRxTPYvktgkq2T7LjLwuFtQr+oLh
CwWw+bBJCett+aSSfZiH/ERGuAKzCCKLIkaoUbMYv89LSv8Yj69Vxn6kQRfd8EGTOujnhRJ+/JKS
IlxaSAjudmO/ywXy+jEQQ4PMP///Vyrgol8MOE3TARsTfM7/Mn7OkVbfpOQYhFZjdhGIVs9jhbsr
fzW/jnFua9ghq49QsqLnXx8seCXa2+Z6hDK2l8pgpFkkvHp5mV/EdBAFgnZ6rdHamCfXt7GJBZTA
zJbBlwLAyDe7jtZqOvilEGsmiCtnJc3pQLQaaI3XNFP9AK+5rqE9t7kJysP2d87tAITF+qMJ6wDi
3Yxp7j/C6PE4ZWEQpvZknb49adQGrYYoEqA1b6fs7osoykrCWB/KjjHXQGf6p9kXq7JMFjJ/doyG
sXG9ltB4+YPHQabvehSAWrSzv16kvQyS0pGVwqA63lhaSt9weABi4L0LbtY3Br5yquaD5nh0qjT9
5ufxvAPcEktmHtNUUjTJkKeeRtCF7kYj/2pwiyVTpQm+rSVm4D2RewmBZYxUvPH5EuGu3ltqwbfU
bwkh/gMdweLwq0UXjxew2r9NIHZPfTGgR/+LLkcBQg86QR7GCAzMbPLyQz4co/wuiOCQgdftetrs
DW8pw0DoRsofsleLzbjdzHkTplI+QSSjNjboT51MkTHIy2qDwQi5tawTcbSyOuj+hlJ+KiGkBM3+
4110eEL9wS18YfvAFx9DKUGfZWiWzV/XoLtNLIW/OGmOhg0Ldw7mX5Ge9kOcVAwJdzBmXE51MCIT
knZYKUauJNMoU0ZhnRuvB+Kr2WuExjy415bSMAFIah8sqajGyMjk/3BXORo4a218vKk/kUfRiADw
IjO9cj3eCVveaZzLc+njvprPPOLcB5O7Pf0Vgh3Q5H/1v8AIE8u+BF9dJ1Whr+TLuFa5cFHMov86
vZhXQAtC1FmyH8BLopaD747cHd80FcrWR2hwTvrcpIHjdQtIFfuGacPneJfLDadHEksHNm4IAIkS
Paky6EWhYu77U/sgSvPYjIes6TSaxy6foQi6/7W8oAu+bPZ02e5eoNv+GrUZepOKDeCpkwnjukyX
dDYmv0amiEe6YLWYnEOr+h0rQzJV0wMfLbXz8q/6RSoHO9Cu4Se6pAQkIg5IstOJDCCPKQI2Aflz
M7okeCe5E0FoDA/rfGjuzCuukxp2PrDewp5TbOj7fuLltxGDdEwtUgFlUELUQz78nyUDsNqzWp5C
AmscB4nUYosxQtEqEnmLFXjP++ac1AxY1nJg3moUsBFEz3c9olgWv95Hv8s0i0iKCM78nNm60G2R
fFB6umACFz4zbrU6LupJYI5GBEeGPvEHNpr590zwLvyKvqUJJLWsRu8sz81ZUJb3T7iQ6HO9W1gK
g/py5mR9JUmV5zhTgfdBTji7WTzHW197LABGPbJsJsG2bvTxvhOkQlv0A+yZxgOni3Si8XkuLar6
4YBpDkEjShfLUfINzYpLjnj2BGBwakMcaflqn9IxqgXqgMs06mBW56tVctOWbjxwgTFUcKRF7qZ2
ew1Dd6hKJFAaCs8j/opFemXLOQHOBOe5jpOTiYiBDQU1+iwAjfHcTz3I7Av+g5h0SWBVH+c4ad3B
oIHWQzmiIVWQUfy42/fgBKQkbNbejuX/ic3PTw/Nux3I2kjPZ49tKdoBSjesrdrmr/WUlZo4wwVS
ooeCsOn7/joSjN6Yae2SCGk29TqjjpwUwMgS4oh7fD+skG3SFzikOMwSj2EqYagU6KNFKsIewHUn
1VWQ9MLcsJtFCJe7dPbV3yz0+600OrzQtmDQlHq25IEFjG5BfoV6Fq8/WcgucfSf3fzZvkNEOlw9
/9/Oyhd0v1pbMwN6aqAmIOAdR8GSW/b3T4y9v4GDTL5Fs4UlfD/QqLkHVs0Jkw38HMkvwkg2WLci
2KddyjxozJ/DJqay1he2hxkSCDDaxgSGFTRjL0MkCl34e/3PiOvrW63vYspXrRdEFlmhyF4BTI+s
SaE8OriWhJDoF+F5+5StPtuP0I6XfxuDPfaU7DyWo610fF6WkHivQQN0muQGTLqrXz2s03e3M3kI
OF77IfBT5jzZzUmB0X456TVEQ++RQ4OM9390yPUkWFsH6+4f72Tbn7RPeB2wWlS/9vAOH5NRIV9I
ej1bi4QWvNdZHYcdh4APbfgkDdTdsGsJV4k60Omm3vfhBYhOzbPM0/DejdAgQkL5S2C+fvwJ7iIm
1bmiC1PNHPQu+eIYXLQQdXF18eZIfE5ZM5DQognA7QA/ughso+y8bOy9iODPx1t2oofwxv+U/ciZ
iy5BAiTDkUqoeL0Kyc28jcchiiDV9GMoYo+nqtkbgsIBdGSnxL/3as3S6SpcsMi+8qKKBMhm/KPY
2OAR4R1Vi/Q4n1KzSAQgnEXAsQ5dr/QIstRSq4WFA0TKnLUwHnlxuXHQvvXk0zwNFt6xmQEja2Pb
SVVyNNqLPmtOOGkCcwExh2TGNia5aYFlN5UB/Al6tRwQLEMy2hiMIpgXCQDWjoV/cFMTDL4x595a
hVCm2wGyQJHpQ63Y83febTDu146qqkbSAS5GKTt8ngtPc9N5P2YVLSVw3I/Ugod/ZwYpHIEGrJPH
DGCCiIxq0RFPnxRxywgvMCPwHFR0RPECMIWTJ5WpUQGzLkdWV9d0c/cmln+3oAMktrCAVg1btdzs
H/2MDyAFazYLQ9a91R9qBVQnfStBUSmrqM/vcl7QkoZyupfoO/jmL0r/dNKjgaUeEDgHHxPx98sr
nE4wVg5Hf0dV83kNdh/JwgR9AOzN/FbHizZoRjMyOCMjPcJw0vBUDXxoEQZTCp4e2YBAxe/jCakD
NOf+3ozQ2czYZBBpVJK31HP5FjXxxMi2gU125KU+I6cLJ8TrE9k2czmrvQLyqxblakFgvrg4A9K4
9tgpnww2JgvavNnn5U274DDW9aQmBlQqMblgeaOxSuY37JCjvWPRwmdqoPf5zZDcpVNoCh4dazYU
YzZmdv30MrBEOOtegLvxInkREGgbuPAAsnJ6o5QCyTRpndYHLLTo4SC/eFHK4pDlbFVFMj5Nz/i6
7gZdb2s62fPjd2XLhAmINhwarstAWTfDdwfMjQNHiOpJHW7k8e1riuwoE4zUi1zvHno6y6lAfp42
CoUtnUmFU/A4BFxAMeP4ne6FybG3ahYl4Wj7G5xfF0i+YAqJX5uQL/GRKknXIsPactwrFRqr9azI
jZXsuasTLOgen99iDnSUZYLqSMJboy2zpJaKwJjrlXlrNJxFk7MTZM4afVNJWyiEKzSq4oxsTxaQ
K/KNXqM3koMdRkujYqxKdr4OD7IrGkRjtMf0thwZBt2736suXN2IZfxjPBWOkm6I3zMvJCp9kSF0
tngSAuBgTYD2I4ddjWMF1x8VPVCVNK7NjFn81xIPq2UCL3Oavs9urFvu34wjPKag2/WXdxIlssTv
qeH4V7+wGDmEWZLPjtPhxepTiJ0XQNu1Te4VwQSkKV+99P3MDpan48dAKsCCF3ZexQSH6suepDUS
pniVfMXxrqQ3vrmVSHLHW/ae+yAGw2qJjucBs7cbEV9tWSTxS6xigS+6+9BJEacN3Ww1JAqJ7bPB
kmxsbkNGTdXGAMKLUxx5lCKgM0pXYaI/PxozNYhjU2zaLuilRjHOT69tGnkELrrJKUizN2dHN3sB
QgWscXIukOAwiKBFUk3P1wTm96S1NadMNgk0a/6EjCLWDG8Q5TPW1N/u9q2S5emdyyP0DdXO8EBy
iNYlkgc07/V+Svs7K2Zyl8Bk/rsoHsD52VX9eCRuy5nX7ArQn91FbqunZgofIrtkCTgfaxSbtuOE
Td3Mgslt62FHgpuTJK0Mt4ZRMz0MN/QRqeYDMzGBhvO18ZROzK6ibeGN/oKdXn50MCy+jQPP0bwY
9pRDAxBn7eJJZhN6onnzaj/TDCiETKnsEJBHIp2vnN4jk6415i2kxufFSL7r3rsn4lwWXzGPeHdF
lEb73hzSxb+slQAGAypw438V/cyaG0PUGSccmCri7Z8KDxtVACPckfGQfzBv0IjyocH8eT/JGFLD
YbbelWVjth8OxAVfB0yYHFJ72JWTy+7laIQeT0QQn5K9M3ZtYzioUbxxt/g05o6GKS+V0dET3lbK
3pQCd46B5bCRr6ACbY+zy9e0wxFybFWZF9zFl5uvnZ+m+PkgahvUODzqQQHuIkmQP3SvKygRw4xQ
uhnriNguM2Rr7DMm1xlXqlS+zFCCSccUBqQ38GqR6IJJYGR8A6qMEiw+IMV3dgfjawkOwESMFtqp
krTJXXN0beIYi7MjAobaD13vHL3nDjDNK74m0vnG2HkgZBjKteS+r1frJGDNtk3xlGnr8w2be2Rr
qIc4hb6zZWOuqu784urMsWfTpH+/OXvN87K9RfIADsh9/rfI2qineYiCRdLQbARc7lenC6wdgPuW
PEv9UD/IKlzjpJ5UbBkTucPLQOvKlBWW9CvNmVv6cWs+xw1qctkrx0DhNlZu1qUl3tQqMDHIOL8e
s7Z+D0eH4oXUMw9wiJ9nCf5kwaMUeoLkDUDHCYu3NoVxjl/AvGoHELwWsD95yl3Ma7TsrrLAzerp
9atKvZyJTrapGYRf6tPRlKMGSfKm4b9tZ/0+EyuDQkf/6mTJCY2xOLRfb/6tR5u7TfJLjsTpluNV
4ye8Jpr8GnTfIo3rr9B/2Buh5c9x6xRanDBAKebDRpPhf0dYa2C2AfwPJdYYi7OoyBN9bCHlZb+3
G0PPFg0+Xbg7hOuiaADTfvbBUeJUQJSgVJC/riTeIZ+pT+K8oeLtbM1a5GMtDejFQo9rt/2dK6XE
1bes1/X2bVg9IlRwrHDYlt6eY/MPtsDIg5gMDL0moHkq+58rbsSDsRj7w4+HUiKi0XEWx5D/yzIB
3W+sgOyDUAnxUSpcdMlbdfyG15QZS/qd66jKEhTHnDKKYIN4xqhhW0HuNqCGJswj3YveoTZ/Xi61
bfTEhK5jWJvzXzyjk3gPH/3TimkYmy7J1O8AwSzFzE/i7YDeN9YVKD6mR5tCO5WzOdHILc/IjV8m
obL3sa+FoBMfz6q38EiBJspxd1jKu1tvYPKteLEBSkcXU9NdT0JBePZ213ytdka0H5N41hD9Lz5K
UlmaHdP2sbg46d7LVlyJnnip1qRsXCJwXPrazXz5oNyycMzysE7oXrv6z8CAALULGYcr7zxUXsAq
OYOzcCl2Q+RhJPWeFjMcA+ikOHomLcKjYWt4oJyGe8NgVIQwdvI93uc7rgSook4JioHnvXfauPWT
8zhcaeUHuj7RW40S7T4fmBLhweeUMEj5NvwuMiWrdMQXNmYXwNwWeISp9QFh/FgG3PlMhE2yMlnl
PkgFC206931o/WfWAc8riiIxu/6KSo0VE0Z4VjQwwRIrIsiTHNT3Rr671I1nqXNpj+gCNOvKGZDk
iu84kjE9PPZyMUpx7Vgt/buU/wP+g4+FksEPiNrDDvmVPhrZw1XVaCcdiB3xKlVV9ZiessIcxsWZ
1yGs5ZyTOwkLwIxVNTjehmsHYjXnULczI9MVvknPvVa9mKBe60efjLOHa/mTc5xKDzkuRI0P/l9i
n6lrm+5AsOoo78bSzJX2qjArbzgIWdIaq7zjIyegH/eSw1/wj5PHeug/ueVqYctUHAL1HoGwmyFZ
2YlvK66lKLepy8aW620lrq29M8u6FFfU6tfVkaz68e334zoTsSigHCzZjAV4/zM1ZajWE4KKh/sU
Y+Pid5OaIYna1e/4GxJHfrOHxIUYWhrz08Pa4McehJWJb7625iwZO7JixiT7wAXZgUHLj595DXJr
PLT+eqH8sCxjp6i5qhTiwRjJqvjOZMxwXzWsEz33FH8oyNDzIiXfxzRb7mtwZVHBP55YQMJFtHZW
92e8hCyvjktbbXsY76fcA1J7beBzJ87w7uBt2dmbXnIpu3WzrZGXDDmZBg3E15at4aR5s5lA/exc
2AzIm5mSnz/gornVFDIHYvdEuYPfOD/VjrlMEfLEv/Sl5IwjUX2uhpjcyvaPPTbD+6DSXLPceEEb
MHY0dlsyIFUaSTDn4hLjFiFZPNQJJWCXmClOpuHJhMoHtrC9ttQ1p8uYDmzNwcep2vXkRtTglrtS
65zQBa/eqyPVtGUlPxTrSXDPu5G9jTYLIg2C83fz6/iNJMQzQ5QHF75Rt/Vb59tIFQaEMh+sgkTx
UhR6EG3EJzH5WA06K/z2uUCX2q57ERxmjdBKS++z1xIVfuCSjuyXO5PeUIF1wtc7lkYNIZfsnjsL
jy9nlpfNUycgTC1l+Z+alOY4UfyNFcmjdc8SIaHYzA9veAmBuZSeEkNLuqwMvPnH/Nj0pRKk5u/d
TDgneibXEiitdayqUFjbHMSRDMD/DL9N8iGlnv0M09fzORmlE+r0SR58sQMdlO6un/yRMYtOLx7H
ZRMnZoj/jMgzHuhHAUFTctlROJDe15NpE5UjTYjxcGSSaNf/0868aX/UJnvdawKP2iCl7TI70Kxw
NNXichBw7Y4k1LlFZOhffLH6HKkW7CmBGucpK7g7+QQ8GFRmApwPamcGscfltoQehuNfl4IE2WiM
yEKgX7Rfw4PIxGecR4SQH7Wgd+sE3BPy6HIsb0P9EVLZ4oLuVX4fapFCOvwzS7zKvdVX8CtMCFHi
gSoWWQE8kZ+GxY62axwKIGt0jmI9ReMVX1T7ygMJmpNG8iP1FRMBzq8BEA8gLANlrPw9y8WIYi99
frEdk/rtMHAW64KDVr6izuBB3me9ZeampztuVnQKZOAOxyWqu5s32FzjxFlCzfYj5KxJ3JD3bWkn
6AzhvuuIpgSgqkz9Xpf2wAOQl1eLIyJa9uhFpojaDlBuflLIWgSmHEv28eMrXoKfIiiAyuK3yUyd
11aKNBlghihSHvHpbKeVOGpJIe2navtqWABa/Du8B/4lcIxgVlmbdFZlo0NtuTFBn7VenFC7YR6P
dFjMpXPSx7lTAp6YF7jWPePWMY4wC+ixdln0rxzKeRSJ4CVTkFsMZKN8RzDY7W76NVpqqPsaY8MF
YQccygz9tAMN3yrr3wcP1CGA+ljtArtqsM1iJmkHuZP3obKr6NDTTB4v1DC8Qdfp2yNjYrfxr0d1
jmFYzR1eLweDygH/Dh8/eIsbDsY8AhA4+DzSTEKSypTQMzfc/a2v6efINCDDU2aVCPqDpyBVWXwX
iNiWbnMy9uo5oy8x1bZfqhHZXMUShTgQx5fB30S5Qb884967SwR8WUeAdO+3I0o9ylHuxIu5b+bp
FEx4QAqPQg3X6pGWv8hePKzFl0C6BRFBZsb7ordMRfJeKp4NzRoe82I6ISTexQJmp+3V8/RUTC2p
qec3gOuxhQe1KC198Tbczq4RZto2tm9KDEswdRmXHpDl2op4VBoQt7Uu7kIBfi3JPjZF7Lo1Rsul
Yc1HI3SLFzE+JaB0GXntsUCO8KQ4qfDakJJPZy311X0E4gyoZKpO2YMFNWgsxqj28rRJgKlI3JwW
SNf4jkcr77x7sSln2ZMG6av+jfrnr4Bc/JPNFFUgIJFX/sZv5IcUez2T//NDSssykmLyeBT1/VcB
Ks8hcd8kppB0J5rotn6O+ZLjRA4Y6mXUwiEgBkIuWiwAOSqH1/AvFuWCgnofPX6cGiEZKg7+5VWK
Zxk+0r5fORUJiWjxucwgwM9tXZlqQeGKXhG4LWLqwyntSoemVc77j3fNjwdGYzKh5pOwvERicxMx
1rKOPW5XJAHbI4CAJJaDU5FR7tmd0zEFd9hUjVduA9C3QW2cXRIZ1G6xKNqW7TMXTzgoEE8PYUJl
oP8zJHmEYqIn2URMmdOOBgq6qovwAvbvLtkBCNbDxblImy4Tn0PSsOXC9LV29kd7KRNqkGnXK4jU
6xlJRJ5EpqNQbMxKd5AOGzAELeOyu+xUndmu2sBMxawWyMkHkwtYniZghAXmrXsya4pQ+Ne3BiT1
jxlW+t0Loiqp4uYSscJ5bCtvOe8xcrlb21GJitfYvhfG/16CUE0ANGRImwOrwkSsrob0k1hFwkz4
iEhTtaLjcDj0ByuXk1rqZkxQk6+tD299ungNQT/dZZSo1pk9AQONPlaUw5/e81vUJOjoMUBOdv2d
P4CogjlkzpEv6OFMONGMH7Itu4/k1CuvsRQ4SUrFWq0ID5oEkhDqNqeX/H8FEABmKyiKxUR5pcQf
ARBCxSPPezblV9/vZaklJBtitoIc8KessZ1GPYxDptSbCVFw3kbfAl0/qj4sLAWUMbifWuCWBPtS
gZODqsadMYSRDKCKMJgCjS0LdI7nRYiK5A2URcQ/o5f7qu+WLjr6miVx6FrIrKxJeVBH9chXDCTA
cXGviH8gu2V+5UNLnqnx4CFVAYaiNepRfLVRsWgsgWBgJvBCmWnOeeLlQJP43B/JZc8xcUArE1XV
ks525ued9P3icgC3JoJ4qGKaUMYfVRBOof31ySm/grGQzNMlO1XYolUkZk8OIMZBh5HMbgeqdULE
vyLnDXOq9c0kJf0VBsjzKo6IoH2KWFRx5NkKtvHMrl7RAPcUsxOSKUoqdKgwbWuOe9bzYNP6hiVD
DIT8V8RNX+lNzNjOunaxGh+h8x2j33v07mj4Iyt8X4kXb1JnBU6tE+xoMiY8AsgAYbW8vKCKGxr1
JP3wsjcYTude0UwozQpIWfetqKJzYM3tZhZQJsS1NTK6TQsnfuTfvmbhuyCPTP3IyulKHFAZbjcS
IkFwD9KYkXRkKtmTkTxXm0IPhoh5/7xZ6Zla4l+jmTKX1vpPAPjTMRggwFxJad/Pe5dQ80Lre1ju
Ndc4Z17eAmx1GsAiHVtYNfrh0CULI0WX1okawfWvqstPVPkWEcQdWv43YwfGevcrNn1d8CexQVhk
Wv9DEb+4ToXYW2iYh96CCcokXKhCJ5UYEZ3kvDj35zz1UEiQ2BpX0/mpt8xoPctE1TxkrOzAXffV
NvMCuw1zBIA772y0eMUlP9pLlWyyQA5JFQg05GO1cF77tPBYh96NUKA/jQqyKB/eIbZ8vsQNf+sj
c96fnVCaPZXpc9mHVzD1sjxzdx4CgY4i4v2hjv/GPHI69vLWaUA7C8G5K5ht1jzkzksqE2I0FAMv
OlzyGAPk2Ba7wmcHaImLCzU3yQGImL9aVVAhHs+VNU6UfvcmcuI26BCJ34T/Q7U6/63BUjxfNHuS
NrgOY3uuMC/I67DeT61nEB7hm7Z8nVoIP/FYlqZsZHuHSpLy2PS/fdGuPEoOlS6EEdMCSFgYPQio
DOuhtUlg48+r5msGVQgSX6xPcPUQ+kZRh2s5WGIfuTFGQRUbQ2WnzlV+Rz6+QHCDCnHMmiwndUmP
xG22ECEJYC2tP9V/owFplqnJx8Ga2Kg7H+doniIwcFsLJVyhqp9Mjt70Stz+ImT3WHLusU4BaAJx
rfLCGzult+peEQ89B4iQxvqebSMny+NcvhnU4BZJnb3Qf42nmOw4kNvYEFeoASpAGzpi5cFf5mVO
MNXfCfsuwZDge5bPpNZ0x0ph4fDUdbwlGsThqqaTizTPEpVgRnEipw5BImNv9iLQ1i9Ea2gVpMv/
flteBvVFmPX/jBstc3CZWYw6FleiOw+gZ6/UARQlO6sgBfTvd0yazIahM100reidfOXk8mF9yt0R
qDevJY0dvAn+tsoslWFY1x8/dGxc/ty+Q+o1cCsclBX32uIL+kl0UBTWCUgcBqh9ObwvDyGJWja7
Pe0cJVbaGz0rLPeQqcAaQELtKCzCTfsI8sFSm51UiwXiRZKW2Xq1B5Wjof/aF2qAgOqa0IsT4xBJ
G96JnDhB1nmM/Z8QRstUD4WBIUwwmmDTR+nRzlzbcUHgXqum3k4wWXrRKj0lofL8970oFnQXlisp
Sf3vDqrMFQNYHw6++ulHiBspih05pdRaI8EVJZU8ZXtNsI1w11NIG8uFg4iruzsUWMOLqZvb7XD3
D8t3xH21IFlmnR1esUdwjPCpIfga+IpArc5n1PVlqedYeg9tix+G4C6++uISKlnkMFtzPZfMbdyG
ghZsNWm0QhjsfXDt9bNJVuz1h9KUVoj8/XP3lkiceIorLc9OM6uRX+TeXu1QabSzeW7RAmfFJiJt
Zpdo94D483GeIluu6WWtohHb6Pifz5QluahvGhjTkIMgu9c415Amfv6fgpny4lL7wb4dDJT1s1qU
wX+1ZovAP/VXnkWGW5I4ZI0ftQSOqu/JwJ4gmYbiDb9lSf2uKlNtwTVbXzi6S7iQlq9OpNNQLa5i
d7cHQ+fnXWY3lkIgAtB3i2ytXgIQGGLbRKZBd5cYzwDHEoxnMZrk6VNUGGUOmWlBmvYdHLSZ68aB
3E/Ny23iUBR8DjjZpiVaBU94EJJWpLJaLHfiFrEIkmlsJfNqso0weAgV+1da1vG7CAGAkhfgOPnv
kztr9S2SggZ5IyGlzkgrba+2CiES3NIk9Q+j9oio5QMOuinZIxQ5G0Z5zom2AbbCzm1HKSALStXL
3S5Xbf/lnvbsQ3zmgHYCiXjw/D7RPekgCPhM/SjMFcwUB2mzGK7e23TJTr7eQNxBVvMM0aF8QUP7
mUtdlATHrp08y3cFoFZ1QT96C/zMhNE9WTX5uIA9hYqy4ZdjIjpnbWVLQ5dIrl6+rnDLWgZrKlNX
/QpHo282MU3B5q3+NoGLmjyRv1SnvIcTGnBQZ3OAXVPLSaIwZgUCQJeCvQBiRExHw5HAsLwXRP9e
Jug/v2dIyXjG7z7r1mWfRNPtyCNxGXZpfazur6pwfdfRvsYni7Q07N3PQuRFo7A4dC29S0KCrOta
HyLF9UZMbS4RQUGEFHymw3L+TO7DmWYxe7QsbewgjgV5KHnaxdXkYFw761IAkCHURiuOnQduxXrf
JYu5ooCKbE7B3RZ0CU09Gj+jlfnZvIEZlC9O+5SBUCQ8wYSMQz9ev9WY7Y2jaz7pl3AnHUfnKGU1
pWvq786itvJob3xP/WdHLgBfPyYvm4W8M9lu97O6woifa8TChHx/RfHd3Vac/mAlY07A7CfZlQBV
PnppoDmonVwnQu5m/qyT/XjLRH7q0+95N9Fdq+QZQOqziFlO3wsBw5gTbWq/hPOeLzb6tMYiTNG6
pCi/+ei+3iHr865BI8J/PlfUUAD3mQhd4rvgtLFkBphBHoF4oHN7JRfXmLhHiFdu0gs46E87Ax/9
nSq8eeMnrnLR+leKJMAZh8s/e9VlMbWBdbU6ss5Goy0a+crlDlsF0tunJbPdsqSQ3/+m9qiEfkQ8
+Zln/HeZaxucXoH6A4TBurQGRqtzonIMF0Y1PRyu/GDVKIcg+falsSj5uHU1SxwHBsBGUtZiN3bs
Q/YRlZiopbbflWoHyNegdFGbP5Q4rELvER0jgK6V1WIud/P+O3v794aSudyHg8FtRne/Bw3JHisB
Ra8ugmXwruE7v0z3pg0JtCkZj7DR9MlHq6rx6OCp9aWKd9A39KePe2q6sTIbwQShnwhbrs6IXHBn
hP5K2DFXqfBi+mwbPSmNsCZmyi/b/u+KrcUK9j0fua97VYZGWQ5tXy1QkZWI6iGmGdDUdDor5mph
5U88LjOHCPSjxIZLbDXUK8vBXzK3jWds2fscvnPdedpzbxwbB5eELxUcWURcXssJmm9mO8H4t1us
jtkRKPkIdz6BKJGKGVGQWRLz3L6DzqGoo5eKrQq4IPcB1vJf7wGvaZneUaDA7nCvt4KUDVXmdgF9
+mljvNJ63u1sG4WAfdxwINGsNDVRo2lGa3VB01a/xA1JqB5v/Rvb3J3SarYNWdSUttsJm05UXgrc
LMLqC39RuE30UI0UDARqgx2q1calv2o5NIbA7eiYwRl1L1RvY91OONaqfAidZRL3Rck5+n8ChL5X
q2zAl1nnbZAyYoNoNWc9TycYYNfPKOyQjobdt9JGWdg+aitiGWAYk5sDmJ7a/fqNIx0p8hAaSZTC
5Iehx8eC+3cohwb/ibmgsJkpNAiqW6b+e8Nmydu4aWEE3SbD7TF+o2kAuWwsNUuRzg72EU3NY6hw
CV8M3Ytwd1TscqVpJNV82liDirATeGWg23dYfkZ9f6odp87+5wErD9ODy8enZ25198Y6WINSW3Pa
TCR1Ggn9OueodOcy5h8vOlspggFFQAqRTjHhU06jYTdE3alLaUJoBJzcHCcd5n7sK6WZnozr1RWx
0WCnbqQHU7KN3eH6oBTL0abTpyYb6Xw9w+XUbsMQXcgxJiuLWw7pk3HzugUIhc58AZV6T1DbQZZ7
Nh1Yu2DyyumcIEM0a1XHOvd1+qTy8trn8KOh53SaUcW+MGQ7/ah5GpA/huE5Y5YXkhYuMw+72e1b
IVl/MNdlD9J2+XVwq3vvF1Z9Oc7iPFmzYp0vZ5H+ijXlou2cgtE1KJ77wV5pF/27y9El/9alPPZE
/UbdPF+NCoIzzPOr42hJy5cDjxrE6ySiQLnPUGwpFlBy30J7QVlcgMYC1Li/ACHBc71omfIeySoF
4PGJtCtw7uyWaJLd/Aa/SPXo9iTDQUbVTmS4ipF+7EYuuNozLZBEsP3wSpqVhcWzO0g9y6Q06QHq
TPwj0tHmEVu9T0GpDGTChUe6JokI48TnaSaif4xzv0sb3O3noRD4sabRO9KjocNxCGFDYpS7aC7u
DFzuz6/Kwf1ad1qQpGrWXVfbUZW/8wdt+s4wohbV+3CBEA8LLrRTYFaMmxyNgsHy8VUn1x1wpC08
gKG9Zwdjq2NLh9Wuvu+AeEgIYTtF4X0dqdPFsvjtlNuwnQhrjb6oJ+bK9VXQyPkdp7Yrtwkk2aqb
GClJKulAUirOAD52vPVVoeSXxiK018WouM2MPRJJYgvGuq8jVT4sGO0Zelmg7M5S/o3kdCMNpkB8
SNAisH91XKiH/1zA3A7ay0fYKvNwPZr9pw2w9tEy9DOI2FdTy+t8/UJklWjqehU/YelIAoWLOjcm
lj65dldOQw3SZHBQIEc5JkNNFSb+4UJ3f0pMzAr2aN/PqSZ1qCFia2g20z0cAUS6snnI4/7Kk6wX
S8tqXhsXB351IDEMF27FhmgtTdn+utFEC1ZJ+Qf2g/JAf+0ZTz7bQAmnblsRi8LE3AEnUxuNiJW5
uHzIdtX87WSTQpsE/4D3TMkmdUY77+IcH4KXbFHVlwpGzw9pNeUaFkgrY3ULPSqTJNumYIFwEIKI
tDEMj5/SXnLaVJI1+WlzEQMV3YuMfpMC04m6/SK/NsoHA+hKZz0XPW5m49ikQVMCC6eZhgXrWprx
SCZe2VOKjvGcnNfYxmiuhlgrvOBJZMinai3DFkl/NKQgVoNJjP/cmq+Aji3qEzLTRnzxCBNx5s3F
hBtnwAdseZifglWuWj4RSAa1x+thq9HNCtSc4cJB8XL1x1FBTGuKPtMVmJc1xeWdlmMrOyF5uYEt
jAmxqy57u3H9Xv+ztH5WyhldY8ylc7mlJntaJt6LqLfO1KBYXVKYvBj45K8rrpBbozJwc+gfY/kV
R14k/6/FGO2PC6TxlMz7MIHFR+8N98Cc9995NH9u0DxNzy5GwZYYyZtryeLK447Y/OoTIz+okMV/
YQ+a1F0zLvzd/EWCQeszG5uCOHztVN05cs519dD5c2hPz7nQoxk6YL/XTlL6aCUM+hEDHbTLlB14
MlPOBM+KOuA55YYua1MddHdr6MO0DghlYnHSZOh9AeaRK0rYghgvUgcepZ6RTh1Zbn9FlhCgI8pD
3Gv2jMZSlj6O6ACUkG2MLRNuDuDiTQDrS/Xv/0qlFuwwdChYEmEIw9oECgylcKd/qqsaz3LnUs6Z
ocqHddPwpvb5pk6o3lJ6fjG0buHCvy/mjALqQJZei47f4OVPXs9KyrtAqKZ2MHNW8b+Eun6i321A
hWMX7FDHD2ufvwNHVxMjrOSRw+iUPs2otSKbeXUrvbIPq5JgmX2p/CvknordLmlO2bjCIdIblFyU
a2BEqTvvl7XF2gr6cswhLS8TnW4ezLPiLUHB1WyXYgFT3C8oISrINXfiQTbeicevPw68y8fRpgL1
6ONEbeWtt9J6qKVA+TPLYV0aU7CWVV/DUavmlPoBS2Nj+fSZxbHz91OJzDR26Qt/SS1ZytfEgEAD
BxFO9l2oi518/KOmSorgydq/tApnZyTiKgd0AjuRIQvCQAstpNH+FmSO7Wm6bomPlmhvS0+ezvlH
/4RQwFmeMObF71P0QdFa0Pl7nuFSveoXC2umDdlEvw5F1J8i0JYNRrApYYLwUB/Xbg0PR6S2Hu3/
gwleu81nviAKhUaOWb70lghdCY/EX/Ks+ZFhWkTVAHhGc1uJ8gYTtAoEXeHmBlu82YUO7xJMNGFR
28mTXl/WXKHdoBoWwKFxclLuL3G96sQ7uQaThb8loXwxa95lhcG7dVS6fe+1DdxnNm3tqjYd+rAG
cvOy6bVaF9y2KhCfvMf7pqN8j9AFBQw1rcM1k1czx7JYUXpyzKbnPx4nrNbPzlTHpmXwetvfHpO1
WPcNfW0veow24ho+VigAMydYiv8nTlnjdb1q+xJg55YLTc6n3D/FEG1Omb6kXi6DkImGCYqA+gfw
32zTetdQ4ClAZY2xVH9pxXfbZ0Md9fjoGkKeVHBFBxCsK3iZCJwtRtRo/6Te2GPepivkRC+N6fIk
wynCLicEkKBzvIgKcJzc+dYThnMc8YKLkcyyfq9p7TXOSY1vUMAyGDXtqzHry6zS/JyIaNFuvUus
WSqSefFG+QaioDjBbp1+gJfBX7zYSGA/RYdNnYnY0oWrLBynYBWeqjlIgfeQOGhvXxG2nj5j4MGC
Ls7849gvD1q6Z09/8/SjkwCzCEc1LnKrXvY2GbluaoLxoKXIt0ORrHm58CUwfknxuXYzctQkrbWt
b+g5ibM14Y7Qo7hGwQeV/FuuZjET4X51iWrexX9QhB0UHlwP4MlzAZS+cuggFIuls/wqOz7qrud7
hM/NZhas/FsgCgWZ2djyLiVkw0PX+EfGlrXeSPDgQW9GaoGR/E4I3Nxb39xIlUQP/nqEArOQ2SFP
YqOURlZyen3Ug2smdQHnzhVmSODk6G6k92c8krsZI86M4bnyYVksuKLRK03XJ7XbXE/eYl+ovXmz
IPDiEqnCC7lV0lmC3DaUJK1Ms3ZwXNLpzXWtZxyO3OjGW0/QiNM7q4Wi0ucL49RvRFeNspb6Jg4M
L9ZfHgT1TOgp6QyGXQN+lQDUyzkavU5eVsybqCgB2xnODLjMU4WMmCBXmvDpozycffXKf7I5WaZh
VYKTTpTqXgd6cUAOi8tD/vKCK73yOyavk76Es1hAe0j0CC60J2OmAk8xoRn2xO4xiuBWkrS6lND2
2Dko6e73cBBqdRQ/svIc4y6NyIP6kfE+kI0+1Tp5pkdDj6nsyA+Y/uPxB7wihWhHWwI4wiHiOWS7
JcQztTS1K+ulQ7d4grvVJ3IPxr+y3mEd6paLjD3VRcEf6+sCkGt/3tGkLwL5q7YQUS6Dc/joi31v
e2MuzIGkgTd+7DuLJ3WIvudimMMzLKRcQ4u7aeZPMZdBtBaBn4gTt4MOujZJMvt60Qp3q0qBAWFW
epsg/njniZ4aWl+veZevMa6HT4cG+cG6g2dGl/YzKRf0B4DmNmnnfBBVyWykq9qM9oUW/0iq8ddW
Cy2PjVpD7L2b1oooC+jgcsk02kUN7UuyQ/n1I9NWL3jqfYp/5eJKJx4LAHJAmQ8PNIULc74xGOYq
IsSYFErXcsxPey69sgWB+qptEbF/6r7ZE/d7fCQXkNDvo8KbvD2+dVuUz/rCzoQNgE9D0gfcvoD0
C8b+8H0qB7WNDRreU/g5NtzgYjr20i64f4Q7FJUgMg/Q32j2YzKhg8eD0lzfexJ1T7McGpYWnt7+
j/hTRjlBgGrYvHEsWyA85/9/STWCz/T5utni8wucizRImOyKcmawVMFV+R0P5MOlgS11hIjkdAMP
zvl7IPjsAnBhSAnMyreJzcvB9lIzevGG10Lad4C8WEEoZFw8FlB7EyK5H4IGplNmwnbsjjZkPehH
4zgMEHS1C/eU17bLNcTsDlLZC16IjJTWe9ZbUo/7xUuqBQQ9NW1q15EVf5SOt6BtOuOD0u2rtA9P
bOhdxdqjwAUFxbuUvz3FiabSYLAlzSpZZ2eloVky13XytCNG5d5R8IQVlXLgSZ2W+GDS4Xh363TQ
Uh+NR+Sn/a0yvCC/TzmdmZimJVcFtg1AdNulKFNG4/bbNrCSbWWqGhI6JZYaAvhVfsteNdM4ZZgZ
b89yHKhC0LcmNpq53TAIjJYD+MMJ/MYEad1VmEq83JhxzqzO8Bg28U8fCmatoQJrUDFxlMsa+Ev2
eqiyvvJR1lyKSAuX7iWgdnHSj9bUxziGoqqFsoiepVynTr+6cBWrM6+MNbsNRW1SQfer2tvOwW26
aowze5yRsfwnOZmTI7zzswa/C2ndqCdQECAhmFpXn11DoK/xjF6+UyYuMbTK926Rxra9INN9bFR5
fT0k/PQV9C9CyfhF/HBS6IH3qpNhW2WFIBNwGOZ2DUpa6OEf1vPziRkZU39++XHvdnGiu9ySqqSD
/a5MOzXGUYwKPmprGgHuRTLZ3giKNgAaFzwIlpYtspEXszd43cySkQFH92cHdAdtbkyzbyc4Qm57
RXof2gvWw+gP+WQIwiwODNIOkX0AcMXF9UjgGJLOrAwi1HJyn9q28dyrjU4ugpMLK95jNve4zsIv
TB50d/QtPh16BXjupVh/bGmmva8Yi3I2RAa8kWyg4UQAWeAQ+a3Oe9lSdq3l3MC+ltSUoUhc5MLV
0uf7KsS53IUI3pceWE9KVTA1rUVg8nAOb5UwSmDBfXBaYm0Pg/v532hVvcZJKtt9WF7nxLVU98hS
q0FJrXrdEffw57ejcvI9SmIJBE39BUG7UHJGchnoBDByQoNh6pVGxa9+1s3v4H4o551hmj+0Po5u
TmwvUJuOUoIbazJ8keuuvq17cMQsIX5CbV+ARBmvhAOgQbSOkidNNq9TuyOoLgC5NmtzU8w4YbcG
KYjNhzU2JqHbK7pMrkVHeajmZXmQ49mTd2PaGNijqvske+jjHMCjW9oL8v3Snett+ccHk8kDzWud
Cwwn+JWB/AraTYDGxjaH55A4e9t0neiUQGwaNv/oXFA6DrsyUudgAJZpxtrImUKA1k0r8rajBMkQ
d24ljZbxXGLCz1wjVJ1/e4jctwoiX/AVrvbbkphjwVeoPjp00eYszKebu6RDjDhStRqtuk8LkbYV
ex5HfNi+HD2SJexaJuaztaryGwikzeFKqn2LjgQPz5pXcBBnB0Qg2lnRGhiqeDff6D0UdUPI6X7D
QDOSRNQyg0NrZEezfhKGActzY/0YVHm1B7eriIyocJgVHHPWGl+8i7ylsJ0EnWxVuv7AE2RAfoc3
wJIV47KvB5wL3MqFi7+0lMu6ZIg5AfO18ku4yePJ9KchCs5TNh32d91BxTzjxEWdFZSza3IjN1se
1yu9uMO/Fq+XCHjX+zOaXlzg2/ixyQvaUf5jUYLfk+zXIv9mE0desGOT7OTpsxSQGVQfSPBOkoT4
1k5pdnTNrsqe2yFjzJ75mnO4pHOpsvb4S7ehxGa/nYrKagvi9tFhT7RGTQZ/hGrL6E7bw/GrlIUG
L1ykca1lvm/jwtygtc/kQ1RcgcNLlrd8okv4+gT3GO6JJtAOenizX/DQHgOd8W/EDQ60jAWHzpnl
z5yPkXU3ZsQotVpnjDE+68BqWPypbTyqcprw3b7hdfiNF1Fl5o1oxkmXAHxKwFblj32rASpEJ23N
nGs8C9fL6Pa00GqwP1p0sygRzBKjBVEDxbuLyTWxUh/VL4iWetEMkGm0FhlgsIvvbg89xFJE53Fh
oeW9Tk0VrEtSqaO5G8Qi0X8A9u+GIx5aV6MBxhRjphj8Z1YOkQIpgdkinMvDf51siZtuEaLNDaa8
t70SrhYF7VaMVg8g7tZuKvzKHSsEMSqStiJh4XHOEe2zlsnQLfiTGQcNO28RurpqKcUduYDQWYGz
iP4PWn0RXyQfl2oo3A+56v+apDYqEuepw3R8PHnOvxHKK2ko9KHYorCocf+DllM8EjLyGm28V9Mk
S9tnEva6IHiMufTQccTnSg/1nUnujJ6oLE0dnK3PNVy2WrF73abQzS9hVQhH6Wn0vJQj6PHnFL0v
IoOzNa1sO/VmX3LxNGS17i1A5xg6CXj8Bggh+oWx89FiwtbLxxzWWTcZbUKgqWtkKl3BOOtT7aKY
9SrHJYWNUxLqDmQmXiCDa34lWZj60TKA5HduugN3ET6+hWFMefm4OjZzLSWZMZWFXJWbdJPG3tk1
xw3fQnBbHAbyl8OowkrRvyUXmB5vH6W1gQORa2uM8JkW92SQkoGAxZrubweY+SyWxJH4wfMiRhhH
ZjQzZLNqMytNk2n5OF1OMhSkUyKFQee12FIh4y9uyxS5XfvV/OX0IKPSOzyFKBBFVaZjYG0xAeN3
Az5tVQccZQRAMscf91YNuVSzbxsd6e8wMupSTJobjueeiamZHgf7JFAwbiGmLYhfgcaGSn/cOaJx
9Q4EErdMcxCgyw84iYW2ky5WDwFGwllZBSFMzsGtmnZNTidQL1SZOBpUgkUo5DpbKEYOEXvWivdp
7LMNdnekwl35jyOM2winDHtg8/h//yhelyFVM4DYjevBWfE3EChpYHjyn0GeynmUEcWMG6jY0ySu
2eogFyKiQ+lNS5o4HPOjTnDyzLjKqEFZEQWLkfSQLilf2YIkZt6jukMpJ0JAGuZUBzHWHhkhkdEY
5dhS1apbsKuDLTEv9Ej3mH9rhYf7YOkiIux/a8qafE/NMKUKum93Xd/qJzFB6VHqDe1bsctsj+kX
MwvTjq1KmgV3Ik74KxHtO9cCs0DxVRLgV1sAcsdquRdFUfUz5NdKQIOeWKb1mDDtW/nKZ5aBF16A
jc0g47Y8cDrKgDIKJpUFUd7G57nz/Re/yqSbKiROYM0fBbN54z7u2W1KEdoVoqru4u39rnSAz3Uq
lYqlqH7V7queuObRZhwwiA8DAOTAevvykw7h/p5PxGiJGFp0udWb3ZkZb12eS6sgF4QOn4OIouS3
rSQjpocZqSj/uswVV3b2tFiz+79DfE58mh/B2abSDWEEgmkxt3y2PSgiZ2zw8tt/hEAZF+RH0BSj
/M2wkJC7lLJgleNwqphxTVEbAoKPGxfXULOZ6BRECW0FKXjf8zsVZ4QvXo8YxB0F0VQdPNeXWqyq
0Vb665P2y+i46+dT7UHj2dT3+Oa/AgTckvTo03jUQAOK6dYRcE/3AruYJEW1HzW7DoFKz6/1YNCS
fw9X8+kG2hiagEhJXpG8i5GWFcgmJ1ml9TqauCaw0ZAQ1pY+thHPAcvUHlF0A3gDJQYeJwdJ1B6Z
OKobNNM2z7Uuft8VZajVBhOp/7NSuG91Qnhtsord53fWruNhIBiI+vknptYOynsOhn5XYkOfKvCO
aTa0JOfLVj9SkdFyI32kcvExZ1mqWkEgj3ApTERofL+eiGhGoOFyjvQ3zTHCeCdHaMTYWMGBgcvZ
VBMW+PFQSROw0Skhjls92vV3Dg1CK8IKOOHpPvA8sGM07f/g9/STXjhiE96Ns4VM9Gy3BvwB7tZf
xpWXQIgiSRxq6gXCEHT9po0f8QK6vUYVI7Mqy+5O5n4+QGJrZtLm4K/I7ZG+CMK0ztFrQVPvGmN+
M04ENJm9grigc7GCb43mNorvbmaHcX5AN+gFTsZobPBhlDQ1RrYij43uZ+HsmQAHUSWbdt+X7bU6
go6SHkFo5QRm8W27EQrE74ZBimkb8ZRVHHsstlUTmVR4Y5fakakEHMhO53QOz2PPSMdWv2lKYK+V
vSjoXTSwMNV0vZvJ3Mpi3qyBAgMgs+9OqL4VEM1q0UhCs+uLlrTZ82X9Mff1K9zMfxY1ZgieTCIP
WRGPCxop5y3qbELY7a4dfP7L6ngYwJFlckBcZqNaELaisN8uJo4i4XHzdA69oj+VIuZWMJ8Y2MgB
3vZB4EiYZl2jV31BBtpN4OjJLcKxZITXPAgx84X2iecJ2/ovAylJP/RbJr92zCgMzaSDPsiaagsX
B47nSYFHmhuRGkQ1xjzyictKGgiwIapxK1AU6tlas82pb0U1xH63rlkxVAivFV4NB7i4BWNnvMAM
wlQBr2Z0ka/xzkUogBNDGqcoack3+cx+Er34M/TdqeAdMSiF/d+DZF5ttWs1nhETaBeRfpRfzUUK
KTa2g/gmabSevy4AVQ32TWzhIYaHnJ3BV2OfsFBygO9niw/kgPtH/gqeqHCtgm/CG63aM2aABh40
+YTIW9yZoXwnLOWfglbwnfKeqZEEO5kvtpc0KlKbGjboWhW+BK47F8VovDmp4dCFnngEnhOYhMcG
eiaxeNRiVPN5M3GjNT907Rs7oLA/G/2BViqu6v3KgRndEFCs00/lKi3/m8L4jJHUlxjzlPQLDMFU
C+dCMSviqav2RXAPuxPiPMg8x8Tqk2RwtUbiAsd781lW13BLSgQnwAujgC732Ra0Dk+0gpZgJ8BH
C172pnxa3aSgwxrrSOeyenqbIXZssuVoWBpSo8vGINc3MdlCBaw4KnlE0ApY96QnClncg7x3qZA4
gkOUqRtZNGI2a/xCMqtpPPzvVLOLK2tOMGFyyaqPyy0IqiHNZ8PE2G3o72pbiH5d+if6qtUPACoW
++RMf19btg2YkSpq5YpsO5tK8Wa9m0yGAeinauRxI1DuvJJAUnZfXzKIz4nxDtSd6KnFJL6UdPBA
KFnZoHkpvoQ3lS0yLFz2MrFOJdsQNf0ZsnRWaw+/yCBkR8jyxld/WIiaTDv1SH1/I+hDQ2sJbEy6
f7iQAisUc/lVnFfZNxAewNzRBp2qz0B/qqETB2CvzVoTkG5VRGutgY+y6D0MYgjr0BrcIQoTXf5O
iS7rBf9XbVnM/+JIjypOp2GnUDdZeXLS1c1+koqOME/7bjhkfdg+twdqJeqGKYbDqq8LemOM131f
8d+CX203bmUHj1dvocz3ufLYnUYx4FDcPdRWfIHqB1qZUQSOwUQ2lIz35hTYs7m0c5WgpW4G+f0T
0rR9KkIp4YJduJmJ5VS2mIqAZbW8Xhm5DcQidFqrjiwJFM3msTP8XuPwaquZed9wXC0Vho2So4R1
sZECNStyl/dVBcqng7xfOmjFu98VRkxxPTAibVDmrDiweRWb/woPPMrQigHv25wxOPfuZx0PDNM4
m9/XCPNsk5ih61+EHOz2SGTkHSmAzBJCRRU2O9jSBOznrcSjrh1nOxOlMScmIsb0gY5cb2dBDjr2
yai73z9UEukbYDhyycDEiDHY+qm/EZtOPjh05/QHOiYsNM98nef4Xg5lwuQNerzdd4CHS6bhz1DK
ExZGdIfqKmk1I4/emUMEl4yIP+3o2qON+Ved6I6ZLZPm2noS/hXsopRYpwPVhuWfJ3AztweJD7Uq
3sywijOGFwNVzOxsT8KUleueWc62pha3z9F2DQVikc2hpw3qc04IeHcZY55RZJCBP7pbC01jFKC5
2hNzoas5t9bKJOieSu/coI8sBX2qBUN9U8FTZJVLIE4P1BunFkooNEtVz20nl5WmZfnFa7MYmIUx
F9hBJEF31Oayq0CNY4yufdS3HyxvWcewCSwyDH4jmXwtA/6+E/SzcQPmSe6xQHjUBkhPOc5CTReu
dL47EhfSEPjzpZKFdvuAGqm+XchTWEzUTRQgfxYN46I8s2mZic+MG//IsJXydm9CQH2GjdOjC3ag
Ol+FbpOmfj2sBwih1cEYD44gQLBItQBXPgfNBW9dmlb270gVq1De+KuB6VGOY25UL2Cda28KYXyM
16SH4P/viKwnyAdzByamAfQC12gN3etj0/tsavXhN0PR6ZxMuuaA/BUaMBjkcgp/2l75XoiXRFSL
oFUi9OHEMDDKKMRgEmxlD2pSy6Z/I7yJk/EaW9PKSo47U2mb7AhIAZV8CNI5+XdEjwYSVk/bpzwB
caD1b7LphWGpsF3dC7pOul3QEmnlK9ExmsoeYXWKTDnqAjOvBF0RKl7qzxCD5cmF6QRi235H6yrY
nAZFCABBQARqAcw8vCbtJPupkl4MPgzMoyEvgKCAxKORcNgM2w6NEcUase+6j7XkeyMNHtFRwh8d
dWTG3i4tw/w4C/RfDgIGAXN/rCCUZsgFxvvUcCYQ1P+6H2m+L5cVrW5SWns8GOC5ER6Fifh6I+JV
+51rPM7t5d5GWDF23IKMDYyMjQTLhIGDHlFhQM/OCdC86VEIFKMNpQtB/WrTn1dSJlGSSN7Qiz9u
ltY/Ern8UKcBYZFb/BQOVPsOvi4DzjKb6QMd+Vwh1CdID1yaTmMWmFE90DRAyYVzDWvo/tcqbE+z
lnkPUsQsasoBBAs7Mk9tYZd7qcI0DILGvd3UHvpxCJU1RxkN8aK0mZUg3BDR3YRWCABHPVppRusP
eR5ekUPtIygptSLpVw0xdLPvndJAHxc18hlipsHzOFpx0eu2RmXOlGIpasI12AlYtrPcphheBDHz
FbhsTyOK2gFu2daU4L2mKEWEHcOlJ72N/VaxnRl3jUWACd2KIp1a+wFBd7Mf8VFHUGt5dLMteLU2
eI6zk6S8X1vCS9PnCXwdgVzoRXR/xmnnvT6BxouricNCuT7wQI4xMR8r5qT07/pW1p9s0i8T/fTp
VzzH4zBU5meJFvz+ERaNDZzFshSvrjo+8PkSvGnHpZ5SfojKO+mXshb52pgxhuSZp0O/fq+rspMO
L+7APZMg7C9m28OgN+qDnINFGzDEGmmKcsbvbb7RAZxIh9k+W+W6WFqcyKBViMhUcsj3jb5cVJbv
WUzRytw9LGctwa3mu2f1HVtxjN0/kifLjtIasxnySMCNAfVfe7JqxdRbrKQ1fZuh+OcfmjwIiHgm
qTSxguN43E3Pj2gprSg4d7hNXJ4C5avIiopOs6QVbzOo6zTXpCa+fLyklLvHvlEEQyUdHg1f95He
wnQCX3ADd3mwe1/PUSgrDhCLtanoX/u6o55PSUpedGAVODaJB4i89k70M7rHPj3iqSJTb2pqkins
qtN4ujmhIlCT2zHl7tRuaDpjNGrfmj1+1LrI2G/zvjvLEMwq7jEEuNUmFGBErDOX6jLbspgz9pq/
tfK5egFddHmo0E6W4UK4CXXPPPll5Djs1joAoLwlI1h4rlD0oHc4zzgmwCKTMHgahhYj/FI7bU2L
BnpE7AjW+uybe2V9nXW0akx1YbPvKMbvdBPLvDYTb+9prjeCgIGaluzdPpBIxP+OjIxwRF5PAulR
1OdEmJhx3Q8vAb0dsiU/NaipIrCK1/pyISMLKzIRr3Q8RNS5+7yYax7xL0757aJnxaVmgbr/a0vA
3uCnde4ULBGVNXERcrDllqzYaLYSE9bjVxFTRgP2uzIuYTAgDI1LmXmyxyFMhtUx2OUFMmIYuru9
Whq/TL3o6h7i8sDajQGQRkZDOqsRJsuWbNqM3fWLnrmip2uymXbhgs0Wetiu7u3ldfZ7PvFnm3JZ
FqJAWGVQCml6u9VWgMHGXPdgnjeyXUiGptgQtDZaF8eD75zJTWRCiFgnNjGgC/T29hmOB3vJbvw4
q3b7tbD/pcLJw5sTWagcriFKAILKwfk6ugCX8P8mjjrshJ/1SWc23axnvCdAKw2A6+Pmu0cUDUft
rRNk8izFMSAvuRQAxX3n9TXqIx8gwDFV1HDLetNGj+bpVQqScb6LMwEUHwYSBGlUjohKM8AxdXil
kGN1T/JOuFqgLSuoB7wKA7gnlXQ6f8mQLfoGxgZJ7vsQy0MZI5gOJ/e/oC5TOkniZ5+Vm17Fe6XD
6Q6lVHY53Xz4wVfBV1n/vKJhGXEKg1jTz14S7ls61T1pzmHEenQoFbtK7l7FEWAQSCRAi1pLjKlj
iNaSgzz/TKl+/55XFUHuh6UKHs12QuNpIhlgw7mFaUOe9i/PSVfueX80H9617su3J5xfKlbh2NFb
jZevy/zOWquB7ijOyTOD/MYqPAAmdsUv33UZCdBDDkP1unjnigG+kgYDXFjWgYqWgkf8jRv1nb+8
l7MMMdgBVonarB3VdxKt+fr9odRw1qag2gMmeTJQ2mJM20V4xZkyyj6U26i+FEbi/S03yE8GE2oL
7D30rbfFcyiHNrZdAyTUuxJ+6TvL5/xcvBImtiSZ8fhLwCXPf3hBnO3MzuMoVynkT+X0tuT69KXg
BYtNXG6pXmX/M+AM0AB6EhqvizTY/L9ZB8F8UXMfsTh/9sbFzHFrWvyt5ViuIWTMCVNitlliqFQD
sYtotuFK/Y43t8QC0rEKphh2qbIeSaOnn++Eh8oN9Rrl3Q4bBVTAJpunWNYrQj8s3RJbrK4JqmDx
56G8x0SfaA+SnJRDkNL+dLSWR5bjp8NIw7JcDTHzUQSYK2NNOvOV3GWRVziq4URqne7BXVzbl/fE
hpNDLGQUffgSWRfhlLQzhaUV//MtaB0KjZbx2EvEkxLubwH7g5LcAzWMqfI8eMPpJKEHOF4URBE+
AEhJ10G9QUNkAa4NJ1wP2LUHhp3HKi49QkOptlQ+SZzOANgMymlkccJmF5l1n05OibhQbkEYKOiX
fVanvKSyElYVukz3Q5uedf/hr0cQX4UqMOeELYqzoPRbTdck4UfRUKuIpzcApy/XcwBH5N/Amdvi
7CGCa6PBtuGccasGPWlwwPoy8JIufjEYJJ5Z9l0u5UIwFsNSO4V7aCWv07yQMKmIy0PRQvsM3kA7
FaARrMcSqD1laFE5H0tPO3qHadPYW6f7gGjBnjVoRZjqTEnxaDn5IEjHvF9oYlN2XgBsdCSMkL3I
NVYrMWMyi+KccruGG82HIn8/31sPn5bsirDm6PQI8fNdKXv5Y26kv0KTZcgF5MgW8Z/kPFGL1IGi
309OqN4LFuvZJzZymg8/YrCQwzzQeiSu6oe4uwob8dInQpr5jaAw5dIgp+J8EkS+UZRxA4/rcCbn
M9STLlK8/OFk/o3g/Dh8sOlUMMXVrDNZAPcPN7XRvdjs9SPds9u6sTDGxs4kD684G/C66HdVxKBc
34d81WPWKy0UeJOnNqsn4XZKKzIZYQrId4Ch/L1GD7bi9hi+Oi20cIcex0cvuT56qn61Uf1WZ78s
n7MLSGlcO4W23jwGFWtcUsMt3o3AqX3qWAdt+OWPk3EnxwzD89f6VX3KxsfYf5U8twgAcy2Po5h/
JwaB330i7E/rMAlIXhO1bkPLya/BiwxL9db1Ebjl2Eh+mjaMJlpZ6RAIyp4GQh6cQ8h0njEPTOpm
drW6drVSGucuBVhimG+cuU15fJ1uGN4m8/vlQP2L9sd9b5AaliSHHURw/+vest0282jHRWgr52EO
BpTwqa60gXroqQIEMsRQpaOZcvM0y8DaH7vM9Afxd4r+atl7uFYBmxpbgyL6uyixZOTR6L2QujZM
8ch/PSqwybIQQftFgscmE1R3kYb4cLF+LswyZZk14ae5K7A3VxAX+Za0/tXyRIUYb7XEIvJGEWK5
+7M88BAF3QktmHzY09C+Jj9DPfPWVDqW/UQEiZyZrRG/7Ptg055MBveE/DcTQJrFPN0JFymiSXCr
nNbfHdOJh030Js82CKOBcFn1YOn2L09sSZrPHMTpm90XB7QY4RPRPSm/gUFXviAeAP2O0ZcQGswo
u7hZTIsv9ncK5ILiSEAYXSzT89rU7AvcjMNyj1cbr7bGxyhXH7VPn1IA+UDtXffhI+leCMtOK/4S
+74U46OhMFKn08+T3QnTeWAEzpRsKZZeIvBnxaCYkNVvSozOmLV5/2rar86EQMdrveW8GohpgnHY
tnnXBZsG/j9Rkjts59iOPmpT6t+5R71xQEqwJHswYW1lTaFQWl8ytDdsj2hmCoMvi2OgiXOuaank
VjjrNNG2ExWWG7EtGHgeMvlgwQ+zAQNvGmkpZGE/O3DmZkxY3nIm7YbvMHtTES0H9oOC8gu6/ONB
6Oy8Iic4cmBaEQK2hKRAzeoOCphAif1VMqlfBw4DIyQE46xDmtzgbobm4KVzUOZRJ03u86I0GxTy
q8WpOjy2/5Nbb/clFISzS6au9ytJyTUz5fNaVuKA6MRAJeemnLsfHsy3NiB3U98TcLq76VLOsbLT
fMh5nlcT0NXVH8nY1rC3AOpnSY2Wb7BodSDiXZUfdkbs7Y9gDr98XBc5jp+4zoj7TNF0R9cJi458
ywr+XndehtrFXJ/VfeYNSjm3TSHUqsGbtlPeqqugEWq3nVUX4oE3pTf0Cjj7bI+A3KyZg3CNaVaD
MPbKyHXrFQODBS0Z4cueqTJdWbi365iIq088axJQLl+bz2CsM+vWqEKqt7jq0QsIDzhFTlMT1wbo
Fu68o/Cj1dKhtES/xO7894DJxnl1kkjMpIm7W+ytltKgL1zlUtDVhkz4nUI/NHjxIZhwFM06WeBY
KvZxUMjs/5pbtHFnQUHq+Q1YZDnMuUctjyrS+egGmOJwgzbKA+NddremHjaN4bKTbJYj6iBBHjGF
2rX81wy3u+C8r4Av1PORhYQtuHZgEEpRTUnk6VbUI4aSBN1rYB/OuNSe5SwzDcLYOgu6eoZwkAOA
6fJCW9ij3ZS/GsShY2eaB4LV2xdcDqMNR/yPVr+Wh5+rYp1xYPYZNyUFC5zyfFrKUqSC9IcCG9Sd
OQpMcz63YShl7MfEQE2R5uX9UOo1ckt7jJSM8F2SYwEqh7OVBn3fl+uDTimWDBMnHO8Pkj970rSf
qcNMUwsx5iY9McsIAJ6Sj2R4wogQFU9v8JynbwJGmNKUX1GgJgQOPBUDP2m9cC5LqJY5v56oZ75c
YreV4KnSCpG/ze7b8/Cud3kddBraxe++T2+AHoD7uOlyfsFp0e2GPJustCzfVH2GBz0EG9W1SJ8O
uxyet4uOUKBIScDtV3oMwme4l+p7FHOOFbKL2bC9ZoFFGPDccWEgQO8bCWPhMn+B2KVDGmMdMDH2
2fDWThRYYxmQkpsPKpM9CEVzO4lDfqpPd2fcDXTsNCIF39pJNhH2s0G33qWUCxtOGpQ8xO4Mlm3R
TA0Zz2XrRVBqDuB+SRgz11LshR1TQULWhZlLj/+ptP0i43xR1Y9qml/T1NZadhUErDuAi7dI9oN+
AtC3Z3jVacq7j6An9k9IAnd0ciowiEQr+6M8l0fMR2G+cCK/XK0XvBOsbr7SRxf+TLgP4jau2rjI
QLXQGzi5gO6vj/VjFzuTtT4/tNgzI3jqrV4q0rMAnaOyGLeerhrC+eW7HAJqLGyweEAFJhiWY+Bp
BOb9o2pUwgdvZeAgqNQU4z/X6x9O9Kgx/z8c2zoadvF8nUWys3tIc1KGjVN8bsyU2AxDCJKTJXAo
yj+5KeGNJDlZcZRQ/m2sxFSwpHok9XkvXATPRJEuu2ANMZpvmr1lTfZOWzDSVatw2KdWqd8lt5VW
xuhpCzWCKtSYZIlNqjuobldOqc+pAwOY89W0sAye0NBcDjvl1eD6QgDmXnAGFQ0LOMWCKojxPy/Z
hanrQGw7Butr6ZH7zWvR8jqJ20xO289HB7uZJRWzYeYQEPsPIOhbRv+L2VA1iX0O4RPro/qr96xP
y82gBFRFRANaA0iHpUMzMgln6/3pntB8o8sHCP6NlD96I51COHrrqgYgoXPKebwi5ekZAEom6oXS
d2aD2VK/euG8idXqJ7cyvBCJJdlscFvh6EPkze0xZ9I6UIqdOMFxAYsijvJCtrsUEjF0sw/PpmsU
Q7AFaFV8zLluS/6leXp1hRVP6boCDgFAI5MrrFha60citT4xT2yxl834A5o3SayJm1UhAD7Kl6dc
V/iF00cDxkRdK7D3392d7qanpz9B4KlQGe5J1rrJwWSU4+SVUTuqI/B7ujrSDN290aOqQ9T1ocVS
i6nmSbvgo9RfQBxXwyLt8MarwIETOJ7typVngmOxNKq50lx3vdCzF/O6zkJ6mrWzskrjr27lqkDi
z/7cDYRDOZitSBoDHGTlCW+YAqo1Q+ab2AKhmBFwUPBy1HE1InK3tUUabSM4x0JSYSidLPlwnb/q
tPa6Z7KZ/CVMLnDgAgCZtROHfFw3o5q1yfJi5PXj2Wau6YyJlhtQ6BVohd1owvEwMBl+ukEbo/HC
EaC9XqWM5lm7lbyWT5HvHy/DYb2V23/YHo4Z2A8aSy12c9NliYk+ESa8DYEbFgjigwhwiqkzk9ep
9hjMjsbujF0j87hmYuEHs4MZzSLGDvHfqD7oGosnxRhKICgNMR/ykufQ8iyqkh9Rbp7urXodgEd5
fZf3ri2JeM73YhMzorCxY+hbrXCfljoF3WocSATe+GQWpHdxY2KT5259phPJ96LsYXv50xrpjQD2
BHgwN/GioU4/rL16AQ7bD+m2oau7uAauDf+HkvPWK7s4kSuU+R91M7wc2uXAUMCtsrXw3pUFWpU3
5m+7qD49Z+KBo0eq6TgUg6ITf32F7z1zSRiVPwyyt8yZrl9hwZEZiCfdPtWw1KX6via/unpEL5k=
`protect end_protected
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/cntrl_delay.vhd | 2 | 9440 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Y92bo4b0+Y2GyuIWDNktz7LxGRzu9bzKVz9wLgYiqs5yBjawiPoSc68s+WHDuTwLhF8A1e0DvjMP
GfoawYu+xw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
it/0B1HgFEJ1pHo6/k3ZfTQbdwQKTdGcQ51QOwfqMlCIJu7K2y+tj57jEshniXexQmQel2fO1fRB
y+DUG66FF/GsN+NIf5J2ShQjyqkPfcEFjF2Fwej0LEkYcmtdsngu/ENnLMJhRUcARqw8LyvVCMGc
Mg9CQ5Qqf0LK9uDBoi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QB+lQeDK8/VLQ/U3uZmQIk5R2GWBkQMkahXvP+DzqjcWcVZaf9cKdyzyRmGSqcOmAmfkpuvYsFaF
ycLHrm5+lCG9E2VhBTPZX5+1S7JYWEdluvqfZZ28Y/dcFnd9kKb4ycmWrhgg4bopu9kvOUzltS5F
+2W3F9bgT/tqpnH9pC0onUOhz5GcifFBDJls5MwToPN0AJuLBdPpxQPZ+R8PwDzZmbJM4E8BCPqG
l4tatSqHu/SG7hboAG/cQ0hPY4I31vWfj5HD4O2jUaJ4coD0u7aOishxPVkkMlbhRkAetJlbHJAl
CKuRLcVnFa+23vJYPRX2Ly+0fansukWKX0jwpg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2nypbkcM487isI/ZQLiMjo3K8WIrTaKcGqffSF7xvJJknRTr+PXhCjp1L4y4daxM3SeopnIXNhJF
y7tP2+zP5KxtRwzRru37dnZCr+NAMCVOV4AFmkWdDK/LCDuyKnMVwaELWX/BQClPTHR3Gmi9GAWp
FN3yY5WC6cO6sNoj/jw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Tt/Bp/zQrsZ6Z7aPbBb0mjZQd86q65t8saM6J5O/KyIDgPr9UfTyKcB8yBY6okpsShBsiB+pJALO
ASecPbbZe8hE09+ro+mcnp4oDsCXsNgHFkWeswPg1VrcAbHklAzjZ5EETk2axxK0OTaxwrcq0En3
PgXbf8Fmb/ehJTtniPisGrBB/hKZhYpLLpLAb5WSpBTSvrq1clo93q5Gn9/jfj+DNMNSbKG0a/px
HRxzrYg3cCvlmDYpUx0SMC5W/WuJwk+IAMQ1NYWwEJGve2ZLvfBPwOR75WBMd3nfK0y6lyniGZbp
BkJEXNuwa/Eq7WznwYteEeA3zao1dRBFOCQruQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5248)
`protect data_block
MPKSrJs2h5ivLkd2ZHn+vn3qjd+lFfB6v5+SO79hPwOSqXUjqjbwlE1WMk6NCPXWOUSehA4hSzop
OfGkJUwDXXzWSXmKVK2VxxnWCmNS63DeScvGHmJD3aVcx/syS/JuZVTfc7waedhp2O3N236NlicE
ecQNo9YRhX0BwQzhC91UcQ9mdGlKr8blmyKBVH02e3T8X3E6GiFGVREsVp3jDb8SkEI8sNSDcMGw
eilQQJ8yLy7Whnr1SP3mCApHOYZVcpLQyWSXxI89s64kRl7eLfflYhGu26MHcP+EyJaWd1MDb9Yc
OtbJ5obn7DC0m6rH7BtEVvqQ7SWE8y7SD1aRUPZvFVVpxAg703rLk0J1hTSgfWY9aMMGBiMijoIc
6Go07rIH44PNL+gy0DiD1x/rYnhkMY088VuvoKKyzgWQY53C0eH67P5V1dyQcA28esfQKo45HUug
aOA7GLXsOlN96NvK8ho7RA2G140+7Xo89NcvwjpaY3mNDWCTzFLQ5mSclF3WcjQsPkl/yqMPJltT
c2DG5NApHEzeNjp2lClLZDqEPvHnKuA2Or9kh156LWZTAQBzagLK8dhm9N92R6yYoG7wSANTMh24
3VcakUFpkYhs4guQdjoPD11R06eadjp34xyAJwAwmkLLexz6ZL38u5SYAdnj7LSWk/OuTVt/G0iF
C3Mrh+4EyPn9DfRRRqK8Wlt7641SjMBI+wXF1Pu2vo8/Ssbcq3CpsdDjWwHsRxptAPUQ8JQTgvP+
j2LQItJ27ic2a1fLWLD56fh/KlVpKXedTydxK/INi8KMWaelGn0MOUidxJZ1dYRBnld+5oHwUJK0
NJsg5cN0cdlQU0V9VrUQ2JOO5nN8lsYJcXkqswvwTmJckUZaBfTvWKzoT1zZwq1kEdDVZ23YBNQ+
sowAc14JaTslPWA/ZaPidK65LNSoe7ZtWFieNjGXDXZ1LcLshLcNDQ6iZvxmtWK+TMf1j8jRcf86
3O90Fl55jQ7mTO7CSP0vPTtuPAZOFG9RPXdJdrqCtjtiQkdoQDVPhR/xcJSPPXC+7nrMP7fOSuTc
KR+M1Hf3IInjiwkffEymZ+CvLGQYkem/preRiEZc90tkpGKdFe1qSx+zskXRGyNDADo4AAkCqRvz
l9e/wcuS8kTk0fdda2GgnAoD+hqPwBA8H1Dk/IryJ7ELPDwlHWZ8btLe59eylNlsRcA7b03PQ27y
M3Hftj1YUw5rRsn5S/dy5C5bP4Kp4M599fQ4Goi6y+8gQ0k2cSfUDP8qwRp7FnbUgqyGa/l0M1x6
Jgbl2bEfdW54/+l5CuS1thDo124iM7Wk4h1j0/uFI4Tmigrx7gWUkl4ETmWNFTWYzC3pBt6r8V66
2zEii2R4IkBrqQIsUN5IPLg+TDGVRmNHKOHR50gaKRGmc46QxuNakELGjZUrd/f3LXtXTUJeB9aN
X6gu/abDP+tvQ7s6uI05nXKxWxLMY4nXxxOjs26Z64YpXbboqPgvDfwL91CKoqPTYuM7syqJPrKN
q64gRWQTlNHOYaAH1IUXaKudBu997P4xcpfPJ/rKVBTGYc5C+o0Dnq5sirSubTYReK1v+Dx0MCFg
qvz/hpOvde7F+yaXcdK+U6sfVRfD1+tzZRHRgGtbvsswHZT9GQvnirNPiVNfEnVwqpQnrhxylUXT
k/f0Yn3Z0zu1t4e38o9xiLkLovOF9lJEvjKPa/CaTCidyHhyoH5/TEs70db/t1pT85osCu3IBas7
Ebmwx5khrZyC22RFiyfrG0u2fYYDr6fpFOSw9ABY9fh9z4s7OY/eaprdUiYy9XYwIYag7lYGw6zx
ge1IWryWFCeZ3acLc7NIScqwcckkvJ2njbgbjxEIC+izn8DSfhyNEUBYwXbCU4YRV+271FMQFklu
JoYGZrfj2abWsTlYGf/PNtO4d5svhS43uxGagjREMbN6yCPt5kaG0xvDBgKSY5Qv44qEoGF1tNSv
DdVE9lzHJ4JKwHPh199cpGJZbKUfInTvH5uut3LaUmGpvvNVUPJcC4EWRMMSluZu9Wt5ScFUk8wr
Q+qJre190ymkO27WXsNC0PyNAHB0dQZMMPXuKMG0FBOLtFopu2y2Ad3Koacp34uF+tft8J7Fyzay
eICER8K2zS+bLJRm4Be1ZQSLBRSWjjnjIwXTGVNtk7sEq084koAricxWKPZV69hshxFkGfwyp9Iy
vtYmXvxBkKeOpgkkzyJ39axCHWBuQ4iuJsFnKcVFLIXvAXI9sjDsll8g/4G7xwj73XTJ5agXuJl/
tt3okdVs7wdfVJyl+n82XearC/jGrtbHjgffMip0RL7v3S2hhJAJ8ViSL602Yquv5JaUP25YnG6q
AUtaL2rsafxAHtPzROxnjHieEFyjo8gVvc91HhEebnSCRtUamnvtYkZIzs/wyBplgF/KzmTdgKwy
2t3jwV31cqFFRTSHNrQqeOwL7Ck4cqdEpP8IJ3zEYFU9W0PA44iyVPkQHIpeS2kIa0AKtg5bRWE+
pSn8XDOpmQj6MCvMlU6Fm6CSeAWnWrE4H8o4Gbf4m+1pZJRdq3wqHLwI57TiLo9h8pr1WxlG70C/
yqwuAY2CqWQrMNZUawMGn2mxlZ1idoMqQg3TqonFCdnB2aWhNAAPE5ArB2vxJ64aJKOrK9+2IFYv
ZBTv5MhJ/V19MrraTpM3g6l9DJ/bt5E5aYHpAfr8IWikjncP4NkqRBGdz7RaRrWERn8OZcMjg+hC
rts5iKKbo4ownPU1d4ue7vcA6hGxV8G+Up0yQWk8NEJzybwjmcP/PH651yI6UD7folFyvAcjpjyo
J2feNY6NM/nEwW3+2Y75j1/IxqYl7TIpK0rQ8QkeFNiyccD3TrMi2Hr8zNvgHM9RpMl0KdyTlq2+
CPCqNCoe2ugQn3XWhxufm+qlHoCEVtdpAWENijWXKkp4meoFOAGLvyZZDCQ+ITrGhy5M7GCDUAIT
KuEVGH48BVPS3SZfq+A9qLdJqnYQFsgz+dlnChdfwutPz8vzrhFmLi2b6Kilkl4F3cji5GNqtEDp
Q4kgdyrHSXmvx9m5xAaQsIxK0MR3Lc6PE0cHtpAe1U+lfNXJe67BFMBht1W0E+iHH6t0i2ZoLZsW
ZqcIjBot1/yMwPBY5y7s7kGTwlMozfDJyr2xgz4qMTGsg2GPPhLs2bbnG5QAbt73yMdDE/mI1x24
qbthYb3iPzplAMRIesIQB0pJxcTuVcqzMe2WrD7VZwyj1w7lcVBil7ZZ0A3ZOLbOENJvD3aueX6N
wsdvBej/u8VMkpUnSEvZ6x0fM760jfDHdGnmYYBQ0LYAd8vYWHdS0tKZA8MK62eY+n4rIJ61DAMD
v737FA3YGysKackpN/2cPc0fTv4As28X+8D7TunJp3zSTw/O0jM+0vB/boJaWR4/vQFe8pZUV7OW
g0GuqVUTZxeOzk63AA+0x753NmZJ2aqS4f9Ak7UcJiLpAkx3aG6vdmDVllx8gHub7ujxnKPt1cfj
VaKDUgTpPgr1rrMkxk6wnW9/6gJl3i2R79KDPN9NQzoXsqVsxbjxxd8vTlwxCIBGPWtUSrReFyBW
vjNuDii7PvxPR1ABl55Epebe2C0ab0oopXG74sDQe+rAGHq9SCZ0Sfc27nGrLpKgcNVvl5jRS226
YWcNzZDmp54B+q6ASWjSUe7aoeZUVWr4klxLEna5alMFvmCF2Th5mrJodVwjCksOdysMTpidnsTu
dzeaQMUqcWPzdMJVWKBrZZEZfCnryePF8BYal8zzMGKC9vVFEZIHPUkQjTQzTAunXTrUt13lSfVy
wbROhGQ2XgGlERXbQQ4550oPGV31lBYAL7YbvzTjhFpu6vWtV0j1s4MnEf1N6u8PsxLzdQ/AMncC
YFz4RrAUG2iYr39JN2HdXTNx7MJlsa9nNTwxOelCUUpRq7a5p6TpmxZB6zNQE649fnpeycXiLnh9
8uFfhC8j0kps4zOdVV4KKiBXweji3dI5YIoqvv57sy5JUu7Nky86VBghINgscdoNdEHmD0L60L3n
nQZ5BZPv5h5wFqwLDcZ6judKA17kyRWxVuxGbOoNv5VpcmzcCzgd/jGfC2xonw0tO26PJ0K2MzA/
4dctwktGK8gQ5DWtkBOdCOZJJQQAE+ZJKxqCgDSS11aVltZ0Ndj56RmOBTqQ63MD9MIWfnJ8oGGf
OaSPmTKYmSlQShz1Tv4TDbDqUZIpcQU8WqLKJnIXkmiTfckwwgcjSmcXlzaVS5uuLDy84AFB7s4k
b1OImb3gkX0zYVXtCUm/lYG2+C6T6U3tGYlWzgCTC5LSYcc7kL0Zor/spU71SqM8BVznuyn+aher
5sTMRR1e6/3Bp2tlhBv26HEYnaDNI24MNqIdqkPC3X6O52UJg5vRwMnJ8RoBLU0Li5YIdFT9rsvG
xdNTf6MFNMY7MrIRAahvzWNfPlu4Ug0hh94w6CP4bNt8mTUapu8vBy6HVpLY582n9oI77nkwwpoW
JmEmyYtxW3hPaPzfQtoTD9MiJo9EcVL6bHnYXSAOYxYBcRxRjQpTao/T5XXbEwGWkQKPdEhS6f/z
nazkyAMXDNBQ/rqD/DGWg+YUPz1eh4tOwXIVyQSJ/z/qQL+yheC4ezqggKb8nCSfh1M8aYRjqfRy
pw3orqvFxpe2lzNOChL1YN0qCin2e2rjtVJOvafxixbCwAeCs4z2DL3OnhUaGNFC7nhaL3+Z1/cD
OJXOMlheBhlIwpV2q1S6IZud+/lpInBvprdoqwFIfwPHFvIUAJ+ueEvwnCQmhKmwKGbPkA3YjXhZ
0+agQYQrkK/kTfsuLh1a+DP4C7MNcZBtsSL/Fmcn7MG+/KqQ02E5l54SZKAqz//m9YNjeFGXnuds
rsBIYAjMkY/2TChjKDSenp7cNI5HyGWQftPng7ZScsidiXp9mVqRo7eZVkUbUhBg8vjDNDmqM0jj
/6OxYihczZJvTd/jYsWI4dUWZYw1I4yCdNsaS3z6YvSse6lD6irZOHacToT/cyxsYagM+PhJ1nhK
0qr0VFsNHoSlBZSI2EgkWqgeq1Pq1SXuLjf/vhaMGMtQPUDZACkZ1pdb1INAM6a8mfsaLmW2Iwks
QAG77iGaYs2dUX1/vJpHukbqYUS8GZzWoJL5r2E7EZVD7vkZ5ZE1gN4kWjygvzmF9GpSI4qoLATM
WvsjNSsROxNElcpZNHlwGXyPz2G9FczoVS6iObsRmKv6fminEJjJhhSwgjFvxP8pCrVPFaXMTQoV
p+RbO0AJ2Tbs+8dqCheTS4nDAPVQnn/Aa9eikxxuO3581XUyvHyPRw3jGygSbyzC14yWOgbIsJs7
QeAuSXCdwlNe6WUsb73ppmbhjXejIifXgkV29NmZUlO2jWdHzLVrP2tn4oWQiNdSJUmgQ+eDRSaT
M7U9mZHGTfmIj3s4pVyXGkR9IzQmI+FNUP/3biGyYTn5q7eJgoY4DPpGzmnW8qyFwzbzUz5B4xZu
/zoRnL1y888XJaEpIWeXG6aHaWQEz1BmLp8h1/DO25WeO7vg2MRt2r1znjqI5pxpAgdMf9g2gN7J
lLGgD30CtMpDUC/nr9MWEhRE4dfcDVrJqy+cQi67ktliyw1p0wShoSBD+oCydObWkuyAQsW+Y4RP
bgjyyXyifhWPqQFtb8DMrn3nWKPBEUJkjiQHfs+h5EDNxovEUoakB5alj49UeIjh4cFwyo2qL5S6
y7b+y+bM6/7foc7wW5B4UGkHgHzOtwmYBUyTMrJK/VA6zZQ3/09D26GV5D6iyrNk7LHuc0US3npb
xw4NR3JTLaOKu9RsFT6YCD+INIKlAvpG6JDyUo+dzZIyE+kMrtKCB7NDkbijmEXuMvkSC/YzCzK7
JQecjs4abWygwL8jnFi14hIW5egwpnKHWqGNrjJ8Q3VgFG87jPTdB3PWfQ2i/WD1Elb5cD4MYZJm
Yl9TZRBlfHpWPGmOudt04nUryQ8skx+ttiOErbVgnjVX+Czs+nln23Lv50weLq4Oj/2h7FEAmnh5
78YiyacE41GeGXt8UQPEfN2JWOTpmwkLALU0VBOXGFkAIlDHpQjzyoTRzDMJrjU/qVId0cYCjU1C
/iKIqdGaV+xiXlYGOfWn2We8cKkgphJG4UEYGysKaCoFj4vAcSsuOUCKS9U/I5AJte9Ci9+GQxpD
GBXQT0xM/bVJ+zO2ZYyFfcknwa9V6aZd50OgPDRm5lKcS7t8ZVhp3Ms6Xb77c9qePgit/8XVIwFq
ehgc3hnHoMwHBYic1YaMT3fQrvTp12rugamec/AbM7I1pRrv6wc8b0cL8CKQlWDDpv2Plo0XsQTM
gJdshU6WrD/6dpPS+i0JcY4molTHtPLsLuF0UHlNs2S3vVq9vy3DvgLyMReUro5MRDBLrrTAZshZ
bqsrpwOXCWmFCq2zpEh/TgUtD269eWRb6u0oduDWL1RMbldo1JdWC0mqRvW1pMwTq7/k/CkUWJnA
xSnqyyImOwQRZykzkudbBDoFy7RT3woZs8rPR721SFBQpMZ8lpW38aAIZ80iuUtBXHaMkLA7t0Ct
vKtzHHcY0r+N8nzfBqCzRBCUn6b6nsXNE5apnUmUAkgeIbr2Qq5Pkd3+vYbm73njb8CxZmzNvSjK
JCnLiEQSemDQJmfkS/Uh9KFxV0z9H/lIQO3f91LIgvl28d4I8Pb2RsNyz9U5BvU/j0dDgPQjjSg2
DAhN8DP4xoLL60HCkPZpOm6Si6o0tHnVth0b9YUPYD123egfSsqAvECdU+c7kIhtUYElfRFSZJW4
M+KgbbSw7yyTNtSDRuqx0fN0aOc8u4IFBE5+PEb4l7AfSE4Pi/PTvSkSF8yEi5RFVj1CScyETqUc
rhQuFPWV0n3WCPsqfg08TS6GkrGDpJhYKjwHoaZIkCyiaiABTuvCgoWyuyrqsPkGG7xreeta8Xym
hhjpZEyfPFI0jFkFLd+s8tCkhXRtd+PA1btVKIqD+Bdx7nfduR1s7tfR/Cp5odAxw2aZDmE9sKg/
cyxBPQ==
`protect end_protected
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/fir_compiler_v7_1/hdl/components.vhd | 2 | 77934 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
NCnPn9EMfeeGkNOZHewsk2qZjbTkxCAiyhgG7pHWLqc2/977+UKlUqmmzmiUQIt3UMbuuZNtFyNy
wNAW6QoPkw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fu6Zvf3+vM3aj30F1X+kRlfGyKq+lu36azwkAmQ/sAgaosjIVnGuNPUqezfuzTUsmFODFsE3ticq
UZD59nfmPkza5fxdJXTk8JHVsdZzYh/7Z+niwN039ic1DiU6DrJjV7OU6aSS/+FS+xgIBqumAVZu
fmnOhHvUNy5Vqf7e/Tc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ou/4ZMNrjfjESNRf3k5gNrbFQ6ZZS06x09izPEG+Gb+4vjMlkQgfTrxxDViYYIuIkGJvNZkhOq8c
cOjDPX3Os/3aon/vqyPkgGNOGoRU9d2wLMUi01z2uHKAbnX2w7cmTrGWDDOxkqGhpc58/JwwWas5
ZVcGa2yCq6rK4knf6BuRloi5w4Yv2RL+WRJk1Blv7BlxtW2er4THGlE2ndARB9RaukSWfM900Pze
Sgonqy+HCkwzVO+7zwMo6H17zjhc6ovcjozMnvzvlGM5ih/H3/n3uDC0hv+yEAJ/tZrRky4/j7HZ
DgwUPKPnCA2KtARPPQAbkEzdc4TO7A57PEBdUA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4T4giQRoEvLDG82I3rVBwAuv3zlXlryL2P8ddyUrgGgIqBIFJq41WJCeE8Zy7Kasxw+AexW2ZYvu
US4V/jYluC0CifBp4JV4GSeM4A1VlmbGhKV7aqSjjXdlTUFCmoozW0bXKlA3XugyA3k/u0GWRZ9m
phOZ5YXCgLPQB+SmxCc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hxCvbq3L1ht6tJPA8Gl/HytlQsz6C8Tl2nQ7RXP2Rfzzc0ZB7CiJ1A7jshFp+Ub+fQkd3A535skn
NqOz0IP4XzdNaaX6x4Xw7WF3elmtbjpck3LDefChLY3V7W5P6STG7D0fN4EoU2Wl3B6+/Qks19rW
sU+gtK3inD0okvDoku80j3sywxOCgJBkKaaP+yiYTqvH1/DkTSLyUaMsOnwfbIH8mLn+BxQ91plM
fZddw8yJbLCPBGvJoguOjdsntL+sBpErBZ0iFExFZ0KL6FCf4lw1n9pMkI9Sy530wMUO8jG2sw1U
IUN9voJbajwjfjBaeIb3Q9zk+P4Y9KzOP8tSlw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55952)
`protect data_block
2UwaJ1mZXkd2cQop4Rg6tMFNqoJQIeYa1cfyafVUZ3Q5XPyy+HyAnKtfvFr8CnwgZaUgLQbPnDIe
7yepapMkvEcK5iKDv3kn5eNhNszGFfyRZ8Xy/B2QqIgdM+VKZdwPKIVqVgitpp2YZ2ktDsU4xdNi
RKC7DeiQPbScpu9M0Lpega6oD8J5dOymjtjxFcBikkdl4ffMdFCSCDPf+a0JvOtTMTBnJhhdxTfL
0qMLhdX6+y34MBlvhN5iVv1GFzBx6dpIy9fjGsz0DXX+Lf74CP84jbHQn0t/H/oI18WtVhUYkvIs
LwWMqeKSUU9/Yg/J8xsF8PYQI2LoUFCGj3on2IbA6zaExc9k8kSdH7VYu8wI/cA/7Oo1CCU2R2hn
urtwWSSNNdXbmWXfLGefzqiJNzPRLYdGiXzf4dWFj5uLQQ9sgq4oEtD+wiIKLDF7ZhLIgdvDNdl8
lfetlQfWdnM0VGOO3jMvE42pUOKUeRLLAPquKQeYgr9eP7YrxuVgIvoiejRjaFwjn4GgsvZzeaF0
vwJpVSQnkIB6rzBBvkTKT7cXdz3GKDkkeCGCOqLYd0w6fCmN/Kjvi31in1t0KJNX2lVAYCiNMWhw
/4cX/cZUQ/S5Tz6tqApca+IaGZO/Jq7iDl+E3qHWq0zL31LP8yvxmFB4DYruv9u9lMWFguOiZpBX
OG2Rh/EZa7zkqNHGjqdszSJ8oByhj3s5gxBr146fxcCrxrkM8AmIZY6juoVNbaQZ69wF5wT22xWB
dKDwUV3WQffUo9cy32nk1FfUIQ/Tohq3PRj0bI4j9JGxE8+sPHfnEHTo1KLOjLrC2fGff4K273Bg
693+aenFRjPOKy99+Uq1fFnANvGTfgRFpod5D2VsO7NAPTpeGZb8BB0Lx7t+6LFtC1e+W1OBDetd
6dv93nNjtw4naPMsu7Uu3BUEZ9uv6O+QXu9gpHmhTOH07ydbv8+fPlIdo7zazq8HpyR5v3MVjv8O
7pNp3hJGNVDGKUrNj0o5wsnTlxiWMjyL6lU8XoFGlrx3iJb6do3XOzr4ngPjRCl/ROAm8ZgiZNiC
fDT+EjfPTOC3zTJJ55wuzpQgixwF4x6X2Za8lziQ2A6+fhaq7PqXRRqyT9EvSy9vnu0+Cj+301RE
RhVg/xi1N81LDf01RZr9Y6NNpmkYjAUXwFihMAW9LqVghLzfupGviE+pxtYxCE2/PhYlISkoQANo
jE9g5nkhtOCYGOUI+dXDP5I5CDRtpFuiNLPANJyAcF4i3fbzGsNAes/49dno8BNvRCdhLW+U1SZd
HHKNu61vLdZmBNe2ALwU4KDjsBo3EO3eGHl+7iAakJ5A5V3zPAkiuvez2O77rxUnRRCVEcPlsQWm
oXOv9btADiS6s/YYGvidEdjduSZyOFBDZg2X9J+xVkGX+LgAl4RwXOKHtrcESnktjPNdNAJt051x
OlzDeC5xLX8X+KOZHBX73nb5QxoulXLgfwtCB/c5he5TshHSHYUtPSNlJWhMvb2b7DDpbNRJXE50
IWdM1pGHzuXTYXjGsUqLM19FKOfLV+S5hlWuSEj2aMRK52JVXqJbwAAqAgNQBMYu+nzO9M54jddX
Kdq6w5vUL7FSelDlRf6EnxtVPypKfjGKBxsJh/5mzMiOC/KfYeYtHreHsbGJ1fJ/V7+uEHMKc7Fb
ijCKqZQO+St14mLJOIU3DHGSLn+nyeUdXoV4XOqS8M3aE/NTNEhZyNWZLgOs+wfQQ96E2BCbjSyU
mscbjUOGR5crmAx6scIWR4dIAF3PK2y1mv0wbDsDMG9GYi11Shc2eyo/Pj2f2FAtxIRapCYQS3Nj
r2uio4hJO5KYeh26FAWWAmiGJs2kcFhAXoSIlfV9iCcb5Q3igENN0sMvZpMebY6bJrRHVxlMxPdu
rgzjahUNs9e6BMSulqTxnFJSqPIH1E3vqYgPmhQGxkURQ3W2vNTMj4wDiN3CZ/lurQiHWVbg9QGq
DdGafdutC+00rrqaUt3fqs3KT0KAUhbbj4OdhwY3G3Y2kgOw9uh9SrlMEiLHphXXpwuTPELPc+LM
ipCdaV0e6Lg3xC7rNTP1/DjnPo2smgmlkoVejHq8NhVvvWdfiC2gr31p2WkUoi3ncPh+a8DCyiQl
udBTT4nYoyP7+jm3cbxDmxPIqMaiAaYzayQnh8S4LeyHgIximWwp/ilp1BhQyKYu7EbKt8j9CPMs
BPeMbHhn+DQCV9XK5fav1GvCpw1vSI9UlFwHqpQh0kfrp1Buv6xM+N3qCy1UE4od1JP4+UUiq+aB
nrngL2Ypz8KpCmKF2IhiOxt6on9sCnaZxcthTAziyWc100IWgWOyp3aOiXFgKE/36ewixXv05TpG
ePnvLhRpnWS0LDDPzeOr+vZ1iaOp/UEVqJJK+73yErj2zO3IBUTKCimFhnq3RAs5PDERqrlmtyp+
jdweV0pwFF9HBGDOxFw+xYYf6fR80KBM1qhS9quWKJULAK/OEfd0d0M0R7khl3gPJJNelr0j9h4M
2gKsIICH3LfCJgPSQYjPS3WlGrpqx7vB94En/ir2gLfJs2QPZen/81bYHtqB2eJMOEIGDTCMKI0O
NQYpWCXpEkcFX4FqOsC1y8tz7qDsf2jaawhyKAXoqrQ750phd/9XhzcBxRSpd6UA2KhNZ3yuYQTP
EDopjYR3j7hs1O9sb15MkntZazLws5xlANcuItHXifbg6XRR/XehF7U8Ero5Ga5MbLHOGyQq8DlV
CEnsSk9aSPVTCiC72oW5ODBj0h0aFfA9U2nI1GBvPv01M6hZdz3GJN7pw4k9kbCn/SyHhfEw+SaD
iEfJ7YxC8kycKZY3DBXlqDkwel6z2Lny8rR8NBq+fdHrSc6vtnL/vTFEftq5Kz/jAjs05oWeJiU7
++HgZJgRC0B5cTkVeHaefTaPWJTFr/ql1QTVIXgVk093bXcdvyWCuH1xYyHCuskfLC5c3TpS/2G+
1yrXpgUtHB7FP+vXFLa8EyqirX6tY8S3EpuWvORkezre0MsKN5ls2RE9pzzAwTl/AtDPdVO0PwXG
zl9/eZ61lUbvFqoPAcg89v6C+SuVkDSuveqXhkYfBCaNoUJ+g6RqIDZRcLWSa+449VXBzpxjpYzv
LXd0rmIvlXborZexdz4kFpkrNZnqmkCwjmqfLaZze6bAbaMUOb9tQuvB8FQoNjqdHPoOi/pRO0Ev
gBq9YStjnr+xI87Rpqz4MUoBSnxZUYnJBQIeE1+G0ZnGQcrBduQZXIzaXy6bUhXaMRBRaTQp7ZUl
zpnaligqlDxcU29jo5eCOPWLsLrPwsJAyjtQcQzJGgo3YZ2lovAHDE9F+IHSITU4LicfFOD+1wgZ
7P+PdJiiOhplqgWLAgBtb0AssMDadjNejWpwAI0XcHCirQJndXnao3t1AanZTHw5itLRXHGPxce/
+n8t5mfDt70lj7BZp2wyK+OLjutju+eV/vlUTYe+3YC9ZpGmEZOPLeWlGIuHpvZiHAQs4LFo2Ta0
BYmauWN1cInCM1LUO/UboyHKpSIDe7QTgrPkPc7b9m/m8hUNI2Y+2oahRlxK7uiX4Wk1q/05WftU
hf0uazQ6DnM/pttnwcXLJwR81k9BFYXZbunaMCxtBzdTg7wKJikZ+yZNPkDFsTyIvmgPpzvDP1AP
I5rPvrxRnEi+C4K0ag+TJo9X7qDcFf4Kr+wnUp3H/HNM9twTGhIx9BQ2Ji2Oz0FwS37R1CZsPPYh
RY+7CnHy15HncMPY7HrSc7RXhP5YTRx1DOsmIEAACz3fudN1UGnRcX20SI+VZXxjo+OrVJv97hJz
J7higyUWK6MhNxOUzb/Ae7UxtKnyfw9l7uucJsECBYSGTVoULEmncGaxpsLcwuOVtlzCXhOoTvWj
kXz5T93qHTsxlGe0mTrLaw3toqqmJqgDb0K9VyBYgB7nkqPu5JBakxiIyZhiY2eiM4xdnZSfbQL8
236jselF5YAtgqDdB82oBsoLbqC0EbZI8TbPAQOG7LQgdwSPM5La8czZDGOx2Foc5RV3+u+UGcf5
+VFTwNB6m5N4AtttlOn9XyyBX6AadDg4uIreVG0PCueXNwp3ZFAKbgVYw2FUsJ+PuaGF5rSWseGQ
h+6tfbHBuJcwEfM2UBbUWhdYqk71VtpvNSbsamVCI2BMiYyI39t3K8FopqIjB2JSE28gEOqNkjPH
FRfoTCQXykDmcL4cKwlhzYnrH73NjQL/MJ72Fs0Vi5K3VnDyhOV/ip4xWN7ZAdeCeV9I9YqP2Ska
C1DDVe0sEQenbfHX0aCOasRlw7YYGxI/p9NVPknUupyaM0xIj+lerpUCM3LgKVhTjuozVMRpyO5o
b8NFRr+lsDkcYI9EpYoEcx3wYcJZbu1IcD84vg4FUfWXbBxUKE8DcDluZqTiKKZdM+u19jhjNlWz
GOfvafMsd7PbTmTpD9dpiV9p0yMb4HKVTX0+o7Mj68Y3mhk7osYbgRaFfhBlVeoXjCabAGlWeL9+
KXW5C8yM/PBQXHrfumr+7RDKfPOgVtPx8ANsxckzwxq7zMMHFnCw625o8TM/TQ9VUoZgBReeTC4H
x5Jb1jWp2AXG84gJ+fIu+d1UHjiZEyfdyDB8Usv3aS4jPBT7c2NEgdDvK11fzUB3Qt5hBL24//rr
O1B8nEKS1o1L3jLrJooY1Kn+aLVdQlDGnkTCjQofmPpOEs8E4ebfAH3cPb6kkgcwGSM0R3/Z6gij
nDNiwCht0bfB7M0jNr/XgOzTJSICa/Z5h8vPxLSngEGDBDCHYSqIdsJgxbfmlmNXrKDOvskh8xnV
DVE9IG/RxqNVEFWOIMhBmV/iWTssXpOYbobSBhX6vdmeCpOo9IBeEDNfe4KvEPaAMpvW+FYJDOY9
zLryyY7bCIBFALazK4EVLLeU1TLmaXlDYQym6ga2g5oqLP+p/h8dFKxBhmHWCj+ybAUjsM44G4ji
f1uXNEK4mBeE3XEFxMQlSq/yAzyF1J7HxcIs46jhl29YkraQaHJ+uE0U7ahGmZZ60hco4smg++t9
BsSoYn1tOU4mf9TNENT3FGkLzFxHWQoEKqF6SCogBoRmaBzW6+LSy4OG00qbbzkoaX6kFnTxJMX3
s3UveT3Ow+IakjVH7z4I5+M/wFF2yHG6P1XJbTHpEK/rsR69FOVZVdcqwwaMXDi6mj2H8wxKLeLA
NPuod6kKojaMvyhdqmWHXx68yC3UYNdsEgtZnhvU2hmlkY/uw/mOoLk8TW9y25syrDLBhwMIOp0A
fslDOOdKjowVjydtiEzowSUyVzohxDTi6tJb143azzmuiauG1uhVjAKReM+erMVpTeti/CDxM/tI
YDeWE6Z7NAJ5itpeYzf29I3uPkvIwEzjUyNUy0nH+L00bSYYYhnJEumNMwCrlOlxvEBnkWcjXq6k
LyWWh38JIxBNCRXXTc8p0lmhhdkOizj42+xLe08ns1J2p5cpzoVQpEKdrvik0OJ8f3SDTeEffat4
vXU9d6kAZls3E9tAs0JN0b+Nu8/q1Aio9Az5zinyUwBUrTQv5wboibv0pDGPjnupVmy05J5JEv0K
nSZTamgbyfFBJ3h2IRACIKWXFRmwtC+NJgumkzoMVs3qitJwzOWm99W/lIjUy9/L9gxUzU4GZdqR
qmbEsnECoRGxdvw1U2lFE+fUyQelNdffGapvfxlpTCpmzc/rtu8rHZxSpAxWqfCbsLcYF5x3wyyR
taMdSh0PUttYp+du+N+mo+KQieC7r5599iho5miaO2JxCtbl+QFPje0XKmXJDMMdkCILxKVeoHvs
EdCbAAPSfynHR0/NH/WsbrrRrZfPYi/eWSnPhWK+2q0L8ENJHiI1SWx121eha2+Txz32wFbFX2Qk
QfWNnBsWgSGDXuUNu7Ht1dte2hLbT89g+q+8rhrEB0fX6YLHiWE841lzH6q7hTXcumiu1qi/F0zZ
QKBURVZMhfGhL3Plnf3RLcn9HBwxz9wExpqCVAXQDRRKMEukJb0HpjtBTBVXGNd7BM/wUqzigLrz
icJHgvxSdEI6FVzCmVXN1i0s2U8fPyr7pA4KUeEzlRvreF6wuhthi5moT6yLoz7vFR9stXZBNS/A
Te95VoolM9XydHBKFGGgzeeaL6yPFMk0I1qkkm/mZwcvZEBWzXGnPp8DWWwuhuMY3//Gg3J4ePHw
bRkAOaD8Dxc/CLeFMq06y9Q2JMAbQ+F3EE+Sx/RB4APvdMjC3vs4HWGcn82YU7LquXAvSYXwefNA
jhL3yJJEzjkHZfnzaQEB6cCWygLicJaYHSWdVqO+FtdVerjF+uKLHJLdFpj+d05me71Pq08ZmLcg
0lXH0vKQt4cokgtt7qm/IwYr1elxTm/7fVGSiJJ2VH/XydXgA5zB3ggNzd6gSsKG8ge+dLbmn58g
bXOrdh/y1uI4f0Kag9+VTe1YTevsXkaa4CJZ6EpQw74Z5HHjMCTLByjMHS280ovYsDFH3qvCCQXk
apYf/ziSRzgQeunyfTur3hA70QoOCQ9+XqNExcHhVULBr2gbcx07Vqe/rv+XevNPuBtO085uKbJQ
Dagb96M1GPvvetOBEp5sozkEoUux5x2u//smmpe0sf2OEI76lq1mJzvQNl4HZXaELxWJuOJXgpAc
zN1JVo31oicJQfouquZlIQevBa3ES/pzgumNXC7Dbk6SYg2psSHPEf3bONJf/yEQYwBa2jUC790q
R+b08C8xKZM5v+IsdAxX786wW/TJSlvmXAh0ax1TcnavTcqmpANYOGNys+eeAK1vs16uGe/dlhvI
oFvJqadcN0KqRx6OXr5eesNlHoRstJeN+QVjhU+Vj0G5wPs5WIiN5XrDpbm2iS7wN2LpLL0r/FYT
vyPaxn1wNmlYilmwduzEY2Ar0t+uwx+tZbFHrxbZ1LwxbRNHJIJ23MH1KNaGkX97baFfkr+qk+oy
O13WvdgcqiJcOkywNifMcDYWc/qr/OXkcVunz5Jy/9g/v5AwmkAzPepLh6MpoYf9aHzZiviFfOBl
fFeLBXGv/+PvZRxcYGPFZPzC+9rdwXtxaC05gvhmUxT1TbfU9b0JjsTqODKEBcHrwENH3cY/NV7N
iw1iyfBJmEd/KLTnjyMYYYvOsv+qSppKDqhcGh2De22q9sezH1213imYRyc64ugynugn35qlj/9+
9wlfoKsPagtwkXj8sKi/KKnqzLQtNSYmMG/SHx0AhmN26Xj895lfgQQlfpr8XFMReEbtspLxj2SM
dHCMh7ITxiksP1uDbSDFOp9fRpGsR/h7sd11bIh3gt4pbUspgSzdQogp4hI/O5SngGtfvZ45ugW8
Dr8KaNX/7T/zWZs+lyzwUgtACV8wak/ZlGRE6yYZQ4toG8Piraskad2XhjziVA2vNZiNqcUa41pw
DjlaMmXv4slaXHZb8ZC2rL/KyuT0xACYrJHhB6TtDTAN27KGHN9Re1Vc3Z+xCxPoI9T4coJxUfsR
lHUfhR/tjKgs8ThkGVuzRNvYiedj+59J8m8/b1u5d5svlZMgMmymZ2bvCVKmBiWzBdLVqICySPcy
eLMuBkOqnQWZVlCt4qN5B4ClNeVqRPZKag7c4SnvyNjCHUHp6hTZ99v/bLu5XeRAQwlIpo5+xKZa
925A9KKC2KYGJT/UHqlwOPcOuvPy+RnWeKpO3+rfcK2rTPN5CIMOk9smUh3vfpcLbSBqu7KZgKij
CgfgL3+R3wiTaay0zUIuGVs9BOtGeeoSlW7Sft1xSgQdOpvH7m06ymc004FiH/R9PCNjzEVHo9AA
PGZW0OpzclpBhxpQ9ODkOI33hoSA4+zHwMDJVOky/EZYNxP3VFShX1j570D4JzjVu3HYrK3ZFPZ5
KnOOMg3Hga3NaRPScxTO/WtBsTFuoI+h1PX9b5xweephZ/dszLznvq8vX6Qrrv20fNx3i+QLkmei
YMvmhPhvL1pu/T8fD5b/hDENZz3GL+XxUYwrhOeVR8sJGmCwYp69H1MFFwAcpsPtaP5999Tuuz8D
cZtRBIaOeg4lMzezAw8iim2zaTdcHkTEP5UGFmC7ge9fpRrZJJTf41hWZAAvvwy4tcDw0k3x6Zlm
DE5baGhK9iGryt48pXlWnGxl9aqANEnKowSLrZ/s/YB8UecW5zbOaxN3iMhPLaG7maXf4np2kIsi
GX2okJC3r0/Qqr+g8ChrN6yzNwd7OYB9smBu1HavUPSG4Ngh5qZKBRdqgEUil5bc8SxkKDfhIcOE
aPM/A5PPKYSwYgmRKaEr6F/e+KYb9WP6663KRjZ2NgME5ocAuu1VFMF10expV2BRQV9Axu/5ibg+
saPIci2i7FYlwyBtcr1ERUZFcLQTI/Be5dkpaC1uSwnrTYhA6YCKtfmNGM1WrpcvjAWiTVD6uEy8
whg3qy+yORphmHFnGlqS9Fw1ZHMKF4GGo3lvFvX6T6qkQKCl9qVJcE3EtUt+5tFZDWNU440qMnIU
pOlnwCefWxuxi8zXG2nRiizuyux2gYScAwphMbpYH53qvOROTbHg4UXjIllcAnFIz1G1sSOExCZ5
c7i8WiTyN79kzZNp6rFSfjW6Vw5wSezNEhsWIci8siRP95AYb17RhbqVOLjqk8wIjGJY8VRTG1z5
qE74JViHMzXhGKNeLPp6YUVBvLw+g3gkP90TBNFYSCKweU+J3+qJnDdoMVLPIEL7LgCG0AbD9uzj
RQCGas0UtYOmvflUnWknb3BuNdoweuOBwktxD7XlXm1xhUsw41TWTmK2zoDR0dJcwFmFaen+1zUG
NUnnU5z3t/kg84JiAhjVt6Ezz9RnMs9/mBVBWK3gLnpB8IesEvPnRqnD07KsYwcWFwyxupf/K6Qo
+MsV8fh1FGwpS2jALKdUFxnRshAtkrmQhjdwOBOsaPwi53kx1hdu1ao/FBdFfOtbbmdDPWLsqnGo
sH8cYemgsI8jR7+6OYdyJlhxcbGsbniY2sMA/WLRXpbJzrD1smQxZ4MM6dCeeGEmKaVVY46q8ZDm
VlITni0LJ4PBlDfW1lQdDYDkgdr4rLI16QUCHQmdKYwIfe8Of/7z0lJbtyyoC7QMikytLYcKsDj4
snugSFH2ky0XX5FopfFD5ubSwVeNpGza1PUQbI5lmodFTqQXvKc09SgOLqBdpmytNpHBJFxbwNc0
YgmtMtXsgf1g/GKQe3rSY2kOZflk2woHXYW1yswiinxzABYRuzUF2JuGUgpkrYC4Sox5yxxVpD/y
SafzMXUbfZXoIMulgEQmUXQ6xyREqfGA2YIvQHtQrQMUyYND4lGVYFrttp/fieEHXA3Sebu8xJ3O
jZMfL/JzihlrsFagGuL1KJvReri9bpi5dq5hANxtI/4a+BYVHaKshkXOUFlurfopFAjfDksjH2MR
uLDY6WghX3pRuSZ7u7B2gvkOTItxWOeT//AdF08uw+Hq9dpOPe7rszv71c3gajxEXz4B9vmt5Rj8
qxgak+Xl7F+xcNMjooXHJgOrrWiUty+fqs+bMFwjKhltiFeFXCn4BWKe7A6qTbkhVf4IMFTo/Ach
D3Bzsbs8NlXPGys3Nbvdx5tFDkwHt2upeBhF0qqb3N9tY353EaH04OGew3147R7w+pS0rfEbaY3s
YAIKM0tfOGz701i0ozTXD5nlyy4McLotnvKHk0VGaVn8I4WlNivBuBGEl/B9BcPzHX+A+uVd8KPV
lRV4AiHZMXM6Ei+7kQVNPC+zPGQjkfSiVo5SEnpvGSBDELpZRqqjFIoVsbCfXtUhTYsN/PlRl4B0
XZXdYOiJxCEW49sYnnGR8/sw60QCuZeqrhaxN4sFrqwsTfeQtsszCs+v9JCMqlPdBv8Sc9ArkD7x
TN/A7FDYe4yfzOUAVEkHzjTZ0esIfAP7TypdFcQWklzZegNxaiGt5ytyx0fhOw9gSaKxZ0xRLBoB
mx/Z/4phKcyZxUihk1cVhJMiEwC/TifmHI/2guqrYRWstWYHAfgavNxSgc7lN1oNgIQCK2h3ASiI
GXUUjKVp6fauNz7n0E+d9ODl5KLHe2HFbfmIf5xxOSrf1Zly2Hw1uRwpc3nvPEIE7+p4ogbUJA3+
RDsV6K3p2ZYrKfM2MNgf2rTof6bHD1BK/6MCbjVmZ8FP/oZCfcLLZq9jLc7xVsmPMMk94zZJ806a
VUQ38uXdr7B4ZkmvsGYCqaDk2An5sWTotAFAqL0VEp3TZQnR+JRAgLwwajuj1SU1e+GN1l+ADDg8
bC3HrCgDv3bYdIryFU0S+MR9axKALnF6J4Bc/eQmps34Qf6Fuvo25vAbcyFYN+PWDPu6xhuGcDdU
7w1O3ypU6O3ogbmOTYbFu9afGY9q2mc9m58GjMAj6GYswjydJP0g9QUqMyzPx5OI4XZdp+OwQIoL
ZN7Pex5s/O9sgsaH2q5JS5kc8K9RAc8N7r2z7hT1N2651eoBtB98yGkIpzmfcmtdaok9Lh98pso6
wHSB01HwOE1WTKvGBh0gDN/4JphtpTDQfsXWlz9iAPfIoSAypB5LMVDgk33P5vXmaC6UtFFJjysp
RPVJJj37FM4Dz0OGVRWxMPrxuleIXUushxd5LSEGBIz8NsTIqxkbpLEJyhEP6Qk4DIoevZF9SWP/
qT4uCtJl0EfkzzqYd2nPu/LXsS2Gh29pBJa2388Gx2PRahzMZQuUE9GThTkFg3U1FGUnSzDSqVLQ
r4v10Yx1Qi4Q1xzMDg4DB9XIvvfw932VCtvmfCvZ9wMGWZMwqcLSKPbmFZyxc6PtXK8ZrIxDrp+P
91BRSjrwtLeTm1UizCQVx47IO7da/acMoexD3mG8ftuF7Y1D1Iv2ZvOOWOQvXG4JSKJoT/wQ72Wo
LL6Uxj2vrhpIn30Kf/cStxwU3732Xv33BTTNKUeGz+nYnLZnePvMPXGniiHU7w2B90IKfNnXfngQ
eT8Jh7XAUfq8kbdgnrxCzjLmGBYNIDBAolJMhIKX5kv0SOK+0CSfATkkT41iWFpbXkgLzUrC+XTZ
vuvERYEFeXthZsJfEKGnQyF2P5ypn99cElf2c29RzBx+/rI0eUtrzpH1hxe7O6gjN/LDg/C/vRqE
viPCNci9iRRZgIGpvtXUdpfV31Mhj8yVj+F87tv55YEReicbYHRXOT+QpT0VrLct6c3gbJ26xnmS
aJaxL3zCX+4bQH76IDeQ8ekrw3rPQ8iJz6s8UowjQgkGAUo9r5RvSfTwCBzKbdaTO1ZzfuGa5rN0
Hhe3zHJEsW29vxuaEK1sYAWxxno8JySDc+wY/VUbwtOfoNIxcY+xPA7SVWylOWzQ318noQODhz74
a/Pg3eUxOGXEDPI40CSkddjWTmBTrbAV5vw+MgFhUTS9jABvBjrunqVf2cPSiC6RVgyFl8+rhB0D
RUYpyC0HGMJQIn1I3i6ZtxXOdtrAv6bP4HmoL8jsE2AKCcQadq5Km4G7ocIt9NaaQ4lE23eNDas1
8CV25GHjxN1D6HQD+GljiVPZoi6DRi3x5Q7nnEDgYPtc9734B0OdZIL77nh8eJnC5J+BO/BpAbu0
ftxtqLUZwvCOuhkO3g6RCmu20YXdVmS3OzunXf9peud6LWNGVqWb8iwOa/mfusYNafMzL5J8USVj
Z0PK4Xjn1nAZi3DupK2RjNSNnzxHdIMH2JRRPrW1207UdWqzrSTAW8Jn75mQ6oCSl3uGSOr7WZbk
4LnDz3d/M9Agg0jqgoGVsEpc7ihqwqDjriwJRkUOWjT3ETYcYEWI2LdfaIL0iOfPWLeHjIpAaJmg
alBD1+sM5sZWYdch0hYzLXC4AN/g/S9+GBvjNbXt+E8XsLc9EjXaPPkbz3vLGEMs7pDfLT5cZ0zy
EFH0jxUWNvVTrTD9uAJLdMV5tVExo+tccshQGSErOtWvmtAHiUuWXqFeZV8r2V6gAUuOj/bhjrQf
LP50YbecXhQSKTbSYK9/HFwkga8daKocZW3dbVr0z+7Ku4vdsNhv0x8QygSDw4Mgw1sY2f4ArQlS
0DlPsVfZmw/bT006Lxm3SPtOFxwW49NjNJOsoGkCGpohIEWNVr+p61ZiYQA7UgcTxMq0RwJ7hKsV
Zt1Ui19mej8m2mNhtlI4w/IqKg37wB65crdyIMdojea567GfFqTVoFt6hKf7dn/bpWIp6kFVJJMg
GALAv5FbyOzult62C1Ri8epqUPaVzLwTKrqcqdIZBt037jxY3H/oz3vny4K7kKhxL/gtZy+vK/z7
xECcBVzHItTV4Jtjk3islsao6FiDJoHrHJr76+uk2XYDVAgHLLYvraWa4tiHrCvo7E7WFoDjTEFI
2VrzYHcQgQp7RIEdgILs1eNHEB6QMctbObAyJ/xxeoyy3Ng9MwV07WStISuYA75YITQuUgzKrhgs
GvSyBzisbs209Z+gdnjI6WjycMuzwy4HR6rmV1jBW//H519dM/hbSNbw7jmnKAN4IHJMAtpS5K1c
9XAYAohcgWswQy7Cksh1x0uxeUGE/sUXsnJ43dSllswfmeT6lUoB7brkCOVBEcRT3xBHHuD+PCzD
wqylqpCO6ON4fW4jCnc7NXY9Jw99EOlbNWO+pxZm0yBpkLDCQRsMezINjnvARML9+flzFIxbFFhp
YtpgntXx6TIdISlRdy5TK9kyeeJM0Kdqy7BgKzYECd3BKFO5X55wb+ZL3+/vE8EbW350JW4g4Bp9
w/sAlqsmKmeztuBZZc+8xr1LsYDV73Cvk/Ovp/c3ANxG4yUjWQagfsNhlFH2Clwf4nUXw2xzZXQ2
iMN1DV4sHksA/f3FhnAlMeZYce24IBvvXM700ThflB3Ff5zLE5DbUD+oURKAGGYCY5QYvEC/gveI
/td6J2UShqZkKhFgCLg7MmWKYURj5VPHrG1j5ceXbLLp+DmmgDMKTJqUMrrxQIpPuz0buxwSRDTq
hTXFx1euYfxOvQZDEGWzi7zup/RaCo9iIluWnzuBqGcbiDWu4QSqVWBjbUoZe2A+jyiZtHWpQy9x
w4LxNBud7pJbXevKVyoo2+lhaSv0GfrQLLxXhDhUeor+Ux9g/zbT6lZkyaKEsqRgcxD7XwEaNON3
kmujLEgFU1PRvfLU/tcp/rLlPPo3kFHJqPyCaIRGXvhS7APNyw3x652V+gMKghnTZnOLOTBSYHSU
bECcJFPIZBZ0MqUFiESRiChAmybi20Kd6vYvc8esh606PPN6wlLJZCU8GvlDMODjYW/H8vPKTIr+
8Q/Pha2GYBY8yMr8F5aMkHlA43pEw6I32FCqbI/QQJ2NZFl8h9hcihSCVLux3wRTZK44B5dNaAaK
GtbcSMGcQdlaFUPvtInBh7xMurPmLE+8jBRCPvzBsNg5mHYFmq94WWs99IJ7BLspCjrZD8etbzYV
tJ3hvS3e96hwJuwdeiGfgge5slxKX+LUAmnOPAhi2ESB0a7aU2ATfsmY74H5meyWxg8TFoB4SNmE
XCNxvqwSy2uXewhk2umDHeyII8tUI/VO6jU8vwXPEvPh7wY5jOlGU5hn+dKjbduNCWcfdb2TOUzG
LjdWCnBvyuvRgTnuMzp1Ndrq1lwiC3w8bqG3/08uxyNn+QGOks4CSd/aPSDqDTuPrc8D5eA+Jo2R
QeXXqKulrciLyWcN+ryiijw/xK4DwgHRGLDMF4q7YP5asdKztRSM7b8WkuAwbBaGhYpkSCpvo9Hl
Ex//EivAe9NkFfnQ8qTT/STPJ62USasyXl3TqLqSpVg5FsIKmIJw2yh8rVY8+XyiiuPXQWSmnVcU
ZNHOSUezR4ipRbDcqNwRh1GnxxtTqjSrnL/ChjFOvnWvoPZt8ooER3ploCE9lQZ0qFOedcQp+lOR
SDEDXoUdNF2wE58h1sEUliCYDNhXruucYOoiZBtjNFuyV+hJmj9STSQzBLVxXCRg4dzWnZgnEPQr
s/oZK44jEcEWf0hklu1XE5QDdjR/RkyW73tjxO/hguo2V0lgM8i6T1nBex+l5kFhFeMmAgGYjX/D
jb4PNMR9LKsG5kSdvX4pimlJ/DBrSOR1qfxYx7npHoKKp8KtGgfBaTYOGu8dghpm7KusnLuTmgbC
pogVm42JEHMxuu3uLTKN28bGkgadJZcUIGaf2o9YSyg9nAGFHA/b6XxVbcHgcTSGbbxILykNoyzX
2M8gxMcp2Kqi+O+WR8hVhslgFS6PzS+iU6wUpf3iW+LLCXVcV4PAAK4Bzrc/M5vUlrK46vZA9zZb
iiUJeQKvqzKSb3CoqH3es1H+KxUT5anpMdhpa2JpnoN1riKv55sKdKJFvCc+RnsGQZ3/+gGU2zC+
VlJstqKVTRZWyoT13W4OFaJ1KQAhicleSSltI8HgaFpDe5SAZKncjaqkA56ARVuwTxgespT2ckEB
eQzvMYKuS8WrQrwxBsnaBx58BR/99anzPVshwb4sMhUHptAcMdJtqRLQ+zh/2saVMP+jV9ocbjSP
LVcB0jGXc10hVrtT4N9NFYKQy+lZCqiATs94WZlE62uGQry5Xa2PSk90i4KEpVKdyTSlYFl1+zxu
1tNadHOC/T5HJt1ok48hfpQgrEoCsi6OccLaFBZGxa2IrJutU37yxcNx22T5IewWENTuPA85Ghf1
BmeGzz7Q6b9UuvBCcs3/LTWvkO0EmiT30j5MJU090NXWOLxHpAVHRKRR+R5WUYVN+zNQSRYsDvn5
5oi+O+WJ22InybZK/wliwgcJYeTTEepPfx3KlL+1o3XWxOxXwIJKleZlsUAfclA9VLi0+vuEvjYH
i2hQV5lu0yz0GpszUIVrqpdGNi9+e6y7cnA7xA+Jj7bRE3lx/hgMzUlo6KdYQaFZnO/y5W3TSubX
bUBMILvJf7a0cqTDm2HmZiTNs8lMI5MEVMvei4Y/zskwtO1SqZLAs3Lgj7OCHNixY49GIppcc/My
iurCKorUPj6AbYhfWPafitvPuqyeDJZP9rnaK0QS1nR94jSXCLjWSHraGBujnYifpKYKkln7el04
S5G+c7L2Flvbi2+GMWEFsm40xemThksdvJt/N60zh3f4IpJd88sE0Oeb0FFi0sXUXQR11kODsQqn
6rOil4BvOBYj3EEurXdUOGGeiRZ+P0FcrS0sPMc5W3mz6uQ7XUewbJPZ4TRrhh3p1nB04AQEFwCR
0BdDcCMQRDE06CRMhwhbgCx2ZuN8Bi3jcWL/MWxNS0L6KyQ20TwgL9ALyLcz5HHuhmuUmBzilEKu
OAsPsQS8CRhhe13BJFJnpsrEQPYMddk1CMORkIaCeljsplpF5s+R5qp9hyEXe9X9e0fRzqsyueZA
C+fuGQzfsCWIFn0bvwOyHRCcLoIKqkm+f8puAcvhY0LSZBzPKMFA80KLGD1DK4wFCVYvHJLXNWzn
j6FZ/PXJHbWKTc0J48JtQcftrQonlUyzvu1w0dTH1+eMsKPixUqgRwzQd/k5QOsugtAj4X9BefRT
yP3UN+4xWp9Egm/vAlpnDbUhg2KNcwrZdhM9S3v2a7rshn+S03GlnZMYPzKuIp6crisrIW83YsQQ
3+S5n5EpWEPXPeij2accV6EYCPs3Xxu5jv+JlUfB/gfoOW7YpUg8V0XOt0auPs3bFU3FsHurorKs
1gENXkhfKXqZkiD0TJRhjyoAaAUYYoI8wtur3KiZYElESQpS3P1hH4rL+uHMAD9YI91Eqb6vz3/6
x8EGEzaGonwwYxysETH6UUHgAlV3E4O8CJdPJ2VcFXUpZUUOEg2DdHODkCvlmulTqsy1KLfX8WE0
zZjq1qeh0dkdf4v2v1gNExBfOa4NQSgGnC5FEcDzUwwZN7DEd6RkBXaUgbTf0o9IWGCR3NKKtNFO
Xv0ecfm88TWcW+t7jT4Ds9d8DVLQsUQ0jz6zjsNjYtgoQpYJILviCGl/bGWMC7EJmrL/1lpHsiIV
RQRX31FI4rCi/3Ia3Aiz5jGYMiJiQFHlzoh7HDun++JXftikU+WZFAMXddeevXssK2d54abXnvyk
P0/eAtEMyPQrx79zxfzL8Zet7QQq/W6na8cHZBI/ABZ05FQsTmoLtxshsY/7klOZEnjI/vG5Cg9W
q9ME93T1jXNQV3+7YgLh9aB8Fju5aB0XTKmyuyVtuhygKaKNpDj55/uxaQSwqPbWIGsv44vEO3tG
XmS3DSnawFB6DLYwg8cYkM+Y9VkiLytpUaCCONYARx19+s3G60f7VRsdFxl+LPi04LN3v4wCjLs3
w6YCUeLQH2DlUfvxC9V6leveGR0lrKDsmIW1DAwOf3YMACdcnbBAA8UyeJhxbmatqZkDLTLfG/P1
dcxfvLrWsxH5eSSK6a5q7AhlQbmWUcJSpNBcMNaq+Q3kanh1FBvLhz1vVShhv4fICGB5iH/AecFZ
L3Pt2XUOwkWmKWQhLcv1PxYLElVN4YwQhaxr9/Sz9Fi1zQRJtGxWyyushUod2i7dnx9P3F2GKL7E
65p7ylGYmsQ3tWXbd6Z3oNLVPwIbFfMX6Y1oOJ8fiWSVIAnrm1LW3x884YLLyZphR/zz9zwrhSCU
BFseIORvsrS0L923v2/jYz716NzG/PrTry1Rz2LAV8iJ6mqET+kQRWOE9RdIkzA6gjl3trCxVPnd
Z1CbIa/G6ncJuQ8BjPCCJNbF13sDxqDejm4J5d8UqvLYExpKDRxZUVg93Lfx3tYigU78Pj6aovjU
j7n4mDQ8ebNrLrssjXGOnN+yw1GS+TYBbuW4H2fRvgAFuIcxVVs97Ehlbf0rjyEbM/HBbiRlv3+e
d4P+Rsp5jiBzPCkJv226wF6r1rg1n4CcSZVhnySMVhD1Ygj8tdyTpnXmC5qfsmmEvRDtGRLrnEJW
Vf+dBrVhCR0finHmrvNMuN+TYifp9XP3Vy0vy9f3vd7J1cfxnd/zqOmzhi3GhBhIfTb/YWJELQO1
we//M2EB0UtfKN1DEA3USHjd81U91OPgxzKI0xTmU5CJv0nevk4x+JAUomDHgNONo28mThgleqp+
EVRe5mD6t7Ql2yk/vfJ7z67R3NYAIcQzzOXMrnAGwBBQu21twQGSIyKTnccZ38grVnDj9//mqnog
1eVFLLRKMwg0I6t/4FGD6Qr6v0ylCxd5MckwXHr83XJ6/0WEdEQCZd9+IeyXKieMFYbYs0LV8AE+
DaN/0SWDgfdb2Q706XlAwfP0g+jskSKc97mqyMU8p3XsXuoVkMLrUoAhrx400ir2dqqiDS7YCKB9
2wQIkkYyJjyn0s+/f5Kv3OJyXwSohh4ZOF6WGglGowag3UkUvleXVcuc3DwrpWJpdedSrEC+j3yT
VgKjVPs+O9dz99Dval5XaM4m2Lld22SBsUDaKS+YrWL66DSLO8DgVUAJJhA5wlluPYX9F/XEGju2
iW7iC4XPiDWFBF/ZLIRZXxi49aBHSMvrwvfClC/9mGRSJmsTA3DdQmXRX90Va0crRXrNbrmxaXA8
OuUYSHT47MKFj6P2UvU1YGkxdAVXt524ARhZLMFN1ishHjU/tY74pgkYFWKSwJfeimWWAHd3+WSI
2FGUFrpbdaDLpGOUP6t+xTYP0for01fRHqhXK3bMWxLcVkPZOFLX6QqlJEXIVHwHecpKO+Yxwjwf
iiW7HzFnmSP1nJFWKw/FcbYX71y2s6tRtX1m50hX5UqXEbtSZQ5gSpMt8Tekds0fJ7dGdG24ZSwB
s66SWa/xU/ZpF/0lOY62+jczdjsrMUPumPjLn5IgnIr940gFpbwxtu52X1QBw7PP1rprFrf8X1Am
PfAaLF4APHU2tZUpN5Tb31Z64LgiGxO0R47yIbW72PMehL4Xk0zhS54Ny0PS/UHpFPeFqIYj/fvt
DNiE9gOxigZmntHovpXnok5hwQWEBv8eYVgigCtdCE3HWozEPVx3nnRXcVcUQxDiq4uzAqILJugn
EykE72lgpq3td3zgqH2heUUUm9Jr3Q8ihN1WMfAkYxnYjXUfcVoarRQCofzzd+0QXr7a2U8F3Jt8
+3fQ1xa4KOWd7HL++MAMtp31WcLOl7ZAuUHLu8hd1qAzsRu7jxYNSkpG1MoH03Tm1pVauwP8fbbS
fUCBo3xiM68t4F3qlR3V3JbzDkVzEvqKkxF90rkfVPSAVvCv2TbAi3o/QrTEzR4hedn8fhyOzwLi
haBriKuRNHrtdp5ZsTApLRDU1FEL1coAaYwP9mErm/s47V5Ava1ubJKBok5VIQxnGsOQ2rWbo/Wq
EZGGLfDb2ZhyYYEOIxKtMLrY1E2UHTgsZPWkLAU8g/i2gzjGi7+cucEBsHZjg3Dkt4wRAkyT2u3D
qM3JUf6fBsSUHp794T9H3lXUyyEzyyUGdzUsygcXFI9VKqNqng6yqeTd6UOKM3mwbKh2NYIjO3kl
jIhSXIdM9ig4KLS1HKzNIXww6LUsswUuiKsXQTMwiPQwHnannRimLftLKvP1OY2W78i9x9UhuPk9
KcX+t2Vp/FKlcu86zV6c0xCsZAZP8+/HZA1PtwfnOdaFboeRFqadm5RVEJ/JkFuG++MDJCroxgzu
rrxq7P0v4IhLu+Ps9cbk2vacKcvEq96DUi5ia3ytj7UI3lZGr8bQFV7AuRet81yvmPEnHpj6SKrN
FIdqyAeXz/7VBMe/lf+afe/yy927Yj20wtf+4ygnVIb7v3qh8xsEZZjK0J+eQONwUEsCKq0CweKh
YnHsLPZhr4qSOlOZjLVcdlSJ2A71xvFNPuL3ZB6GYHGMIrxXBngBnSO33fUeGQsrQwRCNAeQXH0E
nASWE1jAufywy/0kHqN10lNFiIh1DLdNeVSbkq8ZaxfrqB0zUuuTbPZr3B2OZW02jwZU5a0MUMoz
Bd4qs6yhMmz0cVRLNG6oLx/eX/5t8mHnrYeRbsfjzAzyc+yzwTUeryiVjt0JyJOhMKJ1oa1IZ4cP
D5GcurdEnaRBtDvonbZz4Fw2EQ7Ni+P8kIB5y2Npz826RlHSOzDSizmEFlls582Mr6GNfAEt2SbR
Zt7wmhZtu6DdF1/Lx/ore7HBiZMjl1jhWREAhqjLLwD2DxswZ4zOwso+cVkJaJmshIkZyhnoRivO
WavEpbIoj9x0qSWqjiM0zyPPwO51MEugHewZfzRzL3b+XLlKS78E1a7GYZRPW/testwo+FA6In5z
gzE0uf/78OzIXX5froEms9ObRpmMP3UGdAomSlxJKRQZt2BAH0ZjOghQ4YUogNoT5olWsaKf5zGJ
NDlWDtPF+TpCVhN129XtBXZD7+SahrNfHWQhXyELV5uU4tbkvdz9stzqXPhkgJBZL+IXBVPbEP8/
hClfFzD07CsN+kf4h8nlRg4P53AUv8sZCW3s8tQLzQwqQc5dpYCSxaxHJSeU6WCZKOTRJ4zIy3eI
vD3iegjHGls0gbhDoB6TUdeCMKLs+Qkqkf0wx9KbuuR0PHRabR4THLJ/rNSRdza1Q3le83fIZdhQ
+YWYcHnjJZ/xtoor3MpmPgiAo84Rstwp0TYUsOzjVRwGyjUbcD079p2Qyfp1mWspn/+pyu0Iaie/
2K4zqAmBUToqvHVd6NLIPgIg3TMVL3nm512zM6WTaEQQ6G2yr8wXxqyhlY2t0VjnRlUGhQsksp70
TVaPTPPneNdVtUp2IPQau1TKttHgind8mhLG2nQzzNT8hh74RHFxx/KDgUR694tXoac7nXrQ1oM3
6Lt9Nl9bs3Vn8cPp7qU/LvCbMCb8vxQXe/42/8wpvR+Tn12WM63CmmyHzHIbIShOhNbZlWw5zbwi
FT+h+ftE7qPFNzh1Y0zEA1Z18JmwDsqcVIOfI4ww6Vn9wj2ExuzZBkBFZy8xoIS9LcWyMSsxHnQu
WA8hc25AXPc/gBoQwM7OhqWaj3OM//DNpnhoh3pgnmq+n5eKI67uz4UySqEABqi6Ywd0kloqHpFf
ou266enzNpCHsolYHxgaayhL4BPWp5s/qSaHv4edqB+5yF/7/RuMkZ1JL5Qj4NoyMfWdtO7aHnpn
ZFESKtra1nu4E4VH4iFgwm9Q0IL2NeMsHjgWeb8cxU3CvrCgo4yQWBFACuHh+tkFI6v+Imhxfl5w
a9rQlGvVEG59p3g97zORix4UIDZD7nwvoKs7nil7v4eLLyDlMZgvpV4FasL9kxLumuuQFodjFxIE
kCCBxaMq/L2S1Z3B04iTbe2MP7ySwcsWCiW0l5tZZvRdWj2ExJboMELNztnXH1+7Z2C2Lxf3J0MT
h7Prlb+odjA0DNfanzAeGap2GP1rYnw0y3U/R7y3sTNf3JgHA1zGAk4bODFxkHxVchfktgjxzOU4
BgYoVV1QdHYnMmmvjIelnHyildoZQxeFSUzvLQf0I8zHDAig6a2AB2ylG0B/TpkounnmMJjnJbnb
N+vGWDb+DLFEB+hxILam4rYSXPfqqOWQHlrLjbFAMxF+ws9uTDuok2atYgF4gHSWzicYZqeugySF
E7uUT5ngrtcJdlsSs6OCphVh44kdJCGPzmdgQSwYZWloc4P+Cajp2tswmCm2nhXhaPdPNKc5rBQ6
L3aEZHeJ4wLx9QeiW3KghRGXN21bpwGD8uLiNIvBg86HX4ZZRFJ4IIof/hCKdubsgSoPNxJWWvkc
DwkRASeq8hKmIUkL6OOKTw1sM/Ije3n7V+0X2kNB4PTV3HWLXTKxS9TemsGhVo990rZsa/lvoYnP
Jg14CFPJL986FAdI0Jm5S768QsoyohxBaNn3YjNWUi8TXDpK+Ge8DtYNJvjqtd7eVVJlVNJmn8xv
qw0rGDdVZKzeSTGEpwGpYEL7myOD04iJJFh6jg5FhHia7hhFY0k1k3vyhZl/sX57HW3mFc+/CEwS
zTsbgrDj8OoeP3647DaO2GeA54GLGcSQwbeX7pAtUoQahiTGPZPh1uCHbA3+1gAvG/qsVRTYeSyC
7GuCYnpYrQP9naDNRqEXfI1vhz4uaB1Cc93iG32NcF7ymRmnRP04kSlfwgpozepalQgbD1Vf4hjy
Bdq1W6MSxb/VXaQ3+GkzuyZge+XWnKXy+LwV8KrSohGaOR92srXO9HLl0CuTlcEEfnp335ai2b9Z
1TFZgGPmsZ/J51855mswXSMVJwvWV+0UWYxYUoMcuiqrP4CiPMomnfGhOHkctrvWdVBa3E7mmmZy
hLpnk3s1nr7KhN5ilVXHWzupfduX9ReSAqMRK04lCh6c1Cat+G0SYVtXwPV+aySU3OptDB2KkrrW
vxCjFg7sFBtwvBBIec0pnVq+gf7BXhZABlcnr/VrYRQ7e+3DobUlFN3AcoUo25WVarADFLOttEFT
HSEuWkwzktDPurzkGjkKm+wjufM3TOC9hnK1AIimuxQWs0GAMhV59ud9aPLSOnXioOHObgreVxxI
CEzUahTERN6MQo8vRbvX7QNyH8pyUZbcyZ9jSpfVdwvDNJR2YBQx2chmjMVdl90k4uitXiQDoaEO
KCu1HYrrhy2WszQlDCK9RB9VSI3H/dIjo7OfJ/hYuNoBi81S+ZFakQn681kvxVFxZ7sUhhGymXOt
elyg2filfg7zBxebyw4sXFxHy5XAZ5W7saGRrS0s1phbasXwN+rNiJahVs8wuKTzRW86nWixswUc
MvVRToN4dwFdIr9E0MhSNnWtAC/DI9sEHJj2sXLzedg6WiFKIk8/xHrQUxAoOZ/6Tx3ttjcXCC4t
5UKqcTGXK+yru6xFROUTNm/5+cUW63aHPXicg+Y3B+cEFrTbMgd8s/BfsZjeYeXm0eiGtfNlPRxF
8QTtP6EHqtCHrajPxOrMfU+lWtyDGqnp1mLtOXl8bxYLlHrSyUswYBrRwyDfCuuMCY/1Tsesi4rh
SU+vVXKw0u7gOJT7fGCSNT3WnFEPLNDVApKjGHgXuhphXGycn16Oeh+SRwBses6gKxGRmowPtFBT
KcYWwTCPDBApfldG4Q++lVDfB77LJF4gWRRr8k7adACRvVAwBLN8/TNUbgcBreF4b2mdlN1oPeew
TsJlWLPIeiNXluTrQHo16iKw1w5/2tv/9AFmYATVbFiUMfCxPj9vABMKm1wr3u1BGkMJ1fenSL9e
MMV+ko0pMNYZvvMi8FewvMai/miVTd2YD2Y8kyJwZKQ6iIfGQmLtE5G+tchcTvHFdGwOFReXuq/1
yte865N3Q9cBQbhGFIpYp+Sdfqe58fvvw6TMdL1kkOBbRS43+SrFDXpADekgBUROVrA/Qx+mU29x
x60EVipSn+cuZO99cbEt4/L5MmTdLUrf4M0olmZj2U2pNzQG+9H4PF7sja+SzJ+swXL0uyuiy/9Z
kMRxg+YZGEuPLOl+ROGxjE55xuGcbrZ1YvJ1Oc85y4cEKg/WTrEb7yiKOxD2HoqhtEmkXRIBlKIL
sbA8if1jmR+sUvvPFcM+S7aJa3MspkU93/ptkS7o5rIPZHwuBrg4sxpMo6uJqOrmJM6vSVmr2cqT
kajwU1PiDflQUifPMw4AdBxBjO1V9/pih0azoAsJlZMNzBVb4iSvXgRXKjvbEG7Z4xEB4NoF9X1C
xzBarZvPFu5XCdRj7kea4oBW2j21jxHvPe8Xl/3XnYUnMPzH+/UKCh1RjK4IqcrhJOutgF9JWRbt
I8b4ulZhI3lDXrXI+tt+gDhct1oGaFdqDmqR2rpPVPBGkjahAHAnwktENeIYTFpcjGPUWoayByFo
jaVr0IuLEsPQ0V3yxDLA+gQoNrZSrL8a9sMpb8wU2cqj6PoiC0VmVY1SFrXy8hiifxwPcBfqe9QA
T7iRWh3lJLXE0/k8uWTHLj3AsZ1USH7YvkJpryUzKTDIbICcLrzrtpOWNIL19p2YbQMIdXBCubqv
OLV3d8BG/2NecZc8Vpy//FmibXuG/ADE7vR8COSXIc7IJlWXkj+n2Ygl5n8kD0pMAFk14+Kmhz5v
isxVhgF39sngVMgkBZhm97ltiFP435HX1QjKmIAuHsk/hbcql4ekzULdi8m13IguWrZCeesAo85o
88wJBGYj3uYoWBOMeT3SuWV2i1SlAgTYA7hUhCyGfxtmFdywyCJEB5C6rhkHPzneIiKxRpXqAH1b
Fcm0zVMgIsXvEzTwlSwicUvCCtu3uTmnHg9//sayHcd+4ymOfy7/7u90h6bGH9Ea7qjHZQoZHp8h
PeKMo4fk6bNrGWF32zwAtk/qNQgjk0VFVWkzDvTKRz1J/Ivrjnxb8L9Mf0Ae4wiqIt0Lj9Js0vgT
g2hdmF5g44rkS0bnONiQtPkUucP8Jz7/D5yqwT++Jm7gKzSenVTR3bTVFCpXyqD1OWvsy4Ks3aCX
ajNn0uORG8KN/ocj2lo2E2ZMvD+z+XYk+qD1PYdE5Bt2wny3txO0IHdKoaG7vkpU3rKRYl7Pg4Lj
xwG2qzsQ2FDYB1QI38/spVDr5Jxf6Ck+BIsNpYFe1t4vrkSAeazRBKL7OJD2KW8EveLZKZ6uCD8D
XMyEyFLkRcAc6pWRJp+w//bh/pgfSeM3FJ9jZ9jHEzqDj6p7q+XxrsX2rcwwuhKV3g1Bg8jv5bBH
gTC70cW3eWVGk+NAOvQirX8i7l8TlrF/fnggucsiLJlTQ6Gn9sBvmbuMO8Gctfv9hy8Zqz3DQkth
db3NgPOIr9hB6SFDgkqGcXStZsOBRugOblJjN/OgTFiFulm83qrBzF5hIEmtmM5bZ5wTSu/PjSoC
xXeHzF6Cns34EZkD3e0gAqKDqGco3UkezQQVzAgfqFK1vZdGtRWqCNP5ryxabUk5RWaiPsre7k68
cDzQPU+gUCPLgmnFkOWdGWVasOeXFxH6imZw6MXNuy3xXaZlPLITrT1O86CtJ8U+fJQi5KxQgaj+
vJLoqwc3768qFZAeO772+bIZP7Arby53Gp7f0OELCwry5m4+YNAv5uQ9T6ILYEkPfV/CAn5XWL0j
A8CxXFQTX34l0gR3MRlo3E2Bv2I86Vs2H92RSMSC19xiflENzT732amo3aRf/MqltAM8MNPrdGlq
F/ZMOqv6K1Qejplc5ROmrq+bP/q46S7W2SSBoFwc9fZtzbbm1Nztf25fnQUIO5xSKZrJhW6KiJL0
RcyvzHR32JIMI9ROnCnv3r+4pZkqfTmsB5aq16KNLO5e38kQwcaegJ5903jNHfnuTcvQ4Y0r5hcI
n3358XND+27DiSKGCZ0ZX+Wc/MSt3+LqZmLGo24qPNrxuWzuVxz4wrL0D8jRPp4EvJuof+TCaSvb
79WaodWFxZqnPS3Czlppp+kYF+0AbRRDTJplNZW9hMV3KuC3JhOdpTfkfDSH3HE3OGzjXGHd7BiT
Rp07OyerJB0SYFfilv8f9SaBBf46iDi0WkYuH+0z0Q6UfFKtJt7p6slh7N8i8I/lha58y1Y9vQtb
2e+QJlcT053hVHVRSwbFVrPh+j4JbFORyVSIdDR2QlonVZM7fP8QmQ94H265iMBX6WgiYksEzCkS
jAUPsTtFim5j+shjtB5Nk6hX9eB49gOpCLae5E+Xq4BIDfNKbtOj4zsZuoRkKBf+oDLSYO1yO1pA
xcM3QXVDbBgkp6P8pqgZz6V4MuCMWgiCVQK+UWdQpoWvgSHkK4qG9MTD9+E2RnsGKm6puJpAf8aA
oqE+HKZpWPCFBWK+pvLsXLPUYWz9Tdwl8sMq88/jPMNqfQ6SADiaoct5gnMDWmJwVLPPY5DU01J3
8gEVN/6y4ytCB4nHs/yT7smRVVLS78gYzS0U2KsobMNmTBYECruqhcOAko1YxHo2fW+vjUuiFm0R
h6mjiBt7KqzAawx+lW5M9l6uay1lN7EUFTeFXdoSV5VAaE0gcZpuk7MyKh+lRzranjOsoJiJ1bL8
qLz5O9d3ricfqOULsz3wEdIAk6H33nxSzPhK3s8XuU+xu8WYxT6stTK5wLinGr2YIFX7djvZhvjX
yMEAdxUAQz8eaToGg2ks6SXwScV9cMn1MhsM4mcU5aSJxTNr4Sr9Z+yJgn90ELAbmxsKqsv3bgXt
txzClW2xQIYCtVesHfUZzZIRJDBS1WnxGy/N2KGKjC5u1oE1F6BRuPzvu+atSUWMqKVTtNQKjP2U
EKARUxS8tLwnHY7leIhSrqUYJ4xDp9h3FTBo8twPpIlPvJ05E/TLYSY7cdJ1sm27j1CNG3KoSzVT
F5DuK7EYUMOHSkdpnhkdX9vsFu2XzS076dBv7c/DNJnjxpH9pUtgAxSmTP/nxovPhuvgI5dOJ7zq
Y8x75vSxDvX0cJLiQBKShIF7cNRb37vMYykBpLfvY2Ye2cqMuTP1XW3onZctJQf7ju3J8I4rfd61
fxMSvkazdEh06zJl+P7VAqEed1R8/v9TQ+ojUryIgIKcw43xcHusfiNRuekUzj8o44YcaV+gUxoV
55bCaGgzOCH2LiK0AQCPHBIjYgH8M+6c3bFYrnp8QK2EzrPvikHiHBJtnWVU4uklD5ORAY5uWhIs
6mo/vl+YIm6cB7+Vcxq+ZNWgRxuXSk78cHz939iJQqhNmIKkOAQjNleMZcXcXSqN7JTUposLmG9Z
lQq/g2Kr635wd81Bhwr6AxiU2etnw3wFwagEODCRej7vVzsTDS63U1/BO2Pj0Z1zzy5GBB14k/U9
GbIFezPMEH4u7utN1hZvPZc4OBUe/QellP4xfi7xYcVr37yWhw3x/o7XRDa6Q544x/8f0dFDujvs
bbtxjWFNxdlmpsU8Hfr2pqlENO0Ub1wwNmRDT737E4EXeQjll3+tyxauAGd/xprJA4QKbWvLTtwr
dBLbjt0+Dz4/D4JiFfeS0sasCFixggKwFs0t+Kt+vA4/uObyK3L7/FIK8v8LQ04pdiL22vjbRq6v
8ld/q5qmO8KCy/MVTt5I4LKlS8gGStgHQmUwnyvA+9dyGLXHw6BgPavm5YyDeiDJ8M4FiDOKv5lN
bCYFX/OGTww+zj6W2s2xuHfu87at/NeDUh30ukhpVqqnj9sYvW7d61On+9nPv2ndXSkFFVZ0/aDi
SAdB7n75KBBYuhyzdFkeAzOYvBThNp3Ah8NmLv+0XMwH3rb3EpKTido06pWaayyRxaeACHWFALs1
y76rv/AHB5Fz/wMdRLiZmYJ11aFdE8yHYoxB20ieyql59gXgVthHD9LaNSSnLIj0vDZ2veory1A4
LL9x0KMmHfmOjGyCTJS3wqdW01uwNw09V2+0VBFruKCVPET149iSPccdjwSioZiWOMgEa4UNo7sf
P3RGxVUzzE/IJOadtkM8sKUl/ZXbsUuXf+CoejPWkGOYUJyNckA+2MwXfZJH6HlvxoBTnnHuZ1Lu
5G4hAWzWeluSa1Fgg8hpKZhBh9zUQ4bRWf1NnKIFGTzlrwThiI5LaLAtxNt3FksYjw0W+93dy5Fr
xJ/bd0OpWeQBdl6/WmXeSjZhUxTYhxHBOWaSF3LOjfRfHNRbb7fR7/hE833D7wZn4XZoNlVlYUyQ
vAY1K+zRL6TnZrax/Ol9raGGozPCFd/CoxqSavGxsunL4T8lHV+9e8bO5jYMfRR9MeKYsiKFS35e
K+C4HygMtyg4C55FVx6qE0qsEgVs4NXASsBtd3lsgNdqu7YshVHjPNEswFdor3RKmzFLojdBG+yN
DHF0Gi1owYd2XNMbppmChnkKL8gea5ErKAxy6LnCQLPhO7gcSo8YRuSzlPbospWpYbcvK7/jBpon
VHhSeEpwieUUrDgL7vW/3XSEG5t9rvg+wyCuT8uX/iI9Jg0jqLeYNMtTnMWXlB6nkHgGmsLh4e+n
3Nj5bM2B36vlkpE54lr0jLJfMz1cIUHgxppX0vWOVTZT73CNLccX1q75iu+ZeRQHt02MZHEl4icd
lhJ5UgpHUo8TShm1sRMJkZ3dC//tJq7U/8GVLYnae3WwollaX5rHUI6E04bMOIjWwSm/qrWygWVH
A2IPjOD4MNfmSYeIey0MQ4+FbXtMXKo67YyJRDiZA8DuE1jSDuFXztYGe2CApDdK/rZI9PhWHNX0
6TgZeXIN4ycO7LQI1C/rGi+JGpG1zOBwMi5pB/JJAqxR2+i2LOtUhHswUwcXTRx7+9yudYZ86136
2cAUOSH6nL/wCcAZmMsAJLt1D62DvKEvkV/f5VEELO7bl+hlmcqae19wYXRzS087lTtbtJREF7kX
JC0CR61nRo9xaktnPLrEat6xm4CE5dC/gniIfvpzZKAtetaSlG44U8tvpufZDafHvI+SuQmWDpey
IflD9dxpq1/DKOPUT1dlZKLEUX2US7JZNk1YQiVLjM3fQ94ZgvC79Vv1oluEVkKjcIAUA5Z6Rnav
OHZl4TcaqlcoBawuimrfFSwqE8Jmd1Uf536MlqXPgbBIoWsAomP1lxF5nYmTa0+AIPqBfw632ekb
Xmnw7LeuwsYGQ+wd8WBZIHFPA9P1qqa7IAZZnfXnuKYXoNorRHB4V8Wr+4ltEjUckqKmrd+iELuX
FUvt4L1XnHhyfbeIUej22ySI9avY+AsXPzhqagvQDcMkTR4o8Umc0A8xcXkx17OLreq1pG3t1rWd
rjbfu4iuSi/ZF+Wtl4nyuJcUCAGchwErl+XpF2g/9gu9WNgNLhHn6iFwACeRarusV1OM2hs0Hoog
S/V9z8Qvt/YM5aPv4frcfEYNA9XoIoGsOcP1ORgg3bfqouaPLsoEnV7NtODZiwhhLKXFpNW0e1FZ
31JBujYMq6t2Syyv3smDZ7YgO3z2hm5+9rCtaXBUdH6P/rhlQcoqbZQknh7XXbehcHQc9LVmwQDj
iGzvcVONG2qU+pxjwqYYvHdNVOM27WnfgWmmoXttuRaraVYpEaJGI5iketUAkOISnKLXv0WOfUwE
e7CBuNWjsfofC3oFCVLSBhXONq8lhuSVBrDFu++2d7pNWj2F00XnFrwO4zKP4EkB5rNkW5SV7vO3
FMY1M/niS56CFcmWbGovObn1xEXAJ0gVnld4HOhvOz2mKZpe6z3z9eUwaUYFVzZEWCWc6CWmKiMr
aLrqa0cbYt7Kn+iZvO8O9zM9h1YF+kzw0hTSWbTxEJ+Cqq4aW93Xe34I6ai2fhqAGVonWiDtm2WR
ExR0+uK14HrcAGRW62qfwiHkRavFW5B0I9RYsGk9R6vI2gthtJy7DF0r0f8YQbeORMIIGmDfz0gk
C/h9lvKLLfNgFnw4PhFma8mrAxyjK27wJ/HoBmwN7kYM5JRNHeaxeGEO7lDxzCWlGmlAom8hEXBk
nzg1/3wv/W4ThIMxoXHpITJ7grzsH/CoEhYZ8RXSLSEZxVx8Rb8EK3D7bXtRq4S7IgeKkL8vTgTk
pmJeeaIjiFqXoDLzl62XMcD9P9HW8XHkca9riHkHPjonTMqb/G5B3mPoXuF0+jpzegwvRo1sJUxe
NPJ28zLo1k+8CxYVhL/WauQ3iBWVCSFmnxi1T1O1K0aZ50sSGm7yLDUlO366BUKNfeJBGB4ab/WV
QtIcJVLnPIYwjppFTwMX26K1DuahKonKj0dqFO9WNS8TmZHeOaILTqYRe33Tag4pkGVZuAlt0cc2
PpvfkNT1YZ+jTd4Ye7l27BuO5Y9QmFaBufFKmZ+LE5A4z0iDvNNJEakYKyxiqFmXdW99eY9ZXnjS
kEiSEOJ1uFC1URFnvdQOcIKH65a6uefELW0FLMsH92/HI/Vo0QBTVwDrilKlwNcz6DwHBxH92uNd
d+LBS7F37kP4QUPKXprAIhtcONcN5Ls42++lbzQGQrIpd8iY+G9YANE65lfYxETCmO53XOD77iw7
iXZJN3ufOdXR5VDfa78+mEtaa6O3i6OYRGy2zWhCHdY5rag/Nmik7QQI0uRaXr+g4PMMXrMD/2aK
N/EP9g7zkzTvasHkgubTvuA7maiZp7KhqKEd1MXwnW2vLwfm3FPpye+w8jdZtC/eUBLwydhp3Zv4
O+WNOtaFZ79YIE+FvfiKvZDl6v2+J+rQO3LAac/cmLpN2niogm8Khfq8seTuDL4ozTosAqUaUqga
RYElEfYTKvnFeYhuNbcXu0RbO/itmEAj6lolYQv+XPgMCweL9kE2aFrxSuWyMwSeYfcmSeK6nBmc
pRB/ZFpwiluNA5axZRuxNE96Mh7UJalSaU+fuuLrDqKrSXCyuSapqM3z5Lg1GS+BDSEYewjc/kH6
lGnlFr5X3GrRjbqYSswXQUZsVEuLye3s1wGjiEcaBBK/wZ9QegqTAESIR0dCIAnCdGzZXdkg0FwY
T4V0GQZ+xCj5LhRyGFxFhiEOm0uj0vQqJ0QvEyZBBOUP6N3qEoaA/j+15oPWZ8HOLJ+cIEcmTdlL
D+WOQApQCq5XqJ0uQ2sV/zc/NCbLs380fpG0KaMYVyjUQK2uu5L12Thc0433m5KXBLJL2oFLspan
f0e6O3Vkn9gw/jFSo25XXmwU8qjhXggbY/9PYJ/NWLegYDK+VKVpubEBULvDjQqMtnLr4RyH7DOO
7Z6HuduXeouLepngvLpyB5EwHsLDZNMLMdHYTUjh/+/Lw1Q2pwYPwRavNyTE2SyKYorM9WHLt+h+
yiH7fe2z7Lm9SNMzvcBcD2B2IFAWvl8Ei2KVE1qEGyvAGJ5VrVngjKY49peixvQ//ZM92kjoTDhm
kruVcEyZTqR/Z/SAP6hgKZy8UQPfgy781SF9/HnRl13MdXo6v0pzT4vz4VBCGqPw28AcwZzBAVKU
FSNLBpFiRlb2L86GsdF3C3GFDZ4W+Z2H74oRVopnRFPit4ZjgIO97fK8kU7xay/FKguAqIzDn3Lb
z4/srYg0U0mphyQGNi6gKU+qmNJaJWc9gEGGRcpnvqy0/KfAjMD5lRQqME/cnMjds29RuZfTF6IV
8YsqDAIk5IM/Xm2anS0qvJShrrNvxUqFyiiOB8LF1qqB46L4p/E/DjzX74rbKcr/5gi8S8FuQXvm
jGK+X0pj4b9NBBBKKlaEkK0zROkenizLne4WarSnWsLb1533Dr9yzvUiA55M2FNgBJbGaMvqLWvL
I5IYUrhSVy2BJNMbXCArKdWMRXtqc2c/XEIw4UV2UPUpmqQyVYjnMkL1RLE1EF5grDpeS0Y4OsmF
P7PklQBb4IsDwnIW0minG7TngyaAsGF2JPakvFxXVSo8fUCn9bpCq6IFvumAkq3mg4uEAYbY+usO
YtNQYHWcrz7bwekSeROZILGzSOBRBbeti52TVwV1bDJekpu7iJ6jwTveiRW3KtobbACc1tlW/kfU
3eaoLm/VmC2qoh1EFoiFR2TWI4Q9FENmFmP/15RLh56oauBEAjJGCFs1EV0eSLEKKVkjev58MOmn
wwbustFOVqI99qCVT1P/8bPSXDzIse+GGkxOTZZobTxlkpG6M5jJuswkluPj9lj498G9qU45f21d
IbHNHj8I3/H+hAwN3tNq9T9NvlAVA5CkXmvzOrmwP6xSxtbo5IGdNccyl4RBGktsr1V+5bnYYg0c
XKoTBa8rmhUyENg0hgVZfSK1/jQkLx3aOpk5bxSyxnAp+M0B8n39+zOt+aCwM9uTiqWZv4Ps0Qik
enWcumrPqbDAOx1qqRFw3M8yzstrnqWSOH/xagni6aCFAPnQloIevCEtbGAt1wq+FHz3bjB2yQXR
9YoTM0ZjvUxXXmZuZzxjKqeBoYSW24IL/2r8iBSAGYtD8/DBCQU+/r27RRa/ht27+zHM7xQMb7zb
c2g7lolMMGyel3o8Kk11ufK1P97tQzlfFDldKMXlCMGhsaC2uHxPAx3/o72TStcWpAoqC1s0LVl1
IiuBtfEHSrjTaUVnruFDFXEgU2PFkRys29onr2KuNWwc+w3o/68pMQaU+UD+R1D+LT1BhWOzowTg
goVQbfdQpFaouKEKT5EyW2NvSYsUqvTJRX0SkqX8EAPQHmQ4RQGIEBTzeiPz9fUg7+YIScQCc0pK
u/8nB7ogP4sTRK1qb9mv+fi8Nc4Le3Mv8mY/pH+AaOu5+Wz068jhAxBF4GGf+EJnpfMsBFb7srLM
R1FSQzFKAM70Hwshah9l6RK5YQ4ySCjoEAwoNMZB53/N+C0srk9QhU7FXR0pak01Q+UBULIE80CR
Igih3TT0Cigi65IgPrbE5J9IimeC5LjoNkPzjsxVET4CYTe9sOmnn5BYvYadmFbMO5s2qQlBVkla
4DNp0HINncwMW/QxPpoVnyl1XeV8foMh2HTQUDaVt/szLAndTLERQ6t9qaUtpRanFsbcZrugRjNv
cZ//uV50582/nvmcTK0dYHIdVKWccwerrSVKqVYL6FygB6RGtFG+JNiGxxKK32TUcPXOiODDpRVR
PCTgUWFGJcaKiukMhLNcyyvcI6U1AX/kwfLhBLN+vu0/KkqkzxX1KJv/TDEW4ftCDvmsABb6jgn+
2Z6vmVy5ZBGS1bWDjyvjIgJXcr+plBG3E3kHhiUaPhLKMKZ7RLZpv/Ece612UaSuxif77r3xkh0A
KeJznfPbChD6RGU/kL3NTg5nSMykjdPTS/qfzWX91+5x6nBZ9XMca0kCTwmdhEryRoCRKeRT3MoV
RQKvAs+cO0k084Nzf80FYFZa6KKYapcuCqdb0ktNSByu85tYd75YPMYir/z2Va9ZKZhhFY4w5fWO
la+fz+42/vrvzkc3vYar+VGZKlQWESc9BfgBSfL4Bh/B1UWHncs1iVoXEEu4ps/+IAdC5+7qMNLX
E87S8TunWr/788dtA5Gf1hhVxLRcuhw5fL+YtMkGBmbdjfjlgZ85cANIy7Z6hzLU42gtwtt/vSB4
rda6B7EXuVZrelHkDcSsGmXi0TP5AK0AfTCm8j20H8qwdhe5gg4kXlqaeVylWQOv7mmRkDpu4HSp
YLMDxc28lE8GaJifi0noQO/YVvvIpOQ8FzrTMRmiWfFbw0EdF0ckKlx6SyqrShv32XZ7BRv7950c
2s9izfO9eUdcKOnUD2BzYGozgi5q/BMepPERQnb13eQ/7ZsKhkjVAcTcw09QWMqps1UevyaOW37Q
rlu3e6+4DDJvqdZjDHp+mbwnWdbOPdZSnBvPE6apMAKzgVXd4D1BlGUN68g5RIWcbr5p92E3TfMx
wdiW5HuoDGSt/Jk/ic4/QuHrxjA8CJEvg8o+0bq3IKBQrqPJC1AipQhiDITxc3em3hr1O+lkHK7V
0PkTcadoWa9t4dNjoJavwzRd9QxJ49kIaQvzuaK46V5Tvc0HQmBxoUQxTAqSykR80eMzE+OddpAH
wtn0qxdAugseUNq3KaZ3t7DVoP9s6VLngU3cqE7aRIgOWkRuHxEizvCVyc4DlEkUimbPXcehz2wV
ngNzuEc3pop+PF7X3pIw++LyHjo/bzJLeZYFYFS8jurrmMCBwLH+c+7J5yJPK4JjanZ8GQGzNBzo
dcMJmaOIastM1jD7uTfE6MRYzplUh/yMiDVUdfQB2zgpbgF5PuIpRiUxJ8smBzG1XU7kkYncyDX4
8uVpWlhqlCt30IdxHM8T5Uaz5hzY+3JKiZXhs0HWgQTU3ovJiwhGu+fJU0fAy2WI6kX3VXy9BIUa
Ab3dbqZphsj8N455E8RMKY6vEanvaimzB7P5KKQwlOfPnolHeSiZRrJrYPibEhNDSlUml+V1lpx8
ecATEKFejxMkumzIBjE7Q6IY0vjf/VhZKLyGkcBkrHc++E/Em9UIyGesSO5PpccEm3BOzFEAtXwO
2lB2OCpc9ajhebNULv8uUM5LfL/jtolxwXzMhMiv+AqfxF2q8lRsf1gWnJspLJYoIlOhhqQ0Ucl8
LV90KHKiU4VaQeUZRtDzAWcqMFtb8nP92nhRpMUdXH9qoG5mO1r1DJWbuqsagDarMt/j+IsTBBbS
zqDojrSu1Qk3NK68hnLl6SULrLkpTAOVjOkAkMZvvLgUu7GKxg0o1nh3+K/F027xyHUyR60xPCDD
mH9OSPCyXxvpvJfv6NSNx+zEuocdEWCq++P3KAwS3jsWuOzmO+qPKumpNYOpGEVD136rQcg5W06w
kipClS4Qsjjg/foORfgHi5fWZ1WM59j1doFt/eMoa99ec5P8RGfx10r8J7n78j2VKXcnta5TM52m
7XZlUwA/Y06QUo5cwsvII3oF+rzc9B9XOb40pGwRjkP3J9bwbNXjHvdaFsYYP/3rUD1uOCKGsIgs
hxFP5UALR2miW3qQmJzignCeh00vSnA2foSogH1bVt+dUIavJbjAEnkB75ifCKEnWITCoSl6j2rm
Oe+DRHUKT0VALs5Lwc3CPNX9m1W0oM232eKBvTi7mUiS2PK3C2NDFLW/Rho+ibJY7Z9tbHwpwcVW
deApaS7ah5T2UkY/k0ToNZBU/dL52kalaTY4sRRE3Rw2vJk42jhLGqmaBht3FWg5qBCThSFIIXCI
zMa3ekXyyApFp0WRqaCFg4SWrcm5ijS0Gk9GJvFg51muQ6Cm7i7wLLpkN8bFktZQSL8PNm4P8yrX
X3xBGvCYlSWRr5Bt3xwiAfCduAXyX2ppACGArN20d1s4gwRZRmcuTR9g2D9jz4nJFAbTs4M85T4A
qcDeD5XXuBNOnc68xipXVDtw4ENwBWKl96U6OhsjJ1F4xrl7Q4HhatIRrwzjP1Azxg6v68J5lA7s
eDCkgO/rAoqpjoOdg/liAQK97nCLK1TC0guAQ9TnVSowG0GjT2nVzIgYvYmMUPR131DpIm7i5hQx
21WM2DSyoqq9k8i46KorWaXp4uAO1PcslwYZwOZmCHX9dvKDTb3NsdllrffpoP7heScv2lZa0uVK
F4IQ6jyiho6bz4JiDQOTrE++C5HDHHHkDX3YX03xwnomBM/D7Y9Yeaepj8Xqc1dIFjmTBk49ynBt
BuzNsHkkxbBWF+mBcEgNN7WYfllgC5KtMP3aHidKBd6P8xHNAD8q92nrjQ/vcoJksMea3OfCKPFJ
mPa/kXF80NFMlKBW8TyiCE0UUWfOALxGcrV2e6DtLMqMCL/7PdOAtPZl6txx52hiZEMsqvZnelKc
VrsXpNdj4nXBa5+YuHVqZTuuvMX2cJ14egjwUe06UAoxby6xcrFLWD9uPIg405Ws2ykV7BurbUuK
Yd/lxfRcJPrrO0mQrosyUtXf4zPY1bU3KnoQmj5nXCfyp2lehBbFJnsDoVPGiNhXVZrG7ZlrIa0r
jEZdssFV+qROU+qAaDRbawqXlJcKmiVFpCsANFXqXmqAXRt21cXwxKZziwx+F+kWz2T1+u7RmEZW
L9Lx1NRD1G9AhrK/L3320v6lAkd8qRHNEnjVBzg9LM2qhzmYbrG1o/MQkv00/1UdyOpfsSlvyaft
gdvRZBorGHe84bPSNBMr4maPtj28YRIZvy7RZfy7JcGMMYc6k8Kwp73ViAal5hc8lbPG+9MEI7Ck
YfnyS1hZU8mIC4dX0nMC+tjowI+osD/mA+0rBsrZ04erdDA7si9F2u0yZZ2fXp3sZBHMfc+z6jOa
Gzl3IUHBmcSUDSScxmIZ/6v9mgB5WKVbjifEJ0e517niDmwcHHzGlnd4s7meVtzZfiNqsmeGqmy/
tZmcHA/T/bOrzwTkylh/lOKd/3W66WDx1P9KCZJAEOjZP4KxwgsWjPQw0q20oKrtzITVkOxB/i4c
20J1NR/PtQ3vnp6lyRogRGp1AItqgdgvJetlfWoXT+owUaTxuw8x/RcRAhDPayDpxXU2rLHf8bSn
BYmRdlHO7OH3ErUE4Wx3XzbJAuHBLRTIGjkoRsLl2nBwOz0KfpIN4XFrr7TvlNj9No9icFRLUQTB
6fbYDgwpzVE/f8IDfdVWBJpgAbUQ4Uq3WJCm0mV7BLLIGymtNKVFg0PHxyHgS0EUTBeDR7LdyD+C
qPZRcEWoWNkThvdLfvjwyT82/e89oIuU7V7QELPTqYsTdggMaaKGTxRm1gPx7vLoQdlZnrpdcTQX
ZCURv6IJAstHVKeg3yIZ1wpkzikV9zlB6iUa7nC8LyjzPeCUo82Bg+Kd+vQQuWjJZB48EauxslgI
t0lemz/NXQ8scfp/7n/pb0ygnr4Zs5+R63WUBzPE0EdRGx2uhkcCBxUK67DQIrEu+nx2lV1GveMR
TwZ2i036lOP2ckFYs0/scQg4f0QkFRDVNMh2j1moxkYuGrXA0pddrAHYCasK3hoDjLp3ey1MWGG9
PEYbuY1QDTtwjyUMrFddcom2act+tljd4P2ixxuYSPHgH0RdXiBIoGsVkPIpvvf4Iqz8yy8T9Tct
pmMLXNlnYGP1PB/If6RjJimz7NS9w5gAXPglZE2JPCtY7cvrMBQrY2imqqb+vQSu8RPQt/oDR+ps
dQ5yrvE0zVe8a3FeY0JA55tt0xUZEzHBoHk7Z+Dv53Zp6edZkW7efiYTI+8LQ7YmOXFEnObUWcDa
BMf6iZVYqGwoEGL4WnngbgPLQHdX49LkPwdy1Qg9cMymhNT47VWiB4TvIGT20EjVmoVJvU6wQZT6
/cgf2KDWJ84gqtlcD7dwpWZM5NIGcpKkgj9MmuBGIoK4PXondLP/N3jcppiwk7sIwrxGBBpcnl7M
jCQZz5h91JfV4da5KkVJ7hh6NeiLQE4OYDSGpQQ7JV14jqjYN+tV53q3vJLWSpZa0daYalbzdI7k
ubWDBiHvvj9MlVcK+vBP/uFZHGn4rNLiQt/JcGF6WQvtuXo2iwa14xbdb92lKZVjXQwlUX0oe9c7
gK6DmM3O05meu+dhYxV4EP4Qqme741PLMHK4b9qPwX4OfOxU5u4J2mrQN6efVBL5r/64ZFQTvm0T
SquMZPYaBJUy4oy62al7Qfl1d1c2RJJ8HefjWTpnCxmnYtnTdtZgv0KoizTzGxA9TUEuRvhjeO3N
7Qurv8Ysl16I27CSvHOOakJDUDdcG4MrYEDSy/cBkFnbnx2Cpa11W7PWxH28c84bReog0VPB4AnZ
RcDm0tQKYk6piToghlywhNXDpnNDhyNrHoD92y76dBtkGT/NjPFJGt9CQHImzbFt1Mj33cNQhfcn
pDIfp38cJ7bZK8pV1l5ODNPRVcKrivxNekAEDNcDtkRxf825pn4YgF0VrY0PfNvnLB+xpldrGCYc
n3A2zYP0vaCyqtIyKINcE56B2jw5Kkww45U+67wdAqQvX044q92gE3Sz8g1wkffm+ua8RHVMjAYy
sTmve3NXJY6dyLqa3AYQNVm+jMAvpJvf5IuHY1WVln1e+L4fnhLqhJh24so/LC9lrw5MpptqZC/B
Q0moe01O9hRoNLGjyclzxvQZxV02+3H8YGZhNXNk1wgUC0LeAJnwC6GVoVFOJhCEq60KmLKv9gRW
n8iA//2h+qx8RHZGGKNu9IHrHmJG/cJMErtT3qWg/WJjA3hn9rTmdwR0AWiAuYnxFLmBb0JI/RYL
kLVZvGfGz+N8kcW5ngF/GiCUJ7ahX/X6l6XlIUJMrmMx9J/QZUtEmE7iliTR5V6GrX8LITBrPcaO
O+dgfmQQ6H/PSOLnv1an3b+9Hb5MTJCXl1OvDXRcENmqnp7/L9Gvh/jVGr+9nuMBLWX9wKAxKLv0
r42PZ56AjeKIO0aW7kp4ATAz1XxQXybb0PAkGk+pLPVtnEDaeOPJUTl7ZLN0aOPoFgsGX8/4eSqC
THz+GPSyHnRLYEo0wh67MEch1Wn+2iG8hIzquXyZipe8nCv908bdAc+vc/aifjtYbnRT6McnrKE6
4Dz/eTIgRQ86PXszxjNlUx5koFbopP7d1aVhWf1hE0XzWp/kTRNDyD2aTK2ebXEOgl2NwNi4o2RJ
JCuxhz4tN5XyWfQ2YAnYW/LuNMNry7MuL+pCO3k+j9WZdML6wxtyLoWg0CpddaAfTRhhrqqFmb+T
XKdEoObZZXefJvLpkTCKzP9jokU2PbjWLTaQHBiDbJ/zJ8tNPKrmqF+i6W6x7KwtVZqfC/Tg+Q8g
HXXTsswmAdhI8Sn3uZLHKexTk8W5XJ4od5x50uISFYwTg0QMrU6j82rd1PPio9QUnBh4DLM3HjY8
4OBB78uXC0ba0Q623lF3u25kGon/umHWNDTW5tCwMSJT81LK+c3wAHy4m7zZsABsIHg7JtzdNmGx
rJBL3LbuVl5tlNMFZKF2mdmvsbzADMJOKsi9zd6JdxJsIpq9hYXlrZ8v6qe7YrwQxadxhV18jhYW
oHTmRAPYxtCzVTrMrGKBagNi6ofsmDaQvyZcjtNSZUdfGd4IFjrNOErIh2nwDABW+ULGH/8HYL5f
FC7Z/PYbqwk+C/4hhix2K4cOjfT9oNRq+jEDpZu371RUhI042Iv1emoFDQV4/Xt0uryPfCkEIj9R
V2TC6EDkp7hC7amtUmy2PudYlrvQn1Ci+MFhk58lh8XEAxC9VnKZfrM3uTvXkxVCfojAfyIUipoW
zM/uoLiYLGBpdJZXZa4jd9VvbL6eG1Pf+ess7IdxF8yJTv9trXocVUF4CcR+Z8MPOFIr07QU2hKl
BXYj7uiVwEGdFqSrAqCoSGI3uXQO63EbradQnzgwrP7VSbBb6UkERKUTn7kDVoGT575v7WD51Z3w
d3zsZ5tUkauL3TdaeH53HJ/OdjCR/B467mxq8EVlk/A2NXEICX5QI1Gzs8Ut8TGk1l7B0CV1JxN6
IRkCkWsd5Jbp7lMYpoCx+ZrBdkZiLHDVL3FJ3guZm+7c5tl/Mn09FYD/lei3c5Udv2BQs5rJhqlS
Dy0BilE/see0To9X7sXLKfpgCxtUjC8hlwK4+RJRtp7oM7Ts3rAdh8jx6MUdcqGAs6kKmP0PF3CP
ir2vIbluoFmbNgs0OFc8H3OOooA7ggvORpluA9yB07yp+31DSSN6HDqxPGhNrrGZ9HUsYlhaKuCm
GOBND9rXFWOMxr/4Y9r65bXJU7gmq+oOeZxUC5vHGbPqUZBW+tWuuKOREw/gwf4ojgjyGBtc8469
wUZ/spvZP6zkSsaWI4fF0Yg9U20xeU2yz++MdLwbi+90QyKJ07GJ2jK4gixypU77MZ35Nn8IjNnD
woTOe+KL11XIjZ+/0eZNKN+VCCY8OJ2nTjByy/i4n9NqIzDRs9KSN3mV503zeYjNe1WE3tWoflhJ
Z3RLlUSq2L7rLwtZc6M8FhBTGWpHEpnD4DPKtY1b2yRxIL+7JjjGyGFNo/yslkRdhB+2phVIWzpK
jldxsUEvuj0evhoWOItwmNQxxdDMdBxES067ObRna7p8rvZtXXkqfZnxXcrgWGMtrOekIJyH+30P
S5dIsq3fjWvNCePuZXf9O96cYDU+MbwemRIQb+HDSVo44/gtkzJx+hb5Eu/6x9C49nfDL25tm/cu
Um/HF+cij5a7SNu10FRBXhG73N5V91UOWPXmGsxk3VZg5wV9THxOlHW7PISLBSnyp9MQEJXUNSNW
1x3ZgI230dSteGVVIXIJWJoCCECwUpuWOgi8ZFidjhyNFuUs62q5OfLj4EzmsSHeD9lrEpZK6b71
1pCbXfJFwyxa7/ZPDXrwERRQ2LBzltS1XPw0GexZQeF3q8niOQuppg8A1xa4X6mbmwmd1RTzlRr+
XFVBnBZJU4KKVd276/aXPYp6BOPU8bpJ8zpOr8JNl/V0pt+Inxcum7Hv8d0oaZBEPSkWtZGQqw5k
XE9LHgXczqMLtgAx7UJRNc6HsQF9w31oJ1bssT8A10UnAxdMJtRyTGwL5twhj/Ovk/Z/0gRa4PFZ
21OVy5hontG6W+PXydDPAn+3T5rxEMez4Nj2wV6cG41BAHU1DBghlHrevX0Y4f0uq/djnbSqrcTc
8DUvf/TkpzWcavZbzaNuI9YNWjncETdyA6QrFzOaZZpLklp4iBaAzP5dDJVHDwX1Y/D7i48uUfsg
4hpkIJ3ZGZRNwcUKR/JLjnwN5pRAzfsoxfXUlbKPY9cBSy7nZxCxTnfN3rQ0aitt2nHup0GPV1Qz
MIlwcwaSeHgn2EB4l0a6AIO/xe7GTUDffx/ild9nvaPbi2WNiCjB6AgiSXssbvme9dlwJ5+3ibmf
HuemdTbrYgZSa1NCSUwDYO+eV01mvsA8K79q9UxBLiZpI+8bbdNwNSXRNzU14uECI0Q860lMOCbf
dwz5dKEn6uIaCryQe4SKJOJG4RH2Lyc0zeWE3hwnIR3wmPPtFMJB5ysSw+Ju/How6iQx1lZPp+Kd
OQwNTwdVtBf+80bc2UPzcCLZvTp2+GRXmtmCJNDgz4Rih79KhnOVnVIMjHkyyKdfpuLWhQnp9ZAi
j9OAcd2mne/hmPvYt0w/y4+02Y+sEDQ8Lo+/+lRH0U6Vn9kPIJV5Xl88ob4hFUYz76CB7BmPpw/R
6cuaE85SV7v2u8pyG3JCh87fsT8+ldkGbuUtzHg17ws8hOd8Nj9uWpkIkQA23uYvaCFcGJVwpCCD
bxxGKwJYNotpySxmhFq863rWFy7D9mPkrnoSVU3tqEG6d8lxRKI3uCwzA4ZgKrHWxWUc78ue0xMD
HRpS7Mwu2rClkb5icNSBF1nTs53zkx2fPTiBQu1rkqRwFAaHaOkdK4tfemsdPAOQm17AylhDFdIA
i+5H/XUT6/yXZdSr6E3bRdO+5p6FsaQBDszTtie7kS+PyZ4cTgp2oBt6yHADavz1HjKiJbcTf2Nd
SHESkDB02RwBk2WSVtsLUY8xOKDVOhTfFDWnuYXLvamqQXqsRNLxq0kDUIE63rNItdFmPsDk+bSN
lgy8dNJ2ghVlVK79MEvFiT/iq5LCiQ9KXtwLtbXUEdjOzpHAxMix2kxzVvqNREeYBPXaQYpdrR3B
ZXCrD0jCcjM8RUXiYYRVXFS1vBK/hvMDONjVnFEkvyTALVLWYsa0gmiGn6/MYFjoAxNODr7tR3Nc
E7PNzv4On1O6K3PxYGkqtawbYc9CSqepLLsv7mbkgS1oM7ZvVQKwSTvmWHQ/8Ij1Pzcaf+01p/eu
84SZlCIhgbEI+oVMmgxVrcl1BBhbb3iXAJTQKf2jQhvdgS55mkBqqTtpc1B2eS+GfWdyBcvbhoRT
DP4o2asTCgNPzm3WZ0OjuEAcSu3OhwFRi04VESjh0T8iqIbv0HZXjLlNbnIJDXhHH2ubYYIIseRO
6LqqzPKl4c50pAZhi1imK8yvVBZbymBZ06EmvoKJuSheywkD6LNdCBdkIG2mh3aP+4QruO6GnSpO
5AQ1SK4xI/CilvehEB+STdnRMgKx9YLiJL7t8V0jGcuZFvg8ndUrR7uTXgMHmJoe0lvqdHrwUVTM
pcA09XrSOLCJ46dgox/u0DQX+Vke47IBekqBNeRP8uXxl4DhNXeFNM9BKOoS+dcvQvQXTDN0lKHG
tFOzgiKxREA+ZTfPE5Qj3lxJbvub6xOuMEM5baaxRxVVUS7cYxi9mJiV2AG27exN691cbRwd96Rn
FolwQKnjJ5TVO02BwRNmY7LLWVHUASmFaBpokzWRcwvexzrlFVIpl6u5RmxslYWQ0jN3p8fiN52m
KrLYuosb2JK7IbGULEmS/OXBogMrkF/snz2qH9bwRW38qkwL8DVvw1pb99ARFewZPRtVZE9x+nYg
VyKmCrBmHA5Qd5lzg4vLe2V//XPbQu5GOu0NkUC0nULk2cBaLcwjSoHNYAfMds3Cn9lyr4vTF1pE
9b7D4dmUdZHgKiRbrLzCPVG/rmoMnXZtz+sMQlHuxNUKuze5/oD0skYkgmTOUZdYneo9z+C1oqMe
J2JV1SGTNRmXPHL5mxrgUtjdwREC5gklfmqoGn1Fi3TQTvb/N/wZeA8vftml8ih0p+E8F/naYCy7
Z6VJRTDsmLaUuYVhx7h3aJWDyHZ7DHkC5/9NW769cWGtZuyyAxrB/es4upGxsKYtFyLZEzf+atN+
oGdx7kmY9oMz7FEB7vXoowRq2HS3vNCuS+HbAOifWXUtFWyg6kniDezohZh+J0bzL7/MnopnRWN+
FpR5L/CKL64m2M9VvwjIScVswzO0f/ywNUsSPXQhEJpm1xPq7f1jjuwAJeBexqFv8tso1yT5EsNI
r885fWmmOF2xzrI42hGgN68oLKz1uleR8vyV17QnsqXBS7qX9aMISlkry6bHwMixS5Tx92cq7Jw7
x6rwJxuF5mXPRnBktrEnf3Co4ma8GENR3+lBYemEMrsv29GbMshQgd5kyw99r/DOpwjsdDm55B+6
bbUHs2zL08PalQVIsTASlvJAb00e6KHikh7U3Df1ak9GO6qHIsYGF9/5H77b6bETlQkDJk9yB7W7
rzP211HZnEdcM581JV6zEvPcJka7GVFSaI8EcyNTV+ZtANlu3mJ/9mb9bPYLxFjsPPsVQDaE6dtq
53PkNRJdwaQPwKomJJB8GfqXD08k663WGZ6/qhlkRJeDmHv34q/GbW3ETU42/jLCAFGi72KNKdWu
cUSPOK5BRz3SGudQKjAIb1h2gtRPMCtu5y6hVBFyHYoS8e40Ah6SH2shevSXQPGx9v4KGpuZSpRq
oRfz4SA4m1eVPM8LcuQtYZ8STmftYNGdYS7PpBW9uxGjtnNYDWRffN/T4Jz2VndpeZ6RPY6Wll8r
CPMbRCKkX3Y0eq9OOC1RLBP8sMQyhAC2B6FZARU3S9OUe205Fjsb46o7gywmHjTKrKT8ikKzd0iI
+LQrW5f/eINeA9jx0qzlzpIO78ti49HcVsr+kSsfDLOf63VDKfd6M3KXmznS+cwx5CTzVZHooWNx
+Jc5KHfhhz4mRUj7mX/DA1/JXG1L4mjhA5SFXX84Oj3JPK//aEXJj9StB4cOO5WewPp4Iq6CmyRs
KQcx/Q/qjho59T/DF96HYb+1NR1bdnihLFKOnijJ9FtEaTDZ09rRwOTcwVjlbg9eC0v4vf9XOzDM
wUBG1XpTHdZNnv6iz2Sl0w1mmL0TDBIOmM0aPA698nxCwUJA5cTU6qe40lS0uAXSXE+FglXy2FPQ
/xjBom7j2wQXfxolFWokP5Enq6IEh+XmtiGvdIcu2QJsEptt8RYMyaxuKdIB2TUVh58ylZDb8We1
fv8gEmFkLFhvKhD6y8MMgKsaL7fm0hXXIJag6QbW/aeNZtbdu1ZYvtme9t880mf009jSXdglMZKP
dXa1iSjE7APdM2zybefPm2mkjuZqW+7PDpW4TmVRh3mdwibYCw8X64n1+lcys6dyXDkXhPsvZ1G7
tQPtPWAZrkzhc3h8Q/DuquRZMQZIWDkoM0VHTyFwGVcBC9i5KORDzisg07CdwwIAx+ctOSv+ArjS
xMG42VNz9/d8HUJpu0WIP4xSIMPbOLSd23HzY1AKwpcNbjw0XHECH+si3SCVvmMIGPTsUlliZXq2
ZkojktVTmLuraxCyLx99I0jmD/DjFFvY7tjvOUpEQeMq/yH8m+jniu1w1oVHMYLOaITFeKVfmDjm
uv/dwqVgqsJ4FkgszR5ydmAJBIhlN/O1Mjrq+o5X4iCA5Ys+20RMEKnJddg51lGiVoBesoPR3Ufm
Ygolbyifir8umrPHytyPyq4plxe9RRQTi3YH/qLr7d6IFfkHdhprHhWr8DPBeGHcyE8wwdzFrnoI
jOr+omj8VkGGsGutA6643O43TPywVl6jyClcXPliJMspCQN+8ow7p9uJ5gQ1C3pYwvjSQk7NGsxM
KzRdabRnLK5mt83LcKI4buypbkXkHmm2b91Kf+stdCHWcjJQXstHiTcWnwp+RivJEOp+wh3FZikZ
3rti9iCr0j2j47/Cxhg6rPhMQswgNv649l9Q3h0kfKIASPUjJJMnE3IyS/tjqryYSxKfbkh6KoUl
TzLQ8v2bF/FpA+YLcNLzCZV5I0fCyePz+5JwTXMSTnXa+Y9u3yVPdSitUSFOamBqmI35fBqKOrKU
fAVPAXJIumtpfzzNJD5qRBP03Sp7saAT+UVZTSxPOKZfRLKJHC1/4m3DXksXjT6x/5aMsMHaW9RF
0ej5iQhkswvXlvWRr1Yvn8qGC5j90C57iM9//YONo/9yjn2mi2lMALod2Fd2C7QA6pagbFfylzAp
2DHllTCXfNTqTqpBPBqBQFMaM8sZtQ+7sd6E9yw1jQYSGYnLEykX1N3jtGnNbs8MWF68RidJR5Fi
z+OIalpY33Eo29jvqIvOcCnbIJoHbYZeZSeP5MM3OGGfD3+RO6+NVsFObnS9TgMaVH1ZZod9SeGS
7Q1mVwOBuAsTnfZNiiJI0R0Ho6NomqNhsxsaup9RhDUC0M8Ss0dv5nmfZmQ1HDU8J+zslrVnNG44
vx47zv2UjoGyOvclghKWqBv4UcnkpSpfiy1a9NkEBT+lUZffBAOlUXdbaTxYAdE7sCsjQsb3Hn7D
4p9h7S/otu9c1UisOsGs8Y9gSP9NtieqFORX7KMGvn00nDOyHmdB6pIMxMyX44CgKX5c8pSkfBfR
vCtlUyC+FJkyPKh9lsG+DWLql2VWJr3Nnvdoo19ZkSNMlox6WVdmNQwCRq8y5LVMR8C5vlY6TF7d
xHUuNZ0ekpY/KdT4/t2kqJ6IZmuWmACR8c2fcGTzGb5E7l1kPhRVxwJpJkDTFaolVEON+tRSm1Ve
LP6wKcgM3+5hV9k6SUckoV3wFArNPKPLsLXZG7qmQMxVRUBkKcNW2rqjod8Es5f/g/igGrKHLvHI
/sJXod+FMBWyG/M+Y8GTvLvnkXyh8FQo1UFb3YGkng8lACvIel87C8+SKPF6hhamRLlMLXzT0NDN
E8Y72/VcmuKBYFBO7z9bGBks8wxhH6Li05d4lm6u430vHhIxjs/EoMuYk8EoHzjV06WNGIJjbMdC
SzkDX8ZJSVTvh28C+aItK7WF6WRYxC5FC0nz9n7uK8/yqc3uySy2jVCcFQQjvODj61ceY+HpvNvZ
/nUG5GSbPnJ3/gEAkCDbTe7qvbtEHZRsGmAPDqtyivYcKoOM29xtUs7BciTvtSDWZuxme36UpsBg
M4nT4thOEwt8U4hjDsbAhHYPS8lDRXYSXaaph0bb6eowhq9dl+uTBpR8XVjmbIqUljZ8K1fHb4Cm
SsXR2eKB0Nw9rhvpSgH0i4FjXycvJu8DLbQw5yvzo/AdRLm6bXN6mGDs4LUArzQCV4vxXPgO0NJh
+cVBuHRS6mz306jRKmr5cD3kCCutbEb1ZO0sEPHAkHsVlRlGaJ+KjtaZcrhxSvNySk/8TaOomS94
xOcKXu/jrYT39lL9QFpvXuHDnihKR8IBeR0zuQOfXT7PVUeTUxwqZtfrn9xRYOa03sfpjV6FgFqe
qRRBd669z4KS+HT+0QIk9hwLOuBAlT0SEKiw60zdzBZAIW99TAWxwF1WQxTDedHxqKM14vvDXzpZ
o09d0DPKmVg5ehM1WPrg7yTg3qNZMl5CIr8/NrSlljWhJcO+RfmH9jsi739Yzra6ew2VML2e7lBB
7HmVqBiaYILe9kwoKaARpl4P6dmI0VyKASZRvacQiJ6LsDydEeuBKevcOVkp8MW+pHoi+iW35gYp
zXQpMh5fXmw2LlEwF8TXrxVODhKN5AItOpPHqRFy/7eFQ20pZgBEymFjwCOvHIOM+jf79CujFPti
z9EXb1barx2XXAZ0Yi+kwbtWFRSBpVfRjeQn7+V6qKDn1n3BX6APJ5zgm1dbKw4x/WKuVq7C3cs8
TFbkqqLaJsMxsAbDZeS6mLq03EIdYCNyjeNR20WXispjksm94wfHi81XkowEcd854UnriOMKaIdC
iPg5bjA5GKGh3QS3OTokJ7+eisaoZPIEApS9JjyYlIVU5A5dCu+57qm7iFdWhTzAg1X4hXnmHMn9
Wk2c74kloXqBN9KiP9bSWJm3xZpiwhINAArQ9j5fo9NjNvCNBS612mli5SB8vuUSSFLNoSkX3wOv
l73VN2FebbzKQa+bh8b8hz/svc3LRpYg5W6PxUz7JQuHAh2r17P2optlaTSlAsIbV+5W56it9V59
9zpS8m+Dn9h6gj/R3Z0+FE4w9/y1BIMA3YL1BLo+lmf5HuItzf1nmDgXoLVO0xPHsQpEH7jlOPZd
0oO3Z6y/wmutCi/MHsrDr5L3jOFmM7uRt+FlbWtJdGOOhpWCeWw8br8cFjuVMYNE5GJuZ95oDH4Y
OUj/gRQwdTsAV+QREhjFjYKRaPlMLqXVvfVsIAsClviroKIo/0BZSQ0ZULOGUSvP1UtMdjTDWGeU
6mBu7iPF+HarNp+Nz3+7w353QhMce4t4eNr+V2EgYLeBxWJ7gBWnw1V3BshynpzBkLbd0TAw4gfg
/52HPXF2uu4MxG2rO1qGZ8zX/5NQ5UPx/2YP5B3F2e9f6TF43WAOPxwi7QvKXaUD707CNvaEu2cI
JPLM4jJw5RJ4XSKalRgVu/LR7mHVNCrmFnZhKEIyjbZy7Moc3ZTI8EBWKE4sFZj+lDdWJdJU0aac
piDnOYEMy31roWQrkv2zqQ6L/zsNnIoCp6JOSkdH4LDyD55C6Rsj7Yab9RPfKU2SnK0baytDC+YV
9hbn+W8napA3wmP7S9HIHEzzke2ruIZi6A+y0LulN88w1pLZ+Avyjs/N6DY/Lmnj+sunM+Evr80u
mLUgSECFm9/GNA3x5WTIELG73wJKY0wC9LtiudhPX5s9ND/+nTrFFHn+3JsJSpXm0spJ7mpMmNnC
YHLoBNJ3MmoNyJ+kf5TzClzhtl0VxJnn6dtPFNtBjzefzndnHEqIIpZ9WvehCJCBe9ZHRHm9oQi9
KhEbltbwLIYq+jccap1WaY9B9tcJOppV4+NeuJmnXyM3GHDWhk7+r7sVR+AK3+pEoP4xxb2d3bVf
xWQvP38aP6eLnkMhuVLOS7lJWpSxyDuBG8jjD/n83Mg/hE/n+U9akABBOkq1i6TvB43zboiBhE1B
tgPvO5gLxzinLfz/zXCaxzx7haJDZl0pJylZ2G11K2W3ZBIuxGPh0VkOs8WQcLnVtB+PGoZoch57
rI+JEdKZEV9emy6JssT5AoVeoFEzMBzwxdGoLfFKK98WkszUcxaK/hZ+LuDdUeuW4WiLpknMmSqn
fihRXYps83IM+9S/X0K+exTqwDVG/lmWgQoZhGvDfaMLHBhxMZMEJbuLY7s3ladGScwQ02/8dzlV
6ftvQK5zjTQqCuLZM8my/d3EtVBJuTTfG2O0o3OCT5XGZXiP6a4MtQSvtyYQx6DEZgMFxGA3UySh
tkxOSPm6E1AIZ+cfdVWhNr3ySMU6J62n8oEs4lmpRbO94V6yFNoMSf3xZpHbQR5EvsL61e1utH8T
OJfaaqPqkKMs+Rq8pl3RbR3xk3iPY6Uh3xFoHuzxbPv/zSl/V7iANJzrgANTSgeGLBH5Yi+w5yd+
2+s7idE7fo+HyYJQUI7X6LfZh2Wu0Yv7kipfsXkEOFYhLqQCwCHoJRcIqzoWGoC1Is0wlIgTjtkG
l3k4bPIuwi/DuyS3rCHcW58u/YlTYZg/C5YJIQ+40xmZAbm0qgxTbttyQai170LNhtdW8m0Hw3Af
hZGejODeH4pORXp3Ih/iH7tq+f7daRiS8iKo+yCoUzcYdkJJg8jVdq5CRIOZabJF5ppVgSuZtuHj
MgZ/UifPrUzeDAIkAEM/9c/ONCXbytF0FrjKqhTeex0cR6lzXAxlRURjD/VCk75cF1kFkKhPFNia
IDBDwM+XnkxO6xbLmw9QNuZFj/pXR8hvBN5KV0Nlra4xB9ywAL3Ni9UQjYJ/PL/hq3J6u66v+0Nn
MeddxbxlcAxImllGwQMdSw7XYqaEjFr6FSxAxRgskOpfBP6My5hSkzfHktT/t9c1aV7g2QPdnWtT
n4X04tKVVNfbZBs6V9hLqFsN2caiPK4i14452fXeTPeHjVDiYEzVVLhV8MlTVbmklaIP+2gtCwC+
+ra0be868QRxgvz9NIaPhoacGiop6GUk5pqQeW5nIe2058FPmGnbKBQAmmA21Aw3/+wW+fD9c5/j
N7jfTW4+eAAHzpyw0HxaKOb8+3pMSLd30Q3bzZ1N740YnoLvSUotSbcMdPkLWih+yOY9ZUh3bboM
k4LZl1+JTVXDcIaRp5+H+HHl5d4v879tgVRSFTPVgLRSTkykjf35HYa0OdIN+hPkzm4v8f560g4s
KGoU8PL8Qkl0cRZDj6TblPIi0E+p/mc1xXeiylVVDW5TMcmhNOz6oVT2MOr3zDoN1m3DjIi0DuOx
BCNgpZt/iMbMvP0A5tVi6v4uPlMapDsEkSKnLNh9NXcAAFgNDTH4xV3aptXqmBHFtbjoojObkvDO
e130xe2ZUEsidZPlmCKb+LXoIJY5eR7caGpGrnU6uXkNXwzeNDEzV5GOjkwHbm3x0XuA5syIqh2J
1IZjXn8sX0t0DiDyA+s4iDJZR6w+MqBBKeOk0S2RlX4qgAIgseSH6A7J7nD7KfK6OEUeu9wqqpmV
51XnKZdX6XiwH3XeVamG2AVQH+nmNDs0UqC7Qw9cwMYkoZ4LFgo8cOMWxQqY6c76ZLqqP716PpNu
poU/mzl8v1HviseXuw+ofrhdJAbnO9ZXK9z2rCQh+C0m61Q0niSqUZgynx+gfwnnwalpAxEjff31
X0CvTW680kpCn435wdwbeT5pCPks8070XteofzlFCSK1apb9DkXSit7Dvr4TfuNOe1Mzq3kinjor
MGpbr4pxvK3qVlbWNnMOkideJX64v/whiFQ9aUJPzkAwQBF8kp+1XtdOZ7kFp6SDnLvaZe0z+jTP
CgMBk5Utp9XiQ0mxBtTbdTfwTRy+c451Wvi0MULkefljrV1SYvKtaBzl9mci/o2qyK3HhKdrjWYa
uKFdFGtL72cNWxFSrET+GSfyj4bV5ohbeknY82J7n1A/s9q09goHzE1cU2+U5JrG7UMfNQ8av0Pr
vvKJO+gD5BZfcDn5y3AMcDAK8Zh1oa/W2ZFZ2lcC9n1ex4SnCQSbnOk0hTnhdvhUbihJ6Nd8Gn8S
seMrr+lFF28sKBvQfSKJpjF+YKa2xpkC8FGVjnR96XlzoAjPC13BmK844NNQWRFAzsBrqW15dW4C
K2pW528bP17nuL4CL/98YZEQUShEW71x66E/5I6oFLWXyHBG/pHVxFHvZ/4yy5W5qi37Xfr9D5SH
tYJBDVv/1WPdXdZ5FqMTUzSDgpr2EjxTONaKHnLvgNhME7HufgO03xF39i9r+LewnCQaVR5FogBl
PhgehXviaBNW7nJGA1pQDD1xTUBhpilUviU7o1LzazRGrQtiLbIyMK8YZTHQq92fmTSxVdc4rfF0
VNZqaT146+A7/rcFlf6odvfXQxINtjTGMe25Ypw94HYL1bbGllC0FFyG/1uh5E7YsCReOK/pcL7Z
PA3qsC5yTpDQspvkOBAYekIiq1oyCgXcKoq9R6cXGyd2dcnMF/nF/txbeCQ+zYRttMT8CTZPV7jj
zNsRMwmOL4bfEXQ4aQUTV1gjfOjMFrTDuFkLWEIbIUPQK+fEJqH/YD7Jyv2nAQa7O11M6X29nrgs
FhiHh5UEefRiN6foAIM2tydaPClfpAGDEVg7oVE4wADP7eUASTtchRrG8g4GW5RGrG2Qhvwjz3ZF
vssW4ogeKbrBu0pz7HSyr4PSJdqSTEAZ2SObBSmkfrO5gOVr1BlNKFvXBIQSOA+mCm2tr5NaJfjL
hXxb8kb2pxgzqaAnuxPylcp2W+kQIYguCYC/gPRLMx4Na2w+GJLdwlCXUTnS4kC4OYnlH4U9ybJ5
iAcU384WxE7csqOuMyioAgAWaTqE3Gxybg78ysqcKHp8KrlDBTW4O5hUR/PyFNY058eN0aHnJ8Ur
TmJXniNXPDaH2lmFOyuxDkiFkA+Pp+Kz0aqMMbOjp6Vii2zlp0JcHCdv4q2/BuBC43KIMUuAyPO1
Vxr9KExjk/K6KloIoXMcgF3KfuI7OUg45lXYfe6yvq5fGHW/02x0R0uVG5F0kGb6mzHCNU1PDrBD
A4bx4u1qP6GwmSny2k75LFc/H0wVhAXFNYrEiwCvDLcu8q7FQk12+OG8vFGeZn9lzoATETWAyGwy
LjdqjPpSEeI/na24xYuYOgmIn6WBK16LuLeexulYktv/ZYeCpI/ETB0YcZetYtHxaO1/wc+mK106
i32lHzv8GSm1nai5Ow0ECcT+AwmUfZ9qFw743loXWqMb6i4m7Xjcx7EGskCus2CeJp7pcA0bHKKf
ZYebeiqquLcPZGvVc4YcRK+y+1JjkNNPBHkUi564wvsvwZeL5XhoCoOFBB+hGXONWKb3kMQwufN9
YUsUKZ/PiMugK1+7zt4atUwXWtfshoAnHkS/BNdyb83DpPc6AMXMKqt8zNeGaVWnNlr5vcpIplQI
EcZAYthwi5o8PHrP9PV2aYzijMtq0P8XZR017/TojC4+rCdaQ+rSQ1QTRTwdPpm744/5YtNlXCcA
Ifpa9hxSYuSifiHWSEuq6Oz6x1v8msKOnift8C4fy38wVVkwBPuNBEgMpDU2gc+iB9ysEGdqjn2y
DoFzo1IriTMJICF20v1KH6ETzXX1qaNE8G29TehEXUKK8Qt1Y1gY9iDbNg9etDyz2zsZ+hWoZlPS
+Pm58tOUe/Im6Eimo+dEbtAJiGC5wFMovt0bSRZVxsONWZnrI7VOeAHZ+lwlVgrjK6eRAVDhzpd+
fw0offVnZfPRqYRo9pJTT+DQHm15uMGTxw1QD2l5AZYCa2BZk2a26C5hazDy+SAQdcg3VUDs5POh
PLjWyXkajzxPx3soM9CqJzEgtK6h4Nmy7GAPxzkKo1WZWomxQgqjwq7C3mKpFwJgOLXCmHrYgzYO
Ws59/eXdRYV/iIZNr/d6TRMzROLuSXvm7hhfL6LfQl8gTOylV0Fh+CfH91r2ACfUDjsyBT2U79mn
AOyB26klLMzucbQCgoYNFlhGObibDZmILBfbAA/42+g0RpzYL7wdAmnskDqDVE7BBaj41wYoqPYN
wS5DdR7pUgCGhYpV6NzkSb9x0yJT/9Qd6Do12qLCOOauBLGDhb+Fwif6UE3YdRipHph4+mVYabHP
1Oqleh96EWGkMLonBqCWeSUVse/FQglquB0qsezew7ldVoKc4VFBLC6HTr8N4RY31QKZIrUV9CB8
/q3BXvWJwIO6HPDg+aENVsEMR+yvGGB7Nfz5W9awHQwXIMSrgMjGckbubyfhZbiJmTfwB2ZxCQ4c
6+rlqvlASyQZpBhnu6Vv7VHldjQ1U11amRQ/Y7fCV99r4RDB7UA8Spx7gzPuP2O1gYolMpy+M70k
AwAx6OggrDy2K72r5E6aIbfBseJ3LlvLcQvxnnKbMPmI8Umu6FV4TzLQ6iMZFboYPH/5Wmb887TT
3ql/pWiKiAMRnHO1yD04IIo0eC0vqNUw2A0p3sdl/gDFg2wXnnrtZXgVfDgzK+9eHwwlIsctfMpm
ayTDoggCM0ITbXwFoQba3gO3pq+Wli6tTRtBiUDlAob2vwc95Qkz+N5RJgTEmT9Oj8Xk4mlHC2R8
qZbA+gK0IE9Tu9zr4kiW5S9upmJAgngq1CAVi+A0ksC0zVmEKcVdtQQrbPfAcMybgy9JYCE0Azfd
kDISNqQmCa6HNMOfcXg4T+H640xVC3/NIK+ITM+KlDRCUY5XzcOTn84+vpp6c+4M/PmeEDb6h4VW
lrMt2zIwMmHymgyYz4peIPCcx7SAQxIyNpXljwEHwB5a4PV1Ya07XoMGMhvvZ66rRZQdFHe5pTnk
wUVE7guz4TsxfJKsGbaqQvpnxtElJejwWtQIQW2Qn1qgOUvt3snMTxqZgvw8wUxC4nRTSw1USKv7
I+kaesKyRZxdhPWecanRW+f7cT2oZzP1SuZHiLnf6FJ564BndiaS0yquDHt8rIE43c7FjuqXxzqj
mWrTlPJmp3lrbsfXiuy3kr0d5XQbdannIuoICpGZTsnOHu83wiSL7LJwlvjhcKaMdJ4YNjpG4uQm
aDP/TiDMO6XPuqT81oVrB5A6R2f6YdmGTnN+3cZD7qCbv1K9o8gg6ToiUv+dhPd9/+SKfctdaH91
4v9Xb9wX+uzs7I1Qf6y8Aw0roSxUC6LeuF6l4DOKJTsrMIwWwfRM4d6+bhIFtWyWt2VXwkBG+uNQ
hqFkms35fihbifLztmY5OuVqHlXJHui/mOwOj3AtBzH49Rau/aQZuGH7yl9ARqecgMEiW2qmkbkE
ROx+j5cilk1HdJEsMzNGOBn2VyQZxtB2R6qbSP3xPAPkUrjXbsMQRDhqMFQbT4yTyu6l9tOkMOjw
VPMTTxRbsEN9maaNkRmvKZ16zmp+PEyApq8vKawpEFTIT5F6uDb62F1TSxVea35MDh1ijVsc+PLL
n8nSLVLkWrW8Hlhta/UmkfVz0S7Pip3/VQz9cHFVCQ1hHTUdeFC5aXOyy/J2x4AOB4gMwqKT8Ymp
u1sC6dKNSrOA2kTNgB6k04GRB75fR8E3FRWI1djdiSRlhhAuJpXrKHTmRieI0/nsHh067dVVU5vA
n0eV4YaJchhyQ8VUJw1h50m2vvyQhtloqpLUnXvEcvF5U+NF2vCZeHvVkG+jXIQaIiNK1GNykv4t
06z0gj2UNQhOHKpQzR6KdI5+Ep6+6EAudj8K31h/1MKeqCCz9l7EKcxNwMa34dZulKvwbLE2h9Qq
ZQcx3XEdGtcyvk7taHBUKhqNiHLW/mrzkL5cEmm3zT/OrEfPuT/J0vLin6T8rES5OamEJrPSJmte
ItljPxc5YNUEidUHAUwAdYyTKqdDdqwHa6uEtzklzdaTLTu3twKT7lhUrWxMqRlAq24TfsBuvm3e
c1R+U5uYK/LN4UTIgihjvPE5FxgR9EYmVcTrf0a+FNZWo+dFiRUs5hppASJcz5mU2akwmsrAyslk
K3tIi0jA5gvk6Ze9YYNDlHlPgAaFqBA9JtZAzBPUXaRHDuHiH2zWC4SAg0NLI8kEZ3zmICm9AyKs
EIvSfikHlSpBoPzb2yQoqtAGZQK/WdQJA2byryaJ3epQWdftuM9lS25w9xX/VWMmGz3mvpHnPkkQ
KYjLsBrKfcYsSW7zzmQvA+Hv+jlJRyGCZClnelZHraflH4Y4bnZLNpXHkdgVpdzxnJ40x5lHnM26
0sWVuU0Z1O1LrubKorxM1shbK70Rk6gMV2NGdyQetrT+O+ZPg9IPD3o26E2SQkUssmbkNdVwVekd
7wxvOP9tXAiqD/MXoOrqeWuGveF1NNgnh9JrXPkcAIPnSdU/IzXTIckHftJPa/8gSt7qW1awo6yX
4w7XXFgbRATuAKBh9iSPr9uxfGr1/S4G8WX/MkJ0lH1iQGDT8l46i+j3kA7/w5jXJL3t4aZgHuD+
1mNTbjuNmKbU7NKmp3cwnkC5Vuk1DoGVUOQWrWjFYm9sFtqP4RDmr/GWz2A3j6Ft8/4dBjVvtiJ/
GzsXp5rmrxdHly/JJGBrtVuIVUfOh69UOud8IHneBd6M2Z2t281SWx4lCkeceEK+CO8HW44fpWaR
JUetOVadPFbAi6TpwZ9gr8MF12ZUn/3uH4EZgItWHZxHdgrvUxFIL0T9gnSrhCcDP2Lm4CVMNS6Z
bg04uAssFIFPRZ8qc8cnzUOdwaIp7cAsGTcLYXJw77Udww32hic9gwF5H0F9ld/Db3pEbbvwA5kf
AZk5hsl6keYGsmvTTWYPHcBslucrf/C+zimiBn4ML9ydDaqpvhNscUniRNo/DeiaUTRZUhrnez1k
8jNRSTYop3rkOkJ6utY2y0uLEtJAVfUMFsqPZfKWqkxbPHolWi4GofZw8y81s3FcFZKuOLQuQAe7
HTdDzpboj9E1rIImrS4hjcMsAMRJAeyWxxiI2Ed3ZDuJJwWQXZp7uLxVxS4bTTrG1zNuJnEvHUkw
fCNnXVieT3abi0/r3GlqjnEeeo8O6IQ9ZVDCi8oD5UyG+XFkrqdprG5AH0o9FTUPIW3fCzsche52
kfscEzYphXuIMkfdgDbDiBHCqjzTesQbuK9w6vUMVSmalZCOBkHhrwirF7pMh+CRO+DcgYhI4zb3
pr7FeS5Ip6iEWy/iVCKELiDJ++wJUXrGK9IKzm9W8qzuavWyiG8fPmQwXXRcIGSQrIDTL+cCTp8+
ml4lwjaoR5y7nB+FEkt9uCqB7V61L3W6Y8VhQyi+l/7w5TBdLWx0dmquZxfAWmUGrWPOeGcjlfse
zppyiBN3jHH5i2ah71+sNLeTgshgU4ZDyapyc+cOT7/U1DKjQMBAcjfIcjDXrLz/GYtrigOh2b8c
VUalPUr53VoR/3GirXNapVmDnHWZugMgBNGdnCnWvCLZLx/rN04hcs34xflbZvUGYLjj4UWO7ppv
giWlbB+3vJY37qNmOf2374TPZKr7lt280rT8ue4sTnPYdMo2D7xz44jo08zjozIq78ivixeNjUXp
siFh7DI6qkVIJC+DTRv1JfBXKLHREaIMpZ2YS55i4yH5YHib1x4bHTp4QmCuAr94xXlPUgt+fpVN
7bryj0t63PgjFgDAFUGc0lhAJxx4OG7LUdW2haYo0gXWFSpUcrtOLT2SShzXSHb8x8zxIiF0Pi9F
J/aPrwmaBoTSgJ/517CNDuDAQ9DO07ADSbR1BiBYAub6eHmqSA+vJPjepTGq7kQ7G434gk19uGz7
jdjCQVvCXm0NMdhMAhEzazwxiXecsaxdcn/QKODTndDrBHxf172AeFq+RM4WtohP3rLyjABZ3lRw
N+TtXeFUkT6ntoZB+0grcFexkEZp88MV2XR5xydNe5KmIHXn12KDcJ6XVTdBYMaJfsq0fhgSXkRq
YIsow+HGm4FkuWJ6r4CZ5TsZlOVTVejBAsuqZKeSpx/XmwWVc4jEdrqZz0VgpN6SJaGjGCyEPxDz
ZNwv46RnVEuPvxc0Q17OR8YwuxHyqJPRHosuU4LTZjBtx8TsZEjEOHoh8rD0nJCEBJdQ8Rzn9JHT
a9+nh6RQ/cn2SE2DvOHXDd1CD/u2X2Z8oS05zgiDNdEyvhGOEigW2REYRgFfHIPODXtbHf9XIla0
I7H9PISFcXmxl//GgF0cLjHGhGEikgYo+WMaSpgBjSFBTJNq6jr6lTQlk4XcYEEHvehdNVSk5ljs
Ib8Zl0zVXoNod3KPpWJM3h1y/lfMgUvQmrz2S0N0+swK5iFpsoFu4o0UpyskRW5XNkS2YpBbm7nL
T0nWce78KcOy2hAP+HZPeQPuMyA/PBTxpU8XFNf+3G01EX/BqvfOfnXXFGGT7agmkAIxKMVbcnBG
OwQU6lBOctQu241CE6PSnix+k8gv0ceHYLN4DgiKJDzXAKQSm7m8Cor5td00nbfAdqHFrkyHq8CZ
eE6bBull80qgVlLCA9apMizVFdnCbTcWKINPuJJbvnQZIaXZcsgsdwXajTzvGe/l9Cz8aGK68dsR
rZ06F5GxLJLurm7DD9216q5at10HgesSK5yK3DAsYu6bQlQUgyRA99mArMcoJnHf4P8jAq2ZMHhZ
QJu4JP3fS+UWvzulu+KOXfMV7NDMHoWtoeJMf275eXppAF47VPKbPEmKnsEdxfw0Jmrb4IopNciD
Ao93Mddwcnil6VUYdmQqnQMC/ALBNuVvwBk9UJFWS4jDBVt47vjwCRH9GHt+bBP+WEJCJOCM0ey0
LGcELfEW9IhdKi36SLQPTsk8RRgbDYSVdfx7DCqDXkdWV1YTLFf7xFKK8SWDSYJetNB2f4PI4g2D
iUlEajaC9xCH/851HxCWQZxEf1LUuZaWkpxGPTsoAyOMGip4BLUdgs0mLBaVPZnQqdA0XBkctIQ6
YZSW1epv9D9hpc5tK0HvkbcODj+yJHDrFFnmvz3ufV+Z14YPVVUFiKl0sbEsqsprKkpSceyVl7fz
MoR+dk/tUbtI2tMuEsp/XnHG2RbQz+DcT3Y/VQOz0fJs/hBLbuBrugJuxYQ1ww89RD2LFA3ZwLal
fs3GlQWH958kfrrasBYRorGVKDJxrnv2iCGIeHO5rP3sWIyFFDTKHkbNGklrNw90RcGODb3ER3Ck
r/UCzFArXK3RJMawm2ugAFCVqNfhRg6Ito8P5d+JpZ8TPGjU7y0CTubcVdSsaMn4+Nu4lJvSxGcP
+OPAEShmzo7MdUFvBuVrTM/k58VsgKmqmfh4qxxWS6Jjf7sPeK3KQMV+teEcIRqrfxj1oMiu5vJx
yOwS04pzbhltQYuqFknh2NWFxdt2sla20ZgJc42tgrOFYz4+VfNJ5YZySctJMXLgjm0UxQdmldkY
veEg1HByoOUAnAJHhg7MHAaicrFLCg3Pm9A0SS3UA+soNiJv9/oXLveiE84HUYlzhBO0LxG/WakR
B+gIS1d+8a4Ngrd78XclIpXPBeVqfrBobs5oa79irGZtJcPszLv0DvqgHiONY2Ui3OSuimGNECwu
4lPDj9Fj0F7/pDClYVkC8pUnqZgi4qOVbElJytNwtSvIWlJMwNemJzUGgK67rjyzHd93ppM/5vEi
dMXn6oimIfYCY3jBI2hc5qT439Z9dkgXqoabcOTzR/4QbLnEo6v9v0yYVa9wQwBJB/HiiRK9/J3K
NtHPsBSob03MjQgualQxSR6RPQsoGMfJdByOEwJouPtoMoaArKOhIJ0GruL/OmCkvbmVEKBNcHwE
fivBHxF6xDu4Tsi6uhietl9Hq5H6VbGceAr+FSsx/th+bfKVdaRHxwI4y0EQB3hyAitadAOkfBQp
1WvVbrob9Ru5g7qGuP8k4ljgL0zP53FHBBcMBiXYRjtFczqPuK9/d5ffNadkaod+U3K//2JM2fkO
qs74cdGM+IP9916om5+gbMbklIz+vkEiWje7C1YPbTUJUogSfidTCU4w7X2HyFL5rFoM5tZnsTLd
aPFjNNkKHylMmpDEg4gjKiuKmgsrB3rNMzHWgmXGi8sISySqKVr2ERIoCMM0fwynAhcxKdVmsTTP
S+c0yYbDMqaK79itV/fpAnt5cSjJxGiJ7UjsynFFclbdTxFVhx6oKiFWY4Pqqu0xi7HOiG8yT9PZ
lF8CPwMq37ZVO2XECMS1XAL8rfaiIGYYgs5lrGE2O9SCXgl+6kfUFHfeNei13dFuZtqy+aBSgzf5
FrMZ6ufAxq+MHHpa+pZFe2sGX1ezol25sdtx2fvEIQwcgPxOeV+rk4cfw4DGM7XCtx3618T5dnG0
mCs4eb3uo6kNYnsTiT43Yui1eC2otgKCgYEHlAe/+qit9GtJeZ4MuDbp/SN9FrCBC11XUXnQKsbI
t4jia9HVWBEudf8LDbWDuiYdfoRad80vrlLRxyhCpWguiwSb1psZFuY+0uwADLF0q8Kk+lZRE+jr
hMuTap/gVegsNmIyX/kM8r7APPnIGeUxtcDZ1NuwG0Snp0cAz5faq8hgFnz7llA4bKeho3ya6kAg
TQuheNI+e+gFI5NHlIS4BD5XJ28nTBe3YMt1eg5NH4Rl2PJlqmJ0wWiJEx1SQCD8dIM9eCM/+G9J
4l34s65Ag2h3wanDfyyG+LA1F6tC/CtapHRob/TnvvIE+sXD2cvxsaKWb+PPQ+rAfka2my/2XKdu
da0eq1XY7Rxw26ltDJ41erOqlsIbSZ7tGGt98IH7NAuZkvgzTfoHHOzuuH+CI2m1VSvDGBgMKd9A
zczUkm/jab6uZKGgIwiEl8m73mq6b6yP4ym4Xu4CtlvsiAJoTnrViQbXH9CR6wffoi70Z60RzpAY
tULLJFcSGwEgoyFHcq1SecXd3OoGXKDApzaEiTScRt01EH3g9V4NxopkfRxxn4sG9br/QOf6OVvL
SbX/oYhE/V3qWfjtcHMGj3wbo0ykvw7sD5TtBrYRVF0KTVdFDBINZ/KIaIZGirT94jxV+OdmWlip
SlWc1+FP7eMlO34EmqXqn35Sn5kG9A0UJUkazdRjs/t9xSOt/mJToKQ1QHwKxYzMvs8Mxp8oUegx
mEGlk52LcVqyhDsWqQw/LqJLws2Pkbv8cCYitU+EpfOtQB5NSjxbavISkFoLUbPwDLv6wHJPxkPf
UM40Etsms5yAEk+KKOY1vTBfJ6JceZQFoqmCd4l4rJWpzCYS22ZhNduhkeTIra9b2wioSbnscPIc
gzmhjoqk1tBl243+Nu7cvmyMW4eGjwPX88EtmLzJx/P7Kw6iwEVmKPGb4UhwGgM039ZXWx1qkCSG
oF+RHid618neFyhj2oJwjLIJ9hKlOc4ufpT8RuTBlWgzmvS1GuRg9IstpXblCAOHBGDne2K9e354
UBuf1LOpnCoiBWcORqKVanDKtknnziX0p2zAGFKazUFlOOllSlBGYV9/+p1IRDqwcfmN7/+mAu8d
cJEkUb5dDBeoFObmfUsj+hjDarRRlb2lqpMCt+ed9Es2Dj7Jnc51yVRulAlda41oaYVQ/4K98nNW
P7XmI31G3rwkmkG88qp7OsRb6t+ZcKmW9emPbSrBaiv8UDePMqdsC16m51DTnnti0OidoFOycJjT
N2gB2f1/XJgzQVkNBfqLDhzY9R2Otw1R7WDnwWVz0YZOzlEhi7coulvbjbZ0pEEkF2XEht6gnt9+
lMzLqyh48rJfyVs5SU63epKCwIcn4WYXj/p9Vn7hJEvPej2bJffstlXwtkpptwJKHsdtOlD7+GVH
qJvzyfSH/llcvJtetxWgKDi46FSMtsRXC4r/G45ln5slmP7kdSnYVAJv0PzKAcGNQqRvm1yd5WYZ
t+Hj2YSopMt+qJjgaxRGCA/G9ecfclXLrZxAl+sCxTKoBlCtwWzYbt8B7XGD+HyNvTysQ+tuVTCA
DRrx1jHJIgDHFvC0rDqmc4uctQ7Y7gIGOJ5iFU0QHxpJ9HcrMKeksIQwWnPq/zcTTvb1ZApl4pXh
tcN9TjM3vKJoB+Wfqvcaj3/Om0w8Ud2mC93YdDBw4Gud5+jYyNfcXZWo+VT58QxF3hWNOu818Y3n
IIy9HJzr9/gs1dW/lc6t8ff1f0srjsLDi3LLNBnqnpO2BTXSjhPB2LkWTiCeD9kl3ooPj8H7npRs
oLnrYs8zMxyyC2w0OsRQaXjD9zBD5pHF70rPTE3IJMFkqPO47T9vzSEheEfVSbm0xMI7ldZ1N/2B
RfC4yrsE6k8OQiUWGyYsmZQPbDCnxvITYPLRvfRqUI2Wp2H0LuhF0ZI/2vRAV6KC1GM4ONZMOJOl
cAKrj/FslmoYEXoA+hQThxW7Sdb6ZLsszbIACRypLFQlAgQVb7MV24p1KoQeq64NB0jpf1Hw3b9o
ZnGYPr5/d1f3LhPayYu3P5xUd5PC0XdebgPGwcSbj4QAKfTwybT4F73FQunYRaLnpRkE9ktKKFQY
7j1d76hTVopkjaCkoQV1B3DQqIT4jsyTVjA1QYz9LsIdOb71P54trub35kEOqcg627uSVsBb0pHp
PEFdhS/j3w8mNjSdEkfhG0dVyqOJ2N1IlaaAmDMShe64hXp1i8jxpH+acNOs6wfJKVXDgORAnH0l
fj/NVnE8oV5k8/tbf5JVUOJNdX9zqgfxgd0Wjvs3aIy9z3cBBk9RW0ROGZo4e1b3ApcdnZDxIPB+
ORqxWwsnGcjWgSRmxmyGLCtzE/x2Be3yyl6pbVyIUDo+7rDEJ8kRuIjzKX/22Z1A1n6dQiFqM3lj
xiVsKjW558MbwQXVqpMZEaNdlMGuUpPMZUJsP3bFPb4uuxj0oS/6CrZMFjGP2wzrDmxkXOZNw4Aa
JSGRsy17JZs/BEivdUbmAYQp3oeqgpLtx2CpLNRFReO9mGwk9/OsrEIU4jTtanafLuwbzGx8ABCF
wQbZOL40C1h2j2ek7BY8E1r7287ypFGZyLAUQwum8yV9INdXh8peaSLau1zTXjjp2WvHbvCWsR5A
3qqZ66NhND6LZzYPnpvLitAfo5jF6d5rRRvrW21xSFQrFDD5cGkoPF6BVVf0qVXy18QG57D+9TOd
HDcUUh4ASvFsNwCzPquqzWx1LRcFJXD/TIQLsLth0mIX5XLp/N9pAKnJhew+imDbBFZxeUyj8ElB
xVb+fe5GvGdFRC/OMdJBYZrAqVAp7E93G/EBsdO6BgfeiEyXNzvfGSZJ3XJP33ObwyfJNkZeuA6z
RUnviWWV5X5eHaIjrgjuhM8g1YJOCF+OG610oDlYDnKK4A0AJTaJ9gs4wpVI+FUYH/uuzts/zvdT
zIMU+6JdzQscW9iYS+IOCI02I49K1EZYfjYDxl6PYlgmDkVkV0D13/ItCMz2UFr+SG+nEQ35CXuo
yNeQ7dvJXN99lluha/YM26EY5J1ubfa/SSNCvCOPqV8o2xRb49E7menc9fQy7VBAHgcQzjuya7+x
F3G6E9yT9F2Z5EMyAr7dx8iDoYm7c5QHDsXMnh31iTcbqJW9nnmd3/A641a5XERCAy46ODHJbTuJ
9CySMQtL5oXPL2bN9JliWIvHgaBDFI1ROWSXG9k42TCA/rAxp5B3fUz3TT/D+jJesmdiVj9QI9Bh
yqETBTPh6XC5eEEHWm3Oh25bDZaB51xyH32bbtEaMcPb7Irwc7kPSrieOksZtads9qncIzF0isNN
EbaMl1wROCfVfLL/JpDkJxZ8KRPc6UPNth+BdFH/lTSD0VEr19Ed82Z9v6ksAFV3iCoV15U1KePX
wMLDwP/1sTtWcCHBnO65YDTTV0TFCme8+ZmHmo6uVFfE4f5l/OS0zkmvnwcaErR0ReiFFoEK6jj8
qN+Ev4BN9vsmNVK7Cdc9novs9NI7EcquD2XRVNpzx17MQUwLRuy7S/xTS1El0K485P0koWInEmrR
S0FF1FF0JhT2umcCwrmdZ2L0G1061qwDqsOHPAeM8G5jZ5Y+/jmt6zvvVpxTyUqkSiYdkhK/wmLt
jzu27xPlNXwiwhqwMJd4kSdR3A9lI6MKezV5pzVdLQZdKyxvp73fK0AiWVSEwKLR9RQMjjSX1IIP
6tBhbZ6qMqMyeUdFF3CT4U1mZhFfzEUEQ5lDPtJnKPa4Bwq14ZJ0P1ok/X0Q5FKEHb6z0iDMTIRz
/mvkBWRdexxmEOXDg/Zlx0L8p/OKxCc8Gy4soD877ZwW/tnkqsn6EL0+NzYs6TlZuYxF/mP52piV
r1pu55Eyfc+pq9hwrDLHMCeG022ecc0EuMOtarRD4U+XuRcI/p0skn4oopgLBgDvy6U97Ka3/TDq
RyZN+uNzeAb26p5eNPyZnmRo+mLU4EQ/72zymgS1N/oAhgX9QAeFkGxCWPc6NAUMhosobSehmJYD
W7JOw8TKua3l/n+ZQGsn2T/LGPo9THDaAeYRVFNqyV26cg9aAa1sj0Zd0NXWJPXDEWT6Ia9ELdOh
S6tbmd15tRJXqx38WxwWJvy2+6bLDluqQ8hqYkLgzvnpQHpZEpfxYaK2hDk4mYGteKvpl65NARiv
gHg3OwmMEz7dWNQYkTag8eNgHQptmMGjQG00oqIgehWaQoTZ2mLFlA3HLieRowVwsulMMHyFgN8v
BxTJWTp2tkU7//mYYwVtY8AXf+fXh46eVmlWQ0pX5mPB9jR659hK4aFAKrccet9/Akim1Q5h/eFp
e4SM0wv7JI1oPBJ/XGtOVXxijbAEFJjU7NWqGHgBFPb4fQZsw1EUIZzekQmwx8M8I0r96c+2rT0N
h2YBYvFNnUCCQVsqw95m3OGBFs8jRXi2hflz1j1GagW7xUYFtGxQ0k7KrwsmV5NAMhUsZEWWX/4x
9+3FJN9BRYxDp7lRMDp3mBGkAIZWGRxiQPpVo7g2G/jaVIgPZ2Gp/s1l2dWBYlpraI7gs5EpgimP
oKzLLceW/y6bR29mmvv8yBRA7pylA2UtXvWZJdPl9FzfRGylT8aE7dG8MpGzBIP3g34ISPLa7ejp
TrYY5SWtlGgyysJqGGq7XfeE2D2kBtI33V2f4WczJs6FHud/eAUr/8D8wWTcZq8pTfAgpa3TiJxI
cQk6e3bxbZs44IdnmEoq7Wa+sCBVFkEdReEnWMhXlux0yH7y1pQiR1do7p0XWmI/4c1XWUS9/Xja
FSu+mFDrc102+8PChX24LRG7ps/KAEckey5U24EDe56u4hEOopVfwDJbatgNoh/7WLi7qmB1ycig
/LeZy190ggbomVEdHjphet6fToKpWKoKpjs4tF6xMpJTpuIwnYySqyo87aNRhSsAmERrhJJgMO9w
v1G6MbZ9OzFYJEcCcToixFperLKvaz5AbPnHpMBAytJqvzm+5x58YIsMH15TBjQjNpBNnFGg6PQj
mU39bHvR9JwchsHMazs72VbWswwxzb84i8T+/uziMlMoyCvVTETRxsXLWXVieruFx2QEB6b0cuoQ
rQaXugU7Ph5nR9Ib1HY30Lzy7DH8anhCHYYc4X1PQGloI5gZ6P4BNC/rA99m61pCNfagJtf/8+AO
acKirgIStV39IGpCYeoUu9VvtL0X1waLonudUwZwEICkwsfF1YNogRt0GVE/FL+NgqaU8jMtkz3+
UKJCtTgei3wpKii7/3cwdP58XjlADlOFZ3S9PmHBVxsfM9liDRHxq21UUbaUIt2nMbOjgecMGoXU
awuAMRcblpadzp5S7SGt6Ny4BgJIA0tGUGycrkOObYpYVSxw/nulNELkpoJS4jHbe5UlZ/Vj2W6r
4uds+HPvARfqFohzf3qAlLEiX+/PNfkS524EENyM9Is4XLcmKwlH3dgfI2eaYtwJA3dxzoIDOGhd
3/LtZVYhGorruftP10cMHrpssh1+FVCzrbmhHVjn06ZqGbjof5rQ8Ec29P1ZhaMllh2ZG6g6aIOJ
pGmMXqtP/4MEEsR12pPcKGV1ihKmLGAmmNQMuqVOw2+a/UtDWflTRf//W39UgIXHo8BCYm0eA9G4
eaSO1e+tnA/9NJMBxZaePFn82N8ZkvLJXT7sgiSbYzrTjGODkgXGO8vNPpFC5UJExiGZG5ogcX+n
R79WqLEgOA6z/NZgJ+ox+oBgxFGn6iLeFNknZGyK1UtJvBikPc1luWLQ1HEkteMK7mvVNg5F3SRR
YkOSzDNLRBbZ3jkydYAMDkVMY5BwZ7u+vdj+mjGj/H+hli5u8DdcrEFOHdkMPFw9VoCTF7q1EVZ9
4wtWlTxXYM6gqLdMuZy+TIP1UFw1BGF8ho3CGUaXz4mZPghnzQX5ANE9czS6NBWTUHYZhE8DTVXu
PhwomYg2qhegaMa8pwblfmJLEPWe4HCdNj2sndIVfoilUWtpQ2xX8raUTq2Fywcy9/tJMZqBixKV
uF1F230fJADVesvNQXGBaaKA5YkoiJBDEEutfWMg2jw+CNIue0rDHrXpUFyaINq7c1tAzlxNak2R
embtNi/t/zv6oMxT+YHuKc5QGWGd2vmibsPgryb8pRRvLcoGShDrvuH/XrCnpQTClLL1gbItoXq0
3/fLC7BzNmPSPmi/Czt964xFuxUmg4PJ++QafAr4JcsZqPwjwcIqjQWr8t8TVrwiH7MkjsEWr7nq
3e9ob2cPnnTblS3HrKMtkayeO7BA4X6aY3gPAKUnxQfBfgrSCBfjo/wHmm3Lyd+3PgHaK7akKqQ6
uMBXCQj7xQSLZMlUvzdTJKRMTPiKvcz2sMuLSU6Agf4IPoNvZ9uuFK6Ip5QdcIiSspAkR0ptHze7
p9HE2HKs9SF5nnC52XXRsdLuJO1gfmeUrEUVqonZ/Au9EuK1gqxlHhKo1IW3y64+KoWF9zyf+Dup
KZ3yAg39uUJEyMTVGqHAzHn71slR69UaPPL0vlDPlBdT22wP0po8SD00N703Mou5b+k26GtvgzTE
lvfWxgnQf31pSlV5v7xlkD3EPU45q7PJo5ahchCogPV9JEuU0xKNmkkSOfy38RBq32SbvnptBC/h
TLwj9LbvG8nbT58OJJ653FfG15Ztsg+QlBokSPMjBRIc9BDyB3S0chEaD9grOHkQJtt28wXRLl0/
zGaA4+vu7yu5e7d6kOXT6Pyl3cbXLE5/X81kqCX4soEPP0bRCjT2CbORjOkNslKo0xCJTv77GC5F
mr8U+YVqGwUyOwDgt031hHJ3S+CqeeTQNd4/EwMzUub1HJxSTCJ2CZ8XHeSrn30q9fUsKdIfhAEv
U1FX+u3nrLM+ZBJ4JPNmoyLrUu1FVat/vIOD5rpPCuaTg+2bBQXLT1bAtdGcFuAd5fat5pzuU1Hy
nt4ZMaxfW9V8uWdGdZNFOXvvYDefcq30fx0SRHQyiQaiDtsc25u58aah78P1M7ANIl10uw2fQ0XC
gA/f28GEqs07FiaJpZHIThDLtLDL0txakRFP7DHkP+9DmF1tlJwVrAwK+pF6Rd7a1n/rMtmNjpJI
bPguKo3DRooPskzlNSYgwiZwytd0QzfnQck+jYpQUH3cZ4PqOPmGU7dsVT82EqJZLyCBzDb2R7km
+uOW+QOcaPosaBRPw8dCRGdnJiXsp11qNvx29Byj+wnNAtk49njL+7Nk/DWBUuECYXUAsCDjJcZx
YSCBt6WOIi+umkOfc8qCNv4SJicZgU3SvAZUQqZNnE7Hxpyrb/+Sz2sbqrfeLhBM0v1mfYDv+/WJ
1yyzZb1H8E6GX+nTPN6iwLKCg5QtE0sfznBkrxh7F/B1SjxMwmYUPCPX8LsX16/XSxTS3dIZAQrS
dU4BwZ330dDycXjkeXh6I+rJrGXqV+wj+r84yyXfftX2xDB7/JwEzNmDN25b0/+X4VIIVVyAeA/K
Zi8LTHw2DYZbsIvGPk+iCz9wDgkey2di4fmvqlcrIq6d9QOx0nXahI9X3XjKEl7soMbohGrV2u5x
1xPeSosfTiRbiE3zz6cNCWdr4GRGPeWXb0RL3qfBKyFOX/uo4pzg0yvaoyCxr4y2yA3KGh/hlzJV
lJTBmpVmGmO8Y6WfRtCoBsAqQakPXKyBtrnNQV2cOglzVMi6lrC+hCF0oy4xjWEDoUGkI8YTq653
84uSHz1q5oXonRxyVY7B5UUyW22AJxZX7pNmLyKloRy+K9CVQLs6jVM1VE3ogzkrnwJL5y1aF7o3
pDYROStp4R4jiaXZmeGO4deeawfpvLwYpyBrJRBLn4BjQNx8nT2k5uQmurcTEHkHrN/NR4tr3duW
eKLDh3yLa2XoLW0+QgJqUtJV4DIofgabTxWHVjpSzDcCcMUYkqDDNqIsoT3mIUMt+gBuCy0I2piS
EuuPDAtf5vEQ5UtEWzjZVWx5e7xiZRnKWNWWQ9q47VMuTPa+9/YdOzmNl1CgzU4xGBMh8iFRISno
iFY6+lwjnhmmvaiLKmtAgrBl797w8KRir006ehCio/dw/tPQkyF0pVd765myCqw6TaaS0HOBWnzO
dlUookn2vL5HCpebV3mPGMCF/FExDlqyuverVI5/Ikb+9VbOp065NW2z0TGJ6g0gvVs6otQFRNlG
cUBsj1j8vF/xXAKG1a5gwx7n907z0mTlMk+/05ZGHUkvSFyK/eXt/ScgwOtb1IV9fAFGtyKDRThi
iIeHbeKKRVxl8kOOMQu5Tc4i/1inSxsgow3uKbQQew7Ya4IFhZ6DNbX0ryGN2CFBOKxUpOYaX1M2
63fCXRv8KoAHnbLh9ljK8zxL/83NS3wgjCVpbwHVwAyl3/9lloQlZ269RJl5QfBt4A6AA8GMrHBJ
0YAii8EXTUIqHP9U6wURtxYTRgDhFb3HqL9aKTr0y5+oCVt60dYsdx4ByXOinKEI/QhwM9G4TDer
7pio2YsUMMgqJmmXxBQylnM1RfeoRSdyOnJuc9P7CUzCkKne0ktZypTe5XTu3dgPZA0HJvWNzLCo
wvnIlqhCH+PF4R/nzptirgHLGzcM3VXOGRuySY+01kbg06HUsKBffei6nJE1vfpE2x75h/A8KrRw
teMXukrbPBMqvkPv6ZMFkVZgBLtNcPm1w5+b+qScP4MYYFIsKcDP7dVcDPCMVW/VNbR009jsLd1i
zUn5S09s2J5cJ0tdFG1an4Gjbs1tpQjp5EG/MPBvE2/rliXKnenK+e1nt5v4BS/SlNxBqmqHkEM0
WuXJk1cmgPmsWjwLZQHdpMrO2ptejRmsDlbxJPse0zILYJrONjD4OTS2c8C81NASCMYgXslf9d9V
L1gwsVB5KyZt3AdnvTn55f5PE2ho3ypyWniOzSQpAlLYwUTF8yuv9Z5ie1TNqhbJ6xLA0vcIWR1p
fAllsPpwh0kIA4T8cK/p2zEsUkBHhl3/MLmgLO/2rSlyXKrxHLIb94y5fRkHcnf+Je6brluBwdpy
rez4qmbleqqrZox57ng6zZZRVWOTO6lgKfAcdvQqKMr6adIElss7Wrv5ruCG/Cbs2cQNQIQVQ9Cx
yNuI5A7kaJYpaUcHt7pep5XuUizgrdu+sUorbLevlzbSc3zLAno662fl9S/mD+VzqrdrZfrW4RqD
E6YW8NP1I/f3U1XPhBRXmocE3tsfci0Cr0BD/s9v2i8cFJCxntR7kmnnGk4eg7Z5KGDBwAPA/y6W
qTdew0rQCTsnFOzyUASj82ltJeAeb0Tbv5J88F8Gztk9gkdqJGTHOvezQKnybYCiAK42EtXX8vnQ
lx+iaW/U5zIpegfV5d14pIColdm9vNSp6t++0DyhRkdLmE6RGJ1CCg5ZkvFQqcuOcjf6czQyl1Vw
n+GZ3u3yK7wwxCpMvLFVwtlKebzKfwcIwO8Mn8oc9xwI2zR4gk5vH9JL8qGGlCFOS05LFuJSYgRU
fmbgQUlVNAklH/5cXwoXK0jb5myyyC3ObkSJI/BC6YVjL6M9hHTuQY94rLsMwfSrC6AzkArcVDFI
+UOjr6oTatGIwOT5lNeGQIh3wsnRIeVZDeMGwPOaIiq2+G3zo0N4nmjdA9OUUNNGW5kYtYqtxJ86
zrt/pyVEQA6j/4t7wKHTRTGRLcIjLfjacuGJuGj49axDKZWS59nkGxQNkNkO2D3ok9N/evlwX4uz
+VrpTvxEBka+lauEcHj/ljzWPM3me0mAsXaF4qzUuMSiazE21s1ekxBS2+0FjVt8yv1Hq0Zofj8O
ZysDFucwvelv2elyhQnngrTEOMRjn4DVuAh/OV+2P521ba3dNMJBlTMvX6aGq5wPVtt4X/lcPBMz
gtOZkeDkqTzpPh54NK3Kb4qww/SuHPthkfsKjVHovPPHEe0KFIcxvxyVQNIIsAFJsXPx2spJXW5S
93F3k5mNHZ7UaHcnIIq9uS5oUij57Lma2sObPbRi7JpYpHXaHgOybC/g6EAg4qlH8g/2dgdiVIHz
lO1gVvyGYqbfPaGNa+3KoUuii3bjwiAxipatZh3vF7V2G9kg57QDmY6Oc2VMVkHZCcO+419tj3DE
q1kDY4AKIxz5B2jPmSumAWJ7H9QhNK8lptw8W+SsDgKeViH96XApw/in3kmgEg9Jb0iT7/5YpUA9
5efgb0skhfvLNFu3JZbWrAJBUyzEk4ypfKndKRzhjTGMtPd4s4Ori09XCLhRKsNfj27bWf7BCNoM
EygdgMOQL4dmZOQPFPThGnYotL0F5XoByRghMoZwH21/QLPOzVhZbt7pkmt+6COoxPJjdZLxIcRA
Rz3gTaLnnPS1MhVB4zM+pARP0hWk55YDrPfd2pNko8T8WCvKGl0f8Kl/omRFxJkDYokif9SDhMrT
4f1ryHtoNHNajtwIQXRVKvT1b6NAlw3/1eZBrqLPyQ7qKkTTD+mT6KUBHq57HAkq8Tt4jg69qyVz
4GE/ret5bIwEIaBYw8cQYcurzqhcccKv9P28DMIYYkJ3/Snv9EKXlay0hLGBpmBbwJapEA+DMCE1
LyXHP+4wKd4kCt+J95DxmtTrEhxPKWSAbhc+r6/LWYMZKxTWH17ZVyB6SyJMZl4i9UFCYx/zwqHN
9AEp9RfyY6ZxX4vnbcLF0ONUrCm4D8LB3IDUeJPcTIfUYZCLc/r5MZK52K4Pmbjam0Ny3b0TkdRl
FR9Ky4YhpDTEgIEI5ybZBYi2H6Ux3isq5gvBXN3zaA93WU2/ZP6ytecATH/nUFKXFga/hWk145Fm
D0q/gvieLiXA//UBqbvW5FOEIC/tqlQdM59atLVbUl94n/9Mi8qTNaPgdp+JNbm7iCBqsT5Pp4Ud
XP8Pfpp5Ljw6c5y0oRgmQiPfmCcT8s8RjKXA8f6L8A/p9bnspqAIond9Am+7XhvRYuhagipc0XvX
qPro7VWD8W7eRif6CrxfGYFBJ36YC7+jVT3dhbqrd8uIIF0WhQ+dvTCC7yoRwY3rgP+IPCsus0Dv
hckoeW4B5Zi906iyaA3n+TZIo/Nx1EkvPAfqCnlLHoVDAyuuM0zZxq4PM/8mZNebe6CG+uF/SpZV
ubMFQ1Wk0rsvLZXNr5Sozsgm5kAHQoA/670/SJLFt3lXrLhnoNr2agbPMxUJFkRJ0KdwNLbhh8Xn
IBjcbqzYHkaUYuV6oSqVS2v44vqODyYtXHOaWCTCFurt0hod0cqkxqbnKLJf3DxBI9YHrIJzn9VP
BGmoAIPLAIJVW+p/KgsmC+ESr4xRwAZkIDTn17Jw+JRuLk1B4MKZhGwEIimmjercLjdN1pE4vSud
LGG5GhGw4FwEWVNElxZv427TWyzbmpN/3kmqA1J4PFDLF4ermBMXvClZ1rrwrH0TKR0fuXcFyKOx
Z/JPCxFDSsok9zdm0AUasxYwUvHpQA0BX+Yq0BLG3NgmOmhnCEGi2xRFaRsP12jpJxCRFf0fG+KH
k4VYMbNCetn31Rdx26slXq4NzWl0IjO6I9uiYndG7Ikmi86c3+2wT2wS8rWT38SXGLX7sY4TSXeR
2JbOh9wdt/myM4wi0LzaDL82Pc5ZGou/BZxWRSi98UZnscH4SGZH5wnrBwJFCM3L4tUYwCLanGKn
ALMKv6XZannoPmbs3yJs1+NXhRmrUWDeUQPlRTSuq1qQ8WJ9XMIh7b58D3YaOtdkHseQorjl2esN
3eAJPwY0jaZZ4nO4lQBL3q8WLcQtU+UYwnH6jWrE+PxjrgYRp/rxIyFS3yUj2JC1thwMGe72QY8v
+OADQHHQqkf8/+FXS5ozJiPol+rxtJJy960mT5IY7yB0ZSk0NAkIyEYSeQASmr+coVZS5RfrDmr/
T48FORRVh6MgBQGWDaj7Mkr/ApLou+3sasfZii5gA5OCm1BBjFqYcsqfGSSo0N1X+U85Ld9/qAkI
a3A/lmvLwMSY/SVKy/G69t4JF63C41WNBUR0iP1FN+KRwR+rBIWZD9gqSE/0FmDmqOh8qWXoeM6W
LpZzICOQDDFLhFoiQuKKJBciqUflwluQ8I9DGl2Fvxg/WMGIvjX1cV3pxsIHwsFrbNRU8MwOUk3o
KM9f9OqqQzRFDbwzkhWwWssheEVBCrtovhlwEekwjSMmeDEtLkiIhtRvt4pvlcsyaTPJDRNKzL/M
soxvgNEqdwSEicK4YXzUBqkRykFhISfsDnhwMXpuOvDsIsXk2WEUDhL4NYsINBEDLcH0INfgJuuQ
rifozBDoWKK3Rs7I5RTYQXF5aHFpGngOuCjF6kEJ6WCc7B3Vt5I14giFLKT2DV+azN5tGAVr7ogh
fY0rAF5OoAnQLZrfEy18AwBmNeDEZ53n8oPChiT1ZWwecL9dj411syybXFAQt/pcy2j+GsZD06GP
8OYZW2wcs0Zk3+ykHfwEs/BPOz2robMgEhb4Ap9FETbfDCrH38S1kUI7GUm+RIOEQSSQcjLbylC8
0eF9CvOxrtb8DV8O/AYG4SjLV30Dc8qblyk8AyfLaJXj8OaBg2wjIHG5B0uIrZUUCWiHCp6Z+YtU
LbVPFDQUxEUnQYD6+DoucwzPuN04IIcOZ6U2zQ2mq/OUGzS5mf3CMxszdwlOrONjnN82ZP+QmbTd
mE3CRd2ndToDOo5o6XfX8ev+8GuO2EigBKWk3MakLQOFJLRPgcBHU8Df/nqdHLC9nOsvTePonod7
vl+lH+K7vEUGUQrs7zpZIXWjEUZ+9y2VAm/DKyS1kRcvO9MUhEEgLv4RON2aoe2v/EFBPPI1Qv5A
Ai3S56fZL1Z4ATQFp4V8yTerO1n9CZ9qKAxCrSjfmjm8CqFtu8Ti68slWtrj3HmHG0gEhqzbrNKM
wHYl3c2Lyd8KES9EIC9FEeZLcf4yv/hdUhnBFiCTBIftY3qvom5QC/PpnyWsKPHZ0eXrS5HNJguk
6BrACQkXkmvaQyiyGAKI7j05tlBpGtxmjlfJUdQm8qHZs/ynFTItN9tAH8TDXBNUPgzMTM7uBT1s
AcqQxTuCUDMHdt7P8gsjrpass1WLdU79fwhlgtJTk0Akeep9DCU2EawXuix60anS7/b7Y5L0Eyex
MsFuf0VQ1eQjrFVTFvaPbvJVDRIh6HL7wekWe8ShPA5or/cYlxR9ssTXgRdXYYF7Rj+K3Zma2vXc
njic6LJ/4BRzrAiVUCCxsDOuOaV+uvtKOHc1cZDlh9x807gR6MQQq8sP93tPDYtgmOMiJZlHZEo6
0jhu9lJbNRRMaDkmbgntAgCO68QNChnFHB8XzH7VW7N6i4kr4vAFquK+1R1dPbRSVyTGuyxDnOdS
bM0NK07S9pBKaqqTPSQn+qsy/YfMjVCEJ13TlkrCB+OGDuU+SaHV2/feG3liKKnvHtHAq9t+MTu5
VeACQeOaTkBdyo7656oV3sDhESf/icHJRH8KXWumGQroGicz0sJgd1n9TJfu7OIEwL/b/4PWOxRo
ICp3ukMOyr87zi2qIMK5oY20i9xkJfZ++DlJwZNuzlcZmp659D8tB/LZ37VMhShl9KxnRXo0Pm/7
0y/5C5fXiCiRBCFcm+al+5OBEc17R+G/BmZaQ/KnODgiJWfQbaBBgX+49OK9VT8SQ/zgJHoLy9M4
EHUaIskYmorBFyE4pdKOl6DhZ65hwpItF7y5D6JPHJ9d7zzIOGrLGGOzE/VRmcfs6EAvUugUfKfE
3LPme1ExLbPcHZag+Qr4ephl2UXjJZK2k/oUNnzSakZ57nk4uLppGRYlFP5iI/MvdW5tFHW00w6k
ot9lu5vPVkwWs4+iDmKylS4QRBOAcb8MoKPSZ+84M02lzTmZqsyDu3OHUIup/2NA1fH8uSKPGUqV
62uzLdJY9qoi23B1KDNWPjWHWFSLcsmompgOXvm/WkE9p1SjGUHilI/+b3CID9aXzxIAaCBfctA6
PFFb5WDY1MfYfOxOMQPMwPMSQR4EvCxgC3TaMvkoO8b2k95OZ2vYCLflEFUPfJLsQm0JW1aZxlhs
zHKL7VX0FocDTnn0zu3oRoQ5nRSA7i9JQtTbZHWmcQni9sJ2v+4Uqr/DObbEq949+zx3xFcaEPRQ
HtpGuZ7CO9nrVfefC/QhkKtjATSN1pfxFOPmaCf83aFRYpWKU+HT1UMjHbqW4ud7DrQHEPiBbghX
DgHn64ToLnAHaLyajtlvE9dEZNKPlQzaF8tOsmNjXWjOkAaUOLamjbsPA14h4Xty/FGlveeK7wZ5
3BCoO39g3XAQli0+L7iXwYAIwB9LEx6495kzzmQ5E+48Q4TCSZ+g/WylD9S+i5ZRHKib+NhMeDh0
TgrGabZ7tpZYY82SHw6Rm08zrqY34Opkyji+kBsX8swkgltaRWRKw+QxcZvRU3K7KNz+HVJORefL
7SPwjwR0QzEFuTsnUoZRREAKx5MXl8SnfuME9ypNwIcye55idvdLRWn1HsD0MF9Xh6d5/CEnCXeY
/uW6gsrN1iqKVpX+rTL2T0JQcKj+TyZ8jD8olITn/vU8GpXd/gltcjEGirMXUyAhuU1l0TtN02nm
6REK1SUbCPX7yqJqLWoQj8OGjmrWSzGNjN74JCeXv4AfXU8VQyGXG4YW+xainEflP/0qY/3bNw1+
1v/VtSNSLAETZwtnetnYBGosz3Nh6W7u9qiYBvmNKixmmdRNdWATPlXnd8Ml1dEbUSTMv0A9eCU7
mDLoXn/K6ttF/M1RkK0VGIu/9+afj3Z6gQ3xm1F989AVj+cIQZIa7aBQI84oc81b/BqB9hyKTvco
1bwtEZ2KA3H3EY7xH4l2dh953ETkCGZb8Z2cJSuBEaVuD+vQW1fhRFQLj7L7taQA2pjFjeB0VH8g
dutWwIlujE2k6wnTESV18iUh00+radmn/8iQ2F4I5N0QJ8jcCo/UwIUsjLkWCCTKIfBFD5CucTpg
Pm1f4JmWCSeR1hWVL/X1U02D5zNBiE8ySshY0SxLYPzf34chmDl1d+fTsCOEgPwbvEulMNZb4Rci
QPrAzC6NxWM9A21S3edgBniS3qSir/tP0hnPrcqEQOpqvie1HDB9C2Gv7XCu0eTF8Ff3rsaDKuKt
JV4Xwo7vLucr5qFh701uVpdxhUFNeRATaxrljAAIV9wuqQ5lIx9fdaLirHNGA869wg5lcTd/rT0W
DLNkk+zpcCQFUnz7CinCv+OTzbY5QCTSl2EwAOoqMtuy5VrTsmwpxNrDmvy3bxkQwSRVs9o7DAEr
coRLxqkmgYo5Haropd9kWr/1tj4eWUsz0JAZlq2ft1hTyNFtg8kxQ+6hyOYLZL/G5tyRdyHZYssf
OKq+5Du/4CgXvRGCfkeBYeC+jhRWioM0SGkAJpFVqpHZb8mGxh9hrama8rwpNfRwVPPJ1zzK6r4r
41JJl4mtSMK94WezK36ZFTgxY/d3gBpf/k2scR+fKVyTnmdf8oAHJxwaGtJ9z700QZQaNU15VkzM
pyypqkUte8RfmKGSlsm+cXvOAr4lFKFKzRuNCUX9AKhZxyrMAUcunfQX3KUIFG5lcaZ6z/e8BA2U
5s5TBhebAP7gN7IHAOwJBr60UaU2k+FMWoQMyXN5qLaYMD7EugRPIuPp6ZNNHEwUOc306XL6aQQy
ltLctDobQmCeMnDlol7c+h2hSMPRfdjrpSH1zw/PeRW1/LQBbwxDHfS7/2RXAfca3WE6y4xokn6O
h/AFYaxHYawL8Z1gU90Ne0Jy4v4pk9eoCOYgrkFX/etmEKJQxoFcJtpXSTbaL6K7NN8OnXJwc2CZ
UWISiW2eaGpXoNNvEiE1/fgjtESgJHbJoYw5W3sobOp85pMw3aOJg69/wpP0VMSDGcoMdztFzRuX
UVAXMDl3ie8zDeSkG/iIgY2t7OGl6OC3DPt+CIDnWdK9jZG6C3dcUiQ50k+myN1Zf7KcVoP3vrGi
vzcFuu26xMxQV3IrRnOVNHMflS2TQZhzpmvODAiDPiZyj5Rmbqn7aWGDh43LguwQK7IPKjrBMjY6
oLzs0KSfYOgwMnBDRtrRIdevHJbMMqWRt6R8AoTJK5gxdMZEG6nOnoPvdZD2YW6wjHGZ3IAhujsB
RgNp5Pcyg0Wugv7EQz+WK/v3jY6+TC7QTO6N3HKqmkBUMZgIlVJI2qglQgm3yCqmifMzmHf8MU0g
Miwv8bC1vh4vNtqV8crOWmjfN7jwGHwlgELqJXil7lhjdMh5CNa4mD/tDNBDuIynIGyE8iT+EPYl
Crsw9rpEvhB7guxvWE5ZoVBNd5HnOlQftkUGxAwet2u4OqHT+fzFEWx6C/dwdzkWru553w7QVk+8
t8xmO3yQ6DpITH/b0jeaKM3PyaXP/0KHvHIQOdNiuNy9goyN6gL3U2cc/5j+F7PVV/SPv+O6YSk7
8xe1h1W8Foi2s3Nc7vCH0H84oEkZ/85x+H+KAvam1Zx14H205Hybxmq3RKYkyvtfmH0QjgbxrMzC
LkLlRBrxefMg3ie8WsNi42si6zopkMMELsJDEUSjRW6TDEsXNl/bS6bDhvUFe0zSeW5w7BtvueK8
R7uDdtqSCrcWuPlhVnpCYW/EG/cut68TmgnTdVaotjZLJv6DQe6uXKX2Fvgr8uQXaj2Sc7ebvRAd
FCVZouH1KURd4a/0KJVkNnMf8VqYUV6aT0LHzHwYWL0RCCVOxyZy/+699DxoG+VTm9Ltzq78PtSW
aFpvlmZyq4d+a5DXyn3Hzp6RfTGpT2y0DKzWEIhfq69wc4VNNh7PUBz0qRjRnk1GRH8z9G5rU/kh
WuMoHa6U2e8GujvqjAtMMWA9CtsZjXKlLmbpr2SEQgFB/DBqyCUA9PpyiCwm5Awp2fO1ZPEACvGI
xvedH7jFNQepZRGXOChlRhzRlx2HVLVyp5s7GDBdsBK8RQsOvQdn/NvbAGHy3GWFsT2IvIvtEHmU
I/3aHs89+hOiE2Ru8MDWqEtlN9dSzcjavaM4Z+tvytDvZnJpzMYLNrDm3Ekw6iDEs7892C2ZULBB
G0ccl+dHE0iwMKbIv7axGJjYnDSSEaezaLU0ZtTRFH39alzK8pHcfp+hCesA+JSyNhR8dkoqNPEy
8y4KWKgTDCrwAUdKrQOA3S0/PZc9ynD3OKF022jlL15Uvsk+AUfN6K3qYt/ljUtghAuDNB3j3OsA
McafVo5QY7zb50BjXEZ6+DMitNYzX7xzAaVvv3mlOaGXYgSQSMTd4mPFtkdLjMEMrmA6u2DJMOn6
VPrMdjq4O4IiPputFLEEjbq7zJg6Ko6fkdZdcJqjB1Vn3+srHcnFo9OoMjipJ0jLOSrqhh8tIQZ8
dH5ye2xtUV+jKcnrru0vDVufrXU6GG7VhCdg6reWsOyv6XMP8ga/UHRNfGj6k5jJK/qm4HTArXOK
QrQYrq51pB1kGym2Db8sH28iIrxp9URdUD5FpjEYlxpFpCm75ki8q3HGGHMu8xdoXgoZbycETndd
U+KcDT0ac3PSh51e+gQMGB+wvvSHPOQhZH8va8PoT3P0MZ3T6+SR6jGAiS+9iOMpdk3a2pPZhZIS
54WkU6DgWxWGTfuRfpNd4LjJBRnGdlAFy0yG5zY9d3Y8h+w9d/3TjWir9mH3m21ZwELfaeLoaajg
TEvZslarivxfvYMoNQZdY2caxC9j/RKwqUVSN6CTg1u0ao+pnIqIarJcWxhX+U5H6dH3rMYlPl5e
a3AyqAN5lZxadAfabmKZ1YcYpEwojyzzM3z6ZZlCTxxWnstyjmdIJkxQ0VuYdw/eeVY//ThntbkZ
/yUaNhL+H3M0V49vHf9F8qf6U+O/sHsRrFe2KQcFiqXgf7FiY4OlUPZcOPRuo7DkLG1VCBUCd6sH
Elqi3B7ronFIjAwLyuoT2DiFVEgDITdNQEMNbfefnI0zTtLXuO2NFZnwC1RDQSJRJbd/tS27d7zh
YYBPFaw8OMa3ZXH6GjewiNXHJpuYOgtFBeHPylcGHpYK5aEl3MPvTzauy4qSbqjc+da53w/vhLjd
d9TZAINlDt6ZtklY3LF6z949sQlxf1aqq5yTx9nuNSMJBzQB03DK1PHDERRbbZIVjrvWGSxN9Wgx
eNMXQ9QeSmCPaayRoHW2MTjXk7G+Mwh6OEJ2VmXMUo5peyzmQDhSK6RcrIo4yxs66RUHOU8jr92r
z+rbDIqfYY15HNQo3pl6eVRhQXlbXgB65x3qrrctql2ZeByswFm/2ZB+hbMmPLdpLEIwLwYZr30H
vMAz52aDfVW1HfYd4w0tZAZzFffpaVPTezpP28jk0ANxpMwK0CBgJVoVAQBQdjsFXsgi5k7mVYpf
o9abQNjg82puHEYgpK44cRZJHlKUgYr8FJaaVTJ4264GP29YOYjK7hBODyKljovt/0Rn1yBe5I5I
UL4H+O1PNACEyhp8Fxa/DFnTlykNHVTEFIrv4BjpHVCiQuvBjVqtlc3BDXm//c1hmtjni/a3Xhxm
w+SVx+RNwa9Kk1P7y1y/gwhRHFskYsJBtXRiSuYDcS7Ow9laqcdAytPjfYyxXvC/NDrqsJYGNUVQ
823hdkXvQzuIuCFGSZ3nOgk8Tn0fs1xAocO0v2QlAikGLpx1xRc4g+RtcLkhp2LIkP664z0+9IgY
IB6lEdDMnjYfdattj1T/ArR59FaEj/nyusuMTY3egk1VKDDPVTWEPwpyi2h1RvFPSv23Bi7fm0dG
Y7hBzOUTuzE8+xjNUDW5kuQ2w9/Waqss4o26p6bvo60c0ENfidBOpMBJqBZCYHJmxlHNiseVrJpv
C/dFPnUdRGUbmrdPlba/+Ez4gikk2Hn4/dE6o0L0ZeWCgiEACLji6mlnNtmPci9zCl7D6LU8pcof
J9A/dQPFKsN/kTIiseEooDgQh7EnWzz6kDoNZa8c/fmiUxIhHSISCoRwCSRmqLE7Q4oRoyZ2CO3R
omVwHsqU8dxSIupMGkXbkK5B5aS9VqWZy7iemvFUaZZrKNn1UZEjOL0ITBnNbI3UO7TVTsW7cOpn
TPiLDn1ViKF8tXACtkx3uvblRcj3OumEosj4gPLr4FVGDJCMq87ol2Qd0u5P81niwFnl9KOMN6jY
AGz33GgcRe5RJOgc5g6IcM+EZMSwSHDLlx4NEJFiCXJtlMOdRzMj3mK8WVktlrEeg6+ZxJ5qcU+h
K9PlXH6cjatLb00ltBctPzRHFQifzdi7y0DEU8jizCn8da0=
`protect end_protected
| mit |
okaxaki/vm2413 | AttackTable.vhd | 2 | 2045 | --
-- AttackTable.vhd
-- Envelope attack shaping table for VM2413
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity AttackTable is
port (
clk : in std_logic;
addr : in integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
data : out DB_TYPE
);
end AttackTable;
architecture RTL of AttackTable is
type AR_ADJUST_ARRAY is array (addr'range) of DB_TYPE;
constant ar_adjust : AR_ADJUST_ARRAY :=(
"1111111","1111111","1101100","1100010","1011010","1010100","1010000","1001011",
"1001000","1000101","1000010","1000000","0111101","0111011","0111001","0111000",
"0110110","0110100","0110011","0110001","0110000","0101111","0101101","0101100",
"0101011","0101010","0101001","0101000","0100111","0100110","0100101","0100100",
"0100100","0100011","0100010","0100001","0100001","0100000","0011111","0011110",
"0011110","0011101","0011101","0011100","0011011","0011011","0011010","0011010",
"0011001","0011000","0011000","0010111","0010111","0010110","0010110","0010101",
"0010101","0010101","0010100","0010100","0010011","0010011","0010010","0010010",
"0010001","0010001","0010001","0010000","0010000","0001111","0001111","0001111",
"0001110","0001110","0001110","0001101","0001101","0001101","0001100","0001100",
"0001100","0001011","0001011","0001011","0001010","0001010","0001010","0001001",
"0001001","0001001","0001001","0001000","0001000","0001000","0000111","0000111",
"0000111","0000111","0000110","0000110","0000110","0000110","0000101","0000101",
"0000101","0000100","0000100","0000100","0000100","0000100","0000011","0000011",
"0000011","0000011","0000010","0000010","0000010","0000010","0000001","0000001",
"0000001","0000001","0000001","0000000","0000000","0000000","0000000","0000000"
);
begin
process (clk)
begin
if clk'event and clk = '1' then
data <= ar_adjust(addr'high - addr);
end if;
end process;
end RTL; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sImpulsen1Altr.vhd | 8 | 3102 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsen1Altr is
generic (
Impulsedelay : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsen1Altr ;
architecture syn of alt_dspbuilder_sImpulsen1Altr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
end if;
end if;
end process;
cp:process(count, current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
elsif (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_clock.vhd | 10 | 2158 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNCGUFKHRR;
begin
alt_dspbuilder_testbench_clock_GNCGUFKHRR_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "20 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNCGUFKHRR_0: alt_dspbuilder_testbench_clock_GNCGUFKHRR
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "20 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "20 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_testbench_clock.vhd | 10 | 2218 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/Instruct_Memory/simulation/checker.vhd | 69 | 5607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_capture_GNQX2JTRTZ.vhd | 20 | 1755 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_pipelined_adder_GNWEIMU3MK.vhd | 8 | 1300 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
signal cin_internal : std_logic;
Begin
cin_internal <= '1';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '0' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_cast_GNCCZ56SYK.vhd | 4 | 855 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNCCZ56SYK.vhd | 4 | 855 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture; | mit |
Bourgeoisie/ECE368-RISC16 | 368RISC/Data Path/Fetch/fetch_tb.vhd | 1 | 2984 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:39:38 04/22/2015
-- Design Name:
-- Module Name: U:/Desktop/ECE368-RISC16-master/368RISC/fetch_tb.vhd
-- Project Name: RISC16
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fetch_struct
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fetch_tb IS
END fetch_tb;
ARCHITECTURE behavior OF fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fetch_struct
PORT(
clk : IN std_logic;
rst : IN std_logic;
PC_En : IN std_logic;
pc_out : OUT std_logic_vector(4 downto 0);
OPcode_out: OUT std_logic_vector(3 downto 0);
ADRS_A : OUT std_logic_vector(3 downto 0);
ADRS_B : OUT std_logic_vector(3 downto 0);
ADRS_IMM : OUT std_logic_vector(3 downto 0);
Instruction_out : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal PC_En : std_logic := '0';
--Outputs
signal pc_out : std_logic_vector(4 downto 0);
signal OPcode_out: std_logic_vector(3 downto 0);
signal ADRS_A : std_logic_vector(3 downto 0);
signal ADRS_B : std_logic_vector(3 downto 0);
signal ADRS_IMM : std_logic_vector(3 downto 0);
signal Instruction_out : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fetch_struct PORT MAP (
clk => clk,
rst => rst,
PC_En => PC_En,
pc_out => pc_out,
OPcode_out => OPcOdE_oUt,
ADRS_A => ADRS_A,
ADRS_B => ADRS_B,
ADRS_IMM => ADRS_IMM,
Instruction_out => Instruction_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
PC_En <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_decoder.vhd | 2 | 2462 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
DECODE : string := "10";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNEQGKKPXW_0: if ((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNEQGKKPXW_0: alt_dspbuilder_decoder_GNEQGKKPXW
generic map(DECODE => "10", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNM4LOIHXZ_1: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_1: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) or ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_dividerAltr.vhd | 4 | 4072 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_dividerAltr is
generic (
widthin : natural :=8;
pipeline : natural :=0;
isunsigned : natural :=0
);
port
(
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end alt_dspbuilder_dividerAltr;
architecture syn of alt_dspbuilder_dividerAltr is
signal svcc : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
svcc <='1';
gsgn: if (isunsigned=0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
clken => clken,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gsgn;
gugn: if (isunsigned>0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
clken => svcc,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gugn;
end syn;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_if_statement_GNJ7D74ANQ.vhd | 4 | 1401 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNJ7D74ANQ is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_MultAdd.vhd | 12 | 23128 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_constant_GNLJWFEWBD.vhd | 5 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNLJWFEWBD is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000011";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNLJWFEWBD is
Begin
-- Constant
output <= "0000000000000011";
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_constant_GNLJWFEWBD.vhd | 5 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNLJWFEWBD is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000011";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNLJWFEWBD is
Begin
-- Constant
output <= "0000000000000011";
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd | 2 | 45577 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
sop : out std_logic; -- sop.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
data : out std_logic_vector(24 downto 0); -- data.wire
data_en : in std_logic := '0'; -- data_en.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
eop : out std_logic; -- eop.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GN33BXJAZX is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN33BXJAZX;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNWMX2GCN2;
component alt_dspbuilder_case_statement_GNFTM45DFU is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNFTM45DFU;
component alt_dspbuilder_multiplexer_GNLGLCKYZ5 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in3 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNLGLCKYZ5;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN6E6AAQPZ;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_delay_GNIYBMGPQQ is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNIYBMGPQQ;
component alt_dspbuilder_constant_GNLJWFEWBD is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLJWFEWBD;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_if_statement_GNTVBNRAAT is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNTVBNRAAT;
component alt_dspbuilder_delay_GNNBTO2F3L is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNNBTO2F3L;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNHQFFAUXQ;
component alt_dspbuilder_multiplexer_GN6ODCX3D4 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GN6ODCX3D4;
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
component alt_dspbuilder_cast_GN3ODVPHOL is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN3ODVPHOL;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKDE2NVCC is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKDE2NVCC;
component alt_dspbuilder_cast_GNCCZ56SYK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCCZ56SYK;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder2user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder2user_aclrGND:output -> Pipelined_Adder2:user_aclr
signal pipelined_adder2enavcc_output_wire : std_logic; -- Pipelined_Adder2enaVCC:output -> Pipelined_Adder2:ena
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal delaysclrgnd_output_wire : std_logic; -- DelaysclrGND:output -> Delay:sclr
signal delayenavcc_output_wire : std_logic; -- DelayenaVCC:output -> Delay:ena
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay5enavcc_output_wire : std_logic; -- Delay5enaVCC:output -> Delay5:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay3enavcc_output_wire : std_logic; -- Delay3enaVCC:output -> Delay3:ena
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [Bus_Conversion1:input, If_Statement7:a, cast29:input, cast32:input]
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Delay:input
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Delay1:input
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Delay2:input
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Delay3:input
signal constant7_output_wire : std_logic_vector(23 downto 0); -- Constant7:output -> Delay5:input
signal if_statement7_true_wire : std_logic; -- If_Statement7:true -> [Logical_Bit_Operator10:data0, Logical_Bit_Operator9:data1]
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator10:data1, Logical_Bit_Operator3:data1, cast34:input]
signal case_statement2_r1_wire : std_logic; -- Case_Statement2:r1 -> Logical_Bit_Operator3:data0
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> [Logical_Bit_Operator4:data0, Logical_Bit_Operator9:data0, cast33:input]
signal case_statement2_r0_wire : std_logic; -- Case_Statement2:r0 -> Logical_Bit_Operator4:data1
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Logical_Bit_Operator5:data0
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Logical_Bit_Operator5:data1
signal logical_bit_operator10_result_wire : std_logic; -- Logical_Bit_Operator10:result -> Logical_Bit_Operator6:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Logical_Bit_Operator6:data0
signal bus_conversion1_output_wire : std_logic_vector(1 downto 0); -- Bus_Conversion1:output -> Multiplexer:sel
signal delay_output_wire : std_logic_vector(23 downto 0); -- Delay:output -> Multiplexer:in0
signal delay1_output_wire : std_logic_vector(23 downto 0); -- Delay1:output -> Multiplexer:in1
signal delay2_output_wire : std_logic_vector(23 downto 0); -- Delay2:output -> Multiplexer:in2
signal delay3_output_wire : std_logic_vector(23 downto 0); -- Delay3:output -> Multiplexer:in3
signal bus_concatenation_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation:output -> Multiplexer1:sel
signal bus_concatenation1_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation1:output -> Multiplexer2:sel
signal multiplexer2_result_wire : std_logic_vector(24 downto 0); -- Multiplexer2:result -> Multiplexer1:in1
signal constant18_output_wire : std_logic_vector(23 downto 0); -- Constant18:output -> Pipelined_Adder2:datab
signal pipelined_adder2_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder2:result -> If_Statement7:c
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> sop_0:input
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> eop_0:input
signal multiplexer1_result_wire : std_logic_vector(24 downto 0); -- Multiplexer1:result -> data_0:input
signal cast29_output_wire : std_logic_vector(15 downto 0); -- cast29:output -> Case_Statement1:input
signal case_statement1_r0_wire : std_logic; -- Case_Statement1:r0 -> cast30:input
signal cast30_output_wire : std_logic_vector(0 downto 0); -- cast30:output -> Bus_Concatenation1:a
signal case_statement1_r1_wire : std_logic; -- Case_Statement1:r1 -> cast31:input
signal cast31_output_wire : std_logic_vector(0 downto 0); -- cast31:output -> Bus_Concatenation1:b
signal cast32_output_wire : std_logic_vector(15 downto 0); -- cast32:output -> Case_Statement2:input
signal cast33_output_wire : std_logic_vector(0 downto 0); -- cast33:output -> Bus_Concatenation:a
signal cast34_output_wire : std_logic_vector(0 downto 0); -- cast34:output -> Bus_Concatenation:b
signal constant16_output_wire : std_logic_vector(15 downto 0); -- Constant16:output -> cast35:input
signal cast35_output_wire : std_logic_vector(23 downto 0); -- cast35:output -> If_Statement7:b
signal constant5_output_wire : std_logic_vector(23 downto 0); -- Constant5:output -> cast36:input
signal cast36_output_wire : std_logic_vector(24 downto 0); -- cast36:output -> Multiplexer1:in0
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> cast37:input
signal cast37_output_wire : std_logic_vector(24 downto 0); -- cast37:output -> Multiplexer1:in2
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> cast38:input
signal cast38_output_wire : std_logic_vector(24 downto 0); -- cast38:output -> Multiplexer2:in0
signal delay5_output_wire : std_logic_vector(23 downto 0); -- Delay5:output -> cast39:input
signal cast39_output_wire : std_logic_vector(24 downto 0); -- cast39:output -> Multiplexer2:in1
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast40:input
signal cast40_output_wire : std_logic_vector(23 downto 0); -- cast40:output -> Pipelined_Adder2:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Case_Statement1:aclr, Case_Statement2:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay5:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Pipelined_Adder2:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation1:clock, Bus_Concatenation:clock, Case_Statement1:clock, Case_Statement2:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay5:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Pipelined_Adder2:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GN33BXJAZX
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
pipelined_adder2 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast40_output_wire, -- dataa.wire
datab => constant18_output_wire, -- datab.wire
result => pipelined_adder2_result_wire, -- result.wire
user_aclr => pipelined_adder2user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder2enavcc_output_wire -- ena.wire
);
pipelined_adder2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder2user_aclrgnd_output_wire -- output.wire
);
pipelined_adder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder2enavcc_output_wire -- output.wire
);
case_statement1 : component alt_dspbuilder_case_statement_GNWMX2GCN2
generic map (
number_outputs => 2,
hasDefault => 1,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast29_output_wire, -- input.wire
r0 => case_statement1_r0_wire, -- r0.wire
r1 => case_statement1_r1_wire -- r1.wire
);
case_statement2 : component alt_dspbuilder_case_statement_GNFTM45DFU
generic map (
number_outputs => 2,
hasDefault => 0,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast32_output_wire, -- input.wire
r0 => case_statement2_r0_wire, -- r0.wire
r1 => case_statement2_r1_wire -- r1.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNLGLCKYZ5
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_conversion1_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => delay_output_wire, -- in0.wire
in1 => delay1_output_wire, -- in1.wire
in2 => delay2_output_wire, -- in2.wire
in3 => delay3_output_wire -- in3.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => multiplexer1_result_wire, -- input.wire
output => data -- output.wire
);
constant7 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant7_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant5_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast30_output_wire, -- a.wire
b => cast31_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => logical_bit_operator9_result_wire, -- data0.wire
data1 => logical_bit_operator10_result_wire -- data1.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => logical_bit_operator4_result_wire, -- data0.wire
data1 => logical_bit_operator3_result_wire -- data1.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => case_statement2_r0_wire -- data1.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast33_output_wire, -- a.wire
b => cast34_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => if_statement7_true_wire -- data1.wire
);
constant1 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNIYBMGPQQ
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000001111",
width => 24
)
port map (
input => constant1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => delaysclrgnd_output_wire, -- sclr.wire
ena => delayenavcc_output_wire -- ena.wire
);
delaysclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delaysclrgnd_output_wire -- output.wire
);
delayenavcc : component alt_dspbuilder_vcc_GN
port map (
output => delayenavcc_output_wire -- output.wire
);
constant16 : component alt_dspbuilder_constant_GNLJWFEWBD
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000011",
width => 16
)
port map (
output => constant16_output_wire -- output.wire
);
constant18 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant18_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => case_statement2_r1_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator6_result_wire, -- input.wire
output => eop -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
if_statement7 : component alt_dspbuilder_if_statement_GNTVBNRAAT
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement7_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast35_output_wire, -- b.wire
c => pipelined_adder2_result_wire -- c.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => constant7_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => delay5enavcc_output_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay5enavcc_output_wire -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak3_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => delay3enavcc_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay3enavcc_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator5_result_wire, -- input.wire
output => sop -- output.wire
);
logical_bit_operator10 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator10_result_wire, -- result.wire
data0 => if_statement7_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNHQFFAUXQ
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 25,
pipeline => 0,
number_inputs => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast36_output_wire, -- in0.wire
in1 => multiplexer2_result_wire, -- in1.wire
in2 => cast37_output_wire -- in2.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak1_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GN6ODCX3D4
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 1,
width => 25,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation1_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast38_output_wire, -- in0.wire
in1 => cast39_output_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVJUPFOX3
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000000",
width => 24
)
port map (
input => ctrl_pak2_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
cast29 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast29_output_wire -- output.wire
);
cast30 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r0_wire, -- input.wire
output => cast30_output_wire -- output.wire
);
cast31 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r1_wire, -- input.wire
output => cast31_output_wire -- output.wire
);
cast32 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast32_output_wire -- output.wire
);
cast33 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => ctrl_en_0_output_wire, -- input.wire
output => cast33_output_wire -- output.wire
);
cast34 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_en_0_output_wire, -- input.wire
output => cast34_output_wire -- output.wire
);
cast35 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant16_output_wire, -- input.wire
output => cast35_output_wire -- output.wire
);
cast36 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => constant5_output_wire, -- input.wire
output => cast36_output_wire -- output.wire
);
cast37 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplexer_result_wire, -- input.wire
output => cast37_output_wire -- output.wire
);
cast38 : component alt_dspbuilder_cast_GNCCZ56SYK
generic map (
round => 0,
saturate => 0
)
port map (
input => colorbar_0_output_wire, -- input.wire
output => cast38_output_wire -- output.wire
);
cast39 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => cast39_output_wire -- output.wire
);
cast40 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast40_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNCPEUNC4M.vhd | 5 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCPEUNC4M is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCPEUNC4M is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 16 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_sImpulse1nAltr.vhd | 8 | 2837 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulse1nAltr is
generic (
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulse1nAltr ;
architecture syn of alt_dspbuilder_sImpulse1nAltr is
type States_ImpulseAltr is (sclear, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
begin
rp:process(clock,aclr)
begin
if aclr='1' then
current_state <= sclear;
count <= (others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
current_state <= sclear;
count <= (others=>'0');
elsif (ena='1') then
current_state <= next_state;
count <= count+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end process;
cp:process(count,current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= shigh;
else
next_state <= sclear;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsewidth,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_constant_GNZEH3JAKA.vhd | 20 | 592 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNZEH3JAKA is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000001111";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNZEH3JAKA is
Begin
-- Constant
output <= "000000000000000000001111";
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_vcc_GN.vhd | 20 | 373 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_vcc_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_vcc_GN is
Begin
output <= '1';
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_port_GNEPKLLZKY.vhd | 17 | 489 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_if_statement_GNWHMBR6GA.vhd | 4 | 1493 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNWHMBR6GA is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>zero) and (a<b)) or (a=c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNWHMBR6GA is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>zero) and (a<b)) or (a=c)) ;
true <= result;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNMMXHT3UH.vhd | 4 | 852 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMMXHT3UH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMMXHT3UH is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 ,
width_inr=> 0,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(3 downto 0) => input,
yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd | 2 | 34606 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
data_en : in std_logic := '0'; -- data_en.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
colorbar : out std_logic_vector(23 downto 0); -- colorbar.wire
counter : in std_logic_vector(23 downto 0) := (others => '0') -- counter.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_bus_build_GNI6E4JZ66 is
generic (
width : natural := 8
);
port (
output : out std_logic_vector(2 downto 0); -- wire
in0 : in std_logic := 'X'; -- wire
in1 : in std_logic := 'X'; -- wire
in2 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_bus_build_GNI6E4JZ66;
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
Signed : natural := 0;
width : natural := 8;
pipeline : natural := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
denom : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
numer : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
quotient : out std_logic_vector(width-1 downto 0); -- wire
remain : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNJ7D74ANQ;
component alt_dspbuilder_constant_GNKT7L5CDY is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNKT7L5CDY;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_if_statement_GNMQPB5LUF is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNMQPB5LUF;
component alt_dspbuilder_if_statement_GNZR777PB6 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNZR777PB6;
component alt_dspbuilder_constant_GNUWBUDS4L is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNUWBUDS4L;
component alt_dspbuilder_constant_GNJ2DIDH6N is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNJ2DIDH6N;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_constant_GNNCFWNIJI is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNCFWNIJI;
component alt_dspbuilder_if_statement_GNWHMBR6GA is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNWHMBR6GA;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component StateMachineEditor1 is
port (
clock : in std_logic := 'X'; -- clk
col_select : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
data : out std_logic_vector(23 downto 0); -- wire
data_en : in std_logic := 'X'; -- wire
reset : in std_logic := 'X' -- wire
);
end component StateMachineEditor1;
component alt_dspbuilder_counter_GNZKRIGTBB is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNZKRIGTBB;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GNLHWQIRQK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLHWQIRQK;
signal pipelined_adder3user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder3user_aclrGND:output -> Pipelined_Adder3:user_aclr
signal pipelined_adder3enavcc_output_wire : std_logic; -- Pipelined_Adder3enaVCC:output -> Pipelined_Adder3:ena
signal divideruser_aclrgnd_output_wire : std_logic; -- Divideruser_aclrGND:output -> Divider:user_aclr
signal dividerenavcc_output_wire : std_logic; -- DividerenaVCC:output -> Divider:ena
signal single_pulse1sclrgnd_output_wire : std_logic; -- Single_Pulse1sclrGND:output -> Single_Pulse1:sclr
signal single_pulse1enavcc_output_wire : std_logic; -- Single_Pulse1enaVCC:output -> Single_Pulse1:ena
signal multiplieruser_aclrgnd_output_wire : std_logic; -- Multiplieruser_aclrGND:output -> Multiplier:user_aclr
signal multiplierenavcc_output_wire : std_logic; -- MultiplierenaVCC:output -> Multiplier:ena
signal constant9_output_wire : std_logic_vector(23 downto 0); -- Constant9:output -> Counter1:data
signal constant8_output_wire : std_logic_vector(23 downto 0); -- Constant8:output -> Divider:denom
signal counter1_q_wire : std_logic_vector(23 downto 0); -- Counter1:q -> [If_Statement1:a, If_Statement2:a, If_Statement3:a, If_Statement:a]
signal divider_quotient_wire : std_logic_vector(23 downto 0); -- Divider:quotient -> [If_Statement1:b, If_Statement:b, Multiplier:dataa]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Bus_Builder:in0
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Bus_Builder:in1
signal if_statement2_true_wire : std_logic; -- If_Statement2:true -> Bus_Builder:in2
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> If_Statement5:a
signal if_statement3_true_wire : std_logic; -- If_Statement3:true -> Logical_Bit_Operator12:data0
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator12:data1, Logical_Bit_Operator8:data0, State_Machine_Editor1:data_en]
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> Logical_Bit_Operator7:data0
signal logical_bit_operator12_result_wire : std_logic; -- Logical_Bit_Operator12:result -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Counter1:sload
signal if_statement5_true_wire : std_logic; -- If_Statement5:true -> Logical_Bit_Operator8:data1
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Counter1:cnt_ena
signal constant6_output_wire : std_logic_vector(23 downto 0); -- Constant6:output -> Multiplier:datab
signal constant13_output_wire : std_logic_vector(23 downto 0); -- Constant13:output -> Pipelined_Adder3:datab
signal pipelined_adder3_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder3:result -> If_Statement2:c
signal single_pulse1_result_wire : std_logic; -- Single_Pulse1:result -> State_Machine_Editor1:reset
signal state_machine_editor1_data_wire : std_logic_vector(23 downto 0); -- State_Machine_Editor1:data -> colorbar_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> [cast0:input, cast1:input, cast2:input, cast6:input]
signal cast0_output_wire : std_logic_vector(23 downto 0); -- cast0:output -> Divider:numer
signal cast1_output_wire : std_logic_vector(23 downto 0); -- cast1:output -> If_Statement:c
signal cast2_output_wire : std_logic_vector(23 downto 0); -- cast2:output -> If_Statement3:b
signal constant11_output_wire : std_logic_vector(15 downto 0); -- Constant11:output -> cast3:input
signal cast3_output_wire : std_logic_vector(23 downto 0); -- cast3:output -> If_Statement5:b
signal multiplier_result_wire : std_logic_vector(47 downto 0); -- Multiplier:result -> [cast4:input, cast5:input]
signal cast4_output_wire : std_logic_vector(23 downto 0); -- cast4:output -> If_Statement1:c
signal cast5_output_wire : std_logic_vector(23 downto 0); -- cast5:output -> If_Statement2:b
signal cast6_output_wire : std_logic_vector(23 downto 0); -- cast6:output -> Pipelined_Adder3:dataa
signal bus_builder_output_wire : std_logic_vector(2 downto 0); -- Bus_Builder:output -> cast7:input
signal cast7_output_wire : std_logic_vector(2 downto 0); -- cast7:output -> State_Machine_Editor1:col_select
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter1:aclr, Divider:aclr, Multiplier:aclr, Pipelined_Adder3:aclr, Single_Pulse1:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter1:clock, Divider:clock, Multiplier:clock, Pipelined_Adder3:clock, Single_Pulse1:clock, State_Machine_Editor1:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
pipelined_adder3 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast6_output_wire, -- dataa.wire
datab => constant13_output_wire, -- datab.wire
result => pipelined_adder3_result_wire, -- result.wire
user_aclr => pipelined_adder3user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder3enavcc_output_wire -- ena.wire
);
pipelined_adder3user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder3user_aclrgnd_output_wire -- output.wire
);
pipelined_adder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder3enavcc_output_wire -- output.wire
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
bus_builder : component alt_dspbuilder_bus_build_GNI6E4JZ66
generic map (
width => 3
)
port map (
output => bus_builder_output_wire, -- output.wire
in0 => if_statement_true_wire, -- in0.wire
in1 => if_statement1_true_wire, -- in1.wire
in2 => if_statement2_true_wire -- in2.wire
);
divider : component alt_dspbuilder_divider_GNKAPZN5MO
generic map (
Signed => 0,
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
numer => cast0_output_wire, -- numer.wire
denom => constant8_output_wire, -- denom.wire
quotient => divider_quotient_wire, -- quotient.wire
remain => open, -- remain.wire
user_aclr => divideruser_aclrgnd_output_wire, -- user_aclr.wire
ena => dividerenavcc_output_wire -- ena.wire
);
divideruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => divideruser_aclrgnd_output_wire -- output.wire
);
dividerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => dividerenavcc_output_wire -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => state_machine_editor1_data_wire, -- input.wire
output => colorbar -- output.wire
);
if_statement5 : component alt_dspbuilder_if_statement_GNJ7D74ANQ
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement5_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast3_output_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
constant6 : component alt_dspbuilder_constant_GNKT7L5CDY
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000010",
width => 24
)
port map (
output => constant6_output_wire -- output.wire
);
if_statement3 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement3_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast2_output_wire -- b.wire
);
logical_bit_operator12 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator12_result_wire, -- result.wire
data0 => if_statement3_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
if_statement2 : component alt_dspbuilder_if_statement_GNMQPB5LUF
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and ((a<c) or (a=c))",
number_inputs => 3,
width => 24
)
port map (
true => if_statement2_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast5_output_wire, -- b.wire
c => pipelined_adder3_result_wire -- c.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GNZR777PB6
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and (a<c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast4_output_wire -- c.wire
);
constant8 : component alt_dspbuilder_constant_GNUWBUDS4L
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000011",
width => 24
)
port map (
output => constant8_output_wire -- output.wire
);
constant9 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant9_output_wire -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => logical_bit_operator12_result_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
constant11 : component alt_dspbuilder_constant_GNNCFWNIJI
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000100",
width => 16
)
port map (
output => constant11_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNWHMBR6GA
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>zero) and (a<b)) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast1_output_wire -- c.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
constant13 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant13_output_wire -- output.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => data_en_0_output_wire, -- data0.wire
data1 => if_statement5_true_wire -- data1.wire
);
single_pulse1 : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse1_result_wire, -- result.wire
sclr => single_pulse1sclrgnd_output_wire, -- sclr.wire
ena => single_pulse1enavcc_output_wire -- ena.wire
);
single_pulse1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulse1sclrgnd_output_wire -- output.wire
);
single_pulse1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulse1enavcc_output_wire -- output.wire
);
state_machine_editor1 : component StateMachineEditor1
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse1_result_wire, -- reset.wire
col_select => cast7_output_wire, -- col_select.wire
data_en => data_en_0_output_wire, -- data_en.wire
data => state_machine_editor1_data_wire -- data.wire
);
counter1 : component alt_dspbuilder_counter_GNZKRIGTBB
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "true",
use_sclr => "false",
use_cout => "false",
modulus => 65536,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => constant9_output_wire, -- data.wire
cnt_ena => logical_bit_operator8_result_wire, -- cnt_ena.wire
sload => logical_bit_operator7_result_wire, -- sload.wire
q => counter1_q_wire, -- q.wire
cout => open -- cout.wire
);
multiplier : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => divider_quotient_wire, -- dataa.wire
datab => constant6_output_wire, -- datab.wire
result => multiplier_result_wire, -- result.wire
user_aclr => multiplieruser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplierenavcc_output_wire -- ena.wire
);
multiplieruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplieruser_aclrgnd_output_wire -- output.wire
);
multiplierenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplierenavcc_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant11_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
cast6 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast6_output_wire -- output.wire
);
cast7 : component alt_dspbuilder_cast_GNLHWQIRQK
generic map (
round => 0,
saturate => 0
)
port map (
input => bus_builder_output_wire, -- input.wire
output => cast7_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator.vhd | 2 | 2091 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Test_Pattern_Generator is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Test_Pattern_Generator;
architecture rtl of Test_Pattern_Generator is
component Test_Pattern_Generator_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Test_Pattern_Generator_GN;
begin
Test_Pattern_Generator_GN_0: if true generate
inst_Test_Pattern_Generator_GN_0: Test_Pattern_Generator_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_case_statement_GNWMX2GCN2.vhd | 4 | 837 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic ( number_outputs : integer := 2;
hasDefault : natural := 1;
pipeline : natural := 0;
width : integer := 16);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(15 downto 0);
r0 : out std_logic;
r1 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GNWMX2GCN2 is
begin
caseproc:process( input )
begin
case input is
when "0000000000000100" =>
r0 <= '1';
r1 <= '0';
when others =>
r0 <= '0';
r1 <= '1';
end case;
end process;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_counter_GNKAA2ZBZG.vhd | 4 | 1632 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_counter_GNKAA2ZBZG is
generic ( use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "1";
use_sload : string := "false";
use_sclr : string := "true";
use_cout : string := "false";
modulus : integer := 8388608;
use_cnt_ena : string := "true";
width : natural := 24;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0");
port(
aclr : in std_logic;
aload : in std_logic;
aset : in std_logic;
cin : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
data : in std_logic_vector((width)-1 downto 0);
direction : in std_logic;
ena : in std_logic;
q : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic;
sload : in std_logic;
sset : in std_logic;
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_counter_GNKAA2ZBZG is
Begin
-- DSP Builder Block - Simulink Block "Counter"
Counteri : lpm_counter Generic map (
LPM_WIDTH => 24,
LPM_DIRECTION => "UP",
LPM_MODULUS => 8388608,
LPM_AVALUE => "0",
LPM_SVALUE => "1",
LPM_TYPE => "LPM_COUNTER"
)
port map (
clock => clock,
cnt_en => cnt_ena,
aclr => aclr,
sclr => sclr,
q => q);
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_decoder.vhd | 2 | 1567 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(2-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNM4LOIHXZ_0: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_0: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |