instruction stringlengths 48 119 | output stringlengths 40 5.63k |
|---|---|
Build a low-pass RC filter with 4.7Meg resistor and 10n capacitor and run AC analysis. | *Low-Pass RC Filter
V1 IN 0 AC 1 DC 1.8V
R1 IN OUT 4.7Meg
C1 OUT 0 10n
.AC DEC 100 1 10Meg
.END |
Design a voltage divider using resistors and provide the SPICE netlist. | * Z:\mnt\design.r\spice\examples\AD8236.asc
XU1 N004 N003 N002 N001 0 N005 OUT +V AD8236
Vcm N004 0 2.5
Vref N005 0 2.5
V1 +V 0 5
Rload OUT 0 10K
Vdiff N001 N004 SINE(0 .1 1K)
Rgain N002 N003 84.5K
.tran 100m
.lib ADI1.lib
.backanno
.end |
Design an n-channel MOSFET current mirror with W=1u, L=2u devices. | *NMOS Current Mirror
V1 VDD 0 DC 3.3V
R1 VDD REF 6.8k
M1 REF REF 0 0 NMOS W=1u L=2u
M2 OUT REF 0 0 NMOS W=1u L=2u
RL OUT 0 4.7k
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02 GAMMA=0.5 PHI=0.6)
.OP
.END |
Build a bridge rectifier with DC load resistor 470k and filter capacitor. | *Full-Wave Bridge Rectifier
V1 AC+ AC- SIN(0 12.0V 50)
D1 AC+ OUT D1N4148
D2 GND AC+ D1N4148
D3 AC- OUT D1N4148
D4 GND AC- D1N4148
R1 OUT GND 470k
C1 OUT GND 220n
.MODEL D1N4148 D (IS=2.52n RS=16.6 N=1.752 CJO=4p M=0.333 VJ=0.7 BV=100 IBV=100u)
.TRAN 100u 200m
.END |
Build an RC circuit that differentiates a square wave input. | *RC Differentiator
V1 IN 0 PULSE(0 9.0V 0 1n 1n 500u 1m)
C1 IN OUT 22u
R1 OUT 0 1.5Meg
.TRAN 1u 5m
.END |
Write a SPICE netlist for a basic RC charging circuit. | * Z:\mnt\design.r\spice\examples\1726-2.5.asc
V4 N007 0 5
R3 N007 N006 10K
C1 N005 0 47n
C2 N008 0 47n
R1 N001 N004 66.5K
R2 N004 0 100K
XU1 N002 N003 N004 0 N009 N006 N008 N005 LTC1726-2.5
V2 N002 0 PWL(0 0 250m 3.3 3 3.3 3.5 0 4 0 4.5 3.3 100 3.3)
V3 N003 0 PWL(0 0 350m 2.5 1 2.5 1.5 0 2 0 2.5 2.5 100 2.5)
V6 N009 0 ... |
Build a passive RC network circuit and simulate it. | *SPICE Netlist for circuit 428
C1 2 1 1nF
R1 5 1 1k
V1 5 2 5V
.OP
.END |
Design an op-amp voltage follower (unity gain buffer) with 12.0V supply. | *Op-Amp Voltage Follower (Buffer)
V1 VCC 0 DC 12.0V
V2 VEE 0 DC -12.0V
VIN INP 0 AC 1m SIN(0 1 1k)
EOPA OUT 0 INP OUT 100000
RL OUT 0 2.2k
.OP
.AC DEC 50 1 10Meg
.END |
Build a passive RC network circuit and simulate it. | * Z:\mnt\design.r\spice\examples\4608A.asc
V1 IN 0 3.6
C1 OUT 0 100
Rload OUT 0 .225
R2 N001 0 4.87K
XU1 OUT 0 NC_01 IN MP_02 NC_03 MP_04 MP_05 MP_06 NC_07 NC_08 NC_09 0 MP_10 MP_11 MP_12 MP_13 MP_14 MP_15 NC_16 NC_17 NC_18 MP_19 MP_20 MP_21 MP_22 MP_23 MP_24 N001 IN MP_25 NC_26 0 IN MP_27 MP_28 IN NC_29 LTM4608
.tran ... |
Design an analog integrator circuit using an op-amp with capacitive feedback. | *Op-Amp Integrator
V1 VCC 0 DC 9.0V
V2 VEE 0 DC -9.0V
VIN IN 0 PULSE(0 1 0 1n 1n 500u 1m)
RIN IN INM 8.2k
CF INM OUT 22n
EOPA OUT 0 0 INM 100000
.TRAN 10u 5m
.END |
Design a simple RC circuit and write the SPICE netlist. | * Z:\mnt\spice-netlists\LT1028_TA10_LT1055_1.asc
XU1 N001 N003 V+ V- OUT LT1028
D1 OUT N005 1N4148
D2 N008 N010 1N4148
R1 N001 0 1K
R2 N002 N001 1K
C1 OUT N002 .047
R3 N003 N007 2.4K
R4 OUT N003 5.6K
C2 OUT N003 10p
R5 N005 N004 49.9K
R6 N004 N009 100K
C3 N006 N004 15
J1 N007 N009 0 2N4338
C4 N001 0 .047
V1 V+ 0 15
V2 ... |
Design a differential BJT amplifier with tail resistor and dual ±12.0V supply. | *BJT Differential Pair
V1 VCC 0 DC 12.0V
V2 VEE 0 DC -12.0V
VIN+ INP 0 AC 1m
VIN- INM 0 AC 0
RC1 VCC OUTP 1.5k
RC2 VCC OUTM 1.5k
Q1 OUTP INP TAIL Q2N2222
Q2 OUTM INM TAIL Q2N2222
RE1 TAIL VEE 680
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.AC DEC 50 10 100Meg
.END |
Design a single-pole high-pass filter with 47u and 12Meg and simulate frequency response. | *High-Pass RC Filter
V1 IN 0 AC 1
C1 IN OUT 47u
R1 OUT 0 12Meg
.AC DEC 100 1 10Meg
.END |
Design an RC differentiator circuit with R=1.2Meg and C=100n. | *RC Differentiator
V1 IN 0 PULSE(0 12.0V 0 1n 1n 500u 1m)
C1 IN OUT 100n
R1 OUT 0 1.2Meg
.TRAN 1u 5m
.END |
Design a Zener diode voltage regulator with 8.2V reference from 15.9V supply. | *Zener Voltage Regulator
V1 IN 0 DC 15.9V
R1 IN OUT 4.7k
DZ1 0 OUT ZENER
.MODEL ZENER D (BV=8.2 IBV=5m RS=5)
.OP
.END |
Create a non-inverting amplifier with R1=3.3k and Rf=6.8k for gain 3.06. | *Non-Inverting Op-Amp Amplifier (Gain = 3.06)
V1 VCC 0 DC 5.0V
V2 VEE 0 DC -5.0V
VIN INP 0 AC 1m SIN(0 1 1k)
R1 INM 0 3.3k
RF INM OUT 6.8k
EOPA OUT 0 INP INM 100000
.OP
.AC DEC 50 1 10Meg
.END |
Build a simple MOSFET circuit and simulate its DC operating point Include transient analysis. | * Z:\mnt\design.r\spice\examples\3643.asc
XU1 N016 N010 N003 N013 N002 N011 N002 N007 N004 N017 N005 N009 N006 N014 N015 N008 0 LTC3643
R1 N002 N003 10m
L1 N004 N005 4.7
C1 N006 N005 .1
MQ1 N001 N007 N002 N002 Si4427DY
C2 N003 0 47
C3 0 N009 4.7
R2 N014 N016 392K
R3 N016 0 6.04K
C4 N014 0 2
R4 N012 N011 400K
C5 0 N012 ... |
Create a SPICE netlist for a MOSFET-based circuit and perform an operating point simulation. | * Z:\mnt\spice-netlists\LT1249_TA01.asc
XU1 0 N010 N001 N004 N005 N007 N008 N011 LT1249
MQ1 N003 N011 0 0 SUD40N10-25
R1 N006 N007 330K
C1 N005 N007 .047
C2 N005 N006 .47
V2 N008 0 17
R2 N010 N009 10K
C3 N010 0 10p
C4 N009 0 100p
L1 N002 N003 750
R3 N002 N004 1Meg
C5 N004 0 4700p
D1 N003 OUT MUR460
C6 OUT 0 180
D2 + N0... |
Design an op-amp summing amplifier with two inputs using Rf=1.2k. | *Op-Amp Summing Amplifier
V1 VCC 0 DC 12.0V
V2 VEE 0 DC -12.0V
VIN1 IN1 0 SIN(0 1 500)
VIN2 IN2 0 SIN(0 1 1k)
R1 IN1 INM 820
R2 IN2 INM 390
RF INM OUT 1.2k
EOPA OUT 0 0 INM 100000
.TRAN 10u 10m
.END |
Design a passive RC integrator and simulate transient response to a square wave. | *RC Integrator
V1 IN 0 PULSE(0 12.0V 0 1n 1n 500u 1m)
R1 IN OUT 820
C1 OUT 0 100n
.TRAN 1u 5m
.END |
Design a series RLC bandpass filter with resonant frequency of approximately 1.1e+04Hz. | *Series RLC Bandpass Filter
V1 IN 0 AC 1
R1 IN N1 3.9k
L1 N1 N2 4.7u
C1 N2 0 47u
.AC DEC 100 1 100Meg
.END |
Build a high-pass RC filter with 10p capacitor and 5.6Meg resistor and run AC analysis. | *High-Pass RC Filter
V1 IN 0 AC 1
C1 IN OUT 10p
R1 OUT 0 5.6Meg
.AC DEC 100 1 10Meg
.END |
Design an RC differentiator circuit with R=220 and C=220n. | *RC Differentiator
V1 IN 0 PULSE(0 3.3V 0 1n 1n 500u 1m)
C1 IN OUT 220n
R1 OUT 0 220
.TRAN 1u 5m
.END |
Design a simple RC circuit and write the SPICE netlist Include transient analysis. | * Z:\mnt\design.r\spice\examples\ADP151-3.0.asc
V1 IN 0 5
Rload OUT 0 30
XU1 IN 0 IN MP_01 OUT ADP151-x.x T=2Meg
C1 OUT 0 1
.tran 500u startup
.lib ADP151-x.x.sub
.backanno
.end |
Write a SPICE netlist for a mixed-component electronic circuit. | * Z:\mnt\design.r\spice\examples\2641-16.asc
V1 N005 0 PULSE(0 3.3 0 0.1n 0.1n 19.8n 40n)
V2 N002 0 5
V3 N003 0 2.5
V4 N004 0 PULSE(0 3.3 0 0.1n 0.1n 9.9n 20n)
V5 N001 0 PWL(0 3.3 0.6u 3.3 +2n 0 +0.31u 0 +2n 3.3)
V6 N006 0 PWL(0 3.3 2u 3.3 +2n 0 +30n 0 +2n 3.3)
XU1 N003 N001 N004 N005 N006 OUT N002 0 LTC2641-16
C1 OUT ... |
Create a resistor ladder circuit and simulate the DC operating point. | *Resistor Ladder Network
V1 VCC 0 DC 1.8V
R1 VCC N1 56k
R2 N1 N2 120k
R3 N2 0 2.2k
.OP
.END |
Design an NMOS source follower (common-drain) with 9.0V supply. | *NMOS Source Follower
V1 VDD 0 DC 9.0V
V2 IN 0 AC 1m DC 0
RG IN GATE 18Meg
RS SOURCE 0 27k
M1 VDD GATE SOURCE 0 NMOS W=1u L=1u
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02 GAMMA=0.5 PHI=0.6)
.OP
.AC DEC 50 10 100Meg
.END |
Design an analog circuit and generate the SPICE netlist for ngspice simulation Include transient analysis. | * Z:\mnt\design.r\spice\examples\8061-4.1.asc
V1 IN 0 12
C1 OUT 0 .2m
XU1 N001 N001 N001 N002 N003 0 N005 N004 OUT IN OUT MP_01 0 LTM8061-4.1
C3 N001 0 4.7
.tran 3m startup
.lib LTM8061-4.1.sub
.backanno
.end |
Create an inverting amplifier circuit with feedback resistor 56k and input resistor 1.8k. | *Inverting Op-Amp Amplifier (Gain = -31.11)
V1 VCC 0 DC 9.0V
V2 VEE 0 DC -9.0V
VIN IN 0 AC 1m SIN(0 1 1k)
RIN IN INM 1.8k
RF INM OUT 56k
EOPA OUT 0 0 INM 100000
.OP
.AC DEC 50 1 10Meg
.END |
Build a high-pass RC filter with 1u capacitor and 180k resistor and run AC analysis. | *High-Pass RC Filter
V1 IN 0 AC 1
C1 IN OUT 1u
R1 OUT 0 180k
.AC DEC 100 1 10Meg
.END |
Write a SPICE netlist for a series RLC filter circuit. | *Series RLC Bandpass Filter
V1 IN 0 AC 1
R1 IN N1 330
L1 N1 N2 2.2m
C1 N2 0 470p
.AC DEC 100 1 100Meg
.END |
Design a single-pole high-pass filter with 47n and 56k and simulate frequency response. | *High-Pass RC Filter
V1 IN 0 AC 1
C1 IN OUT 47n
R1 OUT 0 56k
.AC DEC 100 1 10Meg
.END |
Build a resistive ladder with three stages from a 1.8V supply. | *Resistor Ladder Network
V1 VCC 0 DC 1.8V
R1 VCC N1 33k
R2 N1 N2 5.6k
R3 N2 0 330k
.OP
.END |
Design a resistive voltage divider with a 9.0V supply, R1=2.2Meg and R2=8.2Meg. | *Voltage Divider
V1 IN 0 DC 9.0V
R1 IN OUT 2.2Meg
R2 OUT 0 8.2Meg
.OP
.END |
Design a single-pole low-pass filter with 12Meg and 1p and simulate frequency response. | *Low-Pass RC Filter
V1 IN 0 AC 1 DC 1.8V
R1 IN OUT 12Meg
C1 OUT 0 1p
.AC DEC 100 1 10Meg
.END |
Write a SPICE netlist for a BJT common-emitter stage with voltage divider bias. | *BJT Common-Emitter Amplifier
V1 VCC 0 DC 12.0V
V2 IN 0 AC 1m DC 0
R1 VCC BASE 33k
R2 BASE 0 47k
RC1 VCC COLL 1k
RE1 EMIT 0 560
Q1 COLL BASE EMIT Q2N2222
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.AC DEC 50 10 100Meg
.END |
Build an inverting amplifier stage with voltage gain of -1.46. | *Inverting Op-Amp Amplifier (Gain = -1.46)
V1 VCC 0 DC 5.0V
V2 VEE 0 DC -5.0V
VIN IN 0 AC 1m SIN(0 1 1k)
RIN IN INM 5.6k
RF INM OUT 8.2k
EOPA OUT 0 0 INM 100000
.OP
.AC DEC 50 1 10Meg
.END |
Create a four-diode bridge rectifier with smoothing capacitor 4.7u. | *Full-Wave Bridge Rectifier
V1 AC+ AC- SIN(0 12.0V 60)
D1 AC+ OUT D1N4148
D2 GND AC+ D1N4148
D3 AC- OUT D1N4148
D4 GND AC- D1N4148
R1 OUT GND 33k
C1 OUT GND 4.7u
.MODEL D1N4148 D (IS=2.52n RS=16.6 N=1.752 CJO=4p M=0.333 VJ=0.7 BV=100 IBV=100u)
.TRAN 100u 200m
.END |
Build a simple MOSFET circuit and simulate its DC operating point. | *SPICE Netlist for circuit 144
R1 0 3 1k
M1 2 1 3 3 NMOS W=1u L=1u
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02)
.OP
.END |
Design a passive RC filter circuit and write the SPICE netlist for AC analysis. | * Z:\mnt\design.r\spice\examples\2078A.asc
V1 +V 0 9
R1 N002 N001 {5.1Meg+120K}
C1 N002 N001 100p
R3 N003 N002 2.64Meg
R4 N004 N003 2.64Meg
C2 N003 0 2000p
R5 OUT N007 1.35Meg
C3 N004 N007 1000p
C4 N007 N002 1000p
R2 N006 N005 27.6K
R6 N005 IN 27.6K
C5 N002 N005 .02
C6 N006 0 .01
V2 IN 0 4.5 AC 1
XU1 N006 N001 +V 0 N00... |
Build a common-drain MOSFET amplifier and analyze its frequency response. | *NMOS Source Follower
V1 VDD 0 DC 5.0V
V2 IN 0 AC 1m DC 0
RG IN GATE 33Meg
RS SOURCE 0 2.7k
M1 VDD GATE SOURCE 0 NMOS W=10u L=0.5u
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02 GAMMA=0.5 PHI=0.6)
.OP
.AC DEC 50 10 100Meg
.END |
Write a SPICE netlist for a diode waveform clipper circuit. | *Diode Clipper Circuit
V1 IN 0 SIN(0 5.0V 1k)
R1 IN OUT 1k
D1 OUT 0 D1N4148
.MODEL D1N4148 D (IS=2.52n RS=16.6 N=1.752 CJO=4p M=0.333 VJ=0.7 BV=100 IBV=100u)
.TRAN 10u 5m
.END |
Create an inverting summing amplifier with R1=390, R2=680, Rf=12k. | *Op-Amp Summing Amplifier
V1 VCC 0 DC 9.0V
V2 VEE 0 DC -9.0V
VIN1 IN1 0 SIN(0 1 500)
VIN2 IN2 0 SIN(0 1 1k)
R1 IN1 INM 390
R2 IN2 INM 680
RF INM OUT 12k
EOPA OUT 0 0 INM 100000
.TRAN 10u 10m
.END |
Write a SPICE netlist for a Zener voltage regulator with 12V breakdown voltage. | *Zener Voltage Regulator
V1 IN 0 DC 22.1V
R1 IN OUT 680
DZ1 0 OUT ZENER
.MODEL ZENER D (BV=12 IBV=5m RS=5)
.OP
.END |
Build an RL circuit and simulate its response to a step input voltage. | *RL Circuit Transient
V1 IN 0 PULSE(0 15.0V 0 1n 1n 500u 1m)
R1 IN N1 12Meg
L1 N1 0 100n
.TRAN 1n 5m
.END |
Create an inverting integrator circuit using an op-amp, resistor, and feedback capacitor. | *Op-Amp Integrator
V1 VCC 0 DC 9.0V
V2 VEE 0 DC -9.0V
VIN IN 0 PULSE(0 1 0 1n 1n 500u 1m)
RIN IN INM 3.9k
CF INM OUT 220n
EOPA OUT 0 0 INM 100000
.TRAN 10u 5m
.END |
Build a low-pass RC filter with 1.8Meg resistor and 470n capacitor and run AC analysis. | *Low-Pass RC Filter
V1 IN 0 AC 1 DC 3.3V
R1 IN OUT 1.8Meg
C1 OUT 0 470n
.AC DEC 100 1 10Meg
.END |
Design an RC integrator circuit with time constant of 7e-05s. | *RC Integrator
V1 IN 0 PULSE(0 1.8V 0 1n 1n 500u 1m)
R1 IN OUT 1.5k
C1 OUT 0 47n
.TRAN 1u 5m
.END |
Create a simple resistor network and provide the SPICE netlist. | * Z:\mnt\design.r\spice\examples\1097.asc
V1 +V 0 15
V2 -V 0 -15
R1 OUT N001 50K
V3 IN- IN+ SINE(0 1 100)
XU1 N002 N001 +V -V OUT LT1097
R3 N001 IN- 50K
R2 N002 IN+ 50K
R4 0 N002 50K
V4 IN+ 0 SINE(0 27 1K)
.tran 30m
* 27V Common Mode Range Difference Amplifier
.lib LTC.lib
.backanno
.end |
Design a Wheatstone bridge circuit with 15.0V supply voltage. | *Wheatstone Bridge
V1 VCC 0 DC 15.0V
R1 VCC A 12Meg
R2 VCC B 680k
R3 A 0 4.7k
R4 B 0 10k
.OP
.END |
Write a SPICE netlist for a basic NMOS current mirror circuit. | *NMOS Current Mirror
V1 VDD 0 DC 3.3V
R1 VDD REF 1k
M1 REF REF 0 0 NMOS W=20u L=1u
M2 OUT REF 0 0 NMOS W=20u L=1u
RL OUT 0 1.5k
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02 GAMMA=0.5 PHI=0.6)
.OP
.END |
Design an inverting op-amp amplifier with gain of -3.93 using Rin=560 and Rf=2.2k. | *Inverting Op-Amp Amplifier (Gain = -3.93)
V1 VCC 0 DC 9.0V
V2 VEE 0 DC -9.0V
VIN IN 0 AC 1m SIN(0 1 1k)
RIN IN INM 560
RF INM OUT 2.2k
EOPA OUT 0 0 INM 100000
.OP
.AC DEC 50 1 10Meg
.END |
Write a SPICE netlist for a mixed-component electronic circuit. | * Z:\mnt\design.r\spice\examples\6400-20.asc
V1 N004 0 SINE(0 10m 100Meg)
XU1 0 0 N001 N002 N006 N007 N007 N004 N005 N003 LTC6400-20
V2 N001 0 1.5
V3 N007 0 -1.5
.tran 100n
.lib LTC6.lib
.backanno
.end |
Build a passive RC network circuit and simulate it. | * Z:\mnt\spice-netlists\LT3020-1_8_DC687A.asc
V1 IN 0 2.1
Rload OUT 0 18
C1 OUT 0 2.2
C2 IN 0 2.2
XU1 OUT MP_01 MP_02 0 IN MP_03 IN LT3020-1.8
.tran 1m startup
* LT3020-1.8 - 100mA, Low Voltage, Very Low Dropout Linear Regulator\nVLDO Regulator\nInput: 2.1V to 10V Output: 1.8V @ 100mA
* Note:\n If the simulation ... |
Design a voltage divider using resistors and provide the SPICE netlist. | * Z:\mnt\design.r\spice\examples\1037.asc
V1 +V 0 15
V2 -V 0 -15
R1 OUT N001 355K
R2 N001 0 365
V3 IN 0 SINE(0 1m 1)
XU1 IN N001 +V -V OUT LT1037
.tran 3
* Gain 1000 Amplifier with .01% Accuracy
.lib LTC.lib
.backanno
.end |
Design an inverting op-amp amplifier with gain of -82.35 using Rin=680 and Rf=56k. | *Inverting Op-Amp Amplifier (Gain = -82.35)
V1 VCC 0 DC 12.0V
V2 VEE 0 DC -12.0V
VIN IN 0 AC 1m SIN(0 1 1k)
RIN IN INM 680
RF INM OUT 56k
EOPA OUT 0 0 INM 100000
.OP
.AC DEC 50 1 10Meg
.END |
Design an RC circuit for timing or filtering and provide the netlist. | * Z:\mnt\design.r\spice\examples\1550LCS8-2.5.asc
C1 N001 0 .1
C2 N003 N002 .1
V1 IN 0 4.5
C3 OUT 0 10
Rload OUT 0 1K
XU1 IN IN N002 OUT N003 0 N001 OUT LTC1550LCS8-2.5
.tran 1m startup
.lib LTC1550LCS8-2.5.sub
.backanno
.end |
Build an RC circuit that differentiates a square wave input. | *RC Differentiator
V1 IN 0 PULSE(0 2.5V 0 1n 1n 500u 1m)
C1 IN OUT 470p
R1 OUT 0 100
.TRAN 1u 5m
.END |
Design a resistor-inductor circuit and analyze its transient behavior. | *RL Circuit Transient
V1 IN 0 PULSE(0 9.0V 0 1n 1n 500u 1m)
R1 IN N1 8.2Meg
L1 N1 0 4.7u
.TRAN 1n 5m
.END |
Design a MOSFET logic or amplifier circuit and provide the complete SPICE netlist. | *SPICE Netlist for circuit 138
M2 5 1 2 2 NMOS W=1u L=1u
M1 4 1 5 5 NMOS W=1u L=1u
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02)
.OP
.END |
Design a half-wave rectifier with 5.0V peak input at 50Hz. | *Half-Wave Rectifier
V1 IN 0 SIN(0 5.0V 50)
D1 IN N1 D1N4148
R1 N1 0 3.9Meg
C1 N1 0 100n
.MODEL D1N4148 D (IS=2.52n RS=16.6 N=1.752 CJO=4p M=0.333 VJ=0.7 BV=100 IBV=100u)
.TRAN 10u 100m
.END |
Build a circuit with 3 MOSFET devices and simulate it. | *SPICE Netlist for circuit 318
C1 3 2 1nF
M2 3 6 0 0 NMOS W=1u L=1u
M3 4 1 0 0 NMOS W=1u L=1u
M1 VDD 2 4 4 NMOS W=1u L=1u
R2 2 VDD 1k
R1 3 VDD 1k
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02)
.OP
.END |
Design a diode clamping circuit and run transient simulation. | *Diode Clipper Circuit
V1 IN 0 SIN(0 5.0V 1k)
R1 IN OUT 390
D1 OUT 0 D1N4148
.MODEL D1N4148 D (IS=2.52n RS=16.6 N=1.752 CJO=4p M=0.333 VJ=0.7 BV=100 IBV=100u)
.TRAN 10u 5m
.END |
Write a SPICE netlist for a passive high-pass filter using a capacitor and resistor. | *High-Pass RC Filter
V1 IN 0 AC 1
C1 IN OUT 1u
R1 OUT 0 56Meg
.AC DEC 100 1 10Meg
.END |
Create a positive diode clipping circuit with series resistor 2.7k. | *Diode Clipper Circuit
V1 IN 0 SIN(0 12.0V 1k)
R1 IN OUT 2.7k
D1 OUT 0 D1N4148
.MODEL D1N4148 D (IS=2.52n RS=16.6 N=1.752 CJO=4p M=0.333 VJ=0.7 BV=100 IBV=100u)
.TRAN 10u 5m
.END |
Write a SPICE netlist for a basic BJT current mirror. | *BJT Current Mirror
V1 VCC 0 DC 12.0V
R1 VCC REF 2.2k
Q1 REF REF 0 Q2N2222
Q2 OUT REF 0 Q2N2222
RL OUT 0 1k
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.END |
Design a three-resistor ladder network with 5.0V supply. | *Resistor Ladder Network
V1 VCC 0 DC 5.0V
R1 VCC N1 1.5Meg
R2 N1 N2 390k
R3 N2 0 820
.OP
.END |
Write a SPICE netlist for a BJT differential amplifier with dual supply. | *BJT Differential Pair
V1 VCC 0 DC 9.0V
V2 VEE 0 DC -9.0V
VIN+ INP 0 AC 1m
VIN- INM 0 AC 0
RC1 VCC OUTP 3.3k
RC2 VCC OUTM 3.3k
Q1 OUTP INP TAIL Q2N2222
Q2 OUTM INM TAIL Q2N2222
RE1 TAIL VEE 390
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.AC DEC 50 10 100Meg
.END |
Design a BJT current mirror circuit with 9.0V supply and 2.7k reference resistor. | *BJT Current Mirror
V1 VCC 0 DC 9.0V
R1 VCC REF 2.7k
Q1 REF REF 0 Q2N2222
Q2 OUT REF 0 Q2N2222
RL OUT 0 1.2k
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.END |
Design a single-pole high-pass filter with 1n and 39k and simulate frequency response. | *High-Pass RC Filter
V1 IN 0 AC 1
C1 IN OUT 1n
R1 OUT 0 39k
.AC DEC 100 1 10Meg
.END |
Design a tank circuit using parallel RLC components and perform AC simulation. | *Parallel RLC Tank Circuit
I1 0 OUT AC 1m
R1 OUT 0 150k
L1 OUT 0 1m
C1 OUT 0 100p
.AC DEC 100 1 100Meg
.END |
Build a BJT saturation switch with base resistor 3.9k and collector load 820. | *BJT Switching Circuit
V1 VCC 0 DC 5.0V
V2 IN 0 PULSE(0 5.0V 0 1n 1n 500u 1m)
RB1 IN BASE 3.9k
RC1 VCC COLL 820
Q1 COLL BASE 0 Q2N2222
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.TRAN 1u 3m
.END |
Create a unity-gain buffer using an NPN transistor in emitter-follower configuration. | *BJT Emitter Follower
V1 VCC 0 DC 9.0V
V2 IN 0 AC 1m DC 0
RB1 VCC BASE 68k
RE1 EMIT 0 10k
Q1 VCC BASE EMIT Q2N2222
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.AC DEC 50 10 100Meg
.END |
Design a diode clamping circuit and run transient simulation. | *Diode Clipper Circuit
V1 IN 0 SIN(0 12.0V 1k)
R1 IN OUT 1.2k
D1 OUT 0 D1N4148
.MODEL D1N4148 D (IS=2.52n RS=16.6 N=1.752 CJO=4p M=0.333 VJ=0.7 BV=100 IBV=100u)
.TRAN 10u 5m
.END |
Create a SPICE netlist for an electronic circuit with multiple components Include transient analysis. | * Z:\mnt\design.r\spice\examples\1152.asc
V1 +V 0 5
V2 -V 0 -5
V3 IN 0 SINE(0 5 1K)
XU1 IN OUT +V -V OUT NC_01 NC_02 NC_03 LTC1152
.tran 3m
.lib LTC.lib
.backanno
.end |
Build a circuit with 2 MOSFET devices and simulate it. | *SPICE Netlist for circuit 321
M1 1 1 0 0 NMOS W=1u L=1u
M2 3 1 0 0 NMOS W=1u L=1u
R1 1 VDD 1k
R2 3 VDD 1k
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02)
.OP
.END |
Design an emitter follower stage with 12k emitter resistor from 5.0V supply. | *BJT Emitter Follower
V1 VCC 0 DC 5.0V
V2 IN 0 AC 1m DC 0
RB1 VCC BASE 22Meg
RE1 EMIT 0 12k
Q1 VCC BASE EMIT Q2N2222
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.AC DEC 50 10 100Meg
.END |
Build an RC circuit that integrates a pulse input with 820k and 4.7u. | *RC Integrator
V1 IN 0 PULSE(0 2.5V 0 1n 1n 500u 1m)
R1 IN OUT 820k
C1 OUT 0 4.7u
.TRAN 1u 5m
.END |
Build a series resonant RLC circuit and simulate its frequency response. | *Series RLC Bandpass Filter
V1 IN 0 AC 1
R1 IN N1 820
L1 N1 N2 2.2n
C1 N2 0 10u
.AC DEC 100 1 100Meg
.END |
Create a MOSFET common-source stage with drain resistor 1.2k and source degeneration 1.2k. | *NMOS Common-Source Amplifier
V1 VDD 0 DC 9.0V
V2 IN 0 AC 1m DC 0
RG IN GATE 680k
RD VDD DRAIN 1.2k
RS SOURCE 0 1.2k
M1 DRAIN GATE SOURCE 0 NMOS W=1u L=2u
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02 GAMMA=0.5 PHI=0.6)
.OP
.AC DEC 50 10 100Meg
.END |
Build a Zener diode clamp circuit that regulates output to 15V. | *Zener Voltage Regulator
V1 IN 0 DC 41.2V
R1 IN OUT 560
DZ1 0 OUT ZENER
.MODEL ZENER D (BV=15 IBV=5m RS=5)
.OP
.END |
Create an inverting amplifier circuit with feedback resistor 1.8k and input resistor 2.7k. | *Inverting Op-Amp Amplifier (Gain = -0.67)
V1 VCC 0 DC 5.0V
V2 VEE 0 DC -5.0V
VIN IN 0 AC 1m SIN(0 1 1k)
RIN IN INM 2.7k
RF INM OUT 1.8k
EOPA OUT 0 0 INM 100000
.OP
.AC DEC 50 1 10Meg
.END |
Write a SPICE netlist for a MOSFET circuit with voltage source and model definition. | *SPICE Netlist for circuit 547
M1 2 1 4 4 NMOS W=1u L=1u
R1 2 VDD 1k
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02)
.OP
.END |
Design a BJT current mirror circuit with 9.0V supply and 22k reference resistor. | *BJT Current Mirror
V1 VCC 0 DC 9.0V
R1 VCC REF 22k
Q1 REF REF 0 Q2N2222
Q2 OUT REF 0 Q2N2222
RL OUT 0 1.2k
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.END |
Create a resistor-capacitor circuit and provide the complete SPICE netlist Include transient analysis. | * Z:\mnt\design.r\spice\examples\ADG1419.asc
V1 +V 0 15
V2 -V 0 -15
V4 N004 0 PULSE(0 5 0 20n 20n 10u 20u)
R2 N001 0 300
V5 N002 0 10
V3 N005 0 5;PULSE(0 5 0 20n 20n 10u 20u)
XU1 N004 N002 N001 N003 N005 -V 0 +V ADG1419
V6 N003 0 0
C1 0 N001 35p
.tran 0.0001
.lib ADG1419.sub
.backanno
.end |
Design a tank circuit using parallel RLC components and perform AC simulation. | *Parallel RLC Tank Circuit
I1 0 OUT AC 1m
R1 OUT 0 2.7k
L1 OUT 0 47n
C1 OUT 0 2.2u
.AC DEC 100 1 100Meg
.END |
Create a two-transistor MOSFET current mirror and simulate the operating point. | *NMOS Current Mirror
V1 VDD 0 DC 12.0V
R1 VDD REF 27k
M1 REF REF 0 0 NMOS W=40u L=0.5u
M2 OUT REF 0 0 NMOS W=40u L=0.5u
RL OUT 0 3.9k
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02 GAMMA=0.5 PHI=0.6)
.OP
.END |
Design an RC integrator circuit with time constant of 4e-05s. | *RC Integrator
V1 IN 0 PULSE(0 2.5V 0 1n 1n 500u 1m)
R1 IN OUT 1.8k
C1 OUT 0 22n
.TRAN 1u 5m
.END |
Build a resistor network and calculate the operating point Include transient analysis. | * Z:\mnt\design.r\spice\examples\1636.asc
V1 +V 0 5
V3 N001 0 SINE(2.5 1 10K)
XU1 N001 OUT +V 0 OUT N002 LT1636
V4 N002 0 PULSE(0 5 0 1u 1u .5m 1m)
R1 OUT 0 10K
.tran 3m startup
.lib LTC.lib
.backanno
.end |
Write a SPICE netlist for a MOSFET-based circuit with multiple transistors. | *SPICE Netlist for circuit 416
I1 VDD 3 DC 1mA
I2 1 0 DC 1mA
R1 5 1 1k
M2 3 2 1 1 NMOS W=1u L=1u
M1 VDD 3 1 1 NMOS W=1u L=1u
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02)
.OP
.END |
Write a SPICE netlist for a series resistor network with 1.8V source. | *Resistor Ladder Network
V1 VCC 0 DC 1.8V
R1 VCC N1 1.8k
R2 N1 N2 1.8Meg
R3 N2 0 150
.OP
.END |
Build a simple MOSFET circuit and simulate its DC operating point Include transient analysis. | * Z:\mnt\design.r\spice\examples\1154.asc
V1 N001 0 PULSE(0 5 0 1u 1u 5m 10m)
MQ1 N004 N007 N008 N008 Si9936DY
R1 N002 N004 .036
C1 N002 N003 .1
R2 N004 N003 100K
XU1 N001 0 N006 0 0 N007 N003 N002 LTC1154
V2 N002 0 PWL(0 5 1 16)
R3 N006 N005 51K
Rload N008 0 10
V3 N005 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\use... |
Create an RC low-pass filter with cutoff frequency of approximately 1.9e+04Hz. | *Low-Pass RC Filter
V1 IN 0 AC 1 DC 12.0V
R1 IN OUT 390
C1 OUT 0 22n
.AC DEC 100 1 10Meg
.END |
Write a SPICE netlist for a MOSFET-based circuit with multiple transistors. | *SPICE Netlist for circuit 297
I1 2 0 DC 1mA
M1 1 3 2 2 NMOS W=1u L=1u
V2 3 0 5V
R1 1 VDD 1k
M2 1 4 VDD VDD PMOS W=1u L=1u
V1 VDD 4 5V
.MODEL NMOS NMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02)
.MODEL PMOS PMOS (LEVEL=1 VTO=1 KP=1.0e-4 LAMBDA=0.02)
.OP
.END |
Design a BJT current mirror circuit with 12.0V supply and 4.7k reference resistor. | *BJT Current Mirror
V1 VCC 0 DC 12.0V
R1 VCC REF 4.7k
Q1 REF REF 0 Q2N2222
Q2 OUT REF 0 Q2N2222
RL OUT 0 5.6k
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.END |
Write a SPICE netlist for a BJT differential amplifier with dual supply. | *BJT Differential Pair
V1 VCC 0 DC 9.0V
V2 VEE 0 DC -9.0V
VIN+ INP 0 AC 1m
VIN- INM 0 AC 0
RC1 VCC OUTP 3.3k
RC2 VCC OUTM 3.3k
Q1 OUTP INP TAIL Q2N2222
Q2 OUTM INM TAIL Q2N2222
RE1 TAIL VEE 470
.MODEL Q2N2222 NPN (IS=1e-14 BF=200 VAF=100 IKF=0.3 RC=0.3 CJC=8p CJE=25p TF=0.5n)
.OP
.AC DEC 50 10 100Meg
.END |
Build a passive RC network and analyze its frequency response Include AC frequency sweep analysis. | * Z:\mnt\spice-netlists\LT6261_BesselSecondOrder.asc
V1 IN VREF PULSE(1 -1 10u 1n 1n 500u) AC 1
V2 V+ 0 5
R1 IN N001 15.4K
R2 N001 N002 15.4K
C1 N001 0 150p
C2 N002 OUT 47p
R3 N001 OUT 15.4K
V3 VREF 0 2.5
XU1 VREF N002 OUT V+ 0 V+ LTC6261
.ac oct 250 100 1meg
* .tran 5m
* .noise V(o1) V1 oct 100 1 10k
* LTC6261 - 30MHz... |
Build a passive RC network circuit and simulate it. | * Z:\mnt\design.r\spice\examples\2914-2.asc
R12 N002 N004 44.2K
R10 N004 N005 1K
R11 N005 0 4.53K
R9 N001 N007 27.4K
R7 N007 N008 1K
R8 N008 0 4.53K
R4 N009 N011 4.64K
R5 N011 N012 845
R6 N012 N018 54.9K
R1 N009 N014 4.64K
R2 N014 N015 768
R3 N015 N017 37.4K
R13 N003 N006 10K
R14 N003 N010 10K
C1 N016 0 .01
V1 N002 0 P... |
Write a SPICE netlist for a passive high-pass filter using a capacitor and resistor. | *High-Pass RC Filter
V1 IN 0 AC 1
C1 IN OUT 470n
R1 OUT 0 68k
.AC DEC 100 1 10Meg
.END |
Design a resistive voltage divider circuit and write the SPICE netlist. | * Z:\mnt\design.r\spice\examples\1015.asc
V1 N001 0 5
V2 N004 0 PULSE(2 3 0 .5u .5u 0 1u)
XU1 N004 N002 N001 0 N003 N005 LT1015
R1 N001 N002 10K
R2 N002 0 10K
V3 N005 0 PULSE(0 5 0 5n 5n 5u 10u)
.tran 30u
.lib LTC1.lib
.backanno
.end |
End of preview. Expand in Data Studio
SPICE Circuits Fine-tune V2
A clean, validated dataset of 7,410 instruction-output pairs for fine-tuning language models to generate SPICE netlists from natural language descriptions.
Dataset Description
This is Version 2 of the SPICE circuits fine-tuning dataset. V1 was polluted with mixed formats (LTspice, KiCad, standard SPICE) and no validation. V2 is fully validated — every netlist passes PySpice's SpiceParser.build_circuit() gate. No exceptions.
Data Sources
- AMSNet (734 entries) — Real-world analog/mixed-signal circuit netlists
- Symbench (2,176 entries) — Real-world netlists from Symbench benchmark suite (LTspice-specific entries discarded)
- Synthetic (4,500 entries) — Programmatically generated netlists across 7 circuit families, validated through PySpice
Circuit Categories
Resistive networks, RC filters, RLC circuits, diode circuits, BJT amplifiers, MOSFET circuits, op-amp configurations.
Format
JSONL — one JSON object per line:
{"instruction": "Design a low-pass RC filter with R=10k and C=1uF.", "output": "*Low-pass RC filter\nR1 IN OUT 10k\nC1 OUT 0 1u\n.AC DEC 100 1 10Meg\n.END"}
Intended Use
Fine-tuning Qwen2.5-Coder-3B-Instruct (or similar small code LLMs) to generate simulation-ready standard SPICE netlists from conversational prompts. Compatible with trl, axolotl, and unsloth.
Validation
All 7,410 entries pass PySpice.Spice.Parser.SpiceParser.build_circuit() — zero failures.
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