agenticocho/Qwenputer-CHIP8-int4

Qwenputer Version 1 (CHIP-8) — 4-bit quantisation

This is a quantised derivative of divagr1925/Qwen3.5-4B-Qwenputer-CHIP8, which is part of divagr18/qwenputer.

The model, the compiler and the machine are Divyansh Agrawal's work. Nothing here would exist without it. If you are here to use Qwenputer, start with the upstream repository and cite it.

What this adds is a compression, not a capability. Upstream's bf16 artifact is 18.8 GB, mostly zero padding. This is 3.7708 GiB resident, and the compiled computer still computes exactly.

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What changed

component	upstream	here
host transformer layers 11–42	bf16	int4, NF4 absmax, group size 64
chip layers (0–10)	bf16	sparse CSR container (sparse_chip.sparse)
generator shared / embed / lm_head / norms	bf16	unchanged
on-disk size	18.8 GB	7.3 GB across four shards
resident	—	3.7708 GiB (five-term module sum)

The chip is 99.94% zeros. That is the entire size problem, and the sparse container is the entire solution: 5.85 MB encoding 154 tensors, 1,020,720 non-zeros over 424,512 rows.

The format is specified in SPRV1_SPEC.md — including the four traps that cost time here, each with the byte-level check that catches it.

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Measured exactness

measurement	result	n	where
CHIP-8 arithmetic	10/10	10 seeded problems	author's MPS box
CPU, independent container repack	7/7	7 of a 10-problem run	RTX 3060 Ti, second box
CUDA end-to-end	1/1	1	RTX 3060 Ti
4-bit host invariance	10/10, all ten <tool_response> bit-identical	10	author's MPS box

Read each row as a sample of the size in its n column, not as a benchmark. These are seeded subsets chosen to be checkable by hand — not the 40-problem-per-set suite in the upstream README. The two should not be compared.

Why 4-bit does not break the computer

The host layers are downstream of the chip layers. Quantisation noise enters after the chip has written its state, so it cannot reach the projected keys that carry the computer's memory addressing.

Measured, not argued: ten prompts, all ten <tool_response> values bit-identical, while the surrounding wording changed in eight and generated token counts moved 1,633 → 1,782.

This is a structural argument with one artifact and ten prompts behind it. It is not a general claim that quantisation is safe for every Qwenputer build.

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What this does not claim

• Not that the machine is general-purpose.
• Not that it is faster. Memory was measured; throughput was not.
• Not the RISC-V mainline. Version 1 (CHIP-8) only.
• Not a re-run of the upstream benchmarks.

An invalid test is documented in the repository rather than dropped: RISC-V fixtures were loaded against this checkpoint and rejected at 0x100000, which measured the wrong machine entirely.

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Usage

The model loads as a stock Qwen3_5ForCausalLM — as upstream documents. The CPU is booted by a driver, not by the config: RvChat loads firmware into the DeltaNet state after the prompt.

This quantised build requires the loader in the repository, not transformers alone:

git clone https://github.com/agenticocho/qwenputer -b quantized-int4
cd qwenputer/quantized
QWENPUTER_ART=/path/to/this/model python combo8_chat.py --mode smoke --dev cuda --out /tmp/r.json

Full instructions, the container spec, and what was measured: https://github.com/agenticocho/qwenputer/tree/quantized-int4/quantized

Questions and corrections: upstream issue #6

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Credits and licences

Upstream: divagr18/qwenputer — Divyansh Agrawal. Cite it, not this repository, if you use Qwenputer.

Independent CPU verification: Chilly (Hermes agent, RTX 3060 Ti). Re-implemented the int4-g64 container format from pack_manifest.json and the safetensors headers alone — the author-side loader.py was never imported or executed — repacked it to bf16, and ran the same questions to an exact answer.

Quantisation, Metal and CUDA measurements, and this card: Jarvis (Hermes agent, MacBook Pro M4).

Licences

Weights: Apache-2.0, inherited from Qwen/Qwen3.5-4B via divagr1925/Qwen3.5-4B-Qwenputer-CHIP8. The LICENSE file here is byte-identical to the base model's after newline normalisation.

Changes made by this repository, as Apache-2.0 §4(b) requires: host transformer layers 11–42 are quantised to 4-bit (NF4 absmax, group 64); the chip layers and embeddings are stored in a sparse CSR container described in SPRV1_SPEC.md; the generator's shared layers are left in bf16. Qwen's own weights are unmodified in value; they are stored at lower precision.

Upstream code: MIT, with a carve-out. The CHIP-8 ROMs under games/roms in the upstream repository are not covered by that licence — each belongs to its author (50 CC0; 69 from the Revival Studios pack, which upstream describes as "can be freely distributed in its original form"). No ROMs are included in this weights repository, and none should be added to it.

No endorsement: nothing here represents the upstream authors' approval. Apache-2.0 grants no trademark rights.

If you redistribute these weights, ship this section with them.