Document ID: chunk:federal_register_of_legislation:F2024L01024:front:0:p130
Version: federal_register_of_legislation:F2024L01024
Segment Type: other
Provision Reference: 
Character Range: 387401–390273

10 bit or more, but less than 12 bit, with a "sample rate" greater than 600 Mega Samples Per Second (MSPS);
3. A resolution of 12 bit or more, but less than 14 bit, with a "sample rate" greater than 400 MSPS;
4. A resolution of 14 bit or more, but less than 16 bit, with a "sample rate" greater than 250 MSPS; or
5. A resolution of 16 bit or more with a "sample rate" greater than 65 MSPS;

                       N.B.: For integrated circuits that contain analogue‑to‑digital converters and store or process the digitised data, see 3A001.a.14.
                  Technical Notes:
                  For the purposes of 3A001.a.5.a.:
                     1. A resolution of n bit corresponds to a quantisation of 2n levels.
                     2. The resolution of the ADC is the number of bits of the digital output that represents the measured analogue input. Effective Number of Bits (ENOB) is not used to determine the resolution of the ADC.
                     3. For "multiple channel ADCs", the "sample rate" is not aggregated and the "sample rate" is the maximum rate of any single channel.
                     4. For "interleaved ADCs" or for "multiple channel ADCs" that are specified to have an interleaved mode of operation, the "sample rates" are aggregated and the "sample rate" is the maximum combined total rate of all of the interleaved channels.
3. A. 001. a. 5. b. Digital‑to‑Analogue Converters (DAC) having any of the following:
1. A resolution of 10 bit or more but less than 12 bit, with an 'adjusted update rate' exceeding 3,500 MSPS; or
2. A resolution of 12 bit or more and having any of the following:
a. An 'adjusted update rate' exceeding 1,250 MSPS but not exceeding 3,500 MSPS, and having any of the following:
                            1. A settling time less than 9 ns to arrive at or within 0.024% of full scale from a full scale step; or
                            2. A 'Spurious Free Dynamic Range' (SFDR) greater than 68 dBc (carrier) when synthesising a full scale analogue signal of 100 MHz or the highest full scale analogue signal frequency specified below 100 MHz; or
b. An 'adjusted update rate' exceeding 3,500 MSPS.
Technical Notes:
For the purposes of 3A001.a.5.b.:
                     1. 'Spurious Free Dynamic Range' (SFDR) is defined as the ratio of the RMS value of the carrier frequency (maximum signal component) at the input of the DAC to the RMS value of the next largest noise or harmonic distortion component at its output.
                     2. SFDR is determined directly from the specification table or from the characterisation plots of SFDR versus frequency.
                     3. A signal is defined to be full scale when its amplitude is greater than ‑3 dBfs (full scale).
                     4. 'Adjusted update rate' for DACs:
                         a. For conventional (non‑interpolating) DACs,