Document ID: chunk:federal_register_of_legislation:F2024L01024:front:0:p132
Version: federal_register_of_legislation:F2024L01024
Segment Type: other
Provision Reference: 
Character Range: 392766–395651

0.02 ns; or
c. An operating frequency exceeding 3 GHz;
11. Digital integrated circuits, other than those described in 3A001.a.3. to 3A001.a.10. and 3A001.a.12., based upon any compound semiconductor and having any of the following:
a. An equivalent gate count of more than 3,000 (2 input gates); or
b. A toggle frequency exceeding 1.2 GHz;
12. Fast Fourier Transform (FFT) processors having a rated execution time for an N‑point complex FFT of less than (N log2 N) /20,480 ms, where N is the number of points;
Technical Note:
              For the purposes of 3A001.a.12., when N is equal to 1,024 points, the formula gives an execution time of 500 μs.
13. Direct Digital Synthesizer (DDS) integrated circuits having any of the following:
a. A Digital‑to‑Analogue Converter (DAC) clock frequency of 3.5 GHz or more and a DAC resolution of 10 bit or more, but less than 12 bit; or
b. A DAC clock frequency of 1.25 GHz or more and a DAC resolution of 12 bit or more;
Technical Note:
For the purposes of 3A001.a.13., the DAC clock frequency may be specified as the master clock frequency or the input clock frequency.
3. A. 001. a. 14. Integrated circuits that perform or are programmable to perform all of the following:
                  a. Analogue‑to‑digital conversions meeting any of the following:
                     1. A resolution of 8 bit or more, but less than 10 bit, with a "sample rate" greater than 1.3 Giga Samples Per Second (GSPS);
                     2. A resolution of 10 bit or more, but less than 12 bit, with a "sample rate" greater than 1.0 GSPS;
                     3. A resolution of 12 bit or more, but less than 14 bit, with a "sample rate" greater than 1.0 GSPS;
                     4. A resolution of 14 bit or more, but less than 16 bit, with a "sample rate" greater than 400 Mega Samples Per Second (MSPS); or
                     5. A resolution of 16 bit or more with a "sample rate" greater than 180 MSPS; and
                  b. Any of the following:
                     1. Storage of digitised data; or
                     2. Processing of digitised data;
                   N.B.1.: For analogue‑to‑digital converter integrated circuits see 3A001.a.5.a.
                   N.B.2.: For field programmable logic devices see 3A001.a.7.
Technical Notes:
For the purposes of 3A001.a.14.:
                  1. A resolution of n bit corresponds to a quantisation of 2n levels.
                  2. The resolution of the ADC is the number of bits of the digital output of the ADC that represents the measured analogue input. Effective Number of Bits (ENOB) is not used to determine the resolution of the ADC.
                  3. For integrated circuits with non‑interleaving "multiple channel ADCs", the "sample rate" is not aggregated and the "sample rate" is the maximum rate of any single channel.
                  4. For integrated circuits with