Document ID: chunk:federal_register_of_legislation:F2024L01024:front:0:p131
Version: federal_register_of_legislation:F2024L01024
Segment Type: other
Provision Reference: 
Character Range: 389961–393025

table or from the characterisation plots of SFDR versus frequency.
                     3. A signal is defined to be full scale when its amplitude is greater than ‑3 dBfs (full scale).
                     4. 'Adjusted update rate' for DACs:
                         a. For conventional (non‑interpolating) DACs, the 'adjusted update rate' is the rate at which the digital signal is converted to an analogue signal and the output analogue values are changed by the DAC. For DACs where the interpolation mode may be bypassed (interpolation factor of one), the DAC should be considered as a conventional (non‑interpolating) DAC;
                         b. For interpolating DACs (oversampling DACs), the 'adjusted update rate' is defined as the DAC update rate divided by the smallest interpolating factor. For interpolating DACs, the 'adjusted update rate' may be referred to by different terms including:
                         ‑ input data rate
                         ‑ input word rate
                         ‑ input sample rate
                         ‑ maximum total input bus rate
                         ‑ maximum DAC clock rate for DAC clock input.
3. A. 001. a. 6. Electro‑optical and "optical integrated circuits", designed for "signal processing" and having all of the following:
a. One or more than one internal "laser" diode;
b. One or more than one internal light detecting element; and
c. Optical waveguides;
3. A. 001. a. 7. Field programmable logic devices having any of the following:
a. A maximum number of single‑ended digital input/outputs greater than 700; or
b. An 'aggregate one‑way peak serial transceiver data rate' of 500 Gb/s or greater;
Note: 3A001.a.7. includes:
‑ Complex Programmable Logic Devices (CPLDs)
‑ Field Programmable Gate Arrays (FPGAs)
‑ Field Programmable Logic Arrays (FPLAs)
‑ Field Programmable Interconnects (FPICs)
N.B.: For integrated circuits having field programmable logic devices that are combined with an analogue‑to‑digital converter, see 3A001.a.14.
Technical Notes:
For the purposes of 3A001.a.7.:
1. Maximum number of digital input/outputs in 3A001.a.7.a. is also referred to as the maximum user input/outputs or maximum available input/outputs, whether the integrated circuit is packaged or bare die.
2. 'Aggregate one‑way peak serial transceiver data rate' is the product of the peak serial one‑way transceiver data rate times the number of transceivers on the FPGA.
3. A. 001. a. 8. Not used;
9. Neural network integrated circuits;
10. Custom integrated circuits for which the function is unknown, or the control status of the equipment in which the integrated circuits will be used is unknown to the manufacturer, having any of the following:
a. More than 1,500 terminals;
b. A typical "basic gate propagation delay time" of less than 0.02 ns; or
c. An operating frequency exceeding 3 GHz;
11. Digital integrated circuits, other than those described in 3A001.a.3. to 3A001.a.10. and 3A001.a.12., based upon any compound semiconductor and having any of the following:
a. An equivalent gate count