Document ID: chunk:federal_register_of_legislation:F2024L01024:front:0:p159
Version: federal_register_of_legislation:F2024L01024
Segment Type: other
Provision Reference: 
Character Range: 462466–465477

on 'floating-point' vectors (one-dimensional arrays of 32-bit or larger numbers) simultaneously, having at least one vector arithmetic logic unit and vector registers of at least 32 elements each.
b. Designed to perform more than four 64‑bit or larger 'floating‑point' operation results per cycle; or
c. Designed to perform more than eight 16‑bit 'fixed‑point' multiply‑accumulate results per cycle (e.g., digital manipulation of analogue information that has been previously converted into digital form, also known as digital "signal processing").
Note 1: 3E002 does not apply to "technology" for multimedia extensions.
Note 2: 3E002 does not apply to "technology" for micro‑processor cores, having all of the following:
a. Using "technology" at or above 0.130 μm; and
b. Incorporating multi‑layer structures with five or fewer metal layers.
Note 3: 3E002 includes "technology" for the "development" or "production" of digital signal processors and digital array processors.
Technical Notes:
1. For the purposes of 3E002.a. and 3E002.b., 'floating‑point' is defined by IEEE‑754.
2. For the purposes of 3E002.c.,'fixed‑point' refers to a fixed‑width real number with both an integer component and a fractional component, and which does not include integer‑only formats.
3. E. 003. Other "technology" for the "development" or "production" of the following:

a. Vacuum microelectronic devices;
b. Hetero‑structure semiconductor devices such as high electron mobility transistors (HEMT), hetero‑bipolar transistors (HBT), quantum well and super lattice devices;
Note: 3E003.b. does not apply to "technology" for high electron mobility transistors (HEMT) operating at frequencies lower than 31.8 GHz and hetero‑junction bipolar transistors (HBT) operating at frequencies lower than 31.8 GHz.
c. "Superconductive" electronic devices;
3. E. 003. d. Substrates of diamond for electronic components;
e. Substrates of silicon‑on‑insulator (SOI) for integrated circuits in which the insulator is silicon dioxide;
f. Substrates of silicon carbide for electronic components;
g. "Vacuum electronic devices" operating at frequencies of 31.8 GHz or higher.
h. Substrates of gallium oxide for electronic components.
3. E. 004. "Technology" "required" for the slicing, grinding and polishing of 300 mm diameter silicon wafers to achieve a 'Site Front least sQuares Range' ('SFQR') less than or equal to 20 nm at any site of 26 mm x 8 mm on the front surface of the wafer and an edge exclusion less than or equal to 2 mm.
Technical Note:
For the purposes of 3E004., 'SFQR' is the range of maximum deviation and minimum deviation from front reference plane, calculated by least square method with all front surface data including site boundary within a site.
3. E. 101. "Technology" according to the General Technology Note for the "use" of equipment or "software" specified by 3A101., 3A102. or 3D101..
3. E. 102. "Technology" according to the General Technology Note for the "development" of "software" specified by 3D101.
3. E.