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Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class IDPool(numIds: Int, lateValid: Boolean = false, revocableSelect: Boolean = false) extends Module {
require (numIds > 0)
val idWidth = log2Up(numIds)
val io = IO(new Bundle {
val free = Flipped(Valid(UInt(idWidth.W)))
val alloc = if (revocableSelect) Decoupled(UInt(idWidth.W)) else Irrevocable(UInt(idWidth.W))
})
// True indicates that the id is available
val bitmap = RegInit(UInt(numIds.W), -1.S(numIds.W).asUInt)
val select = RegInit(0.U(idWidth.W))
val valid = RegInit(true.B)
io.alloc.valid := (if (lateValid) bitmap.orR else valid)
io.alloc.bits := (if (revocableSelect) PriorityEncoder(bitmap) else select)
val taken = Mux(io.alloc.ready, UIntToOH(io.alloc.bits, numIds), 0.U)
val allocated = Mux(io.free .valid, UIntToOH(io.free .bits, numIds), 0.U)
val bitmap1 = (bitmap & ~taken) | allocated
val select1 = PriorityEncoder(bitmap1)
val valid1 = ( (bitmap.orR && !((PopCount(bitmap) === 1.U) && io.alloc.ready)) // bitmap not zero, and not allocating last bit
|| io.free.valid)
// Clock gate the bitmap
when (io.alloc.ready || io.free.valid) {
bitmap := bitmap1
valid := valid1
}
// Make select irrevocable
when (io.alloc.ready || (!io.alloc.valid && io.free.valid)) {
select := select1
}
// No double freeing
assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))
// pre-calculations for timing
if (!lateValid) {
assert (valid === bitmap.orR)
}
if (!revocableSelect) {
when (io.alloc.valid && RegNext(io.alloc.ready || (!io.alloc.valid && io.free.valid))) {
assert (select === PriorityEncoder(bitmap))
}
}
} | module IDPool(
input clock,
input reset,
input io_free_valid,
input [2:0] io_free_bits,
input io_alloc_ready,
output io_alloc_valid,
output [2:0] io_alloc_bits
);
reg [7:0] bitmap;
reg [2:0] select;
reg valid;
wire [7:0] taken = io_alloc_ready ? 8'h1 << select : 8'h0;
wire [7:0] _GEN = {5'h0, io_free_bits};
reg REG;
wire [7:0] bitmap1 = bitmap & ~taken | (io_free_valid ? 8'h1 << _GEN : 8'h0);
wire _GEN_1 = io_alloc_ready | ~valid & io_free_valid;
always @(posedge clock) begin
if (reset) begin
bitmap <= 8'hFF;
select <= 3'h0;
valid <= 1'h1;
end
else begin
if (io_alloc_ready | io_free_valid) begin
bitmap <= bitmap1;
valid <= (|bitmap) & ~({1'h0, {1'h0, {1'h0, bitmap[0]} + {1'h0, bitmap[1]}} + {1'h0, {1'h0, bitmap[2]} + {1'h0, bitmap[3]}}} + {1'h0, {1'h0, {1'h0, bitmap[4]} + {1'h0, bitmap[5]}} + {1'h0, {1'h0, bitmap[6]} + {1'h0, bitmap[7]}}} == 4'h1 & io_alloc_ready) | io_free_valid;
end
if (_GEN_1)
select <= bitmap1[0] ? 3'h0 : bitmap1[1] ? 3'h1 : bitmap1[2] ? 3'h2 : bitmap1[3] ? 3'h3 : bitmap1[4] ? 3'h4 : bitmap1[5] ? 3'h5 : {2'h3, ~(bitmap1[6])};
end
REG <= _GEN_1;
end
assign io_alloc_valid = valid;
assign io_alloc_bits = select;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module data_40x37(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [36:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [36:0] W0_data
);
reg [36:0] Memory[0:39];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 37'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
} | module ClockCrossingReg_w32(
input clock,
input [31:0] io_d,
output [31:0] io_q,
input io_en
);
reg [31:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.internal.firrtl.KnownWidth
import chisel3.util.{Cat, Valid}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.property
/** Base JTAG shifter IO, viewed from input to shift register chain.
* Can be chained together.
*/
class ShifterIO extends Bundle {
val shift = Bool() // advance the scan chain on clock high
val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB
val capture = Bool() // high in the CaptureIR/DR state when this chain is selected
val update = Bool() // high in the UpdateIR/DR state when this chain is selected
/** Sets a output shifter IO's control signals from a input shifter IO's control signals.
*/
def chainControlFrom(in: ShifterIO): Unit = {
shift := in.shift
capture := in.capture
update := in.update
}
}
trait ChainIO extends Bundle {
val chainIn = Input(new ShifterIO)
val chainOut = Output(new ShifterIO)
}
class Capture[+T <: Data](gen: T) extends Bundle {
val bits = Input(gen) // data to capture, should be always valid
val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge
}
object Capture {
def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)
}
/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain
* IO.
*/
trait Chain extends Module {
val io: ChainIO
}
/** One-element shift register, data register for bypass mode.
*
* Implements Clause 10.
*/
class JtagBypassChain(implicit val p: Parameters) extends Chain {
class ModIO extends ChainIO
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val reg = Reg(Bool()) // 10.1.1a single shift register stage
io.chainOut.data := reg
property.cover(io.chainIn.capture, "bypass_chain_capture", "JTAG; bypass_chain_capture; This Bypass Chain captured data")
when (io.chainIn.capture) {
reg := false.B // 10.1.1b capture logic 0 on TCK rising
} .elsewhen (io.chainIn.shift) {
reg := io.chainIn.data
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object JtagBypassChain {
def apply()(implicit p: Parameters) = new JtagBypassChain
}
/** Simple shift register with parallel capture only, for read-only data registers.
*
* Number of stages is the number of bits in gen, which must have a known width.
*
* Useful notes:
* 7.2.1c shifter shifts on TCK rising edge
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
*/
class CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {
override def desiredName = s"CaptureChain_${gen.typeName}"
class ModIO extends ChainIO {
val capture = Capture(gen)
}
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val n = DataMirror.widthOf(gen) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $gen"); -1 // TODO: remove -1 type hack
}
val regs = (0 until n) map (x => Reg(Bool()))
io.chainOut.data := regs(0)
property.cover(io.chainIn.capture, "chain_capture", "JTAG; chain_capture; This Chain captured data")
when (io.chainIn.capture) {
(0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))
io.capture.capture := true.B
} .elsewhen (io.chainIn.shift) {
regs(n-1) := io.chainIn.data
(0 until n-1) map (x => regs(x) := regs(x+1))
io.capture.capture := false.B
} .otherwise {
io.capture.capture := false.B
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object CaptureChain {
def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)
}
/** Simple shift register with parallel capture and update. Useful for general instruction and data
* scan registers.
*
* Number of stages is the max number of bits in genCapture and genUpdate, both of which must have
* known widths. If there is a width mismatch, the unused most significant bits will be zero.
*
* Useful notes:
* 7.2.1c shifter shifts on TCK rising edge
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
*/
class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {
override def desiredName = s"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}"
class ModIO extends ChainIO {
val capture = Capture(genCapture)
val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after
}
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val captureWidth = DataMirror.widthOf(genCapture) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $genCapture"); -1 // TODO: remove -1 type hack
}
val updateWidth = DataMirror.widthOf(genUpdate) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $genUpdate"); -1 // TODO: remove -1 type hack
}
val n = math.max(captureWidth, updateWidth)
val regs = (0 until n) map (x => Reg(Bool()))
io.chainOut.data := regs(0)
val updateBits = Cat(regs.reverse)(updateWidth-1, 0)
io.update.bits := updateBits.asTypeOf(io.update.bits)
val captureBits = io.capture.bits.asUInt
property.cover(io.chainIn.capture, "chain_capture", "JTAG;chain_capture; This Chain captured data")
property.cover(io.chainIn.capture, "chain_update", "JTAG;chain_update; This Chain updated data")
when (io.chainIn.capture) {
(0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))
(captureWidth until n) map (x => regs(x) := 0.U)
io.capture.capture := true.B
io.update.valid := false.B
} .elsewhen (io.chainIn.update) {
io.capture.capture := false.B
io.update.valid := true.B
} .elsewhen (io.chainIn.shift) {
regs(n-1) := io.chainIn.data
(0 until n-1) map (x => regs(x) := regs(x+1))
io.capture.capture := false.B
io.update.valid := false.B
} .otherwise {
io.capture.capture := false.B
io.update.valid := false.B
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object CaptureUpdateChain {
/** Capture-update chain with matching capture and update types.
*/
def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)
def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =
new CaptureUpdateChain(genCapture, genUpdate)
} | module CaptureChain_JTAGIdcodeBundle(
input clock,
input reset,
input io_chainIn_shift,
input io_chainIn_data,
input io_chainIn_capture,
input io_chainIn_update,
output io_chainOut_data
);
reg regs_0;
reg regs_1;
reg regs_2;
reg regs_3;
reg regs_4;
reg regs_5;
reg regs_6;
reg regs_7;
reg regs_8;
reg regs_9;
reg regs_10;
reg regs_11;
reg regs_12;
reg regs_13;
reg regs_14;
reg regs_15;
reg regs_16;
reg regs_17;
reg regs_18;
reg regs_19;
reg regs_20;
reg regs_21;
reg regs_22;
reg regs_23;
reg regs_24;
reg regs_25;
reg regs_26;
reg regs_27;
reg regs_28;
reg regs_29;
reg regs_30;
reg regs_31;
always @(posedge clock) begin
if (io_chainIn_capture) begin
regs_0 <= 1'h1;
regs_1 <= 1'h0;
regs_2 <= 1'h0;
regs_3 <= 1'h0;
regs_4 <= 1'h0;
regs_5 <= 1'h0;
regs_6 <= 1'h0;
regs_7 <= 1'h0;
regs_8 <= 1'h0;
regs_9 <= 1'h0;
regs_10 <= 1'h0;
regs_11 <= 1'h0;
regs_12 <= 1'h0;
regs_13 <= 1'h0;
regs_14 <= 1'h0;
regs_15 <= 1'h0;
regs_16 <= 1'h0;
regs_17 <= 1'h0;
regs_18 <= 1'h0;
regs_19 <= 1'h0;
regs_20 <= 1'h0;
regs_21 <= 1'h0;
regs_22 <= 1'h0;
regs_23 <= 1'h0;
regs_24 <= 1'h0;
regs_25 <= 1'h0;
regs_26 <= 1'h0;
regs_27 <= 1'h0;
regs_28 <= 1'h0;
regs_29 <= 1'h0;
regs_30 <= 1'h0;
regs_31 <= 1'h0;
end
else if (io_chainIn_shift) begin
regs_0 <= regs_1;
regs_1 <= regs_2;
regs_2 <= regs_3;
regs_3 <= regs_4;
regs_4 <= regs_5;
regs_5 <= regs_6;
regs_6 <= regs_7;
regs_7 <= regs_8;
regs_8 <= regs_9;
regs_9 <= regs_10;
regs_10 <= regs_11;
regs_11 <= regs_12;
regs_12 <= regs_13;
regs_13 <= regs_14;
regs_14 <= regs_15;
regs_15 <= regs_16;
regs_16 <= regs_17;
regs_17 <= regs_18;
regs_18 <= regs_19;
regs_19 <= regs_20;
regs_20 <= regs_21;
regs_21 <= regs_22;
regs_22 <= regs_23;
regs_23 <= regs_24;
regs_24 <= regs_25;
regs_25 <= regs_26;
regs_26 <= regs_27;
regs_27 <= regs_28;
regs_28 <= regs_29;
regs_29 <= regs_30;
regs_30 <= regs_31;
regs_31 <= io_chainIn_data;
end
end
assign io_chainOut_data = regs_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomLoopPredictorParams(
nWays: Int = 4,
threshold: Int = 7
)
class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tagSz = 10
override val nSets = 16
class LoopMeta extends Bundle {
val s_cnt = UInt(10.W)
}
class LoopEntry extends Bundle {
val tag = UInt(tagSz.W)
val conf = UInt(3.W)
val age = UInt(3.W)
val p_cnt = UInt(10.W)
val s_cnt = UInt(10.W)
}
class LoopBranchPredictorColumn extends Module {
val io = IO(new Bundle {
val f2_req_valid = Input(Bool())
val f2_req_idx = Input(UInt())
val f3_req_fire = Input(Bool())
val f3_pred_in = Input(Bool())
val f3_pred = Output(Bool())
val f3_meta = Output(new LoopMeta)
val update_mispredict = Input(Bool())
val update_repair = Input(Bool())
val update_idx = Input(UInt())
val update_resolve_dir = Input(Bool())
val update_meta = Input(new LoopMeta)
})
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val entries = Reg(Vec(nSets, new LoopEntry))
val f2_entry = WireInit(entries(io.f2_req_idx))
when (io.update_repair && io.update_idx === io.f2_req_idx) {
f2_entry.s_cnt := io.update_meta.s_cnt
} .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) {
f2_entry.s_cnt := 0.U
}
val f3_entry = RegNext(f2_entry)
val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx),
io.update_meta.s_cnt,
f3_entry.s_cnt)
val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)))
io.f3_pred := io.f3_pred_in
io.f3_meta.s_cnt := f3_scnt
when (f3_entry.tag === f3_tag) {
when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) {
io.f3_pred := !io.f3_pred_in
}
}
val f4_fire = RegNext(io.f3_req_fire)
val f4_entry = RegNext(f3_entry)
val f4_tag = RegNext(f3_tag)
val f4_scnt = RegNext(f3_scnt)
val f4_idx = RegNext(RegNext(io.f2_req_idx))
when (f4_fire) {
when (f4_entry.tag === f4_tag) {
when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) {
entries(f4_idx).age := 7.U
entries(f4_idx).s_cnt := 0.U
} .otherwise {
entries(f4_idx).s_cnt := f4_scnt + 1.U
entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U)
}
}
}
val entry = entries(io.update_idx)
val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))
val tag_match = entry.tag === tag
val ctr_match = entry.p_cnt === io.update_meta.s_cnt
val wentry = WireInit(entry)
when (io.update_mispredict && !doing_reset) {
// Learned, tag match -> decrement confidence
when (entry.conf === 7.U && tag_match) {
wentry.s_cnt := 0.U
wentry.conf := 0.U
// Learned, no tag match -> do nothing? Don't evict super-confident entries?
} .elsewhen (entry.conf === 7.U && !tag_match) {
// Confident, tag match, ctr_match -> increment confidence, reset counter
} .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) {
wentry.conf := entry.conf + 1.U
wentry.s_cnt := 0.U
// Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter
} .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) {
wentry.conf := 0.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
// Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong
} .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) {
wentry.tag := tag
wentry.conf := 1.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
// Confident, no tag match, age > 0 -> decrement age
} .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) {
wentry.age := entry.age - 1.U
// Unconfident, tag match, ctr match -> increment confidence
} .elsewhen (entry.conf === 0.U && tag_match && ctr_match) {
wentry.conf := 1.U
wentry.age := 7.U
wentry.s_cnt := 0.U
// Unconfident, tag match, no ctr match -> set previous counter
} .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) {
wentry.p_cnt := io.update_meta.s_cnt
wentry.age := 7.U
wentry.s_cnt := 0.U
// Unconfident, no tag match -> set previous counter and tag
} .elsewhen (entry.conf === 0.U && !tag_match) {
wentry.tag := tag
wentry.conf := 1.U
wentry.age := 7.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
}
entries(io.update_idx) := wentry
} .elsewhen (io.update_repair && !doing_reset) {
when (tag_match && !(f4_fire && io.update_idx === f4_idx)) {
wentry.s_cnt := io.update_meta.s_cnt
entries(io.update_idx) := wentry
}
}
when (doing_reset) {
entries(reset_idx) := (0.U).asTypeOf(new LoopEntry)
}
}
val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) }
val mems = Nil // TODO fix
val f3_meta = Wire(Vec(bankWidth, new LoopMeta))
override val metaSz = f3_meta.asUInt.getWidth
val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta))
for (w <- 0 until bankWidth) {
columns(w).io.f2_req_valid := s2_valid
columns(w).io.f2_req_idx := s2_idx
columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire &&
RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br))
columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken
io.resp.f3(w).taken := columns(w).io.f3_pred
columns(w).io.update_mispredict := (s1_update.valid &&
s1_update.bits.br_mask(w) &&
s1_update.bits.is_mispredict_update &&
s1_update.bits.cfi_mispredicted)
columns(w).io.update_repair := (s1_update.valid &&
s1_update.bits.br_mask(w) &&
s1_update.bits.is_repair_update)
columns(w).io.update_idx := s1_update_idx
columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken
columns(w).io.update_meta := update_meta(w)
f3_meta(w) := columns(w).io.f3_meta
}
io.f3_meta := f3_meta.asUInt
} | module LoopBranchPredictorColumn(
input clock,
input reset,
input [36:0] io_f2_req_idx,
input io_f3_req_fire,
input io_f3_pred_in,
output io_f3_pred,
output [9:0] io_f3_meta_s_cnt,
input io_update_mispredict,
input io_update_repair,
input [36:0] io_update_idx,
input [9:0] io_update_meta_s_cnt
);
reg doing_reset;
reg [3:0] reset_idx;
reg [9:0] entries_0_tag;
reg [2:0] entries_0_conf;
reg [2:0] entries_0_age;
reg [9:0] entries_0_p_cnt;
reg [9:0] entries_0_s_cnt;
reg [9:0] entries_1_tag;
reg [2:0] entries_1_conf;
reg [2:0] entries_1_age;
reg [9:0] entries_1_p_cnt;
reg [9:0] entries_1_s_cnt;
reg [9:0] entries_2_tag;
reg [2:0] entries_2_conf;
reg [2:0] entries_2_age;
reg [9:0] entries_2_p_cnt;
reg [9:0] entries_2_s_cnt;
reg [9:0] entries_3_tag;
reg [2:0] entries_3_conf;
reg [2:0] entries_3_age;
reg [9:0] entries_3_p_cnt;
reg [9:0] entries_3_s_cnt;
reg [9:0] entries_4_tag;
reg [2:0] entries_4_conf;
reg [2:0] entries_4_age;
reg [9:0] entries_4_p_cnt;
reg [9:0] entries_4_s_cnt;
reg [9:0] entries_5_tag;
reg [2:0] entries_5_conf;
reg [2:0] entries_5_age;
reg [9:0] entries_5_p_cnt;
reg [9:0] entries_5_s_cnt;
reg [9:0] entries_6_tag;
reg [2:0] entries_6_conf;
reg [2:0] entries_6_age;
reg [9:0] entries_6_p_cnt;
reg [9:0] entries_6_s_cnt;
reg [9:0] entries_7_tag;
reg [2:0] entries_7_conf;
reg [2:0] entries_7_age;
reg [9:0] entries_7_p_cnt;
reg [9:0] entries_7_s_cnt;
reg [9:0] entries_8_tag;
reg [2:0] entries_8_conf;
reg [2:0] entries_8_age;
reg [9:0] entries_8_p_cnt;
reg [9:0] entries_8_s_cnt;
reg [9:0] entries_9_tag;
reg [2:0] entries_9_conf;
reg [2:0] entries_9_age;
reg [9:0] entries_9_p_cnt;
reg [9:0] entries_9_s_cnt;
reg [9:0] entries_10_tag;
reg [2:0] entries_10_conf;
reg [2:0] entries_10_age;
reg [9:0] entries_10_p_cnt;
reg [9:0] entries_10_s_cnt;
reg [9:0] entries_11_tag;
reg [2:0] entries_11_conf;
reg [2:0] entries_11_age;
reg [9:0] entries_11_p_cnt;
reg [9:0] entries_11_s_cnt;
reg [9:0] entries_12_tag;
reg [2:0] entries_12_conf;
reg [2:0] entries_12_age;
reg [9:0] entries_12_p_cnt;
reg [9:0] entries_12_s_cnt;
reg [9:0] entries_13_tag;
reg [2:0] entries_13_conf;
reg [2:0] entries_13_age;
reg [9:0] entries_13_p_cnt;
reg [9:0] entries_13_s_cnt;
reg [9:0] entries_14_tag;
reg [2:0] entries_14_conf;
reg [2:0] entries_14_age;
reg [9:0] entries_14_p_cnt;
reg [9:0] entries_14_s_cnt;
reg [9:0] entries_15_tag;
reg [2:0] entries_15_conf;
reg [2:0] entries_15_age;
reg [9:0] entries_15_p_cnt;
reg [9:0] entries_15_s_cnt;
reg [9:0] f3_entry_tag;
reg [2:0] f3_entry_conf;
reg [2:0] f3_entry_age;
reg [9:0] f3_entry_p_cnt;
reg [9:0] f3_entry_s_cnt;
reg [36:0] f3_scnt_REG;
wire [9:0] f3_scnt = io_update_repair & io_update_idx == f3_scnt_REG ? io_update_meta_s_cnt : f3_entry_s_cnt;
reg [9:0] f3_tag;
reg f4_fire;
reg [9:0] f4_entry_tag;
reg [2:0] f4_entry_conf;
reg [2:0] f4_entry_age;
reg [9:0] f4_entry_p_cnt;
reg [9:0] f4_tag;
reg [9:0] f4_scnt;
reg [36:0] f4_idx_REG;
reg [36:0] f4_idx;
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}};
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}};
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}};
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}};
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}};
wire _GEN_4 = io_update_idx == io_f2_req_idx;
wire _GEN_5 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf);
wire [9:0] _GEN_6 = _GEN_5 ? 10'h0 : f4_scnt + 10'h1;
wire _GEN_7 = f4_fire & f4_entry_tag == f4_tag;
wire [2:0] _GEN_8 = _GEN_5 | (&f4_entry_age) ? 3'h7 : f4_entry_age + 3'h1;
wire [9:0] _GEN_9 = _GEN[io_update_idx[3:0]];
wire [2:0] _GEN_10 = _GEN_0[io_update_idx[3:0]];
wire [2:0] _GEN_11 = _GEN_1[io_update_idx[3:0]];
wire [9:0] _GEN_12 = _GEN_2[io_update_idx[3:0]];
wire [9:0] _GEN_13 = _GEN_3[io_update_idx[3:0]];
wire tag_match = _GEN_9 == io_update_idx[13:4];
wire ctr_match = _GEN_12 == io_update_meta_s_cnt;
wire _GEN_14 = io_update_mispredict & ~doing_reset;
wire _GEN_15 = (&_GEN_10) & tag_match;
wire _GEN_16 = _GEN_9 != io_update_idx[13:4];
wire _GEN_17 = (&_GEN_10) & _GEN_16;
wire _GEN_18 = (|_GEN_10) & tag_match;
wire _GEN_19 = _GEN_18 & ctr_match;
wire [2:0] _wentry_conf_T = _GEN_10 + 3'h1;
wire _GEN_20 = _GEN_12 != io_update_meta_s_cnt;
wire _GEN_21 = _GEN_18 & _GEN_20;
wire _GEN_22 = (|_GEN_10) & _GEN_16;
wire _GEN_23 = _GEN_22 & ~(|_GEN_11);
wire _GEN_24 = _GEN_22 & (|_GEN_11);
wire [2:0] _wentry_age_T = _GEN_11 - 3'h1;
wire _GEN_25 = ~(|_GEN_10) & tag_match;
wire _GEN_26 = _GEN_25 & ctr_match;
wire _GEN_27 = _GEN_25 & _GEN_20;
wire _GEN_28 = ~(|_GEN_10) & _GEN_16;
wire _GEN_29 = _GEN_26 | _GEN_27;
wire _GEN_30 = _GEN_19 | _GEN_21;
wire _GEN_31 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_30 | ~(_GEN_23 | ~(_GEN_24 | _GEN_29 | ~_GEN_28));
wire _GEN_32 = _GEN_23 | ~(_GEN_24 | ~(_GEN_26 | ~(_GEN_27 | ~_GEN_28)));
wire _GEN_33 = _GEN_27 | _GEN_28;
wire _GEN_34 = _GEN_26 | _GEN_33;
wire _GEN_35 = _GEN_21 | _GEN_23;
wire _GEN_36 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_19 | _GEN_35;
wire _GEN_37 = _GEN_15 | ~(_GEN_17 | ~(_GEN_30 | _GEN_23 | ~(_GEN_24 | ~(_GEN_29 | _GEN_28))));
wire _GEN_38 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_19 | ~(_GEN_35 | ~(_GEN_24 | _GEN_26 | ~_GEN_33));
wire _GEN_39 = io_update_repair & ~doing_reset;
wire _GEN_40 = tag_match & ~(f4_fire & io_update_idx == f4_idx);
wire _GEN_41 = _GEN_39 & _GEN_40;
wire _GEN_42 = _GEN_14 | _GEN_39 & _GEN_40;
always @(posedge clock) begin
if (reset) begin
doing_reset <= 1'h1;
reset_idx <= 4'h0;
end
else begin
doing_reset <= ~(&reset_idx) & doing_reset;
reset_idx <= reset_idx + {3'h0, doing_reset};
end
if (doing_reset & reset_idx == 4'h0) begin
entries_0_tag <= 10'h0;
entries_0_conf <= 3'h0;
entries_0_age <= 3'h0;
entries_0_p_cnt <= 10'h0;
entries_0_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h0) begin
if (_GEN_31)
entries_0_tag <= _GEN_9;
else
entries_0_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_0_conf <= 3'h0;
else if (_GEN_17)
entries_0_conf <= _GEN_10;
else if (_GEN_19)
entries_0_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_0_conf <= 3'h0;
else if (_GEN_32)
entries_0_conf <= 3'h1;
else
entries_0_conf <= _GEN_10;
end
else
entries_0_conf <= _GEN_10;
if (_GEN_36)
entries_0_age <= _GEN_11;
else if (_GEN_24)
entries_0_age <= _wentry_age_T;
else if (_GEN_34)
entries_0_age <= 3'h7;
else
entries_0_age <= _GEN_11;
if (_GEN_38)
entries_0_p_cnt <= _GEN_12;
else
entries_0_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_0_s_cnt <= 10'h0;
else
entries_0_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_0_s_cnt <= io_update_meta_s_cnt;
else
entries_0_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h0) begin
entries_0_age <= _GEN_8;
entries_0_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h1) begin
entries_1_tag <= 10'h0;
entries_1_conf <= 3'h0;
entries_1_age <= 3'h0;
entries_1_p_cnt <= 10'h0;
entries_1_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h1) begin
if (_GEN_31)
entries_1_tag <= _GEN_9;
else
entries_1_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_1_conf <= 3'h0;
else if (_GEN_17)
entries_1_conf <= _GEN_10;
else if (_GEN_19)
entries_1_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_1_conf <= 3'h0;
else if (_GEN_32)
entries_1_conf <= 3'h1;
else
entries_1_conf <= _GEN_10;
end
else
entries_1_conf <= _GEN_10;
if (_GEN_36)
entries_1_age <= _GEN_11;
else if (_GEN_24)
entries_1_age <= _wentry_age_T;
else if (_GEN_34)
entries_1_age <= 3'h7;
else
entries_1_age <= _GEN_11;
if (_GEN_38)
entries_1_p_cnt <= _GEN_12;
else
entries_1_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_1_s_cnt <= 10'h0;
else
entries_1_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_1_s_cnt <= io_update_meta_s_cnt;
else
entries_1_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h1) begin
entries_1_age <= _GEN_8;
entries_1_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h2) begin
entries_2_tag <= 10'h0;
entries_2_conf <= 3'h0;
entries_2_age <= 3'h0;
entries_2_p_cnt <= 10'h0;
entries_2_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h2) begin
if (_GEN_31)
entries_2_tag <= _GEN_9;
else
entries_2_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_2_conf <= 3'h0;
else if (_GEN_17)
entries_2_conf <= _GEN_10;
else if (_GEN_19)
entries_2_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_2_conf <= 3'h0;
else if (_GEN_32)
entries_2_conf <= 3'h1;
else
entries_2_conf <= _GEN_10;
end
else
entries_2_conf <= _GEN_10;
if (_GEN_36)
entries_2_age <= _GEN_11;
else if (_GEN_24)
entries_2_age <= _wentry_age_T;
else if (_GEN_34)
entries_2_age <= 3'h7;
else
entries_2_age <= _GEN_11;
if (_GEN_38)
entries_2_p_cnt <= _GEN_12;
else
entries_2_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_2_s_cnt <= 10'h0;
else
entries_2_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_2_s_cnt <= io_update_meta_s_cnt;
else
entries_2_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h2) begin
entries_2_age <= _GEN_8;
entries_2_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h3) begin
entries_3_tag <= 10'h0;
entries_3_conf <= 3'h0;
entries_3_age <= 3'h0;
entries_3_p_cnt <= 10'h0;
entries_3_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h3) begin
if (_GEN_31)
entries_3_tag <= _GEN_9;
else
entries_3_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_3_conf <= 3'h0;
else if (_GEN_17)
entries_3_conf <= _GEN_10;
else if (_GEN_19)
entries_3_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_3_conf <= 3'h0;
else if (_GEN_32)
entries_3_conf <= 3'h1;
else
entries_3_conf <= _GEN_10;
end
else
entries_3_conf <= _GEN_10;
if (_GEN_36)
entries_3_age <= _GEN_11;
else if (_GEN_24)
entries_3_age <= _wentry_age_T;
else if (_GEN_34)
entries_3_age <= 3'h7;
else
entries_3_age <= _GEN_11;
if (_GEN_38)
entries_3_p_cnt <= _GEN_12;
else
entries_3_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_3_s_cnt <= 10'h0;
else
entries_3_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_3_s_cnt <= io_update_meta_s_cnt;
else
entries_3_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h3) begin
entries_3_age <= _GEN_8;
entries_3_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h4) begin
entries_4_tag <= 10'h0;
entries_4_conf <= 3'h0;
entries_4_age <= 3'h0;
entries_4_p_cnt <= 10'h0;
entries_4_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h4) begin
if (_GEN_31)
entries_4_tag <= _GEN_9;
else
entries_4_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_4_conf <= 3'h0;
else if (_GEN_17)
entries_4_conf <= _GEN_10;
else if (_GEN_19)
entries_4_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_4_conf <= 3'h0;
else if (_GEN_32)
entries_4_conf <= 3'h1;
else
entries_4_conf <= _GEN_10;
end
else
entries_4_conf <= _GEN_10;
if (_GEN_36)
entries_4_age <= _GEN_11;
else if (_GEN_24)
entries_4_age <= _wentry_age_T;
else if (_GEN_34)
entries_4_age <= 3'h7;
else
entries_4_age <= _GEN_11;
if (_GEN_38)
entries_4_p_cnt <= _GEN_12;
else
entries_4_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_4_s_cnt <= 10'h0;
else
entries_4_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_4_s_cnt <= io_update_meta_s_cnt;
else
entries_4_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h4) begin
entries_4_age <= _GEN_8;
entries_4_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h5) begin
entries_5_tag <= 10'h0;
entries_5_conf <= 3'h0;
entries_5_age <= 3'h0;
entries_5_p_cnt <= 10'h0;
entries_5_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h5) begin
if (_GEN_31)
entries_5_tag <= _GEN_9;
else
entries_5_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_5_conf <= 3'h0;
else if (_GEN_17)
entries_5_conf <= _GEN_10;
else if (_GEN_19)
entries_5_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_5_conf <= 3'h0;
else if (_GEN_32)
entries_5_conf <= 3'h1;
else
entries_5_conf <= _GEN_10;
end
else
entries_5_conf <= _GEN_10;
if (_GEN_36)
entries_5_age <= _GEN_11;
else if (_GEN_24)
entries_5_age <= _wentry_age_T;
else if (_GEN_34)
entries_5_age <= 3'h7;
else
entries_5_age <= _GEN_11;
if (_GEN_38)
entries_5_p_cnt <= _GEN_12;
else
entries_5_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_5_s_cnt <= 10'h0;
else
entries_5_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_5_s_cnt <= io_update_meta_s_cnt;
else
entries_5_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h5) begin
entries_5_age <= _GEN_8;
entries_5_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h6) begin
entries_6_tag <= 10'h0;
entries_6_conf <= 3'h0;
entries_6_age <= 3'h0;
entries_6_p_cnt <= 10'h0;
entries_6_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h6) begin
if (_GEN_31)
entries_6_tag <= _GEN_9;
else
entries_6_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_6_conf <= 3'h0;
else if (_GEN_17)
entries_6_conf <= _GEN_10;
else if (_GEN_19)
entries_6_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_6_conf <= 3'h0;
else if (_GEN_32)
entries_6_conf <= 3'h1;
else
entries_6_conf <= _GEN_10;
end
else
entries_6_conf <= _GEN_10;
if (_GEN_36)
entries_6_age <= _GEN_11;
else if (_GEN_24)
entries_6_age <= _wentry_age_T;
else if (_GEN_34)
entries_6_age <= 3'h7;
else
entries_6_age <= _GEN_11;
if (_GEN_38)
entries_6_p_cnt <= _GEN_12;
else
entries_6_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_6_s_cnt <= 10'h0;
else
entries_6_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_6_s_cnt <= io_update_meta_s_cnt;
else
entries_6_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h6) begin
entries_6_age <= _GEN_8;
entries_6_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h7) begin
entries_7_tag <= 10'h0;
entries_7_conf <= 3'h0;
entries_7_age <= 3'h0;
entries_7_p_cnt <= 10'h0;
entries_7_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h7) begin
if (_GEN_31)
entries_7_tag <= _GEN_9;
else
entries_7_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_7_conf <= 3'h0;
else if (_GEN_17)
entries_7_conf <= _GEN_10;
else if (_GEN_19)
entries_7_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_7_conf <= 3'h0;
else if (_GEN_32)
entries_7_conf <= 3'h1;
else
entries_7_conf <= _GEN_10;
end
else
entries_7_conf <= _GEN_10;
if (_GEN_36)
entries_7_age <= _GEN_11;
else if (_GEN_24)
entries_7_age <= _wentry_age_T;
else if (_GEN_34)
entries_7_age <= 3'h7;
else
entries_7_age <= _GEN_11;
if (_GEN_38)
entries_7_p_cnt <= _GEN_12;
else
entries_7_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_7_s_cnt <= 10'h0;
else
entries_7_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_7_s_cnt <= io_update_meta_s_cnt;
else
entries_7_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h7) begin
entries_7_age <= _GEN_8;
entries_7_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h8) begin
entries_8_tag <= 10'h0;
entries_8_conf <= 3'h0;
entries_8_age <= 3'h0;
entries_8_p_cnt <= 10'h0;
entries_8_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h8) begin
if (_GEN_31)
entries_8_tag <= _GEN_9;
else
entries_8_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_8_conf <= 3'h0;
else if (_GEN_17)
entries_8_conf <= _GEN_10;
else if (_GEN_19)
entries_8_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_8_conf <= 3'h0;
else if (_GEN_32)
entries_8_conf <= 3'h1;
else
entries_8_conf <= _GEN_10;
end
else
entries_8_conf <= _GEN_10;
if (_GEN_36)
entries_8_age <= _GEN_11;
else if (_GEN_24)
entries_8_age <= _wentry_age_T;
else if (_GEN_34)
entries_8_age <= 3'h7;
else
entries_8_age <= _GEN_11;
if (_GEN_38)
entries_8_p_cnt <= _GEN_12;
else
entries_8_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_8_s_cnt <= 10'h0;
else
entries_8_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_8_s_cnt <= io_update_meta_s_cnt;
else
entries_8_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h8) begin
entries_8_age <= _GEN_8;
entries_8_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h9) begin
entries_9_tag <= 10'h0;
entries_9_conf <= 3'h0;
entries_9_age <= 3'h0;
entries_9_p_cnt <= 10'h0;
entries_9_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h9) begin
if (_GEN_31)
entries_9_tag <= _GEN_9;
else
entries_9_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_9_conf <= 3'h0;
else if (_GEN_17)
entries_9_conf <= _GEN_10;
else if (_GEN_19)
entries_9_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_9_conf <= 3'h0;
else if (_GEN_32)
entries_9_conf <= 3'h1;
else
entries_9_conf <= _GEN_10;
end
else
entries_9_conf <= _GEN_10;
if (_GEN_36)
entries_9_age <= _GEN_11;
else if (_GEN_24)
entries_9_age <= _wentry_age_T;
else if (_GEN_34)
entries_9_age <= 3'h7;
else
entries_9_age <= _GEN_11;
if (_GEN_38)
entries_9_p_cnt <= _GEN_12;
else
entries_9_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_9_s_cnt <= 10'h0;
else
entries_9_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_9_s_cnt <= io_update_meta_s_cnt;
else
entries_9_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h9) begin
entries_9_age <= _GEN_8;
entries_9_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hA) begin
entries_10_tag <= 10'h0;
entries_10_conf <= 3'h0;
entries_10_age <= 3'h0;
entries_10_p_cnt <= 10'h0;
entries_10_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hA) begin
if (_GEN_31)
entries_10_tag <= _GEN_9;
else
entries_10_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_10_conf <= 3'h0;
else if (_GEN_17)
entries_10_conf <= _GEN_10;
else if (_GEN_19)
entries_10_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_10_conf <= 3'h0;
else if (_GEN_32)
entries_10_conf <= 3'h1;
else
entries_10_conf <= _GEN_10;
end
else
entries_10_conf <= _GEN_10;
if (_GEN_36)
entries_10_age <= _GEN_11;
else if (_GEN_24)
entries_10_age <= _wentry_age_T;
else if (_GEN_34)
entries_10_age <= 3'h7;
else
entries_10_age <= _GEN_11;
if (_GEN_38)
entries_10_p_cnt <= _GEN_12;
else
entries_10_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_10_s_cnt <= 10'h0;
else
entries_10_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_10_s_cnt <= io_update_meta_s_cnt;
else
entries_10_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hA) begin
entries_10_age <= _GEN_8;
entries_10_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hB) begin
entries_11_tag <= 10'h0;
entries_11_conf <= 3'h0;
entries_11_age <= 3'h0;
entries_11_p_cnt <= 10'h0;
entries_11_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hB) begin
if (_GEN_31)
entries_11_tag <= _GEN_9;
else
entries_11_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_11_conf <= 3'h0;
else if (_GEN_17)
entries_11_conf <= _GEN_10;
else if (_GEN_19)
entries_11_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_11_conf <= 3'h0;
else if (_GEN_32)
entries_11_conf <= 3'h1;
else
entries_11_conf <= _GEN_10;
end
else
entries_11_conf <= _GEN_10;
if (_GEN_36)
entries_11_age <= _GEN_11;
else if (_GEN_24)
entries_11_age <= _wentry_age_T;
else if (_GEN_34)
entries_11_age <= 3'h7;
else
entries_11_age <= _GEN_11;
if (_GEN_38)
entries_11_p_cnt <= _GEN_12;
else
entries_11_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_11_s_cnt <= 10'h0;
else
entries_11_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_11_s_cnt <= io_update_meta_s_cnt;
else
entries_11_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hB) begin
entries_11_age <= _GEN_8;
entries_11_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hC) begin
entries_12_tag <= 10'h0;
entries_12_conf <= 3'h0;
entries_12_age <= 3'h0;
entries_12_p_cnt <= 10'h0;
entries_12_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hC) begin
if (_GEN_31)
entries_12_tag <= _GEN_9;
else
entries_12_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_12_conf <= 3'h0;
else if (_GEN_17)
entries_12_conf <= _GEN_10;
else if (_GEN_19)
entries_12_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_12_conf <= 3'h0;
else if (_GEN_32)
entries_12_conf <= 3'h1;
else
entries_12_conf <= _GEN_10;
end
else
entries_12_conf <= _GEN_10;
if (_GEN_36)
entries_12_age <= _GEN_11;
else if (_GEN_24)
entries_12_age <= _wentry_age_T;
else if (_GEN_34)
entries_12_age <= 3'h7;
else
entries_12_age <= _GEN_11;
if (_GEN_38)
entries_12_p_cnt <= _GEN_12;
else
entries_12_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_12_s_cnt <= 10'h0;
else
entries_12_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_12_s_cnt <= io_update_meta_s_cnt;
else
entries_12_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hC) begin
entries_12_age <= _GEN_8;
entries_12_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hD) begin
entries_13_tag <= 10'h0;
entries_13_conf <= 3'h0;
entries_13_age <= 3'h0;
entries_13_p_cnt <= 10'h0;
entries_13_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hD) begin
if (_GEN_31)
entries_13_tag <= _GEN_9;
else
entries_13_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_13_conf <= 3'h0;
else if (_GEN_17)
entries_13_conf <= _GEN_10;
else if (_GEN_19)
entries_13_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_13_conf <= 3'h0;
else if (_GEN_32)
entries_13_conf <= 3'h1;
else
entries_13_conf <= _GEN_10;
end
else
entries_13_conf <= _GEN_10;
if (_GEN_36)
entries_13_age <= _GEN_11;
else if (_GEN_24)
entries_13_age <= _wentry_age_T;
else if (_GEN_34)
entries_13_age <= 3'h7;
else
entries_13_age <= _GEN_11;
if (_GEN_38)
entries_13_p_cnt <= _GEN_12;
else
entries_13_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_13_s_cnt <= 10'h0;
else
entries_13_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_13_s_cnt <= io_update_meta_s_cnt;
else
entries_13_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hD) begin
entries_13_age <= _GEN_8;
entries_13_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hE) begin
entries_14_tag <= 10'h0;
entries_14_conf <= 3'h0;
entries_14_age <= 3'h0;
entries_14_p_cnt <= 10'h0;
entries_14_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hE) begin
if (_GEN_31)
entries_14_tag <= _GEN_9;
else
entries_14_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_14_conf <= 3'h0;
else if (_GEN_17)
entries_14_conf <= _GEN_10;
else if (_GEN_19)
entries_14_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_14_conf <= 3'h0;
else if (_GEN_32)
entries_14_conf <= 3'h1;
else
entries_14_conf <= _GEN_10;
end
else
entries_14_conf <= _GEN_10;
if (_GEN_36)
entries_14_age <= _GEN_11;
else if (_GEN_24)
entries_14_age <= _wentry_age_T;
else if (_GEN_34)
entries_14_age <= 3'h7;
else
entries_14_age <= _GEN_11;
if (_GEN_38)
entries_14_p_cnt <= _GEN_12;
else
entries_14_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_14_s_cnt <= 10'h0;
else
entries_14_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_14_s_cnt <= io_update_meta_s_cnt;
else
entries_14_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hE) begin
entries_14_age <= _GEN_8;
entries_14_s_cnt <= _GEN_6;
end
if (doing_reset & (&reset_idx)) begin
entries_15_tag <= 10'h0;
entries_15_conf <= 3'h0;
entries_15_age <= 3'h0;
entries_15_p_cnt <= 10'h0;
entries_15_s_cnt <= 10'h0;
end
else if (_GEN_42 & (&(io_update_idx[3:0]))) begin
if (_GEN_31)
entries_15_tag <= _GEN_9;
else
entries_15_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_15_conf <= 3'h0;
else if (_GEN_17)
entries_15_conf <= _GEN_10;
else if (_GEN_19)
entries_15_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_15_conf <= 3'h0;
else if (_GEN_32)
entries_15_conf <= 3'h1;
else
entries_15_conf <= _GEN_10;
end
else
entries_15_conf <= _GEN_10;
if (_GEN_36)
entries_15_age <= _GEN_11;
else if (_GEN_24)
entries_15_age <= _wentry_age_T;
else if (_GEN_34)
entries_15_age <= 3'h7;
else
entries_15_age <= _GEN_11;
if (_GEN_38)
entries_15_p_cnt <= _GEN_12;
else
entries_15_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_15_s_cnt <= 10'h0;
else
entries_15_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_15_s_cnt <= io_update_meta_s_cnt;
else
entries_15_s_cnt <= _GEN_13;
end
else if (_GEN_7 & (&(f4_idx[3:0]))) begin
entries_15_age <= _GEN_8;
entries_15_s_cnt <= _GEN_6;
end
f3_entry_tag <= _GEN[io_f2_req_idx[3:0]];
f3_entry_conf <= _GEN_0[io_f2_req_idx[3:0]];
f3_entry_age <= _GEN_1[io_f2_req_idx[3:0]];
f3_entry_p_cnt <= _GEN_2[io_f2_req_idx[3:0]];
f3_entry_s_cnt <= io_update_repair & _GEN_4 ? io_update_meta_s_cnt : io_update_mispredict & _GEN_4 ? 10'h0 : _GEN_3[io_f2_req_idx[3:0]];
f3_scnt_REG <= io_f2_req_idx;
f3_tag <= io_f2_req_idx[13:4];
f4_fire <= io_f3_req_fire;
f4_entry_tag <= f3_entry_tag;
f4_entry_conf <= f3_entry_conf;
f4_entry_age <= f3_entry_age;
f4_entry_p_cnt <= f3_entry_p_cnt;
f4_tag <= f3_tag;
f4_scnt <= f3_scnt;
f4_idx_REG <= io_f2_req_idx;
f4_idx <= f4_idx_REG;
end
assign io_f3_pred = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ^ io_f3_pred_in;
assign io_f3_meta_s_cnt = f3_scnt;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundRawFNToRecFN_e8_s24(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [9:0] io_in_sExp,
input [26:0] io_in_sig,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags
);
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 roundAnyRawFNToRecFN (
.io_invalidExc (io_invalidExc),
.io_in_isNaN (io_in_isNaN),
.io_in_isInf (io_in_isInf),
.io_in_isZero (io_in_isZero),
.io_in_sign (io_in_sign),
.io_in_sExp (io_in_sExp),
.io_in_sig (io_in_sig),
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomBTBParams(
nSets: Int = 128,
nWays: Int = 2,
offsetSz: Int = 13,
extendedNSets: Int = 128
)
class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
override val nWays = params.nWays
val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1
val offsetSz = params.offsetSz
val extendedNSets = params.extendedNSets
require(isPow2(nSets))
require(isPow2(extendedNSets) || extendedNSets == 0)
require(extendedNSets <= nSets)
require(extendedNSets >= 1)
class BTBEntry extends Bundle {
val offset = SInt(offsetSz.W)
val extended = Bool()
}
val btbEntrySz = offsetSz + 1
class BTBMeta extends Bundle {
val is_br = Bool()
val tag = UInt(tagSz.W)
}
val btbMetaSz = tagSz + 1
class BTBPredictMeta extends Bundle {
val write_way = UInt(log2Ceil(nWays).W)
}
val s1_meta = Wire(new BTBPredictMeta)
val f3_meta = RegNext(RegNext(s1_meta))
io.f3_meta := f3_meta.asUInt
override val metaSz = s1_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }
val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }
val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))
val mems = (((0 until nWays) map ({w:Int => Seq(
(f"btb_meta_way$w", nSets, bankWidth * btbMetaSz),
(f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended)))
val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })
val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })
val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)
val s1_req_tag = s1_idx >> log2Ceil(nSets)
val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))
val s1_is_br = Wire(Vec(bankWidth, Bool()))
val s1_is_jal = Wire(Vec(bankWidth, Bool()))
val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>
VecInit((0 until nWays) map { w =>
s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)
})
})
val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }
val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }
for (w <- 0 until bankWidth) {
val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)
val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)
s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)
s1_resp(w).bits := Mux(
entry_btb.extended,
s1_req_rebtb,
(s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)
s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br
s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br
io.resp.f2(w) := io.resp_in(0).f2(w)
io.resp.f3(w) := io.resp_in(0).f3(w)
when (RegNext(s1_hits(w))) {
io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))
io.resp.f2(w).is_br := RegNext(s1_is_br(w))
io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))
when (RegNext(s1_is_jal(w))) {
io.resp.f2(w).taken := true.B
}
}
when (RegNext(RegNext(s1_hits(w)))) {
io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)
io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)
io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)
when (RegNext(RegNext(s1_is_jal(w)))) {
io.resp.f3(w).taken := true.B
}
}
}
val alloc_way = if (nWays > 1) {
val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))
val l = log2Ceil(nWays)
val nChunks = (r_metas.getWidth + l - 1) / l
val chunks = (0 until nChunks) map { i =>
r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
}
chunks.reduce(_^_)
} else {
0.U
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
alloc_way)
val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)
val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt
val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt
val new_offset_value = (s1_update.bits.target.asSInt -
(s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)
val offset_is_extended = (new_offset_value > max_offset_value ||
new_offset_value < min_offset_value)
val s1_update_wbtb_data = Wire(new BTBEntry)
s1_update_wbtb_data.extended := offset_is_extended
s1_update_wbtb_data.offset := new_offset_value
val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &
Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))
val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &
(Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |
(Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)
)
)
val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))
for (w <- 0 until bankWidth) {
s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))
s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)
}
for (w <- 0 until nWays) {
when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {
btb(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),
VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wbtb_mask).asBools
)
meta(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),
VecInit(s1_update_wmeta_data.map(_.asUInt))),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wmeta_mask).asBools
)
}
}
when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {
ebtb.write(s1_update_idx, s1_update.bits.target)
}
} | module ebtb(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [39:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [39:0] W0_data
);
ebtb_ext ebtb_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Register File (Abstract class and Synthesizable RegFile)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import scala.collection.mutable.ArrayBuffer
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* IO bundle for a register read port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
}
/**
* IO bundle for the register write port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = UInt(addrWidth.W)
val data = UInt(dataWidth.W)
}
/**
* Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.
*/
object WritePort
{
def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)
(implicit p: Parameters): Valid[RegisterFileWritePort] = {
val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))
wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype
wport.bits.addr := enq.bits.uop.pdst
wport.bits.data := enq.bits.data
enq.ready := true.B
wport
}
}
/**
* Register file abstract class
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
abstract class RegisterFile(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?
(implicit p: Parameters) extends BoomModule
{
val io = IO(new BoomBundle {
val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))
val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))
})
private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)
private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer"
override def toString: String = BoomCoreStringPrefix(
"==" + type_str + " Regfile==",
"Num RF Read Ports : " + numReadPorts,
"Num RF Write Ports : " + numWritePorts,
"RF Cost (R+W)*(R+2W) : " + rf_cost,
"Bypassable Units : " + bypassableArray)
}
/**
* A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
class RegisterFileSynthesizable(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean])
(implicit p: Parameters)
extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)
{
// --------------------------------------------------------------
val regfile = Mem(numRegisters, UInt(registerWidth.W))
// --------------------------------------------------------------
// Read ports.
val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))
// Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).
val read_addrs = io.read_ports.map(p => RegNext(p.addr))
for (i <- 0 until numReadPorts) {
read_data(i) := regfile(read_addrs(i))
}
// --------------------------------------------------------------
// Bypass out of the ALU's write ports.
// We are assuming we cannot bypass a writer to a reader within the regfile memory
// for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.
// But since these bypasses are expensive, and not all write ports need to bypass their data,
// only perform the w->r bypass on a select number of write ports.
require (bypassableArray.length == io.write_ports.length)
if (bypassableArray.reduce(_||_)) {
val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()
io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }
for (i <- 0 until numReadPorts) {
val bypass_ens = bypassable_wports.map(x => x.valid &&
x.bits.addr === read_addrs(i))
val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))
io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))
}
} else {
for (i <- 0 until numReadPorts) {
io.read_ports(i).data := read_data(i)
}
}
// --------------------------------------------------------------
// Write ports.
for (wport <- io.write_ports) {
when (wport.valid) {
regfile(wport.bits.addr) := wport.bits.data
}
}
// ensure there is only 1 writer per register (unless to preg0)
if (numWritePorts > 1) {
for (i <- 0 until (numWritePorts - 1)) {
for (j <- (i + 1) until numWritePorts) {
assert(!io.write_ports(i).valid ||
!io.write_ports(j).valid ||
(io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||
(io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here
"[regfile] too many writers a register")
}
}
}
} | module regfile_48x65(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [64:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [64:0] R1_data,
input [5:0] R2_addr,
input R2_en,
input R2_clk,
output [64:0] R2_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [64:0] W0_data,
input [5:0] W1_addr,
input W1_en,
input W1_clk,
input [64:0] W1_data
);
reg [64:0] Memory[0:47];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 65'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 65'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.log2Up
import scala.math._
import consts._
class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val signedOut = Input(Bool())
val out = Output(Bits(intWidth.W))
val intExceptionFlags = Output(Bits(3.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)
val magGeOne = rawIn.sExp(expWidth)
val posExp = rawIn.sExp(expWidth - 1, 0)
val magJustBelowOne = !magGeOne && posExp.andR
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
/*------------------------------------------------------------------------
| Assuming the input floating-point value is not a NaN, its magnitude is
| at least 1, and it is not obviously so large as to lead to overflow,
| convert its significand to fixed-point (i.e., with the binary point in a
| fixed location). For a non-NaN input with a magnitude less than 1, this
| expression contrives to ensure that the integer bits of 'alignedSig'
| will all be zeros.
*------------------------------------------------------------------------*/
val shiftedSig =
(magGeOne ## rawIn.sig(sigWidth - 2, 0))<<
Mux(magGeOne,
rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),
0.U
)
val alignedSig =
(shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR
val unroundedInt = 0.U(intWidth.W) | alignedSig>>2
val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)
val roundIncr_near_even =
(magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||
(magJustBelowOne && alignedSig(1, 0).orR)
val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne
val roundIncr =
(roundingMode_near_even && roundIncr_near_even ) ||
(roundingMode_near_maxMag && roundIncr_near_maxMag) ||
((roundingMode_min || roundingMode_odd) &&
(rawIn.sign && common_inexact)) ||
(roundingMode_max && (!rawIn.sign && common_inexact))
val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)
val roundedInt =
Mux(roundIncr ^ rawIn.sign,
complUnroundedInt + 1.U,
complUnroundedInt
) | (roundingMode_odd && common_inexact)
val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)
//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM
//*** 'unroundedInt'?:
val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr
val common_overflow =
Mux(magGeOne,
(posExp >= intWidth.U) ||
Mux(io.signedOut,
Mux(rawIn.sign,
magGeOne_atOverflowEdge &&
(unroundedInt(intWidth - 2, 0).orR || roundIncr),
magGeOne_atOverflowEdge ||
((posExp === (intWidth - 2).U) && roundCarryBut2)
),
rawIn.sign ||
(magGeOne_atOverflowEdge &&
unroundedInt(intWidth - 2) && roundCarryBut2)
),
!io.signedOut && rawIn.sign && roundIncr
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val invalidExc = rawIn.isNaN || rawIn.isInf
val overflow = !invalidExc && common_overflow
val inexact = !invalidExc && !common_overflow && common_inexact
val excSign = !rawIn.isNaN && rawIn.sign
val excOut =
Mux((io.signedOut === excSign),
(BigInt(1)<<(intWidth - 1)).U,
0.U
) |
Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)
io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)
io.intExceptionFlags := invalidExc ## overflow ## inexact
} | module RecFNToIN_e11_s53_i64(
input [64:0] io_in,
input [2:0] io_roundingMode,
input io_signedOut,
output [63:0] io_out,
output [2:0] io_intExceptionFlags
);
wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61];
wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
wire roundingMode_odd = io_roundingMode == 3'h6;
wire [115:0] shiftedSig = {63'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[57:52] : 6'h0);
wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])};
wire common_inexact = io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61]));
wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6)) | magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] | magJustBelowOne) | (io_roundingMode == 3'h2 | roundingMode_odd) & io_in[64] & common_inexact | io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact;
wire [63:0] complUnroundedInt = {64{io_in[64]}} ^ shiftedSig[115:52];
wire [63:0] _roundedInt_T_3 = roundIncr ^ io_in[64] ? complUnroundedInt + 64'h1 : complUnroundedInt;
wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h3F;
wire roundCarryBut2 = (&(shiftedSig[113:52])) & roundIncr;
wire common_overflow = io_in[63] ? (|(io_in[62:58])) | (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((|(shiftedSig[114:52])) | roundIncr) : magGeOne_atOverflowEdge | io_in[62:52] == 11'h3E & roundCarryBut2) : io_in[64] | magGeOne_atOverflowEdge & shiftedSig[114] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr;
wire invalidExc = rawIn_isNaN | (&(io_in[63:62])) & ~(io_in[61]);
wire excSign = ~rawIn_isNaN & io_in[64];
assign io_out = invalidExc | common_overflow ? {io_signedOut == excSign, {63{~excSign}}} : {_roundedInt_T_3[63:1], _roundedInt_T_3[0] | roundingMode_odd & common_inexact};
assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact};
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.FPConstants._
import freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters}
import freechips.rocketchip.tile
import freechips.rocketchip.rocket
import freechips.rocketchip.util.uintToBitPat
import boom.v3.common._
import boom.v3.util.{ImmGenRm, ImmGenTyp}
/**
* FP Decoder for the FPU
*
* TODO get rid of this decoder and move into the Decode stage? Or the RRd stage?
* most of these signals are already created, just need to be translated
* to the Rocket FPU-speak
*/
class UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters
{
val io = IO(new Bundle {
val uopc = Input(Bits(UOPC_SZ.W))
val sigs = Output(new FPUCtrlSigs())
})
// TODO change N,Y,X to BitPat("b1"), BitPat("b0"), and BitPat("b?")
val N = false.B
val Y = true.B
val X = false.B
val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X)
val f_table: Array[(BitPat, List[BitPat])] =
// Note: not all of these signals are used or necessary, but we're
// constrained by the need to fit the rocket.FPU units' ctrl signals.
// swap12 fma
// | swap32 | div
// | | typeTagIn | | sqrt
// ldst | | | typeTagOut | | wflags
// | wen | | | | from_int | | |
// | | ren1 | | | | | to_int | | |
// | | | ren2 | | | | | | fastpipe |
// | | | | ren3 | | | | | | | | | |
// | | | | | | | | | | | | | | | |
Array(
BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N),
BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N),
BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N),
BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y),
BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y),
BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y),
BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N),
BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y),
BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y)
)
val d_table: Array[(BitPat, List[BitPat])] =
Array(
BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),
BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N),
BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),
BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y),
BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y),
BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y),
BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y),
BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y),
BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N),
BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y),
BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y)
)
// val insns = fLen match {
// case 32 => f_table
// case 64 => f_table ++ d_table
// }
val insns = f_table ++ d_table
val decoder = rocket.DecodeLogic(io.uopc, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,
s.div, s.sqrt, s.wflags)
sigs zip decoder map {case(s,d) => s := d}
s.vec := false.B
}
/**
* FP fused multiple add decoder for the FPU
*/
class FMADecoder extends Module
{
val io = IO(new Bundle {
val uopc = Input(UInt(UOPC_SZ.W))
val cmd = Output(UInt(2.W))
})
val default: List[BitPat] = List(BitPat("b??"))
val table: Array[(BitPat, List[BitPat])] =
Array(
BitPat(uopFADD_S) -> List(BitPat("b00")),
BitPat(uopFSUB_S) -> List(BitPat("b01")),
BitPat(uopFMUL_S) -> List(BitPat("b00")),
BitPat(uopFMADD_S) -> List(BitPat("b00")),
BitPat(uopFMSUB_S) -> List(BitPat("b01")),
BitPat(uopFNMADD_S) -> List(BitPat("b11")),
BitPat(uopFNMSUB_S) -> List(BitPat("b10")),
BitPat(uopFADD_D) -> List(BitPat("b00")),
BitPat(uopFSUB_D) -> List(BitPat("b01")),
BitPat(uopFMUL_D) -> List(BitPat("b00")),
BitPat(uopFMADD_D) -> List(BitPat("b00")),
BitPat(uopFMSUB_D) -> List(BitPat("b01")),
BitPat(uopFNMADD_D) -> List(BitPat("b11")),
BitPat(uopFNMSUB_D) -> List(BitPat("b10"))
)
val decoder = rocket.DecodeLogic(io.uopc, default, table)
val (cmd: UInt) :: Nil = decoder
io.cmd := cmd
}
/**
* Bundle representing data to be sent to the FPU
*/
class FpuReq()(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val rs1_data = Bits(65.W)
val rs2_data = Bits(65.W)
val rs3_data = Bits(65.W)
val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W)
}
/**
* FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat)
*/
class FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters
{
val io = IO(new Bundle {
val req = Flipped(new ValidIO(new FpuReq))
val resp = new ValidIO(new ExeUnitResp(65))
})
io.resp.bits := DontCare
// all FP units are padded out to the same latency for easy scheduling of the write port
val fpu_latency = dfmaLatency
val io_req = io.req.bits
val fp_decoder = Module(new UOPCodeFPUDecoder)
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
def fuInput(minT: Option[tile.FType]): tile.FPInput = {
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, minT)
req.in2 := unbox(io_req.rs2_data, tag, minT)
req.in3 := unbox(io_req.rs3_data, tag, minT)
when (fp_ctrl.swap23) { req.in3 := req.in2 }
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below
when (io_req.uop.uopc === uopFMV_X_W) {
req.fmt := 0.U
}
val fma_decoder = Module(new FMADecoder)
fma_decoder.io.uopc := io_req.uop.uopc
req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) | (!fp_ctrl.ren3 && ex_reg_inst(27))
req
}
val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D))
dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D)
dfma.io.in.bits := fuInput(Some(dfma.t))
val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S))
sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S)
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new tile.FPToInt)
fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint || (fp_ctrl.fastpipe && fp_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe),
fpiu.io.out.bits, fpu_latency-1)
val fpiu_result = Wire(new tile.FPResult)
fpiu_result.data := fpiu_out.bits.toint
fpiu_result.exc := fpiu_out.bits.exc
val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket
fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits
// Response (all FP units have been padded out to the same latency)
io.resp.valid := fpiu_out.valid ||
fpmu.io.out.valid ||
sfma.io.out.valid ||
dfma.io.out.valid
val fpu_out_data =
Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B),
Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B),
Mux(fpiu_out.valid, fpiu_result.data,
box(fpmu.io.out.bits.data, fpmu_double))))
val fpu_out_exc =
Mux(dfma.io.out.valid, dfma.io.out.bits.exc,
Mux(sfma.io.out.valid, sfma.io.out.bits.exc,
Mux(fpiu_out.valid, fpiu_result.exc,
fpmu.io.out.bits.exc)))
io.resp.bits.data := fpu_out_data
io.resp.bits.fflags.valid := io.resp.valid
io.resp.bits.fflags.bits.flags := fpu_out_exc
} | module FMADecoder(
input [6:0] io_uopc,
output [1:0] io_cmd
);
wire [5:0] decoder_decoded_invInputs = ~(io_uopc[5:0]);
assign io_cmd = {|{&{io_uopc[0], io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}, |{&{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}};
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.log2Up
import scala.math._
import consts._
class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val signedOut = Input(Bool())
val out = Output(Bits(intWidth.W))
val intExceptionFlags = Output(Bits(3.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)
val magGeOne = rawIn.sExp(expWidth)
val posExp = rawIn.sExp(expWidth - 1, 0)
val magJustBelowOne = !magGeOne && posExp.andR
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
/*------------------------------------------------------------------------
| Assuming the input floating-point value is not a NaN, its magnitude is
| at least 1, and it is not obviously so large as to lead to overflow,
| convert its significand to fixed-point (i.e., with the binary point in a
| fixed location). For a non-NaN input with a magnitude less than 1, this
| expression contrives to ensure that the integer bits of 'alignedSig'
| will all be zeros.
*------------------------------------------------------------------------*/
val shiftedSig =
(magGeOne ## rawIn.sig(sigWidth - 2, 0))<<
Mux(magGeOne,
rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),
0.U
)
val alignedSig =
(shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR
val unroundedInt = 0.U(intWidth.W) | alignedSig>>2
val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)
val roundIncr_near_even =
(magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||
(magJustBelowOne && alignedSig(1, 0).orR)
val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne
val roundIncr =
(roundingMode_near_even && roundIncr_near_even ) ||
(roundingMode_near_maxMag && roundIncr_near_maxMag) ||
((roundingMode_min || roundingMode_odd) &&
(rawIn.sign && common_inexact)) ||
(roundingMode_max && (!rawIn.sign && common_inexact))
val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)
val roundedInt =
Mux(roundIncr ^ rawIn.sign,
complUnroundedInt + 1.U,
complUnroundedInt
) | (roundingMode_odd && common_inexact)
val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)
//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM
//*** 'unroundedInt'?:
val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr
val common_overflow =
Mux(magGeOne,
(posExp >= intWidth.U) ||
Mux(io.signedOut,
Mux(rawIn.sign,
magGeOne_atOverflowEdge &&
(unroundedInt(intWidth - 2, 0).orR || roundIncr),
magGeOne_atOverflowEdge ||
((posExp === (intWidth - 2).U) && roundCarryBut2)
),
rawIn.sign ||
(magGeOne_atOverflowEdge &&
unroundedInt(intWidth - 2) && roundCarryBut2)
),
!io.signedOut && rawIn.sign && roundIncr
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val invalidExc = rawIn.isNaN || rawIn.isInf
val overflow = !invalidExc && common_overflow
val inexact = !invalidExc && !common_overflow && common_inexact
val excSign = !rawIn.isNaN && rawIn.sign
val excOut =
Mux((io.signedOut === excSign),
(BigInt(1)<<(intWidth - 1)).U,
0.U
) |
Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)
io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)
io.intExceptionFlags := invalidExc ## overflow ## inexact
} | module RecFNToIN_e11_s53_i32(
input [64:0] io_in,
input [2:0] io_roundingMode,
input io_signedOut,
output [2:0] io_intExceptionFlags
);
wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
wire [83:0] shiftedSig = {31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0);
wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])};
wire common_inexact = io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61]));
wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6)) | magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] | magJustBelowOne) | (io_roundingMode == 3'h2 | io_roundingMode == 3'h6) & io_in[64] & common_inexact | io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact;
wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h1F;
wire roundCarryBut2 = (&(shiftedSig[81:52])) & roundIncr;
wire common_overflow = io_in[63] ? (|(io_in[62:57])) | (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((|(shiftedSig[82:52])) | roundIncr) : magGeOne_atOverflowEdge | io_in[62:52] == 11'h1E & roundCarryBut2) : io_in[64] | magGeOne_atOverflowEdge & shiftedSig[82] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr;
wire invalidExc = (&(io_in[63:62])) & io_in[61] | (&(io_in[63:62])) & ~(io_in[61]);
assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact};
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module TageTable_1(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [2:0] io_f3_resp_1_bits_ctr,
output [1:0] io_f3_resp_1_bits_u,
output io_f3_resp_2_valid,
output [2:0] io_f3_resp_2_bits_ctr,
output [1:0] io_f3_resp_2_bits_u,
output io_f3_resp_3_valid,
output [2:0] io_f3_resp_3_bits_ctr,
output [1:0] io_f3_resp_3_bits_u,
input io_update_mask_0,
input io_update_mask_1,
input io_update_mask_2,
input io_update_mask_3,
input io_update_taken_0,
input io_update_taken_1,
input io_update_taken_2,
input io_update_taken_3,
input io_update_alloc_0,
input io_update_alloc_1,
input io_update_alloc_2,
input io_update_alloc_3,
input [2:0] io_update_old_ctr_0,
input [2:0] io_update_old_ctr_1,
input [2:0] io_update_old_ctr_2,
input [2:0] io_update_old_ctr_3,
input [39:0] io_update_pc,
input [63:0] io_update_hist,
input io_update_u_mask_0,
input io_update_u_mask_1,
input io_update_u_mask_2,
input io_update_u_mask_3,
input [1:0] io_update_u_0,
input [1:0] io_update_u_1,
input [1:0] io_update_u_2,
input [1:0] io_update_u_3
);
wire update_lo_wdata_3;
wire update_hi_wdata_3;
wire [2:0] update_wdata_3_ctr;
wire update_lo_wdata_2;
wire update_hi_wdata_2;
wire [2:0] update_wdata_2_ctr;
wire update_lo_wdata_1;
wire update_hi_wdata_1;
wire [2:0] update_wdata_1_ctr;
wire update_lo_wdata_0;
wire update_hi_wdata_0;
wire [2:0] update_wdata_0_ctr;
wire lo_us_MPORT_2_data_3;
wire lo_us_MPORT_2_data_2;
wire lo_us_MPORT_2_data_1;
wire lo_us_MPORT_2_data_0;
wire hi_us_MPORT_1_data_3;
wire hi_us_MPORT_1_data_2;
wire hi_us_MPORT_1_data_1;
wire hi_us_MPORT_1_data_0;
wire [10:0] table_MPORT_data_3;
wire [10:0] table_MPORT_data_2;
wire [10:0] table_MPORT_data_1;
wire [10:0] table_MPORT_data_0;
wire [43:0] _table_R0_data;
wire [3:0] _lo_us_R0_data;
wire [3:0] _hi_us_R0_data;
reg doing_reset;
reg [6:0] reset_idx;
wire [6:0] s1_hashed_idx = {io_f1_req_pc[9:7], io_f1_req_pc[6:3] ^ io_f1_req_ghist[3:0]};
reg [6:0] s2_tag;
reg io_f3_resp_0_valid_REG;
reg [1:0] io_f3_resp_0_bits_u_REG;
reg [2:0] io_f3_resp_0_bits_ctr_REG;
reg io_f3_resp_1_valid_REG;
reg [1:0] io_f3_resp_1_bits_u_REG;
reg [2:0] io_f3_resp_1_bits_ctr_REG;
reg io_f3_resp_2_valid_REG;
reg [1:0] io_f3_resp_2_bits_u_REG;
reg [2:0] io_f3_resp_2_bits_ctr_REG;
reg io_f3_resp_3_valid_REG;
reg [1:0] io_f3_resp_3_bits_u_REG;
reg [2:0] io_f3_resp_3_bits_ctr_REG;
reg [18:0] clear_u_ctr;
wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;
wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[18];
wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[18]);
wire [3:0] _GEN = io_update_pc[6:3] ^ io_update_hist[3:0];
wire [6:0] update_idx = {io_update_pc[9:7], _GEN};
wire [3:0] _GEN_0 = io_update_pc[13:10] ^ io_update_hist[3:0];
wire [6:0] update_tag = {io_update_pc[16:14], _GEN_0};
assign table_MPORT_data_0 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_0_ctr};
assign table_MPORT_data_1 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_1_ctr};
assign table_MPORT_data_2 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_2_ctr};
assign table_MPORT_data_3 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_3_ctr};
wire [6:0] _GEN_1 = {io_update_pc[9:7], _GEN};
wire _GEN_2 = doing_reset | doing_clear_u_hi;
assign hi_us_MPORT_1_data_0 = ~_GEN_2 & update_hi_wdata_0;
assign hi_us_MPORT_1_data_1 = ~_GEN_2 & update_hi_wdata_1;
assign hi_us_MPORT_1_data_2 = ~_GEN_2 & update_hi_wdata_2;
assign hi_us_MPORT_1_data_3 = ~_GEN_2 & update_hi_wdata_3;
wire [3:0] _GEN_3 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};
wire _GEN_4 = doing_reset | doing_clear_u_lo;
assign lo_us_MPORT_2_data_0 = ~_GEN_4 & update_lo_wdata_0;
assign lo_us_MPORT_2_data_1 = ~_GEN_4 & update_lo_wdata_1;
assign lo_us_MPORT_2_data_2 = ~_GEN_4 & update_lo_wdata_2;
assign lo_us_MPORT_2_data_3 = ~_GEN_4 & update_lo_wdata_3;
reg [6:0] wrbypass_tags_0;
reg [6:0] wrbypass_tags_1;
reg [6:0] wrbypass_idxs_0;
reg [6:0] wrbypass_idxs_1;
reg [2:0] wrbypass_0_0;
reg [2:0] wrbypass_0_1;
reg [2:0] wrbypass_0_2;
reg [2:0] wrbypass_0_3;
reg [2:0] wrbypass_1_0;
reg [2:0] wrbypass_1_1;
reg [2:0] wrbypass_1_2;
reg [2:0] wrbypass_1_3;
reg wrbypass_enq_idx;
wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;
wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;
wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;
wire [2:0] _GEN_6 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;
wire [2:0] _GEN_7 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;
wire [2:0] _GEN_8 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;
assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;
assign update_hi_wdata_0 = io_update_u_0[1];
assign update_lo_wdata_0 = io_update_u_0[0];
assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_6) ? 3'h7 : _GEN_6 + 3'h1) : _GEN_6 == 3'h0 ? 3'h0 : _GEN_6 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;
assign update_hi_wdata_1 = io_update_u_1[1];
assign update_lo_wdata_1 = io_update_u_1[0];
assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_7) ? 3'h7 : _GEN_7 + 3'h1) : _GEN_7 == 3'h0 ? 3'h0 : _GEN_7 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;
assign update_hi_wdata_2 = io_update_u_2[1];
assign update_lo_wdata_2 = io_update_u_2[0];
assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_8) ? 3'h7 : _GEN_8 + 3'h1) : _GEN_8 == 3'h0 ? 3'h0 : _GEN_8 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;
assign update_hi_wdata_3 = io_update_u_3[1];
assign update_lo_wdata_3 = io_update_u_3[0];
wire _GEN_9 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;
wire _GEN_10 = ~_GEN_9 | wrbypass_hit | wrbypass_enq_idx;
wire _GEN_11 = ~_GEN_9 | wrbypass_hit | ~wrbypass_enq_idx;
always @(posedge clock) begin
if (reset) begin
doing_reset <= 1'h1;
reset_idx <= 7'h0;
clear_u_ctr <= 19'h0;
wrbypass_enq_idx <= 1'h0;
end
else begin
doing_reset <= reset_idx != 7'h7F & doing_reset;
reset_idx <= reset_idx + {6'h0, doing_reset};
clear_u_ctr <= doing_reset ? 19'h1 : clear_u_ctr + 19'h1;
if (~_GEN_9 | wrbypass_hit) begin
end
else
wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;
end
s2_tag <= {io_f1_req_pc[16:14], io_f1_req_pc[13:10] ^ io_f1_req_ghist[3:0]};
io_f3_resp_0_valid_REG <= _table_R0_data[10] & _table_R0_data[9:3] == s2_tag & ~doing_reset;
io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};
io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];
io_f3_resp_1_valid_REG <= _table_R0_data[21] & _table_R0_data[20:14] == s2_tag & ~doing_reset;
io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};
io_f3_resp_1_bits_ctr_REG <= _table_R0_data[13:11];
io_f3_resp_2_valid_REG <= _table_R0_data[32] & _table_R0_data[31:25] == s2_tag & ~doing_reset;
io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};
io_f3_resp_2_bits_ctr_REG <= _table_R0_data[24:22];
io_f3_resp_3_valid_REG <= _table_R0_data[43] & _table_R0_data[42:36] == s2_tag & ~doing_reset;
io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};
io_f3_resp_3_bits_ctr_REG <= _table_R0_data[35:33];
if (_GEN_10) begin
end
else
wrbypass_tags_0 <= update_tag;
if (_GEN_11) begin
end
else
wrbypass_tags_1 <= update_tag;
if (_GEN_10) begin
end
else
wrbypass_idxs_0 <= update_idx;
if (_GEN_11) begin
end
else
wrbypass_idxs_1 <= update_idx;
if (_GEN_9) begin
if (wrbypass_hit) begin
if (wrbypass_hits_0) begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
end
else if (wrbypass_enq_idx) begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
end
end
hi_us_0 hi_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[17:11] : _GEN_1),
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),
.W0_mask (_GEN_2 ? 4'hF : _GEN_3)
);
lo_us_0 lo_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[17:11] : _GEN_1),
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),
.W0_mask (_GEN_4 ? 4'hF : _GEN_3)
);
table_0_0 table_0 (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx),
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),
.W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})
);
assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;
assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;
assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;
assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Fetch Target Queue (FTQ)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Each entry in the FTQ holds the fetch address and branch prediction snapshot state.
//
// TODO:
// * reduce port counts.
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util.{Str}
import boom.v3.common._
import boom.v3.exu._
import boom.v3.util._
/**
* FTQ Parameters used in configurations
*
* @param nEntries # of entries in the FTQ
*/
case class FtqParameters(
nEntries: Int = 16
)
/**
* Bundle to add to the FTQ RAM and to be used as the pass in IO
*/
class FTQBundle(implicit p: Parameters) extends BoomBundle
with HasBoomFrontendParameters
{
// // TODO compress out high-order bits
// val fetch_pc = UInt(vaddrBitsExtended.W)
// IDX of instruction that was predicted taken, if any
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
// Was the CFI in this bundle found to be taken? or not
val cfi_taken = Bool()
// Was this CFI mispredicted by the branch prediction pipeline?
val cfi_mispredicted = Bool()
// What type of CFI was taken out of this bundle
val cfi_type = UInt(CFI_SZ.W)
// mask of branches which were visible in this fetch bundle
val br_mask = UInt(fetchWidth.W)
// This CFI is likely a CALL
val cfi_is_call = Bool()
// This CFI is likely a RET
val cfi_is_ret = Bool()
// Is the NPC after the CFI +4 or +2
val cfi_npc_plus4 = Bool()
// What was the top of the RAS that this bundle saw?
val ras_top = UInt(vaddrBitsExtended.W)
val ras_idx = UInt(log2Ceil(nRasEntries).W)
// Which bank did this start from?
val start_bank = UInt(1.W)
// // Metadata for the branch predictor
// val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))
}
/**
* IO to provide a port for a FunctionalUnit to get the PC of an instruction.
* And for JALRs, the PC of the next instruction.
*/
class GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = Input(UInt(log2Ceil(ftqSz).W))
val entry = Output(new FTQBundle)
val ghist = Output(new GlobalHistory)
val pc = Output(UInt(vaddrBitsExtended.W))
val com_pc = Output(UInt(vaddrBitsExtended.W))
// the next_pc may not be valid (stalled or still being fetched)
val next_val = Output(Bool())
val next_pc = Output(UInt(vaddrBitsExtended.W))
}
/**
* Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the
* processor.
*
* @param num_entries # of entries in the FTQ
*/
class FetchTargetQueue(implicit p: Parameters) extends BoomModule
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val num_entries = ftqSz
private val idx_sz = log2Ceil(num_entries)
val io = IO(new BoomBundle {
// Enqueue one entry for every fetch cycle.
val enq = Flipped(Decoupled(new FetchBundle()))
// Pass to FetchBuffer (newly fetched instructions).
val enq_idx = Output(UInt(idx_sz.W))
// ROB tells us the youngest committed ftq_idx to remove from FTQ.
val deq = Flipped(Valid(UInt(idx_sz.W)))
// Give PC info to BranchUnit.
val get_ftq_pc = Vec(2, new GetPCFromFtqIO())
// Used to regenerate PC for trace port stuff in FireSim
// Don't tape this out, this blows up the FTQ
val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))
val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W)))
val redirect = Input(Valid(UInt(idx_sz.W)))
val brupdate = Input(new BrUpdateInfo)
val bpdupdate = Output(Valid(new BranchPredictionUpdate))
val ras_update = Output(Bool())
val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W))
val ras_update_pc = Output(UInt(vaddrBitsExtended.W))
})
val bpd_ptr = RegInit(0.U(idx_sz.W))
val deq_ptr = RegInit(0.U(idx_sz.W))
val enq_ptr = RegInit(1.U(idx_sz.W))
val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) ||
(WrapInc(enq_ptr, num_entries) === bpd_ptr))
val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W)))
val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W)))
val ram = Reg(Vec(num_entries, new FTQBundle))
val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) }
val lhist = if (useLHist) {
Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W))))
} else {
None
}
val do_enq = io.enq.fire
// This register lets us initialize the ghist to 0
val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory))
val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle))
val prev_pc = RegInit(0.U(vaddrBitsExtended.W))
when (do_enq) {
pcs(enq_ptr) := io.enq.bits.pc
val new_entry = Wire(new FTQBundle)
new_entry.cfi_idx := io.enq.bits.cfi_idx
// Initially, if we see a CFI, it is assumed to be taken.
// Branch resolutions may change this
new_entry.cfi_taken := io.enq.bits.cfi_idx.valid
new_entry.cfi_mispredicted := false.B
new_entry.cfi_type := io.enq.bits.cfi_type
new_entry.cfi_is_call := io.enq.bits.cfi_is_call
new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret
new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4
new_entry.ras_top := io.enq.bits.ras_top
new_entry.ras_idx := io.enq.bits.ghist.ras_idx
new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask
new_entry.start_bank := bank(io.enq.bits.pc)
val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken,
io.enq.bits.ghist,
prev_ghist.update(
prev_entry.br_mask,
prev_entry.cfi_taken,
prev_entry.br_mask(prev_entry.cfi_idx.bits),
prev_entry.cfi_idx.bits,
prev_entry.cfi_idx.valid,
prev_pc,
prev_entry.cfi_is_call,
prev_entry.cfi_is_ret
)
)
lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist))
ghist.map( g => g.write(enq_ptr, new_ghist))
meta.write(enq_ptr, io.enq.bits.bpd_meta)
ram(enq_ptr) := new_entry
prev_pc := io.enq.bits.pc
prev_entry := new_entry
prev_ghist := new_ghist
enq_ptr := WrapInc(enq_ptr, num_entries)
}
io.enq_idx := enq_ptr
io.bpdupdate.valid := false.B
io.bpdupdate.bits := DontCare
when (io.deq.valid) {
deq_ptr := io.deq.bits
}
// This register avoids a spurious bpd update on the first fetch packet
val first_empty = RegInit(true.B)
// We can update the branch predictors when we know the target of the
// CFI in this fetch bundle
val ras_update = WireInit(false.B)
val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W))
val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W))
io.ras_update := RegNext(ras_update)
io.ras_update_pc := RegNext(ras_update_pc)
io.ras_update_idx := RegNext(ras_update_idx)
val bpd_update_mispredict = RegInit(false.B)
val bpd_update_repair = RegInit(false.B)
val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W))
val bpd_idx = Mux(io.redirect.valid, io.redirect.bits,
Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr))
val bpd_entry = RegNext(ram(bpd_idx))
val bpd_ghist = ghist(0).read(bpd_idx, true.B)
val bpd_lhist = if (useLHist) {
lhist.get.read(bpd_idx, true.B)
} else {
VecInit(Seq.fill(nBanks) { 0.U })
}
val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs
val bpd_pc = RegNext(pcs(bpd_idx))
val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries)))
when (io.redirect.valid) {
bpd_update_mispredict := false.B
bpd_update_repair := false.B
} .elsewhen (RegNext(io.brupdate.b2.mispredict)) {
bpd_update_mispredict := true.B
bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx)
bpd_end_idx := RegNext(enq_ptr)
} .elsewhen (bpd_update_mispredict) {
bpd_update_mispredict := false.B
bpd_update_repair := true.B
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {
bpd_repair_pc := bpd_pc
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair) {
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||
bpd_pc === bpd_repair_pc) {
bpd_update_repair := false.B
}
}
val do_commit_update = (!bpd_update_mispredict &&
!bpd_update_repair &&
bpd_ptr =/= deq_ptr &&
enq_ptr =/= WrapInc(bpd_ptr, num_entries) &&
!io.brupdate.b2.mispredict &&
!io.redirect.valid && !RegNext(io.redirect.valid))
val do_mispredict_update = bpd_update_mispredict
val do_repair_update = bpd_update_repair
when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) {
val cfi_idx = bpd_entry.cfi_idx.bits
val valid_repair = bpd_pc =/= bpd_repair_pc
io.bpdupdate.valid := (!first_empty &&
(bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) &&
!(RegNext(do_repair_update) && !valid_repair))
io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update)
io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update)
io.bpdupdate.bits.pc := bpd_pc
io.bpdupdate.bits.btb_mispredicts := 0.U
io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid,
MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask)
io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx
io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted
io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken
io.bpdupdate.bits.target := bpd_target
io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx)
io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR
io.bpdupdate.bits.ghist := bpd_ghist
io.bpdupdate.bits.lhist := bpd_lhist
io.bpdupdate.bits.meta := bpd_meta
first_empty := false.B
}
when (do_commit_update) {
bpd_ptr := WrapInc(bpd_ptr, num_entries)
}
io.enq.ready := RegNext(!full || do_commit_update)
val redirect_idx = io.redirect.bits
val redirect_entry = ram(redirect_idx)
val redirect_new_entry = WireInit(redirect_entry)
when (io.redirect.valid) {
enq_ptr := WrapInc(io.redirect.bits, num_entries)
when (io.brupdate.b2.mispredict) {
val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^
Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
redirect_new_entry.cfi_idx.valid := true.B
redirect_new_entry.cfi_idx.bits := new_cfi_idx
redirect_new_entry.cfi_mispredicted := true.B
redirect_new_entry.cfi_taken := io.brupdate.b2.taken
redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx
redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx
}
ras_update := true.B
ras_update_pc := redirect_entry.ras_top
ras_update_idx := redirect_entry.ras_idx
} .elsewhen (RegNext(io.redirect.valid)) {
prev_entry := RegNext(redirect_new_entry)
prev_ghist := bpd_ghist
prev_pc := bpd_pc
ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)
}
//-------------------------------------------------------------
// **** Core Read PCs ****
//-------------------------------------------------------------
for (i <- 0 until 2) {
val idx = io.get_ftq_pc(i).ftq_idx
val next_idx = WrapInc(idx, num_entries)
val next_is_enq = (next_idx === enq_ptr) && io.enq.fire
val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))
val get_entry = ram(idx)
val next_entry = ram(next_idx)
io.get_ftq_pc(i).entry := RegNext(get_entry)
if (i == 1)
io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B)
else
io.get_ftq_pc(i).ghist := DontCare
io.get_ftq_pc(i).pc := RegNext(pcs(idx))
io.get_ftq_pc(i).next_pc := RegNext(next_pc)
io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq)
io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))
}
for (w <- 0 until coreWidth) {
io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w)))
}
} | module ghist_1(
input [3:0] R0_addr,
input R0_clk,
output [71:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [71:0] W0_data
);
ghist_0_ext ghist_0_ext (
.R0_addr (R0_addr),
.R0_en (1'h1),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
import freechips.rocketchip.util._
import ALU._
class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
val fn = Bits(SZ_ALU_FN.W)
val dw = Bits(SZ_DW.W)
val in1 = Bits(dataBits.W)
val in2 = Bits(dataBits.W)
val tag = UInt(tagBits.W)
}
class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {
val data = Bits(dataBits.W)
val full_data = Bits((2*dataBits).W)
val tag = UInt(tagBits.W)
}
class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {
val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))
val kill = Input(Bool())
val resp = Decoupled(new MultiplierResp(dataBits, tagBits))
}
case class MulDivParams(
mulUnroll: Int = 1,
divUnroll: Int = 1,
mulEarlyOut: Boolean = false,
divEarlyOut: Boolean = false,
divEarlyOutGranularity: Int = 1
)
class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)
private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)
def minLatency: Int = (minDivLatency ++ minMulLatency).min
val io = IO(new MultiplierIO(width, log2Up(nXpr)))
val w = io.req.bits.in1.getWidth
val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll
val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0
val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8)
val state = RegInit(s_ready)
val req = Reg(chiselTypeOf(io.req.bits))
val count = Reg(UInt(log2Ceil(
((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++
(cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W))
val neg_out = Reg(Bool())
val isHi = Reg(Bool())
val resHi = Reg(Bool())
val divisor = Reg(Bits((w+1).W)) // div only needs w bits
val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits
val mulDecode = List(
FN_MUL -> List(Y, N, X, X),
FN_MULH -> List(Y, Y, Y, Y),
FN_MULHU -> List(Y, Y, N, N),
FN_MULHSU -> List(Y, Y, Y, N))
val divDecode = List(
FN_DIV -> List(N, N, Y, Y),
FN_REM -> List(N, Y, Y, Y),
FN_DIVU -> List(N, N, N, N),
FN_REMU -> List(N, Y, N, N))
val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(io.req.bits.fn, List(X, X, X, X),
(if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)
require(w == 32 || w == 64)
def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32
def sext(x: Bits, halfW: Bool, signed: Bool) = {
val sign = signed && Mux(halfW, x(w/2-1), x(w-1))
val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))
(Cat(hi, x(w/2-1,0)), sign)
}
val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)
val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)
val subtractor = remainder(2*w,w) - divisor
val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0))
val negated_remainder = -result
if (cfg.divUnroll != 0) when (state === s_neg_inputs) {
when (remainder(w-1)) {
remainder := negated_remainder
}
when (divisor(w-1)) {
divisor := subtractor
}
state := s_div
}
if (cfg.divUnroll != 0) when (state === s_neg_output) {
remainder := negated_remainder
state := s_done_div
resHi := false.B
}
if (cfg.mulUnroll != 0) when (state === s_mul) {
val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
val mplierSign = remainder(w)
val mplier = mulReg(mulw-1,0)
val accum = mulReg(2*mulw,mulw).asSInt
val mpcand = divisor.asSInt
val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum
val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll))
val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out
val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0)
val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U &&
!isHi && (mplier & ~eOutMask) === 0.U
val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))
val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0))
count := count + 1.U
when (eOut || count === (mulw/cfg.mulUnroll-1).U) {
state := s_done_mul
resHi := isHi
}
}
if (cfg.divUnroll != 0) when (state === s_div) {
val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) =>
// the special case for iteration 0 is to save HW, not for correctness
val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0)
val less = difference(w)
Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less)
}.tail
remainder := unrolls.last
when (count === (w/cfg.divUnroll).U) {
state := Mux(neg_out, s_neg_output, s_done_div)
resHi := isHi
if (w % cfg.divUnroll < cfg.divUnroll - 1)
remainder := unrolls(w % cfg.divUnroll)
}
count := count + 1.U
val divby0 = count === 0.U && !subtractor(w)
if (cfg.divEarlyOut) {
val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity)
val alignMask = ~((align-1).U(log2Ceil(w).W))
val divisorMSB = Log2(divisor(w-1,0), w) & alignMask
val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask
val eOutPos = ~(dividendMSB - divisorMSB)
val eOut = count === 0.U && !divby0 && eOutPos >= align.U
when (eOut) {
remainder := remainder(w-1,0) << eOutPos
count := eOutPos >> log2Floor(cfg.divUnroll)
}
}
when (divby0 && !isHi) { neg_out := false.B }
}
when (io.resp.fire || io.kill) {
state := s_ready
}
when (io.req.fire) {
state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))
isHi := cmdHi
resHi := false.B
count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U)
neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)
divisor := Cat(rhs_sign, rhs_in)
remainder := lhs_in
req := io.req.bits
}
val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div)
val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0))
val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2))
io.resp.bits.tag := req.tag
io.resp.bits.data := Cat(hiOut, loOut)
io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0))
io.resp.valid := (state === s_done_mul || state === s_done_div)
io.req.ready := state === s_ready
}
class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {
val io = IO(new Bundle {
val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))
val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))
})
val in = Pipe(io.req)
val decode = List(
FN_MUL -> List(N, X, X),
FN_MULH -> List(Y, Y, Y),
FN_MULHU -> List(Y, N, N),
FN_MULHSU -> List(Y, Y, N))
val cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)
val cmdHalf = (width > 32).B && in.bits.dw === DW_32
val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt
val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt
val prod = lhs * rhs
val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0)))
val resp = Pipe(in, latency-1)
io.resp.valid := resp.valid
io.resp.bits.tag := resp.bits.tag
io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits
io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt
} | module PipelinedMultiplier(
input clock,
input reset,
input io_req_valid,
input [4:0] io_req_bits_fn,
input io_req_bits_dw,
input [63:0] io_req_bits_in1,
input [63:0] io_req_bits_in2,
output [63:0] io_resp_bits_data
);
reg in_pipe_v;
reg [4:0] in_pipe_b_fn;
reg in_pipe_b_dw;
reg [63:0] in_pipe_b_in1;
reg [63:0] in_pipe_b_in2;
reg io_resp_bits_data_pipe_v;
reg [63:0] io_resp_bits_data_pipe_b;
reg [63:0] io_resp_bits_data_pipe_pipe_b;
wire [1:0] decoded_invInputs = ~(in_pipe_b_fn[1:0]);
wire [127:0] prod = {{64{(|{decoded_invInputs[1], &{decoded_invInputs[0], in_pipe_b_fn[1]}}) & in_pipe_b_in1[63]}}, in_pipe_b_in1} * {{64{decoded_invInputs[1] & in_pipe_b_in2[63]}}, in_pipe_b_in2};
always @(posedge clock) begin
if (reset) begin
in_pipe_v <= 1'h0;
io_resp_bits_data_pipe_v <= 1'h0;
end
else begin
in_pipe_v <= io_req_valid;
io_resp_bits_data_pipe_v <= in_pipe_v;
end
if (io_req_valid) begin
in_pipe_b_fn <= io_req_bits_fn;
in_pipe_b_dw <= io_req_bits_dw;
in_pipe_b_in1 <= io_req_bits_in1;
in_pipe_b_in2 <= io_req_bits_in2;
end
if (in_pipe_v)
io_resp_bits_data_pipe_b <= (|{in_pipe_b_fn[0], in_pipe_b_fn[1]}) ? prod[127:64] : in_pipe_b_dw ? prod[63:0] : {{32{prod[31]}}, prod[31:0]};
if (io_resp_bits_data_pipe_v)
io_resp_bits_data_pipe_pipe_b <= io_resp_bits_data_pipe_b;
end
assign io_resp_bits_data = io_resp_bits_data_pipe_pipe_b;
endmodule |
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